TPS650941A0RSKT [TI]
适用于 Apollo Lake 处理器的可编程中等输入电压范围电源管理 IC (PMIC) | RSK | 64 | -40 to 85;
| 型号： | TPS650941A0RSKT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 Apollo Lake 处理器的可编程中等输入电压范围电源管理 IC (PMIC) | RSK | 64 | -40 to 85 集成电源管理电路 |
| 文件： | 总96页 (文件大小：1631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65094
ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
适用于 Intel™ Apollo Lake 平台的 TPS65094 PMIC
1 器件概述
1.1 特性
1
(V1P24A)，输出电流为 2A
• 5.6V 至 21V 的宽输入电压范围
• 三个具有可调输出电压的 LDO 稳压器
• 三个可变输出电压同步
降压控制器 D-CAP2™拓扑
– LDOA1：I2C 可选输出电压为 1.35V 至 3.3V，输
出电流高达 200mA
– 对于 BUCK1 (VNN)，电流为 5A；对于 BUCK6
(VDDQ)，电流为 7A，对于典型应用中使用外部
FET 的 BUCK2 (VCCGI)，电流为 21A
– LDOA2 和 LDOA3：I2C 可选输出电压为 0.7V 至
1.5V，输出电流高达 600mA
– 针对 BUCK1 和 BUCK2
– 对于 BUCK6 (VDDQ)，提供 OTP 可编程默认输
出电压
• 适用于 DDR 存储器终端的 VTT LDO
• 三个具有压摆率控制功能的负载开关
– 输出电流高达 400mA，压降小于标称输入电压的
• 三个可变输出电压同步
1.5%
降压转换器，采用 DCS-Control 拓扑技术并支持
– 输入电压为 1.8V 时，RDSON < 96mΩ
• I2C 接口（器件地址 0x5E）支持：
– 标准模式 (100kHz)
I2C DVS 功能
– 输入电压范围为 4.5V 至 5.5V
– 对于 BUCK3 (VCCRAM)，输出电流为 3A
– 对于典型应用中的 BUCK4 (V1P8A) 和 BUCK5
– 快速模式 (400kHz)
– 快速模式+ (1MHz)
1.2 应用
•
2 节、3 节或 4 节锂离子电池供电产品（NVDC 或
非 NVDC）
•
•
平板电脑、 超极本™和笔记本电脑
移动 PC 和移动互联网设备
•
壁式供电设计，特别是 12V 电源
1.3 说明
TPS65094 器件是一款单芯片解决方案电源管理集成芯片 (PMIC)，专为最新的 Intel™处理器进行设计，这
些处理器以通过 2 节、3 节或 4 节锂离子电池组（NVDC 或非 NVDC 电源架构）供电的平板电脑、超极
本、笔记本、工业计算机和物联网 (IOT) 应用 以及壁式供电的 应用为目标。
TPS65094 器件用于合并低电压轨的必需系统，以获得最小的尺寸和成本最低的系统电源解决方案。
TPS65094 器件可提供基于 Intel 参考设计的完整电源解决方案。由上电序列逻辑控制六个高效降压稳压器
(VR)、一个灌/拉 LDO (VTT)、以及一个负载开关，以提供正确的电源轨、定序和保护 — 包括 DDR3 和
DDR4 存储器电源。两个稳压器（BUCK1 和 BUCK2）支持动态电压调节 (DVS)，可最大限度地提高效率
（包括支持联网待机功能）。高频 VR 采用小型电感和电容来减小解决方案体积。凭借 I2C 接口，可通过嵌
入式控制器 (EC) 或片上系统 (SoC) 轻松实现控制功能。
PMIC 采用带散热焊盘的 8mm × 8mm 单行 VQFN 封装，因此散热性能良好，电路板布线简单。
器件信息(1)
封装
器件型号
封装尺寸（标称值）
TPS65094
VQFN (64)
8.00mm x 8.00mm
(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SWCS133
TPS65094
ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
www.ti.com.cn
1.4 功能方框图
Optional(a)
Required(b)
LDO5V
VSYS
BOOT1
DRVH1
EC
LDOA1
1.35 V to 3.3 V
1.8 V(b)
PMICEN
SLP_S3B
SLP_S4B
BUCK1
Default: 1V
SW1
200 mA
VNN
VSET
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
DRVL1
EN
EN
SLP_S0B
Control
FBVOUT1
LDOLS_EN(a)
Inputs
PGNDSNS1
SWA1_EN(b)
5 A
ILIM1
THERMTRIPB
V1P8A
VSYS
BOOT2
DRVH2
CLK
I2C CTRL
BUCK2
Default: 0V
SW2
SoC
DATA
VCCGI
VSET
EN
V1P8A
DRVL2
Typical
Application
Usage:
Control
Outputs
FBVOUT2
0.5 V to 1.45 V
(DVS)
PGNDSNS2
IRQB
21 A
PCH_PWROK
RSMRSTB
PROCHOT
GPO
FBGND2
ILIM2
Internal
Interrupt
Events
BUCK5V
PVIN3
LX3
TEST CTRL
OTP
VSET
EN
BUCK3
Default: 1.05 V
3 A
VCCRAM
FB3
REGISTERS
<PGND_BUCK3>
BUCK5V
BUCK5V
PVIN4
LX4
VSYS
VSYS
BUCK4
Default: 1.8 V
2 A
Digital Core
VSET
EN
V1P8A
V5ANA
LDO5
BUCK5V
FB4
<PGND_BUCK4>
LDO5V
nPUC
LDO3P3
VREF
REFSYS
PVIN5
LX5
VSET
EN
BUCK5
Default: 1.24 V
2 A
V1P24A
FB5
<PGND_BUCK5>
AGND
VSYS
Thermal
monitoring
BOOT6
DRVH6
Thermal shutdown
SW6
BUCK6
Default: OTP
Dependent
7 A
VDDQ
VSET
EN
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
PVINVTT
VTT
VTT_LDO
½ × VDDQ
ILIM set by OTP
VTT
EN
VTTFB
LDOA2
0.7 V to 1.5 V
600 mA
LDOA3
0.7 V to 1.5 V
600 mA
LOAD SWA1
300 mA
LOAD SWB1
400 mA
LOAD SWB2
400 mA
V1P8A(1)
0.5 V to 3.3 V(2)
0.5 V to 3.3 V
Dashed connections optional.
Refer to Pin Attributes for
connection if unused.
(1) LPDDR3 and LPDDR4
(2) DDR3L
(a) LDOA1 Not —Always On“
(b) LDOA1 —Always On“
Copyright © 2016, Texas Instruments Incorporated
图 1-1. PMIC 功能框图
2
器件概述
版权 © 2015–2019, Texas Instruments Incorporated
TPS65094
www.ti.com.cn
ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
内容
1
器件概述.................................................... 1
5.15 Switching Characteristics ........................... 26
5.16 Typical Characteristics .............................. 27
Detailed Description ................................... 28
6.1 Overview ............................................ 28
6.2 Functional Block Diagram........................... 29
6.3 Feature Description ................................. 31
6.4 Device Functional Modes ........................... 48
6.5 Programming ........................................ 48
6.6 Register Maps....................................... 52
Application and Implementation .................... 71
7.1 Application Information.............................. 71
7.2 Typical Application .................................. 71
7.3 Specific Application for TPS650944 ................ 80
7.4 Do's and Don'ts ..................................... 81
Power Supply Recommendations .................. 81
Layout .................................................... 82
9.1 Layout Guidelines ................................... 82
9.2 Layout Example ..................................... 82
1.1 特性 ................................................... 1
1.2 应用 ................................................... 1
1.3 说明 ................................................... 1
1.4 功能方框图............................................ 2
修订历史记录............................................... 3
Device Options ........................................... 5
3.1 OTP Comparison ..................................... 5
Pin Configuration and Functions..................... 6
Specifications ........................................... 10
5.1 Absolute Maximum Ratings......................... 10
5.2 ESD Ratings ........................................ 10
5.3 Recommended Operating Conditions............... 11
5.4 Thermal Information................................. 11
6
2
3
4
5
7
5.5
Electrical Characteristics: Total Current
8
9
Consumption ........................................ 11
Electrical Characteristics: Reference and Monitoring
System .............................................. 12
5.6
5.7
5.8
Electrical Characteristics: Buck Controllers......... 13
10 器件和文档支持 .......................................... 83
10.1 器件支持 ............................................ 83
10.2 文档支持............................................. 83
10.3 接收文档更新通知 ................................... 83
10.4 社区资源............................................. 83
10.5 商标.................................................. 83
10.6 静电放电警告 ........................................ 83
10.7 Glossary ............................................. 83
11 机械、封装和可订购信息 ............................... 83
11.1 Package Option Addendum ......................... 84
Electrical Characteristics: Synchronous Buck
Converters........................................... 17
5.9 Electrical Characteristics: LDOs .................... 20
5.10 Electrical Characteristics: Load Switches........... 24
5.11 Digital Signals: I2C Interface ........................ 25
5.12 Digital Input Signals (LDOLS_EN, SWA1_EN,
THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B,
SLP_S0B) ........................................... 25
5.13 Digital Output Signals (IRQB, RSMRSTB,
PCH_PWROK, PROCHOT)......................... 25
5.14 Timing Requirements ............................... 25
2 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (February 2017) to Revision C
Page
•
•
•
•
•
已更改 在标题中将 TPS65094x 更改为 TPS65094............................................................................... 1
已删除 删除了每页顶部的型号 ...................................................................................................... 1
Added "BUCK3-5 Mode" row and "TPS650945" column to Summary of TPS65094x OTP Differences table ........... 5
Changed the description of the VTTFB pin in the Pin Functions table ........................................................ 8
Changed VSYS to PVIN in the efficiency graphs for BUCK3, BUCK4, and BUCK5 in the Typical Characteristics
section ................................................................................................................................ 27
Added to the description of the deassertion condition that causes an emergency shutdown in the Emergency
Shutdown section ................................................................................................................... 47
Added TPS650945 settings to Section 6.6 ...................................................................................... 52
Changed OCP event to power fault event in the OCP bit description in the OFFONSRC Register Field
•
•
•
Descriptions table ................................................................................................................... 54
Changed second reference of TPS650940 to TPS650944 for the bit reset values in the LDOA2VID Register
Field Descriptions and LDOA3VID Register Field Descriptions tables....................................................... 61
Changed the bit values of the LDOA3_SLPVID[0] and LDOA3_VID[0] bits in the LDOA3VID Register figure......... 61
•
•
版权 © 2015–2019, Texas Instruments Incorporated
修订历史记录
3
TPS65094
ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
www.ti.com.cn
Changes from Revision A (June 2016) to Revision B
Page
•
•
•
•
•
Updated the PROCHOT pin description in the Pin Functions table............................................................ 9
Changed the values for LX3, LX4, LX5 from –1 V and 7 V to –2 V and 8 V in the Absolute Maximum Ratings table 10
Changed the reset value of the LDOA2 VID register (LDOA2VID) to OTP dependent.................................... 61
已添加 接收文档更新通知 部分 .................................................................................................... 83
已更改 静电放电注意事项 声明 .................................................................................................... 83
Changes from September 11, 2015 to June 2, 2016 (from * Revision (September 2015) to A Revision)
Page
•
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•
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•
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•
•
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•
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•
•
将完整版产品说明书发布为 SWCS133A 版本（以前为 SWCS130B 版本）.................................................. 1
已更改 将器件状态更改为 PROD_DATA .......................................................................................... 1
已更改 更改了建议最低输入电压.................................................................................................... 1
已更改 特性 完善 转换器的 说明 .................................................................................................... 1
已更改 特性 达到 400mA 的负载开关输出电流 ................................................................................... 1
已更改 功能框图以包含 TPS65094x 系列 ......................................................................................... 2
已更改 更改了 功能框图以在 PROCHOT 引脚上包含一个逆变器 .............................................................. 2
Changed PROCHOTB to PROCHOT throughout the document ............................................................... 6
Changed minimum absolute-maximum-rating value for SW1, SW2, and SW6 in Section 5.1............................ 10
Changed VSYS in Section 5.3, Recommended Operating Conditions ...................................................... 11
Deleted nominal value from PVINVTT in Section 5.3, Recommended Operating Conditions ........................... 11
Deleted (nu = symbol for efficiency) ............................................................................................. 13
Changed BUCK1 DC output voltage step size to show full range and be consistent in Section 5.7 .................... 13
Changed typo to match correct default of 1 V for ΔVOUT_TR in Section 5.7 ................................................. 13
Changed BUCK2 DC output voltage to show full range and be consistent in Section 5.7 ................................ 14
Changed set condition for BUCK6 for VOUT range in Section 5.7 to match BUCK1 and BUCK2 ........................ 15
Updated formatting and added new OTP information for BUCK6 in Section 5.7........................................... 15
Updated formatting for BUCK3 DC output voltage in Section 5.8 ............................................................ 17
Changed DC output voltage formatting for BUCK4 in Section 5.8 ........................................................... 18
Changed maximum IOUT value for BUCK4 in Section 5.8 to match device capabilities ................................... 18
Changed IOUT and ΔVOUT/ΔIOUT for VTT LDO in Section 5.9 for new OTPs ................................................. 23
Changed test conditions for VTT LDO overcurrent protection in Section 5.9 ............................................... 23
Changed Section 5.10 to show SWB1_2 RDSON is specified per output .................................................... 24
Changed fSW values in Section 5.15 to provide more values ................................................................. 26
Changed current to 1.9 A to match SoC requirements in Table 6-1 ......................................................... 28
Changed BUCK6, LDOA2, LDOA3 typical output voltage range to: OTP Dependent in Table 6-1...................... 28
Changed table note to include additional DDR types in Table 6-1 ........................................................... 28
Changed PMIC Functional Block Diagram to match specifications table ................................................... 30
Changed PROCHOTB to PROCHOT in the Apollo Lake Power Map ....................................................... 30
Changed current ratings in Apollo Lake Power Map ........................................................................... 30
Deleted SWBx PG from PG of PCH_PWROK in Table 6-2 ................................................................... 31
Changed BUCK1–2 to all BUCKs and LDOAs in Section 6.3.3.3 ............................................................ 36
Added Table 6-5 and Table 6-6 to Section 6.3.4.2 ............................................................................. 38
Added more DDR values to the table note in Table 6-7 ....................................................................... 39
Changed Section 6.3.5 to include LDOA1 and reset information............................................................. 40
Changed Section 6.6 to include multiple DDRs ................................................................................. 40
Changed Figure 6-7 and Figure 6-8 to include alternate SWB1_2 Timing .................................................. 42
Changed SWB1_2 from: V3P3A to: V1P8U in Table 6-10 .................................................................... 42
Changed VDDQ voltage to OTP Dependent and SWBx to SWB1_2 in Table 6-11 ....................................... 44
Updated Figure 6-10 to include alternate SWB1_2 Timing.................................................................... 45
Changed Section 6.3.5.5 to include alternate SWB1_2 Timing............................................................... 46
Changed Section 6.3.5.6 to include THERMTRIPB ........................................................................... 47
Added the TPS65094x family OTP values to Section 6.6 ..................................................................... 52
Replaced VID values with link to full VID table in Table 6-18 and Table 6-19 .............................................. 55
Updated naming of bits in the TEMPHOT register.............................................................................. 70
4
修订历史记录
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
www.ti.com.cn
ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
3 Device Options
3.1 OTP Comparison
Table 3-1 summarizes the differences between the various TPS65094x family OTPs.
Table 3-1. Summary of TPS65094x OTP Differences
TPS650940
LPDDR4
1.1 V
TPS650941
LPDDR3
1.2 V
TPS650942
DDR3L
1.35 V
No
TPS650944
LPDDR4
1.1 V
TPS650945
LPDDR4
1.1 V
DDR
BUCK6 Voltage
VTT Disabled
VTT IOCP (minimum)
Yes
No
Yes
Yes
0.95 A
0.95 A
1.8 A
1.8 A
0.95 A
SWB1_2 controlled by SLP_S4B
(V1P8U)
Yes
Yes
No
Yes
Yes
SWB1_2 controlled by SLP_S3B
Pin 14 Usage
No
LDOLS_EN
No
No
LDOLS_EN
No
Yes
LDOLS_EN
No
No
SWA1_EN
Yes
No
LDOLS_EN
No
LDOA1 Always On
LDOA1 Default Voltage
LDOA2 Default Voltage
LDOA3 Default Voltage
PMICEN Low Forces Reset
DEVICEID Register
3.3 V
1.2 V
1.25 V
Yes
3.3 V
1.2 V
1.25 V
Yes
3.3 V
1.2 V
1.25 V
Yes
1.8 V
0.7 V
0.7 V
No
3.3 V
1.2 V
1.25 V
Yes
8h
29h
1Ah
0Bh
8h
BUCK3-5 Mode
Auto
Auto
Auto
Auto
Forced PWM
Copyright © 2015–2019, Texas Instruments Incorporated
Device Options
5
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Product Folder Links: TPS65094
TPS65094
ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
www.ti.com.cn
4 Pin Configuration and Functions
RSK Package
64-Pin VQFN With Thermal Pad
Top View
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
FBGND2
FBVOUT2
DRVH2
1
2
3
4
5
6
7
8
9
48 VTTFB
47 VTT
46 PVINVTT
45 ILIM6
SW2
BOOT2
44 FBVOUT6
43 DRVH6
42 SW6
PGNDSNS2
DRVL2
DRV5V_2_A1
LDOA1
41 BOOT6
40 PGNDSNS6
39 DRVL6
38 DRV5V_1_6
37 DRVL1
36 PGNDSNS1
35 BOOT1
34 SW1
TOP VIEW
PGND/Thermal Pad
LX3 10
PVIN3 11
FB3 12
PMICEN 13
LDOLS_EN or
SWA1_EN
14
IRQB 15
RSMRSTB 16
33 DRVH1
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NOTE: The thermal pad must be connected to the system power ground plane.
6
Pin Configuration and Functions
Copyright © 2015–2019, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TPS65094
TPS65094
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ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
Pin Functions
PIN
NAME
SMPS REGULATORS
SUPPLY, OP
VOLTAGE
LEVEL
I/O
DESCRIPTION
NO.
Remote negative feedback sense for BUCK2 controller. Connect to VCCGI VSS
SENSE sent from the SoC to the PMIC.
1
2
FBGND2
I
I
Remote positive feedback sense for BUCK2 controller. Connect to VCCGI VCC
SENSE sent from the SoC to the PMIC.
FBVOUT2
3
4
DRVH2
SW2
O
I
VSYS + 5 V High-side gate driver output for BUCK2 controller
Switch node connection for BUCK2 controller
Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between
this pin and SW2 pin.
5
BOOT2
I
VSYS + 5 V
Power GND connection for BUCK2. Connect to ground terminal of external low-
side FET.
6
7
8
PGNDSNS2
DRVL2
I
O
I
5 V
5 V
Low-side gate driver output for BUCK2 controller
5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF
(typical) ceramic capacitor. Shorted on board to LDO5P0 pin.
DRV5V_2_A1
Switch node connection for BUCK3 converter. Connect to a 0.47-µH (typical)
inductor with less than 50-mΩ DCR.
10
11
12
20
21
22
23
24
25
29
30
LX3
PVIN3
FB3
O
I
Power input to BUCK3 converter. Bypass to ground with a 10-µF (typical) ceramic
capacitor.
5 V
5 V
5 V
Remote feedback sense for BUCK3 converter. Connect to positive terminal of
output capacitor.
I
Switch node connection for BUCK5 converter. Connect to a 0.47-µH (typical)
inductor with less than 50-mΩ DCR.
LX5
O
I
Power input to BUCK5 converter. Bypass to ground with a 10-µF (typical) ceramic
capacitor.
PVIN5
FB5
Remote feedback sense for BUCK5 converter. Connect to positive terminal of
output capacitor.
I
Remote feedback sense for BUCK4 converter. Connect to positive terminal of
output capacitor.
FB4
I
Power input to BUCK4 converter. Bypass to ground with a 10-µF (typical) ceramic
capacitor.
PVIN4
LX4
I
Switch node connection for BUCK4 converter. Connect to a 0.47-µH (typical)
inductor with less than 50-mΩ DCR.
O
I
Remote feedback sense for BUCK1 controller. Connect to VNN VCC SENSE sent
from the SoC to the PMIC.
FBVOUT1
ILIM1
Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to
set current limit of external low-side FET.
I
33
34
DRVH1
SW1
O
I
VSYS + 5 V High-side gate driver output for BUCK1 controller
Switch node connection for BUCK1 controller
Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between
this pin and SW1 pin.
35
BOOT1
I
VSYS + 5 V
Power GND connection for BUCK1. Connect to ground terminal of external low-
side FET.
36
37
38
39
40
PGNDSNS1
DRVL1
I
O
I
5 V
5 V
5 V
Low-side gate driver output for BUCK1 controller
5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF
(typical) ceramic capacitor. Shorted on board to LDO5P0 pin.
DRV5V_1_6
DRVL6
O
I
Low-side gate driver output for BUCK6 controller
Power GND connection for BUCK6. Connect to ground terminal of external low-
side FET.
PGNDSNS6
Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between
this pin and SW6 pin.
41
BOOT6
I
VSYS + 5 V
42
43
SW6
I
Switch node connection for BUCK6 controller
DRVH6
O
VSYS + 5 V High-side gate driver output for BUCK6 controller
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Pin Functions (continued)
PIN
NAME
SUPPLY, OP
VOLTAGE
LEVEL
I/O
DESCRIPTION
NO.
Remote feedback sense for BUCK6 controller. Connect to positive terminal of
output capacitor.
44
FBVOUT6
ILIM6
I
I
I
Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to
set current limit of external low-side FET.
45
64
Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to
set current limit of external low-side FET.
ILIM2
LDO and LOAD SWITCHES
LDOA1 output. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave
floating when not in use.
9
LDOA1
O
O
1.35–3.3 V
0.5–3.3 V
(1.8-V
Typical)
Output of load switch B1. Bypass to ground with a 0.1-µF (typical) ceramic
capacitor. Short with SWB2.
17
SWB1
0.5–3.3 V
(1.8-V
Typical)
Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (typical)
ceramic capacitor to improve transient performance. Connect to ground when not
in use.
18
19
PVINSWB1_B2
SWB2
I
0.5–3.3 V
(1.8-V
Typical)
Output of load switch B2. Bypass to ground with a 0.1-µF (typical) ceramic
capacitor. Short with SWB1. Leave floating when not in use.
O
Output of load switch A1. Bypass to ground with a 0.1-µF (typical) ceramic
capacitor. Leave floating when not in use.
31
32
46
47
48
49
50
51
54
56
SWA1
PVINSWA1
PVINVTT
VTT
O
I
0.5–3.3 V
0.5–3.3 V
VDDQ
Power supply to load switch A1. Bypass to ground with a 1-µF (typical) ceramic
capacitor to improve transient performance. Connect to ground when not in use.
Power supply to VTT LDO. Bypass to ground with a 10-µF (minimum) ceramic
capacitor. Connect to ground when not in use.
I
Output of load VTT LDO. Bypass to ground with 2× 22-µF (minimum) ceramic
capacitors. Leave floating when not in use.
O
I
VDDQ / 2
VDDQ / 2
0.7–1.5 V
1.8 V
Remote feedback sense for VTT LDO. Connect to positive terminal of output
capacitor. Short to GND when not in use.
VTTFB
Output of LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
Leave floating when not in use.
LDOA3
O
I
Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (typical)
ceramic capacitor. Connect to ground when not in use.
PVINLDOA2_A3
LDOA2
Output of LDOA2. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
Leave floating when not in use.
O
O
O
0.7–1.5 V
3.3 V
Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (typical) ceramic
capacitor.
LDO3P3
LDO5P0
Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA.
Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
5 V
External 5-V supply input to internal load switch that connects this pin to LDO5P0
pin. Bypass this pin with an optional ceramic capacitor to improve transient
performance.
57
V5ANA
I
5 V
8
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Pin Functions (continued)
PIN
SUPPLY, OP
VOLTAGE
LEVEL
I/O
DESCRIPTION
NO.
NAME
INTERFACE
PMIC cold-boot pin. At assertion rising edge of the signal of this pin power state
transitions from G3 to S4/S5. Driving the pin to L shuts down all VRs.
13
14
PMICEN
I
I
Enable pin for LDOA2, LDOA3, and SWA1 when OTP is configured to
LDOLS_EN. Enable pin for just SWA1 when OTP is configured to SWA1_EN.
Resources turn on at assertion (H) and turn off at deassertion (L) of the pin.
Optionally, when the pin is pulled low, the host can write to enable bits in Reg
0xA0–Reg 0xA1 to control the rails.
LDOLS_EN or
SWA1_EN
Open-drain output interrupt pin. Refer to Section 6.6.3, IRQ: PMIC Interrupt
Register, for definitions.
15
16
IRQB
O
O
Open-drain output Always-ON-rail Power Good. It reflects a valid state whenever
VSYS is available.
RSMRSTB
Open-drain output controlled by an I2C register bit defined in Section 6.6.26,
GPO_CTRL: GPO Control Register, by the user, which then can be used as an
enable signal to an external VR.
26
27
28
GPO
O
O
O
Open-drain output global Power Good. It reflects a valid state whenever VSYS is
available.
PCH_PWROK
PROCHOT
Optional open-drain output for indicating PMIC thermal event. Invert before
connecting to SoC if used, otherwise leave floating. This pin is triggered when any
of the PMIC die temperature sensors detects the THOT temperature.
58
59
60
CLK
DATA
I
I/O
I
I2C clock
I2C data
THERMTRIPB
Thermal shutdown signal from SoC
Power state pin. PMIC goes into Connected Standby at falling edge and exits from
Connected Standby at rising edge.
61
62
63
SLP_S0B
SLP_S3B
SLP_S4B
I
I
I
Power state pin. PMIC goes into S3 at falling edge and exits from S3, transitions
into S0 at rising edge.
Power state pin. PMIC goes into S4 at falling edge and exits from S4, transitions
into S3 at rising edge.
REFERENCE
Band-gap reference output. Stabilize it by connecting a 100-nF (typical) ceramic
capacitor between this pin and quiet ground.
53
VREF
AGND
VSYS
O
—
I
1.25 V
Analog ground. Do not connect to the thermal pad ground on top layer. Connect to
ground of VREF capacitor.
52
System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to
ground with a 1-µF (typical) ceramic capacitor.
55
THERMAL PAD
Connect to PCB ground plane using multiple vias for good thermal and electrical
performance.
—
Thermal pad
—
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
ANALOG
VSYS
Input voltage from battery
–0.3
–0.3
–0.3
–0.3
–0.3
–5(2)
–2(3)
–0.3
28
7
V
V
V
V
V
V
V
V
PVIN3, PVIN4, PVIN5, LDO5P0, DRV5V_1_6, DRV5V_2_A1, DRVL1, DRVL2, DRVL6
V5ANA
6
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6
SW1, SW2, SW6
0.3
34
28
8
LX3, LX4, LX5
BOOTx to SWx
Differential voltage
5.5
VREF, LDO3P3, FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5, ILIM1, ILIM2, ILIM6, PVINVTT,
VTT, VTTFB, PVINSWA1, SWA1, PVINSWB1_B2, SWB1, SWB2, LDOA1
–0.3
–0.3
3.6
3.3
V
V
PVINLDOA2_A3, LDOA2, LDOA3
DIGITAL IOs
DATA, CLK, PCH_PWROK, RSMRSTB, GPO
–0.3
–0.3
–40
3.6
7
V
V
PMICEN, SLP_S4B, SLP_S3B, SLP_S0B, LDOLS_EN, SWA1_EN, THERMTRIPB, IRQB, PROCHOT
Storage temperature, Tstg
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Transient for less than 5 ns.
(3) Transient for less than 20 ns.
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS001(1)
Charged Device Model (CDM), per JESD22-C101(2)
Electrostatic
discharge
VESD
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
10
Specifications
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5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
13
MAX UNIT
ANALOG
VSYS
5.6
–0.3
–0.3
–0.3
–0.3
–0.3
–1
21
1.3
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
VREF
PVIN3, PVIN4, PVIN5, LDO5P0, V5ANA, DRV5V_1_6, DRV5V_2_A1
PGNDSNS1, PGNDSNS2, PGNDSNS6, AGND, FBGND2
DRVH1, DRVH2, DRVH6, BOOT1, BOOT2, BOOT6
DRVL1, DRVL2, DRVL6
5
5.5
0.3
26.5
5.5
SW1, SW2, SW6
21
LX3, LX4, LX5
–1
5.5
FBVOUT1, FBVOUT2, FBVOUT6, FB3, FB4, FB5
LDO3P3, ILIM1, ILIM2, ILIM6, LDOA1
PVINVTT
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
3.6
3.3
VDDQ
VDDQ / 2
3.6
VTT, VTTFB
PVINSWA1, SWA1
3.3
PVINSWB1_B2, PVINLDOA2_A3, SWB1, SWB2
LDOA2, LDOA3
1.8
1.5
DIGITAL IOs
DATA, CLK, PMICEN, SLP_S4B, SLP_S3B, LDOLS_EN, SWA1_EN,
SLP_S0B, THERMTRIPB, PROCHOT, IRQB, RSMRSTB, PCH_PWROK,
GPO
–0.3
3.3
V
CHIP
TA
TJ
Operating ambient temperature
Operating junction temperature
–40
–40
27
27
85
°C
°C
125
5.4 Thermal Information
TPS65094x
THERMAL METRIC(1)
RSK (VQFN)
64 PINS
25.8
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
11.3
4.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
4.4
RθJC(bot)
0.7
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
5.5 Electrical Characteristics: Total Current Consumption
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
PMIC shutdown current that includes IQ for
references, LDO5, LDO3P3, and digital core
VSYS = 13 V, all functional output rails
are disabled
ISD
65
µA
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5.6 Electrical Characteristics: Reference and Monitoring System
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE
Band-gap reference voltage
Accuracy
1.25
V
VREF
–0.5%
0.047
5.24
0.5%
0.22
5.56
CVREF
Band-gap output capacitor
VSYS UVLO threshold for LDO5
0.1
5.4
µF
V
VSYS_UVLO_5V
VSYS falling
VSYS UVLO threshold hysteresis for VSYS rising above
VSYS_UVLO_5V_HYS
VSYS_UVLO_3V
200
3.6
mV
V
LDO5
VSYS_UVLO_5V
VSYS UVLO threshold for LDO3P3
VSYS falling
3.45
3.75
VSYS UVLO threshold hysteresis for VSYS rising above
VSYS_UVLO_3V_HYS
150
mV
LDO3P3
VSYS_UVLO_3V
TCRIT
Critical threshold of die temperature
Hysteresis of TCRIT
TJ rising
130
110
145
10
160
120
°C
°C
°C
°C
TCRIT_HYS
THOT
TJ falling
TJ rising
Hot threshold of die temperature
Hysteresis of THOT
115
10
THOT_HYS
LDO5
VIN
TJ falling
Input voltage at VSYS pin
DC output voltage
13
5
21
5.1
V
V
VOUT
IOUT = 10 mA
4.9
IOUT
DC output current
100
180
mA
Measured with output shorted to
ground
IOCP
Overcurrent protection
200
mA
Power Good assertion threshold in
percentage of target VOUT
VTH_PG
VOUT rising
94%
VTH_PG_HYS
IQ
Power Good deassertion hysteresis
Quiescent current
VOUT rising or falling
VIN = 13 V, IOUT = 0 A
4%
20
µA
µF
COUT
External output capacitance
2.7
4.7
10
1
V5ANA-to-LDO5P0 LOAD SWITCH
VIN = 5 V, measured from
V5ANA pin
to LDO5P0 pin at IOUT = 200
mA
RDSON
On resistance
Ω
Power Good threshold for external
5-V supply
VTH_PG
VTH_HYS_PG
ILKG
VV5ANA rising
VV5ANA falling
4.7
V
Power Good threshold hysteresis for
external 5-V supply
100
mV
µA
Switch disabled,
VV5ANA = 5 V, VLDO5 = 0 V
Leakage current
10
21
LDO3P3
VIN
Input voltage at VSYS pin
DC output voltage
13
V
V
IOUT = 10 mA
3.3
VOUT
VIN = 13 V,
IOUT = 10 mA
Accuracy
–3%
70
3%
40
IOUT
IOCP
DC output current
Overcurrent protection
mA
mA
Measured with output shorted to
ground
Power Good assertion threshold in
percentage of target VOUT
VTH_PG
VTH_PG_HYS
IQ
VOUT rising
VOUT falling
92%
3%
20
Power Good deassertion hysteresis
VIN = 13 V,
IOUT = 0 A
Quiescent current
µA
µF
COUT
External output capacitance
2.2
4.7
10
12
Specifications
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5.7 Electrical Characteristics: Buck Controllers
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BUCK1
Power input voltage for
external HSD FET
VIN
5.6
13
21
V
Step size
10
0
mV
BUCK1_VID[6:0] = 0000000
BUCK1_VID[6:0] = 0000001
BUCK1_VID[6:0] = 0000010
⋮
0.5
0.51
⋮
DC output voltage
V
BUCK1_VID[6:0] = 0110011 (default)
⋮
1.00
⋮
VOUT
BUCK1_VID[6:0] = 1110101
BUCK1_VID[6:0] = 1110110–1111111
1.66
1.67
V
OUT ≥ 1 V, IOUT = 100 mA to 5 A
VOUT = 0.75 V, IOUT = 100 mA to 2.1 A
OUT ≤ 0.6 V, IOUT = 10 mA
–2%
–2.5%
–3.5%
–20
2%
2.5%
3.5%
40
DC output voltage
accuracy
V
Total output voltage
accuracy (DC + ripple) in
DCM
IOUT = 10 mA, VOUT ≤ 0.785 V, VSYS = 13 V
IOUT = 10 mA, VOUT ≤ 0.785 V, VSYS = 21 V
mV
–20
2.5
55
SR(VOUT
)
Output DVS slew rate
3.125
mV/µs
Low-side output valley
current limit accuracy
(programmed by external
ILIM_LSD
See Section 6.3.3.4, Current Limit, for details.
–15%
15%
resistor RLIM
)
Low-side current zero
crossing detection
threshold
VTH_ZC
–11
45
11
55
mV
Source current out of
ILIM1 pin
ILIMREF
VLIM
T = 25°C
50
µA
V
Voltage at ILIM1 pin
Line regulation
VLIM = RLIM × ILIMREF
0.2
2.25
ΔVOUT/ΔVIN
VOUT ≥ 1 V, IOUT = 5 A
–0.5%
0.5%
VIN = 13 V, VOUT ≥ 1 V,
IOUT = 0 A to 5 A,
referenced to VOUT at IOUT = 5 A
ΔVOUT/ΔIOUT
Load regulation
0%
1%
50
DC + AC at sense point, VIN = 13 V,
VOUT = 1.00 V,
IOUT = 1.5 A to 5 A and 5 A to 1.5 A with 1 µs of
tr and tf
(1)
ΔVOUT_TR
Load transient regulation
–50
mV
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V,
IOUT = 0.3 A to 1.5 A and 1.5 A to 0.3 A with 1 µs
of tr and tf
Power Good deassertion VOUT rising
threshold in percentage
of target VOUT
108%
92%
VTH_PG
VOUT falling
Power Good reassertion
VTH_HYS_PG
hysteresis entering back VOUT rising or falling
into VTH_PG
3%
External output
capacitance
Recommended amount to meet transient
specification
COUT
LSW
180
220
µF
µH
External output
inductance
0.376
0.47
0.564
(1) Frequency of transient load current ranges from 0 to 1 MHz with duty cycle of 50%. For cases where duty cycle and frequency are
limited by tr and tf, the highest frequency is set by 1 / (tr + tf), where tr is rise time (0% to 100%) and tf is fall time (100% to 0%).
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Electrical Characteristics: Buck Controllers (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Source, IDRVH = –50 mA
MIN
TYP
3
MAX UNIT
RDSON_DRVH
Driver DRVH resistance
Ω
Sink, IDRVH = 50 mA
Source, IDRVL = –50 mA
Sink, IDRVL = 50 mA
BUCK1_DIS[1:0] = 01
BUCK1_DIS[1:0] = 10
BUCK1_DIS[1:0] = 11
2
3
RDSON_DRVL
Driver DRVL resistance
Ω
0.4
100
200
500
100
Output auto-discharge
resistance
RDIS
Ω
CBOOT
RON_BOOT
BUCK2
VIN
Bootstrap capacitance
nF
Bootstrap switch ON
resistance
20
21
Ω
Power input voltage for
external HSD FET
5.6
13
V
Step size
10
0
mV
BUCK2_VID[6:0] = 0000000 (default)
BUCK2_VID[6:0] = 0000001
BUCK2_VID[6:0] = 0000010
⋮
0.5
0.51
⋮
DC output voltage
V
BUCK2_VID[6:0] = 1110101
BUCK2_VID[6:0] = 1110110–1111111
1.66
1.67
VOUT
V
OUT ≥ 1 V, IOUT = 100 mA to 21 A
VOUT = 0.75 V, IOUT = 100 mA to 6.3 A
OUT ≤ 0.6 V, IOUT = 10 mA
–2%
–2.5%
–3.5%
2%
2.5%
3.5%
DC output voltage
accuracy
V
Total output voltage
accuracy (DC + ripple) in IOUT = 10 mA, VOUT ≤ 0.765 V
DCM
–20
2.5
40
mV
SR(VOUT
)
Output DVS slew rate
3.125
mV/µs
Low-side output valley
current limit accuracy
ILIM_LSD
See Section 6.3.3.4, Current Limit, for details.
–15%
15%
(programmed by external
resistor RLIM
)
Low-side current zero
crossing detection
threshold
VTH_ZC
–11
45
11
55
mV
Source current out of
ILIM2 pin
ILIMREF
VLIM
T = 25°C
50
µA
V
Voltage at ILIM2 pin
Line regulation
VLIM = RLIM × ILIMREF
0.2
2.25
ΔVOUT/ΔVIN
VOUT ≥ 1 V, IOUT = 21 A
–0.5%
0.5%
VIN = 13 V, 1 V ≤ VOUT ≤ 1.3 V,
IOUT = 0 A to 21 A,
referenced to VOUT at IOUT = 21 A
ΔVOUT/ΔIOUT
Load regulation
0%
–160
–50
1%
30(2)
50(2)
DC + AC at sense point, VIN = 13 V, VOUT = 1 V,
IOUT = 1 A to 21 A and 21 A to 1 A with 1 µs of tr
and tf
(1)
ΔVOUT_TR
Load transient regulation
mV
DC + AC at sense point, VIN = 13 V,
VOUT = 0.75 V, IOUT = 1 A to 3.3 A and 3.3 A to
1 A with 1 µs of tr and tf
Power Good deassertion VOUT rising
threshold in percentage
of target VOUT
108%
92%
VTH_PG
VOUT falling
(2) Additional overshoot of up to 100 mV is allowed as long as it lasts less than 50 µs.
14 Specifications
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Electrical Characteristics: Buck Controllers (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power Good reassertion
VTH_HYS_PG
hysteresis entering back VOUT rising or falling
into VTH_PG
3%
External output
inductance
LSW
0.176
440
0.22
550
0.264
µH
µF
External output
capacitance
Recommended amount to meet transient
specification
COUT
Source, IDRVH = –50 mA
Sink, IDRVH = 50 mA
Source, IDRVL = –50 mA
Sink, IDRVL = 50 mA
BUCK2_DIS[1:0] = 01
BUCK2_DIS[1:0] = 10
BUCK2_DIS[1:0] = 11
3
2
RDSON_DRVH
Driver DRVH resistance
Driver DRVL resistance
Ω
Ω
3
RDSON_DRVL
0.4
100
200
500
100
Output auto-discharge
resistance
RDIS
Ω
CBOOT
RON_BOOT
BUCK6
VIN
Bootstrap capacitance
nF
Bootstrap switch ON
resistance
20
21
Ω
Power input voltage for
external HSD FET
5.6
13
V
Step size
10
0
mV
BUCK6_VID[6:0] = 0000000
BUCK6_VID[6:0] = 0000001
BUCK6_VID[6:0] = 0000010
⋮
0.5
0.51
⋮
BUCK6_VID[6:0] = 0111101 (TPS650940 and
TPS650944 default)
1.1
DC output voltage
⋮
⋮
1.2
⋮
V
VOUT
BUCK6_VID[6:0] = 1000111 (TPS650941 default)
⋮
BUCK6_VID[6:0] = 1010110 (TPS650942 default)
⋮
1.35
⋮
BUCK6_VID[6:0] = 1110101
BUCK6_VID[6:0] = 1110110–1111111
1.66
1.67
DC output voltage
accuracy
VOUT ≥ 1 V, IOUT = 100 mA to 7 A
–2%
2%
Low-side output valley
current limit accuracy
(programmed by external
ILIM_LSD
See Section 6.3.3.4, Current Limit, for details.
–15%
15%
resistor RLIM
)
Low-side current zero
crossing detection
threshold
VTH_ZC
–11
45
11
55
mV
Source current out of
ILIM6 pin
ILIMREF
T = 25°C
50
µA
V
VLIM
Voltage at ILIM6 pin
Line regulation
VLIM = RLIM × ILIMREF
0.2
2.25
ΔVOUT/ΔVIN
VOUT ≥ 1 V, IOUT = 7 A
–0.5%
0.5%
VIN = 13 V, VOUT ≥ 1 V, IOUT = 0 A to 7 A,
referenced to VOUT at IOUT = 7 A
ΔVOUT/ΔIOUT
Load regulation
0%
1%
DC + AC at sense point, VIN = 13 V,
ΔVOUT_TR
Load transient regulation VOUT = 1.35 V, IOUT = 2.1 A to 7 A and 7 A to
2.1 A with 1.96 µs of tr and tf (2.5 A/µs)
–5%
5%
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Electrical Characteristics: Buck Controllers (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power Good deassertion VOUT rising
threshold in percentage
of target VOUT
108%
VTH_PG
VOUT falling
92%
Power Good reassertion
VTH_HYS_PG
hysteresis entering back VOUT rising or falling
into VTH_PG
3%
External output
inductance
LSW
0.376
150
0.47
220
0.564
µH
µF
External output
capacitance
Recommended amount to meet transient
specification
COUT
Source, IDRVH = –50 mA
Sink, IDRVH = 50 mA
Source, IDRVL = –50 mA
Sink, IDRVL = 50 mA
BUCK6_DIS[1:0] = 01
BUCK6_DIS[1:0] = 10
BUCK6_DIS[1:0] = 11
3
2
RDSON_DRVH
Driver DRVH resistance
Driver DRVL resistance
Ω
Ω
3
RDSON_DRVL
0.4
100
200
500
100
Output auto-discharge
resistance
RDIS
Ω
CBOOT
Bootstrap capacitance
nF
Bootstrap switch ON
resistance
RON_BOOT
20
Ω
16
Specifications
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ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
5.8 Electrical Characteristics: Synchronous Buck Converters
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BUCK3
VIN
Power input voltage
4.5
5
25
5.5
V
Step size
mV
BUCK3_VID[6:0] = 0000000
BUCK3_VID[6:0] = 0000001
BUCK3_VID[6:0] = 0000010
⋮
0
0.65
0.675
⋮
DC output voltage
V
VOUT
BUCK3_VID[6:0] = 0010001 (default)
⋮
1.05
⋮
BUCK3_VID[6:0] = 1110101
BUCK3_VID[6:0] = 1110110–1111111
VOUT = 1.05 V, IOUT = 1.5 A
VOUT = 1.05 V, IOUT = 100 mA
3.55
3.575
–2%
–2.5%
2.5
2%
DC output voltage
accuracy
2.5%
SR(VOUT
)
Output DVS slew rate
3.125
35
mV/µs
A
Continuous DC output
current
IOUT
3
7
IIND_LIM
IQ
HSD FET current limit
Quiescent current
Line regulation
4.3
A
VIN = 5 V, VOUT = 1 V
µA
ΔVOUT/ΔVIN
VOUT = 1.05 V, IOUT = 1.5 A
–0.5%
–0.2%
0.5%
2%
VIN = 5 V, VOUT = 1.05 V, IOUT = 0 A to 3 A,
referenced to VOUT at IOUT = 1.5 A
ΔVOUT/ΔIOUT
Load regulation
DC + AC at sense point,
VIN = 5 V, VOUT = 1.05 V, IOUT = 0.9 A to 3 A and 3 A
to 0.9 A with slew rate of 2.5 A/µs
Load transient
regulation
(1)
ΔVOUT_TR
–5%
7%
Power Good
VOUT rising
108%
92%
deassertion threshold
in percentage of
target VOUT
VTH_PG
VOUT falling
Power Good
reassertion hysteresis
entering back into
VTH_PG
VTH_HYS_PG
VOUT rising or falling
3%
LSW
CIN
Output inductance
0.376
2.5
0.47
10
0.564
12
µH
µF
Input bypass
capacitance
Output filtering
capacitance
COUT
61.6
88
110
µF
BUCK3_DIS[1:0] = 01
BUCK3_DIS[1:0] = 10
BUCK3_DIS[1:0] = 11
100
200
500
Output auto-discharge
resistance
RDIS
Ω
(1) Frequency of transient load current ranges from 0 to 1 MHz with duty cycle of 50%. For cases where duty cycle and frequency are
limited by tr and tf, the highest frequency is set by 1 / (tr + tf), where tr is rise time (0% to 100%) and tf is fall time (100% to 0%).
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Electrical Characteristics: Synchronous Buck Converters (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BUCK4
VIN
Power input voltage
4.5
5
25
5.5
V
Step size
mV
BUCK4_VID[6:0] = 0000000
BUCK4_VID[6:0] = 0000001
BUCK4_VID[6:0] = 0000010
⋮
0
0.65
0.675
⋮
DC output voltage
V
VOUT
BUCK4_VID[6:0] = 0101111 (default)
⋮
1.8
⋮
BUCK4_VID[6:0] = 1110101
BUCK4_VID[6:0] = 1110110–1111111
VOUT = 1.8 V, IOUT = 1.5 A
VOUT = 1.8 V, IOUT = 100 mA
3.55
3.575
–2%
2%
DC output voltage
accuracy
–2.5%
2.5%
Continuous DC output
current
IOUT
3
7
A
IIND_LIM
IQ
HSD FET current limit
Quiescent current
Line regulation
4.3
A
VIN = 5 V, VOUT = 1.8 V
35
µA
ΔVOUT/ΔVIN
VOUT = 1.8 V, IOUT = 1.5 A
–0.5%
–0.2%
0.5%
VIN = 5 V, VOUT = 1.8 V, IOUT = 0 A to 1.5 A,
referenced to VOUT at IOUT = 0.75 A
ΔVOUT/ΔIOUT
Load regulation
0.65%
DC + AC at sense point, VIN = 5 V, VOUT = 1.8 V,
IOUT = 0.45 A to 1.5 A and 1.5 A to 0.45 A with slew
rate of 2.5 A/µs
Load transient
regulation
(1)
ΔVOUT_TR
–5%
5%
Power Good
VOUT rising
108%
92%
deassertion threshold
in percentage of
target VOUT
VTH_PG
VOUT falling
Power Good
reassertion hysteresis
entering back into
VTH_PG
VTH_HYS_PG
VOUT rising or falling
3%
LSW
CIN
Output inductance
0.376
2.5
0.47
10
0.564
12
µH
µF
Input bypass
capacitance
Output filtering
capacitance
COUT
46
66
110
µF
BUCK4_DIS[1:0] = 01
BUCK4_DIS[1:0] = 10
BUCK4_DIS[1:0] = 11
100
200
500
Output auto-discharge
resistance
RDIS
Ω
18
Specifications
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ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
Electrical Characteristics: Synchronous Buck Converters (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BUCK5
VIN
Power input voltage
4.5
5
10
5.5
V
Step size
mV
BUCK5_VID[6:0] = 0000000
BUCK5_VID[6:0] = 0000001
BUCK5_VID[6:0] = 0000010
⋮
0
0.5
0.51
⋮
DC output voltage
V
VOUT
BUCK5_VID[6:0] = 1001011 (default)
⋮
1.24
⋮
BUCK5_VID[6:0] = 1110101
BUCK4_VID[6:0] = 1110110–1111111
VOUT = 1.24 V, IOUT = 1.5 A
VOUT = 1.24 V, IOUT = 100 mA
1.66
1.67
–2%
2%
DC output voltage
accuracy
–2.5%
2.5%
Continuous DC output
current
IOUT
3.2
7
A
IIND_LIM
IQ
HSD FET current limit
Quiescent current
Line regulation
4.3
A
VIN = 5 V, VOUT = 1.24 V
35
µA
ΔVOUT/ΔVIN
VOUT = 1.24 V, IOUT = 1.5 A
–0.5%
–0.2%
0.5%
1%
VIN = 5 V, VOUT = 1.24 V, IOUT = 0 A to 1.5 A,
referenced to VOUT at IOUT = 0.75 A
ΔVOUT/ΔIOUT
Load regulation
DC + AC at sense point, VIN = 5 V,
VOUT = 1.24 V, IOUT = 0.45 A to 1.5 A and 1.5 A to
0.45 A with slew rate of 2.5 A/µs
Load transient
regulation
(1)
ΔVOUT_TR
–5%
5%
Power Good
VOUT rising
108%
92%
deassertion threshold
in percentage of
target VOUT
VTH_PG
VOUT falling
Power Good
reassertion hysteresis
entering back into
VTH_PG
VTH_HYS_PG
VOUT rising or falling
3
LSW
CIN
Output inductance
0.376
2.5
0.47
10
0.564
12
µH
µF
Input bypass
capacitance
Output filtering
capacitance
COUT
31
44
110
µF
BUCK5_DIS[1:0] = 01
BUCK5_DIS[1:0] = 10
BUCK5_DIS[1:0] = 11
100
200
500
Output auto-discharge
resistance
RDIS
Ω
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5.9 Electrical Characteristics: LDOs
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LDOA1
VIN
Input voltage
4.5
5
1.35
1.5
1.6
1.7
1.8
1.9
2
5.5
V
IOUT = 10 mA, LDOA1_SEL[3:0] = 0000
LDOA1_SEL[3:0] = 0001
LDOA1_SEL[3:0] = 0010
LDOA1_SEL[3:0] = 0011
LDOA1_SEL[3:0] = 0100 (TPS650944 default)
LDOA1_SEL[3:0] = 0101
LDOA1_SEL[3:0] = 0110
LDOA1_SEL[3:0] = 0111
2.1
2.3
2.4
2.5
2.7
2.85
3
VOUT
DC output voltage
V
LDOA1_SEL[3:0] = 1000
LDOA1_SEL[3:0] = 1001
LDOA1_SEL[3:0] = 1010
LDOA1_SEL[3:0] = 1011
LDOA1_SEL[3:0] = 1100
LDOA1_SEL[3:0] = 1101
LDOA1_SEL[3:0] = 1110 (TPS650940,
TPS650941, and TPS650942 default)
3.3
VOUT
Accuracy
IOUT = 0 to 200 mA
–2%
2%
200
IOUT
DC output current
Line regulation
mA
mA
ΔVOUT/ΔVIN
IOUT = 40 mA
–0.5%
–2%
0.5%
2%
ΔVOUT/ΔIOUT Load regulation
IOUT = 10 mA to 200 mA
VIN = 5 V, Measured with output shorted to
ground
IOCP
Overcurrent protection
500
Power Good deassertion
threshold in percentage of target
VOUT
VOUT rising
VOUT falling
108%
92%
VTH_PG
Power Good reassertion
hysteresis entering back into
VTH_PG
VTH_HYS_PG
VOUT rising or falling
IOUT = 0 A
3%
IQ
Quiescent current
External output capacitance
ESR
23
µA
µF
2.7
4.7
10
COUT
100 mΩ
LDOA1_DIS[1:0] = 01
100
190
450
RDIS
Output auto-discharge resistance LDOA1_DIS[1:0] = 10
LDOA1_DIS[1:0] = 11
Ω
20
Specifications
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Electrical Characteristics: LDOs (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LDOA2
VOUT
VDROP
+
VIN
Power input voltage
1.8
1.98
V
(1)
LDOA2_VID[3:0] = 0000 (TPS650944 default)
LDOA2_VID[3:0] = 0001
LDOA2_VID[3:0] = 0010
LDOA2_VID[3:0] = 0011
LDOA2_VID[3:0] = 0100
LDOA2_VID[3:0] = 0101
LDOA2_VID[3:0] = 0110
LDOA2_VID[3:0] = 0111
LDOA2_VID[3:0] = 1000
LDOA2_VID[3:0] = 1001
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
DC output voltage in normal
operating mode
VOUT
V
1.15
LDOA2_VID[3:0] = 1010 (TPS650940,
TPS650941, and TPS650942 default)
1.2
LDOA2_VID[3:0] = 1011
LDOA2_VID[3:0] = 1100
LDOA2_VID[3:0] = 1101
LDOA2_VID[3:0] = 1110
LDOA2_VID[3:0] = 1111
IOUT = 0 to 600 mA
1.25
1.3
1.35
1.4
1.5
VOUT
IOUT
DC output voltage accuracy
DC output current
–2%
3%
600
mA
mV
VOUT = 0.99 × VOUT_NOM
IOUT = 600 mA
,
VDROP
Dropout voltage
350
ΔVOUT/ΔVIN
Line regulation
IOUT = 300 mA
–0.5%
–2%
0.5%
2%
ΔVOUT/ΔIOUT Load regulation
IOUT = 10 mA to 600 mA
IOCP
Overcurrent protection
Measured with output shorted to ground
VOUT rising
0.65
1.25
108%
92%
A
Power Good assertion threshold
in percentage of target VOUT
VTH_PG
VOUT falling
Power Good deassertion
hysteresis
VTH_HYS_PG
IQ
VOUT falling
IOUT = 0 A
3%
20
Quiescent current
µA
dB
f = 1 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
48
COUT = 2.2 µF to 4.7 µF
PSRR
Power supply rejection ratio
f = 10 kHz, VIN = 1.8 V, VOUT = 1.2 V,
IOUT = 300 mA,
30
dB
µF
COUT = 2.2 µF to 4.7 µF
External output capacitance
ESR
2.2
4.7
10
COUT
100 mΩ
LDOA2_DIS[1:0] = 01
80
180
475
RDIS
Output auto-discharge resistance LDOA2_DIS[1:0] = 10
LDOA2_DIS[1:0] = 11
Ω
(1) The minimum value must be equal to or greater than 1.62 V.
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Electrical Characteristics: LDOs (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LDOA3
VOUT
VDROP
+
VIN
Power input voltage
1.8
1.98
V
(1)
LDOA3_VID[3:0] = 0000 (TPS650944 default)
LDOA3_VID[3:0] = 0001
LDOA3_VID[3:0] = 0010
LDOA3_VID[3:0] = 0011
LDOA3_VID[3:0] = 0100
LDOA3_VID[3:0] = 0101
LDOA3_VID[3:0] = 0110
LDOA3_VID[3:0] = 0111
LDOA3_VID[3:0] = 1000
LDOA3_VID[3:0] = 1001
LDOA3_VID[3:0] = 1010
0.7
0.75
0.8
0.85
0.9
0.95
1
1.05
1.1
DC output voltage in normal
operating mode
VOUT
V
1.15
1.2
LDOA3_VID[3:0] = 1011 (TPS650940,
TPS650941, and TPS650942 default)
1.25
LDOA3_VID[3:0] = 1100
LDOA3_VID[3:0] = 1101
LDOA3_VID[1:0] = 1110
LDOA3_VID[1:0] = 1111
IOUT = 0 to 600 mA
1.3
1.35
1.4
1.5
VOUT
IOUT
IOCP
DC output voltage accuracy
DC output current
–2%
0.65
3%
600
mA
A
Overcurrent protection
Measured with output shorted to ground
1.25
VOUT = 0.99 × VOUT_NOM
IOUT = 600 mA
,
VDROP
Dropout voltage
Line regulation
350
mV
ΔVOUT/ΔVIN
IOUT = 300 mA
IOUT = 10 mA to 600 mA
VOUT rising
–0.5%
–2%
0.5%
2%
ΔVOUT/ΔIOUT Load regulation
108%
92%
Power Good assertion threshold
in percentage of target VOUT
VTH_PG
VOUT falling
Power Good deassertion
hysteresis
VTH_HYS_PG
IQ
VOUT falling
IOUT = 0 A
3%
20
Quiescent current
µA
dB
µF
f = 1 kHz, VIN = 1.8 V,
VOUT = 1.2 V,
IOUT = 300 mA,
48
COUT = 2.2 µF to 4.7 µF
PSRR
Power supply rejection ratio
f = 10 kHz, VIN = 1.8 V,
VOUT = 1.2 V,
IOUT = 300 mA,
30
COUT = 2.2 µF to 4.7 µF
External output capacitance
ESR
2.2
4.7
10
COUT
100 mΩ
LDOA3_DIS[1:0] = 01
80
180
475
RDIS
Output auto-discharge resistance LDOA3_DIS[1:0] = 10
LDOA3_DIS[1:0] = 11
Ω
22
Specifications
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ZHCSFJ2C –SEPTEMBER 2015–REVISED FEBRUARY 2019
Electrical Characteristics: LDOs (continued)
over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VTT LDO
VIN
Power input voltage
DC output voltage
VDDQ
VIN / 2
3.3
V
V
Measured at VTTFB pin
VOUT
Relative to VIN / 2, IOUT = 100 mA,
1.1 V ≤ VIN ≤ 1.5 V
DC output voltage accuracy
–10
–500
–500
–1800
–10
10
500
500
1800
10
mV
mA
DC Output Current (RMS Value
Over Operation)
1.1 V ≤ VIN ≤ 1.5 V
0
source(+) and sink(–): LPDDR3 and LPDDR4
OTPs, 1.1 V ≤ VIN ≤ 1.5 V
IOUT
Pulsed Current (Duty Cycle
Limited to Remain Below DC
RMS Specification)
mA
source(+) and sink(–): DDR3L OTPs, 1.1 V ≤
VIN ≤ 1.5 V
Relative to VIN / 2, IOUT ≤ 10 mA,
1.1 V ≤ VIN ≤ 1.5 V
Relative to VIN / 2, IOUT ≤ 500 mA,
1.1 V ≤ VIN ≤ 1.5 V
–20
20
ΔVOUT/ΔIOUT Load regulation
mV
Relative to VIN / 2, IOUT ≤ 1200 mA,
1.1 V ≤ VIN ≤ 1.5 V
–30
30
Relative to VIN / 2, IOUT ≤ 1800 mA,
1.1 V ≤ VIN ≤ 1.5 V
–40
40
DC + AC at sense point, 1.1 V ≤ VIN ≤ 1.5 V,
(IOUT = 0 to 350 mA and 350 mA to 0) AND
(0 to –350 mA and –350 mA to 0) with 1 µs of
rise and fall time
ΔVOUT_TR
Load transient regulation
–5%
5%
COUT = 40 µF
Measured with output shorted to ground: OTPs
with VTT ILIM = 0.95 A
0.95
1.8
IOCP
Overcurrent protection
A
Measured with output shorted to ground: OTPs
with VTT ILIM = 1.8 A
Power Good deassertion
threshold in percentage of target
VOUT
VOUT rising
VOUT falling
110%
95%
VTH_PG
Power Good reassertion
hysteresis entering back into
VTH_PG
VTH_HYS_PG
VOUT rising or falling
5%
IQ
Total ground current
VIN = 1.2 V, IOUT = 0 A
VIN = 1.2 V, disabled
240
1
µA
µA
µF
µF
ILKG
CIN
COUT
OFF leakage current
External input capacitance
External output capacitance
10
35
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MAX UNIT
5.10 Electrical Characteristics: Load Switches
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
SWA1
VIN
Input voltage range
DC output current
0.5
1.8
3.3
V
IOUT
300
mA
VIN = 1.8 V, measured from PVINSWA1 pin
to SWA1 pin at IOUT = IOUT(MAX)
60
93
RDSON
ON resistance
mΩ
VIN = 3.3 V, measured from PVINSWA1 pin
to SWA1 pin at IOUT = IOUT(MAX)
100
165
VOUT rising
VOUT falling
108%
92%
Power Good deassertion threshold in
percentage of target VOUT
VTH_PG
VTH_HYS_PG
IINRUSH
Power Good reassertion hysteresis
entering back into VTH_PG
VOUT rising or falling
2%
Inrush current upon turnon
VIN = 3.3 V, COUT = 0.1 µF
VIN = 3.3 V, IOUT = 0 A
10
mA
µA
10.5
9
IQ
Quiescent current
VIN = 1.8 V, IOUT = 0 A
Switch disabled, VIN = 1.8 V
Switch disabled, VIN = 3.3 V
7
370
900
ILKG
Leakage current
nA
µF
10
COUT
External output capacitance
0.1
100
200
500
SWA1_DIS[1:0] = 01
SWA1_DIS[1:0] = 10
SWA1_DIS[1:0] = 11
RDIS
Output auto-discharge resistance
Ω
SWB1_2
VIN
Input voltage range
0.5
1.8
3.3
V
IOUT
DC current per output
400
mA
VIN = 1.8 V, measured from PVINSWB1_B2
pin to SWB1 or SWB2 pin at IOUT
IOUT(MAX)
=
68
75
92
RDSON
ON resistance per output
mΩ
VIN = 3.3 V, measured from PVINSWB1_B2
pin to SWB1 or SWB2 pin at IOUT
IOUT(MAX)
=
125
VOUT rising
VOUT falling
108%
92%
Power Good deassertion threshold in
percentage of target VOUT
VTH_PG
VTH_HYS_PG
IINRUSH
Power Good reassertion hysteresis
entering back into VTH_PG
VOUT rising or falling
2%
Inrush current upon turning on
VIN = 3.3 V, COUT = 0.1 µF
VIN = 3.3 V, IOUT = 0 A
10
mA
µA
10.5
9
IQ
Quiescent current
VIN = 1.8 V, IOUT = 0 A
Switch disabled, VIN = 1.8 V
Switch disabled, VIN = 3.3 V
7
460
ILKG
Leakage current
nA
µF
10
1150
COUT
External output capacitance
0.1
100
200
500
SWBx_DIS[1:0] = 01
SWBx_DIS[1:0] = 10
SWBx_DIS[1:0] = 11
RDIS
Output auto-discharge resistance
Ω
24
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5.11 Digital Signals: I2C Interface
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
Low-level output voltage
High-level input voltage
Low-level input voltage
Leakage current
TEST CONDITIONS
VPULL_UP = 1.8 V
MIN
TYP
MAX UNIT
VOL
VIH
VIL
0.4
V
V
1.2
0.4
0.3
8.5
2.5
1
V
ILKG
VPULL_UP = 1.8 V
Standard mode
Fast mode
0.01
µA
RPULL-UP Pullup resistance
kΩ
Fast mode plus
COUT
Total load capacitance per pin
50
pF
5.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B,
SLP_S4B, SLP_S0B)
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
High-level input voltage
Low-level input voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIH
VIL
0.85
V
0.4
V
5.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
Over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
Low-level output voltage
Leakage current
TEST CONDITIONS
IOL < 2 mA
VPULL_UP = 1.8 V
MIN
TYP
MAX UNIT
VOL
ILKG
0.4
V
0.35
µA
5.14 Timing Requirements
over recommended free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
MIN
NOM
MAX
UNIT
kHz
ns
I2C INTERFACE
Clock frequency (standard mode)
100
400
fCLK
Clock frequency (fast mode)
Clock frequency (fast mode plus)
Rise time (standard mode)
Rise time (fast mode)
1000
1000
300
tr
Rise time (fast mode plus)
Rise time (standard mode)
Rise time (fast mode)
120
300
tf
300
ns
Rise time (fast mode plus)
120
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5.15 Switching Characteristics
over operating free-air temperature range and over recommended input voltage range (typical values are at TA = 25°C)
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
BUCK CONTROLLERS
Measured from enable going high to when output reaches 90% of
target value.
tPG
Total turnon time
550
50
850
µs
ns
Minimum ON time
of DRVH
TON,MIN
DRVH off to DRVL on
DRVL off to DRVH on
15
30
TDEAD
fSW
Driver dead-time
ns
Switching
frequency
Continuous-conduction mode,
VIN = 13 V, VOUT ≥ 1 V
1000
kHz
BUCK CONVERTERS
Measured from enable going high to when output reaches 90% of
tPG
Total turnon time
target value.
250
1000
µs
VOUT = 1 V, COUT = 88 µF
Continuous-conduction mode, BUCK3 VOUT = 1 V, IOUT = 1 A
Continuous-conduction mode, BUCK3 VOUT = 1.05 V, IOUT = 1 A
Continuous-conduction mode, BUCK4 VOUT = 1.8 V, IOUT = 1 A
Continuous-conduction mode, BUCK5 VOUT = 1.24 V, IOUT = 1 A
Continuous-conduction mode, BUCK5 VOUT = 1.35 V, IOUT = 1 A
1.6
1.7
2.5
2.4
2.5
Switching
frequency
fSW
MHz
LDOAx
Measured from enable going high to when output reaches 95% of
tSTARTUP Start-up time
final value,
VOUT = 1.2 V, COUT = 4.7 µF
180
22
µs
µs
VTT LDO
Measured from enable going high to PG assertion,
VOUT = 0.675 V, COUT = 40 µF
tSTARTUP Start-up time
SWA1
Measured from enable going high to reach 95% of final value,
VIN = 3.3 V, COUT = 0.1 µF
0.85
0.63
tTURN-ON Turnon time
SWB1_2
ms
ms
Measured from enable going high to reach 95% of final value,
VIN = 1.8 V, COUT = 0.1 µF
Measured from enable going high to reach 95% of final value,
VIN = 3.3 V, COUT = 0.1 µF
1.1
tTURN-ON Turnon time
Measured from enable going high to reach 95% of final value,
VIN = 1.8 V, COUT = 0.1 µF
0.82
26
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5.16 Typical Characteristics
88%
86%
84%
82%
80%
78%
76%
74%
72%
70%
68%
88%
86%
84%
82%
80%
78%
76%
74%
72%
70%
VSYS = 5.4 V
VSYS = 13 V
VSYS = 18 V
VSYS = 5.4 V
VSYS = 13 V
VSYS = 18 V
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
3
6
9
12
15
18
21
Output Load (A)
Output Load (A)
D001
D002
Figure 5-1. BUCK1 (VNN) Efficiency at VOUT = 1 V
Figure 5-2. BUCK2 (VCCGI) Efficiency at VOUT = 1 V
92%
91%
VSYS = 5.4 V
VSYS = 13 V
VSYS = 18 V
PVIN = 4.5 V
PVIN = 5 V
PVIN = 5.5 V
89%
87%
85%
83%
81%
79%
77%
75%
73%
71%
69%
90%
88%
86%
84%
82%
80%
78%
76%
0
1
2
3
4
5
6
7
0
0.5
1
1.5
2
2.5
3
Output Load (A)
Output Load (A)
D011
D003
Figure 5-3. BUCK6 (VDDQ) Efficiency at VOUT = 1.2 V
Figure 5-4. BUCK3 (VCCRAM) Efficiency at VOUT = 1.05 V
92%
90%
PVIN = 4.5 V
PVIN = 5 V
PVIN = 5.5 V
PVIN = 4.5 V
PVIN = 5 V
PVIN = 5.5 V
89%
91%
90%
89%
88%
87%
86%
85%
84%
83%
88%
87%
86%
85%
84%
83%
82%
81%
80%
0
0.25
0.5
0.75
1
1.25
1.5
0
0.25
0.5
0.75
1
1.25
1.5
Output Load (A)
Output Load (A)
D004
D005
Figure 5-5. BUCK4 (V1P8A) Efficiency at VOUT = 1.8 V
Figure 5-6. BUCK5 (V1P24A) Efficiency at VOUT = 1.24 V
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6 Detailed Description
6.1 Overview
The TPS65094x device provides all the necessary power supplies for the Intel Reference Designs. For an
overview of the different OTP configurations, consult Table 3-1. The following VRs are integrated: three
step-down controllers (BUCK1, BUCK2, and BUCK6), three step-down converters (BUCK3, BUCK4, and
BUCK5), a sink and source LDO (VTT LDO), three low-voltage VIN LDOs (LDOA1–LDOA3), and three
load switches that are managed by power-up sequence logic to provide the proper power rails,
sequencing, and protection. All VRs have a built-in discharge resistor, and the value can be changed by
the DISCHCNT1–DISCHCNT3 and LDOA1_CTRL registers. When enabling a VR, the PMIC automatically
disconnects the discharge resistor for that rail without any I2C command. Table 6-1 summarizes the key
characteristics of the voltage rails.
Table 6-1. Summary of Voltage Regulators
INPUT VOLTAGE
(V)
OUTPUT VOLTAGE RANGE
(V)
TYPICAL
APPLICATION
CURRENT
(mA)
RAIL
TYPE
MIN
MAX
MIN
TYP
MAX
BUCK1 (VNN)
Step-down controller
4.5
4.5
21
21
0.5
0.5
1.05
1
1.67
1.67
5000
BUCK2 (VCCGI) Step-down controller
21000
BUCK3
Step-down converter
(VCCRAM)
4.5
5.5
0.65
1.05
3.575
3000
BUCK4 (V1P8A) Step-down converter
BUCK5 (V1P24A) Step-down converter
4.5
4.5
5.5
5.5
21
0.65
0.5
1.8
3.575
1.67
1.67
3.3
1500
1900
1.24
BUCK6 (VDDQ)
LDOA1
Step-down controller
LDO
4.5
0.5
OTP dependent
OTP dependent
OTP dependent
OTP dependent
7000
200(1)
4.5
5.5
1.98
1.98
3.3
3.3
1.35
0.7
LDOA2
LDO
1.62
1.62
0.5
1.5
600
LDOA3
LDO
0.7
1.5
600
SWA1
SWB1_2(2)
Load switch
Load switch
300
0.5
800 (combined)
Sink and source
LDO
VTT
BUCK6 output
VBUCK6 / 2
OTP dependent
(1) When powered from a 5-V supply through the DRV5V_2_A1 pin. Otherwise, maximum current is limited by maximum IOUT of LDO5.
(2) For LPDDR3 and LPDDR4 memory, SWB1_2 is configured to V1P8U and controlled by SLP_S4B. For DDR3L memory, SWB1_2 is
configured to either V3P3S or V1P8S and controlled by SLP_S3B.
28
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6.2 Functional Block Diagram
Figure 6-1 shows a functional block diagram of the PMIC.
Optional(a)
Required(b)
LDO5V
VSYS
BOOT1
DRVH1
EC
LDOA1
PMICEN
BUCK1
Default: 1V
1.35 V to 3.3 V
1.8 V(b)
SW1
SLP_S3B
SLP_S4B
200 mA
VNN
VSET
EN
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
DRVL1
EN
SLP_S0B
Control
FBVOUT1
LDOLS_EN(a)
Inputs
PGNDSNS1
SWA1_EN(b)
5 A
ILIM1
THERMTRIPB
V1P8A
VSYS
BOOT2
DRVH2
CLK
I2C CTRL
BUCK2
Default: 0V
SW2
SoC
DATA
VCCGI
VSET
EN
V1P8A
DRVL2
Typical
Application
Usage:
Control
Outputs
FBVOUT2
0.5 V to 1.45 V
(DVS)
PGNDSNS2
IRQB
21 A
PCH_PWROK
RSMRSTB
PROCHOT
GPO
FBGND2
ILIM2
Internal
Interrupt
Events
BUCK5V
PVIN3
LX3
TEST CTRL
OTP
VSET
EN
BUCK3
Default: 1.05 V
3 A
VCCRAM
FB3
REGISTERS
<PGND_BUCK3>
BUCK5V
BUCK5V
PVIN4
LX4
VSYS
VSYS
BUCK4
Default: 1.8 V
2 A
Digital Core
VSET
EN
V1P8A
V5ANA
LDO5
BUCK5V
FB4
<PGND_BUCK4>
LDO5V
nPUC
LDO3P3
VREF
REFSYS
PVIN5
LX5
VSET
EN
BUCK5
Default: 1.24 V
2 A
V1P24A
FB5
<PGND_BUCK5>
AGND
VSYS
Thermal
monitoring
BOOT6
DRVH6
Thermal shutdown
SW6
BUCK6
Default: OTP
Dependent
7 A
VDDQ
VSET
EN
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
PVINVTT
VTT
VTT_LDO
½ × VDDQ
ILIM set by OTP
VTT
EN
VTTFB
LDOA2
0.7 V to 1.5 V
600 mA
LDOA3
0.7 V to 1.5 V
600 mA
LOAD SWA1
300 mA
LOAD SWB1
400 mA
LOAD SWB2
400 mA
V1P8A(1)
0.5 V to 3.3 V(2)
0.5 V to 3.3 V
Dashed connections optional.
Refer to Pin Attributes for
connection if unused.
(1) LPDDR3 and LPDDR4
(2) DDR3L
(a) LDOA1 Not —Always On“
(b) LDOA1 —Always On“
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Figure 6-1. PMIC Functional Block Diagram
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PMIC
SoC
PLATFORM
VSYS
LDO5P0
BUCK1 5 A
BUCK2 21 A
BUCK3 3 A
EXT FET
VSYS
VNN
EXT FET
VCCGI
VCCRAM
V1P8A
VSYS
BUCK
5 V
BUCK4 2 A
BUCK
3.3 V
BUCK5 2 A
V1P24A
VDDQ
VSYS
VDDQ
BUCK6 7 A
EXT FET
VTT LDO 1.5 A
LDOA2 0.6 A
LDOA3 0.6 A
SWA1 0.3 A
SWB1 0.4 A
SWB2 0.4 A
LDOA1 0.2 A
LDO5 0.18 A
VTT
V1P8A
0.7 V to 1.5 V
0.7 V to 1.5 V
0.5 V to 3.3 V
0.5 V to 3.3 V
V1P8A(1)
V1P8U(1)
800 mA
0.5 V to 3.3 V(2)
0.5 V to 3.3 V(2)
1.35 V to 3.3 V(a)
1.8 V(b)
LDO5P0
VSYS
+
REF
PG_5V
LDO3P3 0.04 A
IRQB
SLP_S4B
SLP_S3B
SLP_S0B
RSMRSTB
PCH_PWROK
THERMTRIPB
PROCHOT
DATA
PMICEN
LDOLS_EN(a)
SWA1_EN(b)
(1) LPDDR3 and LPDDR4
(2) DDR3L
(a) LDOA1 Not —Always On“
(b) LDOA1 —Always On“
SCLK
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Figure 6-2. Apollo Lake Power Map
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6.3 Feature Description
6.3.1 Power Good (PGOOD)
The TPS65094x device provides information on status of VRs through two Power Good signals or pins.
Table 6-2 defines which signals are required to assert the PGOOD signals.
Table 6-2. Power Good Summary
QUALIFYING SIGNALS (LOGICAL AND)
POWER GOOD(1)
RSMRSTB
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
PCH_PWROK
✓
✓
✓
✓
✓
(1) All Power Good signals must immediately deassert at the loss of any of the qualifying signals, or at the occurrence of a fault condition.
6.3.2 Register Reset Conditions
All registers are reset if any of the following conditions are met:
•
•
•
•
VSYS pin voltage drops below 5.4 V
Falling edge of PMICEN for OTPs where LDOA1 is not "Always On"
Falling edge of THERMTRIPB while RSMRSTB = 1
Power fault of any regulator where xx_FLTMSK = 0 (see Section 6.6.27, PWR_FAULT_MASK1
Register, and Section 6.6.28, PWR_FAULT_MASK2 Register)
•
•
PMIC critical temperature shutdown
Software shutdown (writing 1 to the SDWN bit in the FORCESHUTDN register, see Figure 6-35)
Additionally, BUCK1 and BUCK2 VID registers are reset on the falling edge of SLP_S0IXB and SLP_S3B.
6.3.3 SMPS Voltage Regulators
The buck controllers integrate gate drivers for external power stages with programmable current limit (set
by an external resistor at ILIMx pin), which allows for optimal selection of external passive components
based on the desired system load. The buck converters include integrated power stage and require a
minimum number of pins for power input, inductor, and output voltage feedback input. Combined with
high-frequency switching, all these features allow use of inductors in small form factor, thus reducing the
total cost and size of the system.
BUCK3–BUCK6 have selectable auto- and forced-PWM mode through the BUCKx_MODE bit in the
BUCKxCTRL register. In default auto mode, the VR automatically switches between PWM and PFM
depending on the output load to maximize efficiency. The host cannot select Forced PWM mode for other
SMPS VRs as they stay in auto mode at all times.
See Table 6-3 and Table 6-4 for the full voltage tables for all SMPS regulators.
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Table 6-3. 10-mV Step-Size VOUT Range (BUCK1, BUCK2, BUCK5, BUCK6)
VID Bits
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
VOUT
0
VID Bits
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
VOUT
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
1.09
1.10
1.11
1.12
1.13
1.14
1.15
1.16
1.17
1.18
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
1.28
1.29
1.30
1.31
1.32
1.33
1.34
VID Bits
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
VOUT
1.35
1.36
1.37
1.38
1.39
1.40
1.41
1.42
1.43
1.44
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
1.56
1.57
1.58
1.59
1.60
1.61
1.62
1.63
1.64
1.65
1.66
1.67
1.67
1.67
1.67
1.67
1.67
1.67
1.67
1.67
1.67
0.50
0.51
0.52
0.53
0.54
0.55
0.56
0.57
0.58
0.59
0.60
0.61
0.62
0.63
0.64
0.65
0.66
0.67
0.68
0.69
0.70
0.71
0.72
0.73
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
32
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Table 6-4. 25-mV Step-Size VOUT Range (BUCK3, BUCK4)
VID Bits
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
VOUT
0
VID Bits
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
VOUT
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
1.900
1.925
1.950
1.975
2.000
2.025
2.050
2.075
2.100
2.125
2.150
2.175
2.200
2.225
2.250
2.275
2.300
2.325
2.350
2.375
2.400
2.425
2.450
2.475
2.500
2.525
2.550
2.575
2.600
2.625
2.650
2.675
2.700
2.725
2.750
VID Bits
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
VOUT
2.775
2.800
2.825
2.850
2.875
2.900
2.925
2.950
2.975
3.000
3.025
3.050
3.075
3.100
3.125
3.150
3.175
3.200
3.225
3.250
3.275
3.300
3.325
3.350
3.375
3.400
3.425
3.450
3.475
3.500
3.525
3.550
3.575
3.575
3.575
3.575
3.575
3.575
3.575
3.575
3.575
3.575
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
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6.3.3.1 Controller Overview
The controllers are fast-reacting, high-frequency, scalable output power controllers capable of driving two
external N-MOSFETs. They use a D-CAP2 control scheme that optimizes transient responses at high load
currents for such applications as CORE and DDR supplies. The output voltage is compared with internal
reference voltage after divider resistors. The PWM comparator determines the timing to turn on the high-
side MOSFET. The PWM comparator response maintains a very small PWM output ripple voltage.
Because the device does not have a dedicated oscillator for control loop on board, switching cycle is
controlled by the adaptive ON time circuit. The ON time is controlled to meet the target switching
frequency by feed-forwarding the input and output voltage into the ON time one-shot timer.
The D-CAP2 control scheme has an injected ripple from the SW node that is added to the reference
voltage to simulate output ripple, which eliminates the need for ESR-induced output ripple from D-CAP™
mode control. Thus, low-ESR output capacitors (such as low-cost ceramic MLCC capacitors) can be used
with the controllers.
VDD
VREF œ VTH_PG
+
UV
PGOOD
FAULT
EN
œ
PGOOD
+
DCHG
VFB
OV
VREF + VTH_PG
œ
+
+
Control Logic
œ
+
+
PWM
Ramp Generator
REF
BOOTx
DRVHx
SWx
SS Ramp Comp
HS
VSYS
XCON
œ
OC
DRV5V_x_x
œ
50 µA
+
+
ILIM
LS
DRVLx
œ
NOC
+
PGNDSNSx
One-Shot
GND
+
ZC
œ
PMIC Internal Signals
External Inputs/Outputs
Copyright © 2017, Texas Instruments Incorporated
Figure 6-3. Controller Block Diagram
34
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6.3.3.2 Converter Overview
The PMIC synchronous step-down DC-DC converters include a unique hysteretic PWM control scheme
which enables a high switching frequency converter, excellent transient and AC load regulation, as well as
operation with cost-competitive external components. The controller topology supports forced PWM mode
as well as power-save mode operation. Power-save mode operation, or PFM mode, reduces the quiescent
current consumption and ensures high conversion efficiency at light loads by skipping switch pulses. In
forced PWM mode, the device operates on a quasi-fixed frequency, avoids pulse skipping, and allows
filtering of the switch noise by external filter components. The PMIC device offers fixed output voltage
options featuring smallest solution size by using only three external components per converter.
A significant advantage of PMIC compared to other hysteretic PWM controller topologies is the excellent
capability of the AC load transient regulation. When the output voltage falls below the threshold of the
error comparator, a switch pulse is initiated, and the high-side switch is turned on. The high-side switch
remains turned on until a minimum ON-time of tONmin expires and the output voltage trips the threshold of
the error comparator or the inductor current reaches the high-side switch current limit. When the high-side
switch turns off, the low-side switch rectifier is turned on and the inductor current ramps down until the
high-side switch turns on again or the inductor current reaches zero. In forced PWM mode operation,
negative inductor current is allowed to enable continuous conduction mode even at no load condition.
PVINx
VREF
0.40 V
Current
Limit Comparator
Bandgap
Limit
High Side
MODE / EN
Softstart
MODE
NMOS
NMOS
VIN
FB
Gate Driver
Anti
Shoot-Through
Min. ON Time
Control
Logic
LXx
EN
Min. OFF Time
VREF
Limit
Low Side
FBx
Integrated
Feed Back
Network
Error
Comparator
Zero/Negative
Current Limit Comparator
PGND/Thermal Pad
PMIC Internal Signals
External Inputs/Outputs
Copyright © 2016, Texas Instruments Incorporated
Figure 6-4. Converter Block Diagram
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6.3.3.3 DVS
BUCK1–BUCK6 and LDOA1–3 support dynamic voltage scaling (DVS) for maximum system efficiency.
The VR outputs can slew up and down in either 10-mV or 25-mV steps using the 7-bit voltage ID (VID)
defined in Section 5.7, Electrical Characteristics: Buck Controllers, and Section 5.8, Electrical
Characteristics: Synchronous Buck Converters. DVS slew rate is minimum 2.5 mV/µs. To meet the
minimum slew rate, VID progresses to the next code at 3-µs (nom) interval per 10-mV step. When DVS is
active, the VR is forced into PWM mode to ensure the output keeps track of VID code with minimal delay.
Additionally, PGOOD is masked when DVS is in progress. Figure 6-5 shows an example of slew down
and up from one VID to another.
VID
Number of Steps × 3 µs
VOUT
Figure 6-5. DVS Timing Diagram I
As shown in Figure 6-6, if a BUCKx_VID[6:0] is set to 7b000 0000, the output voltage slews down to 0.5 V
first, and then drifts down to 0 V as the SMPS stops switching. Subsequently, if a BUCKx_VID[6:0] is set
to a value (neither 7b000 0000 nor 7b000 0001) when the output voltage is less than 0.5 V, the VR ramps
up to 0.5 V first with soft-start kicking in, then it slews up to the target voltage in the aforementioned slew
rate.
NOTE
A fixed 200 µs of soft-start time is reserved for VOUT to reach 0.5 V. In this case, however,
the SMPS is not forced into PWM mode because it otherwise could cause VOUT to droop
momentarily if VOUT is drifting above 0.5 V for any reason.
VID
Number of
Steps × 3 µs
VOUT
Load and Time
Dependent
200 µs
Figure 6-6. DVS Timing Diagram II
36
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6.3.3.4 Current Limit
The buck controllers (BUCK1, BUCK2, and BUCK6) have inductor-valley current-limit architecture and the
current limit is programmable by an external resistor at the ILIMx pin. Equation 1 shows the calculation for
a desired resistor value, depending on specific application conditions. ILIMREF is the current source out of
the ILIMx pin that is typically 50 µA, and RDSON is the maximum channel resistance of the low-side FET.
The scaling factor is 1.3 to take into account all errors and temperature variations of RDSON, ILIMREF, and
RILIM. Finally, 8 is another scaling factor associated with ILIMREF
.
Iripple(min)
≈
’
÷
◊
RDSON ì 8 ì 1.3 ì I
-
∆
LIM
2
«
RILIM
=
ILIMREF
where
•
ILIM is the target current limit. An appropriate margin must be allowed when determining ILIM from
maximum output DC load current.
•
Iripple(min) is the minimum peak-to-peak inductor ripple current for a given VOUT
.
(1)
VOUT (V
- VOUT )
IN(MIN)
Iripple(min)
=
Lmax ì V
ì fsw(max)
IN(MIN)
where
•
•
•
Lmax is maximum inductance
fsw(max) is maximum switching frequency
VIN(MIN) minimum input voltage to the external power stage
(2)
The buck converter limit inductor peak current cycle-by-cycle to IIND_LIM is specified in Section 5.8,
Electrical Characteristics: Synchronous Buck Converters.
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6.3.4 LDOs and Load Switches
6.3.4.1 VTT LDO
Powered from the BUCK6 output (VDDQ), the VTT LDO tracks VDDQ and regulates to half of the VDDQ
voltage for proper DDR termination. The LDO current limit is OTP dependent, and it is designed
specifically to power DDR memory. The VTT LDO is enabled by assertion (L → H) of the SLP_S0B pin
and is disabled by deassertion (H → L) of the same pin. The LDO core is a transconductance amplifier
with large gain, and it drives a current output stage that either sources or sinks current depending on the
deviation of VTTFB pin voltage from the target regulation voltage.
6.3.4.2 LDOA1–LDOA3
The TPS65094x device integrates three optional general-purpose LDOs. LDOA1 is powered from a 5-V
supply through the DRV5V_2_A1 pin and it can be factory configured to be an Always-On rail as long as a
valid power supply is available at VSYS. See Table 6-5 for LDOA1 output voltage options. LDOA2 and
LDOA3 share a power input pin (PVINLDOA2_A3). The output regulation voltages are set by writing to
LDOAx_VID[3:0] bits (Reg 0x9A, 0x9B, and 0xAE). See Table 6-6 for LDOA2 and LDOA3 output voltage
options. LDOA1 is controlled by LDOA1CTRL register. LDOA2 and LDOA3 can be controlled either by the
LDOLS_EN pin or by writing to the LDOA2_EN bit (Reg 0xA0) and the LDOA3_EN bit (Reg 0xA1) as long
as LDOLS_EN is low.
Table 6-5. LDOA1 Output Voltage Options
VID Bits
0000
VOUT
1.35
1.5
VID Bits
0100
VOUT
1.8
VID Bits
1000
VOUT
2.3
VID Bits
1100
VOUT
2.85
0001
0101
1.9
1001
2.4
1101
3.0
0010
1.6
0110
2.0
1010
2.5
1110
3.3
0011
1.7
0111
2.1
1011
2.7
1111
Not Used
Table 6-6. LDOA2 and LDOA3 Output Voltage Options
VID Bits
0000
VOUT
0.70
0.75
0.80
0.85
VID Bits
0100
VOUT
0.90
0.95
1.00
1.05
VID Bits
1000
VOUT
1.10
1.15
1.20
1.25
VID Bits
1100
VOUT
1.30
1.35
1.40
1.50
0001
0101
1001
1101
0010
0110
1010
1110
0011
0111
1011
1111
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6.3.4.3 Load Switches
The PMIC features three general-purpose load switches. SWA1 has a power input pin (PVINSWA1), while
SWB1 and SWB2 share a power input pin (PVINSWB1_B2). All switches have built-in slew rate control
during start-up to limit the inrush current.
Table 6-7 lists the control signals for enabling and disabling each LDO and load switch.
Table 6-7. Summary of LDO and Load Switch Control
CONTROL SIGNAL
SLP_S4B or SLP_S3B(1)
LDOLS_EN(2)
RAIL
SWB1_2
LDOA2, LDOA3, SWA1
SWA1
SWA1_EN(3)
SLP_S0B(4)
VTT LDO
(1) For LPDDR3 and LPDDR4 memory, SWB1_2 is configured to
V1P8U and controlled by SLP_S4B. For DDR3L memory, SWB1_2
is configured to either V3P3S or V1P8S and controlled by SLP_S3B.
(2) When LDOLS_EN = 0, the user can write to enable bits in Reg
0xA0–Reg 0xA1 to enable or disable the rails. Alternatively, all of
them could be factory configured to be part of sequence along with
other voltage rails. Pin name changed to SWA1_EN when LDOA1 is
factory programmed to always on.
(3) When SWA1_EN = 0, the user can write to enable bits in Reg
0xA0–Reg 0xA1 to enable or disable the rails. Alternatively, all of
them could be factory configured to be part of sequence along with
other voltage rails. Pin name changed to LDOLS_EN when LDOA1
is not factory programmed to always on.
(4) BUCK6_PG should be asserted as well.
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6.3.5 Power Sequencing and VR Control
When a valid power source is available at VSYS (VSYS ≥ 5.6 V), internal analog blocks including LDO5
and LDO3P3 are enabled. For part numbers with LDOA1 set as an always on rail, the PMIC leaves reset
and I2C communication is available as soon as LDO3P3 and LDO5 power goods are confirmed. For part
numbers with LDOA1 set as a general-purpose LDO, the PMIC remains in reset until PMICEN is set high.
Five input pins of the TPS65094x device are driven by a host or by external-controller (EC) defined power
states that transition from one to another in sequence.
Table 6-8 shows various system-level power states. Also, Table 6-9 summarizes a list of active rails in
each power state. The sequencing for the transitions between these states is described in the following
sections.
If a rail is either disabled by I2C or OTP programming, then it is not enabled by the following sequences.
For example, VTT LDO is not enabled for LPDDR4 OTPs.
Table 6-8. Power State and Corresponding I/O Status
SIGNALS TO PMIC
SIGNALS FROM PMIC
POWER
STATE
PMICEN
SLP_S4B(1)
SLP_S3B(1)
SLP_S0B(2)
THERMTRIPB(3)
RSMRSTB PCH_PWROK
G3
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
1
1
0
1
0
1
1
1
1
0
1
1
1
1
0
0
0
1
1
S4/S5
S3
S0iX
S0
(1) When PMIC is first enabled, SLP_S4B and SLP_S3B are to be treated as if they are low (actual state of signal ignored) until the
deassertion of RSMRSTB (L → H).
(2) When PMIC is first enabled, SLP_S0B are to be treated as if they are high (actual state of signal ignored) until the assertion of
PCH_PWROK (L → H).
(3) THERMTRIPB is to be treated as if it is high (actual state of signal ignored) until the deassertion of RSMRSTB (L → H).
Table 6-9. Active Rails in Each Power State
POWER STATE
S4/S5
ACTIVE RAILS
BUCK1 (VNN), BUCK4 (V1P8A), BUCK5 (V1P24A)
S3
Rails in S4/S5 + SWB1_2 (V1P8U)(1), BUCK6 (VDDQ)
S0
Rails in S3 + SWB1_2(2), VTT, BUCK2 (VCCGI), BUCK3 (VCCRAM)
S0iX
Rails in S0 – BUCK1 (VNN), BUCK2 (VCCGI), BUCK3 (VCCRAM), VTT
(1) For LPDDR3 and LPDDR4
(2) For DDR3L
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6.3.5.1 Cold Boot
G3
S5
S5/S4
S3
S0
VSYS
5.6 V
LDO5V/3.3V
LDOA1(b)
Ext. 5V/3.3V VR
PMICEN
T0
BUCK1 (VNN)
BUCK4 (V1P8A)
BUCK5 (V1P24A)
RSMRSTB
T1
T2
T3
∑ 10ms
THERMTRIPB
SLP_S4B
T4
SWB1_2 (V1P8U)(1)
BUCK6 (VDDQ)
SLP_S3B
T5
SLP_S0B
SWB1_2(2)
T6 ∂ 100us
VTT
T7
BUCK3 (VCCRAM)
PCH_PWROK
BUCK2 (VCCGI)
T8 = PWROKDELAY
SET VID by Host
(1) LPDDR3 and LPDDR4
(2) DDR3L
(a) LDOA1 Not —Always On“
(b) LDOA1 —Always On“
Figure 6-7. Cold Boot Sequence
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As VSYS crosses above VSYS_UVLO_5V + VSYS_UVLO+5V_HYS, the cold-boot sequence is initiated by pulling the
PMICEN pin high followed by driving the remaining control pins high in order. SLP_S3B and SLP_S4B
may go high at the same time. SLP_S0B is not defined until the first transition to S0 after RSMRSTB
deassertion. SLP_S0B is defined for all Sx power-state transitions after the first transition to S0.
Table 6-10 lists definitions of the timing delays. These timing delays also apply to the subsequent
sequences. T0 to T10 are factory programmable to 0 ms, 2 ms, 4 ms, 8 ms, 16 ms, 24 ms, 32 ms, or
64 ms.
Table 6-10. Definition of Delays During Cold Boot Sequence
DELAY
T0
DESCRIPTION
TYP VALUE
UNIT
ms
ms
ms
ms
ms
ms
ms
ms
PMICEN to BUCK1 (VNN) enable
PMICEN to BUCK4 (V1P8A) enable
0
4
T1
T2
BUCK4 PG to BUCK5 (V1P24A) enable
0
T3
BUCK5 PG to RSMRSTB deassertion
10
0
T4
SLP_S4B deassertion to SWB1_2 (V1P8U) enable
SLP_S4B deassertion to BUCK6 (VDDQ) enable
Logical AND of BUCK6 PG, SLP_S0B, SLP_S3B, and SLP_S4B to VTT enable
SLP_S0B deassertion to BUCK3 (VCCRAM) enable
T5
4
T6
0
T7
2
Logical AND of all PGs (except BUCK2) to PCH_PWROK assertion. User selectable
from POK_DELAY register.
T8
100
ms
42
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6.3.5.2 Cold OFF
S0
S3
S4/S5
G3
SLP_S0B
SLP_S3B
SLP_S4B
PMICEN
VTT
BUCK1 (VNN)
BUCK3 (VCCRAM)
BUCK2 (VCCGI)
PCH_PWROK
SWB1_2(2)
SWB1_2 (V1P8U)(1)
BUCK6 (VDDQ)
30ms to 60 ms
BUCK4 (V1P8A)
BUCK5 (V1P24A)
RSMRSTB
(1) LPDDR3 and LPDDR4
(2) DDR3L
Figure 6-8. Cold OFF Sequence
Cold OFF sequence is initiated by pulling the SLP_S3B pin low in the S0 state, followed by SLP_S4B,
SLP_S0B, and PMICEN.
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6.3.5.3 Connected Standby Entry and Exit
S0
S0iX
S0
SLP_S0B
1.8 V
SLP_S3B
SLP_S4B
3.3 V
PCH_PWROK
VTT
∂ 100 µs
1.05 V
VID
BUCK1 (VNN)
Host sets VR to 0 V through I2C
0 V
0 V
0 V
∂ 5 ms
BUCK3 (VCCRAM)
SET VID by Host
VID
VID
Host sets VR to 0 V through I2C
BUCK2 (VCCGI)
Figure 6-9. Connected Standby Entry and Exit Sequence
S0 to S0iX (Connected Standby) entry and exit occurs when SLP_S0B is pulled low and high,
respectively. In Connected Standby state, VTT LDO is turned off, but all PGOODs remain asserted.
BUCK1–BUCK3 are not disabled, but instead stop switching while BUCK4–BUCK6 remain in regulation.
SWB1_2 also stays enabled. On entry, BUCK2 and BUCK3 decay to 0 V with their VID registers retaining
the last programmed values to which the BUCKs ramp back up on exit. The host can write to
BUCK2CTRL and BUCK3CTRL registers regardless of the state of the SLP_S0B pin while SLP_S3B and
SLP_S4B are high, which means that BUCK2 and BUCK3 can be changed to ramp to a different voltage
upon exiting S0iX than they had when entering S0iX state. BUCK1 ramps back up to the default value
(1.05 V).
Table 6-11 summarizes status of each VR in Connected Standby state.
Table 6-11. Summary of Rails on Connected Standby Entry and Exit
VR
S0 → S0IX
S0IX → S0
BUCK1 (VNN)
BUCK2 (VCCGI)
0 V
0 V
1.05 V
0 V
BUCK3 (VCCRAM) 0 V
1.05 V
BUCK4 (V1P8A)
BUCK5 (V1P24A)
BUCK6 (VDDQ)
VTT LDO (VTT)
SWB1_2
VID value
VID value
VID value
VID value
OTP dependent
OTP dependent
VDDQ / 2
ON
OFF
ON
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6.3.5.4 S0 to S3 Entry and Exit
Assertion of SLP_S3B (H → L) triggers S3 entry. Deassertion of SLP_S3B causes S3 exit and S0 entry as
depicted in Figure 6-10. On S3 exit, BUCK1–BUCK3 behave exactly the same way as they do on S0iX
exit, which is explained in Section 6.3.5.3, Connected Standby Entry and Exit.
S0
S3
S0
1.8 V
SLP_S4B
SLP_S0B
SLP_S3B
T8
PCH_PWROK
VTT
∂ 100 µs
VID
1.05 V
BUCK1 (VNN)
BUCK3 (VCCRAM)
BUCK2 (VCCGI)
0 V
∂ 5 ms
SET VID by Host
0 V
0 V
SWB1_2(2)
SWB1_2 (V1P8U)(1)
(1) LPDDR3 and LPDDR4
(2) DDR3L
Figure 6-10. S3 Entry and Exit Sequence
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6.3.5.5 S0 to S4/5 Entry and Exit
Assertion of the SLP_S4B (H → L) after the S3 entry pushes the sequence further down to S4/5 where
SWB1_2 (for LPDDR3 or LPDDR4) and BUCK6 are disabled. Any rails not shown are essentially the
same as the S0 to S3 entry and exit case described in Figure 6-11.
S0
S3
S5/S4
S3
S0
1.8 V
SLP_S0B
SLP_S3B
SLP_S4B
PCH_PWROK
BUCK6 (VDDQ)
VTT
T8
T5
∂ 100 µs
SWB1_2(2)
SWB1_2 (V1P8U)(1)
BUCK1 (VNN)
∂ 2 ms
30 ms to 60 ms
VID
1.05 V
0 V
BUCK3 (VCCRAM)
BUCK2 (VCCGI)
∂ 5 ms
SET VID by Host
0 V
0 V
(1) LPDDR3 and LPDDR4
(2) DDR3L
Figure 6-11. S4/5 Entry and Exit Sequence
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6.3.5.6 Emergency Shutdown
When VSYS crosses below VSYS_UVLO_5V, all Power Good pins are deasserted; after 444 ns (nominal) of
delay, all VRs shut down (see Figure 6-12). Upon shutdown, all internal discharge resistors are set to 100
Ω to ensure timely decay of all VR outputs. VSYS crossing above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS and
assertion of PMICEN is required to re-enable the VRs.
Other conditions that cause emergency shutdown are the following:
•
•
•
The die temperature rising above the critical temperature threshold (TCRIT
)
Falling edge of THERMTRIPB
Deassertion of Power Good of any rail or failure to reach power good within 10 ms of enable
(configurable)
5.4 V
VSYS
RSMRSTB
PCH_PWROK
444 ns (nominal with ±1% variation)
BUCKx
LDOAx
SWx
VTT
Figure 6-12. Emergency Shutdown Sequence
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6.4 Device Functional Modes
6.4.1 Off Mode
When power supply at the VSYS pin is less than VSYS_UVLO_5V (5.4-V nominal) + VSYS_UVLO_5V_HYS (0.2-V
nominal), the device is in off mode, where all output rails are disabled. If the supply voltage is greater than
VSYS_UVLO_3V (3.6-V nominal) + VSYS_UVLO_3V_HYS (0.15-V nominal) while it is still less than VSYS_UVLO_5V
+
VSYS_UVLO_5V_HYS, then the internal band-gap reference (VREF pin) along with LDO3P3 are enabled and
regulated at target values.
6.4.2 Standby Mode
When power supply at the VSYS pin rises above VSYS_UVLO_5V + VSYS_UVLO_5V_HYS, the device enters
standby mode, where all internal reference and regulators (LDO3P3 and LDO5) are running, and I2C
interface and PMICEN pin are ready to respond. All default registers defined in Section 6.6, Register
Maps, should now have been loaded from one-time programmable (OTP) memory. Quiescent current
consumption in standby mode is specified in Section 5.5, Electrical Characteristics: Total Current
Consumption.
6.4.3 Active Mode
The device proceeds to active mode when any output rail is enabled either through an input pin as
discussed in Section 6.3.5, Power Sequencing and VR Control, or by writing to the EN bits through I2C.
Output regulation voltage can also be changed by writing to the VID bits defined in Section 6.6, Register
Maps.
6.5 Programming
6.5.1 I2C Interface
The I2C interface is a 2-wire serial interface developed by NXP™ (formerly Philips Semiconductor) (see
the I2C-Bus Specification and user manual, Rev 4, 13 February 2012). The bus consists of a data line
(SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are
pulled high. All the I2C compatible devices connect to the I2C bus through open-drain I/O pins, DATA and
CLK. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master
is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the start and stop of data transfer. A slave device receives and/or transmits data
on the bus under control of the master device.
The TPS65094x device works as a slave and supports the following data transfer modes, as defined in the
I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode
(1 Mbps). The interface adds flexibility to the power supply solution, enabling programming of most
functions to new values depending on the instantaneous application requirements. Register contents are
loaded when VSYS higher than VSYS_UVLO_5V is applied to the TPS65094x device. The I2C interface is
running from an internal oscillator that is automatically enabled when there is an access to the interface.
The data transfer protocol for standard and fast modes are exactly the same, therefore, they are referred
to as F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is
referred to as H/S-mode.
The TPS65094x device supports 7-bit addressing; however, 10-bit addressing and general call address
are not supported. The default device address is 0x5E.
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6.5.1.1 F/S-Mode Protocol
The master initiates data transfer by generating a START condition. The START condition exists when a
high-to-low transition occurs on the SDA line while SCL is high (see Figure 6-13). All I2C-compatible
devices should recognize a START condition.
The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data
condition requires the SDA line to be stable during the entire high period of the clock pulse (see
Figure 6-14). All devices recognize the address sent by the master and compare it to their internal fixed
addresses. Only the slave device with a matching address generates an acknowledge (see Figure 6-15),
by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this
acknowledge, the master identifies that the communication link with a slave has been established.
The master generates further SCL cycles to either transmit data to the slave (R/W bit = 0) or receive data
from the slave (R/W bit = 1). In either case, the receiver must acknowledge the data sent by the
transmitter. An acknowledge signal can either be generated by the master or by the slave, depending on
which one is the receiver. Any 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge
can continue as long as necessary.
To signal the end of the data transfer, the master generates a STOP condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 6-13). This STOP condition releases the bus and
stops the communication link with the addressed slave. All I2C-compatible devices must recognize the
STOP condition. Upon the receipt of a STOP condition, all devices detect that the bus is released, and
they wait for a START condition followed by a matching address.
SDA
SCL
S
P
START
STOP
Condition
Condition
Figure 6-13. START and STOP Conditions
SDA
SCL
Data Valid
Change of Data Allowed
Figure 6-14. Bit Transfer on the I2C Bus
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Data Output at
Transmitter
Not ACK
Data Output at
Receiver
ACK
SCL from Master
1
2
8
9
S
START
Clock pulse for ACK
Condition
Figure 6-15. Acknowledge on the I2C Bus
Generate ACK Signal
SDA
MSB
ACK Signal From Slave
Address
R/W
7
SCL
1
2
8
9
1
2
3-8
9
ACK
ACK
Byte Complete, Interrupt
Within Slave
Clock Line Held Low While
Interrupts Are Serviced
S or Sr
P or Sr
START or
STOP or
Repeated START Condition
Repeated START Condition
Figure 6-16. I2C Bus Protocol
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SCL
SDA
A6
A5
A4
A0 R /W ACK
R7
R6
R5
R0 ACK
0
D7
D6
D5
D0 ACK
0
0
0
START
Slave Address
Register Address
Data
STOP
Figure 6-17. I2C Interface WRITE to TPS65094x in F/S Mode
SCL
SDA
W
R/
A6
A0
ACK
0
R7
R0 ACK
0
A6
A0
ACK D7
0
D0 ACK
W
R/
0
1
0
Master
Drives ACK
and Stop
Slave Drives
the Data
Slave Address
START
Slave Address
Register Address
STOP
Repeated
START
Figure 6-18. I2C Interface READ from TPS65094x in F/S Mode
(Only Repeated START is Supported)
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6.6 Register Maps
Default value of RESERVED R/W bits must not be written to the opposite value.
6.6.1 VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
Figure 6-19. VENDORID Register (offset = 00h) [reset = 0010 0010]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
VENDORID[7]
VENDORID[6]
VENDORID[5]
VENDORID[4]
VENDORID[3]
VENDORID[2]
VENDORID[1]
VENDORID[0]
0
0
1
0
0
0
1
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-12. VENDORID Register Field Descriptions
Bit
Field
Type Reset
00100010
Description
7–0 VENDORID[7:0]
R
Vendor identification register
6.6.2 DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
Figure 6-20. DEVICEID Register (offset = 01h) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
OTP_
VERSION[1]
OTP_
VERSION[0]
PART_
NUMBER[3]
PART_
NUMBER[2]
PART_
NUMBER[1]
PART_
NUMBER[0]
Bit Name
REVID[1]
REVID[0]
TPS650940
TPS650941
TPS650942
TPS650944
TPS650945
Access
0
0
0
0
0
R
0
0
0
0
0
R
0
1
0
0
0
R
0
0
1
0
0
R
1
1
1
1
1
R
0
0
0
1
1
R
0
0
1
0
0
R
0
1
0
0
1
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-13. DEVICEID Register Field Descriptions
Bit
Field
Type Reset
Description
7–6 REVID[1:0]
R
OTP
Silicon revision ID
OTP variation ID
00: A
5–4 OTP_VERSION[1:0]
R
OTP
01: B
10: C
11: D
Device part number ID
1000: TPS650940
1001: TPS650941
1010: TPS650942
1011: TPS650943
1100: TPS650944
1101: TPS650945
1110: TPS650946
1111: TPS650947
0000: TPS650948
3–0 PART_NUMBER[3:0]
R
OTP
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6.6.3 IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
Figure 6-21. IRQ Register (offset = 02h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
VENDOR_
IRQ
Bit Name
RESERVED
RESERVED
RESERVED
ONOFFSRC
RESERVED
RESERVED
DIETEMP
TPS65094x
Access
0
0
0
0
0
0
0
0
R/W
R
R
R
R/W
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-14. IRQ Register Field Descriptions
Bit
Field
Type Reset
Description
Vendor-specific interrupt, indicating fault event occurrence. Asserted when
either one of following conditions occurs:
A. Deassertion of Power Good of any VR
B. Overcurrent detection from BUCK1, BUCK2, BUCK6, or VTT LDO
C. Die temperature crosses over the hot temperature threshold (THOT
7
VENDOR_IRQ
R/W
0
)
D. Die temperature crosses over the critical temperature threshold (TCRIT
)
0: Not asserted
1: Asserted. Host to write 1 to clear.
Asserted when PMIC shuts down.
0: Not asserted.
1: Asserted. Host to write 1 to clear.
3
0
ONOFFSRC
DIETEMP
R/W
R/W
0
0
Die Temp interrupt. Asserted when PMIC die temperature crosses above the
hot temperature threshold (THOT).
0: Not asserted.
1: Asserted. Host to write 1 to clear.
6.6.4 IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
Figure 6-22. IRQ_MASK Register (offset = 03h) [reset = 1111 1111]
Bit
7
6
5
4
3
2
1
0
MDIETEMP
1
Bit Name
TPS65094x
Access
MVENDOR_IRQ
RESERVED
RESERVED
RESERVED
MONOFFSRC
RESERVED
RESERVED
1
1
1
1
1
1
1
R/W
R
R
R
R/W
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-15. IRQ_MASK Register Field Descriptions
Bit
Field
Type Reset
Description
Vendor-specific fault interrupt mask.
0: Not masked
1: Masked
7
MVENDOR_IRQ
R/W
R/W
R/W
1
1
1
PMIC shutdown event interrupt mask
0: Not masked
1: Masked
3
0
MONOFFSRC
MDIETEMP
Die temp interrupt mask.
0: Not masked
1: Masked
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6.6.5 PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
Figure 6-23. PMICSTAT Register (offset = 04h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
SDIETEMP
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-16. PMICSTAT Register Field Descriptions
Bit
Field
Type Reset
Description
PMIC die temperature status.
0
SDIETEMP
R
0
0: PMIC die temperature is below THOT.
1: PMIC die temperature is above THOT
.
6.6.6 OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
Figure 6-24. OFFONSRC Register (offset = 05h) [reset = 0000 0000]
Bit
7
6
5
4
3
COLDOFF
0
2
UVLO
0
1
0
CRITTEMP
0
Bit Name
TPS65094x
Access
RESERVED
RESERVED
RESERVED
RESERVED
OCP
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-17. OFFONSRC Register Field Descriptions
Bit
Field
Type Reset
Description
Set by PMIC cleared by host. Host writes 1 to this bit to clear it.
0 = Cleared
1 = PMIC was shut down by host through PMIC_EN pin.
3
COLDOFF
R/W
R/W
0
0
Set by PMIC cleared by host. Host writes 1 to this bit to clear it.
0 = Cleared
1 = PMIC was shut down due to a UVLO event (VSYS less 5.4 V). The setting
of this bit sets the ONOFFSRC bit in the PMIC_IRQ register.
2
1
UVLO
OCP
Set by PMIC cleared by host. Host writes 1 to this bit to clear it.
0 = Cleared
1 = PMIC shut down due to a power fault event. The setting of this bit sets the
ONOFFSRC bit in the PMIC_IRQ register.
R/W
R/W
0
0
Set by PMIC cleared by host. Host writes 1 to this bit to clear it.
0 = Cleared
1 = PMIC shut down due to the rise of PMIC die temperature above critical
temperature threshold (TCRIT). The setting of this bit sets the ONOFFSRC bit in
the PMIC_IRQ register.
0
CRITTEMP
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6.6.7 BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
Figure 6-25. BUCK1CTRL Register (offset = 20h) [reset = 0011 1000]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
BUCK1_VID[6] BUCK1_VID[5] BUCK1_VID[4] BUCK1_VID[3] BUCK1_VID[2] BUCK1_VID[1] BUCK1_VID[0]
0
0
1
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-18. BUCK1CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
This field sets the BUCK1 regulator output regulation voltage in normal mode.
Default = 1.05 V. Note that 0 V is a valid setting and all Power Goods stay high
when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-3 for full
details.
0111000
(1.05 V)
6–0 BUCK1_VID[6:0]
R/W
6.6.8 BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
Figure 6-26. BUCK2CTRL Register (offset = 21h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
BUCK2_VID[6] BUCK2_VID[5] BUCK2_VID[4] BUCK2_VID[3] BUCK2_VID[2] BUCK2_VID[1] BUCK2_VID[0]
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-19. BUCK2CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
This field sets the BUCK2 regulator output regulation voltage in normal mode.
Default = 0 V. Note that 0 V is a valid setting and all Power Goods must stay
high when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-3 for full
details.
0000000
(0 V)
6–0 BUCK2_VID[6:0]
R/W
6.6.9 BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
Figure 6-27. BUCK3CTRL Register (offset = 23h) [reset = 0001 0001]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
BUCK3_VID[6] BUCK3_VID[5] BUCK3_VID[4] BUCK3_VID[3] BUCK3_VID[2] BUCK3_VID[1] BUCK3_VID[0]
0
0
0
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-20. BUCK3CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
This field sets the BUCK3 regulator output regulation voltage in normal mode.
Default = 1.05 V. Note that 0 V is a valid setting and all Power Goods must stay
high when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-4 for full
details.
0010001
(1.05 V)
6–0 BUCK3_VID[6:0]
R/W
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6.6.10 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = 0011 1101]
Figure 6-28. BUCK4CTRL Register (offset = 25h) [reset = 0011 1101]
Bit
7
6
5
4
3
2
1
0
Bit Name
RESERVED
0
RESERVED
0
RESERVED
1
RESERVED
1
RESERVED
1
RESERVED
1
BUCK4_MODE
0
RESERVED
1
TPS650940,
TPS650941,
TPS65942, and
TPS650944
TPS650945
Access
0
0
1
1
1
1
1
1
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-21. BUCK4CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
This field sets the BUCK4 regulator operating mode.
0 = Automatic mode
1
BUCK4_MODE
R/W
0
1 = Forced PWM mode
6.6.11 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = 0011 1101]
Figure 6-29. BUCK5CTRL Register (offset = 26h) [reset = 0011 1101]
Bit
7
6
5
4
3
2
1
0
Bit Name
RESERVED
0
RESERVED
0
RESERVED
1
RESERVED
1
RESERVED
1
RESERVED
1
BUCK5_MODE
0
RESERVED
1
TPS650940,
TPS650941,
TPS65942, and
TPS650944
TPS650945
Access
0
0
1
1
1
1
1
1
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-22. BUCK5CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
This field sets the BUCK5 regulator operating mode.
0 = Automatic mode
1
BUCK5_MODE
R/W
0
1 = Forced PWM mode
6.6.12 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
Figure 6-30. BUCK6CTRL Register (offset = 27h) [reset = 0011 1101]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BUCK6_MODE
RESERVED
0
0
1
1
1
1
0
1
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-23. BUCK6CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
This field sets the BUCK6 regulator operating mode.
0 = Automatic mode
1
BUCK6_MODE
R/W
0
1 = Forced PWM mode
56
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6.6.13 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
All xx_DIS[1:0] bits automatically set to 00 when the corresponding VR is enabled. Discharge resistance
values listed here are approximate.
Figure 6-31. DISCHCNT1 Register (offset = 40h) [reset = 0101 0101]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
BUCK4_DIS[1] BUCK4_DIS[0] BUCK3_DIS[1] BUCK3_DIS[0] BUCK2_DIS[1] BUCK2_DIS[0] BUCK1_DIS[1] BUCK1_DIS[0]
0
1
0
1
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-24. DISCHCNT1 Register Field Descriptions
Bit
Field
Type Reset
Description
BUCK4 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
7–6 BUCK4_DIS[1:0]
5–4 BUCK3_DIS[1:0]
3–2 BUCK2_DIS[1:0]
1–0 BUCK1_DIS[1:0]
R/W 01
BUCK3 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
R/W 01
R/W 01
R/W 01
BUCK2 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
BUCK1 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
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6.6.14 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
All xx_DIS[1:0] bits automatically set to 00 when the corresponding VR is enabled. Discharge resistance
values listed here are approximate.
Figure 6-32. DISCHCNT2 Register (offset = 41h) [reset = 0101 0101]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
LDOA2_DIS[1] LDOA2_DIS[0]
SWA1_DIS[1]
SWA1_DIS[0]
BUCK6_DIS[1] BUCK6_DIS[0] BUCK5_DIS[1] BUCK5_DIS[0]
0
1
0
1
0
1
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-25. DISCHCNT2 Register Field Descriptions
Bit
Field
Type Reset
Description
LDOA2 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
7–6 LDOA2_DIS[1:0]
5–4 SWA1_DIS[1:0]
3–2 BUCK6_DIS[1:0]
1–0 BUCK5_DIS[1:0]
R/W 01
SWA1 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
R/W 01
R/W 01
R/W 01
BUCK6 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
BUCK5 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
6.6.15 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
All xx_DIS[1:0] bits automatically set to 00 when the corresponding VR is enabled. Discharge resistance
values listed here are approximate.
Figure 6-33. DISCHCNT3 Register (offset = 42h) [reset = 0000 0101]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
RESERVED
RESERVED
RESERVED
SWB1_DIS[1]
SWB1_DIS[0]
LDOA3_DIS[1] LDOA3_DIS[0]
0
0
0
0
0
1
0
1
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-26. DISCHCNT3 Register Field Descriptions
Bit
Field
Type Reset
Description
SWB1 discharge resistance
00: No discharge
01: 100 Ω
10: 200 Ω
11: 500 Ω
3–2 SWB1_DIS[1:0]
1–0 LDOA3_DIS[1:0]
R/W 01
LDOA3 discharge resistance
00: No discharge
01: 100 Ω
R/W 01
10: 200 Ω
11: 500 Ω
58
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6.6.16 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
Programmable Power Good delay for PCH_PWROK pin, measured from the moment when all VRs reach
the regulation range to Power Good assertion.
Figure 6-34. POK_DELAY Register (Offset = 43h) [reset = 0000 0111]
Bit
7
6
5
4
3
2
1
0
PWROKDELAY PWROKDELAY PWROKDELAY
Bit Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
[2]
[1]
[0]
TPS65094x
Access
0
0
0
0
0
1
1
1
R
R
R
R
R
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-27. POK_DELAY Register Field Descriptions
Bit
Field
Type Reset
Description
Programmable delay measured from the moment all rails have reached
regulation voltage to assertion of PCH_PWROK. All values have ±10%
variation.
000 = 2.5 ms
001 = 5.0 ms
010 = 10 ms
011 = 15 ms
100 = 20 ms
101 = 50 ms
110 = 75 ms
111 = 100 ms (default)
2–0 PWROKDELAY[2:0]
R/W 111
6.6.17 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset
= 0000 0000]
Figure 6-35. FORCESHUTDN Register (offset = 91h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
SDWN
0
Bit Name
TPS65094x
Access
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-28. FORCESHUTDN Register Field Descriptions
Bit
Field
Type Reset
Description
Forces reset of the PMIC. The bit is self-clearing.
0 = No action
0
SDWN
R/W
0
1 = PMIC is forced to shut down.
6.6.18 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
Figure 6-36. BUCK4VID Register (offset = 94h) [reset = 0010 1111]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
BUCK4_VID[6] BUCK4_VID[5] BUCK4_VID[4] BUCK4_VID[3] BUCK4_VID[2] BUCK4_VID[1] BUCK4_VID[0]
0
0
1
0
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-29. BUCK4VID Register Field Descriptions
Bit
Field
Type Reset
Description
This field sets the BUCK4 regulator output regulation voltage in normal mode.
Default = 1.80 V. Note that 0 V is a valid setting and all Power Goods must stay
high when VID is set to 0x00. See Table 6-4 for full details.
0101111
(1.80 V)
6–0 BUCK4_VID[6:0]
R/W
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6.6.19 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
Figure 6-37. BUCK5VID Register (Offset = 96h) [reset = 0100 1011]
Bit
7
6
5
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
BUCK5_VID[6] BUCK5_VID[5] BUCK5_VID[4] BUCK5_VID[3] BUCK5_VID[2] BUCK5_VID[1] BUCK5_VID[0]
0
1
0
0
1
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-30. BUCK5VID Register Field Descriptions
Bit
Field
Type Reset
Description
This field sets the BUCK5 regulator output regulation voltage in normal mode.
Default = 1.24 V. Note that 0 V is a valid setting and all Power Goods stay high
when VID is set to 0x00. See Table 6-3 for full details.
1001011
(1.24 V)
6–0 BUCK5_VID[6:0]
R/W
6.6.20 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
Figure 6-38. BUCK6VID Register (Offset = 98h) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
Bit Name
RESERVED
0
BUCK6_VID[6] BUCK6_VID[5] BUCK6_VID[4] BUCK6_VID[3] BUCK6_VID[2] BUCK6_VID[1] BUCK6_VID[0]
TPS650940,
TPS650944 and
TPS650945
0
1
1
1
1
0
1
TPS650941
TPS650942
Access
0
0
1
1
0
0
0
1
0
0
1
1
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-31. BUCK6VID Register Field Descriptions
Bit
Field
Type
Reset
Description
TPS650940,
TPS650944, and
TPS650945: 0111101
(1.1 V)
TPS650941: 1000111
(1.20 V)
This field sets the BUCK6 regulator output regulation voltage in
normal mode. Default = OTP Dependent. Note that 0 V is a valid
setting and all Power Goods stay high when VID is set to 0x00.
See Table 6-3 for full details.
6–0 BUCK6_VID[6:0]
R/W
TPS650942: 1010110
(1.35 V)
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6.6.21 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
LDOA2_SLPVID is used when SLP_S0B is low. Keep LDOA2_SLPVID equal to LDOA2_VID if sleep
functionality is not desired.
Figure 6-39. LDOA2VID Register (offset = 9Ah) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
LDOA2_
SLPVID[1]
LDOA2_
SLPVID[2]
LDOA2_
SLPVID[1]
LDOA2_
SLPVID[0]
Bit Name
LDOA2_VID[3] LDOA2_VID[2] LDOA2_VID[1] LDOA2_VID[0]
TPS650940,
TPS650941,
TPS650942, and
TPS650945
1
0
1
0
1
0
1
0
TPS650944
Access
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-32. LDOA2VID Register Field Descriptions
Bit
Field
Type Reset
Description
TPS650940,
TPS650941,
TPS650942, and
R/W TPS650945: 1010
(1.2 V)
This field sets the LDOA2 regulator output regulation voltage in sleep
mode. Default = OTP Dependent. See Table 6-6 for full details.
7–4 LDOA2_SLPVID[3:0]
TPS650944: 0000
(0.7 V)
TPS650940,
TPS650941,
TPS650942, and
R/W TPS650945: 1010
(1.2 V)
This field sets the LDOA2 regulator output regulation voltage in normal
mode. Default = OTP Dependent. See Table 6-6 for full details.
3–0 LDOA2_VID[3:0]
TPS650944: 0000
(0.7 V)
6.6.22 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
LDOA3_SLPVID is used when SLP_S0B is low. Keep LDOA3_SLPVID equal to LDOA3_VID if sleep
functionality is not desired.
Figure 6-40. LDOA3VID Register (offset = 9Bh) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
LDOA3_
SLPVID[3]
LDOA3_
SLPVID[2]
LDOA3_
SLPVID[1]
LDOA3_
SLPVID[0]
Bit Name
LDOA3_VID[3] LDOA3_VID[2] LDOA3_VID[1] LDOA3_VID[0]
TPS650940,
TPS650941,
TPS650942, and
TPS650945
1
0
1
1
1
0
1
1
TPS650944
Access
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-33. LDOA3VID Register Field Descriptions
Bit
Field
Type Reset
Description
TPS650940, TPS650941,
TPS650942, and
TPS650945: 1011 (1.25 V)
TPS650944: 0000 (0.7 V)
This field sets the LDOA3 regulator output regulation voltage
in sleep mode. Default = OTP Dependent. See Table 6-6 for
full details.
7–4 LDOA3_SLPVID[3:0]
3–0 LDOA3_VID[3:0]
R/W
R/W
TPS650940, TPS650941,
TPS650942, and
TPS650945: 1011 (1.25 V)
TPS650944: 0000 (0.7 V)
This field sets the LDOA3 regulator output regulation voltage
in normal mode. Default = OTP Dependent. See Table 6-6 for
full details.
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6.6.23 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = 0000 0111]
Figure 6-41. VR_CTRL1 Register (offset = 9Ch) [reset = 0000 0111]
Bit
7
6
5
4
3
2
1
0
BUCK3_
DISABLEB
BUCK2_
DISABLEB
BUCK1_
DISABLEB
Bit Name
RESERVED
0
RESERVED
0
BUCK3_MODE BUCK2_MODE BUCK1_MODE
TPS650940,
TPS650941,
TPS650942, and
TPS650944
0
0
0
1
1
1
TPS650945
Access
0
0
1
0
0
1
1
1
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-34. VR_CTRL1 Register Field Descriptions
Bit
Field
Type
Reset
Description
This field sets the BUCK3 regulator operating mode.
0 = Automatic mode
5
BUCK3_MODE
R/W
0
1 = Forced PWM mode
This field sets the BUCK2 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
4
3
BUCK2_MODE
BUCK1_MODE
R/W
R/W
0
0
This field sets the BUCK1 regulator operating mode.
0 = Automatic mode
1 = Forced PWM mode
BUCK3 Active Low Disable bit. Writing 0 to this bit forces BUCK3 to turn off
regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over
2
1
0
BUCK3_DISABLEB
BUCK2_DISABLEB
BUCK1_DISABLEB
R/W
R/W
R/W
1
1
1
BUCK3_EN.
0: Disabled
1: BUCK3 operates normally.
BUCK2 Active Low Disable bit. Writing 0 to this bit forces BUCK2 to turn off
regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over
BUCK2_EN.
0: Disabled
1: BUCK2 operates normally.
BUCK1 Active Low DISABLE bit. Writing 0 to this bit forces BUCK1 to turn off
regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over
BUCK1_EN.
0: Disabled
1: BUCK1 operates normally.
6.6.24 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
Figure 6-42. VR_CTRL2 Register (offset = 9Eh) [reset = 0000 0000]
Bit
7
LDOA2_EN
0
6
SWA1_EN
0
5
BUCK6_EN
0
4
BUCK5_EN
0
3
BUCK4_EN
0
2
BUCK3_EN
0
1
BUCK2_EN
0
0
BUCK1_EN
0
Bit Name
TPS65094x
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-35. VR_CTRL2 Register Field Descriptions
Bit
Field
Type
Reset
Description
LDOA2 Enable bit.
7
LDOA2_EN
R/W
0
0: Enabled if LDOLS_EN = 1
1: Enabled regardless of LDOLS_EN state
SWA1 Enable bit.
6
SWA1_EN
R/W
0
0: Enabled if LDOLS_EN pin or SWA1_EN pin = 1
1: Enabled regardless of LDOLS_EN or SWA1_EN state
62
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Table 6-35. VR_CTRL2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
BUCK6 Enable bit.
5
BUCK6_EN
R/W
0
0: BUCK6 operates normally.
1: Enabled regardless of power sequencing
BUCK5 Enable bit.
4
3
2
1
0
BUCK5_EN
BUCK4_EN
BUCK3_EN
BUCK2_EN
BUCK1_EN
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0: BUCK5 operates normally.
1: Enabled regardless of power sequencing
BUCK4 Enable bit.
0: BUCK4 operates normally.
1: Enabled regardless of power sequencing
BUCK3 Enable bit. BUCK3_DISABLEB has priority over BUCK3_EN.
0: BUCK3 operates normally.
1: Enabled regardless of power sequencing, unless BUCK3_DISABLEB = 0
BUCK2 Enable bit. BUCK2_DISABLEB has priority over BUCK2_EN.
0: BUCK2 operates normally.
1: Enabled regardless of power sequencing, unless BUCK2_DISABLEB = 0
BUCK1 Enable bit. BUCK1_DISABLEB has priority over BUCK1_EN.
0: BUCK1 operates normally.
1: Enabled regardless of power sequencing, unless BUCK1_DISABLEB = 0
6.6.25 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = 0111 0000]
Figure 6-43. VR_CTRL3 Register (Offset = 9Fh) [reset = 0111 0000]
Bit
7
6
5
4
3
2
1
0
SWB1_2_
DISABLEB
SWA1_
DISABLEB
VTT_
DISABLEB
Bit Name
RESERVED
VTT_EN
RESERVED
SWB1_2_EN
LDOA3_EN
TPS650940,
TPS650944, and
TPS650945
0
1
1
0
1
0
0
0
TPS650941 and
TPS650942
0
1
1
1
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 6-36. VR_CTRL3 Register Field Descriptions
Bit
Field
Type
Reset
Description
SWB1_2 Active Low Disable Bit. Writing 0 to this bit forces
SWB1_2 to turn off regardless of status of enable pins (PMICEN,
SLP_Sx). Has priority over SWB1_2_EN.
0: Disabled
6
SWB1_2_DISABLEB
R/W
1
1: SWB1_2 operates normally.
SWA1 Active Low Disable Bit. Writing 0 to this bit forces SWA1 to
turn off regardless of status of enable pins (PMICEN, SLP_Sx).
Has priority over SWA1_EN.
0: Disabled
1: SWA1 operates normally.
5
4
3
SWA1_DISABLEB
VTT_DISABLEB
VTT_EN
R/W
R/W
R/W
1
TPS650940,
VTT_LDO Active Low Disable Bit. Writing 0 to this bit forces
VTT_LDO to turn off regardless of status of enable pins
(PMICEN, SLP_Sx). Has priority over VTT_EN.
0: Disabled
TPS650944, and
TPS650945: 0
TPS650941 and
TPS650942: 1
1: VTT_LDO operates normally.
TPS650940,
VTT_LDO Enable bit. VTT_DISABLEB has priority over VTT_EN.
0: VTT_LDO operates normally.
1: Enabled regardless of power sequencing, unless
VTT_DISABLEB = 0
TPS650944 and
TPS650945: 1
TPS650941 and
TPS650942: 0
SWB1_2_Enable bit. SWB1_2_DISABLEB has priority over
SWB1_2_EN.
1
0
SWB1_2_EN
LDOA3_EN
R/W
R/W
0
0
0: SWB1_2 operates normally.
1: Enabled regardless of power sequencing, unless
SWB1_2_DISABLEB = 0
LDOA3 Enable bit.
0: Enabled if LDOLS_EN = 1
1: Enabled regardless of LDOLS_EN state
6.6.26 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
Figure 6-44. GPO_CTRL Register (offset = A1h) [reset = 0010 0000]
Bit
7
6
5
GPO_LVL
1
4
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-37. GPO_CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
Open-drain GPO output level bit.
0: The pin is driven to logic low.
1: The pin is high impedance.
5
GPO_LVL
R/W
1
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6.6.27 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
Figure 6-45. PWR_FAULT_MASK1 Register (offset = A2h) [reset = 1100 0000]
Bit
7
6
5
4
3
2
1
0
LDOA2_
FLTMSK
SWA1_
FLTMSK
BUCK6_
FLTMSK
BUCK5_
FLTMSK
BUCK4_
FLTMSK
BUCK3_
FLTMSK
BUCK2_
FLTMSK
BUCK1_
FLTMSK
Bit Name
TPS65094x
Access
1
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-38. PWR_FAULT_MASK1 Register Field Descriptions
Bit
Field
Type Reset
Description
LDOA2 Power Fault Mask. When masked, power fault from LDOA2 does not
cause PMIC shutdown.
0: Not masked
1: Masked
7
LDOA2_FLTMSK
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
0
0
0
0
SWA1 Power Fault Mask. When masked, power fault from SWA1 does not
cause PMIC shutdown.
0: Not masked
6
5
4
3
2
1
0
SWA1_FLTMSK
BUCK6_FLTMSK
BUCK5_FLTMSK
BUCK4_FLTMSK
BUCK3_FLTMSK
BUCK2_FLTMSK
BUCK1_FLTMSK
1: Masked
BUCK6 Power Fault Mask. When masked, power fault from BUCK6 does not
cause PMIC shutdown.
0: Not masked
1: Masked
BUCK5 Power Fault Mask. When masked, power fault from BUCK5 does not
cause PMIC shutdown.
0: Not masked
1: Masked
BUCK4 Power Fault Mask. When masked, power fault from BUCK4 does not
cause PMIC shutdown.
0: Not masked
1: Masked
BUCK3 Power Fault Mask. When masked, power fault from BUCK3 does not
cause PMIC shutdown.
0: Not masked
1: Masked
BUCK2 Power Fault Mask. When masked, power fault from BUCK2 does not
cause PMIC shutdown.
0: Not masked
1: Masked
BUCK1 Power Fault Mask. When masked, power fault from BUCK1 does not
cause PMIC shutdown.
0: Not masked
1: Masked
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6.6.28 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
Figure 6-46. PWR_FAULT_MASK2 Register (offset = A3h) [reset = 0011 0111]
Bit
7
6
5
4
3
2
1
0
V5ANA_
FLTMSK
LDOA1_
FLTMSK
VTT_
FLTMSK
SWB1_2_
FLTMSK[1]
SWB1_2_
FLTMSK[0]
LDOA3_
FLTMSK
Bit Name
RESERVED
RESERVED
TPS65094x
Access
0
0
1
1
0
1
1
1
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-39. PWR_FAULT_MASK2 Register Field Descriptions
Bit
Field
Type Reset
Description
V5ANA Power Fault Mask. When masked, power fault from V5ANA does not
cause PMIC shutdown.
0: Not masked
1: Masked
5
V5ANA_FLTMSK
R/W
R/W
R/W
1
1
0
LDOA1 Power Fault Mask. When masked, power fault from LDOA1 does not
cause PMIC shutdown.
0: Not masked
4
3
LDOA1_FLTMSK
VTT_FLTMSK
1: Masked
VTT LDO Power Fault Mask. When masked, power fault from VTT LDO does
not cause PMIC shutdown.
0: Not Masked
1: Masked
SWB1_2 Power Fault Mask. When masked, power fault from SWB1_2 does not
cause PMIC shutdown.
00: Not masked
2–1 SWB1_2_FLTMSK
R/W 11
11: Masked
01-10 = RESERVED
LDOA3 Power Fault Mask. When masked, power fault from LDOA3 does not
cause PMIC shutdown.
0: Not masked
0
LDOA3_FLTMSK
R/W
1
1: Masked
6.6.29 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
Figure 6-47. DISCHCNT4 Register (offset = ADh) [reset = 0110 0001]
Bit
7
6
5
4
VTT_DIS
0
3
2
1
0
Bit Name
TPS65094x
Access
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
1
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-40. DISCHNT4 Register Field Descriptions
Bit
Field
Type Reset
Description
VTT_LDO discharge resistance
0 = No discharge
4
VTT_DIS
R/W
0
1 = 100 Ω
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6.6.30 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
Figure 6-48. LDOA1CTRL Register (offset = AEh) [reset = OTP Dependent]
Bit
7
6
5
4
3
2
1
0
LDOA1_SDWN_
CONFIG
Bit Name
LDOA1_DIS[1] LDOA1_DIS[0]
LDOA1_VID[3] LDOA1_VID[2] LDOA1_VID[1] LDOA1_VID[0]
LDOA1_EN
0
TPS650940,
TPS650941,
TPS650942, and
TPS650945
0
1
1
1
1
1
0
TPS650944
Access
0
1
1
0
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-41. LDOA1CTRL Register Field Descriptions
Bit
Field
Type
Reset
Description
LDOA1 discharge resistance
00: No discharge
01: 100 Ω
7–6 LDOA1_DIS[1:0]
R/W
01
10: 200 Ω
11: 500 Ω
Control for Disabling LDOA1 during Emergency Shutdown
0: LDOA1 will turn off during Emergency Shutdown.
1: LDOA1 will not turn off during Emergency Shutdown as long as
LDOA1_EN = 1.
5
LDOA1_SDWN_CONFIG
R/W
R/W
1
TPS650940,
TPS650941,
TPS650942,
and
TPS650945:
1110 (3.3 V)
TPS650944:
0100 (1.8V)
This field sets the LDOA3 regulator output regulation voltage in normal
mode. Default = OTP Dependent. See Table 6-5 for full details.
4–1 LDOA1_VID[3:0]
TPS650940,
TPS650941,
TPS650942,
and
TPS650945: 0
TPS650944: 1
LDOA1 Enable Bit.
0: Disable
1: Enable
0
LDOA1_EN
R/W
6.6.31 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
Figure 6-49. PG_STATUS1 Register (offset = B0h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
LDOA2_
PGOOD
BUCK6_
PGOOD
BUCK5_
PGOOD
BUCK4_
PGOOD
BUCK3_
PGOOD
BUCK2
_PGOOD
BUCK1_
PGOOD
Bit Name
RESERVED
TPS65094x
Access
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-42. PG_STATUS1 Register Field Descriptions
Bit
Field
Type Reset
Description
LDOA2 Power Good status.
7
LDOA2_PGOOD
R
R
0
0
0: The output is not in target regulation range.
1: The output is in target regulation range.
BUCK6 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
5
BUCK6_PGOOD
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Table 6-42. PG_STATUS1 Register Field Descriptions (continued)
Bit
Field
Type Reset
Description
BUCK5 Power Good status.
4
BUCK5_PGOOD
R
R
R
R
R
0
0
0
0
0
0: The output is not in target regulation range.
1: The output is in target regulation range.
BUCK4 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
3
2
1
0
BUCK4_PGOOD
BUCK3_PGOOD
BUCK2_PGOOD
BUCK1_PGOOD
BUCK3 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
BUCK2 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
BUCK1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
6.6.32 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
Figure 6-50. PG_STATUS2 Register (offset = B1h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
LDO5_
PGOOD
LDOA1_
PGOOD
VTT_
PGOOD
LDOA3_
PGOOD
Bit Name
RESERVED
RESERVED
RESERVED
RESERVED
TPS65094x
Access
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-43. PG_STATUS2 Register Field Descriptions
Bit
Field
Type Reset
Description
LDO5 Power Good status.
5
LDO5_PGOOD
R
R
R
R
0
0
0
0
0: The output is not in target regulation range.
1: The output is in target regulation range.
LDOA1 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
4
3
0
LDOA1_PGOOD
VTT_PGOOD
VTT LDO Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
LDOA3 Power Good status.
0: The output is not in target regulation range.
1: The output is in target regulation range.
LDOA3_PGOOD
6.6.32.1 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
Figure 6-51. PWR_FAULT_STATUS1 Register (offset = B2h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
LDOA2_
PWRFLT
BUCK6_
PWRFLT
BUCK5_
PWRFLT
BUCK4_
PWRFLT
BUCK3_
PWRFLT
BUCK2_
PWRFLT
BUCK1_
PWRFLT
Bit Name
RESERVED
TPS65094x
Access
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Table 6-44. PWR_FAULT_STATUS1 Register Field Descriptions
Bit
Field
Type Reset
Description
This fields indicates that LDOA2 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
7
LDOA2_PWRFLT
R
R
R
R
R
R
R
0
0
0
0
0
0
0
This fields indicates that BUCK6 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
5
4
3
2
1
0
BUCK6_PWRFLT
BUCK5_PWRFLT
BUCK4_PWRFLT
BUCK3_PWRFLT
BUCK2_PWRFLT
BUCK1_PWRFLT
This fields indicates that BUCK5 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
This fields indicates that BUCK4 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
This fields indicates that BUCK3 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
This fields indicates that BUCK2 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
This fields indicates that BUCK1 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
6.6.32.2 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
Figure 6-52. PWR_FAULT_STATUS2 Register (offset = B3h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
LDOA1_
PWRFLT
VTT_
PWRFLT
LDOA3_
PWRFLT
Bit Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
TPS65094x
Access
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-45. PWR_FAULT_STATUS2 Register Field Descriptions
Bit
Field
Type Reset
Description
This fields indicates that LDOA1 has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
4
LDOA1_PWRFLT
R/W
R/W
R/W
0
0
0
This fields indicates that VTT LDO has lost regulation.
0: No Fault.
1: Power fault has occurred. The host to write 1 to clear.
3
0
VTT_PWRFLT
This fields indicates that LDOA3 has lost regulation.
0: No Fault.
LDOA3_PWRFLT
1: Power fault has occurred. The host to write 1 to clear.
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6.6.33 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
Asserted when an internal temperature sensor detects rise of die temperature above the HOT temperature
threshold (THOT). There are five temperature sensors across the die.
Figure 6-53. TEMPHOT Register (offset = B5h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
TOP-RIGHT
_HOT
TOP-LEFT
_HOT
BOTTOM-
RIGHT_HOT
Bit Name
RESERVED
RESERVED
RESERVED
DIE_HOT
VTT_HOT
TPS65094x
Access
0
0
0
0
0
0
0
0
R
R
R
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-46. TEMPHOT Register Field Descriptions
Bit
Field
Type Reset
Description
Temperature of rest of die has exceeded THOT
.
4
DIE_HOT
R/W
R/W
0
0
0: Not asserted.
1: Asserted. The host to write 1 to clear.
Temperature of VTT LDO has exceeded THOT
0: Not asserted.
1: Asserted. The host to write 1 to clear.
.
3
2
VTT_HOT
Temperature of die top-right has exceeded THOT. Top-right corner of die from
top view given pin 1 is in top-left corner.
0: Not asserted.
TOP-RIGHT_HOT
R/W
R/W
R/W
0
0
0
1: Asserted. The host to write 1 to clear.
Temperature of die top-left has exceeded THOT. Top-left corner of die from top
view given pin 1 is in top-left corner.
0: Not asserted.
1
0
TOP-LEFT_HOT
1: Asserted. The host to write 1 to clear.
Temperature of die bottom-right has exceeded THOT. Bottom-right corner of die
from top view given pin 1 is in top-left corner.
0: Not asserted.
BOTTOM-RIGHT_HOT
1: Asserted. The host to write 1 to clear.
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7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application Information
7.2 Typical Application
For a detailed description about application usage, refer to the TPS65094x Design Guide and to the
TPS65094x Schematic Checklist, Layout Checklist, and ILIM Calculator Tool. The TPS65094x can be
used in several different applications from computing, industrial interfacing, and much more. This section
describes the general application information and provides a more detailed description on the TPS65094x
device that powers the Intel Apollo Lake system. The functional block diagram for the device is shown in
Figure 7-1, which outlines the typical external components necessary for proper device functionality.
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Optional(a)
Required(b)
LDO5V
VSYS
BOOT1
DRVH1
EC
LDOA1
1.35 V to 3.3 V
1.8 V(b)
PMICEN
SLP_S3B
SLP_S4B
BUCK1
Default: 1V
SW1
200 mA
VNN
VSET
Typical
Application
Usage:
0.5 V to 1.45 V
(DVS)
DRVL1
EN
EN
SLP_S0B
Control
FBVOUT1
LDOLS_EN(a)
Inputs
PGNDSNS1
SWA1_EN(b)
5 A
ILIM1
THERMTRIPB
V1P8A
VSYS
BOOT2
DRVH2
CLK
I2C CTRL
BUCK2
Default: 0V
SW2
SoC
DATA
VCCGI
VSET
EN
V1P8A
DRVL2
Typical
Application
Usage:
Control
Outputs
FBVOUT2
0.5 V to 1.45 V
(DVS)
PGNDSNS2
IRQB
21 A
PCH_PWROK
RSMRSTB
PROCHOT
GPO
FBGND2
ILIM2
Internal
Interrupt
Events
BUCK5V
PVIN3
LX3
TEST CTRL
OTP
VSET
EN
BUCK3
Default: 1.05 V
3 A
VCCRAM
FB3
REGISTERS
<PGND_BUCK3>
BUCK5V
BUCK5V
PVIN4
LX4
VSYS
VSYS
BUCK4
Default: 1.8 V
2 A
Digital Core
VSET
EN
V1P8A
V5ANA
LDO5
BUCK5V
FB4
<PGND_BUCK4>
LDO5V
nPUC
LDO3P3
VREF
REFSYS
PVIN5
LX5
VSET
EN
BUCK5
Default: 1.24 V
2 A
V1P24A
FB5
<PGND_BUCK5>
AGND
VSYS
Thermal
monitoring
BOOT6
DRVH6
Thermal shutdown
SW6
BUCK6
Default: OTP
Dependent
7 A
VDDQ
VSET
EN
DRVL6
FBVOUT6
PGNDSNS6
ILIM6
PVINVTT
VTT
VTT_LDO
½ × VDDQ
ILIM set by OTP
VTT
EN
VTTFB
LDOA2
0.7 V to 1.5 V
600 mA
LDOA3
0.7 V to 1.5 V
600 mA
LOAD SWA1
300 mA
LOAD SWB1
400 mA
LOAD SWB2
400 mA
V1P8A(1)
0.5 V to 3.3 V(2)
0.5 V to 3.3 V
Dashed connections optional.
Refer to Pin Attributes for
connection if unused.
(1) LPDDR3 and LPDDR4
(2) DDR3L
(a) LDOA1 Not —Always On“
(b) LDOA1 —Always On“
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. Functional Block Diagram
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7.2.1 Design Requirements
The TPS65094x device requires decoupling capacitors on the supply pins. Follow the values for
recommended capacitance on these supplies given in the Specifications section. The controllers,
converter, LDOs, and some other features can be adjusted to meet specific application requirements.
Section 7.2.2, Detailed Design Procedure, describes how to design and adjust the external components to
achieve desired performance.
7.2.2 Detailed Design Procedure
7.2.2.1 Controller Design Procedure
Designing the controller can be divided into the following steps:
1. Design the output filter.
2. Select the FETs.
3. Select the bootstrap capacitor.
4. Select the input capacitors.
5. Set the current limits.
Figure 7-2 shows a diagram of the controller. Controllers BUCK1, BUCK2, and BUCK6 require a 5-V
supply and capacitors at their corresponding DRV5V_x_x pins. For most applications, the DRV5V_x_x
input must come from the LDO5P0 pin to ensure uninterrupted supply voltage; a 2.2-µF, X5R, 20%, 10-V,
or similar capacitor must be used for decoupling.
VSYS
DRVHx
BOOT1
LDO5V
DRV5V_x_x
VOUT
LOUT
SWx
COUT
Controller
DRVLx
PGNDSNSx
Control
from SOC
FBVOUTx
RILIM
ILIMx
<FBGND2>(1)
PowerPADTM
Copyright © 2017, Texas Instruments Incorporated
Figure 7-2. Controller Diagram
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7.2.2.1.1 Selecting the Output Capacitors
TI recommends using ceramic capacitors with low ESR values to provide the lowest output voltage ripple.
The output capacitor requires either an X7R or an X5R dielectric. Capacitors with Y5V or Z5U dielectrics
display a wide variation in capacitance over temperature and become resistive at high frequencies.
At light load currents, the controller operates in PFM mode, and the output voltage ripple is dependent on
the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize
the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage
ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of
ceramic capacitors drops with increasing DC bias voltage.
For the output capacitors of the BUCK controllers, TI recommends placing small ceramic capacitors
between the inductor and load with many vias to the PGND plane. This solution typically provides the
smallest and lowest cost solution available for DCAP2 controllers.
To meet the transient specifications, the output capacitance must equal or exceed the minimum
capacitance listed in the electrical characteristics table for BUCK1, BUCK2, and BUCK6 (assuming quality
layout techniques are followed). See Section 5.7, Electrical Characteristics: Buck Controllers.
7.2.2.1.2 Selecting the Inductor
An inductor must be placed between the external FETs and the output capacitors. Together, the inductor
and output capacitors make the double-pole that contributes to stability. In addition, the inductor is
responsible for the output ripple, efficiency, and transient performance. When the inductance increases,
the ripple current decreases, which typically results in an increased efficiency. However, with an increase
in inductance, the transient performance decreases. Finally, the inductor selected must be rated for
appropriate saturation current, core losses, and DC resistance (DCR).
Equation 3 shows the calculation for the recommended inductance for the controller.
VOUT ì (V - VOUT
IN ì fsw ì IOUT(MAX) ì KIND
)
IN
L =
V
where
•
•
•
•
•
VOUT is the typical output voltage.
VIN is the typical input voltage.
fSW is the typical switching frequency.
IOUT(MAX) is the maximum load current.
KIND is the ratio of ILripple to the IOUT(MAX). For this application, TI recommends that KIND is set to a value
from 0.2 to 0.4.
(3)
With the chosen inductance value and the peak current for the inductor in steady state operation, IL(max)
can be calculated using Equation 4. The rated saturation current of the inductor must be higher than the
IL(MAX) current.
(V -VOUT ) ì VOUT
2 ì VIN ì fsw ì L
IN
IL(MAX) = IOUT(MAX)
+
(4)
Following the previous equations, Table 7-1 lists the preferred inductor selected for the controllers..
Table 7-1. Recommended Inductors
MANUFACTURER
Cyntec
PART NUMBER
PIMB061H
VALUE
0.47 µH
0.22 µH
SIZE
HEIGHT
1.8 mm
2.4 mm
6.8 mm × 7.3 mm
6.8 mm × 7.3 mm
Cyntec
PIMB062D
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7.2.2.1.3 Selecting the FETs
This controller is designed to drive two NMOS FETs. Typically, lower RDSON values are better for
improving the overall efficiency of the controller. However, higher gate-charge thresholds result in lower
efficiency, so the two must be balanced for optimal performance. As the RDSON for the low-side FET
decreases, the minimum current limit increases; therefore, ensure selection of the appropriate values for
the FETs, inductor, output capacitors, and current-limit resistor. TI's CSD87331Q3D, CSD87381P, and
CSD87588N devices are recommended for the controllers, depending on the required maximum current.
7.2.2.1.4 Bootstrap Capacitor
To ensure the internal high-side gate drivers are supplied with a stable low-noise supply voltage, a
capacitor must be connected between the SWx pins and the respective BOOTx pins. TI recommends
placing ceramic capacitors with the value of 0.1 µF for the controllers. During testing, a 0.1-µF, size 0402,
10-V capacitor is used for the controllers.
TI recommends reserving a small resistor in series with the bootstrap capacitor in case the turnon and
turnoff of the FETs must be slowed to reduce voltage ringing on the switch node, which is a common
practice for controller design.
7.2.2.1.5 Selecting the Input Capacitors
Due to the nature of the switching controller with a pulsating input current, a low-ESR input capacitor is
required for best input-voltage filtering and also for minimizing the interference with other circuits caused
by high input-voltage spikes. For the controller, a typical 2.2-µF capacitor can be used for the DRV5V_x_x
pin to handle the transients on the driver. For the FET input, 10 µF of input capacitance (after derating) is
recommended for most applications. To achieve the low-ESR requirement, a ceramic capacitor is
recommended. However, the voltage rating and DC-bias characteristic of ceramic capacitors must be
considered. For better input-voltage filtering, the input capacitor can be increased without any limit.
7.2.2.1.5.1 Setting the Current Limit
The current-limiting resistor value must be chosen based on Equation 1.
NOTE
Use the correct value for the ceramic capacitor capacitance after derating to achieve the
recommended input capacitance.
TI recommends placing a ceramic capacitor as close as possible to the FET across the respective VSYS
and PGND pins of the FETs. The preferred capacitors for the controllers are two Murata
GRM21BR61E226ME44: 22 µF, 0805, 25 V, ±20%, or similar capacitors.
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7.2.2.2 Converter Design Procedure
Designing the converter has only the following two steps:
1. Design the output filter.
2. Select the input capacitors.
The converter must be supplied by a 5-V source. Figure 7-3 shows a diagram of the converter.
LOUT
VOUT
PVINx
LXx
VIN_BUCK345_ANA
CIN
FBx
Converter
Control from SOC
Copyright © 2017, Texas Instruments Incorporated
Figure 7-3. Converter Diagram
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7.2.2.2.1 Selecting the Inductor
An inductor must be placed between the external FETs and the output capacitors. Together, the inductor
and output capacitors form a double-pole in the control loop that contributes to stability. In addition, the
inductor is responsible for the output ripple, efficiency, and transient performance. When the inductance
increases, the ripple current decreases, which typically results in an increase in efficiency. However, with
an increase in inductance, the transient performance decreases. Finally, the inductor selected must be
rated for appropriate saturation current, core losses, and DCR.
NOTE
Internal parameters for the converters are optimized for a 0.47-µH inductor; however, it is
possible to use other inductor values as long as they are chosen carefully and thoroughly
tested.
Equation 5 shows the calculation for the recommended inductance for the converter.
VOUT ì (V - VOUT
IN ì fsw ì IOUT(MAX) ì KIND
)
IN
L =
V
where
•
•
•
•
•
VOUT is the typical output voltage.
VIN is the typical input voltage.
fSW is the typical switching frequency.
IOUT(MAX) is the maximum load current.
KIND is the ratio of ILripple to the IOUT(MAX). For this application, TI recommends that KIND is set to a value
from 0.2 to 0.4.
(5)
With the chosen inductance value and the peak current for the inductor in steady state operation, IL(MAX)
can be calculated using Equation 6. The rated saturation current of the inductor must be higher than the
IL(MAX) current.
(V -VOUT ) ì VOUT
2 ì VIN ì fsw ì L
IN
IL(MAX) = IOUT(MAX)
+
(6)
Following these equations, Table 7-2 lists the preferred inductor selected for the converters.
Table 7-2. Recommended Inductors
MANUFACTURER
PART NUMBER
VALUE
SIZE
HEIGHT
Cyntec
PIFE32251B-R47MS
0.47 µH
3.2 mm × 2.5 mm
1.2 mm
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7.2.2.2.2 Selecting the Output Capacitors
TI recommends using ceramic capacitors with low-ESR values are recommended to provide the lowest
output voltage ripple. The output capacitor requires either an X7R or an X5R rating. Y5V and Z5U
capacitors, aside from the wide variation in capacitance overtemperature, become resistive at high
frequencies.
At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on
the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize
the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage
ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of
ceramic capacitors drops with increasing DC-bias voltage.
For the output capacitors of the BUCK converters, TI recommends placing small ceramic capacitors
between the inductor and load with many vias to the PGND plane. This solution typically provides the
smallest and lowest-cost solution available for DCAP2 controllers.
To meet the transient specifications, the output capacitance must equal or exceed the minimum
capacitance listed for BUCK3, BUCK4, and BUCK5 (assuming quality layout techniques are followed).
7.2.2.2.3 Selecting the Input Capacitors
Due to the nature of the switching converter with a pulsating input current, a low-ESR input capacitor is
required for best input-voltage filtering and for minimizing the interference with other circuits caused by
high input-voltage spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for
most applications. A ceramic capacitor is recommended to achieve the low-ESR requirement. However,
the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. For better input-
voltage filtering, the input capacitor can be increased without any limit.
NOTE
Use the correct value for the ceramic capacitor capacitance after derating to achieve the
recommended input capacitance.
The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10 µF, 0402, 10 V,
±20%, or similar capacitor.
7.2.2.3 LDO Design Procedure
The VTT LDO must handle the fast load transients from the DDR memory for termination. Therefore, TI
recommends using ceramic capacitors to maintain a high amount of capacitance with low ESR on the VTT
LDO outputs and inputs. The preferred output capacitors for the VTT LDO are the GRM188R60J226MEA0
from Murata (22 µF, 0603, 6.3 V, ±20%, or similar capacitors). The preferred input capacitor for the VTT
LDO is the CL05A106MP5NUNC from Samsung (10 µF, 0402, 10 V, ±20%, or similar capacitor).
The remaining LDOs must have input and output capacitors chosen based on the values in Section 5.9,
Electrical Characteristics: LDOs.
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7.2.3 Application Curves
Figure 7-4. BUCK2 Controller Load Transient
Figure 7-5. BUCK3 Converter Load Transient
Figure 7-7. BUCK3 Converter Start-Up
Figure 7-6. BUCK2 Controller Start-Up
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7.3 Specific Application for TPS650944
For the TPS650944 device, if register reset is desired when the PMICEN pin is pulled low, an alternate
reset condition can be used. There are two simple options. The first option is to write 1 to the SDWN bit in
the FORCESHUTDN register (see Section 6.6.17, FORCESHUTDN: Force Emergency Shutdown Control
Register) to force power rails to turn off and reset all registers. The second option is to use the falling
edge detection of the THERMTRIPB pin to trigger the device reset. In this case, when the PMICEN pin is
pulled low, the THERMTRIPB pin on PMIC should be pulled low simultaneously, which can be done in
several ways. One approach is to connect a low-voltage Schottky diode between the PMICEN and
THERMTRIPB pins. Because the THERMTRIPB SoC pin is push-pull configured, a second diode is
needed to prevent shorting the SoC pin to GND. An example can be seen in Figure 7-8. Both diodes must
have a forward voltage below PMIC VIL (0.4 V) at the appropriate current. Another approach is to route the
THERMTRIPB signal from SoC through the EC and tie PMICEN and THERMTRIPB together at the PMIC.
PMICEN
EC
LDOA1
PMIC
10 kꢀ
THERMTRIPB
SoC
NOTE: Not applicable if LDOA1 is not configured to "Always On"
Figure 7-8. PMICEN and THERMTRIPB Connection Option for LDOA1 "Always On" Spins
For the TPS650944 device, if both the PVINSWA1 and PVINSWB1_B2 pins are tied to 2.5 V, LDOA2 and
LDOA3 will turn on if all VRs and load switches are enabled and have released their Power Good signals.
To avoid LDOA2 and LDOA3 turning on unexpectedly, TI recommends using voltages other than 2.5 V on
both SWA1 and SWB1_2.
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7.4 Do's and Don'ts
•
Connect the LDO5V output to the DRV5V_x_x inputs for situations where an external 5-V supply is not
initially available or is not available the entire time PMIC is on. If the external 5-V supply is always
present, then DRV5V_x_x can be directly connected to remove the V5ANA-to-LDO5P0 load switch
RDSON
.
•
•
Ensure that none of the control pins are potentially floating.
Include 0-Ω resistors on the DRVH and BOOT pins of controllers on prototype boards, which allows for
slowing the controllers if the system is unable to handle the noise generated by the large switching or if
switching voltage is too large due to layout.
•
•
Do not connect the V5ANA power input to a different source other than PVINx. A mismatch here
causes reference circuits to regulate incorrectly.
Do not supply the V5ANA power input before the VSYS. Reference biasing of the internal FETs may
turn on the HS FET and pass the input to the output until VSYS is biased.
8 Power Supply Recommendations
This device is designed to work with several different input voltages. The minimum voltage on the VSYS
pin is 5.6 V for the device to start up; however, this is a low-power rail. The input to the FETs must be
from 5.4 V to 21 V as long as the proper BOM choices are made. Input to the converters must be
5 V. For the device to output maximum power, the input power must be sufficient. For the controllers, VIN
must be able to supply up to 5 A (typically), though less is acceptable with higher voltages or less usage.
For the converters, PVINx must be able to supply 2 A (typically).
A best practice here is to determine power usage by the system and back-calculate the necessary power
input based on expected efficiency values.
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Power Supply Recommendations
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9 Layout
9.1 Layout Guidelines
For a detailed description regarding layout recommendations, refer to the TPS65094x Design Guide and
to the TPS65094x Schematic Checklist, Layout Checklist, and ILIM Calculator Tool. For all switching
power supplies, the layout is an important step in the design, especially at high peak currents and high
switching frequencies. If the layout is not carefully done, the regulator can have stability problems and EMI
issues. Therefore, use wide and short traces for the main current path and for the power ground tracks.
The input capacitors, output capacitors, and inductors must be placed as close as possible to the device.
Use a common-ground node for power ground and use a different, isolated node for control ground to
minimize the effects of ground noise. Connect these ground nodes close to the AGND pin by one or two
vias. Use of the design guide is highly encouraged in addition to the following list of other basic
requirements:
•
•
Do not allow the AGND, PGNDSNSx, or FBGND2 to connect to the thermal pad on the top layer.
To ensure proper sensing based on FET RDSON, PGNDSNSx must not connect to PGND until very
close to the PGND pin of the FET.
•
•
All inductors, input/output capacitors, and FETs for the converters and controller must be on the same
board layer as the device.
To achieve the best regulation performance, place feedback connection points near the output
capacitors and minimize the control feedback loop as much as possible.
•
•
Bootstrap capacitors must be placed close to the device.
The input and output capacitors of the internal reference regulators must be placed close to the device
pins.
•
Route DRVHx and SWx as a differential pair. Ensure that there is a PGND path routed in parallel with
DRVLx, which provides optimal driver loops.
9.2 Layout Example
BUCK2
VREF Capacitor
VTT
BUCK6
BUCK3
BUCK5
BUCK4
BUCK1
Figure 9-1. EVM Layout Example With All Components on the Top Layer
82
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10 器件和文档支持
10.1 器件支持
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构
成此类产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
10.1.2 开发支持
相关开发支持，请参见以下文档：
TPS65094x 原理图检查清单、布局检查清单和 ILIM 计算器工具
10.2 文档支持
10.2.1 相关文档
请参阅如下相关文档：
•
•
TPS65094x 设计指南
TPS65094x 评估模块
10.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周
接收产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster
collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge,
explore ideas and help solve problems with fellow engineers.
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信
息。
10.5 商标
D-CAP2, D-CAP, E2E are trademarks of Texas Instruments.
超极本, Intel are trademarks of Intel Corporation.
NXP is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
10.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
10.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
11 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通
知，且不会对此文档进行修订。如欲获取此产品说明书的浏览器版本，请参阅左侧的导航。
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11.1 Package Option Addendum
11.1.1 Packaging Information
Package
Package
Drawing
Package
Qty
Lead/Ball
Finish(3)
(1)
(2)
(4)
(6)
Orderable Device
TPS650945RSKR
TPS650945RSKT
Status
Pins
64
Eco Plan
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking(5)
T650945
Type
Green (RoHS
& no Sb/Br)
ACTIVE
ACTIVE
VQFN
VQFN
RSK
2000
250
CU NIPDAU
CU NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
PG1.0
Green (RoHS
& no Sb/Br)
T650945
PG1.0
RSK
64
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
space
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest
availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the
requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified
lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used
between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by
weight in homogeneous material)
space
(3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the
finish value exceeds the maximum column width.
space
(4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
space
(5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device
space
(6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief
on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third
parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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11.1.2 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
Reel
Diameter
(mm)
Reel
Width W1
(mm)
Package
Type
Package
Drawing
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
Device
Pins
SPQ
TPS650945RSKR
TPS650945RSKT
VQFN
VQFN
RSK
RSK
64
64
2000
250
330.0
180.0
16.4
16.4
8.3
8.3
8.3
8.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
Device
Package Type
VQFN
Package Drawing Pins
SPQ
2000
250.0
Length (mm) Width (mm)
Height (mm)
38.0
TPS650945RSKR
TPS650945RSKT
RSK
RSK
64
64
367.0
210.0
367.0
185.0
VQFN
35.0
86
机械、封装和可订购信息
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产品主页链接: TPS65094
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS650940A0RSKR
TPS650940A0RSKT
TPS650941A0RSKR
TPS650941A0RSKT
TPS650942A0RSKR
TPS650942A0RSKT
TPS650944A0RSKR
TPS650944A0RSKT
TPS650945A0RSKR
TPS650945A0RSKT
TPS650947A0RSKR
TPS650947A0RSKT
ACTIVE
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
64
64
64
64
64
64
64
64
64
64
64
64
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
2000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
T650940A0
PG1.0
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
T650940A0
PG1.0
T650941A0
PG1.0
T650941A0
PG1.0
T650942A0
PG1.0
T650942A0
PG1.0
T650944A0
PG1.0
T650944A0
PG1.0
T650945A0
PG1.0
T650945A0
PG1.0
T650947A0
PG1.0
T650947A0
PG1.0
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS650940A0RSKR
TPS650940A0RSKR
TPS650940A0RSKT
TPS650940A0RSKT
TPS650941A0RSKR
TPS650941A0RSKR
TPS650941A0RSKT
TPS650941A0RSKT
TPS650942A0RSKR
TPS650942A0RSKT
TPS650944A0RSKR
TPS650944A0RSKR
TPS650944A0RSKT
TPS650944A0RSKT
TPS650945A0RSKR
TPS650945A0RSKT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
2000
2000
250
330.0
330.0
180.0
180.0
330.0
330.0
180.0
180.0
330.0
180.0
330.0
330.0
180.0
180.0
330.0
180.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
8.3
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
1.1
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
250
2000
2000
250
250
2000
250
2000
2000
250
250
2000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS650947A0RSKR
TPS650947A0RSKT
TPS650947A0RSKT
VQFN
VQFN
VQFN
RSK
RSK
RSK
64
64
64
2000
250
330.0
180.0
180.0
16.4
16.4
16.4
8.3
8.3
8.3
8.3
8.3
8.3
1.1
1.1
1.1
12.0
12.0
12.0
16.0
16.0
16.0
Q2
Q2
Q2
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS650940A0RSKR
TPS650940A0RSKR
TPS650940A0RSKT
TPS650940A0RSKT
TPS650941A0RSKR
TPS650941A0RSKR
TPS650941A0RSKT
TPS650941A0RSKT
TPS650942A0RSKR
TPS650942A0RSKT
TPS650944A0RSKR
TPS650944A0RSKR
TPS650944A0RSKT
TPS650944A0RSKT
TPS650945A0RSKR
TPS650945A0RSKT
TPS650947A0RSKR
TPS650947A0RSKT
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
VQFN
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
RSK
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
2000
2000
250
367.0
367.0
210.0
210.0
367.0
367.0
210.0
210.0
367.0
210.0
367.0
367.0
210.0
210.0
367.0
210.0
367.0
210.0
367.0
367.0
185.0
185.0
367.0
367.0
185.0
185.0
367.0
185.0
367.0
367.0
185.0
185.0
367.0
185.0
367.0
185.0
35.0
38.0
35.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
35.0
38.0
35.0
38.0
35.0
250
2000
2000
250
250
2000
250
2000
2000
250
250
2000
250
2000
250
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-May-2023
Device
TPS650947A0RSKT
Package Type Package Drawing Pins
VQFN RSK 64
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
250
Pack Materials-Page 4
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