TPS65110_14 [TI]

LTPS-LCD BIAS POWER SUPPLY, TRIPLE CHARGE PUMP;
TPS65110_14
型号: TPS65110_14
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

LTPS-LCD BIAS POWER SUPPLY, TRIPLE CHARGE PUMP

CD
文件: 总15页 (文件大小:229K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
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SLVS495 − SEPTEMBER 2003  
FEATURES  
DESCRIPTION  
D
Complete LTPS-LCD Bias Solution  
Triple Output Charge Pump Providing  
at 16 mA, V at 2 mA, V at 1 mA  
The TPS65110/11 is a very compact power supply  
solution providing the three voltages required by many  
LTPS LCD displays.  
D
V
CC  
DD  
SS  
D
D
D
D
D
D
D
D
D
2.4 V to 5.5 V Input Voltage Range  
Fixed Output Voltages of 3.3 V, 7.5 V, 2.7 V  
or 5.0 V, 9.0 V, 3.0 V  
50 µA Typical Quiescent Current  
Less Than 1 µA Shutdown Current  
All three regulated outputs are generated using a charge  
pump topology.  
The VCC charge pump provides precise, high efficiency,  
and very low ripple dc/dc conversion for the LCD analog  
power. The VCC boost ratio (x1.0, x1.33, x1.5, and x2.0)  
is automatically set based on input and output voltage  
conditions. The VCC output assures 16 mA of current by  
using three 0.22-µF flying capacitors. If the required output  
current is smaller, smaller capacitors can be applied.  
Ultra-Low Ripple (V  
= 5 mV,  
CC  
Typical at 5 mA)  
Autonomous Boost for V  
Supply  
CC  
1.5% Accuracy on Fixed VCC Output Voltage  
Sequential Power Control  
24-Pin QFN Package (4 x 4)  
The VDD charge pump provides a higher positive voltage,  
and the VSS charge pump provides the negative output  
voltage. Power up/down sequences are internally set and  
are secured even in cases of sudden and abnormal VIN  
drop.  
APPLICATIONS  
D
D
D
Small Form LTPS−LCD Displays  
PDAs, Pocket PCs  
Smart Phones  
One of the most significant features of the TPS65110/11  
is the ultra-low output voltage ripple, as the VCC charge  
pump achieves 5-mV output ripple voltage.  
AVAILABLE OUTPUT VOLTAGE OPTIONS  
APPLICATION CIRCUIT FOR TPS65111  
PART NUMBER  
TPS65110RGE  
TPS65111RGE  
V
V
V
V
DD  
BOOST  
X3  
CC  
DD  
SS  
0.1 µF  
3.3 V  
5.0 V  
7.5 V  
9.0 V  
−2.7 V  
−3.0 V  
X2  
VIN  
2.4 V to 5.5 V  
VSS  
−3 V, 1 mA  
CSP CSN  
(1)  
VIN  
VSS  
4.7 µF  
TPS65111  
2.2 µF  
CCP1  
CDP1  
0.22 µF  
0.22 µF  
0.22 µF  
0.1 µF  
0.1 µF  
0.1 µF  
CCN1  
CCP2  
CDN1  
CDP2  
CCN2  
CCP3  
CDN2  
CDP3  
CCN3  
VCC  
CDN3  
VDD  
VDD  
9 V, 2 mA  
VCC  
5 V, 16 mA  
2.2 µF  
1 µF  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢁꢑ ꢎ ꢊꢒ ꢉ ꢀꢌ ꢎꢘ ꢊ ꢍꢀꢍ ꢙꢚ ꢛꢜ ꢝ ꢞꢟ ꢠꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠꢙ ꢜꢚ ꢨꢟ ꢠꢤꢩ ꢁꢝ ꢜꢨꢣ ꢢꢠꢡ  
ꢢ ꢜꢚ ꢛꢜꢝ ꢞ ꢠꢜ ꢡ ꢥꢤ ꢢ ꢙ ꢛꢙ ꢢ ꢟ ꢠꢙ ꢜꢚꢡ ꢥ ꢤꢝ ꢠꢪꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢀꢤꢫ ꢟꢡ ꢌꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ ꢡꢠ ꢟꢚꢨ ꢟꢝ ꢨ ꢬ ꢟꢝ ꢝ ꢟ ꢚꢠꢭꢩ  
ꢁꢝ ꢜ ꢨꢣꢢ ꢠ ꢙꢜ ꢚ ꢥꢝ ꢜ ꢢ ꢤ ꢡ ꢡ ꢙꢚ ꢮ ꢨꢜ ꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ ꢠꢤ ꢡꢠꢙ ꢚꢮ ꢜꢛ ꢟꢧ ꢧ ꢥꢟ ꢝ ꢟꢞ ꢤꢠꢤ ꢝ ꢡꢩ  
Copyright 2003, Texas Instruments Incorporated  
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SLVS495 − SEPTEMBER 2003  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during  
storage or handling to prevent electrostatic damage to the MOS gates.  
ABSOLUTE MAXIMUM RATINGS  
(1)  
over operating free-air temperature range unless otherwise noted  
UNIT  
−0.3 V to 7.0 V  
−0.3 V to VIN + 0.3 V  
46°C/W  
(2)  
Supply voltage at VIN  
(2)  
Input voltage at EN, CLK, DATA  
(3)  
Power dissipation  
Virtual operation junction temperature, T  
Storage temperature range  
−40°C to 125°C  
−65°C to 150°C  
260°C  
J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds  
(1)  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All voltage values are with respect to network ground terminal.  
(2)  
(3)  
The package thermal impedance is calculated in accordance with JESD 51−5.  
CHANNEL PERFORMANCE OVERVIEW  
CHANNEL  
Output Voltage Control  
Boost Ratio  
VCC  
VDD  
Regulated  
x2 or x3  
Fixed  
VCC  
VSS  
Regulated  
x−1  
Regulated  
x1; x1.333; x1.5; x2  
Boost setting  
Autonomous Boost  
Fixed  
VCC  
1 mA  
3%  
Power Supply  
Output Current  
Accuracy  
VIN  
16 mA  
1.5%  
4
2 mA  
3%  
Num of Ext CAP  
4
2
RECOMMENDED OPERATING CONDITIONS  
MIN NOM  
2.4  
MAX  
5.5  
UNIT  
Input voltage range, VIN  
V
V
V
V
Main output voltage, V  
CC  
3.0  
5.2  
Positive output voltage range, V  
DD  
6.5  
10  
Negative output voltage range, V  
SS  
−4.5  
4.7  
−2.4  
VIN input capacitor(C )  
µꢟ  
µꢟ  
µꢟ  
µꢟ  
µꢟ  
µꢟ  
i
V
CC  
V
DD  
V
SS  
V
CC  
V
DD  
output capacitor(C  
output capacitor(C  
)
)
2.2  
CO  
1.0  
DO  
output capacitor(C  
SO  
)
2.2  
flying capacitors(C 1, C 2, C 3)  
0.22  
0.1  
C
C
C
and V  
SS  
flying capacitors(C 1, C 2, C 3, C )  
D D D S  
Operating ambient temperature, T  
−40  
−40  
85  
°C  
°C  
A
Operating junction temperature, T  
125  
J
2
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SLVS495 − SEPTEMBER 2003  
ELECTRICAL CHARACTERISTICS  
ꢍꢂꢓ  
ꢈꢛꢠ  
ꢠꢂ  
ꢗꢓ  
ꢂꢂ  
ꢂꢠ  
ꢆꢂ  
ꢓꢂ  
°
µ
µ
ꢨꢤ ꢔ µꢟꢢ  
ꢪ ꢫ  
ꢔꢞ µꢟ ꢢ ꢬ ꢨ ꢝ ꢔ  
ꢇꢐ  
ꢑꢆ  
ꢖꢑ  
ꢍꢛ  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
DEVICE  
V
I
Input voltage range  
2.4  
5.5  
V
V = 2.8 V, EN = V ,  
SCLK = DATA = VROM = GND, No load  
I
I
I
Operating quiescent current  
Shutdown supply current  
50  
120  
µA  
Q
V = 2.8 V, EN = GND,  
I
SCLK = DATA = VROM = GND  
I
f
1
µA  
SD  
Maximum operating frequency  
320  
2.1  
2.0  
30  
400  
2.3  
2.2  
100  
520  
2.5  
2.4  
kHz  
max  
V = 0 V to 3.6 V  
I
V
Under−voltage lockout threshold  
Hysteresis  
V
UVLO  
V = 3.6 V to 0 V  
I
mV  
LOGIC SECTION  
V = 2.4 V to 3.5 V  
1.3  
1.5  
I
V
V
EN/CLK/DATA high level input voltage  
V
IH  
V = 3.5 V to 5.5 V  
I
EN/CLK/DATA low level input voltage  
Logic input current  
0.4  
0.1  
V
IL  
I
/ I  
EN = GND or V  
0.01  
3.3  
µA  
IH IL  
I
TPS65110 OUTPUT (V , V , V  
)
CC DD SS  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
Output DC voltage range  
V = 2.8 V, I  
= 5 mA  
3.25  
16  
3.35  
V
I
VCC  
I
Output current  
Output voltage ripple  
Line regulation  
Load regulation  
Rise time  
I
I
= 2 mA, I  
VSS  
= 1 mA  
mA  
mV  
%/V  
%
VCC  
VDD  
V
= 5 mA  
5
0.1  
RIPPLEC  
VCC  
V
V = 2.4 V to 5.5 V  
I
0.5  
1
REGC  
L
V = 2.8 V, I  
I VCC  
= no load to 10 mA  
0.3  
REGC  
t
t
10% to 90%, no load  
90% to 10%, no load  
100  
6
µꢪ  
rC  
Fall time  
mS  
fC  
V to V , V  
= 3.3 V, I  
= 3.3 V, I  
CC CC  
= 1 mA  
84%  
86%  
7.5  
I
CC CC  
VCC  
V
Efficiency  
CC  
V to V , V  
I
= 10 mA  
VCC  
V
DD  
V
DD  
V
DD  
V
DD  
V
DD  
V
DD  
Output DC voltage range  
Output current  
Output voltage ripple  
Rise time  
V
= 3.3 V, I  
= 3.3 V  
= 1 mA  
= 1.0 mA, V  
VDD DD  
boost = x3  
7.27  
2
7.73  
V
CC  
CC  
VDD  
I
V
mA  
mV  
mS  
mS  
VDD  
V
I
7
1.4  
2.4  
RIPPLED  
t
t
10% to 90%, no load  
90% to 10%, no load  
rD  
Fall time  
fD  
V
to V , V  
DD CC  
= 3.3 V, V = 7.5 V,  
DD  
CC  
70%  
I
= 0.2 mA  
VDD  
V
DD  
Efficiency  
V
V
V
to V , V  
DD CC  
= 3.3 V, V  
DD  
= 7.5 V, I = 2 mA  
VDD  
70%  
CC  
V
V
SS  
V
SS  
V
SS  
V
SS  
V
SS  
Output DC voltage range  
Output current  
Output voltage ripple  
Rise time  
= 3.3 V, I = 0.2 mA  
VSS  
−2.78  
1
−2.7 −2.62  
V
SS  
CC  
I
= 3.3 V  
mA  
mV  
VSS  
CC  
V
I
= 0.2 mA  
3
220  
2
RIPPLES  
VSS  
t
10% to 90%, no load  
90% to 10%, no load  
µꢪ  
rS  
fS  
t
Fall time  
mS  
V
to V , V  
SS CC  
= 3.3 V, V  
= −2.8 V,  
= −2.8 V,  
CC  
SS  
SS  
82%  
82%  
I
= 0.2 mA  
VSS  
V
SS  
Efficiency  
V
to V , V  
SS CC  
= 1 mA  
= 3.3 V, V  
CC  
I
VSS  
3
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ELECTRICAL CHARACTERISTICS Continued  
ꢛꢍ  
ꢂꢈ  
ꢠꢠ  
ꢐꢒ  
ꢗꢓ  
ꢂꢡ  
ꢠꢆ ꢂ  
ꢇꢑ  
ꢖꢓ  
°
µ
µ
ꢨ ꢤ ꢔꢤ µꢟꢢ  
ꢪ ꢫ  
ꢔꢞ µꢟ ꢢ ꢬ ꢨ ꢝ ꢔ  
ꢬ ꢢ  
ꢐꢒ  
ꢛꢖ  
ꢖꢐ  
ꢌꢌ  
ꢯꢋ  
ꢐꢛ  
TPS65111 OUTPUT (V , V , V  
)
CC DD SS  
V
V
Output dc voltage range  
V = 3.6 V, I  
VCC  
= 5 mA  
= 1 mA  
4.925  
16  
5.0 5.075  
5
V
CC  
CC  
Maximum V  
I
I
output current  
I
I
= 2 mA, I  
VSS  
mA  
mV  
%/V  
%
VCC  
CC  
VDD  
VCC  
V
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
Output voltage ripple  
Line regulation  
Load regulation  
Rise time  
= 5 mA  
RIPPLEC  
V
V = 2.7 V to 5.5 V  
I
0.1  
0.3  
0.5  
1
REGC  
REGC  
L
V = 3.6 V, I = no load to 10 mA  
I VCC  
t
10% to 90%, no load  
90% to 10%, no load  
200  
9
µS  
rC  
fC  
t
Fall time  
mS  
V to V , V  
= 5.0 V, I  
= 5.0 V, I  
CC CC  
= 1 mA  
88%  
90%  
9.0  
I
CC CC  
VCC  
V
V
Efficiency  
CC  
V to V , V  
I
= 10 mA  
boost = x2  
VCC  
V
DD  
Output dc voltage range  
V
V
= 5.0 V, I  
= 5.0 V  
= 1 mA  
= 1.0 mA, V  
VDD DD  
8.73  
2
9.27  
V
DD  
CC  
CC  
VDD  
I
Maximum V  
DD  
output current  
mA  
mV  
mS  
mS  
VDD  
V
V
DD  
V
DD  
V
DD  
Output voltage ripple  
Rise time  
I
8
1.8  
3
RIPPLED  
t
10% to 90%, no load  
90% to 10%, no load  
rD  
fD  
t
Fall time  
V
to V , V  
DD CC  
= 5.0 V, V  
= 5.0 V, V  
= 0.2 mA  
= 9.0 V,  
CC  
DD  
87%  
88%  
I
= 0.2mA  
VDD  
V
V
Efficiency  
DD  
V
to V , V  
DD CC  
= 9.0 V,  
CC  
DD  
I
= 2mA  
= 5.0 V, I  
= 5.0 V  
VDD  
V
SS  
Output dc voltage range  
V
V
−3.09  
1
−3.0 −2.91  
V
SS  
CC  
VSS  
I
Maximum V  
SS  
output current  
mA  
mV  
VSS  
CC  
V
V
SS  
V
SS  
V
SS  
Output voltage ripple  
Rise time  
I
= 0.2 mA  
3
250  
2.4  
RIPPLES  
VSS  
t
t
10% to 90%, no load  
90% to 10%, no load  
µꢪ  
rS  
Fall time  
mS  
fS  
V
to V , V  
SS CC  
= 5.0 V, V  
= −3.0 V,  
= −3.0 V,  
CC  
SS  
SS  
58%  
58%  
I
= 0.2 mA  
VSS  
V
SS  
Efficiency  
V
to V , V  
SS CC  
= 1 mA  
= 5.0 V, V  
CC  
I
VSS  
4
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PIN ASSIGNMENTS  
RGE PACKAGE  
(TOP VIEW)  
24 23 22 21 20 19  
CSP1  
VCC  
CCN3  
CCP3  
CCN2  
CCP2  
1
18  
17  
16  
15  
CDN2  
CDP3  
CDP2  
VDD  
VROM  
AGND  
2
3
4
Thermal  
Pad  
5
6
14  
13  
7
8
9
10 11 12  
Terminal Functions  
TERMINAL  
DESCRIPTION  
NO.  
1
NAME  
CSP1  
VCC  
VSS Positive terminal for CS  
VCC Charge pump output  
2
3
CCN3  
CCP3  
CCN2  
CCP2  
CCN1  
CCP1  
VIN  
VCC Negative terminal for CC3  
VCC Positive terminal for CC3  
VCC Negative terminal for CC2  
VCC Positive terminal for CC2  
VCC Negative terminal for CC1  
VCC Positive terminal for CC1  
Input supply voltage  
4
5
6
7
8
9
2
I C serial data input  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
DATA  
CLK  
2
I C serial clock input  
EN  
Power on/off enable logic input (H : active / L : shutdown)  
Analog GND  
AGND  
VROM  
VDD  
EEPROM power supply  
VDD Charge pump output  
CDP2  
CDP3  
CDN2  
CDN3  
CDN1  
CDP1  
PGND  
VSS  
VDD Positive terminal for CD2  
VDD Positive terminal for CD3  
VDD Negative terminal for CD2  
VDD Negative terminal for CD3  
VDD Negative terminal for CD1  
VDD Positive terminal for CD1  
Power GND  
VSS Charge pump output  
CSN1  
VSS Negative terminal for CS  
5
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FUNCTIONAL BLOCK DIAGRAM  
VIN  
VCC  
PSEL  
VPS  
VIN  
VIN_PG  
VIN  
BOOST  
CTRL  
PWR_ON  
CLK  
VBG  
OSC  
BG  
IBIAS  
IB  
VINDET  
VBG  
VBG  
VPS  
CCP1  
CCN1  
CCP2  
CCN2  
CCP3  
CCN3  
VCC  
VIN_PG  
SYS_EN  
Sequential  
Power  
Control  
VCC_ON  
VCC  
VSS_ON  
VDD_ON  
CLK  
CLK  
VBG  
EN  
EN  
VPS  
VCC  
CSP1  
CSN1  
VSS  
VROM  
CLK  
VBG  
VSS  
CLK  
EN  
VPS  
SCLK  
DATA  
VCC  
Serial  
I/F  
CDP1  
CDN1  
CDP2  
CDN2  
CDP3  
CDN3  
VDD  
EEPROM  
VROM  
VDD  
CLK  
VBG  
GND  
PGND  
6
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TYPICAL APPLICATION CIRCUIT  
VSS  
CD1  
0.1 µF  
CSO  
2.2 µF  
PGND  
CD2  
CS  
0.1 µF  
24  
23  
22  
21  
20  
19  
18  
0.1 µF  
CDN2  
CDP3  
CDP2  
VDD  
CSP1  
1
2
VCC  
VCC  
17  
16  
15  
14  
13  
CD3  
CCN3  
3
4
5
0.1 µF  
CCO  
2.2 µF  
CC3  
0.22 µF  
CCP3  
VDD  
CDO  
1 µF  
PGND  
CCN2  
VROM  
AGND  
CC2  
CCP2  
0.22 µF  
6
PGND  
7
8
9
10  
11  
12  
CC1  
0.22 µF  
CIN  
4.7 µF  
AGND  
Enable  
Signal  
VIN  
2.4 V to 5.5 V  
7
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TYPICAL CHARACTERISTICS  
VCC EFFICIENCY  
VCC EFFICIENCY  
100  
100  
TPS65110  
V = 2.8 V  
TPS65110  
I
V
CC  
= 3.3 V  
I
= 10 mA  
(VCC)  
V
CC  
= 3.3 V  
90  
80  
90  
80  
70  
70  
I
= 1 mA  
(VCC)  
60  
50  
60  
50  
0
5
10  
15  
20  
25  
30  
35  
40  
2
2.5  
3
3.5  
4
4.5  
5
I
− Supply Current − mA  
(VCC)  
V − Input Voltage − V  
I
Figure 1  
Figure 2  
VCC LOAD REGULATION  
VCC LOAD REGULATION  
3.35  
3.35  
3.30  
TPS65110  
TPS65110  
I
I
= 2 mA,  
= 1 mA,  
(VDD)  
(VSS)  
I
I
= 2 mA,  
= 1 mA,  
(VDD)  
(VSS)  
V = 3.6 V  
I
V = 2.8 V  
I
T
= −40°C  
A
3.30  
3.25  
3.20  
T = −40°C  
A
T
= 25°C  
A
T
A
= 25°C  
3.25  
3.20  
T
= 85°C  
A
T
A
= 85°C  
0
10  
I
20  
30  
40  
50  
0
10  
I
20  
30  
40  
50  
60  
− Supply Current − mA  
− Supply Current − mA  
(VCC)  
(VCC)  
Figure 3  
Figure 4  
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VDD LOAD REGULATION  
VSS LOAD REGULATION  
7.6  
2.80  
2.75  
TPS65110  
= 3.3 V  
TPS65110  
V = 3.3 V  
CC  
(VCC) (VDD)  
V
CC  
I
= I  
= no load  
I
= I = no load  
(VCC) (VSS)  
T
A
= −40°C  
T
= −40°C  
A
7.5  
7.4  
2.70  
2.65  
2.60  
T
= 25°C  
A
T
= 25°C  
A
T
= 85°C  
A
T
= 85°C  
A
7.3  
7.2  
2.55  
2.50  
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
I
− Supply Current − mA  
I
− Supply Current − mA  
(VDD)  
(VSS)  
Figure 5  
Figure 6  
MAXIMUM SWITCHING FREQUENCY  
QUIESCENT CURRENT  
vs  
vs  
INPUT VOLTAGE  
INPUT VOLTAGE  
490  
100  
80  
460  
430  
400  
370  
T
A
= 25°C  
T = 85°C  
A
T
= 25°C  
A
T
A
= −40°C  
60  
T
A
= −40°C  
40  
T
A
= 85°C  
20  
0
340  
310  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
V − Input Voltage − V  
I
V − Input Voltage − V  
I
Figure 7  
Figure 8  
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POWERUP SEQUENCE  
POWERDOWN SEQUENCE  
VDD  
VDD  
VCC  
EN  
VCC  
EN  
VSS  
VSS  
(V = 3.0 V, V  
= 3.3 V, V  
DD  
= 7.5 V, V  
SS  
CO  
= −2.7 V, V  
= 2.2 µF)  
= x3,  
I
CC  
DDBOOST  
(V = 3.0 V, V  
= 3.3 V, V  
DD  
= 7.5 V, V  
SS  
CO  
= −2.7 V, V  
= 2.2 µF)  
= x3,  
I
CC  
DDBOOST  
No load, C 1/2/3 = 0.22 µF, C  
C
No load, C 1/2/3 = 0.22 µF, C  
C
Figure 10  
Figure 9  
VCC RIPPLE VOLTAGE  
VCC RIPPLE VOLTAGE  
I
O
= 10 mA  
I
O
= 0.5 mA  
VCC  
VCC  
CCP1  
CCP1  
(V = 2.7 V, V  
CC  
CO  
= 3.3 V, T = 25°C, C 1/2/3 = 0.1 µF,  
I
A
C
(V = 2.7 V, V  
CC  
CO  
= 3.3 V, T = 25°C, C 1/2/3 = 0.1 µF,  
I
A
C
C
= 2.2 µF)  
C
= 2.2 µF)  
Figure 11  
Figure 12  
10  
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DETAILED DESCRIPTION  
VCC Charge Pump  
The VCC output provides a very high efficiency, regulated, dc/dc conversion through a wide input range by  
supporting x1.0, x1.33, x1.5, and x2.0 boost charge pump operation. TPS65110 automatically sets the boost  
ratio based on input and output voltage conditions. For example, when the input voltage from a battery becomes  
lower, the device automatically increases the boost ratio from x1.33 to x1.5. In a fixed input voltage mode, the  
device provides for higher conversion efficiency; for example, in the case of 2.8 V to 3.3 V conversion or 2.8  
V to 5.0 V conversion. In this case, the VCC charge pump can enter into a SKIP mode operation in order to  
maintain the efficiency of a low load condition. The highest frequency of the charge pump is 400 kHz (typ). The  
charge pump operates by using higher frequencies in the heavier load current conditions, and decreases the  
frequency in the lighter load conditions. Maximum output current and operating frequency characteristics are  
dependent on external conditions such as the flying capacitor, output capacitor, and ambient temperature  
range.  
VIN [V]  
VCC[V]  
2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.5  
3.3  
5.0  
x1.5  
NA  
x1.33  
x2  
x1  
x1.5  
x1.33  
x1  
:
NOTE Gray portion is HYSTERESIS.  
Of importance, the VCC charge pump is also used as the power source for the VDD and VSS charge pumps.  
Therefore, consider a case where the VDD charge pump’s output current is required to be 2mA, and the boost  
ratio is x3. With this condition, the required (additional) current for the VCC output is slightly more than 6 mA.  
If the VSS charge pump output current requirement is 1 mA, then the (additional) required current from VCC  
is another 1 mA. (Note: the VCC charge pump maintains a minimum of 16-mA output capability in addition to  
the loads required to support the VDD and VSS charge pumps under the recommended conditions.)  
VDD Charge Pump  
The power source for the VDD charge pump is the VCC charge pump. The output voltage and boost ratio of  
the VDD charge pump are fixed at either a 7.5 V and x3 boost (TPS65110), or a 9.0 V and x2 boost (TPS65111).  
The topology of this charge pump is SKIP mode, and the maximum frequency is 400 kHz. Maximum output  
current is dependent on the flying capacitors and ambient temperature range (refer to the typical  
characteristics).  
VSS Charge Pump  
The VSS charge pump is powered from the VCC charge pump and has a fixed output voltage of either –2.7  
V (TPS65110) or –3.0 V (TPS65111). The boost ratio for the VSS charge pump is fixed at x−1. The operation  
topology is SKIP mode and has a maximum frequency of 400 kHz. Maximum output current is dependent on  
the flying capacitor and ambient temperature range (refer to the typical characteristics).  
UVLO − Under Voltage Lockout  
The UVLO provides for the save operation of the device. It prevents the converter from turning on when the  
voltage on the VIN pin is less than the threshold voltage of UVLO. Note that although the input voltage range  
of the product is shown to be down to 2.4 V, the maximum threshold of the UVLO for a rising VIN is 2.5 V.  
Therefore, to operate down to 2.4 V, the device must first be powered by a source of more than 2.5 V.  
Enable  
Low logic on the EN pin forces the TPS6511x into shutdown mode. In shutdown, the power switch, drivers,  
voltage reference, oscillator, and all other functions are turned off. The supply current is reduced to less than  
1 µA in shutdown mode.  
Power-Up and Power-Down Sequencing  
The TPS65110/11 controls power-up and power-down sequence through an enable pin. This signal should be  
terminated and not be left floating to prevent miss-operation.  
Power-Up Sequence  
When the enable pin EN is pulled high, the device starts its power on sequencing. The VCC output starts up  
first. When the output voltage VCC has reached 75% of its nominal value, the VSS output comes up next. When  
VSS has reached 75% of the nominal value, the positive output VDD finally comes up.  
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Power-Down Sequencing  
When the enable pin EN is pulled low, the device starts its power-down sequencing. The VDD output goes down  
first. When the output voltage VDD has reached 70% of its nominal value, the VSS output goes down next.  
When VSS has reached 70% of the nominal value, the positive output VCC finally goes down. The TPS6511x  
ensures this power-down sequence even in the case of a sudden V drop.  
I
2.3 V  
2.2 V  
1
2
VIN  
1
EN  
1
1
2
V
ref  
3
(Internal)  
x0.75  
x0.75  
3
2
3
VCC  
VSS  
4
3
x0.7  
x0.7  
x0.7  
x0.7  
2
4
5
x0.7  
x0.7  
VDD  
1
4
1 2  
SYS_EN  
(Internal)  
Power Sequence  
12  
PACKAGE OPTION ADDENDUM  
www.ti.com  
30-Mar-2005  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
QFN  
QFN  
QFN  
Drawing  
TPS65110RGE  
TPS65110RGER  
TPS65110RGERG4  
ACTIVE  
ACTIVE  
ACTIVE  
RGE  
24  
24  
24  
92  
TBD  
TBD  
CU SN  
CU SN  
Level-2-235C-1 YEAR  
Level-2-235C-1 YEAR  
RGE  
3000  
RGE  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
TPS65111RGE  
ACTIVE  
ACTIVE  
QFN  
QFN  
RGE  
RGE  
24  
24  
150  
TBD  
TBD  
CU SN  
CU SN  
Level-2-235C-1 YEAR  
Level-2-235C-1 YEAR  
TPS65111RGER  
3000  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
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