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TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

TPS65132 单电感器 - 双输出电源

1 特性

2 应用范围

1

•

输入电压范围：2.5V 至 5.5V

_POS升压转换器：

由 4V 转换为 6V（步长为 0.1V）

_NEG反相降压-升压转换器：

•

小型、中型双极液晶显示屏 (LCD)

V

–

智能手机、平板电脑

摄像头、全球定位系统 (GPS)

家庭自动化、销售点

•

V

由 -6V 转换为 -4V（步长为 0.1V）

可穿戴设备（智能手表、活动追踪器）

最大输出电流：

80mA 或 150mA

•

通用分离轨电源

–

差分音频、耳机放大器

出色的综合效率

仪表、运算放大器、比较器

数模转换器/模数转换器 (DAC/ADC)

–

> 85%（I_OUT> 10mA）

> 90%（I_OUT> 40 mA）

•

性能优异

3 说明

–

出色的瞬态响应

TPS65132 系列设计用于支持正/负驱动应用。该器件

的两路输出均采用单电感方案，为用户提供尺寸最小的

解决方案，在简化物料清单的同时保持高效。该器件可

在低噪声条件下提供最佳线路和负载调节能力。凭借

2.5V 至 5.5V 的输入电压范围，该器件针对由单节电

池（锂离子电池、锂镍电池和锂聚合物电池）供电的产

品以及固定电压为 3.3V 和 5V 的电源轨进行了优化。

TPS656132 系列器件提供 80mA 和 150mA 输出电流

选项，可通过编程设定为 40mA。提供 CSP 和 QFN

两种封装选项。

在整个温度范围内保持 1% 的输出电压精度

I²C 接口

–

可编程上电/掉电

序列选项

–

灵活的输出电压编程

可编程有源输出放电

> 1000x 的可编程非易失性存储器

•

欠压锁定和过热保护

两种封装选项

–

15 焊球芯片尺寸封装 (CSP)

器件信息 ⁽¹⁾

20 引脚四方扁平无引线 (QFN) 封装

器件型号

封装

封装尺寸（标称值）

2.11mm × 1.51mm

4.00mm × 3.00mm

TPS65132

-B、-L、-T、-S

DSBGA (15)

WQFN (20)

TPS65132W

(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。

空白

典型应用

效率与输出电流间的关系

L

4.7 µH

100

95

90

85

80

75

70

V_IN

VIN

SW

C1

4.7 µF

V_POS

2.5V to 5.5 V

OUTP

REG

5.4 V/40 mA

C3

ENP

ENN

4.7 µF

C2

4.7 µF

V_NEG

SCL

SDA

OUTN

–5.4 V/40 mA

65

VIN = 4.5V

C5

4.7 µF

60

PGND

AGND

CFLY1

CFLY2

C4

VIN = 3.7V

2.2 µF

55

VIN = 2.8V

50

0

5

10

15

20

25

30

35

40

C003

IOUT (mA)

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION

DATA.

English Data Sheet: SLVSBM1

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

8.4 Device Functional Modes........................................ 16

8.5 Programming........................................................... 17

8.6 Register Maps......................................................... 19

Application and Implementation ........................ 26

9.1 Application Information............................................ 26

9.2 Typical Applications ................................................ 26

1

2

3

4

5

6

7

特性.......................................................................... 1

应用范围................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Device Comparison Table..................................... 4

Pin Configuration and Functions......................... 5

Specifications......................................................... 8

7.1 Absolute Maximum Ratings ...................................... 8

7.2 ESD Ratings.............................................................. 8

7.3 Recommended Operating Conditions....................... 8

7.4 Thermal Information.................................................. 8

7.5 Electrical Characteristics........................................... 9

9

10 Power Supply Recommendations ..................... 53

11 Layout................................................................... 54

11.1 Layout Guidelines ................................................. 54

11.2 Layout Example .................................................... 54

12 器件和文档支持 ..................................................... 55

12.1 器件支持 ............................................................... 55

12.2 接收文档更新通知 ................................................. 55

12.3 社区资源................................................................ 55

12.4 商标....................................................................... 55

12.5 静电放电警告......................................................... 55

12.6 Glossary................................................................ 55

13 机械、封装和可订购信息....................................... 56

13.1 CSP 封装概要 ...................................................... 56

7.6 I²C Interface Timing Requirements / Characteristics

................................................................................. 10

7.7 Typical Characteristics............................................ 11

Detailed Description ............................................ 12

8.1 Overview ................................................................. 12

8.2 Functional Block Diagram ....................................... 12

8.3 Feature Description................................................. 12

8

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

Changes from Revision G (August 2015) to Revision H

Page

•

已删除 TPS65132S 中的产品预览.......................................................................................................................................... 1

Changed Device Comparison Table ...................................................................................................................................... 4

Added description of clock stretching .................................................................................................................................. 17

Deleted detailed I²C interface description ........................................................................................................................... 17

Added that the DLYx Register is only valid for TPS65132Sx versions. .............................................................................. 22

Changed Table 6 ................................................................................................................................................................. 23

Changes from Revision F (June 2015) to Revision G

Page

•

Changed scope figures for Boost Converter switching. ...................................................................................................... 13

Changes from Revision E (November 2014) to Revision F

Page

•

Added TPS65132L1 device to Device Comparison table ..................................................................................................... 4

Added TPS65132T6 device to the Device Comparison Table. ............................................................................................. 4

Separated LOGIC SCL, SDA spec MIN/MAX from LOGIC EN, ENN, ENP, SYNC spec MIN/MAX ..................................... 9

Changed DAC Registers section for clarity ......................................................................................................................... 19

Added High-current Applications (≤ 150 mA) section........................................................................................................... 44

Changes from Revision D (October 2014) to Revision E

Page

•

Added TPS65132L0 device to Device Comparison table ..................................................................................................... 4

2

TPS65132

www.ti.com.cn

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

Changes from Revision C (July 2014) to Revision D

Page

•

已将器件信息表中的封装类型更改为符合行业标准的标识符 .................................................................................................. 1

Changes from Revision B (May 2014) to Revision C

Page

•

Added note to Device Comparison Table .............................................................................................................................. 4

Added reference to Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) .................................... 12

Added Table 1 and various references to it ......................................................................................................................... 14

Added "Power-Down And Discharge (CPN) shows the V_NEGdischarge behavior of each device variant".......................... 16

Added Table 2 and various references to it ........................................................................................................................ 16

Added note to Figure 18 ...................................................................................................................................................... 23

Changes from Revision A (August 2013) to Revision B

Page

•

已将格式更改为全新的数据表标准.......................................................................................................................................... 1

已添加新封装选项 (QFN) 至器件信息表 ................................................................................................................................ 1

Added new package option (QFN) to Pin Configurations section ......................................................................................... 7

Added the ESD Ratings table ................................................................................................................................................ 8

Changes from Original (June 2013) to Revision A

Page

•

Added TPS65132Bx devices to the Device Comparison table .............................................................................................. 4

3

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

5

Device Comparison Table

PRE-

PROGRAMMED

OUTPUT

VOLTAGES

PRE-

STARTUP

TIME

PRE-

PROGRAMMED

I_OUT

PROGRAMMED

ACTIVE

PART NUMBER⁽¹⁾

I_{OUT_MAX}

I_SD

PACKAGE

VPOS / VNEG

DISCHARGE⁽²⁾

(3)

V_POS= 5.4 V

TPS65132A

V_NEG= –5.4 V

80 mA

40 mA

V_POS/ V_NEG

FAST

30 µA

CSP

V_POS= 5.0 V

TPS65132A0

V_NEG= –5.0 V

V_POS= 5.4 V

TPS65132B

V_NEG= –5.4V

V_POS= 5.0 V

TPS65132B0

80 mA

V_POS/ V_NEG

130 nA

CSP

V_NEG= –5.0 V

V_POS= 5.5 V

TPS65132B5

V_NEG= –5.5 V

V_POS= 5.2 V

TPS65132B2

V_NEG= –5.2 V

V_POS= 5.4 V

TPS65132L

40 mA

V_POS/ V_NEG

SLOW

V_NEG= –5.4 V

V_POS= 5.0 V

TPS65132L0

V_NEG= –5.0 V

V_POS= 5.1 V

(4)

TPS65132L1

V_NEG= –5.1 V

80 mA

150 mA

80 mA

40 mA

80 mA

V_POS/ V_NEG

SLOW

130 nA

CSP

QFN

V_POS= 5.6 V

TPS65132T6

V_NEG= –5.6 V

V_POS= 5.4 V

TPS65132S

V_NEG= –5.4 V

V_POS= 5.4 V

TPS65132W

V_NEG= –5.4 V

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com

(2) See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed description of how each device variant

implements the active discharge function.

(3) Please refer to Power-Up And Soft-Start (LDO) and Power-Up And Soft-Start (CPN) for more details.

(4) Product preview.

4

TPS65132

www.ti.com.cn

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

6 Pin Configuration and Functions

YFF Package

15 Bumps

(top view)

TPS65132Ax / Bx / Lx / Tx

(bottom view)

TPS65132Ax / Bx / Lx / Tx

PGND

OUTP

REG

AGND

SDA

PGND

REG

AGND

SDA

OUTP

REG

E

D

C

B

A

E

D

C

B

A

SW

VIN

CFLY1

PGND

VIN

CFLY1

PGND

SCL

ENP

SCL

ENP

OUTN

CFLY2

ENN

CFLY2

ENN

3

2

1

2

3

(top view)

TPS65132Sx

(bottom view)

TPS65132Sx

PGND

OUTP

REG

AGND

SDA

PGND

REG

AGND

SDA

OUTP

REG

E

D

C

B

A

E

D

C

B

A

SW

VIN

CFLY1

PGND

VIN

CFLY1

PGND

SCL

EN

SCL

EN

OUTN

CFLY2

SYNC

CFLY2

SYNC

3

2

1

2

3

5

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

Pin Functions

I/O

DESCRIPTION

NAME

AGND

CFLY1

CFLY2

EN

Ax, Bx, Lx, Tx

Sx

D2

C3

A3

B1

—

D2

C3

A3

—

I/O

Analog ground

Negative charge pump flying capacitor pin

Enable pin (sequence programmed)

Enable pin for V_NEGrail

ENN

A1

B1

E3

A2

B3

E1

D3

E2

B2

C2

D1

—

I

ENP

B1

E3

A2

B3

E1

D3

E2

B2

C2

D1

A1

C1

I

Enable pin for V_POSrail

OUTP

OUTN

O

Output pin of the LDO (V_POS)

Output pin of the negative charge pump (V_NEG

)

PGND

REG

—

Power ground

I/O

Boost converter output pin

SCL

SDA

SW

I/O

I

I²C interface clock signal pin

I²C interface data signal pin

Switch pin of the boost converter

SYNC

VIN

Synchronization pin. 150 mA current enabled if this pin is pulled HIGH.

Input voltage supply pin

C1

I

6

TPS65132

www.ti.com.cn

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

QFN Package

20 Pins

RVC package

(top view)

RVC package

(bottom view)

19

18

17

20

17

18

19

20

16

15

14

13

12

11

16

15

14

13

12

11

1

2

3

4

5

6

PGND

OUTP

REG

PGND

AGND

VIN

OUTP

1

2

3

4

5

6

OUTP

REG

PGND

AGND

VIN

PowerPAD

CFLY1

PGND

CFLY1

PGND

ENP

ENN

7

8

9

10

9

8

7

Pin Functions

I/O

DESCRIPTION

NAME

Wx

3

AGND

—

Analog ground

17

13

10

6

CFLY1

CFLY2

ENN

I/O

Negative charge pump flying capacitor pin

Enable pin for V_NEGrail

I/O

I

ENP

5

Enable pin for V_POSrail

16

15

9

OUTP

OUTN

O

Output pin of the LDO (V_POS)

Output pin of the negative charge pump (V_NEG

)

1

2

PGND

—

Power ground

11

12

14

18

8

REG

I/O

Boost converter output pin

SCL

SDA

I/O

I²C interface clock signal pin

I²C interface data signal pin

7

19

20

4

SW

VIN

I/O

I

Switch pin of the boost converter

Input voltage supply pin

7

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

7 Specifications

(1)(2)

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

–0.3

–7

MAX

7

CFLY1, EN, ENN, ENP, OUTP, REG, SCL, SDA, SW, SYNC,

VIN

V

Voltage range

CFLY2, OUTN

0.3

Continuous total power dissipation

Operating junction temperature, T_J

Operating ambient temperature, T_A

Storage temperature, T_stg

See Thermal Information

–40

–65

150

85

°C

150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to ground.

7.2 ESD Ratings

VALUE

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

±2000

V

V_ESD

Charged device model (CDM) per JEDEC specification JESD22-

C101, all pins⁽²⁾

±500

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN

2.5

2.2

4.7

2.2

4.7

–40

TYP

MAX

5.5

UNIT

V

V_IN

Input voltage range

Inductor⁽¹⁾

Input capacitor⁽¹⁾⁽²⁾

Flying capacitor⁽¹⁾⁽²⁾

Output capacitors⁽¹⁾⁽²⁾

Operating ambient temperature

Operating junction temperature

L

4.7

µH

µF

°C

C_IN

C_FLY

C_OUTP, C_OUTN, C_REG

T_A

T_J

85

125

°C

(1) Please see Detailed Description section for further information.

(2) X7R (or better dielectric material) is recommended.

7.4 Thermal Information

TPS65132

YFF

TPS65132

(1)

THERMAL METRIC

RVC

(20) PINS

39.0

UNIT

(15) BALLS

76.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJCtop

R_θJB

0.2

42.7

44

13.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.6

0.6

ψ_JB

43.4

13.6

R_θJCbot

N/A

3.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

8

TPS65132

www.ti.com.cn

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

7.5 Electrical Characteristics

V_IN= 3.7 V, EN = ENN = ENP = V_IN, V_POS= 5.4 V, V_NEG= –5.4 V, T_A= –40°C to 85°C; typical values are at T_A= 25°C

(unless otherwise noted).

PARAMETER

SUPPLY CURRENT

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_IN

Input voltage range

2.5

2.3

2.1

5.5

2.5

2.3

V

V_INrising

V_INfalling

V_UVLO

I_Q

Undervoltage lockout threshold

Quiescent current

0.54

140

5

mA

°C

Thermal shutdown

Thermal shutdown hysteresis

°C

LOGIC EN, ENN, ENP, SYNC

V_IH

V_IL

High level input voltage

Low level input voltage

Pulldown resistors

1.1

V_IN= 2.5 V to 5.5 V

V

0.4

R_EN

200

kΩ

LOGIC SCL, SDA

V_IH

V_IL

High level input voltage

Low level input voltage

V

0.54

BOOST CONVERTER

I_LIMBoost converter valley current limit

f_SWBoost converter switching frequency

LDO OUTPUT V_POS

0.9

1.2

1.5

A

1.35

1.80

2.25

MHz

V_POS

V_{POS_acc}

I_POS

Positive output voltage range

4.0

–1 %

200

6.0

V

Positive output voltage accuracy

Positive output current capability

Dropout voltage

+1 %

mA

mV

%/A

Ω

V_DO

V_REG= V_POS(NOM)= 5.4V, I_OUT= 150 mA

V_IN= 2.5 V to 5.5 V, I_OUT= 40 mA

ΔI_OUT= 80 mA

160

2.7

3.4

70

Line regulation

Load regulation

R_D

Discharge resistor

NEGATIVE CHARGE PUMP OUTPUT V_NEG

V_NEG

Negative output voltage range

–6.0

–1 %

40

–4.0

V

V_{NEG_acc}

Negative output voltage accuracy

+1 %

40mA MODE

I_NEG

Negative output current capability

mA

80mA MODE

80

I_NEG

f_OSC

TPS65132Sx, SYNC = HIGH

150

mA

Negative charge pump switching

frequency

0.8

1.0

1.2

MHz

Line regulation

Load regulation

Discharge resistor

V_IN= 2.5 V to 5.5 V, I_OUT= 40 mA

3.3

6.1

20

mV

%/A

Ω

ΔI_OUT= 80 mA

R_D

9

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

MAX UNIT

7.6 I²C Interface Timing Requirements / Characteristics

(1)

PARAMETER

TEST CONDITIONS

Standard mode

Fast mode

MIN

TYP

100

400

kHz

µs

ns

µs

ns

µs

ns

µs

ns

f_SCL

SCL clock frequency

Standard mode

Fast mode

4.7

1.3

t_LOW

t_HIGH

t_BUF

LOW period of the SCL clock

Standard mode

Fast mode

4.0

HIGH period of the SCL clock

600

4.7

Standard mode

Fast mode

Bus free time between a STOP and START condition

1.3

Standard mode

Fast mode

4.0

t_hd;STAHold time for a repeated START condition

t_su;STASetup time for a repeated START condition

t_su;DATData setup time

600

4.7

Standard mode

Fast mode

600

250

100

0.05

Standard mode

Fast mode

Standard mode

Fast mode

3.45

0.9

t_hd;DATData hold time

Standard mode

20 +

1000

0.1C_B

Rise time of SCL signal after a repeated START condition

and after an acknowledge bit

t_RCL1

Fast mode

20 +

1000

300

ns

0.1C_B

Standard mode

Fast mode

20 +

0.1C_B

t_RCL

t_FCL

t_RDA

t_FDA

Rise time of SCL signal

Fall time of SCL signal

Rise time of SDA signal

Fall time of SDA signal

20 +

0.1C_B

Standard mode

Fast mode

20 +

0.1C_B

300

20 +

0.1C_B

300

Standard mode

Fast mode

20 +

0.1C_B

1000

300

20 +

0.1C_B

Standard mode

Fast mode

20 +

0.1C_B

300

20 +

300

0.1C_B

Standard mode

Fast mode

4.0

µs

ns

nF

t_su;STOSetup time for STOP condition

C_BCapacitive load for SDA and SCL

600

0.4

(1) Industry standard I²C timing characteristics according to I²C-Bus Specification, Version 2.1, January 2000. Not tested in production.

SDA

t

f

BUF

t

f

t

LOW

t

r

su;DAT

t

r

hd;STA

SCL

t

su;STO

hd;STA

su;STA

t

hd;DAT

HIGH

S

Sr

P

S

Figure 1. Serial Interface Timing For F/S-Mode

10

TPS65132

www.ti.com.cn

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

7.7 Typical Characteristics

V_IN= 3.7 V, V_POS= 5.4 V, V_NEG= –5.4 V, unless otherwise noted

3

0.6

0.58

0.56

0.54

0.52

0.5

VIN = 2.9 V

VIN = 3.7 V

VIN = 4.5 V

VIN = 3.7 V

VIN = 4.5 V

2.5

2

1.5

1

0.48

0.46

0.44

0.42

0.4

0.5

0

-40

-20

0

20

40

60

80

-40

-20

0

20

40

60

80

C04

Ta (°C)

C04

Ta (°C)

Figure 2. Shutdown Current (all versions but Ax)

Figure 3. Quiescent Current

1.2

1.15

1.1

2.5

2.45

2.4

VIN = 2.9 V

VIN = 3.7 V

VIN = 4.5 V

UVLO_rising

UVLO_falling

1.05

1

2.35

2.3

0.95

0.9

2.25

2.2

0.85

0.8

-40

10

60

-40

-20

0

20

40

60

80

C03

Ta (°C)

Figure 4. Main Oscillator Frequency

Figure 5. UVLO

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8 Detailed Description

8.1 Overview

The TPS65132, supporting input voltage range from 2.5 V to 5.5 V, operates with a single inductor scheme to

provide a high efficiency with a small solution size. The synchronous boost converter generates a positive

voltage that is regulated down by an integrated LDO, providing the positive supply rail (V_POS). The negative

supply rail (V_NEG) is generated by an integrated negative charge pump (or CPN) driven from the boost converter

output pin, REG. The operating mode can be selected between 40mA and 80mA in order to select the necessary

output current capability and to get the best efficiency possible based on the application. The device topology

allows a 100% asymmetry of the output currents.

8.2 Functional Block Diagram

SW

REG

V_POS

OUTP

VIN

SYNC

BOOST

V_IN

LDO

CPN

5.4 V/40 mA

(battery voltage)

V_NEG

OUTN

AGND

ENP

ENN

–5.4 V/40 mA

SCL

SDA

8.3 Feature Description

8.3.1 Undervoltage Lockout (UVLO)

The TPS65132 integrates an undervoltage lockout block (UVLO) that enables the device once the voltage on the

VIN pin exceeds the UVLO threshold (2.5 V maximum). No output voltage will be generated as long as the

enable signals are not pulled HIGH. The device, as well as all converters (boost converter, LDO, CPN), will be

disabled as soon as the V_INvoltage falls below the UVLO threshold. The UVLO threshold is designed in a way

that the TPS65132 will continue operating as long as V_INstays above 2.3 V. This guarantees a proper operation

even in the event of extensive line transients when the battery gets suddenly heavily loaded.

For TPS65132Ax, a 40 ms delay is starting as soon as the UVLO threshold is reached. This delay prevents the

device to be disabled and enabled by an unwanted VIN voltage spike. Once this delay has passed, the output

rails can be enabled and disabled as desired with the enable signals without any delay.

8.3.2 Active Discharge

An active discharge of the positive rail and/or the negative rail can be programmed (DISP and DISN bits

respectively - refer to Registers). If programmed to be active, the discharge will occur at power down, when the

enable signals go LOW (Figure 37 and Figure 38 for TPS65132Ax, Bx, Lx, Tx, Wx — Figure 105 and Figure 104

for TPS65132Sx). See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed

description of how each device variant implements the active discharge function.

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Feature Description (continued)

8.3.3 Boost Converter

8.3.3.1 Boost Converter Operation

The synchronous boost converter uses a current mode topology and operates at a quasi-fixed frequency of

typically 1.8 MHz, allowing chip inductors such as 2.2 µH or 4.7 µH to be used. The converter is internally

compensated and provides a regulated output voltage automatically adjusted depending on the programmed

V_POSand V_NEGvoltages. The boost converter operates either in continuous conduction mode (CCM) or Pulse

Frequency Modulation mode (PFM), depending on the load current in order to provide the highest efficiency

possible. The switch node waveforms for CCM and DCM operation are shown in Figure 6 and Figure 7.

8.3.3.2 Power-Up And Soft-Start (Boost Converter)

The boost converter starts switching as soon as one enable signal is pulled HIGH and the voltage on VIN pin is

above the UVLO threshold. For TPS65132Ax, in the case where one enable signal is already HIGH when V_IN

reaches the UVLO threshold, the boost converter will only start switching after a 40 ms delay has passed (see

Undervoltage Lockout (UVLO)).

The boost converter starts up with an integrated soft-start to avoid drawing excessive inrush current from the

supply. The output voltage V_REGis slowly ramped up to its target value. Typical startup waveforms for low-current

applications are shown in Figure 33 and Figure 35.

8.3.3.3 Power-Down (Boost Converter)

The boost converter stops switching when V_INis below the UVLO threshold or when both output rails are

disabled. For example, due to a special sequencing, the LDO might still be operating while the CPN is already

disabled, in which case, the boost will continue operating until the LDO has been disabled. Typical power-down

waveforms for low-current applications are shown in Figure 34 and Figure 36.

8.3.3.4 Isolation (Boost Converter)

The boost converter output (REG) is isolated from the input supply V_IN, providing a true shutdown.

8.3.3.5 Output Voltage (Boost Converter)

The output voltage of the boost converter is automatically adjusted depending on the programmed V_POSand

V_NEGvoltages.

8.3.3.6 Advanced Power-Save Mode For Light-Load Efficiency And PFM

The TPS65132 device integrates a power save mode to improve efficiency at light load. In power save mode the

converter stops switching when the inductor current reaches 0 A. The device resumes its switching activity with

one or more pulses once the V_REGvoltage falls below its regulation level, and goes again into power save mode

once the inductor current reaches 0 A. The pulse duration remains constant, but the frequency of these pulses

varies according to the output load. This operating mode is also known as Pulse Frequency Modulation or PFM.

Figure 6 provides plots of the inductor current and the switch node in PFM mode.

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Feature Description (continued)

TPS65132B - Low-Current Application

2

V_{REG_AC}

V_SW

3

I_L

4

Ch4 100 mA/div

Ch2 50.0 mV/div

Ch3 2.00 V/div

Ch4 100 mA/div

Ch2 50.0 mV/div

Ch3 2.00 V/div

1 µs/div

Figure 7. Boost Converter — Heavy Load (40 mA)

Figure 6. Boost Converter - Light Load (1 mA)

8.3.4 LDO Regulator

8.3.4.1 LDO Operation

The Low Dropout regulator (or LDO) generates the positive voltage rail, V_POS, by regulating down the output

voltage of the boost converter (V_REG). Its inherent power supply rejection helps filtering the output ripple of the

boost converter in order to provide on OUTP pin a clean voltage, e.g. to supply the source driver IC of the

display.

8.3.4.2 Power-Up And Soft-Start (LDO)

The LDO starts operating as soon as the ENP signal is pulled HIGH, V_INvoltage is above the UVLO threshold

and the boost converter has reached its Power Good threshold.

In the case where the enable signal is already HIGH when V_INexceeds the UVLO threshold, the boost converter

will start first and the LDO will only start after the boost converter has reached its target voltage. For

TPS65132Ax, the boost will start after the 40 ms delay has passed (see Undervoltage Lockout (UVLO)).

For TPS65132Sx the LDO startup is defined by the setting of the DLYx register and the SEQU bits, see

Registers for more details.

The LDO integrates a soft-start that slowly ramps up its output voltage V_POSregardless of the output capacitor

and the target voltage, as long as the LDO current limit is not reached. For TPS65132Ax and TPS65132Bx

(except TPS65132B2), the typical startup time is 140 µs. For TPS65132B2, TPS65132Lx, TPS65132Sx,

TPS65132Tx and TPS65132Wx, the typical ramp-up time is 500 µs and the inrush current is also reduced by a

factor of 3. Typical startup waveforms for the low-current application are shown in Figure 33 to Figure 35.

8.3.4.3 Power-Down And Discharge (LDO)

The LDO stops operating when V_INis below the UVLO threshold or when ENP is pulled LOW. Or for

TPS65132Sx when EN is pulled LOW, and the internal sequencing has passed.

The positive rail can be actively discharged to GND during power-down if required. A discharge selection bit is

available to enable or disable this function. See Registers for more details, as well as waveforms in Figure 37

and Figure 38. Table 1 shows the V_POSactive discharge behavior of each device variant.

Table 1. V_POSActive Discharge Behavior

PART NUMBER

V_IN

ENP (or EN)

Don't Care

Low

ENN (or SYNC)

Don't Care

Low

V_POSDISCHARGE

< V_UVLO

On

Determined by DISP bit

TPS65132Ax

Low

High

Determined by DISP bit

> V_UVLO

High

Low

Off

High

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Feature Description (continued)

Table 1. V_POSActive Discharge Behavior (continued)

PART NUMBER

V_IN

ENP (or EN)

Don't Care

Low

ENN (or SYNC)

Don't Care

Low

V_POSDISCHARGE

< V_UVLO

On

TPS65132Bx

TPS65132Lx

TPS65132Sx

TPS65132Tx

TPS65132Wx

On

Low

High

Determined by DISP bit

> V_UVLO

High

Low

Off

High

8.3.4.4 Isolation (LDO)

The LDO is isolating the V_POSrail from V_REG(boost converter output) as long as the rail is not enabled in order to

ensure flexible startup like V_NEGbefore V_POS

.

8.3.4.5 Setting The Output Voltage (LDO)

The output voltage of the LDO is programmable via a I²C compatible interface, from –6.0 V to –4.0 V in 100 mV

steps. For more details, please refer to the VPOS Register – Address: 0x00

8.3.5 Negative Charge Pump

8.3.5.1 Operation

The negative charge pump (CPN) generates the negative voltage rail, V_NEG, by inverting and regulating the

output voltage of the boost converter (V_REG). The charge pump uses 4 switches and an external flying capacitor

to generate the negative rail. Two of the switches are turned on in the first phase to charge the flying capacitor

up to V_REG, and in the second phase they are turned-off and the two others turn on to pump the energy

negatively out of the OUTN capacitor.

8.3.5.2 Power-Up And Soft-Start (CPN)

The CPN starts operating as soon as the ENN signal is pulled HIGH, V_INvoltage is above the UVLO threshold

and the boost converter has reached its Power Good threshold.

In the case where the enable signal is already HIGH when V_INreaches the UVLO threshold, the boost converter

will start first and the CPN will only start after the boost converter has reached its target voltage. For

TPS65132Ax, the boost will start after the 40 ms delay has passed (see Undervoltage Lockout (UVLO)).

For TPS65132Sx the CPN startup is defined by the setting of the DLYx register and the SEQU bits, see

Registers for more details.

The CPN integrates a soft-start that slowly ramps up its output voltage V_NEGwithin a time defined by the selected

mode (40mA or 80mA), the output voltage and the output capacitor value. For TPS65132Ax and TPS65132Bx

(except TPS65132B2), the startup current charging the output capacitor in 40mA mode is 50 mA, and 100 mA

typically in 80mA mode. For TPS65132B2, TPS65132Lx, TPS65132Tx, and TPS65132Wx, the typical ramp-up

times are slowed down by a factor of 4 (i.e 12.5 mA and 25 mA typical output current for 40mA and 80mA modes

respectively) and the inrush current is also reduced by a factor of about 4. Typical startup waveforms for the low-

current application are shown in Figure 39 to Figure 42.

For TPS65132Sx, the negative rail starts-up in 40mA or 80mA mode, thus the startup current is set by the mode

the device is programmed to, and not related to the SYNC pin state. The full current of 150 mA minimum is only

released once both rails (V_POSand V_NEG) have reached their Power Good levels.

C_OUT´ V_NEG

t_STARTUP

=

I_STARTUP

The estimated startup time can be calculated using the following formula:

Where:

t_STARTUP= startup time of the V_NEGrail

C_OUT= output capacitance of the V_NEGrail

V_NEG= target output voltage

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I_STARTUP= output current of the V_NEGrail charging up the output capacitor at startup (12.5 mA, 25 mA, 50 mA

or 100 mA as described above)

8.3.5.3 Power-Down And Discharge (CPN)

The CPN stops operating when V_INis below the UVLO threshold or when ENN is pulled LOW.

Or when EN is pulled LOW in the TPS65132Sx, and the internal sequencing has passed.

The negative rail can be actively discharged to GND during power-down if required. A discharge selection bit is

available to enable or disable this function. See for more details, as well as waveforms Figure 37 and Figure 38.

Table 2 shows the V_NEGdischarge behavior of each device variant.

Table 2. V_NEGActive Discharge Behavior

PART NUMBER

V_IN

ENP (or EN)

Don't Care

Low

ENN (or SYNC)

Don't Care

Low

V_NEGDISCHARGE

< V_UVLO

On

Determined by DISN bit

TPS65132Ax

Low

High

Off

> V_UVLO

< V_UVLO

> V_UVLO

< V_UVLO

> V_UVLO

High

Low

Determined by DISN bit

High

Off

Don't Care

Low

Don't Care

Low

On

TPS65132Bx

TPS65132Lx

TPS65132Tx

TPS65132Wx

On

Low

High

Off

High

Low

Determined by DISN bit

High

Off

Don't Care

Low

Don't Care

Low

On

TPS65132Sx

Low

High

Determined by DISN bit

High

Low

Off

High

8.3.5.4 Isolation (CPN)

The CPN isolates the V_NEGrail from V_REG(boost converter output) as long as the rail is not enabled in order to

ensure flexible startup like V_POSbefore V_NEG

.

8.3.5.5 Setting The Output Voltage (CPN)

The output voltage of the CPN is programmable via a I²C compatible interface, from –4.0 V to –6.0 V in 100 mV

steps. For more details, please refer to the VNEG Register – Address 0x01.

8.4 Device Functional Modes

8.4.1 Enabling and Disabling the Device

At startup (V_INgoes above UVLO and at least one of the enable pins (ENP, ENN, or EN) goes HIGH), the

EEPROM content is loaded into the DAC registers and the IC starts with these default values. The TPS65132 is

enabled as long as the V_INvoltage is above the UVLO and one of the enable pins (ENP, ENN, or EN) is HIGH.

Pulling ENP or ENN LOW disables either rail (V_POSor V_NEGrespectively); and, pulling both pins LOW disables

the device entirely (the internal oscillator of the TPS65132Ax continues running to allow access to the I²C

interface).

For TPS65132Sx, pulling EN LOW disables the device.

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8.5 Programming

8.5.1 I²C Serial Interface Description

The TPS65132 communicates through an industry standard I²C compatible interface, to receive data in slave

mode. I²C is a 2-wire serial interface developed by Philips Semiconductor (see I²C-Bus Specification, Version

2.1, January 2000).

The TPS65132 integrates a non-volatile memory (EEPROM) that allows the storage of the register values with a

capability of up to 1000 programming cycles. At startup the TPS65132 loads first the EEPROM content into the

registers and uses these voltages to start.

It is recommended to stop I²C communication with the TPS65132 for 50 ms after the command "Write EEPROM

data" was sent. If the device is accessed via I²C during EEPROM programming, the device will pull down the

SCL line (clock stretch) after it recognized its I²C address. The SCL line will be released after EEPROM

programming is finished.

The TPS65132 works as a slave and supports the following data transfer modes, as defined in the I²C-Bus

specification: standard mode (100 kbps) and fast mode (400 kbps). The data transfer protocol for standard and

fast modes is exactly the same, therefore they are referred to as F/S-mode in this document. The TPS65132

supports 7-bit addressing. The device 7-bit address is 3E (see Figure 8), and the LSB enables the write or read

function.

Figure 8. TPS65132 Slave Address Byte

MSB

0

TPS65132

1

Address

1

LSB

R/W

1

0

R/W = R/(W)

NOTE

With TPS65132Ax, the I²C interface is accessible as long as the input voltage is above

the undervoltage lockout threshold. In all other versions, the I²C interface is accessible

only as soon as one of the enable pins is pulled HIGH while the input voltage is above the

undervoltage lockout.

8.5.2 I²C Interface Protocol

7

8

1

S

Slave Address

R/

W

A

Data Register

A

P

A

Register Address

“0” Write

A

S

= Acknowledge (SDA LOW)

= Not Acknowledge (SDA HIGH)

= START condition

From Master to Slave

From Slave to Master

Sr = REPEATED START condition

= STOP condition

P

Figure 9. “Write" Data To DAC – Transfer Format In F/S-Mode

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7

8

1

A

Register Address (n)

A

Data n^thRegister

A

Data (n+1)^thRegister

S

Slave Address

R/

W

A

“0” Write

8

1

A

1

P

Data (Last) Register

A

S

= Acknowledge (SDA LOW)

= Not Acknowledge (SDA HIGH)

= START condition

From Master to Slave

From Slave to Master

Sr = REPEATED START condition

= STOP condition

P

Figure 10. "Write" Data To DAC – Transfer Format In F/S-Mode

Featuring Register Address Auto-Increment

7

8

1

S

Slave Address

R/

W

A

P

CR Data (1xxxxxxx)

A

CR Address

“1” Write all DAC data to EEPROM

“0” Write

A

S

= Acknowledge (SDA LOW)

= Not Acknowledge (SDA HIGH)

= START condition

From Master to Slave

From Slave to Master

Sr = REPEATED START condition

= STOP condition

P

Figure 11. “Write” Data To EEPROM – Transfer Format In F/S-Mode

7

8

1

S

Slave Address

R/

W

A

CR data (0xxxxxx0)

A

P

A

CR Address

“0” Read from DAC Register

“1” Read from EEPROM Register

“0” Write

7

8

7

Slave Address

8

1

R/

1

A

1

S

Slave Address

W

Register Address

A

Sr

R/W

A

Data

P

A

“0” Write

“1” Read

A

S

= Acknowledge (SDA LOW)

= Not Acknowledge (SDA HIGH)

= START condition

From Master to Slave

Sr = REPEATED START condition

= STOP condition

From Slave to Master

P

Figure 12. “Read” Data From DAC/EEPROM – Transfer Format In F/S-Mode

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7

8

1

S

Slave Address

R/

W

A

CR data (0xxxxxx0)

A

P

A

CR Address

“0” Read from DAC Register

“1” Read from EEPROM Register

“0” Write

7

8

7

Slave Address

8

1

R/

1

A

Data n^thRegister

S

Slave Address

W

Register Address

A

Sr

R/W

A

“0” Write

“1” Read

8

1

A

1

A

1

Data (n+1)^thRegister

Data (Last) Register

P

A

S

= Acknowledge (SDA LOW)

= Not Acknowledge (SDA HIGH)

= START condition

From Master to Slave

From Slave to Master

Sr = REPEATED START condition

= STOP condition

P

Figure 13. “Read” Data From DAC/EEPROM – Transfer Format In F/S-Mode

Featuring Register Address Auto-Increment

8.6 Register Maps

The TPS65132 has a non-volatile memory (EEPROM) which contains the initial values and one volatile memory

(Registers) which contains the actual settings. The EEPROM and the Registers are accessed with the same

address.

Startup option: At power-up, the values contained in the EEPROM are loaded into the Registers to the last

stored setting within less than 20 µs. The programmed factory value of the EEPROM of each address is

described in section Factory Default Register Value.

Write description: The user has to program all Registers first (0×00 to 0×03), then set the WED (Write

EEPROM Data) bit to 1. A dead time of 50 ms is then initiated during which the register content or all registers

(0×00 ~ 0×03) are stored into the non-volatile EEPROM cells. During that time, there should be no data flowing

through the I²C because the I²C interface is momentarily not responding.

After the 50 ms have passed, the WED bit is automatically reset to 0, and the user is able to read the values or

program again.

Slave address: 0x3E

X = R/W

R/W = 1 → read mode

R/W = 0 → write mode

8.6.1 Registers

Attempting to read data from register addresses not listed in the following section will result in 0x00 being read

out.

8.6.1.1 VPOS Register – Address: 0x00

Figure 14. VPOS Register

7

RSVD

0

6

RSVD

0

5

RSVD

0

4

3

2

VPOS[4:0]

1

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

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Table 3. VPOS Register Field Descriptions

Bit

Field

Description

7:5

RSVD[2:0]

Reserved, always set to 0

VPOS output voltage adjustment

VPOS[4:0] Value

(binary)

VPOS Output Voltage

VPOS[4:0] Value

(binary)

VPOS Output Voltage

(V)

4.0

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

5.0

(V)

5.1

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

6.0

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

4:0

VPOS[4:0]

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8.6.1.2 VNEG Register – Address 0x01

Figure 15. VNEG Register

7

RSVD

0

6

RSVD

0

5

RSVD

0

4

3

2

VNEG[4:0]

1

0

1

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. VNEG Register Field Descriptions

Bit

Field

Description

7:5

RSVD[2:0]

Reserved, always set to 0

VNEG output voltage adjustment

VNEG[4:0] Value

(binary)

VNEG Output Voltage

(V)

VNEG[4:0] Value

(binary)

VNEG Output Voltage

(V)

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

–4.0

–4.1

–4.2

–4.3

–4.4

–4.5

–4.6

–4.7

–4.8

–4.9

–5.0

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

–5.1

–5.2

–5.3

–5.4

–5.5

–5.6

–5.7

–5.8

–5.9

–6.0

4:0

VNEG[4:0]

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8.6.1.3 DLYx Register – Address 0x02 (Only valid for TPS65132Sx)

Figure 16. DLYx Register

7

DLYP2

0

6

DLYP2

0

5

DLYN2

0

4

DLYN2

0

3

DLYP1

0

2

DLYP1

0

1

DLYN1

0

DLYN1

1

R/W

Table 5. DLYx Register Field Descriptions

Bit

Field

Description

7:6

5:4

3:2

1:0

DLYP2[1:0]

DLYN2[1:0]

DLYP1[1:0]

DLYN1[1:0]

Delay in milliseconds

DLYx Value (binary)

DLYx Delay (ms)

00

01

10

11

0

DLYx[1:0]

1

5

10

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8.6.1.4 APPS - SEQU - SEQD - DISP - DISN Register – Address 0x03

Figure 17. APPS - SEQU - SEQD - DISP - DISN Register

7

RSVD

0

6

APPS

0

5

SEQU

0

4

SEQU

0

3

SEQD

0

2

SEQD

0

1

DISP

1

0

DISN

0

R

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. APPS - SEQU - SEQD - DISP - DISN Field Descriptions

Value

(binary)

Bit

Field

Description

Action

7

RSVD

Reserved, always set to 0

0

1

40mA

80mA

APPS

Application

6

APPS

Value

00

01

10

11

00

01

10

11

0

V_POSand V_NEGsimultaneously (DLYP1 after EN goes HIGH)

V_POS(DLYP1 after EN goes HIGH) and then V_NEG(DLYN1 after V_POS

)

Sequencing at

Startup

SEQU

Value

5:4

SEQU⁽¹⁾

V_NEG(DLYN1 after EN goes HIGH) and then V_POS(DLYP1 after V_NEG

)

V_POSonly

V_POSand V_NEGsimultaneously (DLYP2 after EN goes LOW)

V_POS(DLYP2 after EN goes LOW) and then V_NEG(DLYN2 after V_POS

)

Sequencing at

Shutdown

SEQD

Value

3:2

SEQD⁽¹⁾

V_NEG(DLYN2 after EN goes LOW) and then V_POS(DLYP2 after V_NEG

)

Ignored

No discharge

1

0

DISP⁽²⁾

DISN⁽²⁾

Discharge V_POSDISP Value

Discharge V_NEGDISN Value

1

V_POSactively discharged

No discharge

0

1

V_NEGactively discharged

(1) SEQU and SEQD bits are just valid for TPS65132Sx

(2) See Power-Down And Discharge (LDO) and Power-Down And Discharge (CPN) for a detailed description of how each device variant

implements the active discharge function.

23

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

8.6.1.5 Control Register – Address 0xFF

Figure 18. Control Register

7

6

5

4

3

2

1

0

WED

RSVD[6:1]

EE/(DR)

The Reserved bits are ignored when written and return either 0 or 1 when read.

Table 7. Control Register Field Descriptions

Value

(binary)

Bit

Field

Description

0

No action

7

6:1

0

WED

1

Write EEPROM Data

RSVD[6:1]

EE/(DR)

Reserved

0

1

Read from Registers

Read from EEPROM

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TPS65132

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

8.6.2 Factory Default Register Value

Register address

Part number

0x00

0x0E

0x0A

0x0E

0x0A

0x0C

0x0F

0x0E

0x0A

0x0B

0x0E

0x10h

0x0E

0x01

0x0E

0x0A

0x0E

0x0A

0x0C

0x0F

0x0E

0x0A

0x0B

0x0E

0x10h

0x0E

0x02

—

0x03

0x43

TPS65132A

TPS65132A0

TPS65132B

TPS65132B0

TPS65132B2

TPS65132B5

TPS65132L

TPS65132L0

—

(1)

TPS65132L1

TPS65132S

TPS65132T6

TPS65132W

—

0x00

—

(1) Product preview.

25

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS65132xx devices, primarily intended to supplying TFT LCD displays, can be used for any application

that requires positive and negative supplies, ranging from ±4 V to ±6 V and current up to 80 mA (150 mA for the

TPS65132Sx version). Both output voltages can be set independently and their sequencing is also independent.

The following section presents the different operating modes that the device can support as well as the different

features that the user can select.

9.2 Typical Applications

9.2.1 Low-current Applications (≤ 40 mA)

The TPS65132 can be programmed to 40mA mode with the APPS bit to support applications that require output

currents up to 40 mA (refer to Figure 17). The 40mA mode limits the negative charge pump output current to 40

mA DC in order to provide the highest efficiency possible. The V_POSrail can deliver up to 200 mA DC regardless

of the mode. Output peak currents are supported by the output capacitors.

L

4.7 µH

V_IN

VIN

SW

C1

4.7 µF

V_POS

2.5V to 5.5 V

OUTP

5.4 V/40 mA

C3

REG

ENP

ENN

4.7 µF

C2

4.7 µF

V_NEG

SCL

SDA

OUTN

–5.4 V/40 mA

C5

4.7 µF

PGND

AGND

CFLY1

CFLY2

C4

2.2 µF

Figure 19. Typical Low-current Application Circuit

9.2.1.1 Design Requirements

Table 8. Design Parameters

PARAMETERS

Input Voltage Range

EXAMPLE VALUES

2.5 V to 5.5 V

4.0 V to 6.0 V, –4.0 V to –6.0 V

40 mA

Output Voltages

Output Current Rating

Boost Converter Switching Frequency

1.8 MHz

Negative Charge Pump Switching Frequency

1.0 MHz

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Sequencing

Each output rail (V_POSand V_NEG) is enabled and disabled using an external enable signal. If not explicitly

specified, the enable signal in the rest of the document refers to ENN or ENP: ENP for the positive rail V_POSand

ENN for the negative rail V_NEG. Figure 33 to Figure 36 show the typical sequencing waveforms.

NOTE

In the case where V_INfalls below the UVLO threshold while one of the enable signals is

still high, all converters will be shut down instantaneously and both V_POSand V_NEGoutput

rails will be actively discharged to GND.

9.2.1.2.2 Boost Converter Design Procedure

The first step in the design procedure is to verify whether the maximum possible output current of the boost

converter supports the specific application requirements. A simple approach is to estimate the converter

efficiency, by taking the efficiency number from the provided efficiency curves at the application's maximum load

or to use a worst case assumption for the expected efficiency, e.g., 85%.

V

´ η

IN_min

D = 1 -

1. Duty Cycle:

V

RSEG

V

´ D

IN_min

ΔI =

L

2. Inductor ripple current:

3. Maximum output current:

f_SW´ L

DI_L

æ

ç

ö

I

= I_{LIM_min}

è

+

´ 1-D

(

)

OUT_max

÷

2

ø

I_OUT

DI_L

4. Peak switch current of the application:

I_SWPEAK

=

+

1-D

2

η = Estimated boost converter efficiency (use the number from the efficiency plots or 85% as an estimation)

ƒ_SW= Boost converter switching frequency (1.8 MHz)

L = Selected inductor value for the boost converter (see the Inductor Selection section)

I_SWPEAK= Boost converter switch current at the desired output current (must be < [ I_{LIM_min}+ ΔI_L])

ΔI_L= Inductor peak-to-peak ripple current

V_REG= max (V_POS, |V_NEG|) + 200 mV (in 40mA mode — + 300 mV in 80mA mode — + 500 mV with

TPS65132Sx with SYNC = HIGH)

I_OUT= I_{OUT_VPOS}+ | I_{OUT_VNEG}| (I_{OUT_max}being the maximum current delivered on each rail)

The peak switch current is the current that the integrated switch and the inductor have to handle. The calculation

must be done for the minimum input voltage where the peak switch current is highest.

9.2.1.2.2.1 Inductor Selection (Boost Converter)

Saturation current: the inductor must handle the maximum peak current (I_{L_SAT}> I_SWPEAK, or I_{L_SAT}> [ I_{LIM_min}

ΔI_L] as conservative approach)

+

DC Resistance: the lower the DCR, the lower the losses

Inductor value: in order to keep the ratio I_OUT/ΔI_Llow enough for proper sensing operation purpose, it is

recommended to use a 4.7 µH inductor for 40mA mode (a 2.2 µH might however be used, but the efficiency

might be lower than with 4.7 µH at light loads depending on the inductor characteristics).

27

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

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Table 9. Inductor Selection Boost⁽¹⁾

L

DCR TYP

(mΩ)

I_SAT

(A)

SUPPLIER⁽¹⁾

COMPONENT CODE

EIA SIZE

(µH)

2.2

4.7

Toko

Murata

Toko

1269AS-H-2R2N=P2

LQM2HPN2R2MG0

LQM21PN2R2NGC

1269AS-H-4R7N=P2

LQM21PN4R7MGR

MIPS2520D4R7

1008

0805

1008

0805

1008

130

80

2.4

1.3

0.8

1.6

0.8

0.7

250

230

280

Murata

FDK

(1) See Third-Party Products Disclaimer

9.2.1.2.2.2 Input Capacitor Selection (Boost Converter)

For best input voltage filtering low ESR ceramic capacitors are recommended. TPS65132 has an analog input

pin VIN. A 4.7 µF minimum bypass capacitor is required as close as possible from VIN to GND. This capacitor is

also used as the boost converter input capacitor.

For better input voltage filtering, this value can be increased or two capacitors can be used: one 4.7 µF input

capacitor for the boost converter as well as a 1 µF bypass capacitor close to the VIN pin. Refer to the

Recommended Operating Conditions, Table 10 and Figure 19 for input capacitor recommendations.

9.2.1.2.2.3 Output Capacitor Selection (Boost Converter)

For the best output voltage filtering, low-ESR ceramic capacitors are recommended. A minimum of 4.7 µF

ceramic output capacitor is required. Higher capacitor values can be used to improve the load transient

response. Refer to the Recommended Operating Conditions, Table 10 and Figure 19 for output capacitor

recommendations.

Table 10. Input And Output Capacitor Selection⁽¹⁾

CAPACITOR

(µF)

EIA SIZE (Thickness

max.)

VOLTAGE RATING

(V)

SUPPLIER

Murata

COMPONENT CODE

GRM188R61C225KAAD

GRM188R61C475KAAJ

GRM219R61C106KA73

COMMENTS

2.2

4.7

10

0603 (0.9 mm)

0603 (0.95 mm)

16

C_FLY

C_IN, C_NEG, C_POS

,

Murata

C_REG

Murata

C_NEG, C_REG

(1) See Third-Party Products Disclaimer

9.2.1.2.3 Input Capacitor Selection (LDO)

The LDO input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating

Conditions, Table 10 and Figure 19.

9.2.1.2.4 Output Capacitor Selection (LDO)

The LDO is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended

Operating Conditions, Table 10 and Figure 19.

9.2.1.2.5 Input Capacitor Selection (CPN)

The CPN input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating

Conditions, Table 10 and Figure 19.

9.2.1.2.6 Output Capacitor Selection (CPN)

The CPN is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended

Operating Conditions, Table 10 and Figure 19.

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

9.2.1.2.7 Flying Capacitor Selection (CPN)

The CPN needs an external flying capacitor. The minimum value is 2.2 µF. Special care must be taken while

choosing the flying capacitor as it will directly impact the output voltage accuracy and load regulation

performance. Therefore, a minimum capacitance of 1 µF must be achieved by the capacitor at a DC bias voltage

of │V_NEG│ + 300 mV. For proper operation, the flying capacitor value must be lower than the output capacitor of

the boost converter on REG pin.

9.2.1.3 Application Curves

V_IN= 3.7 V, V_POS= 5.4 V, V_NEG= –5.4 V, unless otherwise noted

Table 11. Component List Used For The Application Curves

REFERENCE

DESCRIPTION

2.2 µF, 16 V, 0603, X5R, ceramic

4.7 µF, 16 V, 0603, X5R, ceramic

10 μF, 16 V, 0603, X5R, ceramic

MANUFACTURER AND PART NUMBER⁽¹⁾

Murata - GRM188R61C225KAAD

Murata - GRM188R61C475KAAJ

C

Murata - GRM188R61E106MA73

Toko - DFE252010C (1269AS-H-2R2N=P2)

Toko - DFE252010C (1269AS-H-4R7N=P2)

Texas Instruments

2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm

4.7 µH, 1.6 A, 250 mΩ, 2.5 mm × 2.0 mm × 1.0 mm

TPS65132AYFF

L

U1

(1) See Third-Party Products Disclaimer

Table 12. Table Of Graphs

PARAMETER

EFFICIENCY

CONDITIONS

Figure

Efficiency vs. Output

Current

± 5.0 V — 40mA Mode — L = 4.7 µH

Figure 20

Figure 21

Figure 22

Figure 23

Efficiency vs. Output

Current

± 5.4 V — 40mA Mode — L = 4.7 µH

± 5.0 V — 40mA Mode — L = 2.2 µH

± 5.4 V — 40mA Mode — L = 2.2 µH

Efficiency vs. Output

Current

Efficiency vs. Output

Current

CONVERTERS WAVEFORMS

V_NEGOutput Ripple

V_POSOutput Ripple

LOAD TRANSIENT

Load Transient

I_NEG= 2 mA / 20 mA / 40 mA — 40mA Mode — C_OUT= 4.7 µF

I_NEG= 2 mA / 20 mA / 40 mA — 40mA Mode — C_OUT= 2 × 4.7 µF

Any load

Figure 24

Figure 25

Figure 26

V_IN= 2.9 V — I_POS= –I_NEG= 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH

V_IN= 3.7 V — I_POS= –I_NEG= 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH

V_IN= 4.5 V — I_POS= –I_NEG= 5 mA → 35 mA → 5 mA — 40mA Mode — L = 4.7 µH

Figure 27

Figure 28

Figure 29

Load Transient

LINE TRANSIENT

Line Transient

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 0 mA — 40mA Mode — L = 4.7 µH

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 5 mA — 40mA Mode — L = 4.7 µH

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 35 mA — 40mA Mode — L = 4.7 µH

Figure 30

Figure 31

Figure 32

Line Transient

29

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

Figure

Table 12. Table Of Graphs (continued)

PARAMETER

CONDITIONS

POWER SEQUENCING

Power-up Sequencing

Power-down Sequencing

Power-up Sequencing

Power-down Sequencing

Simultaneous — no load

Figure 33

Figure 34

Figure 35

Figure 36

Simultaneous — no load with Active Discharge

Sequential — no load

Sequential — no load with Active Discharge

Power-up/down

Sequencing

Simultaneous — no load with Active Discharge

Simultaneous — no load without Active Discharge

Figure 37

Figure 38

Power-up/down

Sequencing

INRUSH CURRENT

Inrush Current

Simultaneous — no load — 40mA Mode

Figure 39

Figure 40

Figure 41

Figure 42

Inrush Current

Sequential — no load — 40mA Mode

Inrush Current

Simultaneous — no load — 40mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx

Sequential — no load — 40mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx

Inrush Current

LOAD REGULATION

V_POSvs Output Current

V_NEGvs Output Current

LINE REGULATION

V_POS= 5.0 V — 40mA Mode — I_POS= 0 mA to 40 mA — L = 4.7 µH and 2.2 µH

V_POS= 5.4 V — 40mA Mode — I_POS= 0 mA to 40 mA — L = 4.7 µH and 2.2 µH

V_NEG= –5.0 V — 40mA Mode — I_NEG= 0 mA to 40 mA — L = 4.7 µH and 2.2 µH

V_NEG= –5.4 V — 40mA Mode — I_NEG= 0 mA to 40 mA — L = 4.7 µH and 2.2 µH

Figure 43

Figure 44

Figure 45

Figure 46

V_IN= 2.5 V to 5.5 V — V_POS= 5.0 V — 40mA Mode — I_POS= 20 mA — L = 4.7 µH and 2.2

µH

V_POSvs Output Voltage

V_NEGvs Output Voltage

Figure 47

Figure 48

Figure 49

Figure 50

V_IN= 2.5 V to 5.5 V — V_POS= 5.4 V — 40mA Mode — I_POS= 20 mA — L = 4.7 µH and 2.2

µH

V_IN= 2.5 V to 5.5 V — V_NEG= –5.0 V — 40mA Mode — I_NEG= 20 mA — L = 4.7 µH and 2.2

µH

V_IN= 2.5 V to 5.5 V — V_NEG= –5.4 V — 40mA Mode — I_NEG= 20 mA — L = 4.7 µH and 2.2

µH

spacer

NOTE

In this section, I_OUTmeans that the outputs are loaded with I_POS= –I_NEGsimultaneously.

100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

VIN = 4.5V

VIN = 3.7V

VIN = 2.8V

60

VIN = 3.7V

55

VIN = 2.8V

50

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

C005

C006

IOUT (mA)

L = 4.7 µH

IOUT (mA)

L = 4.7 µH

± 5.0 V

± 5.4 V

Figure 20. Combined Efficiency — 40mA Mode

Figure 21. Combined Efficiency — 40mA Mode

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TPS65132

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

VIN = 4.5V

VIN = 3.7V

VIN = 2.8V

35

VIN = 4.5V

VIN = 3.7V

VIN = 2.8V

50

0

5

10

15

20

25

30

40

0

5

10

15

20

25

30

35

40

C003

C004

IOUT (mA)

L = 2.2 µH

IOUT (mA)

L = 2.2 µH

± 5.0 V

± 5.4 V

Figure 22. Combined Efficiency — 40mA Mode

Figure 23. Combined Efficiency — 40mA Mode

V_{NEG_AC}[I_NEG= 2mA]

1

R2

R1

1

V_{NEG_AC}[I_NEG= 20mA]

R1

R2

V_{NEG_AC}[I_NEG= 40mA]

20.0mV AC BW

R1

R2

20.0mV AC BW

R1

R2

L = 4.7 µH

C_OUT= 2 × 4.7 µF

L = 4.7 µH

C_OUT= 4.7 µF

Figure 25. V_NEGOutput Voltage Ripple — 40mA Mode

Figure 24. V_NEGOutput Voltage Ripple — 40mA Mode

V_{POS_AC}

1

Figure 26. V_POSOutput Voltage Ripple

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V_{POS_AC}

1

V_{NEG_AC}

2

I_{POS = -}I_NEG

4

V_IN= 2.9 V

ΔI_OUT= 30 mA

V_IN= 3.7 V

ΔI_OUT= 30 mA

Figure 27. Load Transient — 40mA Mode

Figure 28. Load Transient — 40mA Mode

V_{POS_AC}

1

V_{NEG_AC}

2

I_{POS = -}I_NEG

4

3

V_IN

V_IN= 4.5 V

ΔI_OUT= 30 mA

I_OUT= 0 mA

ΔV_IN= 1.7 V

Figure 29. Load Transient — 40mA Mode

Figure 30. Line Transient — 40mA Mode

V_{POS_AC}

1

V_{NEG_AC}

2

3

V_IN

I_OUT= 5 mA

ΔV_IN= 1.7 V

I_OUT= 35 mA

ΔV_IN= 1.7 V

Figure 31. Line Transient — 40mA Mode

Figure 32. Line Transient — 40mA Mode

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TPS65132

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

ENP

ENN

1

ENN

V_REG

R2

V_SW

2

V_POS

V_NEG

V_POS

V_NEG

3

4

3

4

R2

5.0V

R2

5.0V

Figure 33. Power-Up Sequencing — Simultaneous

Figure 34. Power-Down Sequencing — Simultaneous

(with Active Discharge)

ENP

ENN

ENP

1

ENN

R2

V_REG

V_SW

2

V_POS

V_NEG

V_POS

V_NEG

3

4

3

4

5.0V

R2

5.0V

R2

Figure 35. Power-Up Sequencing — Sequential

Figure 36. Power-Down Sequencing — Sequential

(with Active Discharge)

ENP

ENN

ENP

ENN

1

R2

V_SW

2

V_POS

V_NEG

V_POS

V_NEG

3

4

3

4

R2

5.0V

R2

5.0V

Figure 38. Power-Up/Down Without Active Discharge

(TPS65132Ax only)

Figure 37. Power-Up/Down With Active Discharge

33

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V_REG

1

V_POS

V_NEG

2

3

2

3

V_NEG

I_IN

4

Figure 39. Inrush Current — Simultaneous

Figure 40. Inrush Current — Sequential

V_REG

1

V_POS

V_NEG

V_POS

V_NEG

2

3

2

3

I_IN

4

Figure 41. Inrush Current — Simultaneous

(TPS65132B2, –Lx, –Sx, –Tx, –Wx)

Figure 42. Inrush Current — Sequential

(TPS65132B2, –Lx, –Sx, –Tx, –Wx)

5.45

5.44

5.43

5.42

5.41

5.40

5.39

5.38

5.37

5.36

5.35

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

40mA Mode ; 4.7 µH

40mA Mode ; 2.2 µH

40mA Mode ; 4.7 µH

40mA Mode ; 2.2 µH

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

C009

IOUT (mA)

C008

IOUT (mA)

V_POS= 5.4 V

V_POS= 5 V

Figure 44. Load Regulation

Figure 43. Load Regulation

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TPS65132

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

-4.95

-4.96

-4.97

-4.98

-4.99

-5.00

-5.01

-5.02

-5.03

-5.04

-5.35

-5.36

-5.37

-5.38

-5.39

-5.40

-5.41

-5.42

-5.43

-5.44

-5.45

40mA Mode ; 4.7 µH

40mA Mode ; 2.2 µH

40mA Mode ; 4.7 µH

40mA Mode ; 2.2 µH

-5.05

0

5

10

15

20

25

30

35

40

0

5

10

15

20

25

30

35

40

C01

IOUT (mA)

V_NEG= –5 V

V_NEG= –5.4 V

Figure 45. Load Regulation

Figure 46. Load Regulation

5.02

5.42

5.41

5.40

5.39

5.38

5.37

40mA Mode ; 4.7 µH

40mA Mode ; 2.2 µH

40mA Mode ; 4.7 µH

40mA Mode ; 2.2 µH

5.01

5.00

4.99

4.98

4.97

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

C01

VIN (V)

V_POS= 5 V

V_POS= 5.4 V

Figure 47. Line Regulation

Figure 48. Line Regulation

-4.96

-4.97

-4.98

-4.99

-5.00

-5.01

-5.36

40mA Mode ; 4.7 µH

40mA Mode ; 2.2 µH

-5.37

-5.38

-5.39

-5.40

-5.41

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

C01

VIN (V)

V_NEG= –5 V

V_NEG= –5.4 V

Figure 49. Line Regulation

Figure 50. Line Regulation

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9.2.2 Mid-current Applications (≤ 80 mA)

The TPS65132 can be programmed to 80mA mode with the APPS bit to support applications that require output

currents up to 80 mA (refer to Figure 17). The 80mA mode is limiting the negative charge pump (CPN) output

current to 80 mA DC in order to provide the highest efficiency possible where the V_(POS)rail can deliver up to 200

mA DC regardless of the mode. Output peak currents are supported by the output capacitors.

L

2.2 µH

V_IN

VIN

SW

C1

4.7 µF

V_POS

2.5V to 5.5 V

OUTP

5.4 V/80 mA

C3

REG

ENP

ENN

10 µF

C2

10 µF

V_NEG

SCL

SDA

OUTN

–5.4 V/80 mA

C5

10 µF

PGND

AGND

CFLY1

CFLY2

C4

4.7 µF

Figure 51. Typical Mid-current Application Circuit

9.2.2.1 Design Requirements

Table 13. Design Parameters

PARAMETERS

Input Voltage Range

EXAMPLE VALUES

2.5 V to 5.5 V

4.0 V to 6.0 V, –4.0 V to –6.0 V

80 mA

Output Voltages

Output Current Rating

Boost Converter Switching Frequency

1.8 MHz

Negative Charge Pump Switching Frequency

1.0 MHz

9.2.2.2 Detailed Design Procedure

The design procedure for the mid-current applications (80mA mode) is identical to the one for the low-current

applications (40mA mode), except for the BOM (bill of materials). Refer to the Detailed Design Procedure for

details about the sequencing and the general component selection.

9.2.2.2.1 Boost Converter Design Procedure

9.2.2.2.1.1 Inductor Selection (Boost Converter)

In order to keep the ratio I_OUT/ΔI_Llow enough for proper sensing operation purpose, it is recommended to use a

2.2 µH inductor for 80mA mode. For details, see Inductor Selection (Boost Converter).

9.2.2.2.1.2 Input Capacitor Selection (Boost Converter)

A 4.7 µF minimum bypass capacitor is required as close as possible from VIN to GND. This capacitor is also

used as the boost converter input capacitor.

For better input voltage filtering, this value can be increased or two capacitors can be used: one 4.7 µF input

capacitor for the boost converter as well as a 1 µF bypass capacitor close to the VIN pin. Refer to the

Recommended Operating Conditions, Table 10 and Figure 51 for input capacitor recommendations.

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

9.2.2.2.1.3 Output Capacitor Selection (Boost Converter)

For best output voltage filtering low ESR ceramic capacitors are recommended. A minimum of 10 µF ceramic

output capacitor is required. Higher capacitor values can be used to improve the load transient response. Refer

to the Recommended Operating Conditions, Table 10 and Figure 51 for output capacitor recommendations.

9.2.2.2.2 Input Capacitor Selection (LDO)

The LDO input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating

Conditions, Table 10 and Figure 51.

9.2.2.2.3 Output Capacitor Selection (LDO)

The LDO is designed to operate with a 4.7 µF minimum ceramic output capacitor. Refer to the Recommended

Operating Conditions, Table 10 and Figure 51.

9.2.2.2.4 Input Capacitor Selection (CPN)

The CPN input capacitor is also the boost converter output capacitor. Refer to the Recommended Operating

Conditions, Table 10 and Figure 51.

9.2.2.2.5 Output Capacitor Selection (CPN)

The CPN is designed to operate with a 10 µF minimum ceramic output capacitor. Refer to the Recommended

Operating Conditions, Table 10 and Figure 51.

9.2.2.2.6 Flying Capacitor Selection (CPN)

The CPN needs an external flying capacitor. The minimum value is 4.7 µF. Special care must be taken while

choosing the flying capacitor as it will directly impact the output voltage accuracy and load regulation

performance. Therefore, a minimum capacitance of 2.2 µF must be achieved by the capacitor at a DC bias

voltage of │V_NEG│ + 300 mV. For proper operation, the flying capacitor value must be lower than the output

capacitor of the boost converter on REG pin.

9.2.2.3 Application Curves

V_IN= 3.7 V, V_POS= 5.4 V, V_NEG= –5.4 V, unless otherwise noted

Table 14. Component List For Typical Characteristics Circuits

REFERENCE

DESCRIPTION

2.2 µF, 16 V, 0603, X5R, ceramic

4.7 µF, 16 V, 0603, X5R, ceramic

10 μF, 16 V, 0603, X5R, ceramic

2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm

TPS65132AYFF

MANUFACTURER AND PART NUMBER⁽¹⁾

Murata - GRM188R61C225KAAD

Murata - GRM188R61C475KAAJ

Murata - GRM188R61E106MA73

Toko - DFE252010C (1269AS-H-2R2N=P2)

Texas Instruments

C

L

U1

(1) See Third-Party Products Disclaimer

37

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

Figure

Table 15. Table Of Graphs

PARAMETER

EFFICIENCY

CONDITIONS

Efficiency vs. Output

Current

± 5.0 V — 80mA Mode — L = 2.2 µH

± 5.4 V — 80mA Mode — L = 2.2 µH

Figure 52

Figure 53

Efficiency vs. Output

Current

CONVERTERS WAVEFORMS

V_NEGOutput Ripple

V_POSOutput Ripple

LOAD TRANSIENT

Load Transient

I_NEG= 4 mA / 40 mA / 80 mA — 80mA Mode — C_OUT= 10 µF

I_NEG= 4 mA / 40 mA / 80 mA — 80mA Mode — C_OUT= 2 × 10 µF

I_POS= 150 mA — 80mA Mode

Figure 54

Figure 55

Figure 56

V_IN= 2.9 V — I_POS= –I_NEG= 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH

V_IN= 3.7 V — I_POS= –I_NEG= 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH

V_IN= 4.5 V — I_POS= –I_NEG= 10 mA → 70 mA → 10 mA — 80mA Mode — L = 2.2 µH

Figure 57

Figure 58

Figure 59

Load Transient

LINE TRANSIENT

Line Transient

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 0 mA — 80mA Mode — L = 2.2 µH

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 40 mA — 80mA Mode — L = 2.2 µH

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 70 mA — 80mA Mode — L = 2.2 µH

Figure 60

Figure 61

Figure 62

Line Transient

POWER SEQUENCING

Power-up Sequencing

Power-down Sequencing

Power-up Sequencing

Power-down Sequencing

Simultaneous — no load

Figure 63

Figure 64

Figure 65

Figure 66

Simultaneous — no load with Active Discharge

Sequential — no load

Sequential — no load with Active Discharge

Power-up/down

Sequencing

Simultaneous — no load with Active Discharge

Simultaneous — no load without Active Discharge

Figure 67

Figure 68

Power-up/down

Sequencing

INRUSH CURRENT

Inrush Current

Simultaneous — no load — 80mA Mode

Figure 69

Figure 70

Figure 71

Figure 72

Inrush Current

Sequential — no load — 80mA Mode

Inrush Current

Simultaneous — no load — 80mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx

Sequential — no load — 80mA Mode — TPS65132B2, –Lx, –Sx, –Tx, –Wx

Inrush Current

LOAD REGULATION

V_POSvs Output Current

V_NEGvs Output Current

LINE REGULATION

V_POSvs Output Voltage

V_NEGvs Output Voltage

V_POS= 5.0 V — 80mA Mode — I_POS= 0 mA to 80 mA — L = 2.2 µH

V_POS= 5.4 V — 80mA Mode — I_POS= 0 mA to 80 mA — L = 2.2 µH

V_NEG= –5.0 V — 80mA Mode — I_NEG= 0 mA to 80 mA — L = 2.2 µH

V_NEG= –5.4 V — 80mA Mode — I_NEG= 0 mA to 80 mA — L = 2.2 µH

Figure 73

Figure 74

Figure 75

Figure 76

V_IN= 2.5 V to 5.5 V — V_POS= 5.0 V — 80mA Mode — I_POS= 60 mA — L = 2.2 µH

V_IN= 2.5 V to 5.5 V — V_POS= 5.4 V — 80mA Mode — I_POS= 60 mA — L = 2.2 µH

V_IN= 2.5 V to 5.5 V — V_NEG= –5.0 V — 80mA Mode — I_NEG= 60 mA — L = 2.2 µH

V_IN= 2.5 V to 5.5 V — V_NEG= –5.4 V — 80mA Mode — I_NEG= 60 mA — L = 2.2 µH

Figure 77

Figure 78

Figure 79

Figure 80

spacer

NOTE

In this section, I_OUTmeans that the outputs are loaded with I_POS= –I_NEGsimultaneously.

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100

95

90

85

80

75

70

65

60

55

100

95

90

85

80

75

70

65

60

55

50

VIN = 4.5V

VIN = 3.7V

VIN = 2.8V

VIN = 4.5V

VIN = 3.7V

VIN = 2.8V

50

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

C001

C002

IOUT (mA)

± 5 V

L = 2.2 µH

± 5.4 V

L = 2.2 µH

Figure 52. Combined Efficiency — 80mA Mode

Figure 53. Combined Efficiency — 80mA Mode

V_{NEG_AC}[I_NEG= 4mA]

1

R2

R1

1

V_{NEG_AC}[I_NEG= 40mA]

R1

V_{NEG_AC}[I_NEG= 80mA]

R2

V_{NEG_AC}[I_NEG= 80mA]

20.0mV AC BW

R1

R2

20.0mV AC BW

R1

R2

L = 2.2 µH

C_OUT= 2 × 10 µF

L = 2.2 µH

C_OUT= 10 µF

Figure 55. V_NEGOutput Voltage Ripple — 80mA Mode

Figure 54. V_NEGOutput Voltage Ripple — 80mA Mode

V_{POS_AC}

1

Figure 56. V_POSOutput Voltage Ripple

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V_{POS_AC}

1

V_{NEG_AC}

2

4

I_{POS = -}I_NEG

V_IN= 2.9 V

ΔI_OUT= 60 mA

V_IN= 3.7 V

ΔI_OUT= 60 mA

Figure 57. Load Transient — 80mA Mode

Figure 58. Load Transient — 80mA Mode

V_{POS_AC}

1

V_{NEG_AC}

2

4

3

V_IN

I_{POS = -}I_NEG

V_IN= 4.5 V

ΔI_OUT= 60 mA

I_OUT= 0 mA

ΔV_IN= 1.7 V

Figure 59. Load Transient — 80mA Mode

Figure 60. Line Transient — 80mA Mode

V_{POS_AC}

1

V_{NEG_AC}

2

3

V_IN

I_OUT= 40 mA

ΔV_IN= 1.7 V

I_OUT= 70 mA

ΔV_IN= 1.7 V

Figure 61. Line Transient — 80mA Mode

Figure 62. Line Transient — 80mA Mode

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

ENP

ENN

1

ENN

V_REG

R2

V_SW

2

V_POS

V_NEG

V_POS

V_NEG

3

4

3

4

R2

5.0V

R2

5.0V

Figure 63. Power-Up Sequencing — Simultaneous

Figure 64. Power-Down Sequencing — Simultaneous

(with Active Discharge)

ENP

ENN

ENP

1

ENN

R2

V_REG

V_SW

2

V_POS

V_NEG

V_POS

V_NEG

3

4

3

4

5.0V

R2

5.0V

R2

Figure 65. Power-Up Sequencing — Sequential

Figure 66. Power-Down Sequencing — Sequential

(with Active Discharge)

ENP

ENN

ENP

ENN

1

R2

V_SW

2

V_POS

V_NEG

V_POS

V_NEG

3

4

3

4

R2

5.0V

R2

5.0V

Figure 68. Power-Up/Down Without Active Discharge

(TPS65132Ax only)

Figure 67. Power-Up/Down With Active Discharge

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V_REG

1

V_POS

V_NEG

2

3

2

3

V_NEG

I_IN

4

Figure 69. Inrush Current — Simultaneous

Figure 70. Inrush Current — Sequential

V_REG

1

V_POS

V_NEG

V_POS

V_NEG

2

3

2

3

I_IN

4

Figure 71. Inrush Current — Simultaneous

(TPS65132B2, –Lx, –Sx, –Wx)

Figure 72. Inrush Current — Sequential

(TPS65132B2, –Lx, –Sx, –Wx)

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

5.45

5.44

5.43

5.42

5.41

5.40

5.39

5.38

5.37

5.36

5.35

80mA Mode ; 2.2 µH

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

C016

C017

IOUT (mA)

V_POS= 5 V

V_POS= 5.4 V

Figure 73. Load Regulation

Figure 74. Load Regulation

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TPS65132

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

-4.95

-4.96

-4.97

-4.98

-4.99

-5.00

-5.01

-5.02

-5.03

-5.04

-5.35

-5.36

-5.37

-5.38

-5.39

-5.40

-5.41

-5.42

-5.43

-5.44

-5.45

80mA Mode ; 2.2 µH

-5.05

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

0

5

10 15 20 25 30 35 40 45 50 55 60 65 70 75 80

C01

IOUT (mA)

V_NEG= –5 V

V_NEG= –5.4 V

Figure 75. Load Regulation

Figure 76. Load Regulation

5.01

5.41

5.40

5.39

5.38

5.37

5.36

80mA Mode ; 2.2 µH

5.00

4.99

4.98

4.97

4.96

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

C02

VIN (V)

V_POS= 5 V

V_POS= 5.4 V

Figure 77. Line Regulation

Figure 78. Line Regulation

-4.97

-4.98

-4.99

-5.00

-5.01

-5.02

-5.37

80mA Mode ; 2.2 µH

-5.38

-5.39

-5.40

-5.41

-5.42

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

C02

VIN (V)

V_NEG= –5 V

V_NEG= –5.4 V

Figure 79. Line Regulation

Figure 80. Line Regulation

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9.2.3 High-current Applications (≤ 150 mA)

The TPS65132Sx version allows output current up to 150 mA on both V_POSand V_NEGwhen the SYNC pin is

pulled HIGH. If the SYNC pin is pulled LOW, the TPS65132Sx can be programmed to 40mA or 80mA mode with

the APPS bit to lower the output current capability of the V_NEGrail if needed (in the case the efficiency is an

important parameter). See Low-current Applications (≤ 40 mA) and Mid-current Applications (≤ 80 mA) for more

details about the 40mA and 80mA modes.

L

2.2 µH

V_IN

VIN

SW

C1

4.7 µF

V_POS

2.5V to 5.5 V

OUTP

5.4 V/150 mA

C3

REG

EN

10 µF

C2

SYNC

10 µF

V_NEG

SCL

SDA

OUTN

–5.4 V/150 mA

C5

10 µF

PGND

AGND

CFLY1

CFLY2

C4

4.7 µF

Figure 81. Typical Application Circuit For High Current

9.2.3.1 Design Requirements

Table 16. Design Parameters

PARAMETERS

Input Voltage Range

EXAMPLE VALUES

2.5 V to 5.5 V

4.0 V to 6.0 V, –4.0 V to –6.0 V

150 mA

Output Voltages

Output Current Rating

Boost Converter Switching Frequency

1.8 MHz

Negative Charge Pump Switching Frequency

1.0 MHz

9.2.3.2 Detailed Design Procedure

The design procedure and BOM list of the TPS65132Sx is identical to the 80mA mode. Please refer to the Mid-

current Applications (≤ 80 mA) for more details about the general component selection.

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9.2.3.2.1 Sequencing

The output rails (V_POSand V_NEG) are enabled and disabled using an external logic signal on the EN pin. The

power-up and power-down sequencing events are programmable. Please refer to Programmable Sequencing

Scenarios for the different sequencing as well as Registers for the programming options. Figure 98 to Figure 103

show the typical sequencing waveforms.

V_POS

V_NEG

V_POS

Simultaneous

V_IN

EN

V_IN

EN

V_IN

EN

DLYP1

V_POS

V_NEG

V_POS

V_NEG

V_POS

V_NEG

DLYN1

V_IN

EN

V_POS

DLYP2

V_NEG

DLYN2

Figure 82. Programmable Sequencing Scenarios

NOTE

•

In the case where the UVLO falling threshold is triggered while the enable signal is still

HIGH (EN), all converters will be shut down instantaneously and both V_POSand V_NEG

output rails will be actively discharged to GND.

The power-up and power-down sequencing must be finalized (all delays have passed)

before re-toggling the EN pin.

9.2.3.2.2 SYNC = HIGH

When the SYNC pin is pulled HIGH, the boost converter voltage increases instantaneously to allow enough

headroom to deliver the 150 mA. See Figure 88 to Figure 91 for detailed waveforms.

When SYNC pin is pulled LOW, the boost converter keeps its offset for 300 µs typically, and during this time, the

device is still capable if supplying 150 mA on both output rail. After these 300 µs have passed, current limit

settles at 40 mA or 80 mA maximum, depending on the application mode it is programmed to (40mA or 80mA —

see Low-current Applications (≤ 40 mA) and Mid-current Applications (≤ 80 mA) for more details ) and the boost

output voltage regulates down to its nominal value.

9.2.3.2.3 Startup

The TPS65132Sx can startup with SYNC = HIGH, however, the boost offset as well as the 150 mA output

current capability will only be available as soon as the last rail to start is in regulation.

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TPS65132

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9.2.3.3 Application Curves

V_IN= 3.7 V, V_POS= 5.4 V, V_NEG= –5.4 V, unless otherwise noted

Table 17. Component List For Typical Characteristics Circuits

REFERENCE

DESCRIPTION

2.2 µF, 16 V, 0603, X5R, ceramic

MANUFACTURER AND PART NUMBER

Murata - GRM188R61C225KAAD

C

4.7 µF, 16 V, 0603, X5R, ceramic

10 μF, 16 V, 0603, X5R, ceramic

2.2 µH, 2.4 A, 130 mΩ, 2.5 mm × 2.0 mm × 1.0 mm

TPS65132SYFF

Murata - GRM188R61C475KAAJ

Murata - GRM188R61E106MA73

Toko - DFE252010C (1269AS-H-2R2N=P2)

Texas Instruments

L

U1

Table 18. Table Of Graphs

PARAMETER

CONDITIONS

Figure

EFFICIENCY

Efficiency vs.

Output Current

± 5.0 V — SYNC = HIGH — L = 2.2 µH

± 5.4 V — SYNC = HIGH — L = 2.2 µH

Figure 83

Figure 84

Efficiency vs.

Output Current

CONVERTERS WAVEFORMS

V_POSOutput

Ripple

I_POS= 150 mA — SYNC = HIGH

Figure 85

Figure 86

Figure 87

V_NEGOutput

Ripple

I_NEG= 10mA / 80 mA / 150 mA — SYNC = HIGH — C_OUT= 10 µF

I_NEG= 4 mA / 40 mA / 80 mA — SYNC = HIGH — C_OUT= 2 × 10 µF

V_NEGOutput

Ripple

SYNC = HIGH Signal

SYNC = HIGH

I_POS= –I_NEG= 10 mA

Figure 88

Figure 89

I_POS= –I_NEG= 150 mA

SYNC = HIGH

Zoom

I_POS= –I_NEG= 10 mA

Figure 90

Figure 91

SYNC = LOW

Zoom

I_POS= –I_NEG= 10 mA

LOAD TRANSIENT

Load Transient

LINE TRANSIENT

Line Transient

V_IN= 2.9 V — I_POS= –I_NEG= 10 mA → 150 mA → 10 mA — SYNC = HIGH — L = 2.2 µH

V_IN= 3.7 V — I_POS= –I_NEG= 10 mA → 150 mA → 10 mA — SYNC = HIGH — L = 2.2 µH

V_IN= 4.5 V — I_POS= –I_NEG= 10 mA → 150 mA → 10mA — SYNC = HIGH — L = 2.2 µH

Figure 92

Figure 93

Figure 94

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 10 mA — SYNC = HIGH — L = 2.2 µH

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 100 mA — SYNC = HIGH — L = 2.2 µH

V_IN= 2.8 V → 4.5 V → 2.8 V — I_POS= –I_NEG= 150 mA — SYNC = HIGH — L = 2.2 µH

Figure 95

Figure 96

Figure 97

Line Transient

POWER SEQUENCING

Power-up

Sequencing

Simultaneous — no load

Figure 98

Figure 99

Figure 100

Figure 101

Figure 102

Figure 103

Power-down

Sequencing

Simultaneous — no load with Active Discharge

Sequential (V_POS→ V_NEG) — no load

Power-up

Sequencing

Power-down

Sequencing

Sequential (V_NEG→ V_POS) — no load with Active Discharge

Sequential (V_NEG→ V_POS) — no load

Power-up

Sequencing

Power-down

Sequencing

Sequential (V_POS→ V_NEG) — no load with Active Discharge

46

TPS65132

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PARAMETER

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

Table 18. Table Of Graphs (continued)

CONDITIONS

Figure

Power-up/down

Sequencing

Simultaneous — no load without Active Discharge

Figure 104

Power-up/down

Sequencing

Simultaneous — no load with Active Discharge

Figure 105

INRUSH CURRENT

Inrush Current

Simultaneous — no load — SYNC = HIGH — L = 2.2 µH

Sequential — no load — SYNC = HIGH — L = 2.2 µH

Figure 106

Figure 107

Inrush Current

LOAD REGULATION

V_POSvs Output

Current

V_POS= 5.0 V — SYNC = HIGH — I_POS= 0 mA to 150 mA — L = 2.2 µH

Figure 108

Figure 109

Figure 110

Figure 111

V_POSvs Output

Current

V_POS= 5.4 V — SYNC = HIGH — I_POS= 0 mA to 150 mA — L = 2.2 µH

V_NEG= –5.0 V — SYNC = HIGH — I_NEG= 0 mA to 150 mA — L = 2.2 µH

V_NEG= –5.4 V — SYNC = HIGH — I_NEG= 0 mA to 150 mA — L = 2.2 µH

V_NEGvs Output

Current

V_NEGvs Output

Current

LINE REGULATION

V_POSvs Output

Voltage

V_IN= 2.5 V to 5.5 V — V_POS= 5.0 V — SYNC = HIGH — I_POS= 120 mA — L = 2.2 µH

V_IN= 2.5 V to 5.5 V — V_POS= 5.4 V — SYNC = HIGH — I_POS= 120 mA — L = 2.2 µH

V_IN= 2.5 V to 5.5 V — V_NEG= –5.0 V — SYNC = HIGH — I_NEG= 120 mA — L = 2.2 µH

V_IN= 2.5 V to 5.5 V — V_NEG= –5.4 V — SYNC = HIGH — I_NEG= 120 mA — L = 2.2 µH

Figure 112

Figure 113

Figure 114

Figure 115

V_POSvs Output

Voltage

V_NEGvs Output

Voltage

V_NEGvs Output

Voltage

spacer

NOTE

In this section, I_OUTmeans that the outputs are loaded with I_POS= –I_NEGsimultaneously.

47

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100

95

90

85

80

75

70

65

60

55

50

100

95

90

85

80

75

70

65

60

55

50

VIN = 4.5V

VIN = 3.7V

VIN = 2.8V

VIN = 4.5V

VIN = 3.7V

VIN = 2.8V

0

10 20 30 40 50 60 70 80 90 100110120130140150

0

10 20 30 40 50 60 70 80 90 100110120130140150

C02

IOUT (mA)

Figure 83. Combined Efficiency — ± 5.0 V — SYNC = HIGH

L = 2.2 µH

Figure 84. Combined Efficiency — ± 5.4 V — SYNC = HIGH

L = 2.2 µH

V_{NEG_AC}[I_NEG= 10mA]

1

V_{NEG_AC}[I_NEG= 80mA]

V_{POS_AC}

R2

1

V_{NEG_AC}[I_NEG= 150mA]

R1

50.50m.V0mVACACBWBW

50.0mV AC BW

R1R1

R2

Figure 85. V_POSOutput Voltage Ripple — SYNC = HIGH

Figure 86. V_NEGOutput Voltage Ripple — SYNC = HIGH —

L = 2.2 µH — C_OUT= 10 µF

V_{NEG_AC}[I_NEG= 10mA]

1

V_{NEG_AC}[I_NEG= 80mA]

R2

V_{NEG_AC}[I_NEG= 150mA]

R1

50.0mV AC BW

R1

R2

Figure 87. V_NEGOutput Voltage Ripple — SYNC = HIGH —

L = 2.2 µH — C_OUT= 2 × 10 µF

48

TPS65132

www.ti.com.cn

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

SYNC

V_{REG_AC}

1

V_{REG_AC}

2

V_POS

3

V_NEG

4

Figure 88. SYNC Signal — I_OUT= 10 mA

Figure 89. SYNC Signal — I_OUT= 150 mA

SYNC

V_REG

1

2

V_REG

V_POS

3

V_NEG

4

Figure 90. SYNC = HIGH (zoom)

Figure 91. SYNC = LOW (zoom) with Delay

V_{POS_AC}

1

V_{NEG_AC}

2

I_{POS = -}I_NEG

4

Figure 92. Load Transient — V_IN= 2.9 V

Figure 93. Load Transient — V_IN= 3.7 V

SYNC = HIGH — ΔI_OUT= 140 mA

49

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

V_{POS_AC}

1

V_{NEG_AC}

2

I_{POS = -}I_NEG

3

4

V_IN

Figure 94. Load Transient — V_IN= 4.5 V

Figure 95. Line Transient — I_OUT= 10 mA

SYNC = HIGH — ΔV_IN= 1.7 V

SYNC = HIGH — ΔI_OUT= 140 mA

V_{POS_AC}

1

V_{NEG_AC}

2

3

V_IN

Figure 96. Line Transient — I_OUT= 100 mA

Figure 97. Line Transient — I_OUT= 150 mA

SYNC = HIGH — ΔV_IN= 1.7 V

EN

1

EN

1

V_SW

2

V_REG

2

V_POS

V_NEG

3

V_POS

3

4

V_NEG

4

Figure 98. Power-Up Sequencing — Simultaneous

SYNC = HIGH

Figure 99. Power-Down Sequencing — Simultaneous

SYNC = HIGH

50

TPS65132

www.ti.com.cn

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

EN

V_SW

1

EN

1

2

3

V_REG

2

V_POS

V_NEG

3

4

V_NEG

4

Figure 100. Power-Up Sequencing — Sequential

Figure 101. Power-Down Sequencing — Sequential

VPOS → VNEG — SYNC = HIGH

VNEG → VPOS— SYNC = HIGH

EN

V_SW

1

EN

1

2

3

V_REG

2

V_POS

V_NEG

3

4

V_NEG

4

Figure 102. Power-Up Sequencing — Sequential

Figure 103. Power-Down Sequencing — Sequential

VNEG → VPOS — SYNC = HIGH

VPOS → VNEG — SYNC = HIGH

EN

V_SW

EN

V_SW

1

2

3

2

3

V_POS

V_NEG

4

Figure 104. Power-Up/Down Without Active Discharge —

SYNC = HIGH

Figure 105. Power-Up/Down With Active Discharge —

SYNC = HIGH

51

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

V_REG

1

V_POS

V_NEG

2

3

2

3

V_NEG

I_IN

4

Figure 106. Inrush Current — Simultaneous —

SYNC = HIGH

Figure 107. Inrush Current — Sequential

SYNC = HIGH

5.05

5.04

5.03

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

5.45

5.44

5.43

5.42

5.41

5.40

5.39

5.38

5.37

5.36

5.35

SYNC = HIGH_2.2µH

0

10 20 30 40 50 60 70 80 90 100110120130140150

0

10 20 30 40 50 60 70 80 90 100110120130140150

C02

IOUT (mA)

Figure 108. Load Regulation V_POS= 5.0 V — SYNC = HIGH

Figure 109. Load Regulation V_POS= 5.4 V — SYNC = HIGH

-4.95

-5.35

SYNC = HIGH_2.2µH

-4.96

SYNC = HIGH_2.2µH

-5.36

-4.97

-4.98

-4.99

-5.00

-5.01

-5.02

-5.03

-5.04

-5.05

-5.37

-5.38

-5.39

-5.40

-5.41

-5.42

-5.43

-5.44

-5.45

0

10 20 30 40 50 60 70 80 90 100110120130140150

0

10 20 30 40 50 60 70 80 90 100110120130140150

C02

IOUT (mA)

Figure 110. Load Regulation V_NEG= –5.0 V — SYNC =

HIGH

Figure 111. Load Regulation V_NEG= –5.4 V — SYNC =

HIGH

52

TPS65132

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

5.03

-4.97

-4.98

-4.99

-5.00

-5.01

-5.02

-5.03

SYNC = HIGH_2.2 µH

5.02

5.01

5.00

4.99

4.98

4.97

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

C03

VIN (V)

Figure 112. Line Regulation V_POS= 5.0 V — SYNC = HIGH

Figure 113. Line Regulation V_POS= 5.4 V — SYNC = HIGH

-5.37

-4.97

80mA Mode ; 2.2 µH

SYNC = HIGH_2.2 µH

-5.38

-5.39

-5.40

-5.41

-4.98

-4.99

-5.00

-5.01

-5.42

-5.02

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5

C03

VIN (V)

C02

VIN (V)

Figure 115. Line Regulation V_NEG= –5.4 V — SYNC = HIGH

Figure 114. Line Regulation V_NEG= –5.0 V — SYNC = HIGH

10 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 2.5 V and 5.5 V. This input

supply must be well regulated. A ceramic input capacitor with a value of 4.7 μF is a typical choice.

53

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

PCB layout is an important task in the power supply design. Good PCB layout minimizes EMI and allows very

good output voltage regulation. For the TPS65132 the following PCB layout guidelines are recommended.

•

Keep the power ground plane on the top layer (all capacitor grounds and PGND pins must be

connected together with one uninterrupted ground plane).

•

AGND and PGND must be connected together on the same ground plane.

Place the flying capacitor as close as possible to the IC.

Always avoid vias when possible. They have high inductance and resistance. If vias are necessary, always

use more than one in parallel to decrease parasitics especially for power lines.

•

Connect REG pins together.

For high dv/dt signals (switch pin traces): keep copper area to a minimum to prevent making unintentional

parallel plate capacitors with other traces or to a ground plane. Best to route signal and return on same layer.

•

For high di/dt signals: keep traces short, wide and closely spaced. This will reduce stray inductance and

decrease the current loop area to help prevent EMI.

•

Keep input capacitor close to the IC with low inductance traces.

Keep trace from switching node pin to inductor short if possible: it reduces EMI emissions and noise that

may couple into other portions of the converter.

•

Isolate analog signal paths from power paths.

11.2 Layout Example

C5

C2

L1

ENN

OUTN

CFLY2

PGND

CFLY1

REG

ENP

C4

C1

SCL

SDA

19

18

17

20

VIN

16

15

14

13

12

11

1

2

3

4

5

6

PGND

OUTP

REG

SW

AGND

REG

L1

PGND

AGND

C3

PGND

OUTP

C3

C1

PowerPAD

C2

VIN

ENP

ENN

CFLY1

PGND

C4

Via to signal layer on internal or bottom layer.

PGND

7

8

9

10

C5

Via to signal layer on internal or bottom layer.

Figure 117. PCB Layout Example for QFN Package

Figure 116. PCB Layout Example for CSP Package

54

TPS65132

www.ti.com.cn

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

12 器件和文档支持

12.1 器件支持

12.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

12.2 接收文档更新通知

如需接收文档更新通知，请访问 www.ti.com.cn 网站上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册

后，即可每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

12.3 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

55

TPS65132

ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

www.ti.com.cn

13 机械、封装和可订购信息

以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

13.1 CSP 封装概要

CHIP SCALE PACKAGE

(top view)

CHIP SCALE PACKAGE

(bottom view)

E

E2

D2

C2

B2

A2

E3

D3

C3

B3

A3

E1

D1

C1

B1

A1

D

Ball A1

Code:

TI -- TI letters

YM -- Year-Month date code

LLLL -- Lot trace code

S -- Assembly site code

xx -- Revision code (contains alpha-numeric characters - can be left

blank), refer to the Ordering Information section for detailed information)

13.1.1 芯片级封装尺寸

TPS65132 器件采用 15 凸点芯片级封装（YFF，NanoFree™)。封装尺寸如下：

• D = 2108μm ±30μm

• D = 1514μm ±30μm

56

TPS65132

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ZHCSCH4H –JUNE 2013–REVISED NOVEMBER 2016

CSP 封装概要 (接下页)

13.1.2 RVC 封装概要

QFN PACKAGE

(top view)

QFN PACKAGE

(bottom view)

11

13

15

16

12

14

10

17

18

19

20

65132xx

TI YMS

LLLL

PowerPAD

8

7

5

4

3

2

1

Pin 1

Code:

TI -- TI letters

YM -- Year-Month date code

LLLL -- Lot trace code

S -- Assembly site code

xx -- Revision code (contains alpha-numeric characters - can be left

blank), refer to the Ordering Information section for detailed information)

57

PACKAGE OUTLINE

YFF0015

DSBGA - 0.625 mm max height

S

C

A

L

E

6

.

0

DIE SIZE BALL GRID ARRAY

B

E

A

BALL A1

CORNER

D

C

0.625 MAX

SEATING PLANE

0.05 C

0.30

0.12

BALL TYP

0.8 TYP

SYMM

E

D

C

1.6

D: Max = 2.138 mm, Min =2.078 mm

E: Max = 1.544 mm, Min =1.484 mm

TYP

SYMM

B

A

0.4 TYP

0.3

3

1

2

15X

0.2

0.015

C A B

0.4

TYP

4219378/B 05/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YFF0015

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

15X ( 0.23)

(0.4) TYP

2

3

1

A

B

C

SYMM

D

E

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:40X

0.05 MAX

0.05 MIN

METAL UNDER

SOLDER MASK

(

0.23)

METAL

EXPOSED

METAL

EXPOSED

METAL

(

0.23)

SOLDER MASK

OPENING

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4219378/B 05/2020

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YFF0015

DSBGA - 0.625 mm max height

DIE SIZE BALL GRID ARRAY

(0.4) TYP

(R0.05) TYP

3

15X ( 0.25)

1

2

A

B

(0.4) TYP

METAL

TYP

SYMM

C

D

E

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:40X

4219378/B 05/2020

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

PACKAGE OUTLINE

RVC0020A

WQFN - 0.8 mm max height

S

C

A

L

E

3

.

7

0

PLASTIC QUAD FLATPACK - NO LEAD

3.1

2.9

A

B

PIN 1 INDEX AREA

0.45

0.35

4.1

3.9

0.25

0.15

DETAIL

OPTIONAL TERMINAL

TYPICAL

C

0.8 MAX

SEATING PLANE

0.08

0.05

0.00

2X 1.5

SYMM

(0.2) TYP

EXPOSED

THERMAL PAD

7

10

16X 0.5

11

6

2X

SYMM

21

2.5

2.6 0.1

SEE TERMINAL

DETAIL

1

16

0.25

20X

0.15

20

17

PIN 1 ID

(OPTIONAL)

0.1

C A B

1.6 0.1

0.05

0.45

0.35

20X

4219150/B 03/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(1.6)

SYMM

(R0.05)

TYP

17

20

20X (0.6)

1

16

20X (0.2)

(1)

TYP

21

(3.8)

(2.6)

SYMM

16X (0.5)

11

6

(

0.2) TYP

VIA

7

10

(1 TYP)

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219150/B 03/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RVC0020A

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

2X (1.47)

20

17

20X (0.6)

1

21

16

20X (0.2)

(R0.05) TYP

SYMM

2X

(1.15)

(3.8)

(0.675)

TYP

16X (0.5)

11

6

METAL

TYP

7

10

SYMM

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD X

81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219150/B 03/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS65132S
厂家：	TEXAS INSTRUMENTS
描述：	适用于双极小型/中型显示屏的单电感器 - 双路输出电源电感器
文件：	总70页 (文件大小：2784K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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