TPS65137AS [TI]

250mA 双路输出有源矩阵有机发光二极管 (AMOLED) 显示屏电源;


型号：	TPS65137AS
厂家：	TEXAS INSTRUMENTS
描述：	250mA 双路输出有源矩阵有机发光二极管 (AMOLED) 显示屏电源二极管
文件：	总22页 (文件大小：1163K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65137AS

www.ti.com.cn

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

250mA 双路输出有源矩阵有机发光二极管 (AMOLED) 显示屏电源

查询样品: TPS65137AS

特性

说明

•

2.5V 至 4.8V 输入电压范围

0.8% 输出电压精度 V_正向

出色的线路瞬态稳压

TPS65137AS 被设计用于驱动需要正负电压电源轨的

AMOLED 显示屏（有源矩阵有机发光二极管）。此器

件集成了一个具有低压降 (LDO) 后置稳压器的升压转

换器和一个适合于电池供电类产品的反相降压-升压转

换器。数字控制引脚 (CTRL) 允许用数字步进设定负

输出电压。 TPS65137AS 使用一个可实现出色线路和

负载稳压的全新技术。需要使用此技术来避免手机发

送阶段产生的输入电压干扰对 AMOLED 显示屏造成的

影响。

250mA 输出电流

固定 4.6V V_正向输出电压

数字可编程 V_负向，-2.2V 至 -5.2V

_负向的缺省值为 -4.9V

短路保护

热关断

3mm × 3mm 10 引脚四方扁平无引线 (QFN) 封装

应用范围

•

有源矩阵 OLED

典型应用

4.7uH

V_POS

4.6V/250mA

V_IN

2.5V to 4.8V

TPS65137AS

SWP

VIN

4.7PF

PGND

CTRL

OUTP

OUTN

V_NEG

-4.9V/250mA

EN and

Program V_NEG

4.7PF

SWN

GND

4.7PF

100nF

4.7PH

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

English Data Sheet: SLVSB21

TPS65137AS

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

www.ti.com.cn

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION^{(1) (2)}

T_A

PACKAGE⁽²⁾

ORDERABLE PART

NUMBER

TOP-SIDE MARKING

–40°C to 85°C

10-Pin 3x3 QFN

TPS65137ASDSCR

PPGC

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

VALUE

UNIT

MIN

MAX

5.5

–6.5

5.5

3.6

PVIN, SWP, OUTP, CTRL, VL, CB

OUTN

Pin Voltage⁽²⁾

ESD rating

SWN

–6.5

HBM

200

500

CDM

T_J

Operating junction temperature range

Operating ambient temperature range

Storage temperature range

–40

–65

50 °C

T_A

85 °C

T_stg

150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) With respect to GND pin.

THERMAL INFORMATION

TPS65137AS

THERMAL METRIC⁽¹⁾

DSC

UNITS

θ_JA

θ_JB

ψ_JT

ψ_JB

Junction-to-ambient thermal resistance

56.5

25.2

1.0

Junction-to-board thermal resistance

°C/W

Junction-to-top characterization parameter

Junction-to-board characterization parameter

17.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

RECOMMENDED OPERATING CONDITIONS

MIN

2.5

TYP

3.7

MAX UNIT

V_IN

T_A

T_J

Input supply voltage range

4.8

Operating ambient temperature

Operating junction temperature

–40

°C

125

TPS65137AS

www.ti.com.cn

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

ELECTRICAL CHARACTERISTICS

V_IN= 3.7V, CTRL = V_IN, V_POS= 4.6V, V_NEG= –4.9V, T_A= –40°C to 85°C, typical values are at T_A= 25°C (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY CURRENT AND THERMAL PROTECTION

V_IN

I_Q

Input voltage range

2.5

4.8

Operating quiescent current into V_IN

Shutdown current into V_IN

V_POSand V_NEGhave no load⁽¹⁾

CTRL = GND

μA

I_SD

0.1

V_INfalling

2.0

2.3

V_UVLO

Under-voltage lockout threshold

Thermal shutdown

V_INrising

145

°C

OUTPUT V_POS

V_POS

Positive output voltage regulation

–0.8%

0.9

4.6

200

250

1.6

1.2

3.7

0.8%

mΩ

MHz

SWP MOSFET on-resistance

SWP MOSFET rectifier on-resistance

SWP Switching frequency

SWP switch current limit

Short circuit threshold in operation

Leakage current into V_POS

LDO drop out voltage

I_SWP= 200 mA

I_POS= 0 mA

r_DS(ON)

f_SWP

I_SWP

Inductor valley current

V_POSfalling

V_P(SCP)

I_PLEAK

V_DROP

CTRL = GND

µA

I_POS= 100 mA

I_POS= 0 mA

400

%/V

%/A

Line regulation

Load regulation

I_POS= 0 to 250 mA

0.28

OUTPUT V_NEG

V_NEG

Negative output voltage default

–4.9

Negative output voltage range

–2.2

–1%

–5.2

Negative output voltage regulation

–5.2 ≤ V_NEG≤ –4.2

–4.2 < V_NEG≤ –2.2

I_SWN= 200 mA

–1.5%

1.5%

SWN MOSFET on-resistance

SWN MOSFET rectifier on-resistance

SWN switching frequency

200

300

1.7

2.2

420

0.21

r_DS(ON)

mΩ

I_SWN= 200 mA

f_SWN

I_NEG= 100 mA

MHz

I_SWN

SWN switch current limit

V_IN= 2.9 V

1.2

V_N(SCP)

Short circuit threshold in operation

Short circuit threshold in start-up

Short circuit detection time in start-up

Leakage current out of V_NEG

V_NEGPull down resistor before start up

Line regulation

Voltage drop from programmed V_NEG

0.18

0.24

t_N(SCP)

I_NLEAK

R_N(PD)

µA

CTRL = GND

I_NEG= 1 mA

300

%/V

%/A

Load regulation

I_NEG= 0 to 250 mA

0.28

CTRL INTERFACE

V_H

Logic high-level voltage

1.2

V_L

Logic low-level voltage

Pull down resistor

0.4

860

400

150

400

300

kΩ

μs

kΩ

t_INIT

t_OFF

t_HIGH

t_low

Initialization time

Shutdown time period

Pulse high level time period

Pulse low level time period

Data storage/accept time period

C_Tpin output impedance

t_STORE

R_T

150

325

500

(1) With inductor DFE252012C 4.7 µH from TOKO

TPS65137AS

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

www.ti.com.cn

DEVICE INFORMATION

10 PIN TQFN PACKAGE

(TOP VIEW

VIN

PGND

SWP

SWN

Exposed

Thermal Die*

OUTN

CTRL

OUTP

GND

Pin Functions

I/O⁽¹⁾

DESCRIPTION

NO.

NAME

VIN

Input supply for the negative buck-boost converter generating V_NEG

Switch pin of the negative buck-boost converter

Output of negative buck-boost converter

Combined enable and V_NEGprogramming pin.

Sets the settling time for the voltage on V_NEGwhen programmed to a new value

Analog ground

SWN

OUTN

CTRL

GND

OUTP

Output of the boost converter

Internal boost converter bypass capacitor

Switch pin of the boost converter

SWP

PGND

Power ground of boost converter

Exposed thermal die

Connect this pad to analog GND.

(1) G = Ground, I = Input, O = Output

TPS65137AS

www.ti.com.cn

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

FUNCTIONAL BLOCK DIAGRAM

SWP

OUTP

LDO

Softstart

generation

Gate Drive

Current

Sense/

Softstart

Short Circuit

Protection

PGND

SWP

PWM

Vref

Control

Current

Sense/

Softstart

Short Circuit

Protection

OUTN

PWM

Control

5 Bit

DAC

Gate Drive

Digital

Interface

VIN

OUTN

GND

SWN

CTRL

PGND

TPS65137AS

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

www.ti.com.cn

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE

Efficiency versus Output current (Output current is

V_POS= 4.6 V, V_NEG= –4.9 V

Figure 1

from V_POSto V_NEG

)

Startup

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

I_OUT= 100 mA, Boost and BuckBoost

I_OUT= 250 mA, Boost and BuckBoost

I_OUT= 250 mA, Boost

Switch pins and output waveforms (Output current is

from V_POSto V_NEG

)

I_OUT= 250 mA, BuckBoost

EFFICIENCY

OUTPUT CURRENT (V_POS4.6V, V_NEG-4.9V)

STARTUP

100

CTRL

5 V/div

V_POS

5 V/div

V_IN= 4.5V

V_IN= 3.7V

V_IN= 3.3V

V_IN= 2.9V

V_IN= 2.5V

V_NEG

5 V/div

Inductor

TOKO DFE252012C 4.7PH

I_IN

200 mA/div

0.00

0.05

0.10

0.15

0.20

0.25

Output current - A

2 ms/div

Figure 2.

Figure 1.

SWITCH PINS AND OUTPUTS BOOST AND BUCKBOOST,

I_OUT100mA

SWITCH PINS AND OUTPUTS BOOST AND BUCKBOOST,

I_OUT250mA

V_POS

50 mV/div

SW_BOOST

5 V/div

SW_BOOST

5 V/div

V_NEG

50 mV/div

SW_BUCKBOOST

5 V/div

SW_BUCKBOOST

5 V/div

500 ns/div

Figure 3.

Figure 4.

TPS65137AS

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ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

SWITCH PINS AND OUTPUTS BOOST, I_OUT250mA

SWITCH PINS AND OUTPUTS BUCKBOOST, I_OUT250mA

V_POS

50 mV/div

V_NEG

50 mV/div

SW_BUCKBOOST

5 V/div

SW_BOOST

5 V/div

I_{L_BUCKBOOST}

500 ma/div

I_{L_BOOST}

200 ma/div

500 ns/div

Figure 5.

Figure 6.

TPS65137AS

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

www.ti.com.cn

APPLICATION FOR TYPICAL CHARACTERISTICS

4.7uH

V_POS

4.6V/250mA

V_IN

2.5V to 4.8V

TPS65137AS

SWP

VIN

4.7PF

PGND

CTRL

OUTP

OUTN

V_NEG

-4.9V/250mA

EN and

Program V_NEG

4.7PF

SWN

GND

4.7PF

100nF

4.7PH

Figure 7. Application for Typical Characteristics

Table 1. Bill of Materials for Typical Characteristics

Value

4.7 µF, X5R

100 nF, X7R

4.7 µH

Part Number

Manufacturer

C1, C2, C3, C5

GRM21BR61C475KA88

GRM21BR71E104KA01

DFE252012C 4.7 µH

Murata

TOKO

L1, L2

TPS65137AS

www.ti.com.cn

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

DETAILED DESCRIPTION

The TPS65137AS consists of a boost converter using an LDO as post regulator and an inverting buck-boost

converter. The positive output is fixed at 4.6V. The negative output is programmable by a digital interface in the

range of –2.2V to –5.2V, the default is –4.9V. The transition time of the negative output is adjustable by the CT

pin capacitor.

SOFT START and START-UP SEQUENCE

The device has a soft start to limit the in-rush current. When the device is enabled by the CTRL pin going HIGH,

the boost converter starts with a reduced switch current limit. 8ms after CTRL going HIGH, the buck-boost

converter starts with the default value of –4.9V. The typical start-up sequence is shown in Figure 8.

V_POS

CTRL

10ms Typ.

V_NEG

Figure 8. Start-up Sequence

SHORT CIRCUIT PROTECTION

The device is protected against short circuits of the outputs to ground and short circuit of the outputs to each

other. During normal operation, an error condition is detected if V_POSfalls below 3.7V for more than 3ms or V_NEG

gets above 420mV above the programmed value for more than 3ms. In either case, the device goes into

shutdown and this state is latched. The input and the outputs are disconnected. To resume normal operation, V_IN

has to cycle below UVLO or CTRL has to toggle LOW and HIGH.

During start up, an error condition is detected in the following cases:

•

V_POSis not in regulation 10ms after CTRL goes HIGH.

V_NEGis higher than threshold level 10ms after CTRL goes HIGH.

V_NEGis not in regulation 20ms after CTRL goes HIGH.

In the above cases, the device goes into shutdown and this state is latched. The input and the outputs are

disconnected. To resume normal operation, VIN has to cycle below UVLO or CTRL has to toggle LOW and

HIGH.

ENABLE (CTRL PIN)

The CTRL pin serves two functions. One is to enable and disable the device the other is the output voltage

programming of the device. If the digital interface is not required the CTRL pin can be used as a standard enable

pin for the device and the device will come up with its default value on V_NEGof –4.9V. When CTRL is pulled high,

the device is enabled. The device is shut down with CTRL low.

DIGITAL INTERFACE (CTRL)

The digital interface allows programming the negative output voltage V_NEGin digital steps. If the digital output

voltage setting is not required then the CTRL pin can also be used as a standard enable pin.

TPS65137AS

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

www.ti.com.cn

The digital output voltage programming of V_NEGis implemented by a simple digital interface with the timing

shown in Figure 9.

t_INIT

t_OFF

t_STORE

t_HIGH

t_LOW

High

CTRL

Low

V_POS

V_NEG

4.62V

t_SCP

t_SET

-4.9V

-5.0V

Figure 9. Digital Interface Using CTRL

Once CTRL is pulled high the device will come up with its default voltage of –4.9V. The device has a 6-bit DAC

implemented with the corresponding output voltages as given in the table below. The interface counts now the

rising edges applied to the CTRL pin once the device is enabled. For the example above, V_NEGis programmed to

–5.0V since 3 rising edges are detected. Other output voltages can be programmed according Table 2.

Table 2. Programming Table for V_NEG

BIT/RISING EDGES

V_NEG

DAC VALUE

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

BIT/RISING EDGES

V_NEG

DAC VALUE

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

0/ no pulse

–4.9 V

–5.2 V

–5.1 V

–5.0 V

–4.9 V

–4.8 V

–4.7 V

–4.6 V

–4.5 V

–4.4 V

–4.3 V

–4.2 V

–4.1 V

–4.0 V

–3.9 V

–3.8 V

–3.7 V

–3.6 V

–3.5 V

–3.4 V

–3.3 V

–3.2 V

–3.1 V

–3.0 V

–2.9 V

–2.8 V

–2.7 V

–2.6 V

–2.5 V

–2.4 V

–2.3 V

–2.2 V

TPS65137AS

www.ti.com.cn

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

SETTING TRANSITION TIME t_setfor V_NEG(C_T)

The device allows setting the transition time t_setusing an external capacitor connected to pin CT. The transition

time is the time period required to move V_NEGfrom one voltage level to the next programmed voltage level. The

capacitor connected to pin CT does not influence the soft start time t_ssof the V_NEGdefault value. When the CT

pin is left open then the shortest possible transition time is programmed. When connecting a capacitor to the CT

pin then the transition time is given by an R-C time constant. This is given by the output impedance of the CT pin

typically 325kΩ and the external capacitance. Within one τ the output voltage V_NEGhas reached 70% of its

programmed value. An example is given when using 100nF for C_T.

τ ≈ t_set70%= 325 kΩ × C_T= 325 kΩ × 100 nF = 32.5 mS

The output voltage is almost at its programmed value after 3τ.

PCB LAYOUT

Figure 10 and Figure 11 show an example of a PCB layout design.

1. Place the input capacitor on VIN and the output capacitor on OUTN as close as possible to the device.

Use short and wide traces to connect the input capacitor to VIN and the output capacitor to OUTN.

2. Place the output capacitor on OUTP and the capacitor on CB as close as possible to the device.

Use short and wide traces to connect the output capacitor to OUTP.

3. Connect the ground of the CT capacitor to the GND pin, pin 6, directly.

4. Connect the input ground and the output ground on the same board layer, not through vias.

Figure 10. Example of PCB Layout Design (Top layer)

TPS65137AS

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

www.ti.com.cn

Figure 11. Example of PCB Layout Design (Bottom layer)

Figure 12. Schematic for the Example of PCB Layout Design

TPS65137AS

www.ti.com.cn

ZHCSBI8B –AUGUST 2011–REVISED SEPTEMBER 2013

4.7uH

V_POS

4.6V/250mA

V_IN

2.5V to 4.8V

TPS65137AS

SWP

VIN

4.7PF

PGND

CTRL

OUTP

OUTN

V_NEG

-4.9V/250mA

EN and

Program V_NEG

SWN

GND

4.7PF

100nF

4.7PH

Figure 13. Typical Application Circuit

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS65137ASDSCR

ACTIVE

WSON

DSC

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 85

PPGC

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65137ASDSCR

WSON

DSC

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

WSON DSC 10

SPQ

Length (mm) Width (mm) Height (mm)

552.0 346.0 36.0

TPS65137ASDSCR

3000

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TUBE

T - Tube

height

L - Tube length

W - Tube

width

B - Alignment groove width

*All dimensions are nominal

Device

Package Name Package Type

DSC WSON

Pins

SPQ

L (mm)

W (mm)

T (µm)

B (mm)

TPS65137ASDSCR

3000

381

4.83

2286

Pack Materials-Page 3

PACKAGE OUTLINE

DSC0010J

WSON - 0.8 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.8

0.7

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

(0.2) TYP

EXPOSED

THERMAL PAD

4X (0.25)

SYMM

2.4 0.1

8X 0.5

0.30

0.18

10X

SYMM

PIN 1 ID

0.1

C A B

(OPTIONAL)

0.05

0.5

0.3

10X

4221826/D 08/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DSC0010J

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

10X (0.24)

(2.4)

(3.4)

SYMM

(0.95)

8X (0.5)

(R0.05) TYP

(

0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4221826/D 08/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

DSC0010J

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

10X (0.6)

(1.53)

10X (0.24)

(1.06)

SYMM

(0.63)

8X (0.5)

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4221826/D 08/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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TPS65137AS [TI]

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