TPS65154RSLR [TI]
集成 WLED 驱动器的 LCD 偏置 IC | RSL | 48 | -40 to 85;
| 型号： | TPS65154RSLR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 集成 WLED 驱动器的 LCD 偏置 IC | RSL | 48 | -40 to 85 驱动 CD 接口集成电路 驱动器 |
| 文件： | 总88页 (文件大小：3165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS65154
ZHCSF63A –SEPTEMBER 2013–REVISED JUNE 2016
TPS65154 集成 WLED 驱动器的 LCD 偏置 IC
1 器件概述
1.1 特性
1
• 2.0V 至 5.5V 输入电压范围
• 同步升压转换器 (AVDD
• 非同步升压转换器 (VGH
• 低压降线性稳压器 (VCC
• 面板复位信号 (XAO)
• T-CON 复位信号 (RST)
• 具有写保护的片上 EEPROM
• I2C 接口
)
)
)
• 集成缓冲器放大器的可编程 VCOM 校准器
• 热关断
• 6 通道 WLED 驱动器，支持直接调光和相移调光模
式
• 48 引脚、6mm × 6mm、0.4mm 间距 VQFN
• 栅极电压整形
1.2 应用范围
•
笔记本电脑
•
平板电脑
1.3 说明
TPS65154 是一款紧凑型 LCD 偏置解决方案，此解决方案主要用于笔记本电脑和平板电脑。此器件配有两
个能够为 LCD 面板的源极驱动器和栅极驱动器供电的升压转换器、一个提供系统逻辑电压的线性稳压器、
一个带有高速放大器的可编程 VCOM 以及一个 6 通道 WLED 驱动器，并且具备栅极电压整形功能。
间距
器件信息(1)
封装
器件型号
封装尺寸（标称值）
TPS65154
VQFN (48)
6.00mm × 6.00mm
(1) 要了解所有可用封装，请见数据手册末尾的可订购产品附录。
1.4 简化系统图
VIN (2.0V to 5.5V)
AVDD (6.5V to 9.6V)
VGH (18V to 25.5V)
VGHM
Boost Converter 1
Boost Converter 2
AVDD
VGH
Gate Voltage
Shaping
VCC (1.0V to 2.5V)
VGL (–5V to –8V)
VCOM
VIN
Linear Regulator
Negative Charge Pump
AVDD
Programmable
VCOM Buffer
RST
XAO
I2C
Miscellaneous
Boost Converter 3
WLED Driver
VLED (4.5V to 24V)
<38 V
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSBG2
TPS65154
ZHCSF63A –SEPTEMBER 2013–REVISED JUNE 2016
www.ti.com
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用范围 .............................................. 1
1.3 说明 ................................................... 1
1.4 简化系统图............................................ 1
修订历史记录............................................... 2
Pin Configuration and Functions..................... 3
Specifications ............................................ 5
4.1 Absolute Maximum Ratings .......................... 5
4.2 ESD Ratings.......................................... 5
4.3 Recommended Operating Conditions ................ 5
4.4 Thermal Information .................................. 6
4.5 Electrical Characteristics ............................. 7
4.6 Timing Requirements................................. 9
Detailed Description ................................... 12
5.1 Overview ............................................ 12
5.2 Functional Block Diagram........................... 12
5.3 Feature Description ................................. 14
5.4 Device Functional Modes ........................... 22
5.5 Programming ........................................ 26
5.6 Register Map ........................................ 38
Application and Implementation .................... 63
6.1 Application Information.............................. 63
6.2 Typical Application .................................. 63
Power Supply Recommendations .................. 75
Layout .................................................... 76
8.1 Layout Guidelines ................................... 76
8.2 Layout Example ..................................... 76
器件和文档支持 .......................................... 78
9.1 器件支持............................................. 78
9.2 接收文档更新通知 ................................... 78
9.3 社区资源............................................. 78
9.4 商标.................................................. 78
9.5 静电放电警告 ........................................ 78
9.6 Glossary ............................................. 78
6
2
3
4
7
8
9
5
10 机械、封装和可订购信息 ............................... 79
10.1 封装信息............................................. 79
2 修订历史记录
Changes from Original (September 2013) to Revision A
Page
•
•
已更改 数据表为数据手册格式 ...................................................................................................... 1
已添加 器件信息表，ESD 额定值表，特性 描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局
部分，器件和文档支持部分以及机械、封装和可订购信息部分。............................................................... 1
2
修订历史记录
Copyright © 2013–2016, Texas Instruments Incorporated
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TPS65154
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ZHCSF63A –SEPTEMBER 2013–REVISED JUNE 2016
3 Pin Configuration and Functions
NC
BSUP
AVDD
AVDD
SW1
1
2
3
4
5
6
7
8
9
36 NC
35 OVP
34 SW3
33 PGND
32 IFB1
31 IFB2
30 IFB3
29 IFB4
28 IFB5
27 IFB6
26 AGND
25 NC
PGND
VIN
Thermal Pad
VCC
PGND
SW2 10
VGH 11
NC 12
Figure 3-1. RSL Package, 48-Pin VQFN (Top View)
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NC
NO.
1
N/A
P
No internal connection.
BSUP
AVDD
AVDD
SW1
PGND
VIN
2
Positive supply for the VCOM buffer.
Boost converter 1 output voltage sense.
Boost converter 1 rectifier output.
Boost converter 1 switch pin.
3
P
4
P
5
P
6
P
Ground.
7
P
Positive supply.
VCC
PGND
SW2
VGH
NC
8
P
Linear regulator output.
9
P
Ground.
10
11
12
13
14
15
16
17
18
19
20
P
Boost converter 2 switch pin.
P
VGH regulation point and positive supply for gate voltage shaping function.
No internal connection.
N/A
N/A
P
NC
No internal connection.
VGHM
RE
Gate voltage shaping output.
I/O
I/O
I/O
P
Gate votlage shaping discharge resistor connection.
Gate votlage shaping flicker clock input.
Internal linear regulator compensation network connection.
Negative charge pump output and VGL regulation point.
Negative charge pump flying capacitor connection.
Negative charge pump flying ccapacitor connection.
FLK
COMP2
VGL
C1A
P
C1B
P
Copyright © 2013–2016, Texas Instruments Incorporated
Pin Configuration and Functions
3
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ZHCSF63A –SEPTEMBER 2013–REVISED JUNE 2016
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Pin Functions (continued)
PIN
TYPE
DESCRIPTION
NAME
RST
NO.
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Pad
I/O
I/O
I/O
N/A
N/A
P
Reset generator output.
Panel discharge generator output.
XAO
ISET
NC
WLED driver current-setting resistor connection.
No internal connection.
NC
No internal connection.
AGND
IFB6
IFB5
IFB4
IFB3
IFB2
IFB1
PGND
SW3
OVP
NC
Ground.
I/O
I/O
I/O
I/O
I/O
I/O
P
WLED driver channel 6 output.
WLED driver channel 5 output.
WLED driver channel 4 output.
WLED driver channel 3 output.
WLED driver channel 2 output.
WLED driver channel 1 output.
Ground.
P
WLED driver boost converter switch pin.
WLED driver boost converter output voltage sensing pin.
No internal connection.
I/O
N/A
N/A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
NC
No internal connection.
PWM
EN
WLED driver PWM input.
WLED driver enable input.
WLED driver boost converter compensation network connection.
EEPROM write protect input.
I2C data.
COMP3
WP
SDA
SCL
I2C clock.
NEG
VCOM
COMP1
BGND
NC
VCOM buffer inverting input.
VCOM buffer output.
Boost converter 1 compensation network connection.
Ground.
N/A
P
No internal connection.
GND
Ground.
4
Pin Configuration and Functions
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ZHCSF63A –SEPTEMBER 2013–REVISED JUNE 2016
4 Specifications
4.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.3
–0.3
–0.3
–0.3
–10
MAX
7
UNIT
V
VIN, VCC, SCL, SDA, FLK, WP, XAO, COMP1
AVDD, SW1, VCOM, NEG, BSUP, RST
EN, PWM
12
V
20
V
COMP2, COMP3, ISET
3.6
12
V
Pin voltage
C1A, C1B
V
VGL
–10
0.3
40
V
SW3, OVP
–0.3
–0.3
V
IFB1, IFB2, IFB3, IFB4, IFB5, IFB6, VGH, VGHM, RE, SW2
30
V
Pin current
SW2
TBD
85
A
Ambient temperature, TA
Junction temperature, TJ
Storage temperature, TSTG
–40
–40
–65
°C
°C
°C
150
150
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
700
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
4.3 Recommended Operating Conditions
MIN NOM MAX UNIT
Normal operation
2.0
2.6
5.5
5.5
11
VIN
Input voltage range
V
EEPROM programming
dVIN/dt
VBSUP
VBAT
VIN rise time
0.45
6.5
ms
V
Input voltage range
Input voltage range
9.6
24
4.5
V
dVBAT/dt VBAT rise time
0.45
11
ms
LINEAR REGULATOR (VCC
)
VCC
IICC
Output voltage
Output current
1.0
4.7
6.5
2.5
300
22
V
mA
µF
COUT
Output capacitance
10
BOOST CONVERTER 1 (AVDD
)
AVDD
IAVDD
L
Boost converter 1 output voltage range
Boost converter 1 output current at VIN = 3.7 V
Inductance
9.6
400
15
V
mA
µH
µF
4.7
4.7
10
10
COUT
Boost converter 1 output capacitance
22
BOOST CONVERTER 2 (VGH
)
AVDD
VGH
IGH
Input voltage range
6.5
18
9.6
25.5
25
V
V
Output voltage range
Output current
mA
Copyright © 2013–2016, Texas Instruments Incorporated
Specifications
5
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Recommended Operating Conditions (continued)
MIN NOM MAX UNIT
L
Inductance
4.7
1
10
15
10
µH
µF
COUT
Output capacitance
4.7
NEGATIVE CHARGE PUMP (VGL
)
VGL
Output voltage
–5
–8
25
V
IGL
Output current
mA
µF
µF
CFLY
COUT
Flying capacitance
Output capacitance
0.5
0.5
5
BOOST CONVERTER 3 (WLED)
VOUT
IOUT
L
Output voltage
Output current
Inductance
38
250
15
V
mA
µH
µF
4.7
2.2
10
COUT
Output capacitance
4.7
10
INTERNAL REGULATOR
COUT Capacitance connected to the TCOMP pin
1
µF
4.4 Thermal Information
TPS65154
RSL (VQFN)
48 PIN
29.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
15.8
Junction-to-board thermal resistance
5.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.2
ψJB
5.1
RθJC(bot)
0.8
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.
6
Specifications
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ZHCSF63A –SEPTEMBER 2013–REVISED JUNE 2016
4.5 Electrical Characteristics
VIN = 3.3 V, VLED = 12 V, VCC = 2.5 V, AVDD = 8 V, VGL = –6.8 V, VGH = 20 V, TA = −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
POWER SUPPLY
IIN
Supply current into VIN pin
Supply current into AVDD pins
Supply current into BSUP pin
Supply current into VGH pin
Converters not switching
0.1
0.75
2.5
1
2.5
5
mA
mA
mA
mA
IAVDD
IBSUP
IGH
Pins 2 and 3 connected together
No load on VGHM
0.1
1
UNDERVOLTAGE LOCKOUT
VIN falling
VIN rising
1.75
90
Undervoltage lockout threshold
V
VUVLO
2.2
Hysteresis
LINEAR REGULATOR (VCC
mV
)
Linear regulator output voltage range
Tolerance
1.0
–3%
60%
25%
300
250
10
2.5
+3%
75%
40%
V
VCC
ICC = 10 mA
VCC falling
VCC falling
VUVP
VSCP
Undervoltage protection threshold
Short circuit protection threshold
70%
30%
TJ = 25°C to 125°C
TJ = –40°C
ILIM
Current limit
VCC = 5% below value at 10 mA.
mA
rDS(ON)
Active pull-down resistance
21
35
Ω
BOOST CONVERTER 1 (AVDD
)
Output voltage range
Tolerance
6.5
–2%
60%
25%
9.6
+2%
75%
35%
0.25
3.6
V
AVDD
VUVP
VSCP
rDS(ON)
ILIM
Undervoltage protection threshold
Short-circuit protection threshold
Switch ON resistance
Switch current limit
70%
30%
0.1
ISW = 1 A
ISW = 1 A
Ω
A
2.4
3.0
rDS(ON)
Rectifier ON resistance
Switching frequency
Tolerance
0.25
0.4
Ω
400
1000
+20%
kHz
fSW
–20%
NEGATIVE CHARGE PUMP (VGL
)
Output voltage range
VGL
–5
–3%
65%
25%
50
–8
3.5%
75%
35%
150
160
1.0
V
Output voltage tolerance
VUVP
VSCP
Undervoltage protection threshold
Short-circuit protection threshold
VGL rising
70%
30%
VGL rising
C1B sinking
C1B sourcing
IDRVN
Maximum drive current
mA
60
VDO
Dropout voltage
fSW = 500 kHz, CFLY = 0.5 µF, IGL = 10 mA
0.6
500
3
V
fSW
Switching frequency
Discharge ON resistance
400
2.1
600
3.9
kHz
kΩ
rDS(ON)
IMEAS = 2 mA
BOOST CONVERTER 2 (VGH
)
Output voltage range
Tolerance
18
–3%
65%
25%
25.5
3%
75%
35%
1.0
V
VGH
VUVP
Undervoltage protection threshold
Short-circuit protection threshold
Switch ON resistance
Maximum tON time
VGH falling
VGH falling
ISW = 1 A
70%
30%
0.3
2
VSCP
rDS(ON)
tON(MAX)
tOFF
Ω
1
2
2.5
µs
µs
tOFF time
2.7
4
BOOST CONVERTER 3
VOUT Output voltage range
ILIM
VLED+2
2.0
38
3.7
V
A
Ω
Switch current limit
2.7
0.2
rDS(ON)
Switch ON resistance
ISW = 1 A
0.35
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Specifications
7
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Electrical Characteristics (continued)
VIN = 3.3 V, VLED = 12 V, VCC = 2.5 V, AVDD = 8 V, VGL = –6.8 V, VGH = 20 V, TA = −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
30
TYP MAX
UNIT
OVP range
39
+5%
0.6
V
VOVP
Tolerance
-5%
VIL
EN low input voltage
EN high input voltage
EN input hysteresis
EN falling
EN rising
V
V
V
VIH
1.5
VIH – VIL
0.09
0.16
0.27
RPULL-
EN pull-down resistance
450
750 1250
kΩ
DOWN
WLED DIMMING
Maximum current
40
mA
bits
IFB
Channel-to-channel current matching
Output dimming resolution
–3%
+3%
10
DMIN
DHYS
Minimum output duty cycle
1%
–0.048
%
0.048
%
Input PWM jitter hysteresis
VSET
KSET
VIL
ISET regulation voltage
ISET multiplication constant
PWM low input voltage
–3%
1.0
+3%
V
1260 1296 1332
PWM falling
PWM rising
0.6
V
V
V
VIH
PWM high input voltage
PWM input voltage hysteresis
1.2
VIH – VIL
0.09
450
0.16
0.27
RPULL-
PWM pull-down resistance
750 1250
kΩ
DOWN
RESET (RST)
VOL
IOH
Output voltage
Leakage current
IRST = 1 mA (sinking)
VRST = 1.8 V
0.2
0.5
1
V
µA
PROGRAMMABLE VCOM
VCOM DAC set zero-scale error
VMIN = 07h, VMAX = 07h
VMIN = 07h, VMAX = 07h
−7
–1
–1
−7
–1
−1
7
1
1
7
1
1
1
1
1
SETZSE
SETFSE
DNL
VMAX DAC set zero-scale error
VMIN DAC set zero-scale error
VCOM set full-scale error
VMAX set full-scale error
LSB
LSB
LSB
VMIN set full-scale error
VCOM
VMAX
VMIN
Differential nonlinearity
Closed-loop; AV = –1; RF = 1 kΩ, RIN = 1 kΩ, VCM = 4 V; VSIGNAL
= 63 mVpp; RL = ∞
BW
Small-signal bandwidth
Peak output current
21
MHz
mA
Open-loop; VPOS = 4 V, VNEG = 3 V
Open-loop; VPOS = 4 V, VNEG = –5 V
Open-loop; VPOS = 4 V, VNEG = 5 V
Open-loop; VPOS = 4 V, VNEG = 3 V
Closed-loop; AV = +1; RF = 1 MΩ; VPOS = 4 V
VNEG = 3 V
400
330
36
IOUT
SR
Slew rate
V/µs
μA
V
33
IIB–
Input bias current (inverting input)
Output voltage drop
−1
1
0.1
0.1
0.06
0.03
Open-loop; VPOS = 4 V; IMEAS
10 mA
=
VDROP
VNEG = 5 V
GATE VOLTAGE SHAPING
rDS(ON)H VGH to VGHM ON resistance
VGH = 20 V, IGHM = 10 mA, VFLK = 1.8 V
VGHM = 20 V, IGHM = 10 mA, VFLK = 0 V
VGHM = 6 V, IGHM = 10 mA, VFLK = 0 V
VFLK falling
13
26
26
25
50
50
Ω
Ω
rDS(ON)L
VGHM to RE ON resistance
VIL
FLK low input voltage threshold
FLK high input voltage threshold
FLK input hysteresis
0.6
V
V
V
VIH
VFLK rising
1.2
VIH – VIL
0.09
0.15
0.27
8
Specifications
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Electrical Characteristics (continued)
VIN = 3.3 V, VLED = 12 V, VCC = 2.5 V, AVDD = 8 V, VGL = –6.8 V, VGH = 20 V, TA = −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
PARAMETER
FLK low input current
FLK high input current
TEST CONDITIONS
MIN
–100
–100
TYP MAX
100
UNIT
nA
IIL
VFLK = 0 V
IIH
VFLK = 1.8 V
100
nA
PANEL RESET (XAO)
VOL(XAO) Output voltage
ILK(XAO)
IXAO = 1 mA (sinking)
VXAO = 1.8 V
0.16
0.5
1
V
µA
V
Leakage current
XAO Threshold voltage range
Tolerance
VUVLO
–3%
0.05
3.0
+3%
0.3
VIN falling
VIN rising
VDET
Hysteresis
V
I2C INTERFACE
Configuration parameters slave address
74h
28h
ADDR
Programmable VCOM slave address
Low level input voltage
High level input voltage
Input hysteresis
VIL
SCL or SDA falling, standard and fast modes
SCL or SDA rising, standard and fast modes
0.6
V
V
VIH
1.0
VIH – VIL
VOL
0.05
V
Low level output voltage
Input capacitance
Sinking 3 mA
0.36
10
V
CI
pF
Standard mode
Fast mode
400
400
CB
Capacitive load on SDA and SCL
pF
EEPROM
VIL
WP low input voltage threshold
WP high input voltage threshold
WP input voltage hysteresis
WP internal pull-up resistor
Number of write cycles
VWP falling
VWP rising
0.8
V
V
VIH
1.2
0.1
VIH – VIL
RPULL-UP
NWRITE
0.03
20
0.05
60
V
100
kΩ
1000
100
Data retention
Storage temperature = 150 °C
1000 hrs
°C
THERMAL SHUTDOWN
Thermal shutdown temperature
Thermal shutdown hysteresis
150
10
TSD
4.6 Timing Requirements
VIN = 3.3 V, VLED = 12 V, VCC = 2.5 V, AVDD = 8 V, VGL = –6.8 V, VGH = 20 V, TA = −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
MIN
TYP
MAX
UNIT
LINEAR REGULATOR (VCC
)
Linear regulator start-up delay time
Tolerance
0
75
ms
tDLY1
–20%
30%
BOOST CONVERTER 1 (AVDD
)
Boost converter 1 soft-start duration range
Tolerance
0.5
–20%
0
75
30%
75
ms
ms
tSS2
Boost converter 1 start-up delay range
Tolerance
tDLY2
–20%
30%
NEGATIVE CHARGE PUMP (VGL
)
Negative charge pump soft-start duration
Tolerance
0
–20%
0
35
30%
35
ms
ms
tSS3
Negative charge pump start-up delay
Tolerance
tDLY3
–20%
30%
BOOST CONVERTER 2 (VGH
)
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Timing Requirements (continued)
VIN = 3.3 V, VLED = 12 V, VCC = 2.5 V, AVDD = 8 V, VGL = –6.8 V, VGH = 20 V, TA = −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
MIN
0
TYP
MAX
35
UNIT
Boost converter 2 soft-start duration range
Tolerance
ms
tSS4
–20%
30%
BOOST CONVERTER 3
Switching frequency range
Tolerance
WLED DIMMING
tPWMIN Input pulse width
400
1000
20%
kHz
fSW
–20%
500
0.1
ns
Direct dimming
DPWM dimming
15
22
Output frequency range
kHz
fOUT
15
Tolerance
–20%
0.1
20%
15
fIN
Input frequency range
PWM and direct dimming modes
kHz
ms
RESET (RST)
Reset pulse duration range
Tolerance
0
15
tRST
Measured from end of VCC's ramp to 50% of
RST's rising edge with a 10 kΩ pull-up resistor.
–20%
20%
GATE VOLTAGE SHAPING
tPLH
VGHM rising, VFLK = 0 V/1.8 V, 50% thresholds,
CVGHM = 150 pF, RE = 0 Ω
92
88
200
200
Propagation delay
ns
tPHL
VGHM falling, VFLK =0 V/1.8 V, 50% thresholds,
CVGHM = 150 pF, RE = 0 Ω
tDLY4
Gate voltage shaping start-up delay range
Tolerance
PANEL RESET (XAO)
Panel reset duration range
0
35
ms
–20%
30%
0
35
ms
ms
tDLY6
Measured from VIN = VDET to 50% of XAO's
rising edge with a 10-kΩ pull-up resistor.
Tolerance
–20%
30%
TIMING
tUVP
Undervoltage protection timeout
40
50
60
I2C INTERFACE
Standard mode
Fast mode
100
400
fSCL
Clock frequency
kHz
µs
Standard mode
Fast mode
4.7
1.3
4.0
0.6
4.7
1.3
tLOW
Clock low period
Clock high period
Standard mode
Fast mode
tHIGH
µs
Bus free time between a
STOP and a START
condition
Standard mode
Fast mode
tBUF
µs
Standard mode
Fast mode
4.0
0.6
Hold time for a repeated
START condition
thd:STA
tsu:STA
tsu:DAT
thd:DAT
µs
µs
ns
µs
Standard mode
Fast mode
4.0
Set-up time for a repeated
START condition
0.6
Standard mode
Fast mode
250
100
0.05
0.05
Data set-up time
Data hold time
Standard mode
Fast mode
3.45
0.9
10
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Timing Requirements (continued)
VIN = 3.3 V, VLED = 12 V, VCC = 2.5 V, AVDD = 8 V, VGL = –6.8 V, VGH = 20 V, TA = −40°C to 85°C. Typical values are at 25°C
(unless otherwise noted).
MIN
20+0.1CB
20+0.1CB
TYP
MAX
1000
1000
UNIT
Rise time of SCL after a
repeated START condition
and after an ACK bit
Standard mode
Fast mode
tRCL1
ns
Standard mode
Fast mode
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
20+0.1CB
4.0
1000
300
300
300
1000
300
300
300
tRCL
Rise time of SCL
Fall time of SCL
Rise time of SDA
Fall time of SDA
ns
ns
ns
ns
µs
Standard mode
Fast mode
tFCL
Standard mode
Fast mode
tRDA
Standard mode
Fast mode
tFDA
Standard mode
Fast mode
Set-up time for STOP
condition
tsu:STO
0.6
EEPROM
tWRITE
Write time
100
ms
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5 Detailed Description
5.1 Overview
The TPS65154 device integrates the bias and backlight functions needed by an active matrix liquid crystal
display.
The LCD bias functions comprise
•
•
•
•
•
•
•
•
A synchronous boost converter to generate AVDD
A non-synchronous boost converter to generate VGH
An inverting charge pump to generate VGL
An low dropout linear regulator to generate VCC
A gate-voltage shaping function
A programmable VCOM buffer
XAO and RST signals
An I2C programming interface
The backlight driver functions comprise
•
•
A non-synchronous boost converter
A six-channel WLED driver with PWM dimming
The device configuration is stored in an on-chip nonvolatile memory, which can be programmed via an I2C
interface.
5.2 Functional Block Diagram
Figure 5-1 shows a top-level block diagram of the TPS65154.
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VIN
7
SW1
5
VIN
3
4
AVDD
AVDD
COMP2 17
LDO
AVDD
To internal blocks
œ
PWM
Control
DAC
+
WP 41
SDA 42
SCL 43
I2C
Interface
6
PGND
46 COMP1
10 SW2
VCC
8
LDO
DAC
+
PWM
Control
œ
9
PGND
VGH
RST 21
XAO 22
Sequencing
VIN
VUVLO
VDET
11
Gate
Voltage
Shaping
Control
OVP 35
SW3 34
14 VGHM
PWM
Control
PGND 33
15 RE
+
Vref
EN 39
16 FLK
18 VGL
œ
COMP3 40
AVDD
IFB1 32
IFB2 31
IFB3 30
IFB4 29
IFB5 28
IFB6 27
19 C1A
20 C1B
+
œ
œ
DAC
+
Only one channel
shown in detail
DAC
2
BSUP
DAC
+
+
1 V
45 VCOM
47 BGND
44 NEG
Dimming
Control
PWM 37
œ
œ
DAC
23
26
ISET AGND
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Figure 5-1. Top-Level Block Diagram
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5.3 Feature Description
The following sections describe the features of the TPS65154.
5.3.1 Linear Regulator (VCC)
The linear regulator is supplied directly from the VIN pin, and its output voltage can be programmed to
1.0 V, 1.2 V, 1.89 V, or 2.5 V using the VCC register.
VCC
VCC
VIN
COUT
+
–
VCC
DAC
Copyright © 2016, Texas Instruments Incorporated
Figure 5-2. Linear Regulator Block Diagram
5.3.1.1 Power-Up (Linear Regulator)
The linear regulator starts tDLY1 milliseconds after the supply voltage exceeds the undervoltage lockout
threshold (VIN > VUVLO). It does not have a soft-start function, and its output ramps up as fast as the
supply voltage slew rate and the linear regulator's output capacitance allow.
5.3.1.2 Power-Down (Linear Regulator)
The linear regulator is turned off as soon as the supply voltage falls below the undervoltage lockout
threshold (VIN < VUVLO). VCC is actively discharged during power-down.
5.3.1.3 Protection (Linear Regulator)
The linear regulator is protected against short-circuits and undervoltage conditions. An undervoltage
condition is detected if the linear regulator's output falls below 70% of its programmed voltage for longer
than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the linear regulator's
output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-
circuit detection has no time delay associated with it). To recover normal operation following either an
undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR
applied.
5.3.2 Boost Converter 1 (AVDD)
Boost converter 1 is synchronous and uses a virtual current mode topology that:
•
•
achieves high efficiencies;
allows the converter to work in continuous conduction mode under all operating conditions, simplifying
compensation; and
•
provides true input-output isolation when the boost converter is disabled.
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VIN
L
AVDD
VIN
SW1
Q1B
AVDD
AVDD
COUT
PWM
Control
–
+
AVDD
DAC
Q1A
GND
COMP1
RCOMP
CCOMP
Copyright © 2016, Texas Instruments Incorporated
Figure 5-3. Boost Converter 1 Internal Block Diagram
Boost converter 1's switching frequency can be programmed to 400 kHz, 600 kHz, 800 kHz, or 1 MHz
using the FSW1 register. Its output voltage can be programmed from 6.5 V to 9.6 V in 100 mV steps using
the AVDD register.
Boost converter 1 uses an external compensation network connected to the COMP1 pin to stabilize its
feedback loop. A simple series R-C network connected between the COMP1 pin and ground is sufficient
to achieve good performance, that is, stable and with good transient response. Good starting values,
which will work for most applications, are 25 kΩ and 3.9 nF.
In some applications (for example, those using electrolytic output capacitors), it may be necessary to
include a second compensation capacitor between the COMP1 pin and ground. This has the effect of
adding an additional pole in the feedback loop's frequency response, which cancels the zero introduced by
the output capacitor's ESR.
The synchronous topology of boost converter 1 ensures that AVDD is fully isolated from VIN when the
converter is disabled.
5.3.2.1 Power-Up (Boost Converter 1)
Boost converter 1 starts tDLY2 milliseconds after RST goes high. Delay time tDLY2 can be programmed from
0 ms to 75 ms using the DLY2 register.
To minimize inrush current during start-up, boost converter 1 ramps its output voltage in tSS2 milliseconds.
Start-up time tSS2 can be programmed from 0.5 ms to 75 ms using the SS2 register. Longer soft-start
times generate lower inrush currents.
5.3.2.2 Power-Down (Boost Converter 1)
Boost converter 1 is disabled when VIN<VUVLO. When disabled, boost converter 2 actively discharges
AVDD by turning on Q2.
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5.3.2.3 Protection (Boost Converter 1)
Boost converter 1 is protected against short-circuits and undervoltage conditions. An undervoltage
condition is detected if the boost converter's output falls below 70% of its programmed voltage for longer
than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the boost converter's
output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-
circuit detection has no time delay associated with it). To recover normal operation following either an
undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR
applied.
5.3.3 Boost Converter 2 (VGH)
Boost converter 2 is non-synchronous and uses a constant off-time topology. The converter's switching
frequency is not constant but adapts itself to VIN and VGH. Boost converter 2 uses peak current control and
is designed to operate permanently in discontinuous conduction mode (DCM), thereby allowing the
internal compensation circuit to achieve stable operation over a wide range of output voltages and
currents. Boost converter 2's output voltage can be programmed from 18 V to 25.5 V using the VGH
register.
L
AVDD
VGH
COUT
AVDD
VGH
SW2
PWM
Control
–
+
DAC
VGH
GND
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Figure 5-4. Boost Converter 2 Block Diagram
5.3.3.1 Power-Up (Boost Converter 2)
Boost converter 2 is enabled as soon as VGL has finished ramping down. To minimize inrush current
during start-up, boost converter 2 ramps VGH linearly to its programmed value in tSS4 seconds. Soft-start
time tSS4 can be programmed from 0.256 ms to 35 ms using the SS4 register. Because boost converter 2
is non-synchronous, its output is already equal to AVDD (minus the voltage drop across its rectifier diode)
before it starts switching, which means that the time during which VGH is actually ramping during start-up
is less than the actual programmed soft-start time (see Figure 5-5).
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VGH
AVDD
tSS4
tDLY3 + tSS3
Figure 5-5. Boost Converter 2 Soft-Start
5.3.3.2 Power-Down (Boost Converter 2)
Boost converter 2 is disabled when VIN<VUVLO. The converter's output is not actively discharged when the
converter is disabled.
5.3.3.3 Protection (Boost Converter 2)
Boost converter 2 is protected against short-circuits and undervoltage conditions. An undervoltage
condition is detected if the boost converter's output falls below 70% of its programmed voltage for longer
than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the boost converter's
output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-
circuit detection has no time delay associated with it). To recover normal operation following either an
undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR
applied.
5.3.4 Negative Charge Pump (VGL)
The negative charge pump inverts AVDD and regulates its output to the voltage set by the VGL register.
VGL can be programmed from –5 V to –8 V in 0.2 V steps using the VGL register, however, since the
negative charge pump inverts AVDD to generate its output, the most negative voltage that can be
generated is approximately –AVDD+1 V. Thus, if AVDD = 8.0 V, the usable range of VGL is approximately –5
V to –7 V. If VGL is programmed to a more negative voltage than this the charge pump may not be able to
regulate its output. This will not damage the IC, but performance may be impaired.
The negative charge pump in the TPS65154 is fully integrated and requires only two external capacitors to
operate (a flying capacitor connected between the C1A and C1B pins, and an output capacitor connected
between the VGL pin and ground).
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AVDD
C1A
Osc.
CFLY
C1B
VGL
DAC
VGL
IDRVN
VGL
COUT
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Figure 5-6. Negative Charge Pump Block Diagram
5.3.4.1 Power-Up (Negative Charge Pump)
The negative charge pump starts tDLY3 milliseconds after boost converter 1 (AVDD) starts ramping and
ramps its output linearly from zero to its programmed output voltage in tSS3 ms. Delay time tDLY3 can be
programmed from 0 ms to 35 ms using the DLY3 register. Soft-start time tSS3 can be programmed from
0 ms to 35 ms using the SS3 register.
5.3.4.2 Power-Down (Negative Charge Pump)
The negative charge pump is disabled when the supply voltage falls below the undervoltage lockout
threshold (VIN<VUVLO). During power-down the charge pump's output is actively discharge to GND.
5.3.4.3 Protection (Negative Charge Pump)
The negative charge pump is protected against short-circuits and undervoltage conditions. An
undervoltage condition is detected if the charge pump's output falls below 70% of its programmed voltage
for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the charge
pump's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately
(short-circuit detection has no time delay associated with it). To recover normal operation following either
an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR
applied.
5.3.5 Gate Voltage Shaping
The gate voltage shaping function can be used to reduce image sticking in LCD panels by modulating the
LCD panel's gate ON voltage (VGH). Figure 5-7 shows a block diagram of the gate voltage shaping
function and Figure 5-8 shows the typical waveforms during operation.
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VGH
Q1
VGHM
Control
Logic
FLK
Q2
Q3
Q4
RE
AVDD
Copyright © 2016, Texas Instruments Incorporated
Figure 5-7. Gate Voltage Shaping Block Diagram
VPG4
FLK
Don’t Care
VGH
tDLY4
VGHM
AVDD
GND
Figure 5-8. Gate Voltage Shaping Waveforms
Gate voltage shaping is controlled by the FLK input. When FLK is high, Q1 is on, Q2, Q3 and Q4 are off,
and VGHM is equal to VGH. On the falling edge of FLK, Q1 is turned off, Q2 and Q3 are turned on, and the
LCD panel load connected to the VGHM pin discharges through the external resistor connected to the RE
pin.
During power-up, Q1, Q2 and Q3 are held off and Q4 is turned on, pulling the VGHM pin pulled to GND,
regardless of the state of the FLK signal, until tDLY4 milliseconds after boost converter 2 (VGH) has finished
ramping. The value of tDLY4 can be programmed from 0 ms to 35 ms using the DLY4 register.
During power-down Q1 is held permanently on and Q2, Q3 and Q4 permanently off, regardless of the
state of the FLK signal.
5.3.6 Panel Discharge (XAO)
The TPS65154 provides an output signal via its XAO pin that can be used to drive the outputs of the
display panel's gate driver IC high during power-down. The XAO pin is pulled low whenever VIN<VDET. The
VDET threshold voltage can be configured using the VDET register.
The XAO output is an open-drain type and requires an external pull-up, typically in the range 10 kΩ to
100 kΩ.
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5.3.7 Reset Generator (RST)
The RST pin generates an active-low reset signal for the rest of the system. During power-up, the reset
timer starts when VCC has finished ramping. The reset pulse duration tRST can be programmed from 0 ms
to 15 ms using the RESET register. The RST signal is latched when it goes high and will not be taken low
again until the device is powered down (even if VCC temporarily falls out of regulation). The active power-
down threshold (VUVLO or VDET) can be selected using the RMODE bit in the CONFIG register.
The RST output is an open-drain type that requires an external pull-up resistor. Pull-up resistor values in
the range 10 kΩ to 100 kΩ are recommended for most applications.
5.3.8 Programmable VCOM
The programmable VCOM uses three digital-to-analog converters (DACs) to generate a VCOM voltage that
is subsequently buffered by a high-speed op-amp. The maximum value of VCOM is set by the 4-bit VMAX
register, and can be programmed in the range 2.5/8×AVDD to 4/8×AVDD. The minimum value of VCOM is
set by the 4-bit VMIN register, and can be programmed in the range 2/8 × AVDD to 3.5/8 × AVDD. Note, for
proper operation, VMAX must be greater than VMIN. By programming the 7-bit VCOM parameter, users
can adjust the VCOM voltage appearing at the OUT pin between VMIN and VMAX as follows:
+ (VMAX - VMIN )×VCOM
127
VCOM = VMIN
(1)
where VCOM is the value stored in the Wiper Register (see Figure 5-9).
AVDD
BSUP
4/8×AVDD
VMAX
DAC
2.5/8×AVDD
+
–
VCOM
NEG
VCOM
DAC
VCOM
3.5/8×AVDD
Feedback from
display panel
VMIN
DAC
2/8×AVDD
BGND
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Figure 5-9. Programmable VCOM Block Diagram
The programmable VCOM function has three registers. The volatile Wiper Register (WR) contains the
value currently output by the programmable VCOM DAC; this value is lost when power to the device is
removed. The non-volatile Initial Value Register (IVR) contains the value loaded into the DAC every time
the device is powered up. The Control Register (CR) determines whether data is written to or read from
the WR, the IVR, or both. If the CR contains 00h, during write operations data is stored in the WR and the
IVR, and during read operations data is read from the IVR. If the CR contains 80h, data is written to and
read from the WR register only. 00h and 80h are the only valid values for the CR. Table 5-1 shows the
programmable VCOM's register address map.
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Table 5-1. Programmable VCOM Register Address Map
REGISTER ADDRESS
NON-VOLATILE
Initial Value Register (IVR)
Not Used
VOLATILE
00h
02h
Wiper Register (WR)
Control Register (CR)
5.3.8.1 Operational Amplifier Performance
Like most op-amps, the VCOM op-amp in the TPS65154 is not designed to drive purely capacitive loads, so
it is not recommended to connect a capacitor directly to its output in an attempt to increase performance;
however, the op-amp is capable of delivering high peak currents that make such capacitors unnecessary
in most applications.
High-speed op amps such as the one in the TPS65154 require care when using them. The most common
problem is when parasitic capacitance at the inverting input creates a pole with the feedback resistor,
reducing amplifier stability. Two things can be done to minimize the likelihood of this happening. Both of
these work by shifting the pole (which can never be completely eliminated) to a frequency outside the op
amp's bandwidth, where it has no effect.
•
Reduce the value of the feedback resistor. In applications where no feedback from the panel is used,
the feedback resistor can be made zero. In applications where a non-zero feedback resistor has to be
used, a small capacitor (between 10 pF and 100 pF) across the feedback resistor will minimize ringing.
•
Minimize the parasitic capacitance at the op amp's inverting input. This is achieved by using short PCB
traces between the feedback resistor and the inverting input, and by removing ground planes and other
copper areas above and below this PCB trace.
5.3.8.2 Power-Up (Programmable VCOM)
The programmable VCOM is enabled when AVDD > VUVLO2
.
5.3.8.3 Power-Down (Programmable VCOM)
During power-down, the programmable VCOM continues to operate until AVDD < VUVLO2
.
5.3.9 WLED Driver
5.3.9.1 WLED Boost Converter
The WLED boost converter boosts a 4.5 V to 24 V supply VBAT to a higher voltage to supply the LED
strings connected to the WLED driver. It uses a fixed-frequency, current-mode topology. The converter's
output voltage is automatically adjusted to maintain the lowest feedback voltage (IFB1 to IFB6) between
450 mV and 750 mV, thus ensuring sufficient headroom for the output current sinks, but without
dissipating excessive power in the IC. This approach automatically compensates for changes in the LED
string voltage, for example, because of temperature effects. The WLED boost converter's switching
frequency can be programmed to 400 kHz, 600 kHz, 800 kHz, and 1 MHz using the FSW3 register.
The WLED boost converter features a soft-start circuit to limit inrush current when the converter starts.
The duration of the soft-start ramp depends on the value of the capacitor connected to the COMP3 pin.
Note, that because the converter is a non-synchronous type, its output voltage before it starts switching is
equal to VBAT (minus the voltage drop across its rectifier).
5.3.9.2 Current Sinks
The brightness of the LED strings is determined by the average current flowing through each string, which
is the product of the output duty cycle and the current sink's output current. The output current of all
current sinks is the same and is set by the external resistor connected between the ISET pin and ground:
VSET
IMAX
=
×KSET
RSET
(2)
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where:
•
•
•
VSET is the voltage on the ISET pin
RSET is the resistance between the ISET pin and GND
KSET is a constant
When the TPS65154 measures zero current flowing in one of the IFB pins it determines that the string is
open and automatically disables that output. The WLED boost converter's output voltage is subsequently
regulated according to the remaining operational strings. If an application uses fewer than six LED strings,
it is recommended to connected the unused outputs to ground; this ensures the most rapid detection of
the unused strings. Once open strings have been detected, they remain disabled until a POR occurs or
EN is toggled.
5.3.9.3 Protection
The WLED boost converter and dimming circuits feature a variety of protection schemes to ensure reliable
operation when subjected to various failure modes. These protection schemes are listed in Table 5-2.
Table 5-2. WLED Driver Protection
ERROR
DETECTION
ACTION
RECOVERY
VOVP exceeds programmed
threshold
(30 V, 33 V, 36 V or 39 V)
WLED boost converter output
regulated to programmed
threshold
WLED boost converter output
voltage too high
None required
WLED boost converter switch
current too high
Switch automatically re-enabled
at start of next switching cycle
ISW > ILIM
Switch turned off
Disable all output channels and
boost converter
Output channels re-enabled
following power cycle
All LED strings open-circuit
IIFB = 0 mA and VOUT = VOVP
IIFB = 0 mA and VOUT = VOVP
IIFB = 0 mA for longer than 4 ms
Individual LED string(s) open-
circuit
Disable affected output
channel(s)
Functional output channels
continue operating.
Affected output channel(s) re-
enabled following power cycle
Individual LED string(s) shorted-
circuited to ground
5.3.9.4 Enable and Start-Up
The WLED driver is enabled and disabled by EN, however, this signal has no effect until the LCD bias
functions have completed their start-up sequence. Following a POR, EN has no effect until tDLY4 is
complete; after that the WLED driver can be enabled and disabled at any time using EN (providing nothing
happens to cause the LCD bias functions to re-start) and applying a PWM signal. In applications that do
not generate an EN signal, the EN pin can be tied to VIN, in which case the WLED driver will start
automatically at the end of tDLY4. Note, that a permanently low PWM signal (0% duty cycle) will prevent
boost converter 3 from starting-up.
When the WLED driver is enabled it first checks the status of IFB1 to IFB6 and shuts down any channels
that it detects are disabled/unused. These channels will be subsequently ignored until a POR occurs or
EN is toggled.
5.3.10 Undervoltage Lockout
An undervoltage lockout function disables the IC when the supply voltage is too low for proper operation.
5.4 Device Functional Modes
5.4.1 Dimming Modes
The TPS65154 support direct dimming and phase-shift dimming modes. The active dimming mode can be
selected using the DMODE bit in the CONFIG register.
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5.4.1.1 Direct Dimming
When direct dimming is selected, the output current sinks are controlled directly by the PWM signal. In this
mode, they are turned on and off together, at the same frequency and duty cycle as the PWM signal (see
Figure 5-10).
PWM
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
Figure 5-10. Direct Dimming
5.4.1.2 Phase-Shift Dimming
When phase-shift dimming mode is selected, the output dimming frequency does not depend on the
frequency of the PWM signal but can be independently programmed from 15 kHz to 22 kHz using the
FDIM register. In this mode, the duty cycle information contained in the PWM signal is extracted and re-
used to generate up to six outputs, at the output frequency set by the FDIM register, and phase-shifted
with respect to each other by 360°/N, where N is the number of outputs in use (see Figure 5-11). Using
phase-shifted outputs, the maximum load current step is reduced by the same factor N, resulting in
reduced voltage ripple on the boost converter's output and consequently lower audible noise.
PWM
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
Figure 5-11. Phase-Shift Dimming
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5.4.2 Power Sequencing
Figure 5-12 shows the typical power-up/down characteristic of the TPS65154.
5.4.2.1 Power-Up
VCC starts ramping tDLY1 seconds after VIN > VUVLO
.
RST is initially held low. tRST seconds after VCC has finished ramping RST goes high.
AVDD starts ramping tDLY2 seconds after RST has gone high.
VGL starts ramping tDLY3 seconds after AVDD starts ramping.
VGH starts ramping as soon as VGL has finished ramping.
VGHM is initially held low (connected to RE). tDLY4 seconds after VGH has finished ramping, gate voltage
shaping is enabled and VGHM follows the state of FLK.
XAO is initially held low. tDLY6 seconds after VIN>VDET XAO goes high.
The WLED driver is enabled by the logical AND of AVDD (that is, AVDD has finished ramping) and EN.
5.4.2.2 Power-Down
VCC, AVDD, VGH and VGL are disabled when VIN<VUVLO
.
XAO goes low when VIN falls below the threshold selected for it (VUVLO or VDET).
RST goes low when VIN falls below the threshold selected for it (VUVLO or VDET).
The WLED driver is turned off when EN = 0 or VIN < VUVLO
.
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VIN>VDET
VIN
VIN>VDET
VIN>VUVLO1
VIN>VUVLO1
tDLY1
VCC
tRST
RST
RMODE=0
RMODE=1
RST
AVDD
tDLY2
tSS2
tSS3
tDLY3
VGL
tSS4
VGH
tDLY4
AVDD
VGHM
AVDD>VUVLO2
AVDD<VUVLO2
VCOM
tDLY6
XAO
If EN goes high before AVDD, WLED
boost starts when AVDD finishes ramping
EN
VLED
If EN goes high after AVDD, WLED
boost starts on rising edge of EN
EN
VLED
Figure 5-12. Power Up/Down Sequencing
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5.5 Programming
5.5.1 Configuration
The TPS65154 divides the configuration parameters into two categories:
•
•
Configuration parameters
VCOM
In typical applications, all configuration parameters except VCOM are programmed by the subcontractor
during PCB assembly, and VCOM is programmed by the display manufacturer during display calibration.
5.5.1.1 General
Configuration parameters can be changed by writing the desired values to the appropriate RAM
register(s). The RAM registers are volatile and their contents are lost when power is removed from the
device. By writing to the Control Register, it is possible to store the active configuration in non-volatile
EEPROM; during power-up, the contents of the EEPROM are copied into the RAM registers and used to
configure the device.
5.5.1.1.1 I2C Interface
The TPS65154 features an industry-standard I2C interface that supports both Standard and Fast modes of
operation.
5.5.1.1.2 Slave Addresses
The configuration parameters are all accessed using slave address 74h and the VCOM is accessed using
slave address 28h.
5.5.1.1.3 Write Protect
An active-high Write Protect pin (WP) prevents the configuration parameters from being changed by
accident. This pin is internally pulled high and must be actively pulled low to access to the EEPROM or
RAM registers. Note that the WP pin disables all I2C traffic to the TPS65154, and must also be pulled low
during read operations. This is to ensure that noise present on the I2C lines does not erroneously
overwrite the active configuration stored in RAM (which would not be protected by a simple EEPROM
write-protect scheme). The write protect function can be enabled and disabled using the WPEN bit in the
CONFIG register. Note that once the write protect function is enabled it is not possible to disable again it
without pulling the WP pin low. For this reason, it is strongly recommended that applications include some
way to pull the WP pin low (for example, a test pad), even if it is not normally used.
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5.5.2 Programming Examples (Excluding VCOM)
5.5.2.1 Writing to a Single RAM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65154 acknowledges
4. Bus master sends address of RAM register (00h)
5. TPS65154 acknowledges
6. Bus master sends data to be written
7. TPS65154 acknowledges
8. Bus master sends STOP condition
E8h
00h
DATA
RAM Register Address
RAM Register Data
P
S
7-Bit Slave Address
0
A
A
A
Figure 5-13. Writing to a Single RAM Register
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5.5.2.2 Writing to Multiple RAM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h).
3. TPS65154 acknowledges
4. Bus master sends address of first RAM register to be written to (00h)
5. TPS65154 acknowledges
6. Bus master sends data to be written to first RAM register
7. TPS65154 acknowledges
8. Bus master sends data to be written to RAM register at next higher address (auto-increment)
9. TPS65154 acknowledges
10. Steps (8) and (9) repeated until data for final RAM register has been sent
11. TPS65154 acknowledges
12. Bus master sends STOP condition
E8h
00h
DATA
DATA
RAM Register Address (n)
RAM Register Data (n)
RAM Register Data (n+1)
7-Bit Slave Address
S
0
A
A
A
A
DATA
RAM Register Data (Last)
P
A
Figure 5-14. Writing to Multiple RAM Registers
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5.5.2.3 Saving Contents of all RAM Registers to EEPROM
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65154 acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65154 acknowledges
6. Bus master sends data to be written to the Control Register (80h)
7. TPS65154 acknowledges
8. Bus master sends STOP condition
E8h
FFh
80h
Control Register Address
Control Register Data
7-Bit Slave Address
P
S
0
A
A
A
Figure 5-15. Saving Contents of all RAM Registers to EEPROM
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5.5.2.4 Reading from a Single RAM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65154 acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65154 acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS65154 acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65154 acknowledges
12. Bus master sends address of RAM register (00h)
13. TPS65154 acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65154 acknowledges
17. TPS65154 sends RAM register data
18. Bus master does not acknowledge
19. Bus master sends STOP condition
E8h
FFh
00h
Control Register Address
Control Register Data
S
7-Bit Slave Address
0
A
A
A
P
R/W
0
E8h
00h
E9h
DATA
RAM Register Address
RAM Register Data
7-Bit Slave Address
7-Bit Slave Address
S
A
A
Sr
1
A
A
P
Figure 5-16. Reading from a Single RAM Register
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5.5.2.5 Reading from a Single EEPROM Register
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65154 acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65154 acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS65154 acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65154 acknowledges
12. Bus master sends address of EEPROM register (00h)
13. TPS65154 acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65154 acknowledges
17. TPS65154 sends EEPROM register data
18. Bus master does not acknowledge
19. Bus master sends STOP condition
E8h
FFh
01h
S
7-Bit Slave Address
0
A
Control Register Address
A
Control Register Data
A
P
E8h
00h
E9h
DATA
S
7-Bit Slave Address
0
A
EEPROM Register Address
A
Sr
7-Bit Slave Address
1
A
EEPROM Register Data
P
A
Figure 5-17. Reading from a Single EEPROM Register
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5.5.2.6 Reading from Multiple RAM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65154 acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65154 acknowledges
6. Bus master sends data for Control Register (00h)
7. TPS65154 acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65154 acknowledges
12. Bus master sends address of first register to be read (00h)
13. TPS65154 acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65154 acknowledges
17. TPS65154 sends contents of first RAM register to be read
18. Bus master acknowledges
19. TPS65154 sends contents of second RAM register to be read
20. Bus master acknowledges
21. TPS65154 sends contents of third (last) RAM register to be read
22. Bus master does not acknowledge
23. Bus master sends STOP condition
E8h
FFh
00h
S
7-Bit Slave Address
0
A
Control Register Address
A
Control Register Data
A
P
R/W
0
E8h
00h
E9h
DATA
S
7-Bit Slave Address
A
RAM Register Address (n)
A
Sr
7-Bit Slave Address
1
A
RAM Register Data (n)
A
DATA
DATA
RAM Register Data (n+1)
A
RAM Register Data (Last)
P
A
Figure 5-18. Reading from Multiple RAM Registers
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5.5.2.7 Reading from Multiple EEPROM Registers
1. Bus master sends START condition
2. Bus master sends 7-bit slave address plus low R/W bit (E8h)
3. TPS65154 acknowledges
4. Bus master sends address of Control Register (FFh)
5. TPS65154 acknowledges
6. Bus master sends data for Control Register (01h)
7. TPS65154 acknowledges
8. Bus master sends STOP condition
9. Bus master sends START condition
10. Bus master sends 7-bit slave address plus low R/W bit (E8h)
11. TPS65154 acknowledges
12. Bus master sends address of first EEPROM register to be read (00h)
13. TPS65154 acknowledges
14. Bus master sends REPEATED START condition
15. Bus master sends 7-bit slave address plus high R/W bit (E9h)
16. TPS65154 acknowledges
17. TPS65154 sends contents of first EEPROM register to be read
18. Bus master acknowledges
19. TPS65154 sends contents of second EEPROM register to be read
20. Bus master acknowledges
21. TPS65154 sends contents of third (last) EEPROM register to be read
22. Bus master does not acknowledge
23. Bus master sends STOP condition
E8h
FFh
01h
S
7-Bit Slave Address
0
A
Control Register Address
A
Control Register Data
A
P
R/W
0
E8h
00h
E9h
DATA
S
7-Bit Slave Address
A
EEPROM Register Addr (n)
A
Sr
7-Bit Slave Address
1
A
EEPROM Register Data (n)
A
DATA
DATA
EEPROM Register Data (n+1)
A
EEPROM Register Data (Last)
P
A
Figure 5-19. Reading from Multiple EEPROM Registers
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5.5.3 Programming Examples - VCOM
5.5.3.1 Writing a VCOM Value of 77h to WR
1. The bus master sends a START condition.
2. The bus master sends 7-bit slave address plus low R/W bit.
3. TPS65154 slave acknowledges.
4. The bus master sends the CR address of 02h.
5. The TPS65154 acknowledges.
6. The bus master sends the CR contents of 80h.
7. The TPS65154 slave acknowledges.
8. The bus master sends a STOP condition.
9. The bus master sends a START condition.
10. The bus master sends 7-bit slave address plus low R/W bit.
11. TPS65154 slave acknowledges.
12. The bus master sends the WR address of 00h.
13. The TPS65154 acknowledges.
14. The bus master sends the WR contents of 77h (right-justified).
15. The TPS65154 slave acknowledges.
16. The bus master sends a STOP condition.
50h
02h
80h
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
1
0
A
1
0
0
0
0
0
0
0
A
P
0
Slave Address
CR Address
CR Data
R/W
50h
00h
77h
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
A
0
1
1
1
0
1
1
1
A
P
0
Slave Address
WR Address
WR Data
R/W
Figure 5-20. Writing a VCOM Value of 77h to WR
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5.5.3.2 Writing a VCOM Value of 77h to IVR and WR
1. The bus master sends a START condition.
2. The bus master sends 7-bit slave address plus low R/W bit.
3. TPS65154 slave acknowledges.
4. The bus master sends the CR address of 02h.
5. The TPS65154 acknowledges.
6. The bus master sends the CR contents of 00h.
7. The TPS65154 slave acknowledges.
8. The bus master sends a STOP condition.
9. The bus master sends a START condition.
10. The bus master sends 7-bit slave address plus low R/W bit.
11. TPS65154 slave acknowledges.
12. The bus master sends the WR address of 00h.
13. The TPS65154 acknowledges.
14. The bus master sends the WR contents of 77h (right-justified).
15. The TPS65154 slave acknowledges.
16. The bus master sends a STOP condition.
50h
02h
00h
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
1
0
A
0
0
0
0
0
0
0
0
A
P
Slave Address
CR Address
CR Data
R/W
50h
00h
77h
S
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
0
1
1
1
0
1
1
1
A
P
Slave Address
WR Address
WR Data
R/W
Figure 5-21. Writing a VCOM Value of 77h to IVR and WR
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5.5.3.3 Reading a VCOM Value of 77h from WR
1. The bus master sends a START condition.
2. The bus master sends 7-bit slave address plus low R/W bit.
3. TPS65154 slave acknowledges.
4. The bus master sends the CR address of 02h.
5. The TPS65154 acknowledges.
6. The bus master sends the CR contents of 80h.
7. The TPS65154 slave acknowledges.
8. The bus master sends a STOP condition.
9. The bus master sends a START condition.
10. The bus master sends 7-bit slave address plus low R/W bit.
11. TPS65154 slave acknowledges.
12. The bus master sends the WR address of 00h.
13. The TPS65154 acknowledges.
14. The bus master sends a REPEATED START condition.
15. The bus master sends 7-bit slave address plus high R/W bit.
16. The TPS65154 sends the WR contents of 77h (right-justified).
17. The bus master does not acknowledge.
18. The bus master sends a STOP condition.
50h
02h
80h
S
0
1
0
1
0
0
0
0
0
0
A
0
0
0
A
0
0
0
0
0
1
0
0
1
A
0
1
1
A
1
0
0
0
0
0
0
0
A
P
0
Slave Address
CR Address
CR Data
R/W
50h
00h
S
0
1
0
1
0
0
0
A
0
0
0
0
Slave Address
IVR Address
R/W
Repeated Start
00h
51h
S
0
1
0
1
0
0
1
1
1
1
A
P
0
Slave Address
WR Data
R/W
Figure 5-22. Reading 77h from WR
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5.5.3.4 Reading a VCOM Value of 77h from IVR
1. The bus master sends a START condition.
2. The bus master sends 7-bit slave address plus low R/W bit.
3. TPS65154 slave acknowledges.
4. The bus master sends the CR address of 02h.
5. The TPS65154 acknowledges.
6. The bus master sends the CR contents of 00h.
7. The TPS65154 slave acknowledges.
8. The bus master sends a STOP condition.
9. The bus master sends a START condition.
10. The bus master sends 7-bit slave address plus low R/W bit.
11. TPS65154 slave acknowledges.
12. The bus master sends the WR address of 00h.
13. The TPS65154 acknowledges.
14. The bus master sends a REPEATED START condition.
15. The bus master sends 7-bit slave address plus high R/W bit.
16. The TPS65154 sends the WR contents of 77h (right-justified).
17. The bus master does not acknowledge.
18. The bus master sends a STOP condition.
50h
02h
00h
S
0
1
0
1
0
0
0
0
0
0
A
0
0
0
A
0
0
0
0
0
1
0
0
1
A
0
1
0
A
1
0
0
0
0
0
0
0
A
P
0
Slave Address
CR Address
CR Data
R/W
50h
00h
S
0
1
0
1
0
0
0
A
0
0
0
0
Slave Address
IVR Address
R/W
Repeated Start
00h
51h
S
0
1
0
1
0
0
1
1
1
1
A
P
0
Slave Address
IVR Data
R/W
Figure 5-23. Reading 77h from IVR
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5.6 Register Map
5.6.1 Configuration Registers (Excluding VCOM)
Table 5-3 shows the memory map of the configuration parameters.
Table 5-3. Configuration Memory Map
REGISTER
ADDRESS
REGISTER
NAME
FACTORY DEFAULT
DESCRIPTION
Sets miscellaneous configuration bits
00h
CONFIG
02h
KMODE = 0
WPEN = 0
DMODE = 1
RMODE = 0
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
VCC
DLY1
AVDD
FSW1
SS2
03h
02h
0Fh
01h
04h
02h
09h
01h
01h
04h
01h
01h
02h
03h
2.5 V
10 ms
8.0 V
Sets the output voltage of the linear regulator (VCC
Sets the start-up delay of the linear regulator (VCC
Sets the output voltage of boost converter 1 (AVDD
Sets the switching frequency of boost converter 1 (AVDD
)
)
)
600 kHz
20 ms
10 ms
–6.8 V
5 ms
)
Sets the soft-start time of boost converter 1 (AVDD
)
)
DLY2
VGL
Sets the start-up delay of boost converter 1 (AVDD
Sets the output voltage of the negative charge pump (VGL
)
SS3
Sets the soft-start time of the negative charge pump (VGL
)
DLY3
VGH
SS4
5 ms
Sets the start-up delay of the negative charge pump (VGL)
20.0 V
5 ms
Sets the output voltage of boost converter 2 (VGH
Sets the soft-start time of boost converter 2 (VGH
Sets the switching frequency of boost converter 3 (WLED)
)
)
FSW3
DLY4
OVP
600 kHz
10 ms
39 V
Sets the start-up delay of the gate voltage shaping function (VGHM
)
Sets the over-voltage protection threshold of boost converter 3
(WLED)
0Fh
FDIM
07h
22 kHz
Sets the output dimming frequency of the WLED driver in phase-shift
dimming mode
10h
11h
12h
13h
14h
15h
FFh
RESET
VDET
05h
00h
02h
07h
07h
00h
00h
5 ms
VDET = VUVLO
30 ms
Sets the reset pulse duration
Sets the threshold of the RST and XAO signals
Sets the start-up delay of the XAO signal
Sets the maximum VCOM voltage
Sets the minimum VCOM voltage
For customer use
DLY6
VMAX
3.2 V
VMIN
2.7 V
USER1
CONTROL
00h
Controls whether read and write operations access RAM or EEPROM
registers
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5.6.1.1 CONFIG (00h)
The CONFIG register can be written to and read from.
Figure 5-24. CONFIG Register Bit Allocation
7
6
5
4
3
2
1
0
ADIS
R/W-0
Reserved
R/W-0
KMODE
R/W-0
WPEN
R/W-0
DMODE
R/W-1
RMODE
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-4. CONFIG Register Field Descriptions
Bit
Field
Value
Description
7
ADIS
This bit can be used to disable boost converter 1 (AVDD), boost converter 2 (VGH) and the negative
charge pump (VGL) during device programming. This bit is volatile and is never stored in EEPROM.
It is always reset (that is, ADIS = 0) following power-up, that is, the affected converters are always
enabled following power-up.
0
1
Boost converter 1 (AVDD), boost converter 2 (VGH), and negative charge pump (VGL) enabled.
Boost converter 1 (AVDD), boost converter 2 (VGH), and negative charge pump (VGL) disabled.
These bits are reserved for future use and should be programmed to 0 to ensure proper operation.
This bit can be used to enable and disable boost converter 1's active discharge function.
Boost converter 1 (AVDD) active discharge enabled.
6-4
3
Reserved
KMODE
N/A
0
1
Boost converter 1 (AVDD) active discharge disabled.
2
1
0
WPEN
DMODE
RMODE
This bit can be used to enable and disable the write protect function.
Disabled. WP not used and I2C interface always active.
Enabled. I2C interface only active when WP pulled low.
This bit determines which dimming mode is used by the WLED driver.
Direct dimming.
0
1
0
1
Phase-shift dimming.
This bit determines which threshold is used to assert RST during power-down.
VUVLO threshold used.
0
1
VDET threshold used.
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5.6.1.2 VCC (01h)
The VCC register can be written to and read from.
Figure 5-25. VCC Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VCC
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-5. VCC Register Field Descriptions
Bit
Field
Value
Description
7-2
Not implemented
N/A
These bits are not implemented. During write operations, data for these bits is ignored, and during
read operations 0 is returned.
1-0
VCC
These bits determine the output voltage of the linear regulator (VCC).
0h
1h
2h
3h
1.0 V
1.2 V
1.89 V
2.5 V
40
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5.6.1.3 DLY1 (02h)
The DLY1 register can be written to and read from.
Figure 5-26. DLY1 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
DLY1
R/W-0
R/W-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-6. DLY1 Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
write operations 0 is returned.
3-0
DLY1
These bits determine how soon after VIN>VUVLO the linear regulator (VCC) starts.
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
0 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
40 ms
45 ms
50 ms
55 ms
60 ms
65 ms
70 ms
75 ms
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5.6.1.4 AVDD (03h)
The AVDD register can be written to and read from.
Figure 5-27. AVDD Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
AVDD
R/W-1
R/W-0
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-7. AVDD Register Field Descriptions
Bit
Field
Value
Description
1
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
0
AVDD
These bits determine the output voltage of boost converter 1 (AVDD).
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
6.5 V
6.6 V
6.7 V
6.8 V
6.9 V
7.0 V
7.1 V
7.2 V
7.3 V
7.4 V
7.5 V
7.6 V
7.7 V
7.8 V
7.9 V
8.0 V
8.1 V
8.2 V
8.3 V
8.4 V
8.5 V
8.6 V
8.7 V
8.8 V
8.9 V
9.0 V
9.1 V
9.2 V
9.3 V
9.4 V
9.5 V
9.6 V
42
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5.6.1.5 FSW1 (04h)
The FSW1 register can be written to and read from.
Figure 5-28. FSW1 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
FSW1
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-8. FSW1 Register Field Descriptions
Bit
Field
Value
Description
7-2
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
1-0
FSW1
These bits determine the switching frequency of boost converter 1 (AVDD).
0h
1h
2h
3h
400 kHz
600 kHz
800 kHz
1 MHz
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5.6.1.6 SS2 (05h)
The SS2 register can be written to and read from.
Figure 5-29. SS2 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
SS2
R/W-0
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-9. SS2 Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
SS2
These bits determine the soft-start time of boost converter 1 (AVDD).
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
0.5 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
40 ms
45 ms
50 ms
55 ms
60 ms
65 ms
70 ms
75 ms
44
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5.6.1.7 DLY2 (06h)
The DLY2 register can be written to and read from.
Figure 5-30. DLY2 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
DLY2
R/W-0
R/W-0
R/W-1
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-10. DLY2 Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
DLY2
These bits determine how soon after RST goes high boost converter 1 (AVDD) starts.
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
0 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
40 ms
45 ms
50 ms
55 ms
60 ms
65 ms
70 ms
75 ms
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5.6.1.8 VGL (07h)
The VGL register can be written to and read from.
Figure 5-31. VGL Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VGL
R/W-1
R/W-0
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-11. VGL Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
VGL
These bits determine the output voltage of the negative charge pump (VGL).
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
–5.0 V
–5.2 V
–5.4 V
–5.6 V
–5.8 V
–6.0 V
–6.2 V
–6.4 V
–6.6 V
–6.8 V
–7.0 V
–7.2 V
–7.4 V
–7.6 V
–7.8 V
–8.0 V
46
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5.6.1.9 SS3 (08h)
The SS3 register can be written to and read from.
Figure 5-32. SS3 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
SS3
R/W-0
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-12. SS3 Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
SS3
These bits determine the soft-start time of the negative charge pump (VGL).
0h
1h
2h
3h
4h
5h
6h
7h
0.256 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
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5.6.1.10 DLY3 (09h)
The DLY3 register can be written to and read from.
Figure 5-33. DLY3 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
DLY3
R/W-0
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-13. DLY3 Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
DLY3
These bits determine how soon after boost converter 1 (AVDD) starts the negative charge pump
(VGL) starts.
0h
1h
2h
3h
4h
5h
6h
7h
0 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
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5.6.1.11 VGH (0Ah)
The VGH register can be written to and read from.
Figure 5-34. VGH Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VGH
R/W-0
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-14. VGH Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
VGH
These bits determine the output voltage of boost converter 2 (VGH).
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
18.0 V
18.5 V
19.0 V
19.5 V
20.0 V
20.5 V
21.0 V
21.5 V
22 0 V
22.5 V
23.0 V
23.5 V
24.0 V
24.5 V
25.0 V
25.5 V
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5.6.1.12 SS4 (0Bh)
The SS4 register can be written to and read from.
Figure 5-35. SS4 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
SS4
R/W-0
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-15. SS4 Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
SS4
These bits determine the soft-start time of boost converter 2 (VGH).
0h
1h
2h
3h
4h
5h
6h
7h
0.256 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
50
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5.6.1.13 FSW3 (0Ch)
The FSW3 register can be written to and read from.
Figure 5-36. FSW3 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
FSW3
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-16. FSW3 Register Field Descriptions
Bit
Field
Value
Description
7-2
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
1-0
FSW3
These bits determine the switching frequency of boost converter 3 (WLED).
0h
1h
2h
3h
400 kHz
600 kHz
800 kHz
1 MHz
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5.6.1.14 DLY4 (0Dh)
The DLY4 register can be written to and read from.
Figure 5-37. DLY4 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
DLY4
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-17. DLY4 Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
DLY4
These bits determine the start-up delay of the gate voltage shaping function.
0h
1h
2h
3h
4h
5h
6h
7h
0 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
52
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5.6.1.15 OVP (0Eh)
The OVP register can be written to and read from.
Figure 5-38. OVP Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
OVP
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-18. OVP Register Field Descriptions
Bit
Field
Value
Description
7-2
Not implemented
N/A
These bits are not implemented. During write operations, data for these bits is ignored, and during
read operations 0 is returned.
1-0
OVP
These bits determine the overvoltage threshold of boost converter 3 (WLED).
0h
1h
2h
3h
30 V
33 V
36 V
39 V
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5.6.1.16 FDIM (OFh)
The FDIM register can be written to and read from.
Figure 5-39. FDIM Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
FDIM
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-19. FDIM Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
FDIM
These bits determine the WLED driver's output dimming frequency in phase-shift dimming mode.
0h
1h
2h
3h
4h
5h
6h
7h
15 kHz
16 kHz
17 kHz
18 kHz
19 kHz
20 kHz
21 kHz
22 kHz
54
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5.6.1.17 RESET (10h)
The RESET register can be written to and read from.
Figure 5-40. RESET Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
RESET
R/W-0
R/W-1
R/W-0
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-20. RESET Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
RESET
These bits determine the duration of the reset pulse (RST).
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
0 ms
1 ms
2 ms
3 ms
4 ms
5 ms
6 ms
7 ms
8 ms
9 ms
10 ms
11 ms
12 ms
13 ms
14 ms
15 ms
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5.6.1.18 VDET (11h)
The VDET register can be written to and read from.
Figure 5-41. VDET Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VDET
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-21. VDET Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
VDET
These bits determine the threshold voltage of the XAO signal.
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
VUVLO
2.0 V
2.1 V
2.2 V
2.3 V
2.4 V
2.5 V
2.6 V
2.7 V
2.8 V
2.9 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
56
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5.6.1.19 DLY6 (12h)
The DLY6 register can be written to and read from.
Figure 5-42. DLY6 Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
DLY6
R/W-1
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-22. DLY6 Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
DLY6
These bits determine the start-up delay time of the XAO signal.
0h
1h
2h
3h
4h
5h
6h
7h
0 ms
5 ms
10 ms
15 ms
20 ms
25 ms
30 ms
35 ms
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5.6.1.20 VMAX (13h)
The VMAX register can be written to and read from.
Figure 5-43. VMAX Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VMAX
R/W-0
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-23. VMAX Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
VMAX
These bits determine the maximum VCOM voltage.
2.5/8 × AVDD
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
2.6/8 × AVDD
2.7/8 × AVDD
2.8/8 × AVDD
2.9/8 × AVDD
3.0/8 × AVDD
3.1/8 × AVDD
3.2/8 × AVDD
3.3/8 × AVDD
3.4/8 × AVDD
3.5/8 × AVDD
3.6/8 × AVDD
3.7/8 × AVDD
3.8/8 × AVDD
3.9/8 × AVDD
4.0/8 × AVDD
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5.6.1.21 VMIN (14h)
The VMIN register can be written to and read from.
Figure 5-44. VMIN Register Bit Allocation
7
6
5
4
3
2
1
0
Not Implemented
VMIN
R/W-0
R/W-1
R/W-1
R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-24. VMIN Register Field Descriptions
Bit
Field
Value
Description
7-4
Not Implemented
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
3-0
VMIN
These bits determine the minimum VCOM voltage.
2.0/8 × AVDD
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
2.1/8 × AVDD
2.2/8 × AVDD
2.3/8 × AVDD
2.4/8 × AVDD
2.5/8 × AVDD
2.6/8 × AVDD
2.7/8 × AVDD
2.8/8 × AVDD
2.9/8 × AVDD
3.0/8 × AVDD
3.1/8 × AVDD
3.2/8 × AVDD
3.3/8 × AVDD
3.4/8 × AVDD
3.5/8 × AVDD
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5.6.1.22 USER (15h)
The USER register can be written to and read from.
Figure 5-45. USER Register Bit Allocation
7
6
5
4
3
2
1
0
USER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-25. USER Register Field Descriptions
Bit
Field
Value
Description
7-0
USER
N/A
These bits are free for customer use. Their contents have no effect on device operation.
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5.6.1.23 CONTROL (FFh)
Figure 5-46. CONTROL Register Bit Allocation
7
6
5
4
3
2
1
0
WED
R/W-0
Not Implemented
RED
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-26. CONTROL Register Field Descriptions
Bit
Field
Value
Description
7
WED
This bit determines whether write operations affect the contents of the volatile or non-volatile
registers.
0h
1h
Not applicable (see below).
Data is copied from the RAM registers to the EEPROM registers. This bit is automatically reset
upon completion of this task.
6-1
0
Not Implemented
RED
N/A
These bits are not implemented. During write operations data for these bits is ignored, and during
read operations 0 is returned.
This bit determines whether read operations return the contents of the volatile or non-volatile
registers.
0h
1h
Volatile register data is returned.
Non-volatile register data is returned.
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5.6.2 VCOM Registers
5.6.2.1 VCOM DATA (Slave Address 28h, Register Address 00h)
The VCOM DATA register can be written to and read from.
Figure 5-47. VCOM DATA Register Bit Allocation
7
6
5
4
3
2
1
0
NI
VCOM
R/W-0
R-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-27. VCOM DATA Register Bit Description
Bit
7
Field
Not implemented
VCOM
Value
Description
N/A
This bit is reserved for future use and should be programmed to 0 for proper operation.
Bits 6 through 0 set the value of the VCOM voltage.
6-0
N/A
VCOM=(VCOM/127) × (VMAX–VMIN) + VMIN
5.6.2.2 VCOM CONTROL (Slave Address 28h, Register Address 02h)
The VCOM CONTROL register is write-only.
Figure 5-48. VCOM CONTROL Register Bit Allocation
7
6
5
4
3
2
1
0
SEL
Not Implemented
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = factory default
Table 5-28. VCOM CONTROL Register Bit Description
Bit
Field
Value
Description
7
SEL
The SEL bit determines whether read/write operations to the VCOM DATA register access the IVR,
the WR, or both.
0
1
Write operations store data in the IVR and WR.
Read operations return the contents of the IVR.
Write operations store data in the WR only.
Read operations return the contents of the WR.
6-0
Not implemented
N/A
Bits 6 through 0 are reserved for future use. They should be programmed to 0 for proper operation.
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6 Application and Implementation
NOTE
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
6.1 Application Information
The TPS65154 devices is intended primarily for use in notebook PC and tablet applications. It needs
these two supply voltages
•
•
A regulated 3.3-V or 5-V supply for the LCD bias functions
A direct connection to the battery for the WLED driver functions
The device configuration parameters are set by I2C interface and stored in the on-chip nonvolatile
memory.
6.2 Typical Application
Figure 6-1 shows the recommended application circuit for typical applications. The I2C interface is used to
optimize the circuit's operating parameters for a specific application. If different component values are
used, make sure that the values are within the recommended operating conditions (see Recommended
Operating Conditions). If different component values are used, the compensation components may also
need to be optimized for stability and best performance.
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10μH
SW1
AVDD
AVDD
AVDD
VIN
VIN
20μF
20μF
BOOST
CONVERTER 1
PGND
PGND
3.9nF 24.9k
COMP1
VCC
AVDD
LINEAR
REGULATOR
VCC
10μF
10μH
VGH
SW2
1k
BAS70W
AVDD
10k
RE
4.7μF
BOOST
CONVERTER 2
VCC
VGH
FLK
VGHM
10k
VGHM
RST
XAO
MISCELLANEOUS
C1A
NEGATIVE
CHARGE PUMP
VGL
1μF
1μF
VGL
4.7μF
C1B
VCOM
AVDD
VCOM
NEG
BSUP
1k
VCOM
BUFFER
100nF
1k
VCOM-FB
BGND
SCL
SDA
WP
I2C INTERFACE
VBAT
EN
10μH
VLED
RB160M
PWM
SW3
OVP
10μF
24.9k
PGND
WLED
DRIVER
ISET
10μF
470nF
IFB1
IFB2
IFB3
IFB4
IFB5
IFB6
COMP2
COMP3
AGND
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Figure 6-1. Typical Application Circuit
6.2.1 Design Requirements
This design example uses the parameters listed in Table 6-1 as the input parameters.
Table 6-1. Input Parameters
PARAMETER
SYMBOL
VIN
VALUE
3.3 V
Input supply voltage – LCD bias functions
Input supply voltage – WLED driver
VBAT
9 V to 21 V
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Table 6-1. Input Parameters (continued)
PARAMETER
SYMBOL
AVDD
VGL
VALUE
8 V
Boost converter 1 output voltage
Inverting charge pump output voltage
Boost converter 2 output voltage
Linear regulator output voltage
–6.8 V
20 V
VGH
VCC
2.5 V
50 mA
WLED driver output current (per string)
ISET
6.2.2 Detailed Design Procedure
6.2.2.1 External Component Selection
Care should be applied to the choice of external components since they greatly affect overall
performance. The TPS65154 was developed with the twin goals of high performance and small/low-profile
solution size. Since these two goals are often in direct opposition to one another (for example, larger
inductors tend to achieve higher efficiencies), some trade-off is always necessary.
Inductors must have adequate current capability so that they do not saturate under worst-case conditions.
For high efficiency, they should also have low dc resistance (DCR).
Capacitors must have adequate effective capacitance under the applicable dc bias conditions they
experience in the application. MLCC capacitors typically exhibit only a fraction of their nominal
capacitance under real-world conditions and this must be taken into consideration when selecting them.
This problem is especially acute in low profile capacitors, in which the dielectric field strength is higher
than in taller components. In general, the capacitance values shown in circuit diagrams in this data sheet
refer to the effective capacitance after dc bias effects have been taken into consideration. Reputable
capacitor manufacturers provide capacitance versus dc bias curves that greatly simplify component
selection.
The following tables list some components suitable for use with the TPS65154. The list is not exhaustive –
other components may exist that are equally suitable (or better), however, these components have been
proven to work well and were used extensively during the development of the TPS65154.
Table 6-2. Linear Regulator External Component Recommendations
REF.
DESCRIPTION
PART NUMBER
MANUFACTURER
MAX. THICKNESS
COUT
10 µF, 6.3 V, ±20%, X5R, 0603
GRM188R60J106ME84
Murata
0.95 mm
Table 6-3. Boost Converter 1 External Components
REF.
L
DESCRIPTION
PART NUMBER
NRS6012T100MMGG
GRM319R61C106KE15D
MANUFACTURER
MAX. THICKNESS
1.2 mm
10 µH, 1.5 A, 0.205 Ω
Taiyo Yuden
Murata
COUT
10 µF, 16 V, ±10%, X5R, 1206
0.85 ±0.1 mm
Table 6-4. Boost Converter 2 External Components
REF.
L
DESCRIPTION
PART NUMBER
NRH3010T100MN
MANUFACTURER
MAX. THICKNESS
1 mm
10 µH, 0.6 A
Taiyo Yuden
Murata
COUT
4.7 µF, 50 V, ±10%, X5R, 1206
GRM319R61H475KA12
0.95 mm
Table 6-5. Boost Converter 3 External Components
REF.
L
DESCRIPTION
PART NUMBER
MANUFACTURER
MAX. THICKNESS
1.2 mm
10 µH, 1.5 A, 0.205 Ω
NRS6012T100MMGGJ
GRM319R61H475KA12
Taiyo Yuden
Murata
COUT
4.7 µF, 50 V, ±10%, X5R, 1206
0.95 mm
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6.2.3 Application Curves
100
90
80
70
60
50
40
30
20
8.10
8.08
8.06
8.04
8.02
8.00
7.98
7.96
7.94
7.92
7.90
AVDD=7.0 V
AVDD=8.0 V
AVDD=9.0 V
10
VIN=3.3 V
IOUT=100 mA
2.5 3.0
AVDD=8.0 V
5.0 5.5 6.0
0
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
2.0
3.5
4.0
4.5
Output Current (A)
Input Voltage (V)
G001
G002
Figure 6-2. Boost Converter 1 (AVDD) Efficiency
Figure 6-3. Boost Converter 1 (AVDD) Line Regulation
8.10
8.08
8.06
8.04
8.02
8.00
7.98
7.96
7.94
7.92
7.90
VIN=3.3 V
AVDD=8.0 V
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40
Output Current (A)
G003
Figure 6-4. Boost Converter 1 (AVDD) Load Regulation
Figure 6-5. Boost Converter 1 (AVDD) Line Transient Response
Figure 6-7. Boost Converter 1 (AVDD) Output Voltage Ripple
Figure 6-6. Boost Converter 1 (AVDD) Load Transient Response
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100
90
80
70
60
50
40
30
20
10
0
VGH=19 V
VGH=20 V
VGH=21.5 V
AVDD=8.0 V
10 20
0
30
40
50
60
70
80 90 100
Output Current (mA)
G008
Figure 6-9. Boost Converter 2 (VGH) Efficiency
Figure 6-8. Boost Converter 1 (AVDD) Switching Waveforms
20.2
20.1
20.0
20.2
20.1
20.0
IOUT=10 mA
7.0
VGH=20 V
9.5 10.0
AVDD=8 V
10
VGH=20 V
40 45 50
6.5
7.5
8.0
8.5
9.0
0
5
15
20
25
30
35
Input Voltage (V)
Output Current (mA)
G009
G010
Figure 6-10. Boost Converter 2 (VGH) Line Regulation
Figure 6-11. Boost Converter 2 (VGH) Load Regulation
Figure 6-12. Boost Converter 2 (VGH) Load Transient Response
Figure 6-13. Boost Converter 2 (VGH) Output Voltage Ripple
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500
450
400
350
300
250
200
150
100
50
VGH=18.0 V
VGH=21.0 V
VGH=25.5 V
IGH=10 mA
7.0
0
6.5
7.5
8.0
8.5
9.0
9.5
10.0
Input Voltage − AVDD (V)
G014
Figure 6-15. Boost Converter 2 (VGH) Switching Frequency
Figure 6-14. Boost Converter 2 (VGH) Switching Waveforms
1.90
1.90
1.89
1.88
1.87
1.86
1.89
IOUT=100 mA
3.0
VCC=1.89 V
5.5 6.0
VIN=3.3 V
50
VCC=1.89 V
300 350 400
1.88
2.5
1.85
3.5
4.0
4.5
5.0
0
100
150
200
250
Input Voltage (V)
Output Current (mA)
G015
G016
Figure 6-16. Linear Regulator (VCC) Line Regulation
Figure 6-17. Linear Regulator (VCC) Load Regulation
Figure 6-18. Linear Regulator (VCC) Line Transient Response
Figure 6-19. Linear Regulator (VCC) Load Transient Response
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−6.5
−6.6
−6.7
−6.8
−6.9
−7.0
−7.1
−7.2
−7.3
−7.4
−7.5
VIN=3.3 V
10
AVDD=8.0 V
40 45 50
0
5
15
20
25
30
35
Output Current (mA)
G019
Figure 6-20. Negative Charge Pump (VGL) Load Regulation
Figure 6-21. Negative Charge Pump (VGL) Load Transient
Response
Figure 6-22. Negative Charge Pump (VGL) Output Voltage Ripple Figure 6-23. Gate Voltage Shaping (VGHM) Switching Waveforms
Figure 6-24. VCOM Buffer Large-Signal Response
Figure 6-25. VCOM Buffer Small-Signal Bandwidth
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Figure 6-26. VCOM Buffer Peak Output Current
Figure 6-28. LCD Bias Power-Up Sequencing
Figure 6-30. LCD Bias Power-Up Sequencing
Figure 6-27. LCD Bias Power-Up Sequencing
Figure 6-29. LCD Bias Power-Up Sequencing
Figure 6-31. LCD Bias Power-Down Sequencing
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Figure 6-32. LCD Bias Power-Down Sequencing
Figure 6-33. LCD Bias Power-Down Sequencing
Figure 6-34. LCD Bias Power-Down Sequencing
Figure 6-35. Boost Converter 3 (VLED) Efficiency
100
90
80
70
60
50
40
30
100
90
80
70
60
50
40
30
VBAT=6 V
VBAT=6 V
VBAT=12 V
VBAT=18 V
VBAT=24 V
VBAT=12 V
VBAT=18 V
VBAT=24 V
20
10
0
20
10
0
VLED=32 V
fSW=600 kHz
VLED=36 V
fSW=600 kHz
0
50
100
150
200
250
300
0
50
100
150
200
250
300
Output Current (mA)
Output Current (mA)
G035
G036
Figure 6-36. Boost Converter 3 (VLED) Efficiency
Figure 6-37. Boost Converter 3 (VLED) Efficiency
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32.8
32.7
32.6
32.5
32.4
32.3
32.2
32.1
32.0
32.8
32.7
32.6
32.5
32.4
32.3
32.2
32.1
32.0
31.9
31.8
31.9
IOUT=120 mA
VLED=32 V
20 24
VBAT=12 V
50
VLED=32 V
250 300
31.8
4
8
12
16
0
100
150
200
Input Voltage (V)
Output Current (mA)
G037
G038
Figure 6-38. Boost Converter 3 (VLED) Line Regulation
Figure 6-39. Boost Converter 3 (VLED) Load Regulation
Figure 6-40. Boost Converter 3 (VLED) Line Transient Response Figure 6-41. Boost Converter 3 (VLED) Load Transient Response
Figure 6-42. Boost Converter 3 (VLED) Output Voltage Ripple
Figure 6-43. Boost Converter 3 (VLED) Switching Waveforms
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Figure 6-44. PWM Direct Dimming Waveforms
Figure 6-45. PWM Phase-Shifted Dimming
Figure 6-47. WLED Driver Power-Up Sequence
Figure 6-49. WLED Driver Power-Up Sequence
Figure 6-46. WLED Driver Power-Up Sequence
Figure 6-48. WLED Driver Power-Up Sequence
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Figure 6-50. WLED Driver Power-Up Sequence
Figure 6-51. WLED Driver Power-Up Sequence
3.0
2.5
2.0
1.5
1.0
0.5
TJ rising
TJ falling
0.0
VIN=3.3 V
−0.5
110
120
130
140
150
160
Temperature (°C)
G051
Figure 6-52. Thermal Shutdown
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7 Power Supply Recommendations
The TPS65154 device is designed to operate with two input supplies:
•
One supply in the range 2 V to 5.5 V powers the LCD bias functions. Typically, this is a regulated 3.3-
V or 5-V supply generated by a dc-dc converter somewhere else in the system. Note that this supply
must be higher than 2.5 V if the user wants to program the EEPROM.
•
One supply in the range 4.5 V to 24 V powers the WLED driver boost converter. Typically, this is an
unregulated supply taken from the battery system in a notebook PC or tablet.
The input supplies must be stable and free of noise to achieve the full performance of the device. If the
input supplies are located more than a few centimeters away from the TPS65154 device, additional bulk
capacitance may be required. The input capacitance shown in Figure 6-1 is sufficient for typical
applications.
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8 Layout
8.1 Layout Guidelines
The PCB layout is an important step in a power supply design. An incorrect layout can cause converter
instability, load regulation problems, noise, and EMI issues. The list of recommendations below highlights
the most important points to consider when doing the layout for the TPS65154 device. However, all PCB
layout is a trade-off between theory and practice, and some compromise is always necessary.
•
If possible, use a 4-layer PCB. Route high di/dt signals on layer 1 and use the second layer to form a
solid ground plane. If a 2-layer PCB is used, route high di/dt signals on layer 1 and add a copper pour
connected to ground on the bottom layer.
•
•
Place a decoupling capacitor close to the VIN pin. Use short, wide traces on layer 1 to connect to it.
Place at least one of the boost converter 1 output capacitors close to the device. Use short, wide
traces on layer 1 to connect it between pins 3 and 4, and pin 6.
•
•
•
•
•
•
Place the boost converter 3 rectifier diode and output capacitor close to the device. Use short, wide
traces on layer 1 to connect them to pins 9 and 10.
Place the boost converter 2 rectifier diode and output capacitor close to the device. Use short, wide
traces on layer 1 to connect them to pins 33 and 34.
Place the flying capacitor connected to pins 19 and 20 and the output capacitor connected to pin 18
close to the device. Use short, wide traces on layer 1 to connect to them.
Place the VCOM buffer decoupling capacitor connected between pin 2 and pin 47 close to the device.
Use short, wide traces on layer 1 to connect to it.
Route the signals to the compensation components connected to pin 7, pin 40 and pin 46 away from
noisy signals.
Use thermal vias to connect the thermal pad to a large, unbroken copper ground plane (typically, on
layer 2).
8.2 Layout Example
Figure 8-1 shows the main features of the TPS65154 Evaluation Module PCB layout.
76
Layout
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VCOM_FB
AVDD
VCOM
GND
AVDD
VLED
VIN
GND
VBAT
GND
VCC
GND
VLED
GND
ISET
XAO
RST
GND
VGL
VGH
Figure 8-1. Example PCB Layout
版权 © 2013–2016, Texas Instruments Incorporated
Layout
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产品主页链接: TPS65154
TPS65154
ZHCSF63A –SEPTEMBER 2013–REVISED JUNE 2016
www.ti.com.cn
9 器件和文档支持
9.1 器件支持
9.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES
NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR
SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR
SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
9.2 接收文档更新通知
如需接收文档更新通知，请访问 ti.com 上的器件产品文件夹。点击右上角的提醒我 (Alert me) 注册后，即可
每周定期收到已更改的产品信息。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。
9.3 社区资源
下列链接提供到 TI 社区资源的连接。 链接的内容由各个分销商“按照原样”提供。 这些内容并不构成 TI 技术
规范和标准且不一定反映 TI 的观点；请见 TI 的使用条款。
TI E2E™ 在线社区 TI 工程师对工程师 (E2E) 社区。 此社区的创建目的是为了促进工程师之间协作。 在
e2e.ti.com 中，您可以咨询问题、共享知识、探索思路，在同领域工程师的帮助下解决问题。
德州仪器 (TI) 嵌入式处理器维基网站 德州仪器 (TI) 嵌入式处理器维基网站。 此网站的建立是为了帮助开发
人员从德州仪器 (TI) 的嵌入式处理器入门并且也为了促进与这些器件相关的硬件和软件的总体
知识的创新和增长。
9.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
9.5 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
78
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ZHCSF63A –SEPTEMBER 2013–REVISED JUNE 2016
10 机械、封装和可订购信息
10.1 封装信息
以下页中包括机械、封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知
且不对本文档进行修订的情况下发生改变。要获得这份数据表的浏览器版本，请查阅左侧的导航栏。
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机械、封装和可订购信息
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65154RSLR
ACTIVE
VQFN
RSL
48
2500 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
TPS
65154
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65154RSLR
VQFN
RSL
48
2500
330.0
16.4
6.3
6.3
1.1
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RSL 48
SPQ
Length (mm) Width (mm) Height (mm)
552.0 367.0 38.0
TPS65154RSLR
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2022
TUBE
*All dimensions are nominal
Device
Package Name Package Type
RSL VQFN
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TPS65154RSLR
48
2500
381.5
7.92
2286
0
Pack Materials-Page 3
PACKAGE OUTLINE
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
4.4
13
24
44X 0.4
12
23
SYMM
49
4.5
4.3
4.4
1
36
0.25
0.15
48X
PIN 1 IDENTIFICATION
(OPTIONAL)
37
48
0.1
C A B
C
SYMM
0.5
0.3
0.05
48X
4219205/A 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
(
4.4)
SYMM
48
37
48X (0.6)
48X (0.2)
1
36
44X (0.4)
SYMM
(5.8)
10X (1.12)
49
6X (0.83)
(R0.05) TYP
12
25
13
6X (0.83)
24
(Ø0.2) VIA
10X (1.12)
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.05 MAX
0.05 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219205/A 02/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
SYMM
48
37
48X (0.6)
48X (0.2)
1
49
36
44X (0.4)
16X
(
0.92)
SYMM
8X (0.56)
(5.8)
8X (1.12)
(R0.05) TYP
12
25
13
8X (1.12)
24
METAL TYP
8X (0.56)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED COVERAGE BY AREA
SCALE: 12X
4219205/A 02/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
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