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TPS652170

ZHCSJX9 –JUNE 2019

适用于电池驱动型系统的 TPS652170 可编程 PMIC

1 特性

2 应用

1

•

充电器和电源路径

•

Sitara™AM335x 处理器电源

便携式导航系统

–

电源路径上具有 2A 输出电流

线性充电器；700mA 最大充电电流

可耐受 20V USB 和交流输入

热调节，安全计时器

平板电脑计算

5V 工业设备

3 说明

温度检测输入

TPS652170 是一款单芯片电源管理 IC (PMIC)，专门

设计用于为便携式和 5V 线路供电型应用中的 AM335x

ARM^®Cortex^®-A8 处理器供电。该 PMIC 器件包含一

个线性电池充电器（支持单节锂离子电池和锂聚合物电

池）、双输入电源路径、三个降压转化器、四个低压降

(LDO) 稳压器以及一个高效升压转换器，可为两个分

别由多达 10 个 LED 组成的灯串供电。此系统可由

USB 端口、5V 交流适配器或锂离子电池的任意组合供

电。此器件的额定运行温度范围为 -40°C 至 +105°C，

非常适合工业应用。三个高效 2.25MHz 降压转换器可

为系统提供内核电压、存储器和 I/O 电压。

•

降压转换器（DCDC1、DCDC2、DCDC3）

–

三个具有集成开关 FET 的降压转换器

2.25MHz 固定频率运行

轻负载电流状态下进入节能模式

PWM 模式下输出电压精度为 ±2%

100% 占空比，可实现最低压降

每个转换器的静态电流典型值为 15µA

禁用时支持无源对地放电

•

LDO 稳压器（LDO1、LDO2）

–

两个可调 LDO

LDO2 可配置为跟踪 DCDC3

15µA 静态电流（典型值）

TPS652170 器件采用具有 0.4mm 间距的 48 引脚无引

线封装 (6mm × 6mm VQFN)。

•

负载开关（LDO3、LDO4）

两个可配置为 LDO 的独立负载开关

WLED 驱动器

器件信息⁽¹⁾

–

器件型号

TPS652170

封装

VQFN (48)

封装尺寸（标称值）

6.00mm × 6.00mm

–

内部生成的 PWM 可支持调光控制

38V 开路 LED 保护

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

支持两个 LED 灯串（每串多达 10 个 LED，每

个 LED 的电流为 25mA）

简化应用示意图

–

内部低侧灌电流

TPS65217C,

TPS65217D

PMIC

Sitara AM335xZCZ

Processor

DDR3 or DDR3L

Memory

AC adapter

DC 5-V out

VDDQ/2

V_AC

V_SYS

•

保护

VTT, VREFCA

VDD, VDDQ

AC

SYS

V_USB

–

欠压锁定和电池故障比较器

USB

1.5 V or

1.35 V

USB direct

connection

常开按钮监视器

1.2 A

VDDS_DDR

DCDC1

DCDC2

DCDC3

BAT

BAT_SENSE

1.1 V

硬件复位引脚

受密码保护的 I²C 寄存器

VDD_MPU

GND

VDD_CORE

接口

1.8 V

3.3 V

1.8 V

PB_IN

100 mA

400 mA

LDO1

LDO2

VDDS, VDDS_RTC

–

I²C 接口（地址 0x24）

受密码保护的 I²C 寄存器

VDDA_ADC, VDDS_OSC,

VDDS_PLL, VDDS_SRAM,

VDDSHVx(1.8),

LS1/LDO3

VDDA1P8V_USB0

3.3 V

400 mA

VDDSHVx(3.3),

LS2/LDO4

VDDA3P3V_USB0

I2C0_SCL

I2C0_SDA

SCL

SDA

PMIC_PWR_EN

EXT_WAKEUP

PWR_EN

nWAKEUP

1

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SLVSF11

TPS652170

ZHCSJX9 –JUNE 2019

www.ti.com.cn

7.5 Programming........................................................... 39

7.6 Register Maps......................................................... 42

Application and Implementation ........................ 71

8.1 Application Information............................................ 71

8.2 Typical Application .................................................. 72

Power Supply Recommendations...................... 79

1

2

3

4

5

6

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 6

6.5 Electrical Characteristics........................................... 6

6.6 I²C Timing Requirements........................................ 13

6.7 Typical Characteristics............................................ 14

Detailed Description ............................................ 15

7.1 Overview ................................................................. 15

7.2 Functional Block Diagram ....................................... 16

7.3 Feature Description................................................. 17

7.4 Device Functional Modes........................................ 37

8

9

10 Layout................................................................... 80

10.1 Layout Guidelines ................................................. 80

10.2 Layout Example .................................................... 80

11 器件和文档支持 ..................................................... 81

11.1 器件支持................................................................ 81

11.2 文档支持................................................................ 81

11.3 接收文档更新通知 ................................................. 81

11.4 社区资源................................................................ 81

11.5 商标....................................................................... 81

11.6 静电放电警告......................................................... 81

11.7 Glossary................................................................ 81

12 机械、封装和可订购信息....................................... 81

7

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2019 年 6 月

*

最初发布版本。

2

TPS652170

www.ti.com.cn

ZHCSJX9 –JUNE 2019

5 Pin Configuration and Functions

RSL Package

48-Pin VQFN With Exposed Thermal Pad

Top View

VLDO2

VINLDO

VLDO1

BAT

1

36

35

34

33

32

31

30

29

28

27

26

25

ISET2

ISET1

ISINK1

ISINK2

2

3

4

BAT

5

VIN_DCDC3

L3

BAT_SENSE

SYS

6

Thermal

Pad

7

PGND

VDCDC3

SCL

SYS

8

PWR_EN

AC

9

10

11

12

SDA

TS

PGOOD

PB_IN

USB

NC – No internal connection

Pin Functions

I/O

DESCRIPTION

NAME

AC

NO.

10

41

I

AC-adapter input to power path. Connect this pin to an external dc supply.

Analog ground (GND). Connect the AGND pin to the ground plane.

Battery charger output. Connect these pins to the battery.

AGND

BAT

—

I/O

4, 5

Battery-voltage sense input. Connect the BAT_SENSE pin to the BAT pin directly at the battery

terminal.

BAT_SENSE

BYPASS

FB_WLED

INT_LDO

ISET1

6

I

O

I

47

38

48

35

Internal bias voltage (2.25 V). TI does not recommend connecting any external load to this pin.

Feedback pin for the WLED boost converter. This pin is also connected to the anode of the

WLED strings.

O

I

Internal bias voltage (2.3 V). TI does not recommend connecting any external load to this pin.

Low-level WLED current set. Connect this pin to a resistor to ground to set the WLED low-level

current value.

High-level WLED current set. Connect this pin to a resistor to ground to set the WLED high-level

current value.

ISET2

36

I

3

TPS652170

ZHCSJX9 –JUNE 2019

www.ti.com.cn

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

Input to the WLED current SINK1. Connect this pin to the cathode of the WLED string. Current

through the SINK1 pin equals current through the ISINK2 pin. If only one WLED string is used,

short the ISINK1 and ISINK2 pins together.

ISINK1

ISINK2

34

I

Input to the WLED current SINK2. Connect this pin to the cathode of the WLED string. Current

through the SINK1 pin equals current through the ISINK2 pin. If only one WLED string is used,

short the ISINK1 and ISINK2 pins together.

33

I

L1

L2

L3

L4

20

23

31

37

O

Switch pin for DCDC1. Connect this pin to the respective inductor.

Switch pin for DCDC2. Connect this pin to the respective inductor.

Switch pin for DCDC3. Connect this pin to the respective inductor.

Switch pin of the WLED boost converter. Connected this pin to the respective inductor.

Power-good signal for the LDO regulator (LDO1 and LDO2 only). This pin is a push-pull output.

This pin is pulled low when either the LDO1 or LDO2 regulator is out of regulation.

LDO_PGOOD

46

O

LS1_IN

LS1_OUT

LS2_IN

LS2_OUT

MUX_IN

MUX_OUT

NC

39

40

I

Input voltage pin for load switch 1 (LS1) or LDO3

Output voltage pin for load switch 1 (LS1) or LDO3

Input voltage pin for load switch 2 (LS2) or LDO4

Output voltage pin for load switch 2 (LS2) or LDO4

Input to analog multiplexer

O

I

42

43

O

14

16

Output pin of analog multiplexer

15, 17

Not used

Interrupt output. This pin is an active-low, open-drain output. This pin is pulled low if an interrupt

bit is set. The output goes high after the bit causing the interrupt in the INT register is read. The

interrupt sources can be masked in the INT register, such that no interrupt is generated when the

corresponding interrupt bit is set.

nINT

45

O

I

Reset pin. This pin is an active-low input. Pulling this pin low causes the PMIC to shut down.

When this pin returns to a high voltage level, the PMIC powers up in its default state after a 1-s

delay.

nRESET

44

nWAKEUP

PB_IN

13

25

30

26

O

I

Signal to the host to indicate a power-on event. This pin is an active-low, open-drain output.

Push-button monitor input. This pin is typically connected to a momentary switch to ground. This

pin is an active-low input.

PGND

Power ground. Connect this pin to the ground plane.

Power-good output. This pin is a push-pull output. This pin is pulled low when any of the power

rails are out of regulation.

PGOOD

O

I

Enable input for the DCDC1, DCDC2, and DCDC3 converters, and the LDO1, LDO2, LDO3, and

LDO4 regulators. Pull this pin high to start the power-up sequence.

PWR_EN

9

SCL

SDA

28

27

I

Clock input for the I²C interface

Data line for the I²C interface

I/O

System voltage pin and output of the power path. All voltage regulators are typically powered

from this output.

SYS

7, 8

O

Temperature sense input. Connect this pin to the NTC thermistor to sense the battery

temperature. This pin works with 10-kΩ and 100-kΩ thermistors. For more information, see the

Battery-Pack Temperature Monitoring section.

TS

11

I

USB

12

19

24

29

2

I

USB voltage input to power path. Connect this pin to an external voltage from a USB port.

DCDC1 output and feedback voltage-sense input

DCDC2 output and feedback voltage-sense input

DCDC3 output and feedback voltage-sense input

Input voltage for LDO1 and LDO2

VDCDC1

VDCDC2

VDCDC3

VINLDO

VIN_DCDC1

VIN_DCDC2

VIN_DCDC3

VIO

I

21

22

32

18

3

I

Input voltage for DCDC1. This pin must be connected to the SYS pin.

Input voltage for DCDC2. This pin must be connected to the SYS pin.

Input voltage for DCDC3. This pin must be connected to the SYS pin.

Output-high supply for output buffers

I

VLDO1

O

Output voltage of LDO1

4

TPS652170

www.ti.com.cn

ZHCSJX9 –JUNE 2019

Pin Functions (continued)

I/O

DESCRIPTION

NAME

NO.

VLDO2

1

O

Output voltage of LDO2

Power-ground connection for the PMIC. Connect the thermal pad to the ground plane.

Thermal pad

—

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

MIN

–0.3

0.3

MAX

7

UNIT

BAT

Supply voltage (with respect to PGND)

USB, AC

V

20

All pins unless specified separately

7

Input/output voltage (with respect to

PGND)

ISINK

20

V

L4, FB_WLED

44

Absolute voltage difference between SYS and any VIN_DCDCx pin or SYS and VINLDO

0.3

3000

6

V

Terminal current

SYS, USB, BAT

3000

6

mA

°C

Source or Sink current

Sink current

PGOOD, LDO_PGOOD

nWAKEUP, nINT

2

T_J

Operating junction temperature

Operating ambient temperature

Storage temperature

125

–40

–65

125

105

150

T_A

°C

T_stg

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

Electrostatic

discharge

V_(ESD)

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

4.3

NOM

MAX

5.8

5.5

2.5

1.3

2

UNIT

V

Supply voltage, USB, AC

Supply voltage, BAT

2.75

V

Input current from AC

A

Input current from USB

A

Battery current

A

Input voltage range for DCDC1, DCDC2, and DCDC3

Input voltage range for LDO1, LDO2

Input voltage range for LS1 or LDO3, LS2, or LDO4 configured as LDOs

Input voltage range for LS1 or LDO3, LS2, or LDO4 configured as load switches

Output voltage range for LDO1

2.7

1.8

2.7

1.8

1

5.8

3.3

V

Output voltage range for LDO2

0.9

1.8

V

Output voltage range for LS1 or LDO3, LS2, or LDO4

V

5

TPS652170

ZHCSJX9 –JUNE 2019

www.ti.com.cn

Recommended Operating Conditions (continued)

over operating ambient temperature range (unless otherwise noted)

MIN

0

NOM

MAX

UNIT

A

Output current DCDC1

1.2

Output current DCDC2

0

A

Output current DCDC3

0

1.2

A

Output current LDO1, LDO2

Output current LS1 or LDO3, LS2 or LDO4 configured as load switches⁽¹⁾

0

100

200

mA

0

(1) When LS1 (LDO3) and LS2 (LDO4) are configured as LDO regulators, the maximum output current can also be configured as 200 mA

or 400 mA.

6.4 Thermal Information

TPS652170

THERMAL METRIC⁽¹⁾

RSL (VQFN)

48 PINS

30.4

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

16.4

5.6

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.2

ψ_JB

5.6

R_θJC(bot)

1.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics

V_BAT= 3.6 V ±5%, T_J= 27ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

INPUT VOLTAGE AND CURRENTS

USB or AC supply connected

USB and AC not connected

Valid range for charging

0

2.75

4.3

5.5

V

V_BAT

Battery input voltage range

5.5

V_AC

AC adapter input voltage range

USB input voltage range

5.8

V

V_USB

4.3

UVLO[1:0] = 00b

2.73

2.89

3.18

3.3

Measured in respect to

V_BAT; supply falling;

V_AC= V_USB= 0 V

UVLO[1:0] = 01b

UVLO[1:0] = 10b

UVLO[1:0] = 11b

Undervoltage lockout

V

V_UVLO

UVLO accuracy

UVLO deglitch time⁽¹⁾

–2%

4

2%

6

ms

V_BAT< V_UVLO; Device shuts down when V_AC

V_USBdrop below V_UVLO+ V_OFFSET

,

V_OFFSET

AC and USB UVLO offset

200

6

mV

OFF current,

Total current into VSYS, VINDCDCx,

VINLDO

I_OFF

All rails disabled, T_A= 27°C

µA

Sleep current,

Total current into VSYS, VINDCDCx,

VINLDO

LDO1 and LDO2 enabled, no load.

All other rails disabled.

V_SYS= 4 V, T_A= 0.105°C

I_SLEEP

80

106

125

V_BAT> V_UVLO, AC and USB valid when V_AC-

_USB– V_BAT> V_IN(DT)

190

4.3

mV

V

V_IN(DT)

AC and USB voltage-detection threshold

V_BAT< V_UVLO, AC and USB valid when V_AC-USB

> V_IN(DT)

V_BAT> V_UVLO, AC and USB invalid when

V_AC/USB– V_BAT< V_IN(DT)

mV

V

AC and USB voltage-removal detection

threshold

V_IN(NDT)

V_BAT< V_UVLO, AC and USB invalid when V_AC-

_USB< V_IN(DT)

V_UVLO

+

V_OFFSET

(1) Not tested in production

6

TPS652170

www.ti.com.cn

ZHCSJX9 –JUNE 2019

Electrical Characteristics (continued)

V_BAT= 3.6 V ±5%, T_J= 27ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Voltage rising from 100 mV to 4.5 V. If rise time

is exceeded, device may not power up.

t_RISE

V_AC, V_USBrise time

50

ms

t_DG(DT)

Power detected deglitch⁽¹⁾

AC or USB voltage increasing

USB and AC input

22.5

6

ms

V

V_IN(OVP)

Input overvoltage detection threshold

5.8

6.4

POWER PATH TIMING

t_SW(PSEL)

Switching from AC to USB⁽¹⁾

150

µs

POWER PATH MOSFET CHARACTERISTICS

V_{DO, AC}

V_{DO, USB}

V_{DO, BAT}

AC input switch dropout voltage

USB input switch dropout voltage

Battery switch dropout voltage

IAC[1:0] = 11b (2.5 A), I_SYS= 1 A

IUSB[1:0] = 01b (500 mA), I_SYS= 500 mA

IUSB[1:0] = 10b (1300 mA), I_SYS= 800 mA

V_BAT= 3 V, I_BAT= 1 A

150

100

160

60

mV

POWER PATH INPUT CURRENT LIMITS

IAC[1:0] = 00b

IAC[1:0] = 01b

IAC[1:0] = 10b

IAC[1:0] = 11b

IUSB[1:0] = 00b

IUSB[1:0] = 01b

IUSB[1:0] = 10b

IUSB[1:0] = 11b

90

480

130

580

I_ACLMT

Input current limit; AC pin

mA

1000

2000

90

1500

2500

100

500

460

I_USBLMT

Input current limit; USB pin

Battery load current⁽¹⁾

mA

A

1000

1500

1300

1800

I_BAT

2

POWER PATH BATTERY SUPPLEMENT DETECTION

V_SYS≤ V_BAT– VBSUP1,

V_SYSfalling IUSB[1:0] = 10b

Battery supplement threshold

V_BSUP

40

20

mV

Battery supplement hysteresis

V_SYSrising

POWER PATH BATTERY PROTECTION

V_BAT(SC)

I_BAT(SC)

BAT pin short-circuit detection threshold

1.3

3.5

1.5

7.5

1.7

V

Source current for BAT pin short-circuit

detection

mA

INPUT BASED DYNAMIC POWER PATH MANAGEMENT (DPPM)

Threshold at which DPPM loop is

V_DPPM

I²C selectable

4.25

V

enabled

BATTERY CHARGER

I²C selectable

Battery charger voltage

4.1

4.25

1%

V_OREG

V

Battery charger accuracy

–2%

VPRECHG = 0b

VPRECHG = 1b

2.9

2.5

Precharge to fast-charge transition

threshold

V_LOWV

Deglitch time on precharge to fast-charge

transition⁽¹⁾

t_DGL1(LOWV)

t_DGL2(LOWV)

25

ms

Deglitch time on fast-charge to precharge

transition⁽¹⁾

ICHRG[1:0] = 00b

ICHRG[1:0] = 01b

ICHRG[1:0] = 10b

ICHRG[1:0] = 11b

ICHRG[1:0] = 00b

ICHRG[1:0] = 01b

ICHRG[1:0] = 10b

ICHRG[1:0] = 11b

300

400

500

700

30

Battery fast charge current range

I_CHG

V_OREG> V_BAT> V_LOWV

,

mA

450

25

550

75

V_IN= V_USB= 5 V

40

I_PRECHG

Precharge current

50

70

7

TPS652170

ZHCSJX9 –JUNE 2019

www.ti.com.cn

Electrical Characteristics (continued)

V_BAT= 3.6 V ±5%, T_J= 27ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

2.5%

7.5%

15%

18%

125

MAX UNIT

TERMIF[1:0] = 00b

TERMIF[1:0] = 01b

TERMIF[1:0] = 10b

TERMIF[1:0] = 11b

3%

10%

Charge current value for termination

detection threshold (fraction of I_CHG

I_TERM

)

t_DGL(TERM)

V_RCH

Deglitch time, termination detected⁽¹⁾

Recharge detection threshold

ms

Voltage below V_OREG

150

3

100

70

10

mV

ms

mA

Deglitch time, recharge threshold

detected⁽¹⁾

t_DGL(RCH)

I_BAT(DET)

125

7.5

Sink current for battery detection

T_J= 27°C

Battery detection timer. I_BAT(DET)is pulled

from the battery for t_DET. If BAT voltage

stays above V_RCHthreshold the battery is

connected.⁽¹⁾

t_DET

V_BAT< V_RCH;

250

ms

Safety timer range, thermal and DPPM not

active, selectable by I²C

t_CHG

Charge safety timer⁽¹⁾

4

8

h

Pre charge timer, thermal

and DPPM loops not

active, selectable by I²C

PCHRGT = 0b

PCHRGT = 1b

30

60

t_PRECHG

Precharge timer⁽¹⁾

min

BATTERY NTC MONITOR

Thermistor power on time at charger off,

sampling mode on

t_THON

10

1

ms

s

Thermistor power sampling period at

charger off, sampling mode on

t_THOFF

NTC_TYPE = 1 (10-kΩ NTC)

7.35

60.5

Pullup resistor from thermistor to Internal

LDO, I²C selectable

kΩ

mV

R_{NTC_PULL}

NTC_TYPE = 0 (100-kΩ NTC)

T_A= 27°C

Accuracy

–3%

3%

Temperature falling

Temperature rising

Temperature falling

1660

1610

910

V_LTF

Low-temperature failure threshold

TRANGE = 0b

Temperature rising

Temperature falling

Temperature rising

860

V_HTF

High-temperature failure threshold

Thermistor detection threshold

667

TRANGE = 1b

622

V_DET

1750

1850

mV

ms

Thermistor not detected. Battery not

present deglitch⁽¹⁾

t_BATDET

26

THERMAL REGULATION

Temperature regulation limit, temperature

at which charge current is decreased

T_J(REG)

111

2.7

123

°C

DCDC1 (BUCK)

V_IN

Input voltage range

VIN_DCDC1 pin

V_SYS

V

I_Q,SLEEP

Quiescent current in SLEEP mode

No load, V_SYS= 4 V, T_A= 25°C

30

40

µA

External resistor divider (XADJ1 = 1b)

0.6

0.9

V_IN

I²C selectable in 25-mV steps

(XADJ1 = 0b)

Output voltage range

V

1.8⁽²⁾

V_OUT

V_IN= V_OUT+ 0.3 V to 5.8 V;

0 mA ≤ I_OUT≤ 1.2 A

DC output voltage accuracy

–2%

3%

I_OUT= 1 mA, PFM mode

L = 2.2 µH, C_OUT= 20 µF

Power-save mode (PSM) ripple voltage

mV_pp

A

I_OUT

Output current range

0

1.2

High-side MOSFET on-resistance

Low-side MOSFET on-resistance

High-side MOSFET leakage current

Low-side MOSFET leakage current

V_IN= 2.7 V

V_IN= 5.8 V

V_DS= 5.8 V

170

120

r_DS(on)

mΩ

2

1

I_LEAK

µA

(2) Contact factory for 3.3-V option.

8

TPS652170

www.ti.com.cn

ZHCSJX9 –JUNE 2019

Electrical Characteristics (continued)

V_BAT= 3.6 V ±5%, T_J= 27ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

2.7 V < V_IN< 5.8 V

MIN

TYP

MAX UNIT

Current limit (high- and low-side

I_LIMIT

1.6

A

MOSFET).

f_SW

V_FB

t_SS

R_DIS

L

Switching frequency

Feedback voltage

Soft-start time

1.95

2.25

600

750

250

2.2

22

2.55

MHz

mV

µs

XADJ = 1b

Time to ramp V_OUTfrom 5% to 95%, no load

Internal discharge resistor at L1⁽³⁾

Ω

Inductor

1.5

10

µH

µF

Output capacitor

ESR of output capacitor

Ceramic

C_OUT

20

mΩ

DCDC2 (BUCK)

V_IN

Input voltage range

VIN_DCDC2 pin

2.7

V_SYS

V

I_Q,SLEEP

Quiescent current in SLEEP mode

No load, V_SYS= 4 V, T_A= 25°C

External resistor divider (XADJ2 = 1b)

30

µA

0.6

0.9

V_IN

3.3

I²C selectable in 25-mV steps

(XADJ2 = 0b)

Output voltage range

V

V_OUT

V_IN= V_OUT+ 0.3 V to 5.8 V;

0 mA ≤ I_OUT≤ 1.2 A

DC output voltage accuracy

–2%

3%

I_OUT= 1 mA, PFM mode

L = 2.2 µH, C_OUT= 20 µF

Power-save mode (PSM) ripple voltage

40

mV_pp

A

I_OUT

Output current range

0

1.2

High-side MOSFET on-resistance

Low-side MOSFET on-resistance

High-side MOSFET leakage current

Low-side MOSFET leakage current

V_IN= 2.7 V

V_IN= 5.8 V

V_DS= 5.8 V

170

120

r_DS(on)

mΩ

2

1

I_LEAK

µA

A

Current limit (high and low side

MOSFET).

I_LIMIT

2.7 V < V_IN< 5.8 V

1.6

f_SW

V_FB

t_SS

R_DIS

L

Switching frequency

Feedback voltage

Soft-start time

1.95

2.25

600

750

250

2.2

22

2.55

MHz

mV

µs

XADJ = 1b

Time to ramp V_OUTfrom 5% to 95%, no load

Internal discharge resistor at L2

Inductor

Ω

1.5

10

µH

µF

Output capacitor

Ceramic

C_OUT

ESR of output capacitor

20

mΩ

DCDC3 (BUCK)

V_IN

Input voltage range

VIN_DCDC3 pin

2.7

V_SYS

V

I_Q,SLEEP

Quiescent current in SLEEP mode

No load, V_SYS= 4 V, T_A= 25°C

External resistor divider (XADJ3 = 1b)

30

µA

0.6

0.9

V_IN

I²C selectable in 25-mV steps

(XADJ3 = 0b)

Output voltage range

V

1.5⁽²⁾

V_OUT

V_IN= V_OUT+ 0.3 V to 5.8 V;

0 mA ≤ I_OUT≤ 1.2 A

DC output voltage accuracy

–2%

3%

I_OUT= 1 mA, PFM mode

L = 2.2 µH, C_OUT= 20 µF

Power save mode (PSM) ripple voltage

40

mV_pp

A

I_OUT

Output current range

0

1.2

High-side MOSFET on-resistance

Low side MOSFET on-resistance

High-side MOSFET leakage current

Low-side MOSFET leakage current

V_IN= 2.7 V

V_IN= 5.8 V

V_DS= 5.8 V

170

120

r_DS(on)

mΩ

2

1

I_LEAK

µA

A

Current limit (high- and low-side

MOSFET).

I_LIMIT

2.7 V < V_IN< 5.8 V

1.6

f_SW

Switching frequency

Feedback voltage

1.95

2.25

600

2.55

MHz

mV

V_FB

XADJ = 1b

(3) Can be factory disabled.

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TPS652170

ZHCSJX9 –JUNE 2019

www.ti.com.cn

Electrical Characteristics (continued)

V_BAT= 3.6 V ±5%, T_J= 27ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

750

250

2.2

22

MAX UNIT

t_SS

R_DIS

L

Soft-start time

Time to ramp V_OUTfrom 5% to 95%, no load

µs

Ω

Internal discharge resistor at L1, L2

Inductor

1.5

10

µH

µF

mΩ

Output capacitor

Ceramic

C_OUT

ESR of output capacitor

20

LDO1, LDO2

V_IN

Input voltage range

1.8

5.8

V

I_Q,SLEEP

Quiescent current in SLEEP mode

No load, V_SYS= 4 V, T_A= 25°C

LDO1, I²C selectable

5

µA

1

3.3

Output voltage range

V

LDO2, I²C selectable

0.9

I_OUT= 10 mA, V_IN> V_OUT+ 200 mV,

V_OUT> 0.9 V

DC output voltage accuracy

Line regulation

–2%

–1%

2%

1%

V_IN= 2.7 V - 5.5 V, V_OUT= 1.2 V,

I_OUT= 100 mA

V_OUT

I_OUT= 1 mA - 100 mA, V_OUT= 1.2 V,

V_IN= 3.3 V

–1%

1%

Load regulation

I_OUT= 0 mA - 1 mA, V_OUT= 1.2 V,

V_IN= 3.3 V

–2.5%

2.5%

SLEEP state

0

1

I_OUT

Output current range

mA

ACTIVE state

100

I_SC

Short circuit current limit

Dropout voltage

Output shorted to GND

I_OUT= 100 mA, V_IN= 3.3 V

100

250

mA

mV

Ω

V_DO

R_DIS

200

Internal discharge resistor at output

Output capacitor

430

2.2

20

Ceramic

µF

C_OUT

ESR of output capacitor

mΩ

LS1 OR LDO3, AND LS2 OR LDO4, CONFIGURED AS LDOs

V_IN

Input voltage range

2.7

5.8

V

I_Q,SLEEP

Quiescent current in SLEEP mode

No load, V_SYS= 4 V, T_A= 25°C

30

µA

LS1LDO3 = 1b, LS2LDO4 = 1b

I²C selectable

Output voltage range

DC output voltage accuracy

Line regulation

1.5

–2%

–1%

3.3

2%

1%

V

I_OUT= 10 mA, V_IN> V_OUT+ 200 mV,

V_OUT> 1.8 V

V_OUT

V_IN= 2.7 V - 5.5 V, V_OUT= 1.8 V,

I_OUT= 200 mA

I_OUT= 1 mA - 200 mA, V_OUT= 1.8 V,

V_IN= 3.3 V

Load regulation

1%

V_DO

Dropout voltage

Internal discharge resistor at output⁽³⁾

I_OUT= 200 mA, V_IN= 3.3 V

200

mV

Ω

R_DIS

375

10

Output capacitor

Ceramic

8

12

µF

mΩ

C_OUT

ESR of output capacitor

20

LS1 OR LDO3, AND LS2 OR LDO4, CONFIGURED AS LOAD SWITCHES

V_IN

Input voltage range

LS1_VIN, LS2_VIN pins

1.8

200

1

5.8

V

R_DS(ON)

I_SC

P-channel MOSFET on-resistance

Short circuit current limit

Internal discharge resistor at output

Output capacitor

V_IN= 1.8 V, over full temperature range

Output shorted to GND

300

280

375

10

650

mΩ

mA

Ω

R_DIS

Ceramic

12

µF

mΩ

C_OUT

ESR of output capacitor

20

WLED BOOST

V_IN

Input voltage range

2.7

32

37

5.8

39

V

Ω

V_OUT

Max output voltage

I_SINK= 20 mA

V_IN= 3.6 V

V_OVP

Output overvoltage protection

N-channel MOSFET on-resistance

38

R_DS(ON)

0.6

10

TPS652170

www.ti.com.cn

ZHCSJX9 –JUNE 2019

Electrical Characteristics (continued)

V_BAT= 3.6 V ±5%, T_J= 27ºC (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

2

MAX UNIT

I_LEAK

I_LIMIT

f_SW

N-channel leakage current

N-channel MOSFET current limit

Switching frequency

V_DS= 25 V, T_A= 25°C

µA

1.6

1.125

1.1

2.1

18

1.9

A

MHz

V_IN= 3.6 V, 1% duty cycle setting

V_IN= 3.6 V, 100% duty cycle setting

I_INRUSH

L

Inrush current on start-up

A

Inductor

µH

µF

Output capacitor

ESR of output capacitor

Ceramic

4.7

20

C_OUT

mΩ

WLED CURRENT SINK1, SINK2

Overvoltage protection threshold at

ISINK1, ISINK2 pins

V_SINK1,2

19

25

V

V_{DO, SINK1,2}

V_ISET1,2

Current sink drop-out voltage

ISET1, ISET2 pin voltage

Measured from ISINK to GND

400

mV

V

1.24

WLED current range (ISINK1, ISINK2)

1

R_ISET= 130.0 kΩ

10

15

20

25

R_ISET= 86.6 kΩ

mA

WLED sink current

R_ISET= 64.9 kΩ

R_ISET= 52.3 kΩ

I_SINK1,2

DC current set accuracy

DC current matching

I_SINK= 5 mA to 25 mA, 100% duty cycle

–5%

5%

R_SET1= 52.3 kΩ, I_SINK= 25 mA,

V_BAT= 3.6 V, 100% duty cycle

R_SET1= 130 kΩ, I_SINK= 10 mA,

V_BAT= 3.6 V, 100% duty cycle

–5%

5%

FDIM[1:0] = 00b

FDIM[1:0] = 01b

FDIM[1:0] = 10b

FDIM[1:0] = 11b

100

200

f_PWM

PWM dimming frequency

Hz

500

1000

ANALOG MULTIPLEXER

Gain, VBAT (V_BAT/ V_OUT,MUX); VSYS

3

1

(V_SYS/ V_OUT,MUX

)

V/V

Gain, VTS (V_TS/ V_OUT,MUX); MUX_IN

(V_{MUX_IN}/ V_{MUX_OUT}

)

g

ICHRG[1:0] = 00b

ICHRG[1:0] = 01b

ICHRG[1:0] = 10b

ICHRG[1:0] = 11b

7.575

5.625

4.5

Gain, V_ICHARGE(V_OUT,MUX/ V_ICHARGE

)

V/A

V

3.214

V_SYS= 3.6 V, MUX[2:0] = 101b

(V_{MUX_IN}– V_{MUX_OUT}) / V_{MUX_IN}> 1%

V_OUT

Buffer headroom (V_SYS– V_{MUX_OUT}

)

0.7

1

R_OUT

I_LEAK

Output Impedance

Leakage current

180

Ω

MUX[2:0] = 000b (HiZ), V_MUX= 2.25 V

µA

LOGIC LEVELS AND TIMING CHARACTERISTICS

(SCL, SDA, PB_IN, PGOOD, LDO_PGOOD, PWR_EN, nINT, nWAKEUP, nRESET)

Output voltage falling, % of set voltage

90%

95%

PGOOD comparator treshold,

P_GTH

All DC/DC converters and LDOs⁽¹⁾

Output voltage rising, % of set voltage

Output voltage falling, DCDC1, DCDC2,

DCDC3

2

1

4

2

P_GDG

PGOOD deglitch time

ms

Output voltage falling, LDO1, LDO2, LDO3,

LDO4

PGDLY[1:0] = 00b

PGDLY[1:0] = 01b

PGDLY[1:0] = 10b

PGDLY[1:0] = 11b

20

100

200

400

8

P_GDLY

PGOOD delay time

ms

s

t_HRST

PB-IN hard-reset-detect time⁽¹⁾

11

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ZHCSJX9 –JUNE 2019

www.ti.com.cn

Electrical Characteristics (continued)

V_BAT= 3.6 V ±5%, T_J= 27ºC (unless otherwise noted)

PARAMETER

PB_IN pin deglitch time⁽¹⁾

TEST CONDITIONS

MIN

TYP

50

MAX UNIT

t_DG

PWR_EN pin deglitch time⁽¹⁾

nRESET pin deglitch time⁽¹⁾

PB_IN internal pullup resistor

nRESET internal pullup resistor

50

ms

30

100

R_PULLUP

kΩ

High-level input voltage

PB_IN, SCL, SDA, PWR_EN, nRESET

V_IH

V_IL

1.2

0

V_IN

0.4

1

V

Low-level input voltage

PB_IN, SCL, SDA, PWR_EN, nRESET

Input bias current

PB_IN, SCL, SDA

I_BIAS

0.01

µA

nINT, nWAKEUP, I_O= 1 mA

0.3

V_OL

Output low voltage

V

PGOOD, LDO_PGOOD, I_O= 1 mA

V_OH

Output high voltage

V_IO– 0.3

V

Pin leakage current

nINT, nWAKEUP

I_LEAK

Pin pulled up to 3.3-V supply

0.2

µA

I²C slave address

0x24h

9

OSCILLATOR

Oscillator frequency

MHz

f_OSC

Oscillator frequency accuracy

T_A= –40°C to 105°C

–10%

10%

OVERTEMPERATURE SHUTDOWN

Overtemperature shutdown

Increasing junction temperature

Decreasing junction temperature

150

20

°C

T_OTS

Hysteresis

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ZHCSJX9 –JUNE 2019

6.6 I²C Timing Requirements

V_BAT= 3.6 V ±5%, T_A= 25ºC, C_L= 100 pF (unless otherwise noted). For the I²C timing diagram, see Figure 1.

MIN

100

4

NOM

MAX

UNIT

kHz

µs

f_SCL

Serial clock frequency

400

Hold time (repeated) START

condition. After this period, the first

clock pulse is generated

SCL = 100 KHz

SCL = 400 KHz

t_HD;STA

600

ns

µs

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

SCL = 100 KHz

SCL = 400 KHz

4.7

1.3

4

t_LOW

t_HIGH

t_SU;STA

t_HD;DAT

t_SU;DAT

t_r

LOW period of the SCL clock

HIGH period of the SCL clock

µs

ns

µs

ns

µs

ns

600

4.7

600

0

Set-up time for a repeated START

condition

3.45

900

Data hold time

0

250

100

Data set-up time

ns

1000

300

Rise time of both SDA and SCL

signals

Fall time of both SDA and SCL

signals

t_f

4

600

4.7

1.3

NA

0

µs

ns

t_SU;STO

t_BUF

t_SP

Set-up time for STOP condition

Bus free time between stop and start

condition

µs

NA

50

Pulse duratoin of spikes which mst

be suppressed by the input filter

ns

400

C_b

Capacitive load for each bus line

pF

SDA

t_SU;DAT

t_f

t_LOW

t_r

t_HD;STA

t_SP

t_r

t_BUF

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_f

t_HD;DATt_HIGH

S

S_r

P

S

Figure 1. I²C Data Transmission Timing

13

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ZHCSJX9 –JUNE 2019

www.ti.com.cn

6.7 Typical Characteristics

100%

95%

90%

85%

80%

75%

70%

65%

60%

55%

50%

3.3 Vout

1.8 Vout

1.1 Vout

0.000

0.200

0.400

0.600

0.800

1.000

1.200

Load Current (A)

Figure 2. TPS652170 DC/DC Efficiency, 5 V_INand an LQM2HPN2R2MG0L Inductor

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TPS652170

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ZHCSJX9 –JUNE 2019

7 Detailed Description

7.1 Overview

The TPS652170 device has three step-down converters, two low-dropout (LDO) regulators, two load switches, a

linear battery charger, a white LED driver, and a power path. The system can be supplied by any combination of

a USB port, 5-V AC adaptor, or Li-ion battery. The device is characterized across a temperature range from

–40°C to +105°C, making it suitable for industrial applications where a 5-V power supply rail is available. The

device offers configurable power-up and power-down sequencing and several low-speed, system-level functions

such as a power-good output, push-button monitor, hardware-reset function, and temperature sensor to protect

the battery.

The I²C interface has comprehensive features for using the TPS652170 device. All rails, load switches, and LDO

regulators can be enabled or disabled. Power-up and power-down sequences, overtemperature thresholds, and

overcurrent threshold can be programmed through the I²C interface. The I²C interface also monitors battery

charging and controls LED dimming parameters.

The three DC/DC step-down converters can each supply up to 1.2 A of current. The output voltages for each

converter can be adjusted through the I²C interface in real time to support processor clock frequency changes.

All three converters feature dynamic voltage positioning to decrease voltage undershoots and overshoots.

Typically, the converters work at a fixed-frequency of 2.25 MHz, pulse-width modulation (PWM) at moderate-to-

heavy load currents. At light load currents the converters automatically go to power save mode and operate in

pulse-frequency modulation (PFM) for maximum efficiency across the widest possible range of load currents. For

low-noise applications, each converter can be forced into fixed-frequency PWM using the I²C interface. The step-

down converters allow the use of small inductors and capacitors to achieve a small solution size.

The device has two traditional LDO regulators: LDO1 and LDO2. The LDO1 and LDO2 regulators can support up

to 100 mA each during normal operation, but in the SLEEP state they are limited to 1 mA to decrease quiescent

current while supporting system-standby mode. The TPS652170 variant of the device also has two load

switches, LS1 and LS2, that can alternately be configured as LDO regulators, LDO3 and LDO4, respectively. The

LDO3 and LDO4 regulators can also be configured with to support a maximum load of up to 200 mA or 400

mA.All four LDO regulators have a wide input voltage range that allows them to be supplied either from one of

the DC/DC converters or directly from the system voltage node.

The device has two power-good logic signals. The primary power-good signal, PGOOD, monitors the DCDC1,

DCDC2, and DCDC3 converters, and LS1 (or LDO3) and LS2 (or LDO4) configurable power outputs. This signal

is high in the ACTIVE state, but low in the SLEEP, RESET, and OFF states. The secondary power-good signal,

LDO_PGOOD, monitors LDO1 and LDO2; the signal is high in the ACTIVE and SLEEP states, but low in the

RESET and OFF states. The PGOOD and LDO_PGOOD signals are both pulled low when all the monitored rails

are pulled low, or when one or more of the monitored rails are enabled and have encountered a fault, typically an

output short or overcurrent condition.

The highly-efficient boost converter has two current sinks that can drive two strings of up to 10 LEDs at 25 mA

each, or one string of 20 LEDs at 50 mA. An internal PWM signal and I²C control support brightness and

dimming. Both current sources are controlled together and cannot operate independently.

The triple system power path lets simultaneous and independent powering of the system and battery charging

through the linear battery charger for single-cell Li-ion and Li-Polymer batteries. The AC input is prioritized over

USB input as the power source for charging the battery and powering the system. Both these sources are

prioritized over the battery for powering the system to decrease the number of charge and discharge cycles on

the battery.

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7.2 Functional Block Diagram

4.7 mF

AC

SYS

BAT

Q1

from USB connector

to system load

USB

Q1

from USB connector

22 mF

4.7 mF

Linear Charger

and

Power-Path

Management

VBAT

VSYS

VICHARGE

VTS

Single-Cell

Li+ Battery

MUX_OUT

Q2

to system host or µC

MUX

100 nF

MUX_IN

10 mF

BAT_SENSE

from system

TS

INT_LDO

TEMP SENSE

100 nF

NTC

BIAS

BYPASS

10 mF

VIO

I/O Voltage

PWR_EN

from system host or µC

PGOOD

LDO_PGOOD

nWAKEUP

nINT

to system host or µC

Always-on

supply

Momentatary Push-Button

100 kW

PB_IN

100 kW VIO (always on)

DIGITAL

Always-on

supply

100 kW

nRESET

from system host or µC

4.7 mF

VIO

SCL

VIN_DCDC1

from system host or µC

SYS

VIO

I²C

SDA

from system host or µC

L1

to system

L4

DCDC1

VDCDC1

10 mF

SYS

4.7 mF

FB_WLED

VIN_DCDC2

SYS

4.7 mF

Up to 2 ´10 LEDs

WLED

Driver

L2

to system

ISINK1

ISINK2

ISET1

ISET2

DCDC2

VDCDC2

10 mF

4.7 mF

VIN_DCDC3

SYS

L3

to system

4.7 mF

DCDC3

VDCDC3

10 mF

VINDO

SYS

VLDO1

LS1_IN

to system

from 1.8-V to 5.8-V supply

to system load

LDO1

LDO2

LS1_OUT

LOAD SW1

or LDO3

VLDO2

to system

10 mF

2.2 mF

LS2_IN

from 1.8-V to 5.8-V supply

to system load

LS2_OUT

LOAD SW2

or LDO4

10 mF

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7.3 Feature Description

7.3.1 Wake-Up and Power-Up Sequencing

The TPS652170 device has a predefined power-up–power-down sequence which, in a typical application, does

not require changing. However, users can define custom sequences through I²C control. The power-up sequence

is defined by strobes and delay times. Each output rail is assigned to a strobe to determine the order in which the

rails are enabled. The delay times from one strobe to the next are programmable in a range from 1 ms to 10 ms.

NOTE

Although the user can modify the power-up and power-down sequence through the SEQx

registers, those registers are reset to default values when the device goes to the SLEEP,

OFF, or RESET state. In practice, this situation means that the power-up sequence is

fixed and a custom power-down sequence must be written each time the device is

powered up.

Custom power-up and power-down sequences can be tested and verified in the ACTIVE

state (PWR_EN pin pulled high) by using I²C to toggle the SEQUP and SEQDWN bits.

Permanent changes to the default power-up sequence timing require custom programming

at the TI factory.

7.3.1.1 Power-Up Sequencing

When the power-up sequence is initiated, STROBE1 occurs and any rail assigned to this strobe is enabled. After

a delay time of DLY1, STROBE2 occurs and the rail assigned to this strobe is powered up. The sequence

continues until all strobes have occurred and all DLYx times have been executed.

AC

(input)

USB

(input)

PB

(input)

nWAKEUP

(output)

PWR_EN

(input)

5s max

DLY6

DLY1

DLY2

DLY3

DLY4

DLY5

DLY6

STROBE15

SEQ = 1111

STROBE14

SEQ = 1110

STROBE 1

SEQ = 0001

STROBE 2

SEQ = 0010

STROBE 3

SEQ = 0011

STROBE 4

SEQ = 0100

STROBE 5

SEQ = 0101

STROBE 6

SEQ = 0110

STROBE 7

SEQ = 0111

The power-up sequence is defined by strobes and delay times. In this example, push-button low is the power-up

event.

Figure 3. Power-Up Sequence

The default power-up sequence can be changed by writing to the SEQ1 through SEQ6 registers. Strobes are

assigned to rails by writing to the SEQ1 through SEQ4 registers. A rail can be assigned to only one strobe but

multiple rails can be assigned to the same strobe. Delays between strobes are defined in the SEQ5 and SEQ6

registers.

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Feature Description (continued)

STROBE15 STROBE1

STROBE2

STROBE3

STROBE4

DLY1

5ms

DLY2

1ms

DLY3

1ms

VSYS

(1)

WAKEUP

PWR_EN (DG) ⁽²⁾

(3)

LDO1

LDO2

DCDC1

DCDC2

DCDC3

LS1

LS2

PGDLY 20 ms

PGOOD

For default power-up sequences of the other TPS65217x family members, refer to the Powering the AM335x with the

TPS65217x user's guide.

Figure 4. Default Power-Up Sequence for the TPS65217A Device

The power-up sequence is executed if the following events occurs:

From the OFF state (going to the ACTIVE state):

•

Push-button is pressed (falling edge on PB_IN) OR

USB voltage is asserted (rising edge on USB) OR

The AC adaptor is inserted (rising edge on the AC pin)

The PWR_EN pin is level-sensitive (opposed to edge-sensitive), and the pin can be asserted before or after the

previously listed power-up events. However, the PWR_EN pin must be asserted within 5 s of the power-up event;

otherwise, the power-down sequence is triggered and the device goes to the OFF state. If a fault occurs because

the device is in undervoltage lockout (UVLO) or requires overtemperature shutdown (OTS), the device goes to

the OFF state.

From the SLEEP state (going to the ACTIVE state):

•

The push-button is pressed (falling edge on the PB_IN pin) OR

The USB voltage is asserted (rising edge on the USB pin) OR

The AC adaptor is inserted (rising edge on the AC pin) OR

The PWR_EN pin is asserted (pulled high).

In the SLEEP state, the power-up sequence can be triggered by asserting the PWR_EN pin only, and the push-

button press or AC and USB assertion are not required. If a fault occurs because the device is in undervoltage

lockout (UVLO) or requires overtemperature shutdown (OTS), the device goes to the OFF state.

In the ACTIVE state:

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Feature Description (continued)

The sequencer can be triggered any time by setting the SEQUP bit in the SEQ6 register high. The SEQUP bit is

automatically cleared after the sequencer is complete.

Rails that are not assigned to a strobe (the SEQ bit set to 0000b) are not affected by power-up and power-down

sequencing and stay in their current ON or OFF state regardless of the sequencer. Any rail can be enabled or

disabled at any time by setting the corresponding enable bit in the ENABLE register with the only exception that

the ENABLE register cannot be accessed while the sequencer is active. Enable bits always reflect the current

enable state of the rail, that is, the sequencer sets or resets the enable bits for the rails under its control. Also,

whenever faults occur which shut-down the power-rails, the corresponding enable bits are reset.

7.3.1.2 Power-Down Sequencing

By default, power-down sequencing follows the reverse power-up sequence. When the power-down sequence is

triggered, STROBE7 occurs first, and any rail assigned to STROBE7 is shut down. After a delay time of DLY6,

STROBE6 occurs, and any rail assigned to STROBE6 is shut down. The sequence continues until all strobes

have occurred and all DLYx times have been executed.

In some applications, all rails may be required to shut down at the same time with no delay between rails. Set the

INSTDWN bit in the SEQ6 register to bypass all delay times and shut-down all rails at the same time when the

power-down sequence is triggered.

A power-down sequence is executed if one of the following events occurs:

•

The SEQDWN bit is set.

The PWR_EN pin is pulled low.

The push-button is pressed for more than 8 s.

The nRESET pin is pulled low.

A fault occurs in the device (either an OTS, UVLO, or PGOOD failure).

The PWR_EN pin is not asserted (pulled high) within 5 s of a power-up event and the OFF bit is set to 1b.

When the device goes from the ACTIVE to the OFF state, any rail not controlled by the sequencer is shut down

after the power-down sequencer is complete. When the device goes from the ACTIVE to the SLEEP state, any

rail not controlled by the power-down sequencer stays in its present state.

PWR_EN

(input)

DLY6

DLY5

DLY4

DLY3

DLY2

DLY1

DLY5

DLY6

STROBE 7

SEQ = 0111

STROBE 6

SEQ = 0110

STROBE 5

SEQ = 0101

STROBE 4

SEQ = 0100

STROBE 3

SEQ = 0011

STROBE 2

SEQ = 0010

STROBE 1

SEQ = 0001

STROBE14

SEQ = 1110

STROBE15

SEQ = 1111

Figure 5. Power-Down Sequence from ON State to OFF State (All Rails Turned OFF)

PWR_EN

(input)

DLY6

DLY5

DLY4

DLY3

DLY2

DLY1

STROBE 7

SEQ = 0111

STROBE 6

SEQ = 0110

STROBE 5

SEQ = 0101

STROBE 4

SEQ = 0100

STROBE 3

SEQ = 0011

STROBE 2

SEQ = 0010

STROBE 1

SEQ = 0001

STROBE14 and STROBE15 are omitted to let the LDO1 or LDO2 regulators stay ON.

Figure 6. Power-Down Sequence from ON State to SLEEP State

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Feature Description (continued)

7.3.1.3 Special Strobes (STROBE 14 and 15)

STROBE 14 and STROBE 15 are not assigned to the sequencer but used to control rails that are always-on, that

is, are powered up as soon as the device goes out of the OFF state and stay ON in the SLEEP state. STROBE

14 and STROBE 15 options are available only for the LDO1 and LDO2 rails and not for any of the other rails.

STROBE 15 occurs as soon as the push-button is pressed or the USB or AC adaptor is connected to the device.

STROBE 14 occurs after a delay time of DLY6. The LDO1 and LDO2 rails can be assigned to either strobe but

by default only LDO1 is assigned to special STROBE 15 (default settings must be programmed by TI at the

factory because all registers are reset during transitions to the OFF or SLEEP states).

When a power-down sequence is initiated, STROBE 15 and STROBE 14 occur only if the OFF bit is set.

Otherwise both strobes are omitted, and the LDO1 and LDO2 rails keep their state.

7.3.2 Power Good

The power-good signals are used to indicate if an output rail is in regulation or at fault. Internally, all power-good

signals of the enabled rails are monitored at all times and if any of the signals goes low, a fault is declared. All

power-good signals are internally deglitched. When a fault occurs, all output rails are powered down and the

device goes to the OFF state.

The TPS652170 device has two power-good output pins: one is dedicated to the LDO1 and LDO2 rails

(LDO_PGOOD) and one for all other rails (PGOOD). The power-good signals that are indicated by the PGOOD

pin are programmable. The following rules apply to both output pins:

•

The power-up default state for the PGOOD pin and the LDO_PGOOD pin is low. When all rails are disabled,

the PGOOD and LDO_PGOOD pins are both low.

•

Only enabled rails are monitored. Disabled rails are ignored.

Power-good monitoring of a particular rail starts 5 ms after the rail has been enabled. The power-good signal

is continuously monitored after the 5-ms deglitch time expires.

•

The signals controlling the PGOOD and LDO_PGOOD pins are delayed by the PGDLY (20 ms default) after

the sequencer is done.

If a fault occurs on an enabled rail (such as a shorted output, OTS condition, or UVLO condition), the PGOOD

pin, LDO_PGOOD pin, or both pins are pulled low, and all rails are shut down.

If the user disables a rail (either manually or through the sequencer), this action has no effect on the PGOOD

or LDO_PGOOD pin.

If the user disables all rails (either manually or through the sequencer), the PGOOD pin, LDO_PGOOD pin, or

both pins are pulled low.

7.3.2.1 LDO1, LDO2 Power-Good (LDO_PGOOD)

The LDO_PGOOD pin is a push-pull output that is driven to a high level when either the LDO1 regulator or the

LDO2 regulator is enabled and in regulation. The LDO_PGOOD pin is pulled low when both LDO regulators are

disabled or one is enabled but has encountered a fault. A typical fault is an output short or overcurrent condition.

In normal operation, the LDO_PGOOD pin is high in the ACTIVE and SLEEP states and low in the RESET and

OFF states.

7.3.2.2 Primary Power-Good (PGOOD)

The primary PGOOD pin has similar functionality to the LDO_PGOOD pin except that PGOOD monitors the

DCDC1, DCDC2, and DCDC3 converters, and the LDO3 and LDO4 outputs configured as LDO regulators. The

user can also choose to monitor the LDO1 and LDO2 regulators by setting the LDO1PGM and LDO2PGM mask

bits low in the DEFPG register. By default, the power-good signal of the LDO1 and LDO2 regulators does not

affect the PGOOD pin (mask bits are set to 1b by default). In normal operation the PGOOD pin is high in the

ACTIVE state but low in the SLEEP, RESET, and OFF states.

In the SLEEP state and the WAIT PWR_EN state, the PGOOD pin is forced low. The PGOOD pin is set high

after the device goes to the ACTIVE state, the power sequencer is complete, and the PGDLY time is expired.

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Feature Description (continued)

7.3.2.3 Load Switch PGOOD

When either LS1 or LS2 is configured as a load switch, the device ignores the respective power-good signal. An

overcurrent or short condition present on the LS1 or LS2 load switch does not affect the PGOOD pin or any of

the power rails unless the power dissipation leads to thermal shutdown.

VSYS

5s max

PB_IN

nWAKEUP

PWR_EN (deglitched)

LDO1

5ms

PG LDO1 (internal)

DLY5

LDO2

PG LDO2 (internal)

DCDC1

5ms

PG DCDC1 (internal)

FAULT

DLY1

DCDC2

PG DCDC2 (internal)

DCDC3

5ms

DLY2

5ms

DLY3

PG DCDC3 (internal)

LS1/LDO3

5ms

PG LS1/LDO3 (internal)

LS2/LDO4

DLY6+DLY5+DLY4

DLY3

5ms

PG LS2/LDO4 (internal)

LDO_PGOOD

PG_DLY

PGOOD

This figure also shows the power-down sequence for the case of a short on the DCDC2 output.

Figure 7. Default Power-Up Sequence

7.3.3 Push-Button Monitor (PB_IN)

The TPS652170 device has an active-low PB_IN input pin that is typically connected to ground through a push-

button switch. The PB_IN input has a 50-ms deglitch time and an internal pull-up resistor that is connected to an

always-on supply. The always-on supply is an unregulated internal power rail that is functionally equivalent to the

power path. The source of the always-on supply is the same as the source of the SYS pin. The push-button

monitor has two functions. The first is to power-up the device from the OFF or SLEEP state when a falling edge

is detected on the PB_IN pin. The second is to power cycle the device when the PB_IN pin is held low for more

than 8 s.

For a description of each function, see the Device Functional Modes section. A change in push-button status (the

PB_IN pin goes from high to low or low to high) is signaled to the host through the PBI interrupt bit in the INT

register. The current status of the interrupt can be checked by reading the PB status bit in the STATUS register.

Figure 8 shows a timing diagram for the push-button monitor.

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Feature Description (continued)

PB is released before

INT register is read

through I²C. INT pin

remains low, PB status

bit is reset.

PB is pressed,

INT pin is pulled

low, PB status

bit is reset.

PB is pressed,

INT pin is pulled

low, PB status

bit is set.

PB is pressed,

INT pin is pulled

low, PB status

bit is set.

PB_IN pin (input)

PBI interrupt bit

nINT pin (output)

PB status bit

I²C access to INT register

INT register is read

through I²C. INT pin is

released.

INT register is read

through I²C.

INT register is read

through I²C while PB

remains pressed. INT

pin is released, PB

status bit remains set.

Figure 8. Timing Diagram of the Push-Button Monitor Circuit

7.3.4 nWAKEUP Pin (nWAKEUP)

The nWAKEUP pin is an open-drain, active-low output that is used to signal a wakeup event to the system host.

This pin is pulled low whenever the device is in the OFF or SLEEP state and detects a wakeup event as

described in the Device Functional Modes section. The nWAKEUP pin is delayed for 50 ms over the power-up

event and stays low for 50 ms after the PWR_EN pin has been asserted. If the PWR_EN pin is not asserted

within 5 s of the power-up event, the device shuts down and goes to the OFF state. In the ACTIVE state, the

nWAKEUP pin is always high. Figure 9 shows the timing diagram for the nWAKEUP pin.

7.3.5 Power Enable Pin (PWR_EN)

The PWR_EN pin is used to keep the device in the ACTIVE mode after it detects a wakeup event as described

in the Device Functional Modes section. If the PWR_EN pin is not asserted within 5 s of the nWAKEUP pin being

pulled low, the device shuts down the power and goes to either the OFF or SLEEP state, depending on the OFF

bit in the STATUS register. The PWR_EN pin is level-sensitive, meaning that PWR_EN may be pulled high

before the wake-up event.

The PWR_EN pin can also be used to toggle between the ACTIVE and SLEEP states. For more information, see

SLEEP in the PMIC States section.

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Feature Description (continued)

AC

(input)

USB

(input)

PB_IN

(input)

50 ms

deglitch

nWAKEUP

(output)

50 ms

deglitch

PWR_EN

(input)

5s max

(1) In the example shown, the wakeup event is a falling edge on the PB_IN.

(2) If the PWR_EN pin is not asserted within 5 s of the WAKEUP pin being pulled low, the device goes to the OFF or

SLEEP state

Figure 9. nWAKEUP Timing Diagram

7.3.6 Reset Pin (nRESET)

When the nRESET pin is pulled low, all power rails, including LDO1 and LDO2, are powered down, and the

default register settings are restored. The device stays powered down as long as the nRESET pin is held low,

but for a minimum of 1 s. After the nRESET pin is pulled high, the device goes to the ACTIVE state, and the

default power-up sequence executes. For more information, see RESET in the PMIC States section.

7.3.7 Interrupt Pin (nINT)

The interrupt pin is used to signal any event or fault condition to the host processor. Whenever a fault or event

occurs in the device, the corresponding interrupt bit is set in the INT register, and the open-drain output is pulled

low. The nINT pin is released (Hi-Z) and the fault bits are cleared when the INT register is read by the host.

However, if a failure continues, the corresponding INT bit stays set and the nINT pin is pulled low again after a

maximum of 32 µs.

Interrupt events include pushing or releasing the push-button and a change in the USB or AC voltage status.

The mask bits in the INT register are used to mask events from generating interrupts. The mask settings affect

the nINT pin only and have no impact on the protection and monitor circuits themselves.

NOTE

Continuous event conditions such as an ISINK-enabled shutdown can cause the nINT pin

to be pulled low for an extended period of time, which can keep the host in a loop trying to

resolve the interrupt. If this behavior is not desired, set the corresponding mask bit after

receiving the interrupt and poll the INT register to determine when the event condition

resolves and the corresponding interrupt bit is cleared. Then the interrupt that caused the

nINT pin to stay low can be un-masked.

7.3.8 Analog Multiplexer

The TPS652170 device has an analog multiplexer (mux) that provides access to critical system voltages. The

voltages that can be measured by an ADC at the MUX_OUT pin are as follows:

•

Battery voltage (VBAT)

System voltage (VSYS)

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Feature Description (continued)

•

Temperature-sense voltage (VTS), and

VICHARGE, a voltage proportional to the charging current, and

MUX_IN, an external input pin to monitor an additional system voltage

In addition, one external input is available. The VBAT and VSYS voltages are divided by three (for example,

MUX_OUT = VBAT / 3) to be compatible with the input-voltage range of the ADC that resides on the system-host

side. The output of the MUX is buffered and can drive a maximum of 1-mA load current.

MUX_IN

VICH (Voltage proportional to charge current )

VTS (Thermistor voltage )

101

-

MUX_OUT

010

001

100

VSYS (System voltage)

HiZ

011

+

001/ 010

000

VBAT (Battery sense voltage )

2R

1R

MUX[2:0]

Figure 10. Analog Multiplexer

7.3.9 Battery Charger and Power Path

The TPS652170 device has a linear charger for Li+ batteries and a triple system-power path targeted at space-

limited portable applications. The power path lets simultaneous and independent charging of the battery and

powering of the system. This feature enables the system to run with a defective or absent battery pack and lets

instant system turnon even with a totally discharged battery. The input power source for charging the battery and

running the system can be either an AC adapter or a USB port. The power path prioritizes the AC input over the

USB input, and both over the battery input, to decrease the number of charge and discharge cycles on the

battery. Charging current is automatically decreased when the system load increases to the point where the AC

or USB power supply reach the maximum allowable current. If the AC or USB power supply cannot provide

enough current to the system, the battery supplies the additional current required and the battery will discharge

until the system load is reduced. Figure 11 shows a block diagram of the power path. Figure 12 shows an

example of the power path management function.

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Feature Description (continued)

BATDET

VBAT

1

AC detect

0

4.1V

AC

VSYS

ACSINK

AC_SINK

AC_EN

IAC[1:0]

SWITCH CONTROL

VBAT

USB detect

USB

USBSINK

USB_SINK

USB_EN

IUSB[1:0]

SWITCH CONTROL

BACKGATE

CONTROL

ISC

enable

BAT

ACTIVE

BATTEMP

TSUSP

DPPM

TREG

TERMI

CHG_EN

SUSP

RESET

BAT_SENSE

TS

CHRGER

CONTROL

TMR_EN

TIMER[1:0]

DYN_TIMER

PCHRT

TIMER

BATDET

1.5V

PCHGTOUT

CHGTOUT

Figure 11. Block Diagram of the Power Path and Battery Charger

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Feature Description (continued)

System load

1000mA

ISYS

700mA

500mA

300mA

Time

Charge current setting

IBAT

IAC

Time

1300mA current limit

1300mA

1200mA

Time

In this example, the AC input current limit is set to 1300 mA, battery charge current is 500 mA, and system load is

700 mA. As the system load increases to 1000 mA, the battery charging current is decreased to 300 mA to keep the

AC input current of 1300 mA.

Figure 12. Power Path Management

The detection thresholds for AC and USB inputs are a function of the battery voltage, and three basic use cases

must be considered: shorted or absent battery, dead battery, and good battery.

7.3.9.1 Shorted or Absent Battery (V_BAT< 1.5 V)

The AC or USB inputs are valid and the device powers up if the AC or USB input voltage increases above 4.3 V.

After powering up, the input voltage can decrease to a value of V_UVLO+ V_OFFSET(for example, 3.3 V + 200 mV)

before the device powers down.

The AC input is prioritized over the USB input; that is, if both inputs are valid, current is pulled from the AC input

and not the USB input. If both AC and USB supplies are available, the power-path switches to the USB input if

AC voltage decreases to less than 4.1 V (fixed threshold).

NOTE

The rise time of the AC and USB input voltage must be less than 50 ms for the detection

circuits to operate correctly. If the rise time is longer than 50 ms, the device may fail to

power up.

The linear charger periodically applies a 10-mA current source to the BAT pin to check for the presence of a

battery. This applied current causes the BAT pin to float up to more than 3 V, which may interfere with AC

removal detection and prevent switching from the AC to the USB input. For this reason, TI does not recommend

using both the AC and USB inputs when the battery is absent.

7.3.9.2 Dead Battery (1.5 V < V_BAT< V_UVLO

)

Functionality for this case is the same as for the shorted battery case. The only difference is that after the AC

input is selected as the input, the power-path does not switch back to the USB input as AC input voltage

decreases to less than 4.1 V.

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Feature Description (continued)

7.3.9.3 Good Battery (V_BAT> V_UVLO

)

The AC and USB supplies are detected when the input is 190 mV above the battery voltage, and are considered

absent when the voltage difference to the battery is less than 125 mV. This feature makes sure that the AC and

USB supplies are used whenever possible to save battery life. The USB and AC inputs are both current-limited

and controlled through the PPATH register.

In case AC or USB is not present or is blocked by the power path control logic (for example, in the OFF state),

the battery voltage always supplies the system (SYS pin).

7.3.9.4 AC and USB Input Discharge

The AC and USB inputs have 90-µA internal current sinks which are used to discharge the input pins to avoid

false detection of an input source. The AC sink is enabled when the USB input is a valid supply and the AC

voltage (V_AC) is less than the detection threshold. Likewise, the USB sink is enabled when the AC input is a valid

supply and the USB voltage (V_USB) is less than the detection limit. Both current sinks can be forced OFF by

setting the ACSINK and USBSINK bits to 11b. Both bits are located in the PPATH register (address 0x01).

NOTE

Setting the ACSINK or USBSINK bit to 01b and 10b is not recommended as these

settings may cause unexpected enabling and disabling of the current sinks.

7.3.10 Battery Charging

When the charger is enabled (the CH_EN bit is set to 1b), it first checks for a short circuit on the BAT pin by

sourcing a small current and monitoring the BAT voltage. If the voltage on the BAT pin increases to more than

the BAT pin short-circuit detection threshold (V_BAT(SC)), a battery is present and charging can start. The battery is

charged in three phases: precharge, constant-current fast charge (current regulation), and constant-voltage (CV)

charge (voltage regulation). In all charge phases, an internal control loop monitors the device junction

temperature and decreases the charge current if an internal temperature threshold is exceeded. Figure 13 shows

a typical charging profile. Figure 14 shows a modified charging profile.

PRE

CHARGE

CC FAST

CHARGE

CV

TAPER

DONE

V_OREG

[1:0]

ICHRG

Battery

Current

Battery

Voltage

V_LOWV

I_PRECHG

I_TERM

Termination

Figure 13. Charging Profiles—Typical Charge Current Profile With Termination Enabled

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Feature Description (continued)

PRE

CHARGE

CC FAST

CHARGE

CV

TAPER

DONE

V_OREG

[1:0]

ICHRG

Battery

Voltage

Battery

Current

V_LOWV

Thermal

Regulation

I_PRECHG

I_TERM

Termination

T_J(REG)

IC junction temperature T_J

Figure 14. Charging Profiles—Modified Charging Profile With Thermal Regulation Loop Active and

Termination Enabled

In the precharge phase, the battery is charged at the precharge current (I_PRECHG), which is typically 10% of the

fast-charge current rate. The battery voltage starts rising. After the battery voltage crosses the precharge-to-fast-

charge transition threshold (V_LOWV), the battery is charged at the fast charge current (I_CHG). The battery voltage

continues to rise. When the battery voltage reaches the battery charger voltage (V_OREG), the battery is held at a

constant value of V_OREG. The battery current now decreases as the battery approaches full charge. When the

battery current reaches the charge current for termination detection threshold (I_TERM), the TERMI bit in the

CHGCONFIG0 register is set to 1b. To avoid false termination when the charger goes to either the dynamic

power path management (DPPM) loop or thermal loop, termination is disabled when either loop is active.

The charge current cannot exceed the input current limit of the power path minus the load current on the SYS pin

because the power-path manager decreases the charge current to support the system load if the input current

limit is exceeded. Whenever the nominal charge current is decreased by action of the power-path manger, the

DPPM loop, or the thermal loop, the safety timer is clocked with half the nominal frequency to extend the

charging time by a factor of 2.

7.3.11 Precharge

The precharge current is preset to a factor of 10% of the fast-charge current (ICHRG[1:0]) and cannot be

changed by the user.

7.3.12 Charge Termination

When the charging current decreases to less than the termination current threshold, the charger is turned off.

The value of the termination current threshold can be set in the CHGCONFIG3 register using the TERMIF[1:0]

bits. The termination current has a default setting of 7.5% of the ICHRG[1:0] setting.

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Feature Description (continued)

Charge termination is enabled by default and can be disabled by setting the TERM bit of the CHGCONFIG1

register to 1b. When termination is disabled, the device goes through the precharge, fast-charge, and CV

phases, then stays in the CV phase. The charger behaves like an LDO regulator with an output voltage equal to

the battery charger voltage (V_OREG) and can source current up to the fast charge current (I_CHG) or maximum input

current (I_IN-MAX), whichever is less. Battery detection is not performed.

NOTE

The termination current threshold is not a tightly controlled parameter. Using the lowest

setting (2.5% of the nominal charge current) is not recommended because the minimum

termination current can be very close to 0. Any leakage on the battery side may cause the

termination not to trigger and charging to time out eventually.

7.3.13 Battery Detection and Recharge

Whenever the battery voltage decreases to less than the recharge detection threshold (V_RCH), the sink current for

battery detection (I_BAT(DET)) is pulled from the battery for the battery detection time (t_DET) to determine if the

battery was removed. The voltage on the BAT pin staying above V_LOWVvoltage indicates that the battery is still

connected. If the charger is enabled (the CH_EN bit set to 1b), a new battery charging cycle starts.

When the BAT pin voltage is decreasing and less than the V_LOWVvoltage in the battery detection test, this

indicates that the battery was removed. The device then checks for battery insertion by turning on the charging

path and sources the I_PRECHGcurrent out of the BAT pin for the t_DETtime. Failure of the voltage to increase to

greater than the V_RCHvoltage indicates that a battery has been inserted, and a new charge cycle can start. If,

however, the voltage is already greater than the V_RCHvoltage, a fully charged battery was possibly inserted. To

check for this case, the I_BAT(DET)current is pulled from the battery for the t_DETtime and if the voltage falls below

the V_LOWVvoltage, no battery is present. The battery detection cycle continues until the device detects a battery

or the charger is disabled.

When the battery is removed from the system, the charger also flags a BATTEMP error which indicates that the

TS input is not connected to a thermistor.

7.3.14 Safety Timer

The TPS652170 device hosts an internal safety timer for the precharge and fast-charge phases to help prevent

potential damage to either the battery or the system. The default fast-charge time can be changed in the

CHGCONFIG1 register and the precharge time can be changed in the CHGCONFIG3 register. The timer

functions can be disabled by resetting the TMR_EN bit of the CHGCONFIG1 register to 0b. Both timers are

disabled when the charge termination is disabled (the TERM bit is cleared to 0b).

7.3.14.1 Dynamic Timer Function

Under some circumstances, the charger current is decreased to ensure support when changes in the system

load or junction temperature occur. Two events can decrease the charging current. The first event is an increase

in the system load current, which causes the DPPM loop to decrease the available charging current. The second

event is when the junction temperature exceeds the temperature regulation limit (T_J(REG)), which causes the

device to go to thermal regulation.

In each of these events, the timer is clocked with half-frequency to extend the charger time by a factor of 2, and

charger termination is disabled. Normal operation starts again after the device junction temperature decreases to

less than (T_J(REG)) and the system load decreases to a level where enough current is available to charge the

battery at the desired charge rate. This feature is enabled by default and can be disabled by resetting the

DYNTMR bit in the CHGCONFIG2 register to 0b. Figure 14 shows a modified charge cycle with the thermal loop

active.

7.3.14.2 Timer Fault

A timer fault occurs if the battery voltage does not exceed the V_LOWVvoltage in the t_PRECHGtime during

precharging. A timer fault also occurs if the battery current does not reach the I_TERMcurrent in fast charge before

the safety timer expires. Fast-charge time is measured from the start of the fast-charge cycle.

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Feature Description (continued)

The fault status is indicated by the CHTOUT and PCHTOUT bits in the CHGCONFIG0 register. Time-out faults

are cleared and a new charge cycle is started when either the USB or AC supply is connected (rising edge of

V_USBor V_AC), the charger RESET bit is set to 1b in the CHGCONFIG1 register, or the battery voltage decreases

to less than the recharge threshold (V_RCH).

CH_EN = 0

OFF

ANY STATE

CH_EN = 0 ||

BATTEMP = 1

CH_EN = 0 &

BATTEMP = 0

BATTERY

SHORTED?

YES

NO

No FAULT

RESTART

Timer frozen

Charging off

SUSPEND

PRECHARGE

TIMEOUT

TEMP FAULT

V > V_LOWV

TERM = 0

No FAULT

RESTART

Timer frozen

Charging off

SUSPEND

FAST CHARGE

TIMEOUT

TEMP FAULT

TERM = 1 &

TERMI = 1

WAIT FOR

RECHARGE

TERM = 0 ||

Battery removed

V_BAT< V_RCH&

Battery present

(1) TEMP FAULT = Battery HOT || Battery cold || Thermal shutdown

(2) RESTART = V_USB(↑) || V_AC(↑) || Charger RESET bit (↑) || V_BAT< V_RCH

Figure 15. State Diagram of Battery Charger

7.3.15 Battery-Pack Temperature Monitoring

The TS pin of the TPS652170 device connects to the NTC resistor in the battery pack. During charging, if the

NTC resistance indicates that battery operation is less than or greater than the limits of normal operation,

charging is suspended and the safety timer value is paused and held at the present value. When the battery

pack temperature returns to within the limits of normal operation, charging resumes and the safety time is started

again without resetting.

By default, the device supports a 10-kΩ NTC resistor with a B-value of 3480. The NTC resistor is biased through

a 7.35-kΩ internal resistor connected to the BYPASS rail (2.25 V) and requires an external 75-kΩ resistor parallel

to the NTC resistor to linearize the temperature response curve.

The TPS652170 device supports two different temperature ranges for charging: 0°C to 45°C and 0°C to 60°C.

The temperature range is selected through the TRANGE bit in the CHCONFIG3 register.

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Feature Description (continued)

NOTE

The device can be configured to support a 100-kΩ NTC resistor (with a B-value of 3960)

by setting the NTC_TYPE bit to 1b in the CHGCONFIG1 register. However, TI does not

recommended this real-time manual configuration. In the SLEEP state, the charger

continues charging the battery, but all register values are reset to default values, in which

case the charger gets the wrong temperature information. If 100-kΩ NTC resistor support

is required, custom programming during production at the TI factory is required.

TRANGE = 0

TRANGE = 1

ICHRG[1:0]

300 mA, 400 mA, 500 mA, 700 mA

0

Temperature [C]

0°C

45°C

0°C

60°C

Figure 16. Charge Current as a Function of Battery Temperature

BYPASS

2.25 V

BIAS

10 µF

7.35 kW

62.5 kW

1

0

NTC_TYPE

TS

VOPEN

VLTF

1.8 V

10-kW NTC

75 kW

NTC logic

1.66 V (0°C)

TRANGE

0

1

0.86 V (45°C)

0.622 V (60°C)

VHTF

Figure 17. NTC Bias Circuit

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Feature Description (continued)

7.3.16 DC/DC Converters

7.3.16.1 Operation

The TPS652170 step-down converters typically operate with 2.25-MHz fixed-frequency pulse-width modulation

(PWM) at moderate-to-heavy load currents. At light load currents, the converter automatically goes to power-

save mode and operates in pulse-frequency modulation (PFM).

During PWM operation, the converter uses a unique fast-response voltage-mode controller scheme with input-

voltage feed-forward to achieve good line and load regulation. This controller scheme allows the use of small

ceramic input and output capacitors. At the start of each clock cycle, the high-side MOSFET is turned on. The

current flows from the input capacitor through the high-side MOSFET through the inductor to the output capacitor

and load. During this phase, the current ramps up until the PWM comparator trips and the control logic turns off

the switch. The current-limit comparator also turns off the switch in case the current limit of the high-side

MOSFET switch is exceeded. After a dead time to prevent shoot-through current, the low-side MOSFET rectifier

is turned on and the inductor current ramps down. The direction of current flow is now from the inductor to the

output capacitor and to the load. The current returns back to the inductor through the low-side MOSFET rectifier.

The next cycle turns off the low-side MOSFET rectifier and turns on the on the high-side MOSFET.

The DC/DC converters operate in synchronization with each other, with converter 1 as the master. A 120° phase

shift between DCDC1 and DCDC2 and between DCDC2 and DCDC3 decreases the combined input root mean

square (RMS) current at the VIN_DCDCx pins. Therefore, smaller input capacitors can be used.

7.3.16.2 Output Voltage Setting

The setpoint of the output voltage for the DC/DC converters is determined in one of two different ways. The first

way is as a fixed-voltage converter where the voltage is defined in the DEFDCDCx register. The second way is

an external resistor network. Set the XADJx bit in the DEFDCDCx register and use Equation 1 to calculate the

output voltage.

æ

ö

÷

ø

R₁

R₂

V_OUT= V_REF´ 1+

ç

è

where

•

V_REFis the feedback voltage of 0.6 V

(1)

TI recommends selecting values to keep the combined resistance of the R1 and R2 resistors less than 1 MΩ.

Shield the VDCDC1, VDCDC2, and VDCDC3 lines from switching nodes and from the L1, L2, and L3 inductors

to prevent coupling of noise into the feedback pins.

L3

to system

VDCDC3

10 μF

DCDC1, DCDC2, and DCDC3 offer two

methods to adjust the output voltage.

DCDC1, DCDC2, and DCDC3 offer two

methods to adjust the output voltage.

Figure 18. Example for DCDC3—Fixed-Voltage

Options Programmable Through I²C (XADJ3 = 0b,

default)

Figure 19. Example for DCDC3—Voltage is Set by

External Feedback Resistor Network (XADJ3 = 1b)

7.3.16.3 Power-Save Mode and Pulse-Frequency Modulation (PFM)

By default, all three DC/DC converters go to pulse-frequency modulation (PFM) mode at light loads, and fixed-

frequency pulse-width modulation (PWM) mode at heavy loads. In some applications, forcing PWM operation

even at light loads is required, which is done by setting the PFM_ENx bits in the DEFSLEW registers to 1b

(default setting is 0b). In PFM mode, the converter skips switching cycles and operates with decreased frequency

with a minimum quiescent current to keep high efficiency. The converter positions the output voltage typically 1%

above the nominal output voltage. This voltage-positioning feature minimizes the voltage drop caused by a

sudden load step.

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The converters go from PWM to PFM mode after the inductor current in the low-side MOSFET switch becomes

0 A.

When the converters are in power-save mode, the output voltage is monitored with a PFM comparator. As the

output voltage decreases to less than the PFM comparator threshold of V_OUT+ 1%, the device starts a PFM

current pulse. Starting the pulse is done by turning on the high-side MOSFET and ramping up the inductor

current. Then the high-side MOSFET turns off and the low-side MOSFET switch turns on until the inductor

current becomes 0 A again.

The converter effectively delivers a current to the output capacitor and the load. If the load is less than the

delivered current, the output voltage rises. If the output voltage is equal to or greater than the PFM comparator

threshold, the device stops switching and goes to a sleep mode with a typical 15-µA current consumption. In

case the output voltage is still less than the PFM comparator threshold, additional PFM current pulses are

generated until the PFM comparator threshold is reached. The converter starts switching again after the output

voltage decreases to less than the PFM comparator threshold.

With one threshold comparator, the output-voltage ripple during PFM mode operation can be kept very small.

The ripple voltage depends on the PFM comparator delay, the size of the output capacitor, and the inductor

value. Increasing the value of the output capacitors, inductors, or both keeps the output ripple at a minimum.

The converter goes from PFM mode and goes to PWM mode the output current can no longer be supported in

PFM mode or if the output voltage decreases to less than a second threshold, called the PFM comparator-low

threshold. This PFM comparator-low threshold is set to a value of V_OUT– 1% and enables a fast transition from

power-save mode to PWM mode during a load step.

The power-save mode can be disabled through the I²C interface for each of the step-down converters,

independently of each other. If the power-save mode is disabled, the converter then operates in fixed-PWM

mode.

7.3.16.4 Dynamic Voltage Positioning

This feature decreases the voltage undershoots and overshoots at load steps from light to heavy load and from

heavy to light load. This feature is active in power-save mode and provides more headroom for both the voltage

drop at a load step and the voltage increase at a load removal. This improves load-transient behavior. At light

loads in which the converter operates in PFM mode, the output voltage is regulated typically 1% greater than the

nominal value (V_OUT). In case of a load transient from light load to heavy load, the output voltage drops until it

reaches the low threshold of the PFM comparator set to –1% less than the nominal value, and goes to PWM

mode. During a load removal from heavy load to light load, the voltage overshoot is low because of active

regulation turning on the low-side MOSFET.

Output Voltage

Voltage Positioning

V_OUT+ 1%

PFM Comp

V_OUT(PWM)

V_OUT– 1%

PFM Comp Low

Load Current

PWM MODE

PFM Mode

Figure 20. Dynamic Voltage Positioning in Power Save Mode

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7.3.16.5 100% Duty-Cycle Low-Dropout Operation

The converter starts to go to the 100% duty-cycle mode after the input voltage (V_IN) comes close to the nominal

output voltage. To keep the output voltage steady, the high-side MOSFET is turned on 100% for one or more

cycles. As the V_INvoltage decreases further, the high-side MOSFET is turned on completely. In this case, the

converter offers a low input-to-output voltage difference which is particularly useful in battery-powered

applications to achieve longest operation time by taking full advantage of the whole battery voltage range.

Use Equation 2 to calculate the minimum input voltage to keep regulation (V_IN,MIN) which depends on the load

current and output voltage.

V_IN,MIN= V_OUT,MAX+ I_OUT,MAX´ R_DSON,MAX+ R_L

(

)

where

•

V_OUT,MAXis the nominal output voltage plus the maximum output voltage tolerance.

I_OUT,MAXthe maximum output current plus the inductor ripple current.

R_DSON,MAXis the maximum upper MOSFET switch R_DSONresistance.

R_Lis the DC resistance of the inductor.

(2)

7.3.16.6 Short-Circuit Protection

High-side and low-side MOSFET switches are short-circuit protected. After the high-side MOSFET switch

reaches its current limit, it is turned off and the low-side MOSFET switch is turned on. The high-side MOSFET

switch can only turn on again after the current in the low-side MOSFET switch decreases to less than its current

limit.

7.3.16.7 Soft Start

The three step-down converters in the TPS652170 device have an internal soft-start circuit that controls the

ramp-up of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within 750 µs.

This ramp up limits the inrush current in the converter during start-up and prevents possible input voltage drops

when a battery or high-impedance power source is used. The soft-start circuit is enabled after the start-up time,

t_Start, expires.

EN

95%

5%

V_OUT

t

RAMP

Start

Figure 21. Output of the DC/DC Converters is Ramped Up Within 750 µs

7.3.17 Standby LDO Regulators (LDO1, LDO2)

The LDO1 and LDO2 regulators support up to 100 mA each, are internally current limited, and have a maximum

dropout voltage of 200 mV at the rated output current. In SLEEP mode, however, the output current is limited to

1 mA each. When disabled, both outputs are discharged to ground through a 430-Ω resistor.

The LDO1 regulator supports an output voltage range from 1 V to 1.8 V, which is controlled through the

DEFLDO1 register. The LDO2 regulator supports an output voltage range from 0.9 V to 1.5 V, and is controlled

through the DEFLDO2 register. By default, the LDO1 regulator is enabled immediately after a power-up event as

described in the PMIC States section and stays on in the SLEEP state to support system standby. Each LDO

regulator has low standby current of less than 15 µA (typical).

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The LDO2 regulator can be configured to track the output voltage of the DCDC3 converter (core voltage). When

the TRACK bit is set to 1b in the DEFLDO2 register, the output is determined by the DCDC3[5:0] bits of the

DEFDCDC3 register and the LDO2[5:0] bits of the DEFLDO2 register are ignored.

The LDO1 and LDO2 regulators can be controlled through STROBE 1 through 6, special STROBES 14 and 15,

or through the corresponding enable bits in the ENABLE register. By default, the LDO1 regulator is controlled by

STROBE 15, which keeps LDO1 on in the SLEEP state. The STROBE assignments can be changed by the user

while the device is in the ACTIVE state, but all register settings are reset to the default values when the device

goes to the SLEEP or OFF state. TI does not recommend real-time modification of the STROBE assignments of

the LDO1 or LDO2 regulator. For permanent changes to the default STROBE assignments, custom programming

during production at the TI factory is required.

7.3.18 Load Switches or LDO Regulators (LS1 or LDO3, LS2 or LDO4)

The TPS65217x device has two general-purpose load switches that can also be configured as LDOs. As LDOs,

they support up to 200 mA or 400 mA each, are internally current-limited, and have a maximum dropout voltage

of 200 mV at rated output current. The on-off state of the load switches (LS1 and LS2) or the LDO regulators

(LDO3 and LDO4) is controlled either through the sequencer or the LS1_EN and LS2_EN bits of the ENABLE

register. When disabled, both outputs are discharged to ground through a 375-Ω resistor.

Configured as load switches, LS1 and LS2 have a maximum impedance of 650 mΩ. Different from LDO

operation, load switches can stay in current limit indefinitely without affecting the internal power-good signal or

affecting the other rails.

NOTE

Excessive power dissipation in the switches may cause thermal shutdown of the device.

Load switch and LDO modes are controlled by the LS1LDO3 and LS2LDO4 bits of the DEFLS1 and DEFLS2

registers.

7.3.19 White LED Driver

The TPS652170 device has a boost converter and two current sinks capable of driving two strings containing up

to 10 LEDs in each string (also known as a 2 × 10 matrix) LEDs at 25 mA or one string of up to 10 LEDs at 50

mA of current. Use Equation 3 to calculate the current of each current sink.

1.24 V

I_LED= 1048´

R_SET

(3)

Two different current levels can be programmed using two external R_SETresistors. Only one current setting is

active at any given time, and both current sinks are always regulated to the same current. The active current

setting is selected through the ISEL bit of the WLEDCTRL1 register.

An internal PWM signal and I²C control support brightness and dimming. Both current sources are controlled

together and cannot operate independently. By default, the PWM frequency is set to 200 Hz, but can be changed

to 100 Hz, 500 Hz, or 1000 Hz. The PWM duty cycle can be adjusted from 1% (default) to 100% in 1% steps

through the WLEDCTRL2 register.

When the ISINK_EN bit of WLEDCTRL1 register is set to 1b, both current sinks are enabled, and the boost

output voltage at the FB_WLED pin is regulated to support the same sink current through each current sink. The

boost output voltage, however, is internally limited to 39 V.

If only one WLED string is required, short the ISINK1 and ISINK2 pins together and connect them to the cathode

of the diode string. In this case, the LED current two times the sink current. Figure 22 shows the basic schematic

and internal circuitry of the WLED driver used to drive two strings. Figure 23 shows the basic schematic and

internal circuitry of the WLED driver used to one string. 表 33 and 表 34 list the recommended inductors and

output capacitors for the WLED boost converters.

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L4

SYS

FB_WLED

BOOST

CONTROL

4.7mF

ISINK1

ISINK2

PWM

generator

DUTY[6:0]

FDIM[1:0]

ISEL

R1

R2

Figure 22. Block Diagram of WLED Driver—Dual-String Operation

L4

SYS

FB_WLED

4.7 μF

BOOST

CONTROL

ISINK1

ISINK2

PWM

generator

DUTY[6:0]

FDIM[1:0]

ISEL

2xR1

2xR2

This operation has the same LED current as dual-string operation. For single-string operation, both ISINK pins are

shorted together and the RSET resistor values (R1 and R2) are doubled to halve the current that each ISINKx pin

pulls, resulting in the same current through the LEDs as in dual-string operation.

Figure 23. Block Diagram of WLED Driver—Single-String Operation

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7.4 Device Functional Modes

POWER

DOWN

DCDCx = OFF

WLED = OFF

BAT | USB | AC

LDOx

I2C

= OFF

= NO

PPATH = OFF⁽³⁾

CHRGR = OFF

OFF

PB_IN = 0 for > 8 s

| nRESET = 0

default

Registers‰

PGOOD = low

LDO_PGOOD = low

DCDCx = OFF

WLED = OFF

PB_IN = 0 | USB = 1 | AC = 1

LDOx

= OFF

PPATH = OFF⁽³⁾

CHRGR = OFF

Noise

AC = 0 &

USB = 0 &

PB_IN = 1

WAIT

DEGLITCH

WAIT MIN

OFF TIME1

(1 s)

I2C

= NO

PGOOD = low

LDO_PGOOD = low

55 ms done

PB_IN (;) | USB (9) | AC (9)

nRESET = 0

1 s done

PRE

OFF

POR

RESET

Registers‰ default

EEPROM

load done

CHECK

FAULTS

DCDCx= OFF

WLED = OFF

WAIT MIN

OFF TIME3

(1 s)

LDOx = OFF

PPATH= OFF⁽³⁾

CHARGER= OFF

Low power LDO

mode disabled

DCDCx = OFF

WLED = OFF

LDO1

LDO2,3,4 = OFF

I2C = YES

PPATH = ON

CHRGR = ON⁽¹⁾

PGOOD = low

10 ms done

= ON⁽⁴⁾

5-s timeout

WAIT

10 ms

PWR_EN

PB_IN = 0 (;) |

USB = 1 (9) | AC = 1 (9) |

PWR_EN = 1 | SEQUP(bit) = 1

PWR_EN = 1

DCDCx

WLED

LDO1

LDO2,3,4

I2C

PPATH

CHRGR

PGOOD

=

OFF⁽²⁾

OFF

UVLO | OTS

| PGOOD = 0

ON⁽⁴⁾

OFF⁽²⁾

NO

SLEEP

MIN ON TIME

(5 s)

ON⁽¹⁾

= low

10 ms done

WAIT

Registers‰ default

5 s done

DCDCx = ON

WLED = ON

LDOx

I2C

= ON

= YES

ACTIVE

PWR_EN = 0

10 ms

PPATH = ON

CHRGR = ON⁽¹⁾

Low power LDO

mode enabled

YES

OFF(bit) = 1?

NO

1 s done

DCDCx = OFF⁽²⁾

WLED = OFF

LDO1

= ON⁽⁴⁾

WAIT MIN

OFF TIME2

(1 s)

LDO2,3,4 = OFF⁽²⁾

I2C

= NO

PPATH = ON⁽¹⁾

CHRGR = ON⁽¹⁾

PGOOD = low

(1) Only if USB or AC supply is present

(2) Rails are powered-down as controlled by the sequencer in default EEPROM settings

(3) Battery voltage always supplies the system (from BAT pin to SYS pin)

(4) LDO1 is assigned to STROBE15 in default EEPROM settings and this special strobe is not controlled by the

sequencer. LDO1 can only source 1 mA in the SLEEP state

(5) The 9-MHz oscillator is enabled only when WLED or DCDC or PPATH or CHARGER is enabled.

(6) The charger, auto-discharge, PPATH, and 9-MHz oscillator are ON in the SLEEP state if AC or USB is present and

the charger is enabled and not fully charged.

(7) Any USB = 1(↑) or AC = 1 (↑) event in the WAIT MIN OFF TIME2 state makes the device go from the SLEEP state

when the timer expires. Any USB = 1(↑) or AC = 1 (↑) event in the WAIT MIN OFF TIME3 state makes the device go

from the PRE-OFF state when the timer expires.

(8) All user registers are reset to default values each time the device goes to the SLEEP state.

(9) UVLO and OTS are monitored in all the states except the OFF, POR, and WAIT DEGLITCH states.

Figure 24. Global State Diagram

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Device Functional Modes (continued)

7.4.1 PMIC States

7.4.1.1 OFF State

In the OFF state, the PMIC is completely shut down with the exception of a few circuits to monitor the voltage on

the AC, USB, and PB_IN pins. All output power rails are turned off and the registers are reset to their default

values. The I²C communication interface is turned off. The lowest amount of power is used in this state. To exit

the OFF state, one of the following wake-up events must occur:

•

The PB_IN pin is pulled low.

The USB supply is connected (positive edge).

The AC adapter is connected (positive edge).

To go to the OFF state, set the OFF bit in the STATUS register to 1b, and then pull the PWR_EN pin low. In

normal operation, the device can only go to the OFF state from the ACTIVE state. Whenever a fault occurs

during operation, such as thermal shutdown, power-good fail, undervoltage lockout, or a PWR_EN pin timeout,

all power rails are shut down and the device goes to the OFF state. The device stays in the OFF state until the

fault is removed then a new power-up event occurs.

7.4.1.2 ACTIVE State

This state is the typical mode of operation when the system is up and running. All DC/DC converters, LDO

regulators, load switches, the WLED driver, and the battery charger are operational and can be controlled

through the I²C interface.

After a wake-up event, the PMIC enables all rails not controlled by the sequencer and pulls the nWAKEUP pin

low to signal the event to the host processor. The device goes to the ACTIVE state only if the host asserts the

PWR_EN pin within 5 s after the wake-up event. Otherwise, the device goes to the OFF state. In the ACTIVE

state, the sequencer is triggered to automatically enable the remaining power rails. The nWAKEUP pin returns to

the Hi-Z state after the PWR_EN pin has been asserted. Figure 3 shows a timing diagram. The device can also

go directly to the ACTIVE state from the SLEEP state by pulling the PWR_EN pin high. For more information,

see the description of the SLEEP State.

The PWR_EN pin must be pulled low for the device to go from ACTIVE state.

7.4.1.3 SLEEP State

The SLEEP state is a low-power mode of operation intended to support system standby. Typically, all power rails

are turned off with the exception of the LDO1 rail, and the registers are reset to their default values. The LDO1

rail stays operational but can support only a limited amount of current (1 mA typical).

To go to the SLEEP state, set the OFF bit in the STATUS register to 0b (default), and then pull the PWR_EN pin

low. All power rails controlled by the power-down sequencer are shut down, and after 1 s the device goes to the

SLEEP state. If the LDO1 rail was enabled in the ACTIVE state, the LDO1 rail stays enabled in the SLEEP sate.

All rails not controlled by the power-down sequencer also keep state. The battery charger stays active for as long

as either the USB or AC supply is connected to the device. All register values are reset when the device goes to

the SLEEP state, including charger parameters.

The device goes to the ACTIVE state after detecting a wake-up event as described in the previous sections. In

addition, the device goes from the SLEEP to the ACTIVE state when the PWR_EN pin is pulled high. The system

host can go between the ACTIVE and SLEEP states by control of the PWR_EN pin only. This feature bypasses

the requirement for a wake-up event from an external source to occur.

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Device Functional Modes (continued)

7.4.1.4 RESET State

The TPS652170 device can be reset by either pulling the nRESET pin low or by holding the PB_IN pin low for

more than 8 s. All rails are shut down by the sequencer and all register values are reset to their default values.

Rails not controlled by the sequencer are shut down after the power-down sequencer is complete. The device

stays in the this state for as long as the reset pin is held low, and the nRESET pin must be high for the device to

go from the RESET state. However, the device stays in the RESET state for a minimum of 1 s before going back

to the ACTIVE state. As detailed in the description of the ACTIVE State, the PWR_EN pin must be asserted

within 5 s of the nWAKEUP pin going low for the device to go to the ACTIVE state. The RESET function power-

cycles the device and only shuts down the output rails temporarily. Resetting the device does put the device in

the OFF state.

If the PB_IN pin is kept low for an extended amount of time, the device continues to cycle between the ACTIVE

and RESET states, and goes to the RESET state after each 8-s time period.

7.5 Programming

7.5.1 I²C Bus Operation

The TPS652170 device hosts a slave I²C interface that is compliant with I²C standard 3.0 and supports data

rates up to 400 kbit/s and auto-increments addressing.

Slave Address + R/nW

Reg Address

Data

R/nW

S

A6 A5 A4 A3 A2 A1 A0

A

S7 S6 S5 S4 S3 S2 S1 S0

A

D7 D6 D5 D4 D3 D2 D1 D0

A

P

S

Start Condition

Read / not Write

A

P

Acknowledge

A6 ... A0 Device Address

S7 ... S0 Sub-Address

D7 ... D0 Data

R/nW

Stop Condition

Figure 25. Subaddress in I²C Transmission

The I²C bus is a communications link between a controller and a series of slave terminals. The link is established

using a two-wire bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is

sourced from the controller in all cases, where the serial data line is bidirectional for data communication

between the controller and the slave terminals. Each device has an open-drain output to transmit data on the

serial data line. An external pullup resistor must be placed on the serial data line to pull the drain output high

during data transmission.

Data transmission is initiated with a start bit from the controller as shown in Figure 28. The start condition is

recognized when the SDA line goes from high to low during the high portion of the SCL signal. On reception of a

start bit, the device receives serial data on the SDA input and checks for valid address and control information. If

the appropriate group and address bits are set for the device, then the device issues an acknowledge (ACK)

pulse and prepares for the reception of subaddress data. Subaddress data is decoded and responded to

according to the Register Maps. Data transmission is completed by either the reception of a stop condition or the

reception of the data word sent to the device. A stop condition is recognized as a low-to-high transition of the

SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the

low portion of the SCL signal. An acknowledge is issued after the reception of a valid address, subaddress, and

data words. The I²C interface auto-sequences through the register addresses, so that multiple data words can be

sent for a given I²C transmission. For details, see Figure 26, Figure 27, and Figure 28.

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Programming (continued)

S

SLAVE ADDRESS

W A

REG ADDRESS

A

DATA_REGADDR

A

Ā

DATA _{SUBADDR +n}

n bytes + ACK

DATA _{SUBADDR +n+1}

P

From master to slave

From slave to master

R Read (high)

W Write (low)

S Start

P Stop

Ā

Not Acknowlege

A Acknowlege

Figure 26. I²C Data Protocol—Master Writes Data To Slave

S

SLAVE ADDRESS

W A

REG ADDRESS

A

S

SLAVE ADDRESS

R

A

DATA_REGADDR

A

DATA_{REGADDR +n}

n bytes + ACK

DATA_{REGADDR +n+1}

Ā P

From master to slave

From slave to master

R Read (high)

W Write (low)

S Start

P Stop

Ā

Not Acknowlege

A Acknowlege

Figure 27. I²C Data Protocol—Master Reads Data from Slave

SDA

SCL

1-7

8

9

1-7

8

9

1-7

8

9

S

P

START

ADDRESS R/W ACK

DATA

ACK

DATA

STOP

ACK/

nACK

Figure 28. I²C Start-Stop-Acknowledge Protocol

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Programming (continued)

7.5.2 Password Protection

Registers 0x0B through 0x1F, with the exception of the password register, are protected against accidental

writing by an 8-bit password. The password must be written before writing to a protected register and is

automatically reset to 0x00 after the following I²C transaction, regardless of the register that was accessed and

regardless of the transaction type (read or write). The password is required for write access only and is not

required for read access.

7.5.2.1 Level1 Protection

To write to a Level1 protected register, follow these steps:

1. Write the address of the destination register, XORed with the protection password (0x7D) to the

PASSWORD register.

2. Write data to the password-protected register.

3. Data is only transferred to the protected register if the content of the PASSWORD register XORed with the

address sent in Step 2 matches 0x7D. Otherwise, the transaction is ignored. The PASSWORD register is

reset to 0x00 after the transaction regardless of whether the XOR logical function matched 0x7D or not.

The cycle must be repeated for any other register that is Level1 write protected.

7.5.2.2 Level2 Protection

To write to a Level2 protected register, follow these steps:

1. Write the address of the destination register, XORed with the protection password (0x7D) to the

PASSWORD register.

2. Write data to the password-protected register.

3. The data is temporarily stored if the content of the PASSWORD register XORed with the address sent in

Step 2 matches 0x7D. The register value does not change at this point, but the PASSWORD register is reset

to 0x00 after the transaction regardless of whether the XOR logical function matched 0x7D or not.

4. Write the address of the destination register, XORed with the protection password (0x7D) to the

PASSWORD register.

5. Write the same data as in Step 2 to the password protected register.

6. The content of the PASSWORD register is XORed again with the address sent in Step 5 must match 0x7D

for the data to be valid.

7. The register is updated only if both data transfers in Step 2 and Step 5 were valid, and the transferred data

matched.

NOTE

No other I²C transaction can occur between Step 2 and Step 5, and the register is not

updated if any other transaction occurs between Step 2 and Step 5. The cycle must be

repeated for any other register that is Level2 write protected.

7.5.3 Resetting of Registers to Default Values

All registers are reset to default values when one or more of the following conditions occur:

•

The device goes from the ACTIVE state to the SLEEP state or OFF state.

The BAT or USB supply is applied from a power-less state (power-on reset).

The push-button input is pulled low for more than 8 s.

The nRESET pin is pulled low.

A fault occurs.

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7.6 Register Maps

7.6.1 Register Address Map

7.6.1.1 Programming Power-Up Default Values

Applying 8 V to the PWR_EN pin and writing 1b to bit 4 of register 0x2C commits the current register settings to

EEPROM memory so they become the new power-up default values. Any changes made to the EEPROM-

backed register settings will become permanent until bit 4 of register 0x2C is rest to 0b, which can be done

manually by I2C or by power-cycling the TPS652170 device. If programming is performed in-line during

production of the end equipment, PWR_EN must be returned to a voltage that meets the absolute maximum

ratings before powering on the full system. When 8 V is applied at the PWR_EN pin of the TPS652170 device for

programming, it will not damage the pin; however, the PWR_EN signal may contact pins of other ICs and the

absolute maximum ratings of any IC other than the TPS652170 should not be violated at any time.

NOTE

Only bits marked with (E2) in the register map have EEPROM programmable power-up

default settings. All other bits keep the factory settings listed in the register map. Changing

the default value of unlisted bits or bits marked as reserved is not advisable and should be

avoided during the programming procedure.

The EEPROM of a device can only be programmed up to 1000 times. The number of programming cycles should

never exceed this amount. Contact TI for changing production settings.

NOTE

All re-programmed EEPROM settings must be validated during prototyping phase to

ensure desired functionality because parts cannot be returned in case of incorrect

programming. Any issues should be reported to the e2e forum.

For more detailed instructions on how to program the TPS652170 device, refer to the BOOSTXL-TPS652170

User's Guide.

Figure 29 lists the memory-mapped registers for the device registers. All register offset addresses not listed in

should be considered as reserved locations and the register contents should not be modified.

Figure 29. Register Address Map

Address

(Decimal)

Address

(Hexadecimal)

Password

Protection Level

Default

Value

Name

Description

Section

0

1

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

CHIPID

PPATH

None

Level1

Level2

0x02

0x3D

0x00

0xB1

0x80

0xB2

0xB1

0x00

0x0C

0x18

0x08

Chip ID

Go

Power path control

2

INT

Interrupt flags and masks

Charger control register 0

Charger control register 1

Charger control register 2

Charger control register 3

WLED control register

3

CHGCONFIG0

CHGCONFIG1

CHGCONFIG2

CHGCONFIG3

WLEDCTRL1

WLEDCTRL2

MUXCTRL

STATUS

4

5

6

7

8

WLED PWM duty cycle

Analog multiplexer control register

Status register

9

10

11

12

13

14

15

16

PASSWORD

PGOOD

Write password

Power good (PG) flags

Power good (PG) delay

DCDC1 voltage adjustment

DCDC2 voltage adjustment

DCDC3 voltage adjustment

DEFPG

DEFDCDC1

DEFDCDC2

DEFDCDC3

Slew control for DCDC1, DCDC2, DCDC3, and

PFM mode enable

17

0x11

DEFSLEW

Level2

0x06

Go

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Address

(Decimal)

Address

(Hexadecimal)

Password

Protection Level

Default

Value

Name

Description

LDO1 voltage adjustment

Section

18

19

20

21

22

23

24

25

26

27

28

29

0x12

0x13

0x14

0x15

0x16

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

DEFLDO1

DEFLDO2

DEFLS1

DEFLS2

ENABLE

DEFUVLO

SEQ1

Level2

Level1

0x09

0x38

0x26

0x3F

0x00

0x20

0x00

Go

LDO2 voltage adjustment

LS1 or LDO3 voltage adjustment

LS2 or LDO4 voltage adjustment

Enable register

UVLO control register

Power-up STROBE definition

Power-up delay times

SEQ2

SEQ3

SEQ4

SEQ5

SEQ6

Power-up delay times

Bit access types are abbreviated to fit into small table cells. Table 1 shows the abbreviation codes that are used

for access types in this section.

Table 1. Access Type Codes

Access Type⁽¹⁾

Read

Code

R

Description

Read-only

Read/Write

R/W

Read and Write

(1) Reserved bits can be R or R/W. Read-only (R) Reserved bits are not used and writing data to these

bits will have no effect on device operation. Read and Write (R/W) Reserved bits are settings that

cannot be modified. The reset value must always be written to these bits. Modifying a R/W Reserved

bit will have an impact on device operation and can produce unwanted device behavior.

7.6.2 Chip ID Register (CHIPID) (Address = 0x00) [reset = 0x02]

CHIPID is shown in Figure 30 and described in Table 2.

Return to Summary Table.

Figure 30. CHIPID Register

7

6

5

4

3

2

1

0

CHIP[3:0]

R-0000b

REV[3:0]

R-0010b

Table 2. CHIPID Register Field Descriptions

Bit

Field

Type

Reset

Description

7–4

CHIP[3:0]

R

0000b

Chip ID

0000b = TPS652170

0001b = Future use

0110b = TPS65217D

0111b = TPS65217A

1000b = Future use

1001b to 1101b = Reserved

1110b = TPS65217C

1111b = TPS65217B

3–0

REV[3:0]

R

0010b

Revision code

0000b = revision 1.0

0001b = revision 1.1

0010b = revision 1.2

0011b to 1110b = Reserved

1111b = Future use

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7.6.3 Power Path Control Register (PPATH) (Address = 0x01) [reset = 0x3D]

PPATH is shown in Figure 31 and described in Table 3.

Return to Summary Table.

Figure 31. PPATH Register

7

6

5

4

3

2

1

0

ACSINK

R/W-0b

USBSINK

R/W-0b

AC_EN

R/W-1b

USB_EN

R/W-1b

IAC[1:0]

R/W-11b

IUSB[1:0]

R/W-01b

Table 3. PPATH Register Field Descriptions

Bit

Field

Type

R/W

Reset

0b

Description

7

ACSINK

AC current-sink control

NOTE: [ACSINK, USBSINK] = 01b and 10b combinations are

not recommended, as these may lead to unexpected enabling

and disabling of the current sinks.

0b = AC sink is enabled when USB is a valid supply and V_ACis

less than the detection threshold

1b = Set ACSINK and USBSINK to 1b at the same time to force

both (AC and USB) current sinks OFF

6

USBSINK

R/W

1b

USB current-sink control

NOTE: [ACSINK, USBSINK] = 01b and 10b combinations are

not recommended, as these may lead to unexpected enabling

and disabling of the current sinks.

0b = USB sink is enabled when AC is a valid supply and V_USBis

less than the detection threshold

1b = Set ACSINK and USBSINK to 1b at the same time to force

both (AC and USB) current sinks OFF

5

4

AC_EN

USB_EN

IAC[1:0]

R/W

1b

AC power path enable

0b = AC power input is turned off.

1b = AC power input is turned on.

USB power path enable

0b = USB power input is turned off (USB suspend mode).

1b = USB power input is turned on.

3–2

R/W,

E2⁽¹⁾

11b

01b

AC input-current limit

00b = 100 mA

01b = 500 mA

10b = 1300 mA

11b = 2500 mA

1–0

IUSB[1:0]

R/W,

E2⁽¹⁾

USB input-current limit

00b = 100 mA

01b = 500 mA

10b = 1300 mA

11b = 1800 mA

(1) The least-significant bit is not programmable.

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7.6.4 Interrupt Register (INT) (Address = 0x02) [reset = 0x80]

INT is shown in Figure 32 and described in Table 4.

Return to Summary Table.

Figure 32. INT Register

7

6

5

4

3

2

1

0

Reserved

R/W-0b

PBM

ACM

USBM

R/W-0b

Reserved

R/W-0b

PBI

ACI

USBI

R/W-0b

Table 4. INT Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

Reserved

0b

This bit is reserved

6

PBM

R/W

Push-button status change interrupt mask

0b = Interrupt is issued when PB status changes.

1b = No interrupt is issued when PB status changes.

5

4

ACM

0b

AC interrupt mask

0b = Interrupt is issued when power to the AC input is applied or

removed.

1b = No interrupt is issued when power to the AC input is

applied or removed.

USBM

R/W

USB power status change interrupt mask

0b = Interrupt is issued when power to USB input is applied or

removed.

1b = No interrupt is issued when power to USB input is applied

or removed.

3

2

Reserved

PBI

R

0b

This bit is reserved

Push-button status change interrupt

NOTE: Status information is available in the STATUS register.

0b = No change in status

1b = Push-button status change (PB_IN changed high to low or

low to high)

1

0

ACI

R

0b

AC power status change interrupt

NOTE: Status information is available in the STATUS register.

0b = No change in status

1b = AC power status change (power to the AC pin has either

been applied or removed)

USBI

USB power status change interrupt

NOTE: Status information is available in the STATUS register.

0b = No change in status

1b = USB power status change (power to the USB pin has either

been applied or removed)

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7.6.5 Charger Configuration Register 0 (CHGCONFIG0) (Address = 0x03) [reset = 0x00]

CHGCONFIG0 is shown in Figure 33 and described in Table 5.

Return to Summary Table.

Figure 33. CHGCONFIG0 Register

7

6

5

4

3

2

1

0

TREG

R-0b

DPPM

R-0b

TSUSP

R-0b

TERMI

R-0b

ACTIVE

R-0b

CHGTOUT

R-0b

PCHGTOUT

R-0b

BATTEMP

R-0b

Table 5. CHGCONFIG0 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

TREG

DPPM

TSUSP

TERMI

R

0b

Thermal regulation

0b = Charger is in normal operation.

1b Charge current is reduced because of high chip

=

temperature.

DPPM active

0b = DPPM loop is not active.

1b = DPPM loop is active; charge current is reduced to support

the load with the current required.

Thermal suspend

0b = Charging is allowed.

1b

= Charging is temporarily suspended because battery

temperature is out of range.

Termination current detect

0b = Charging, charge termination current threshold has not

been crossed.

1b = Charge termination current threshold has been crossed and

charging has been stopped. This can be from a battery reaching

full capacity or to a battery removal condition.

3

2

1

0

ACTIVE

R

0b

Charger active bit

0b = Charger is not charging.

1b = Charger is charging (DPPM or thermal regulation may be

active).

CHGTOUT

PCHGTOUT

BATTEMP

Charge timer time-out

0b = Charging, timers did not time out.

1b = One of the timers has timed out and charging has been

terminated.

Precharge timer time-out

0b = Charging, precharge timer did not time out.

1b = Precharge timer has timed out and charging has been

terminated.

Battery temperature and NTC error

NOTE: This bit does not indicate that the battery temperature is

within the valid range for charging.

0b = Battery temperature is in the allowed range for charging.

1b = No temperature sensor detected or battery temperature

outside valid charging range

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7.6.6 Charger Configuration Register 1 (CHGCONFIG1) (Address = 0x04) [reset = 0xB1]

CHGCONFIG1 is shown in Figure 34 and described in Table 6.

Return to Summary Table.

Figure 34. CHGCONFIG1 Register

7

6

5

4

3

2

1

0

TIMER[1:0]

R/W-10b

TMR_EN

R/W-1b

NTC_TYPE

R/W-1b

RESET

R/W-0b

TERM

R/W-0b

SUSP

R/W-0b

CHG_EN

R/W-1b

Table 6. CHGCONFIG1 Register Field Descriptions

Bit

Field

Type

R/W

Reset

10b

Description

7–6

TIMER[1:0]

Charge safety timer setting (fast-charge timer)

00b = 4h

01b = 5h

10b = 6h

11b = 8h

5

4

3

TMR_EN

NTC_TYPE

RESET

R/W

1b

Safety timer enable

0b = Precharge timer and fast charge timer are disabled.

1b = Precharge timer and fast charge time are enabled.

R/W, E2 1b

NTC type (for battery temperature measurement)

0b = 100k (curve 1, B = 3960)

1b = 10k (curve 2, B = 3480)

R/W

0b

Charger reset

0b = Inactive

1b = Reset active. This bit must be set and then reset via the

serial interface to restart the charge algorithm.

2

TERM

Charge termination on-off

0b

= Charge termination enabled, based on timers and

termination current

1b = Current-based charge termination does not occur and the

charger is always on

1

0

SUSP

R/W

0b

Suspend charge

0b = Safety timer and precharge timers are not suspended.

1b = Safety timer and precharge timers are suspended.

CHG_EN

R/W, E2 1b

Charger enable

0b = Charger is disabled.

1b = Charger is enabled.

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7.6.7 Charger Configuration Register 2 (CHGCONFIG2) (Address = 0x05) [reset = 0x80]

CHGCONFIG2 is shown in Figure 35 and described in Table 7.

Return to Summary Table.

Figure 35. CHGCONFIG2 Register

7

6

5

4

3

2

1

0

DYNTMR

R/W-1b

VPRECHG

R/W-0b

VOREG[1:0]

R/W-00b

Reserved

R/W-0000b

Table 7. CHGCONFIG2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

DYNTMR

R/W, E2 1b

Dynamic timer function

0b = Safety timers run with their nominal clock speed.

1b = Clock speed is divided by 2 if thermal loop or DPPM loop is

active.

6

VPRECHG

R/W, E2 0b

Precharge voltage

0b = Precharge to fast-charge transition voltage is 2.9 V.

1b = Precharge to fast-charge transition voltage is 2.5 V.

5–4

VOREG[1:0]

R/W, E2 00b

Charge voltage selection

00b = 4.1 V

01b = 4.15 V

10b = 4.2 V

11b = 4.2 V

3–0

Reserved

R/W

0000b

These bits are reserved

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7.6.8 Charger Configuration Register 3 (CHGCONFIG3) (Address = 0x06) [reset = 0xB2]

CHGCONFIG3 is shown in Figure 36 and described in Table 8.

Return to Summary Table.

Figure 36. CHGCONFIG3 Register

7

6

5

4

3

2

1

0

ICHRG[1:0]

R/W-10b

DPPMTH[1:0]

R/W-11b

PCHRGT

R/W-0b

TERMIF[1:0]

R/W-01b

TRANGE

R/W-0b

Table 8. CHGCONFIG3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–6

ICHRG[1:0]

R/W, E2 10b

Charge current setting

00b = 300 mA

01b = 400 mA

10b = 500 mA

11b = 700 mA

5–4

DPPMTH[1:0]

R/W, E2 11b

Power path DPPM threshold

00b = 3.5 V

01b = 3.75 V

10b = 4 V

11b = 4.25 V

3

PCHRGT

R/W, E2 0b

R/W, E2 01b

Precharge time

0b = 30 min

1b = 60 min

2–1

TERMIF[1:0]

Termination current factor

NOTE: Termination current = TERMIF x ICHRG

00b = 2.5%

01b = 7.5%

10b = 15%

11b = 18%

0

TRANGE

R/W, E2 0b

Temperature range for charging

0b = 0°C to 45°C

1b = 0°C to 60°C

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7.6.9 WLED Control Register 1 (WLEDCTRL1) (Address = 0x07) [reset = 0xB1]

WLEDCTRL1 is shown in Figure 37 and described in Table 9.

Return to Summary Table.

Figure 37. WLEDCTRL1 Register

7

6

5

4

3

2

1

0

Reserved

R-0000b

ISINK_EN

R/W-0b

ISEL

FDIM[1:0]

R/W-01b

R/W-0b

Table 9. WLEDCTRL1 Register Field Descriptions

Bit

7–4

3

Field

Type

Reset

0000b

Description

Reserved

ISINK_EN

R

These bits are reserved

Current sink enable

R/W

0b

NOTE: This bit enables both current sinks.

0b = Current sink is disabled (OFF).

1b = Current sink is enabled (ON).

2

ISEL

R/W

0b

ISET selection bit

0b = Low-level (define by ISET1 pin)

1b = High-level (defined by ISET2 pin)

1–0

FDIM[1:0]

01b

PWM dimming frequency

00b = 100 Hz

01b = 200 Hz

10b = 500 Hz

11b = 1000 Hz

7.6.10 WLED Control Register 2 (WLEDCTRL2) (Address = 0x08) [reset = 0x00]

WLEDCTRL2 is shown in Figure 38 and described in Table 10.

Return to Summary Table.

Figure 38. WLEDCTRL2 Register

7

6

5

4

3

2

1

0

Reserved

R-0b

DUTY[6:0]

R/W-0000000b

Table 10. WLEDCTRL2 Register Field Descriptions

Bit

7

Field

Type

Reset

0b

Description

Reserved

DUTY[6:0]

R

This bit is reserved

6–0

R/W

0000000b PWM dimming duty cycle

000 0000b = 1%

000 0001b = 2%

...

110 0010b = 99%

110 0011b = 100%

110 0100b = 0%

...

111 1110b = 0%

111 1111b = 0%

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7.6.11 MUX Control Register (MUXCTRL) (Address = 0x09) [reset = 0x00]

MUXCTRL is shown in Figure 39 and described in Table 11.

Return to Summary Table.

Figure 39. MUXCTRL Register

7

6

5

4

3

2

1

0

Reserved

R-00000b

MUX[2:0]

R/W-000b

Table 11. MUXCTRL Register Field Descriptions

Bit

7–3

2–0

Field

Type

Reset

00000b

000b

Description

Reserved

MUX[2:0]

R

These bits are reserved

R/W

Analog multiplexer selection

000b = MUX is disabled, output is Hi-Z.

001b = VBAT

010b = VSYS

011b = VTS

100b = VICHARGE

101b = MUX_IN (external input)

110b = MUX is disabled, output is Hi-Z.

111b = MUX is disabled, output is Hi-Z.

7.6.12 Status Register (STATUS) (Address = 0x0A) [reset = 0x00]

STATUS is shown in Figure 40 and described in Table 12.

Return to Summary Table.

Figure 40. STATUS Register

7

6

5

4

3

2

1

0

OFF

Reserved

R-000b

ACPWR

R-0b

USBPWR

R-0b

Reserved

R-0b

PB

R/W-0b

R-0b

Table 12. STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

OFF

R/W, E2 0b

OFF bit. Set this bit to 1b to enter the OFF state when PWR_EN

pin is pulled low. The bit is automatically reset to 0b.

6–4

3

Reserved

ACPWR

R

000b

These bits are reserved

0b

AC power status bit

0b = AC power is not present and/or not in the range valid for

charging.

1b = AC source is present and in the range valid for charging.

2

USBPWR

R

0b

USB power

0b = USB power is not present and/or not in the range valid for

charging.

1b = USB source is present and in the range valid for charging.

This bit is reserved

1

0

Reserved

PB

R

0b

Push Button status bit

0b = Push-button is inactive (PB_IN is pulled high).

1b = Push-button is active (PB_IN is pulled low).

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7.6.13 Password Register (PASSWORD) (Address = 0x0B) [reset = 0x00]

PASSWORD is shown in Figure 41 and described in Table 13.

Return to Summary Table.

Figure 41. PASSWORD Register

7

6

5

4

3

2

1

0

PWRD[7:0]

R/W-00000000b

Table 13. Password Register (PASSWORD) Field Descriptions

Bit

7–0

Field

Type

R/W

Reset

Description

PWRD[7:0]

00000000b

Password protection locking and unlocking

NOTE: Register is automatically reset to 0x00 after the following I²C

transaction. See the Password Protection section for details.

0000 0000b = Password-protected registers are locked for write access.

...

0111 1100b = Password-protected registers are locked for write access.

0111 1101b = Allows writing to a password-protected register in the next

write cycle

0111 1110b = Password-protected registers are locked for write access.

...

1111 1111b = Password-protected registers are locked for write access.

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7.6.14 Power Good Register (PGOOD) (Address = 0x0C) [reset = 0x00]

PGOOD is shown in Figure 42 and described in Table 14.

Return to Summary Table.

Figure 42. PGOOD Register

7

6

5

4

3

2

1

0

Reserved

R-0b

LDO3_PG

R-0b

LDO4_PG

R-0b

DC1_PG

R-0b

DC2_PG

R-0b

DC3_PG

R-0b

LDO1_PG

R-0b

LDO2_PG

R-0b

Table 14. PGOOD Register Field Descriptions

Bit

7

Field

Type

Reset

Description

Reserved

R

0b

This bit is reserved

LDO3 power-good

6

LDO3_PG

0b = LDO is either disabled or not in regulation.

1b = LDO is in regulation or LS1 or LDO3 is configured as a

switch.

5

LDO4_PG

R

0b

LDO4 power-good

0b = LDO is either disabled or not in regulation

1b = LDO is in regulation or LS2 or LDO4 is configured as a

switch.

4

3

2

1

0

DC1_PG

DC2_PG

DC3_PG

LDO1_PG

LDO2_PG

R

0b

DCDC1 power-good

0b = DCDC1 is either disabled or not in regulation.

1b = DCDC1 is in regulation.

DCDC2 power-good

0b = DCDC2 is either disabled or not in regulation.

1b = DCDC2 is in regulation.

DCDC3 power-good

0b = DCDC3 is either disabled or not in regulation.

1b = DCDC3 is in regulation.

LDO1 power-good.

0b = LDO is either disabled or not in regulation

1b = LDO is in regulation

LDO2 power-good

0b = LDO is either disabled or not in regulation

1b = LDO is in regulation

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7.6.15 Power-Good Control Register (DEFPG) (Address = 0x0D) [reset = 0x0C]

DEFPG is shown in Figure 43 and described in Table 15.

Return to Summary Table.

This register is password protected.

Figure 43. DEFPG Register

7

6

5

4

3

2

1

0

Reserved

R-0000b

LDO1PGM

R/W-1b

LDO2PGM

R/W-1b

PGDLY[1:0]

R/W-00b

Table 15. DEFPG Register Field Descriptions

Bit

7–4

3

Field

Type

Reset

0000b

Description

Reserved

R

These bits are reserved

LDO1PGM

R/W, E2 1b

LDO1 power-good masking bit

0b = PGOOD pin is pulled low if LDO1_PG is low

1b = LDO1_PG status does not affect the status of the PGOOD

output pin.

2

LDO2PGM

PGDLY[1:0]

R/W, E2 1b

LDO2 power-good masking bit

0b = PGOOD pin is pulled low if LDO2_PG is low

1b = LDO2_PG status does not affect the status of the PGOOD

output pin.

1–0

R/W, E2 00b

Power-good delay

NOTE: PGDLY applies to the PGOOD pin.

00b = 20 ms

01b = 100 ms

10b = 200 ms

11b = 400 ms

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7.6.16 DCDC1 Control Register (DEFDCDC1) (Address = 0x0E) [reset = 0x18]

DEFDCDC1 is shown in Figure 44 and described in Table 16.

Return to Summary Table.

This register is password protected.

Figure 44. DEFDCDC1 Register

7

6

5

4

3

2

1

0

XADJ1

R/W-0b

Reserved

R-0b

DCDC1[5:0]

R/W-011000b

Table 16. DEFDCDC1 Register Field Descriptions

Bit

Field

XADJ1

Type

Reset

Description

7

R/W,

E2

0b

DCDC1 voltage adjustment option

0b = Output voltage is adjusted through the register setting.

1b = Output voltage is externally adjusted.

This bit is reserved

6

Reserved

R

5–0

DCDC1[5:0] R/W,

E2⁽¹⁾

01 1000b

DCDC1 output-voltage setting

00 0000b = 0.9 V

01 0000b = 1.3 V

10 0000b = 1.9 V

11 0000b = 2.7 V

00 0001b = 0.925 01 0001b = 1.325 10 0001b = 1.95 V 11 0001b = 2.75 V

V

10 0010b = 2 V

11 0010b = 2.8 V

10 0011b = 2.05 V 11 0011b = 2.85 V

10 0100b = 2.1 V 11 0100b = 2.9 V

10 0101b = 2.15 V 11 0101b = 3 V

10 0110b = 2.2 V 11 0110b = 3.1 V

10 0111b = 2.25 V 11 0111b = 3.2 V

10 1000b = 2.3 V 11 1000b = 3.3 V

10 1001b = 2.35 V 11 1001b = 3.3 V

10 1010b = 2.4 V 11 1010b = 3.3 V

10 1011b = 2.45 V 11 1011b = 3.3 V

10 1100b = 2.5 V 11 1100b = 3.3 V

10 1101b = 2.55 V 11 1101b = 3.3 V

10 1110b = 2.6 V 11 1110b = 3.3 V

10 1111b = 2.65 V 11 1111b = 3.3 V

00 0010b = 0.95 V 01 0010b = 1.35 V

00 0011b = 0.975 01 0011b = 1.375

V

00 0100b = 1 V

01 0100b = 1.4 V

00 0101b = 1.025 01 0101b = 1.425

V

00 0110b = 1.05 V 01 0110b = 1.45 V

00 0111b = 1.075 01 0111b = 1.475

V

00 1000b = 1.1 V

01 1000b = 1.5 V

00 1001b = 1.125 01 1001b = 1.55 V

V

01 1010b = 1.6 V

00 1010b = 1.15 V

01 1011b = 1.65 V

00 1011b = 1.175

01 1100b = 1.7 V

V

01 1101b = 1.75 V

00 1100b = 1.2V

01 1110b = 1.80V

00 1101b = 1.225

01 1111b = 1.85 V

V

00 1110b = 1.25 V

00 1111b = 1.275

V

(1) The least-significant bit is not programmable.

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7.6.17 DCDC2 Control Register (DEFDCDC2) (Address = 0x0F) [reset = 0x08]

DEFDCDC2 is shown in Figure 45 and described in Table 17.

Return to Summary Table.

This register is password protected.

Figure 45. DEFDCDC2 Register

7

6

5

4

3

2

1

0

XADJ2

R/W-0b

Reserved

R-0b

DCDC2[5:0]

R/W-001000b

Table 17. DEFDCDC2 Register Field Descriptions

Bit

Field

XADJ2

Type

Reset

Description

7

R/W,

E2

0b

DCDC2 voltage adjustment option

0b = Output voltage is adjusted through the register setting.

1b = Output voltage is externally adjusted.

This bit is reserved

6

Reserved

R

5–0

DCDC2[5:0] R/W,

E2⁽¹⁾

00 1000b

DCDC2 output voltage setting

00 0000b = 0.9 V

01 0000b = 1.3 V

10 0000b = 1.9 V

11 0000b = 2.7 V

00 0001b = 0.925 01 0001b = 1.325 10 0001b = 1.95 V 11 0001b = 2.75 V

V

10 0010b = 2 V

11 0010b = 2.8 V

10 0011b = 2.05 V 11 0011b = 2.85 V

10 0100b = 2.1 V 11 0100b = 2.9 V

10 0101b = 2.15 V 11 0101b = 3 V

10 0110b = 2.2 V 11 0110b = 3.1 V

10 0111b = 2.25 V 11 0111b = 3.2 V

10 1000b = 2.3 V 11 1000b = 3.3 V

10 1001b = 2.35 V 11 1001b = 3.3 V

10 1010b = 2.4 V 11 1010b = 3.3 V

10 1011b = 2.45 V 11 1011b = 3.3 V

10 1100b = 2.5 V 11 1100b = 3.3 V

10 1101b = 2.55 V 11 1101b = 3.3 V

10 1110b = 2.6 V 11 1110b = 3.3 V

00 0010b = 0.950V 01 0010b = 1.35 V

00 0011b = 0.975 01 0011b = 1.375

V

00 0100b = 1 V

01 0100b = 1.4 V

00 0101b = 1.025 01 0101b = 1.425

V

00 0110b = 1.05 V 01 0110b = 1.45 V

00 0111b = 1.075 01 0111b = 1.475

V

00 1000b = 1.1 V

01 1000b = 1.5 V

00 1001b = 1.125 01 1001b = 1.55 V

V

01 1010b = 1.6 V

00 1010b = 1.15 V

01 1011b = 1.65 V

00 1011b = 1.175

01 1100b = 1.7 V

10 1111b = 2.65 V 11 1111b = 3.3 V

V

01 1101b = 1.75 V

00 1100b = 1.2 V

01 1110b = 1.8 V

00 1101b = 1.225

01 1111b = 1.85 V

V

00 1110b = 1.25 V

00 1111b = 1.275

V

(1) The least-significant bit is not programmable.

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7.6.18 DCDC3 Control Register (DEFDCDC3) (Address = 0x10) [reset = 0x08]

DEFDCDC3 is shown in Figure 46 and described in Table 18.

Return to Summary Table.

This register is password protected.

Figure 46. DEFDCDC3 Register

7

6

5

4

3

2

1

0

XADJ3

R/W-0b

Reserved

R-0b

DCDC3[5:0]

R/W-001000b

Table 18. DEFDCDC3 Register Field Descriptions

Bit

Field

XADJ3

Type

Reset

Description

7

R/W,

E2

0b

DCDC3 voltage adjustment option

0b = Output voltage is adjusted through register setting

1b = Output voltage is externally adjusted

This bit is reserved

6

Reserved

R

5–0

DCDC3[5:0] R/W,

E2⁽¹⁾

00 1000b

DCDC3 output voltage setting

00 0000b = 0.9 V

00 0001b = 0.925 V

00 0010b = 0.95 V

00 0011b = 0.975 V

00 0100b = 1 V

01 0000b = 1.3 V

01 0001b = 1.325 V

01 0010b = 1.35 V

01 0011b = 1.375 V

01 0100b = 1.4 V

01 0101b = 1.425 V

01 0110b = 1.45 V

01 0111b = 1.475 V

01 1000b = 1.5 V

01 1001b = 1.55 V

01 1010b = 1.6 V

01 1011b = 1.65 V

01 1100b = 1.7 V

01 1101b = 1.75 V

01 1110b = 1.8 V

01 1111b = 1.85 V

10 0000b = 1.9 V

11 0000b = 2.7 V

10 0001b = 1.95 V 11 0001b = 2.75 V

10 0010b = 2 V 11 0010b = 2.8 V

10 0011b = 2.05 V 11 0011b = 2.85 V

10 0100b = 2.1 V 11 0100b = 2.9 V

10 0101b = 2.15 V 11 0101b = 3 V

10 0110b = 2.2 V 11 0110b = 3.1 V

00 0101b = 1.025 V

00 0110b = 1.05 V

00 0111b = 1.075 V

00 1000b = 1.1 V

00 1001b = 1.125 V

00 1010b = 1.15 V

00 1011b = 1.175 V

00 1100b = 1.2 V

00 1101b = 1.225 V

00 1110b = 1.25 V

00 1111b = 1.275 V

10 0111b = 2.25 V 11 0111b = 3.2 V

10 1000b = 2.30 V 11 1000b = 3.3 V

10 1001b = 2.35 V 11 1001b = 3.3 V

10 1010b = 2.4 V

10 1011b = 2.45 V 11 1011b = 3.3 V

10 1100b = 2.5 V 11 1100b = 3.3 V

10 1101b = 2.55 V 11 1101b = 3.3 V

10 1110b = 2.6 V 11 1110b = 3.3 V

10 1111b = 2.65 V 11 1111b = 3.3 V

11 1010b = 3.3 V

(1) The most-significant and least-significant bits are not programmable.

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7.6.19 Slew-Rate Control Register (DEFSLEW) (Address = 0x11) [reset = 0x06]

DEFSLEW is shown in Figure 47 and described in Table 19.

Return to Summary Table.

Slew-rate control applies to all three DC/DC converters.

This register is password protected.

Figure 47. DEFSLEW Register

7

6

5

4

3

2

1

0

GO

GODSBL

R/W-0b

PFM_EN1

R/W-0b

PFM_EN2

R/W-0b

PFM_EN3

R/W-0b

SLEW[2:0]

R/W-110b

R/W-0b

Table 19. DEFSLEW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7

GO

0b

Go bit

NOTE: Bit is automatically reset at the end of the voltage

transition.

0b = No change

1b = Initiates the transition from the present state to the output

voltage setting currently stored in the DEFDCDCx register

6

5

GODSBL

PFM_EN1

PFM_EN2

PFM_EN3

SLEW[2:0]

R/W

0b

Go Disable bit

0b = Enabled

1b

= Disabled; DCDCx output voltage changes whenever

setpoint is updated in DEFDCDCx register without having to

write to the GO bit. SLEW[2:0] setting does apply.

PFM enable bit, DCDC1

0b = DC/DC converter operates in the PWM or PFM mode,

depending on load.

1b = DC/DC converter is forced into the fixed-frequency PWM

mode.

4

PFM enable bit, DCDC2

0b = DC/DC converter operates in the PWM or PFM mode,

depending on load.

1b = DC/DC converter is forced into the fixed-frequency PWM

mode.

3

PFM enable bit, DCDC3

0b = DC/DC converter operates in the PWM or PFM mode,

depending on load.

1b = DC/DC converter is forced into the fixed-frequency PWM

mode.

2–0

0110b

Output slew-rate setting

NOTE: The actual slew rate depends on the voltage step per

code. See the DCDC1 and DCDC2 registers for details.

000b = 224 µs/step (0.11 mV/µs at 25 mV per step)

001b = 112 µs/step (0.22 mV/µs at 25 mV per step)

010b = 56 µs/step (0.45 mV/µs at 25 mV per step)

011b = 28 µs/step (0.90 mV/µs at 25 mV per step)

100b = 14 µs/step (1.80 mV/µs at 25 mV per step)

101b = 7 µs/step (3.60 mV/µs at 25 mV per step)

110b = 3.5 µs/step (7.2 mV/µs at 25 mV per step)

111b = Immediate; slew rate is only limited by the control loop

response time.

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7.6.20 LDO1 Control Register (DEFLDO1) (Address = 0x12) [reset = 0x09]

DEFLDO1 is shown in Figure 48 and described in Table 20.

Return to Summary Table.

This register is password protected.

Figure 48. DEFLDO1 Register

7

6

5

4

3

2

1

0

Reserved

R-0000b

LDO1[3:0]

R/W-1001b

Table 20. DEFLDO1 Register Field Descriptions

Bit

7–4

3–0

Field

Type

Reset

0000b

1001b

Description

Reserved

LDO1[3:0]

R

These bits are reserved

R/W,

E2

LDO1 output voltage setting

0000b = 1 V

1000b = 1.6 V

1001b = 1.8 V

1010b = 2.5 V

1011b = 2.75 V

1100b = 2.8 V

1101b = 3 V

0001b = 1.1 V

0010b = 1.2 V

0011b = 1.25 V

0100b = 1.3 V

0101b = 1.35 V

0110b = 1.4 V

0111b = 1.5 V

1110b = 3.1 V

1111b = 3.3 V

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7.6.21 LDO2 Control Register (DEFLDO2) (Address = 0x13) [reset = 0x38]

DEFLDO2 is shown in Figure 49 and described in Table 21.

Return to Summary Table.

This register is password protected.

Figure 49. DEFLDO2 Register

7

6

5

4

3

2

1

0

Reserved

R-0b

TRACK

R/W-0b

LDO2[5:0]

R/W-111000b

Table 21. DEFLDO2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

Reserved

TRACK

R

0b

This bit is reserved

LDO2 tracking bit

R/W,

E2

0b = Output voltage is defined by the LDO2[5:0] bits.

1b = Output voltage follows the DCDC3 voltage setting (DEFDCDC3 register).

5–0

LDO2[5:0]

R/W,

E2⁽¹⁾

11 1000b

LDO2 output voltage setting

00 0000b = 0.9 V

00 0001b = 0.925 V

00 0010b = 0.95 V

00 0011b = 0.975 V

00 0100b = 1 V

01 0000b = 1.3 V

01 0001b = 1.325 V

01 0010b = 1.35 V

01 0011b = 1.375 V

01 0100b = 1.4 V

01 0101b = 1.425 V

01 0110b = 1.45 V

01 0111b = 1.475 V

01 1000b = 1.5 V

01 1001b = 1.55 V

01 1010b = 1.60 V

01 1011b = 1.65 V

01 1100b = 1.7 V

01 1101b = 1.75 V

01 1110b = 1.8 V

01 1111b = 1.85 V

10 0000b = 1.9 V

10 0001b = 1.95 V

10 0010b = 2 V

11 0000b = 2.7 V

11 0001b = 2.75 V

11 0010b = 2.8 V

11 0011b = 2.85 V

11 0100b = 2.9 V

11 0101b = 3 V

10 0011b = 2.05 V

10 0100b = 2.1 V

10 0101b = 2.15 V

10 0110b = 2.2 V

10 0111b = 2.25 V

10 1000b = 2.3 V

10 1001b = 2.35 V

10 1010b = 2.4 V

10 1011b = 2.45 V

10 1100b = 2.5 V

10 1101b = 2.55 V

10 1110b = 2.6 V

10 1111b = 2.65 V

00 0101b = 1.025 V

00 0110b = 1.05 V

00 0111b = 1.075 V

00 1000b = 1.1 V

00 1001b = 1.125 V

00 1010b = 1.15 V

00 1011b = 1.175 V

00 1100b = 1.2 V

00 1101b = 1.225 V

00 1110b = 1.25 V

00 1111b = 1.275 V

11 0110b = 3.1 V

11 0111b = 3.2 V

11 1000b = 3.3 V

11 1001b = 3.3 V

11 1010b = 3.3 V

11 1011b = 3.3 V

11 1100b = 3.3 V

11 1101b = 3.3 V

11 1110b = 3.3 V

11 1111b = 3.3 V

(1) The least-significant bit is not programmable.

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7.6.22 Load Switch1 or LDO3 Control Register (DEFLS1) (Address = 0x14) [reset = 0x26]

DEFLS1 is shown in Figure 50 and described in Table 22.

Return to Summary Table.

This register is password protected.

Figure 50. DEFLS1 Register

7

6

5

4

3

2

1

0

Reserved

R-00b

LS1LDO3

R/W-0b

LDO3[4:0]

R/W-00110b

Table 22. DEFLS1 Register Field Descriptions

Bit

7–6

5

Field

Reserved

LS1LDO3

Type

Reset

Description

R

00b

This bit is reserved

R/W,

E2

LS or LDO tracking bit

0b = FET functions as load switch (LS1).

1b = FET is configured as LDO3.

4–0

LDO3[4:0]

R/W,

E2

0 0110b

LDO3 output voltage setting (LS1LDO3 = 1b)

0 0000b = 1.5 V

0 0001b = 1.55 V

0 0010b = 1.6 V

0 0011b = 1.65 V

0 0100b = 1.7 V

0 0101b = 1.75 V

0 0110b = 1.8 V

0 0111b = 1.85 V

0 1000b = 1.90V

0 1001b = 2 V

1 0000b = 2.55 V

1 0001b = 2.6 V

1 0010b = 2.65 V

1 0011b = 2.7 V

1 0100b = 2.75 V

1 0101b = 2.8 V

1 0110b = 2.85 V

1 0111b = 2.9 V

1 1000b = 2.95 V

1 1001b = 3 V

0 1010b = 2.1 V

0 1011b = 2.2 V

0 1100b = 2.3 V

0 1101b = 2.4 V

0 1110b = 2.45 V

0 1111b = 2.5 V

1 1010b = 3.05 V

1 1011b = 3.1 V

1 1100b = 3.15 V

1 1101b = 3.2 V

1 1110b = 3.25 V

1 1111b = 3.3 V

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7.6.23 Load Switch2 or LDO4 Control Register (DEFLS2) (Address = 0x15) [reset = 0x3F]

DEFLS2 is shown in Figure 51 and described in Table 23.

Return to Summary Table.

This register is password protected.

Figure 51. DEFLS2 Register

7

6

5

4

3

2

1

0

Reserved

R-00b

LS2LDO4

R/W-1b

LDO4[4:0]

R/W-11111b

Table 23. DEFLS2 Register Field Descriptions

Bit

7–6

5

Field

Reserved

LS2LDO4

Type

Reset

Description

R

00b

1b

These bits are reserved

R/W,

E2

LS or LDO configuration bit

0b = FET functions as load a switch (LS2).

1b = FET is configured as LDO4.

4–0

LDO4[4:0]

R/W,

E2

1 1111b

LDO4 output voltage setting (LS2LDO4 = 1b)

0 0000b = 1.5 V

0 0001b = 1.55 V

0 0010b = 1.6 V

0 0011b = 1.65 V

0 0100b = 1.7 V

0 0101b = 1.75 V

0 0110b = 1.8 V

0 0111b = 1.85 V

0 1000b = 1.9 V

0 1001b = 2 V

1 0000b = 2.55 V

1 0001b = 2.6 V

1 0010b = 2.65 V

1 0011b = 2.7 V

1 0100b = 2.75 V

1 0101b = 2.8 V

1 0110b = 2.85 V

1 0111b = 2.9 V

1 1000b = 2.95 V

1 1001b = 3 V

0 1010b = 2.1 V

0 1011b = 2.2 V

0 1100b = 2.3 V

0 1101b = 2.4 V

0 1110b = 2.45 V

0 1111b = 2.5 V

1 1010b = 3.05 V

1 1011b = 3.1 V

1 1100b = 3.15 V

1 1101b = 3.2 V

1 1110b = 3.25 V

1 1111b = 3.3 V

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7.6.24 Enable Register (ENABLE) (Address = 0x16) [reset = 0x00]

ENABLE is shown in Figure 52 and described in Table 24.

Return to Summary Table.

This register is password protected.

Figure 52. ENABLE Register

7

6

5

4

3

2

1

0

Reserved

R-0b

LS1_EN

R/W-0b

LS2_EN

R/W-0b

DC1_EN

R/W-0b

DC2_EN

R/W-0b

DC3_EN

R/W-0b

LDO1_EN

R/W-0b

LDO2_EN

R/W-0b

Table 24. ENABLE Register Field Descriptions

Bit

Field

Type

Reset

Description

7

Reserved

R

0b

This bit is reserved

6

5

4

LS1_EN

LS2_EN

DC1_EN

R/W

LSW1 or LDO3 enable bit

NOTE: PWR_EN pin must be high to enable LS1 or LDO3.

0b = Disabled

1b = Enabled

0b

LS2 or LDO4 enable bit

NOTE: PWR_EN pin must be high to enable LS2 or LDO4.

0b = Disabled

1b = Enabled

DCDC1 enable bit

NOTE: PWR_EN pin must be high to enable the DC/DC

converter.

0b = DCDC1 is disabled.

1b = DCDC1 is enabled.

3

2

DC2_EN

DC3_EN

R/W

0b

DCDC2 enable bit

NOTE: PWR_EN pin must be high to enable the DC/DC

converter.

0b = DCDC2 is disabled.

1b = DCDC2 is enabled.

DCDC3 enable bit

NOTE: PWR_EN pin must be high to enable the DC/DC

converter.

0b = DCDC3 is disabled.

1b = DCDC3 is enabled.

1

0

LDO1_EN

LDO2_EN

R/W

0b

LDO1 enable bit

0b = Disabled

1b = Enabled

LDO2 enable bit

0b = Disabled

1b = Enabled

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7.6.25 UVLO Control Register (DEFUVLO) (Address = 0x18) [reset = 0x00]

DEFUVLO is shown in Figure 53 and described in Table 25.

Return to Summary Table.

This register is password protected.

Figure 53. DEFUVLO Register

7

6

5

4

3

2

1

0

Reserved

R-00000b

Reserved

R/W-0b

UVLO[1:0]

R/W-00b

Table 25. DEFUVLO Register Field Descriptions

Bit

7–3

2

Field

Type

Reset

00000b

0b

Description

Reserved

UVLO[1:0]

R

These bits are reserved

This bit is reserved

R/W

1–0

R/W, E2 00b

Undervoltage lockout setting

00b = 2.73 V

01b = 2.89 V

10b = 3.18 V

11b = 3.3 V

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7.6.26 Sequencer Register 1 (SEQ1) (Address = 0x19) [reset = 0x00]

SEQ1 is shown in Figure 54 and described in Table 26.

Return to Summary Table.

This register is password protected.

Figure 54. SEQ1 Register

7

6

5

4

3

2

1

0

Reserved

R-0b

DC1_SEQ[2:0]

R/W-000b

Reserved

R-0b

DC2_SEQ[2:0]

R/W-000b

Table 26. SEQ1 Register Field Descriptions

Bit

7

Field

Reserved

Type

Reset

Description

R

0b

This bit is reserved

6–4

DC1_SEQ[3:0]

R/W,

E2

000b

DCDC1 enable STROBE

000b = Rail is not controlled by sequencer.

001b = Enable at STROBE1

010b = Enable at STROBE2

011b = Enable at STROBE3

100b = Enable at STROBE4

101b = Enable at STROBE5

110b = Enable at STROBE6

111b = Enable at STROBE7

This bit is reserved

3

Reserved

R

0b

2–0

DC2_SEQ[3:0]

R/W,

E2

000b

DCDC2 enable STROBE

000b = Rail is not controlled by sequencer.

001b = Enable at STROBE1

010b = Enable at STROBE2

011b = Enable at STROBE3

100b = Enable at STROBE4

101b = Enable at STROBE5

110b = Enable at STROBE6

111b = Enable at STROBE7

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7.6.27 Sequencer Register 2 (SEQ2) (Address = 0x1A) [reset = 0x00]

SEQ2 is shown in Figure 55 and described in Table 27.

Return to Summary Table.

This register is password protected.

Figure 55. SEQ2 Register

7

6

5

4

3

2

1

0

Reserved

R-0b

DC3_SEQ[2:0]

R/W-000b

LDO1_SEQ[3:0]

R/W-0000b

Table 27. SEQ2 Register Field Descriptions

Bit

Field

Reserved

DC3_SEQ[2 R/W,

:0] E2

Type

Reset

Description

7

R

0b

This bit is reserved

6–4

000b

DCDC3 enable STROBE

000b = Rail is not controlled by sequencer.

001b = Enable at STROBE1

010b = Enable at STROBE2

011b = Enable at STROBE3

100b = Enable at STROBE4

101b = Enable at STROBE5

110b = Enable at STROBE6

111b = Enable at STROBE7

3–0

LDO1_SEQ R/W,

[3:0] E2

0000b

LDO1 enable state

0000b = Rail is not controlled by sequencer.

0001b = Enable at STROBE1

0010b = Enable at STROBE2

0011b = Enable at STROBE3

0100b = Enable at STROBE4

0101b = Enable at STROBE5

0110b = Enable at STROBE6

0111b = Enable at STROBE7

1000b = Rail is not controlled by sequencer

1001b = Rail is not controlled by sequencer

1010b to 1101b = Reserved

1110b = Enable at STROBE14

1111b = Enabled at STROBE15 (with SYS)

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7.6.28 Sequencer Register 3 (SEQ3) (Address = 0x1B) [reset = 0x00]

SEQ3 is shown in Figure 56 and described in Table 28.

Return to Summary Table.

This register is password protected.

Figure 56. SEQ3 Register

7

6

5

4

3

2

1

0

LDO2_SEQ[3:0]

R/W-0000b

Reserved

R-0b

LDO3_SEQ[2:0]

R/W-000b

Table 28. SEQ3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–4

LDO2_SEQ[3:0]

R/W, E2 0000b

LDO2 enable STROBE

0000b = Rail is not controlled by sequencer.

0001b = Enable at STROBE1

0010b = Enable at STROBE2

0011b = Enable at STROBE3

0100b = Enable at STROBE4

0101b = Enable at STROBE5

0110b = Enable at STROBE6

0111b = Enable at STROBE7

1000b = Rail is not controlled by sequencer.

1001b = Rail is not controlled by sequencer.

1010b to 1101b = Reserved

1110b = Enable at STROBE14

1111b = Enabled at STROBE15 (with SYS)

This bit is reserved

3

Reserved

R

0b

2–0

LDO3_SEQ[2:0]

R/W, E2 000b

LS1 or LDO3 enable state

000b = Rail is not controlled by sequencer

001b = Enable at STROBE1

010b = Enable at STROBE2

011b = Enable at STROBE3

100b = Enable at STROBE4

101b = Enable at STROBE5

110b = Enable at STROBE6

111b = Enable at STROBE7

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7.6.29 Sequencer Register 4 (SEQ4) (Address = 0x1C) [reset = 0x40]

SEQ4 is shown in Figure 57 and described in Table 29.

Return to Summary Table.

This register is password protected.

Figure 57. SEQ4 Register

7

6

5

4

3

2

1

0

Reserved

R-0b

LDO4_SEQ[2:0]

R/W-0000b

Reserved

R-0000b

Table 29. SEQ4 Register Field Descriptions

Bit

7

Field

Type

Reset

0b

R/W, E2 000b

Description

Reserved

LDO4_SEQ[2:0]

R

This bit is reserved

6–4

LS2 or LDO4 enable state

0000b = Rail is not controlled by sequencer.

0001b = Enable at STROBE1

0010b = Enable at STROBE2

0011b = Enable at STROBE3

0100b = Enable at STROBE4

0101b = Enable at STROBE5

0110b = Enable at STROBE6

0111b = Enable at STROBE7

These bits are reserved

3–0

Reserved

R

0000b

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7.6.30 Sequencer Register 5 (SEQ5) (Address = 0x1D) [reset = 0x20]

SEQ5 is shown in Figure 58 and described in Table 30.

Return to Summary Table.

This register is password protected.

Figure 58. SEQ5 Register

7

6

5

4

3

2

1

0

DLY4[1:0]

DLY1[1:0]

R/W-00b

DLY2[1:0]

R/W-10b

DLY3[1:0]

R/W-00b

Table 30. SEQ5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–6

DLY1[1:0]

DLY2[1:0]

DLY3[1:0]

DLY4[1:0]

R/W, E2⁽¹⁾00b

Delay1 time

00b = 1 ms

01b = 2 ms

10b = 5 ms

11b = 10 ms

5–4

3–2

1–0

R/W, E2⁽¹⁾10b

R/W, E2⁽¹⁾00b

Delay2 time

00b = 1 ms

01b = 2 ms

10b = 5 ms

11b = 10 ms

Delay3 time

00b = 1 ms

01b = 2 ms

10b = 5 ms

11b = 10 ms

Delay4 time

00b = 1 ms

01b = 2 ms

10b = 5 ms

11b = 10 ms

(1) The least-significant bit is not programmable.

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7.6.31 Sequencer Register 6 (SEQ6) (Address = 0x1E) [reset = 0x00]

SEQ6 is shown in Figure 59 and described in Table 31.

Return to Summary Table.

This register is password protected.

Figure 59. SEQ6 Register

7

6

5

4

3

2

1

0

DLY5[1:0]

R/W-00b

DLY6[1:0]

R/W-00b

Reserved

R-0b

SEQUP

R/W-0b

SEQDWN

R/W-0b

INSTDWN

R/W-0b

Table 31. SEQ6 Register Field Descriptions

Bit

Field

Type

Reset

Description

7–6

DLY5[1:0]

R/W,

E2⁽¹⁾

00b

Delay5 time

00b = 1 ms

01b = 2 ms

10b = 5 ms

11b = 10 ms

5–4

DLY6[1:0]

R/W,

E2⁽¹⁾

00b

Delay6 time

00b = 1 ms

01b = 2 ms

10b = 5 ms

11b = 10 ms

This bit is reserved

3

2

Reserved

SEQUP

R

0b

R/W

Set this bit to 1b to trigger a power-up sequence. This bit is

automatically reset to 0b.

1

0

SEQDWN

INSTDWN

R/W

0b

Set this bit to 1b to trigger a power-down sequence. This bit is

automatically reset to 0b.

Instant shutdown bit

NOTE: Shutdown occurs when the PWR_EN pin is pulled low or

the SEQDWN bit is set. Only those rails controlled by the

sequencer are shut down.

0b = Shutdown follows reverse power-up sequence

1b = All delays are bypassed and all rails are shut down at the

same time.

(1) The least-significant bit is not programmable.

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8 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS65217x device is designed to pair with various application processors. For detailed information on using

the TPS65217x device with Sitara AM335x processors, refer to the Powering the AM335x with the TPS65217x

user's guide.

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8.2 Typical Application

AC

SYS

BAT

from AC connector

To system load

VDDS_OSC

4.7µF

VDDS_PLL_DDR

VDDS_PLL_MPU

VDDS_PLL_CORE_LCD

VDDS_SRAM_MPU_BB

VDDS_SRAM_CORE_BG

VDDA1P8V_USB0

VDDS_DDR

22µF

USB

Single cell

Li+ Battery

Power Path

and Charger

from USB connector

4.7µF

BAT_SENSE

TS

10µF

INT_LDO

BYPASS

100nF

75k

10k NTC

VDDS

10µF

VDDSHVx(1.8)

L1

(1.8V)

VIN_DCDC1

VDDA_ADC

DCDC1

DCDC2

VDCDC1

10µF

DDR2

10µF

L2

(3.3V)

VIN_DCDC2

VDDSHVx(3.3)

VDCDC2

10µF

VDDA3P3V_USB0

10µF

SYS

L3

(1.1V)

VIN_DCDC3

VDD_CORE

VDD_MPU

DCDC3

VDCDC3

10µF

VIN_LDO

VLDO1

(1.8V)

LDO1

LDO2

VDDS_RTC

2.2uF

10uF

4.7µF

AGND

VLDO2

(3.3V)

Any system

power needs

PGND

LS1_IN

LS1_OUT

LS2_OUT

Any system

power needs

LS1/LDO3

LS2/LDO4

SYS or VDCDCx

LS2_IN

Any system

power needs

VBAT

VSYS

VICHARGE

VTS

MUX_OUT

AIN4

MUX

(0..3.3V)

MUX_IN

100nF

Any system voltage

Always-on

supply

Always-on

supply

100k

PB_IN

VIO

nRESET

SCL

No Connect

4.7k

VDDSHV6

I2C0_SCL

4.7k

VDDSHV6

SDA

VLDO1

SYS

18uH

I2C0_SDA

L4

PWR_EN

PGOOD

LDO_PGOOD

nINT

PMIC_PWR_EN

PWRONRSTN

RTC_PWRONRSTN

EXTINTn

FB_WLED

4.7µF

10k

VDDSHV6

VLDO1

WLED

Driver

100k

nWAKEUP

ISINK1

ISINK2

ISET1

ISET2

EXT_WAKEUP

Power Pad (TM)

TPS65217A

AM335x

图 60. Connection Diagram for Typical Application

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Typical Application (接下页)

8.2.1 Design Requirements

For this design example, use the parameters listed in 表 32.

表 32. Design Requirements

RAIL

DCDC1

VOLTAGE

SEQUENCE

1.8 V

3.3 V

1

2

DCDC2

DCDC3

1.1 V

3

LDO1

1.8 V

15

2

LDO2

3.3 V

LS1 or LDO3

LS2 or LDO4

Load switch

1

4

8.2.2 Detailed Design Procedure

表 33 lists the recommended inductors for the WLED boost converter. 表 34 lists the recommended capacitor for

the WLED boost converter.

表 33. Recommended Inductors for WLED Boost Converter

DIMENSIONS

PART NUMBER

SUPPLIER

VALUE (µH)

R_DS(mΩ) MAX

RATED CURRENT (A)

(mm × mm × mm)

7.5 × 7.5 × 4.5

CDRH74NP-180M

P1167.183

Sumida

Pulse

18

73

37

1.31

1.5

表 34. Recommended Output Capacitor for WLED Boost Converter

PART NUMBER

SUPPLIER

VOLTAGE RATING (V)

VALUE (µF)

DIMENSIONS

1206

DIELECTRIC

UMK316BJ475ML-T

Taiyo Yuden

50

4.7

X5R

8.2.2.1 Output Filter Design (Inductor and Output Capacitor)

8.2.2.1.1 Inductor Selection for Buck Converters

The step-down converters operate typically with 2.2-µH output inductors. Larger or smaller inductor values can

be used to optimize the performance of the device for specific operation conditions. The selected inductor must

be rated for its dc resistance and saturation current. The dc resistance of the inductance directly influences the

efficiency of the converter. Therefore, an inductor with the lowest dc resistance should be selected for highest

efficiency.

Use 公式 4 to calculate the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current, because, during heavy load transients, the

inductor current increases to a value greater than the calculated value.

DI_L

I_Lmax= I_OUTmax

+

2

where

•

I_Lmaxis the maximum inductor current

I_OUTmaxis the maximum output current

ΔI_Lis the peak-to-peak inductor ripple current (see 公式 5)

(4)

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V_OUT

V_IN

1-

DI_L= V_OUT

´

L ´ f

where

•

L is the inductor value.

f is the switching frequency (2.25 MHz typical).

(5)

The highest inductor current occurs at maximum input voltage (V_IN). Open-core inductors have a soft saturation

characteristic and can usually support greater inductor currents than a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the

corresponding converter. The core material must be considered because it differs from inductor to inductor and

has an impact on the efficiency, especially at high switching frequencies. Also, the resistance of the windings

greatly affects the converter efficiency at high load. 表 35 lists the recommended inductors.

表 35. Recommended Inductors for DCDC1, DCDC2, and DCDC3

PART NUMBER

LQM2HPN2R2MG0L

VLCF4018T-2R2N1R4-2

SUPPLIER

Murata

TDK

VALUE (µH)

R_DS(mΩ) MAX

RATED CURRENT (A)

DIMENSIONS (mm)

2 x 2.5 x 0.9

2.2

100

60

1.3

1.44

3.9 x 4.7 x 1.8

8.2.2.1.2 Output Capacitor Selection

The advanced fast-response voltage-mode control scheme of the two converters lets the use of small ceramic

capacitors with a typical value of 10 µF, without having large output-voltage undershoots and overshoots during

heavy load transients. Ceramic capacitors having low ESR values result in the lowest output voltage ripple and

are therefore recommended.

If ceramic output capacitors are used, the capacitor RMS ripple-current rating must always meet the application

requirements. Use 公式 6 to calculate the RMS ripple current (I_RMSCout).

V_OUT

1-

V_IN

1

I_RMSCout= V_OUT

´

L ´ f

2´ 3

(6)

At the nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple

is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging

and discharging the output capacitor as shown in 公式 7.

V_OUT

1-

V_IN

æ

ç

è

ö

÷

ø

1

DV_OUT= V_OUT

´

+ ESR

L ´ f

8´ C_OUT´ f

where

•

the highest output voltage ripple occurs at the highest input voltage

(7)

At light-load currents, the converters operate in power-save mode, and the output-voltage ripple depends on the

output capacitor value. The output-voltage ripple is set by the internal comparator delay and the external

capacitor. The typical output-voltage ripple is less than 1% of the nominal output voltage.

8.2.2.1.3 Input Capacitor Selection

Because the buck converter has a pulsating input current, a low-ESR input capacitor is required for the best input

voltage filtering and to minimize the interference with other circuits caused by high input-voltage spikes. The

converters require a ceramic input capacitor of 10 µF. The input capacitor can be increased without any limit for

better input voltage filtering. 表 36 lists the recommended ceramic capacitors.

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表 36. Recommended Input Capacitors for DCDC1, DCDC2, and DCDC3

PART NUMBER

C2012X5R0J226MT

JMK212BJ226MG

JMK212BJ106M

SUPPLIER

TDK

VALUE (µF)

DIMENSIONS

0805

22

10

Taiyo Yuden

TDK

0805

C2012X5R0J106M

0805

8.2.2.2 5-V Operation Without a Battery

The TPS652170 device has a linear charger for Li+ batteries, and TI recommends that a battery is included in

designs for ideal performance. However, the device can operate without a battery attached. Three basic use

cases are available for operation without a battery:

1. The system is designed for battery operation, but the battery is removable and the end user does not have

the battery inserted. The system can be powered by connecting an AC adaptor or USB supply.

2. A nonportable system operates on a (regulated) 5-V supply, but the PMIC must provide protection against

input overvoltage up to 20 V. Electrically, this case is the same as the previous case where the device is

powered by an AC adaptor. The battery pins (BAT and BATSENSE) are shorted together and floating, the

temperature sensing pin (TS) is left floating, and power is provided through the AC pin. The DC/DC

converters, the WLED driver, and the LDO regulators connect to the overvoltage-protected SYS pins. The

load switches (or LDO3 and LDO4, depending on configuration) typically connect to one of the lower system

rails, but can also be connected to the SYS pin.

3. A nonportable system operates on a regulated 5-V supply that does not require input overvoltage protection.

In this case, the 5-V power supply is connected through the BAT pins. The DC/DC converter inputs, WLED

driver, LDO1, and LDO2 are connected directly to the 5-V supply. A standard, constant-value 10-kΩ resistor

is connected from the TS pin to ground to simulate the NTC thermistor monitoring the battery. The load

switches (or LDO3 and LDO4, depending on configuration) typically connect to one of the lower system rails,

but can also be connected directly to the 5-V input supply.

图 61 shows the connection of the input power supply to the device for 5-V only operation, with 20-V input

overvoltage protection. 图 62 shows the connection of the input power supply to the device for 5-V only operation

without 20-V input overvoltage protection. 表 37 lists the functional differences between both setups.

5 V power supply

(4.3, 5.8 V)

AC

USB

22 μ

BAT

BAT_SENSE

BAT, BAT_SENSE,

and TS pins are

floating

BAT_SENSE

TS

SYS

10 k

TS

SYS

TPS65217

4.7 μ

18 μ

TPS65217

22 μ SYS

5V power supply

(2.7..5.5V)

L4

VIN_DCDC1

VIN_DCDC2

VIN_DCDC3

VIN_LDO

18 μ

L4

VIN_DCDC1

VIN_DCDC2

VIN_DCDC3

VIN_LDO

10 μ 10 μ 10 μ 10 μ

(1) The DC/DC converters are not protected

against input overvoltage.

10 μ 10 μ 10 μ 10 μ

图 62. Power Connection for 5-V Only Operation

The SYS node and DC/DC converters are

protected against input overvoltage up to

20 V.

Directly Wired to BAT Instead of a Battery

图 61. Power Connection for 5-V Only Operation

With OVP, Without a Battery

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表 37. Functional Differences Between 5-V Only Operation Without a Battery and With and Without 20-V

Input Overvoltage Protection

POWER SUPPLIED THROUGH AC PIN

(CASE (1) AND (2))

POWER SUPPLIED THROUGH BAT PIN

(CASE (3))

RESOURCE IMPACTED

The maximum operating input voltage is 5.8 V,

but the device is protected from input

overvoltage up to 20 V.

Input protection

The maximum operating input voltage is 5.5 V.

The input current for DC/DC converters passes

through AC-SYS power-path switch

(approximately 150 mΩ).

The internal power path is bypassed to minimize I²R

losses.

Power efficiency

BATTEMP bit

The BATTEMP bit (bit 0 in register 0x03) always

reads 1, but has no effect on operation of the

device.

The BATTEMP bit (bit 0 in register 0x03) always

The LDO1 regulator is automatically powered up The LDO1 regulator is OFF when the BAT pin is

when the AC pin is connected to the 5-V supply, connected to the 5-V supply. The PB_IN pin must be

Output rail status on initial power

connection

and the device goes to the WAIT PWR_EN

pulled low to go to the WAIT PWR_EN state. The

state. If the PWR_EN pin is not asserted within 5 PB_IN pin cannot stay low for greater than 8 s or a

s, the LDO1 regulator turns OFF.

Device goes to the OFF state.⁽¹⁾

reset will occur.

Not applicable

Response to input overvoltage

In an application with one source of input power,

if the input power drops below UVLO and

recovers before reaching 100 mV, the rising

edge may not be detected by the device. This

condition, known as a brownout, can cause a

lockup of the device in which the I²C is

Power path

Not applicable

responsive but SYS is not connected to the AC

(2)

or USB through the power path.

(1) If a battery is present in the system, the TPS652170 device automatically switches from using the AC pin as the power supply to using

BAT as the supply when the AC input exceeds 6.4 V. The device automatically switches back to supplying power from the AC pin when

the AC input recovers and the voltages decreases to less than 5.8 V.

(2) As a workaround, supply power through the BAT input pin or change UVLO to 2.73 V by changing the UVLO[1:0] bits in register 0x18 to

00b. This setting must be changed during initialization after the first power-on event of the device. The bits return to the default value

when all I²C registers reset. As a result, if a brownout condition can occur during the first power-on event, then external circuitry must be

added to prevent the TPS652170 device from being affected by the brownout condition.

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8.2.3 Application Curves

图 63. DCDCx Voltage Ripple and Inductor Current at 5 mA

图 64. DCDCx Voltage Ripple and Inductor Current at 50

Load, 1.1-V V_OUT

mA Load, 1.1-V V_OUT

图 65. DCDCx Voltage Ripple and Inductor Current at 300

图 66. DCDCx Voltage Ripple and Inductor Current at 5 mA

mA Load, 1.1-V V_OUT

Load, 1.5-V V_OUT

图 67. DCDCx Voltage Ripple and Inductor Current at 50

图 68. DCDCx Voltage Ripple and Inductor Current at 300

mA Load, 1.5-V V_OUT

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图 69. DCDCx Voltage Ripple and Inductor Current at 5 mA

图 70. DCDCx Voltage Ripple and Inductor Current at 50

Load, 3.3-V V_OUT

mA Load, 3.3-V V_OUT

图 71. DCDCx Voltage Ripple and Inductor Current at 300

图 72. DCDCx Load Transient Response, 1.1 V_OUT, 50-500-

mA Load, 3.3-V V_OUT

50 mA Load

图 73. DCDCx Load Transient Response, 1.1 V_OUT, 200-

图 74. DCDCx Load Transient Response, 1.5 V_OUT, 50-500-

1000-200 mA Load

50 mA Load

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图 75. DCDCx Load Transient Response, 1.5 V_OUT, 200-

1000-200 mA Load

图 76. DCDCx Load Transient Response, 3.3 V_OUT, 50-500-

50 mA Load

图 77. DCDCx Load Transient Response, 3.3 V_OUT, 200-1000-200 mA Load

9 Power Supply Recommendations

The device is designed to operate with an input voltage supply range from 2.75 V to 5.8 V. This input supply can

be from a single-cell Li-ion, Li-polymer batteries, dc supply, USB supply, or other externally regulated supply. If

the input supply is located more than a few inches from the TPS652170 device, additional bulk capacitance may

be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 4.7 µF is a

typical choice.

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10 Layout

10.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. Proper function of the device

requires careful attention to printed circuit-board (PCB) layout. Care must be taken in board layout to get the

specified performance.

•

The VIN_DCDCx and VINLDO pins should be bypassed to ground with a low-ESR ceramic bypass capacitor.

The typical recommended bypass capacitance is 10 μF and 4.7 μF with a X5R or X7R dielectric, respectively.

•

The optimum placement of these bypass capacitors is close to the VIN_DCDCx and VINLDO pins of the

TPS652170 device. Care should be taken to minimize the loop area formed by the bypass capacitor

connection, the VIN_DCDCx and VINLDO pins, and the thermal pad of the device.

•

The thermal pad should be tied to the PCB ground plane with multiple vias.

The inductor traces from the Lx pins to the V_OUTnode (VDCDCx) of each DCDCx converter should be kept

on the PCB top layer and free of any vias.

•

The VLDOx and VDCDCx pin (feedback pin labeled FB1 in 图 78) traces should be routed away from any

potential noise source to avoid coupling.

The DCDCx output capacitance should be placed immediately at the DCDCx pin. Excessive distance

between the capacitance and DCDCx pin may cause poor converter performance.

10.2 Layout Example

V_OUT

Output filter

capacitor

Input bypass

capacitor

Via to ground plane

Via to internal plane

IN

Thermal

Pad

图 78. Layout Example Schematic

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11 器件和文档支持

11.1 器件支持

11.1.1 第三方产品免责声明

TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类

产品或服务单独或与任何 TI 产品或服务一起的表示或认可。

11.2 文档支持

11.2.1 相关文档

请参阅如下相关文档：：

•

德州仪器 (TI)，《降压转换器功率级的基本计算》应用报告

德州仪器 (TI)，设计强大的 TPS65217 系统，以便应对 V_IN欠压的情况应用报告

德州仪器 (TI)，借助适用于处理器应用的电源管理 IC (PMIC) 改进设计应用报告

德州仪器 (TI)，TPS65217 电源管理 IC 评估模块用户指南

德州仪器 (TI)，使用 TPS65217x 为 AM335x 供电用户指南

德州仪器 (TI)，TPS65217x 原理图检查清单

11.3 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息、请查阅已修订文档中包含的修订历史记录。

11.4 社区资源

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.5 商标

E2E is a trademark of Texas Instruments.

Sitara is a trademark of Texas Instruments Incorporated.

ARM, Cortex are registered trademarks of ARM Ltd.

All other trademarks are the property of their respective owners.

11.6 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查看左侧的导航面板。

81

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122


型号：	TPS652170RSLT
厂家：	TEXAS INSTRUMENTS
描述：	具有 3 个直流/直流转换器、4 个 LDO、电池充电器和 LED 驱动器的用户可编程电源管理 IC (PMIC) \| RSL \| 48 \| -40 to 105 电池驱动集成电源管理电路驱动器转换器
文件：	总88页 (文件大小：1689K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS652170RSLT [TI]

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