TPS6521815RSLT [TI]
具有 6 个直流/直流转换器、1 个 LDO 和 3 个负载开关的用户可编程电源管理 IC (PMIC) | RSL | 48 | -40 to 105;
| 型号： | TPS6521815RSLT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 6 个直流/直流转换器、1 个 LDO 和 3 个负载开关的用户可编程电源管理 IC (PMIC) | RSL | 48 | -40 to 105 开关 集成电源管理电路 转换器 |
| 文件： | 总95页 (文件大小：2989K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS6521815
ZHCSKD3A –NOVEMBER 2019 –REVISED FEBRUARY 2021
具有6 个直流/直流转换器、1 个LDO 和3 个负载开关的TPS6521815 用户可编
程电源管理IC (PMIC)
– 欠压锁定(UVLO)
– 常开按钮监视器
– 过热警告和关断
– 备用电源和主电源采用独立的电源正常状态输出
– I2C 接口（地址0x24）（请参阅400kHz 时的
I2C 操作时序要求）
1 特性
• 具有集成开关FET 的3 个可调节降压转换器
（DCDC1、DCDC2 和DCDC3）：
– 高达1.8A 的输出电流
– 输入电压范围：2.7V 至5.5V
– 可调节输出电压范围：0.85V 至1.675V
（DCDC1 和DCDC2）
– 可调节输出电压范围：0.9V 至3.4V (DCDC3)
– 轻负载电流状态下进入节能模式
– 100% 占空比，可实现最低压降
– 禁用时支持有源输出放电
2 应用
• 电网基础设施
• 电器
• 楼宇安全系统
• 人机界面(HMI)
• 工业自动化
• 电子销售点(ePOS)
• 测试和测量
• 具有集成开关FET 的1 个可调节降压/升压转换器
(DCDC4)：
– 高达1.6A 的输出电流
3 说明
– 输入电压范围：2.7V 至5.5V
– 可调节输出电压范围：1.175V 至3.4V
– 禁用时支持有源输出放电
TPS6521815 是一款单芯片电源管理 IC (PMIC)，用户
可对其进行编程，以便为各种 SoC 和 FPGA 供电。此
器件的额定工作温度范围为 -40°C 至 +105°C，适用于
各种工业应用。
• 2 个适用于备用电池域的低静态电流、高效降压转
换器（DCDC5、DCDC6）
– DCDC5：1V 输出电压
– DCDC6：1.8V 输出电压
– 输入电压范围：2.2V 至5.5V
– 由系统电源或备用纽扣电池供电
• 可调节通用LDO (LDO1)
器件信息(1)
封装尺寸（标称值）
器件型号
封装
TPS6521815
VQFN (48) 6.00mm × 6.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– LDO1：默认电压为1.8V，电流高达400mA
– 输入电压范围：1.8V 至5.5V
– 可调节输出电压范围：0.9V 至3.4V
– 禁用时支持有源输出放电
• 具有350mA 电流限制的低电压负载开关(LS1)
– 输入电压范围：1.2V 至3.6V
– 电压为1.35V 时，开关阻抗为110mΩ（最大
值）
• 具有100mA 或500mA 可选电流限制的5V 负载开
关(LS2)
– 输入电压范围：3V 至5.5V
– 电压为5V 时，开关阻抗为500mΩ（最大值）
• 具有100mA 或500mA 可选电流限制的高电压负载
开关(LS3)
– 输入电压范围：1.8V 至10V
– 开关阻抗：500mΩ（最大值）
• 带有内置监控功能的监控器可用于监测：
– DCDC1、DCDC2 ±4% 容差
– DCDC3、DCDC4 ±5% 容差
– LDO1 ±5% 容差
• 保护、诊断和控制：
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLDS261
TPS6521815
ZHCSKD3A –NOVEMBER 2019 –REVISED FEBRUARY 2021
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3.1 Simplified Schematic
+
10 …F
10 …F
œ
1 …F
4.7 …F
4.7 …F
4.7 …F
1 …F
IN_DCDC3
SYS_BU
L6
L3
10 …F
22 …F
1.5 µH
10 µH
FB3
FB6
nWAKEUP
FB5
VDD_18
(DCDC6)
100 kꢀ
FB2
L5
22 …F
1.5 µH
10 …F
L2
PGOOD_BU
IN_nCC
DC34_SEL
PFI
1.5 µH
TPS65218xx
IN_DCDC2
4.7 …F
PB
IN_BIAS
100 kꢀ
nINT
VIO
100 kꢀ
PWR_EN
DCDC4
L4B
100 nF
47 …F
100 kꢀ
FB1
1.5 µH
L1
10 …F
1.5 µH
L4A
10 …F
10 …F
4.7 …F
4.7 …F
4.7 …F
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Table of Contents
8.4 Device Functional Modes..........................................43
8.5 Programming............................................................ 45
8.6 Register Maps...........................................................46
9 Application and Implementation..................................78
9.1 Application Information............................................. 78
9.2 Typical Application.................................................... 80
10 Power Supply Recommendations..............................84
11 Layout...........................................................................84
11.1 Layout Guidelines................................................... 84
11.2 Layout Example...................................................... 84
12 Device and Documentation Support..........................86
12.1 Documentation Support.......................................... 86
12.2 Receiving Notification of Documentation Updates..86
12.3 支持资源..................................................................86
12.4 Trademarks.............................................................86
12.5 静电放电警告.......................................................... 86
12.6 术语表..................................................................... 86
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
3.1 Simplified Schematic...................................................2
4 Revision History.............................................................. 3
5 Description (continued).................................................. 4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings............................................................... 7
7.3 Recommended Operating Conditions.........................8
7.4 Thermal Information....................................................8
7.5 Electrical Characteristics.............................................9
7.6 Timing Requirements................................................18
7.7 Typical Characteristics..............................................19
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................21
8.3 Feature Description...................................................22
Information.................................................................... 86
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2019) to Revision A (February 2021)
Page
• 更新了整个文档的表、图和交叉参考的编号格式................................................................................................ 1
• 删除了应用部分中的医疗设备.............................................................................................................................1
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5 Description (continued)
Three hysteretic step-down converters are targeted at providing power for the processor core, MPU, and DDRx
memory. The default output voltages for each converter can be adjusted through the I2C interface. DCDC1 and
DCDC2 feature dynamic voltage scaling to provide power at all operating points of the processor. DCDC1 and
DCDC2 also have programmable slew rates to help protect processor components. DCDC3 remains powered
while the processor is in sleep mode to maintain power to DDRx memory. Backup power provides two step-down
converters for the tamper, RTC, or both domains of the processor if system power fails or is disabled. If both
system power and coin-cell battery are connected to the PMIC, power is not drawn from the coin-cell battery. A
separate power good signal monitors the backup converters. A battery backup monitor determines the power
level of the coin-cell battery.
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6 Pin Configuration and Functions
图6-1 shows the 48-pin RSL Plastic Quad Flatpack No-Lead.
IN_DCDC1
SDA
1
36
35
34
33
32
31
30
29
28
27
26
25
IN_BIAS
INT_LDO
GPO2
LS2
2
SCL
3
LDO1
4
IN_LDO1
IN_LS3
LS3
5
IN_LS2
IN_LS1
LS1
6
Thermal
Pad
7
PGOOD
AC_DET
nPFO
8
N/C
9
N/C
10
11
12
IN_BU
GPIO3
CC
GPIO1
IN_DCDC4
Not to scale
图6-1. 48-Pin RSL VQFN With Exposed Thermal Pad (Top View, 6 mm × 6 mm × 1 mm With 0.4-mm
Pitch)
表6-1. Pin Functions
PIN
TYPE
DESCRIPTION
NO.
1
NAME
IN_DCDC1
SDA
P
Input supply pin for DCDC1.
2
I/O Data line for the I2C interface. Connect to pullup resistor.
3
SCL
I
Clock input for the I2C interface. Connect to pullup resistor.
Output voltage pin for LDO1. Connect to capacitor.
Input supply pin for LDO1.
4
LDO1
O
P
P
O
5
IN_LDO1
IN_LS3
LS3
6
Input supply pin for load switch 3.
7
Output voltage pin for load switch 3. Connect to capacitor.
Power-good output (configured as open drain). Pulled low when either DCDC1-4 or LDO1 are out of
regulation. Load switches and DCDC5-6 do not affect PGOOD pin.
8
PGOOD
AC_DET
nPFO
O
I
AC monitor input and enable for DCDC1-4, LDO1 and load switches. See 节8.4.1 for details. Tie pin to
IN_BIAS if not used.
9
Power-fail comparator output, deglitched (open drain). Pin is pulled low when PFI input is below power-fail
threshold.
10
11
O
Pin configured as DDR reset-input (driving GPO2) or as general-purpose, open-drain output. See 节8.3.1.14
for more information.
GPIO1
I/O
12
13
14
15
16
IN_DCDC4
L4A
P
P
P
P
I
Input supply pin for DCDC4.
Switch pin for DCDC4. Connect to inductor.
Switch pin for DCDC4. Connect to inductor.
Output voltage pin for DCDC4. Connect to capacitor.
Power-fail comparator input. Connect to resistor divider.
L4B
DCDC4
PFI
Power-up default selection pin for DCDC3 or DCDC4. Power-up default is programmed by a resistor
connected to ground. See 节8.3.1.13 for resistor options.
17
DC34_SEL
I
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表6-1. Pin Functions (continued)
PIN
NAME
TYPE
DESCRIPTION
NO.
Output pin indicates if DCDC5 and DCDC6 are powered from main supply (IN_BU) or coin-cell battery (CC).
Pin is push-pull output. Pulled low when PMIC is powered from coin cell battery. Pulled high when PMIC is
powered from main supply (IN_BU).
18
IN_nCC
O
O
Power-good, push-pull output for DCDC5 and DCDC6. Pulled low when either DCDC5 or DCDC6 is out of
regulation. Pulled high (to DCDC6 output voltage) when both rails are in regulation.
19
PGOOD_BU
20
21
22
23
L5
FB5
FB6
L6
P
I
Switch pin for DCDC5. Connect to inductor.
Feedback voltage pin for DCDC5. Connect to output capacitor.
Feedback voltage pin for DCDC6. Connect to output capacitor.
Switch pin for DCDC6. Connect to inductor.
I
P
System voltage pin for battery-backup supply power path. Connect to 1-µF capacitor. Connecting any
external load to this pin is not recommended.
24
25
26
SYS_BU
CC
P
P
Coin cell battery input. Serves as the supply to DCDC5 and DCDC6 if no voltage is applied to IN_BU. Tie this
pin to ground if it is not in use.
Pin can be configured as warm reset (negative edge) for DCDC1 and DCDC2 or as a general-purpose, open-
drain output. See 节8.3.1.14 for more details.
GPIO3
I/O
P
27
28
29
30
31
32
33
IN_BU
N/C
Default input supply pin for battery backup supplies (DCDC5 and DCDC6).
No connect. Leave pin floating.
—
N/C
LS1
O
P
P
O
Output voltage pin for load switch 1. Connect to capacitor.
Input supply pin for load switch 1.
IN_LS1
IN_LS2
LS2
Input supply pin for load switch 2.
Output voltage pin for load switch 2. Connect to capacitor.
Pin configured as DDR reset signal (controlled by GPIO1) or as general-purpose output. Buffer can be
configured as push-pull or open-drain.
34
35
GPO2
O
P
Internal bias voltage. Connect to a 1-μF capacitor. TI does not recommended connecting any external load
to this pin.
INT_LDO
36
37
38
39
40
41
42
43
IN_BIAS
IN_DCDC3
L3
P
P
P
I
Input supply pin for reference system.
Input supply pin for DCDC3.
Switch pin for DCDC3. Connect to inductor.
Feedback voltage pin for DCDC3. Connect to output capacitor.
Signal to SOC to indicate a power on event (active low, open-drain output).
Feedback voltage pin for DCDC2. Connect to output capacitor.
Switch pin for DCDC2. Connect to inductor.
Input supply pin for DCDC2.
FB3
nWAKEUP
FB2
O
I
L2
P
P
IN_DCDC2
Push-button monitor input. Typically connected to a momentary switch to ground (active low). See 节8.4.1
for details.
44
45
PB
I
Interrupt output (active low, open drain). Pin is pulled low if an interrupt bit is set. The pin returns to Hi-Z state
after the bit causing the interrupt has been read. Interrupts can be masked.
nINT
O
46
47
48
—
PWR_EN
FB1
I
Power enable input for DCDC1-4, LDO1 and load switches. See 节8.4.1 for details.
Feedback voltage pin for DCDC1. Connect to output capacitor.
Switch pin for DCDC1. Connect to inductor.
I
L1
P
P
Thermal Pad
Power ground and thermal relief. Connect to ground plane.
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7 Specifications
7.1 Absolute Maximum Ratings
Operating under free-air temperature range (unless otherwise noted).(1)
MIN
MAX
UNIT
IN_BIAS, IN_LDO1, IN_LS2, IN_DCDC1, IN_DCDC2,
IN_DCDC3, IN_DCDC4
7
–0.3
IN_LS1, CC
3.6
11.2
5.8
7
–0.3
–0.3
–0.3
–0.3
Supply voltage
V
IN_LS3
IN_BU
Output voltage
All pins unless specified separately
GPO2
V
6
Source or sink
current
mA
PGOOD_BU, IN_nCC
1
Sink current
PGOOD, nWAKEUP, nINT, nPFO, SDA, GPIO1, GPIO3
6
mA
°C
°C
°C
TA
Operating ambient temperature
Junction temperature
105
125
150
–40
–40
–65
TJ
Tstg
Storage temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted).
MIN
2.7
NOM
MAX
UNIT
V
Supply voltage, IN_BIAS
Input voltage for DCDC1, DCDC2, DCDC3, and DCDC4
Supply voltage, IN_BU
5.5
5.5
2.7
V
2.2
5.5
V
Supply voltage, CC
2.2
3.3
V
Input voltage for LDO1
1.8
5.5
V
Input voltage for LS1
1.2
3.6
V
Input voltage for LS2
3
5.5
V
Input voltage for LS3
1.8
10
V
Output voltage for DCDC1
Output voltage for DCDC2
Output voltage for DCDC3
Output voltage for DCDC4
Output voltage for DCDC5
Output voltage for DCDC6
Output voltage for LDO1
0.85
0.85
0.9
1.675
1.675
3.4
V
V
V
1.175
3.4
V
1
V
1.8
V
0.9
0
3.4
1.8
1
V
Output current for DCDC1, DCDC2, and DCDC3
VIN_DCDC4 = 2.8 V
A
Output current for DCDC4
VIN_DCDC4 = 3.6 V
VIN_DCDC4 = 5 V
1.3
1.6
25
A
Output current for DCDC5 and DCDC6
Output current for LDO1
0
0
0
0
0
0
mA
mA
mA
mA
400
300
920
900
475
Output current for LS1
Output current for LS2
VIN_LS3 > 2.3 V
Output current for LS3
mA
VIN_LS3 ≤2.3 V
7.4 Thermal Information
TPS6521815
RSL (VQFN)
48 PINS
17.2
THERMAL METRIC(1)
UNIT
RθJC(top)
RθJB
Junction-to-case (top)
Junction-to-board
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
5.8
RθJA
Thermal resistance, junction-to-ambient. JEDEC 4-layer, high-K board.
Junction-to-package top
30.6
0.2
ΨJT
Junction-to-board
5.6
ΨJB
RθJC(bot)
Junction-to-case (bottom)
1.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
INPUT VOLTAGE AND CURRENTS
Normal operation
2.7
4.5
5.5
V
5.5
VIN_BIAS
Input supply voltage range
EEPROM programming
Deglitch time
5
5
ms
µA
OFF state current, total current
into IN_BIAS, IN_DCDCx,
IN_LDO1, IN_LS
VIN = 3.6 V; All rails disabled.
TJ = 0°C to 85°C
IOFF
VIN = 3.6 V; DCDC3 enabled, low-power mode, no
load.
All other rails disabled.
TJ = 0°C to 105°C
SUSPEND current, total current
into IN_BIAS, IN_DCDCx,
IN_LDO1, IN_LS
ISUSPEND
220
µA
SYS_BU
VSYS_BU
SYS_BU voltage range
Powered from VIN_BU or VCC
2.2
5.5
V
Recommended SYS_BU
capacitor
1
µF
Ceramic, X5R or X7R, see 表9-3.
Ceramic, X5R or X7R, rated voltage ≥6.3 V
CSYS_BU
Tolerance
20%
–20%
INT_LDO
Output voltage
2.5
23
V
VINT_LDO
DC accuracy
IOUT < 10 mA
2%
–2%
IOUT
Output current range
Short circuit current limit
Maximum allowable external load
Output shorted to GND
0
10 mA
mA
ILIMIT
Measured from VINT_LDO = to VINT_LDO = 1.8 V
All rails enabled before power off,
IN_BIAS tied to IN_DCDC1-4, IN_LDO1
VIN_BIAS = 2.8 V to 0 V in < 5 µs
tHOLD
Hold-up time
150
ms
No external load on INT_LDO
CINT_LDO = 1 µF, see 表9-3.
Nominal output capacitor value
Tolerance
0.1
1
22 µF
Ceramic, X5R or X7R, see 表9-3.
COUT
20%
Ceramic, X5R or X7R, rated voltage ≥6.3 V
–20%
DCDC1 (1.1-V BUCK)
VIN_DCDC1 Input voltage range
VIN_BIAS > VUVLO
5.5
V
V
Output voltage range
DC accuracy
Adjustable through I2C
2.7 V ≤VIN ≤5.5 V; 0 A ≤IOUT ≤1.8 A
VIN_DCDC1 > 2.7 V
0.85
1.675
2%
VDCDC1
IOUT
IQ
–2%
Continuous output current
1.8
A
Total current from IN_DCDC1 pin; Device not switching,
no load
Quiescent current
25
50 µA
High-side FET on resistance
Low-side FET on resistance
High-side current limit
VIN_DCDC1 = 3.6 V
VIN_DCDC1 = 3.6 V
VIN_DCDC1 = 3.6 V
VIN_DCDC1 = 3.6 V
230
90
355
145
RDS(ON)
mΩ
2.8
3.1
ILIMIT
A
Low-side current limit
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MAX UNIT
7.5 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
88.5%
96%
TYP
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
90% 91.5%
Power-good threshold
VOUT falling
VOUT rising
VOUT falling
VOUT rising
96.5%
97%
3.8%
4.1%
0.25%
1
4.4%
Hysteresis
VPG
ms
µs
µs
µs
ms
50
Deglitch
Time-out
10
10
5
Overvoltage detection threshold VOUT rising, STRICT = 1b
103% 103.5%
104%
VOV
Hysteresis
VOUT falling, STRICT = 1b
VOUT rising, STRICT = 1b
0.25%
50
Deglitch
µs
IINRUSH
RDIS
Inrush current
VIN_DCDC1 = 3.6 V; COUT = 10 µF to 100 µF
500 mA
350
2.2 µH
30%
100(8) µF
Discharge resistor
Nominal inductor value
Tolerance
150
1
250
1.5
Ω
See 表9-2.
L
–30%
10
COUT
Output capacitance value
22
Ceramic, X5R or X7R, see 表9-3.
DCDC2 (1.1-V BUCK)
VIN_DCDC2 Input voltage range
VIN_BIAS > VUVLO
2.7
0.85
5.5
1.675
2%
V
V
Output voltage range
DC accuracy
Adjustable through I2C
2.7 V ≤VIN ≤5.5 V; 0 A ≤IOUT ≤1.8 A
VIN_DCDC2 > 2.7 V
VDCDC2
IOUT
IQ
–2%
Continuous output current
1.8
A
Total current from IN_DCDC2 pin; device not switching,
no load
Quiescent current
25
50 µA
High-side FET on resistance
Low-side FET on resistance
High-side current limit
VIN_DCDC2 = 3.6 V
VIN_DCDC2 = 3.6 V
VIN_DCDC2 = 3.6 V
VIN_DCDC2 = 3.6 V
230
90
355
145
RDS(ON)
mΩ
2.8
3.1
ILIMIT
A
Low-side current limit
STRICT = 0b
88.5%
96%
90% 91.5%
Power-good threshold
Hysteresis
VOUT falling
STRICT = 1b
96.5%
97%
STRICT = 0b
3.8%
4.1%
0.25%
1
4.4%
VOUT rising
STRICT = 1b
STRICT = 0b
ms
µs
µs
µs
VPG
VOUT falling
STRICT = 1b
50
Deglitch
Time-out
STRICT = 0b
10
VOUT rising
STRICT = 1b
10
Occurs at enable of DCDC2 and after DCDC2
register write (register 0x17).
5
ms
Overvoltage detection threshold VOUT rising, STRICT = 1b
103% 103.5%
104%
VOV
Hysteresis
VOUT falling, STRICT = 1b
0.25%
50
Deglitch
VOUT rising, STRICT = 1b
µs
IINRUSH
RDIS
Inrush current
Discharge resistor
Nominal inductor value
Tolerance
VIN_DCDC2 = 3.6 V; COUT = 10 µF to 100 µF
500 mA
350
2.2 µH
30%
150
1
250
1.5
Ω
See 表9-2.
L
–30%
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7.5 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
COUT
Output capacitance value
10
22
100(8) µF
Ceramic, X5R or X7R, see 表9-3.
DCDC3 (1.2-V BUCK)
VIN_DCDC3 Input voltage range
VIN_BIAS > VUVLO
2.7
0.9
5.5
3.4
V
V
Output voltage range
Adjustable through I2C
VDCDC3
2.7 V ≤VIN ≤5.5 V; 0 A ≤IOUT ≤1.8 A,
DC accuracy
2%
1.8
–2%
VIN_DCDC3 ≥(VDCDC3 + 700 mV)
IOUT
IQ
Continuous output current
Quiescent current
VIN_DCDC3 > 2.7 V
A
Total current from IN_DCDC3 pin;
Device not switching, no load
25
50 µA
High-side FET on resistance
Low-side FET on resistance
High-side current limit
VIN_DCDC3 = 3.6 V
VIN_DCDC3 = 3.6 V
VIN_DCDC3 = 3.6 V
VIN_DCDC3 = 3.6 V
230
100
2.8
3
345
150
RDS(ON)
mΩ
ILIMIT
A
Low-side current limit
STRICT = 0b
88.5%
95%
90% 91.5%
Power-good threshold
Hysteresis
VOUT falling
VOUT rising
VOUT falling
VOUT rising
STRICT = 1b
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
95.5%
96%
3.8%
4.1%
0.25%
1
4.4%
ms
µs
µs
µs
VPG
50
Deglitch
Time-out
10
10
Occurs at enable of DCDC3 and after DCDC3
register write (register 0x18).
5
ms
Overvoltage detection threshold VOUT rising, STRICT = 1b
104% 104.5%
105%
VOV
Hysteresis
VOUT falling, STRICT = 1b
0.25%
50
Deglitch
VOUT rising, STRICT = 1b
µs
IINRUSH
RDIS
Inrush current
VIN_DCDC3 = 3.6 V; COUT = 10 µF to 100 µF
500 mA
350
2.2 µH
30%
Discharge resistor
Nominal inductor value
Tolerance
150
1.0
250
1.5
Ω
See 表9-2.
L
–30%
10
COUT
Output capacitance value
22
100 µF
Ceramic, X5R or X7R, see 表9-3.
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O
PFM mode enabled;
4.2 V ≤VIN ≤5.5 V;
0 A ≤IOUT ≤1.6 A
VOUT = 3.3 V
Output voltage ripple
150 mVpp
Minimum duty cycle in step-
down mode
18%
1
VIN_DCDC4 = 2.8 V, VOUT = 3.3 V
VIN_DCDC4 = 3.6 V, VOUT = 3.3 V
VIN_DCDC4 = 5 V, VOUT = 3.3 V
IOUT
Continuous output current
1.3
1.6
A
Total current from IN_DCDC4 pin; Device not
switching, no load.
IQ
Quiescent current
25
50 µA
kHz
fSW
Switching frequency
2400
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MAX UNIT
7.5 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
166
IN_DCDC4 to L4A
L4B to DCDC4
L4A to GND
High-side FET on resistance
VIN_DCDC3 = 3.6 V
149
RDS(ON)
mΩ
142
190
Low-side FET on resistance
Average switch current limit
Power-good threshold
VIN_DCDC3 = 3.6 V
VIN_DCDC4 = 3.6 V
VOUT falling
L4B to GND
144
190
mA
ILIMIT
3000
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
88.5%
95%
90% 91.5%
95.5%
96%
3.8%
4.1%
0.25%
1
4.4%
Hysteresis
VOUT rising
VOUT falling
VOUT rising
ms
µs
µs
µs
VPG
50
Deglitch
Time-out
10
10
Occurs at enable of DCDC4 and after DCDC4
register write (register 0x19)
5
ms
Overvoltage detection threshold VOUT rising, STRICT = 1b
104% 104.5%
105%
VOV
Hysteresis
Deglitch
VOUT falling, STRICT = 1b
0.25%
50
VOUT rising, STRICT = 1b
µs
VIN_DCDC4 = 3.3 V ≤VINDCDC4 ≤5.5 V; 40 µF ≤
IINRUSH
RDIS
Inrush current
500 mA
COUT ≤100 µF
Discharge resistor
Nominal inductor value
Tolerance
150
1.2
250
1.5
350
2.2 µH
30%
100 µF
Ω
See 表9-2.
L
–30%
40
COUT
Output capacitance value
80
Ceramic, X5R or X7R, see 表9-3.
DCDC5 and DCDC6 POWER PATH
DCDC5 and DCDC6 input
voltage range.
VCC
VIN_BU = 0 V
2.2
3.3
5.5
V
DCDC5 and DCDC6 input
VIN_BU
2.2
30
V
voltage range(1)
tRISE
VCC, VIN_BU rise time
VCC = 0 V to 3.3 V, VIN_BU = 0 V to 5.5 V
µs
CC to SYS_BU
VCC = 2.4 V, VIN_BU = 0 V
Power path switch impedance
14.5
10.5
RDS(ON)
Ω
IN_BU to SYS_BU
VIN_BU = 3.6 V
Power path switch impedance
Forward leakage current
Into CC pin;
VCC = 3.3 V, VIN_BU = 0 V;
OFF state; FSEAL = 0b;
over full temperature range
50
300
ILEAK
nA
Out of CC pin;
Reverse leakage current
VCC = 1.5 V; VIN_BU = 5.5 V;
over full temperature range
500
Acceptable CC source
impedance
IOUT, DCDC5 < 10 µA;
IOUT, DCDC6 < 10 µA
RCC
IQ
1000
Ω
Average current into CC pin; RECOVERY or OFF
state; VIN_BU = 0 V; VCC = 2.4 V; DCDC5 and
DCDC6 enabled, no load TJ = 25°C
Quiescent current
Inrush charge
350
720
nA
VIN_BIAS = decaying; CC = 3 V; CSYS_BU = 1 µF;
SYS_BU = 2.3 V to 3 V; CCseries_resist = 10 ΩCCC
4.7 µF
QINRUSH
nC
=
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7.5 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
DCDC5 (1-V BATTERY BACKUP SUPPLY)
Output voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
1
V
2.7 V ≤VIN_BU ≤5.5 V;
1.5 µA ≤IOUT ≤25 mA
–40°C ≤TA < 0°C
2.5%
–2.5%
2.7 V ≤VIN_BU ≤5.5 V
1.5 µA ≤IOUT ≤25 mA
0°C ≤TA < 105°C
DC accuracy
VDCDC5
2%
–2%
2.2 V ≤VCC ≤3.3 V; VIN_BU = 0;
1.5 µA ≤IOUT ≤100 µA
2.5%
–2.5%
L = 10 µH; COUT = 22 µF; 100-µA load, occurs during
band-gap sampling
Output voltage ripple
32(9) mVpp
100 µA
2.2 V ≤VCC ≤3.3 V
VIN_BU = 0 V
10
IOUT
Continuous output current
25 mA
3.5
Ω
2.7 V ≤VIN_BU ≤5.5 V
VIN_BU = 2.8 V
High-side FET on resistance
Low-side FET on resistance
High-side current limit
Power-good threshold
Hysteresis
2.5
2
RDS(ON)
ILIMIT
VIN_BU = 2.8 V
3
VIN_BU = 2.8 V
50
mA
VOUT falling
79%
85%
6%
10
91%
VPG
VOUT rising
Nominal inductor value
Tolerance
4.7
–30%
20(10)
22 µH
30%
Chip inductor, see 表9-3.
L
Output capacitance value
Tolerance
47 µF
20%
Ceramic, X5R or X7R, see 表9-3.
COUT
–20%
DCDC6 (1.8-V BATTERY BACKUP SUPPLY)
VDCDC6
VDCDC6
Output voltage
1.8
10
V
Output voltage ripple
L = 10 µH; COUT = 22 µF; 100-µA load
30(9) mVpp
2.2 V ≤VCC ≤3.3 V
VIN_BU = 0 V
100 µA
IOUT
Continuous output current
25 mA
3.5
Ω
2.7 V ≤VIN_BU ≤5.5 V
VIN_BU = 3 V
High-side FET on resistance
Low-side FET on resistance
High-side current limit
Power-good threshold
Hysteresis
2.5
2
RDS(ON)
ILIMIT
VIN_BU = 3 V
3
VIN_BU = 3 V
50
mA
VOUT falling
87%
91%
3%
10
95%
VPG
VOUT rising
Nominal inductor value
Tolerance
4.7
–30%
20(10)
22 µH
30%
Chip inductor, see 表9-3
L
Output capacitance value
Tolerance
47 µF
20%
Ceramic, X5R or X7R, see 表9-3
COUT
–20%
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MAX UNIT
7.5 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
LDO1 (1.8-V LDO)
VIN_LDO1
IQ
TEST CONDITIONS
MIN
TYP
Input voltage range
Quiescent current
Output voltage range
DC accuracy
VIN_BIAS > VUVLO
1.8
5.5
V
µA
V
No load
35
Adjustable through I2C
0.9
–2%
0
3.4
2%
VOUT
VOUT + 0.2 V ≤VIN ≤5.5 V; 0 A ≤IOUT ≤200 mA
200
400
V
IN_LDO1 –VDO = VOUT
IOUT
Output current range
mA
mA
VIN_LDO1 > 2.7 V, VOUT = 1.8 V
Output shorted to GND
0
ILIMIT
VDO
Short circuit current limit
Dropout voltage
445
550
IOUT = 100 mA, VIN = 3.6 V
200 mV
94%
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
STRICT = 0b
STRICT = 1b
86%
95%
3%
90%
95.5%
4%
VOUT falling
96%
Power-good threshold
5%
Hysteresis, VOUT rising
VOUT falling
0.25%
1
ms
µs
µs
µs
VPG
50
Deglitch
Time-out
10
VOUT rising
10
Occurs at enable of LDO and after LDO register
write (register 0x1B)
5
ms
Overvoltage detection threshold VOUT rising, STRICT = 1b
104% 104.5%
105%
Hysteresis
VOUT falling, STRICT = 1b
VOUT rising, STRICT = 1b
VOUT falling, STRICT = 1b
0.25%
50
VOV
µs
Deglitch
1
ms
RDIS
Discharge resistor
150
1.2
250
22
380
Ω
COUT
Output capacitance value
Ceramic, X5R or X7R
VIN_BIAS > VUVLO
100 µF
LOAD SWITCH 1 (LS1)
VIN_LS1 Input voltage range
3.6
V
VIN_LS1 = 3.3 V, IOUT = 300 mA, over full temperature
range
110
VIN_LS1 = 1.8 V, IOUT = 300 mA,
DDR2, LPDDR, MDDR at 266 MHz over full
temperature range
110
RDS(ON)
Static on resistance
VIN_LS1 = 1.5 V, IOUT = 300 mA,
DDR3 at 333 MHz over full temperature range
mΩ
110
110
150
VIN_LS1 = 1.35 V, IOUT = 300 mA,
DDR3L at 333 MHz over full temperature range
VIN_LS1 = 1.2 V, IOUT = 200 mA,
LPDDR2 at 333 MHz over full temperature range
ILIMIT
Short circuit current limit
Interrupt blanking time
Output shorted to GND
350
mA
ms
tBLANK
Output shorted to GND until interrupt is triggered.
15
Internal discharge resistor at
output(2)
RDIS
TOTS
COUT
LS1DCHRG = 1
150
125
250
380
139
Ω
Overtemperature shutdown(3)
132
10
°C
Hysteresis
Nominal output capacitance
value
10
100 µF
Ceramic, X5R or X7R, see 表9-3.
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7.5 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LOAD SWITCH 2 (LS2)
VIN_LS2
VUVLO
Input voltage range
Undervoltage lockout
Hysteresis
VIN_BIAS > VUVLO
3
5.5
2.7
V
V
Measured at IN_LS2. Supply falling(4)
2.48
2.6
Input voltage rising
170
mV
VIN_LS2 = 5 V, IOUT = 500 mA, over full temperature
range
RDS(ON)
Static on resistance
500
mΩ
LS2ILIM[1:0] = 00b
94
188
465
922
126
251
LS2ILIM[1:0] = 01b
LS2ILIM[1:0] = 10b
LS2ILIM[1:0] = 11b
Output shorted to GND; VIN_LS2
≥4 V
ILIMIT
Short circuit current limit
mA
631
1290
ILEAK
Reverse leakage current
Interrupt blanking time
VLS2 > VIN_LS2 + 1 V
12
15
30 µA
ms
tBLANK
Output shorted to GND until interrupt is triggered
LS2DCHRG = 1b
Internal discharge resistor at
output(2)
RDIS
TOTS
COUT
150
125
250
380
139
Ω
Overtemperature shutdown(4)
132
10
°C
Hysteresis
Nominal output capacitance
value
1
100 µF
Ceramic, X5R or X7R, see 表9-3.
LOAD SWITCH 3 (LS3)
VIN_LS3 Input voltage range
VIN_BIAS > VUVLO
1.8
10
V
VIN_LS3 = 9 V, IOUT= 500 mA, over full temperature
range
440
VIN_LS3 = 5 V, IOUT= 500 mA, over full temperature
range
526
656
910
RDS(ON)
Static on resistance
mΩ
VIN_LS3 = 2.8 V, IOUT= 200 mA, over full temperature
range
VIN_LS3 = 1.8 V, IOUT= 200 mA, over full temperature
range
LS3ILIM[1:0] = 00b
98
194
475
900
98
126
253
738
LS3ILIM[1:0] = 01b
LS3ILIM[1:0] = 10b
LS3ILIM[1:0] = 11b
LS3ILIM[1:0] = 00b
LS3ILIM[1:0] = 01b
LS3ILIM[1:0] = 10b
VIN_LS3 > 2.3 V,
Output shorted to GND
ILIMIT
Short circuit current limit
Interrupt blanking time
1234 mA
126
V
IN_LS3 ≤2.3 V,
194
475
253
Output shorted to GND
738
tBLANK
RDIS
Output shorted to GND until interrupt is triggered.
LS3DCHRG = 1
15
ms
Internal discharge resistor at
output(2)
650
125
1000
1500
Ω
Overtemperature shutdown(4)
132
10
139 °C
°C
TOTS
Hysteresis
Nominal output capacitance
value
COUT
1
100
220 µF
Ceramic, X5R or X7R, see 表9-3.
BACKUP BATTERY MONITOR
Ideal level
Good level
Low level
3
2.6
2.3
V
Comparator threshold
VTH
V
V
Accuracy
3%
–3%
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MAX UNIT
7.5 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
RLOAD
tDLY
Load impedance
Applied from CC to GND during comparison.
70
100
130
kΩ
RLOAD is connected during delay time. Measurement
is taken at the end of delay.
Measurement delay
600
ms
I/O LEVELS AND TIMING CHARACTERISTICS
PGDLY[1:0] = 00b
PGDLY[1:0] = 01b
PGDLY[1:0] = 10b
PGDLY[1:0] = 11b
10
20
50
150
100
50
100
10
10
100
1
PGDLY
PGOOD delay time
ms
Rising edge
ms
ms
µs
PB input
Falling edge
Rising edge
AC_DET input
Falling edge
ms
ms
µs
Rising edge
PWR_EN input
tDG
Deglitch time
Falling edge
Rising edge
ms
ms
µs
GPIO1
Falling edge
1
Rising edge
5
GPIO3
Falling edge
5
µs
TRST = 0b
PB input held low
8
tRESET
Reset time
s
TRST = 1b
15
SCL, SDA, GPIO1, and GPIO3
AC_DET, PB
1.3
0.66 ×
IN_BIAS
VIH
High level input voltage
V
PWR_EN
1.3
0
SCL, SDA, PWR_EN, AC_DET, PB, GPIO1, and
GPIO3
VIL
Low level input voltage
High level output voltage
0.4
V
V
VIN_LS1
–0.3
GPO2; ISOURCE = 5 mA; GPO2_BUF = 1
PGOOD_BU; ISOURCE = 100 µA
VIN_LS1
VOH
VDCDC6
–10 mV
nWAKEUP, nINT, SDA, PGOOD, GPIO1, GPO2, and
GPIO3; ISINK = 2 mA
0
0.3
VOL
Low level output voltage
V
nPFO; ISINK = 2 mA
0
0
0.35
0.3
PGOOD_BU; ISINK = 100 µA
Power-fail comparator threshold Input falling
800
40
mV
mV
Hysteresis
Accuracy
Input rising
VPFI
4%
–4%
Input falling
25
10
10
µs
Deglitch
Input rising
ms
IDC34_SEL
DC34_SEL bias current
Enabled only at power-up.
9.05
11.93 µA
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7.5 Electrical Characteristics (continued)
Over operating free-air temperature range (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
100
163
275
400
575
825
1200
0
MAX UNIT
Threshold 1
Threshold 2
Threshold 3
DCDC3 and DCDC4 power-up
default selection thresholds
VDC34_SEL
Threshold 4
mV
Threshold 5
Threshold 6
Threshold 7
Setting 0
0
11.8
19.5
30.9
44.4
64.8
93.6
146
7.7
12.4
20.5
Setting 1
12.1
20
Setting 2
Setting 3
31.6
45.3
66.1
95.3
150
0.01
32.3
kΩ
DCDC3 and DCDC4 power-up
default selection resistor values
RDC34_SEL
Setting 4
46.3
Setting 5
67.3
97.2
Setting 6
Setting 7
SCL, SDA, GPIO1(5), GPIO3 (5); VIN = 3.3 V
1
µA
IBIAS
Input bias current
PB, AC_DET, PFI; VIN = 3.3 V
500 nA
nINT, nWAKEUP, nPFO, PGOOD, PWR_EN,
GPIO1(6), GPO2(7), GPIO3(6)
VOUT = 3.3 V
ILEAK
Pin leakage current
500 nA
OSCILLATOR
Oscillator frequency
Frequency accuracy
2400
kHz
ƒOSC
12%
TJ = –40°C to +105°C
–12%
135
OVERTEMPERATURE SHUTDOWN
Overtemperature shutdown
Increasing junction temperature
Decreasing junction temperature
Increasing junction temperature
Decreasing junction temperature
145
20
155
°C
TOTS
Hysteresis
High-temperature warning
90
100
15
110
°C
TWARN
Hysteresis
(1) IN_BU has priority over CC input.
(2) Discharge function disabled by default.
(3) Switch is temporarily turned OFF if temperature exceeds OTS threshold.
(4) Switch is temporarily turned OFF if input voltage drops below UVLO threshold.
(5) Configured as input.
(6) Configured as output.
(7) Configured as open-drain output.
(8) 500-µF of remote capacitance can be supported for DCDC1 and DCDC2.
(9) For PHP package: 160 mVpp at -40°C, and 120 mVpp from 25°C to 105°C.
(10) For PHP package: 40 µF.
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7.6 Timing Requirements
MIN
NOM
100
MAX
UNIT
fSCL
Serial clock frequency
kHz
400
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz(1)
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
SCL = 100 kHz
SCL = 400 kHz
4
600
4.7
1.3
4
µs
ns
Hold time (repeated) START condition. After this period, the
first clock pulse is generated.
tHD;STA
tLOW
LOW period of the SCL clock
HIGH period of the SCL clock
µs
µs
tHIGH
1
4.7
600
0
µs
ns
µs
ns
tSU;STA Set-up time for a repeated START condition
tHD;DAT Data hold time
3.45
900
0
250
100
tSU;DAT Data set-up time
ns
ns
ns
1000
300
300
300
tr
tf
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
4
600
4.7
µs
ns
tSU;STO Set-up time for STOP condition
tBUF
tSP
Cb
Bus free time between STOP and START condition
µs
ns
pF
1.3
(2)
(2)
—
—
Pulse width of spikes which must be suppressed by the input
filter
0
50
400
400
Capacitive load for each bus line
(1) The SCL duty cycle at 400 kHz must be > 40%.
(2) The inputs of I2C devices in Standard-mode do not require spike suppression.
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7.7 Typical Characteristics
At TJ = 25°C unless otherwise noted.
0.3%
0.25%
0.2%
0.15%
0.1%
VIN = 3.6 V
VIN = 5 V
VIN = 3.6 V
VIN = 5 V
0.05%
0
0.15%
0.1%
-0.05%
-0.1%
-0.15%
-0.2%
-0.25%
-0.3%
-0.35%
-0.4%
-0.45%
-0.5%
-0.55%
0.05%
0
-0.05%
-0.1%
-0.15%
-0.2%
-0.25%
-0.3%
-0.35%
-0.4%
0
0
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
1.8
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
1.8
D002
D001
VOUT = 1.1 V
VOUT = 1.1 V
图7-2. DCDC2 Accuracy
图7-1. DCDC1 Accuracy
0.1%
0.05%
0
0.75%
0.5%
VIN = 3.6 V
VIN = 5 V
VIN = 3.6 V
VIN = 5 V
0.25%
0
-0.05%
-0.1%
-0.15%
-0.2%
-0.25%
-0.25%
-0.5%
-0.75%
-1%
-1.25%
0
0.2
0.4
0.6 0.8
Output Current (A)
1
1.2
1.4
1.6
1.8
0.2
0.4
0.6
Output Current (A)
0.8
1
1.2
1.4
1.6
D003
D004
VOUT = 1.2 V
VOUT = 3.3 V
图7-3. DCDC3 Accuracy
图7-4. DCDC4 Accuracy
1.4%
1.2%
1%
0.05%
0
VIN = 3.6 V
VIN = 5 V
VIN = 3.6 V
VIN = 5 V
-0.05%
-0.1%
-0.15%
-0.2%
-0.25%
-0.3%
-0.35%
-0.4%
-0.45%
-0.5%
-0.55%
-0.6%
0.8%
0.6%
0.4%
0.2%
0
-0.2%
-0.4%
-0.6%
-0.8%
0.005
0.01 0.015
Output Current (A)
0.02
0.025
0
0.005
0.01 0.015
Output Current (A)
0.02
0.025
D006
D005
VOUT = 1.8 V
VOUT = 1 V
图7-6. DCDC6 Accuracy
图7-5. DCDC5 Accuracy
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8 Detailed Description
8.1 Overview
The TPS6521815 provides three step-down converters, three load switches, three general-purpose I/Os, two
battery backup supplies, one buck-boost converter, and one LDO. The system can be supplied by a regulated 5-
V supply. A coin-cell battery can be added to supply the two always-on backup supplies. The device is
characterized across a –40°C to +105°C temperature range, which makes it suitable for various industrial
applications.
The I2C interface provides comprehensive features for using TPS6521815. All rails, load switches , and GPIOs
can be enabled and disabled. Voltage thresholds for the UVLO and supervisor can be customized. Power-up
and power-down sequences can also be programmed through I2C. Interrupts for overtemperature, overcurrent,
and undervoltage can be monitored for the load-switches (LSx).
The integrated voltage supervisor monitors DCDC 1-4 and LDO1. It has two settings; the standard settings only
monitor for undervoltage, while the strict settings implement tight tolerances on both undervoltage and
overvoltage. A power-good signal is provided to report the regulation state of the five rails.
The three hysteretic step-down converters can each supply up to 1.8 A of current. The default output voltages for
each converter can be adjusted through the I2C interface. DCDC1 and DCDC2 features dynamic voltage scaling
with an adjustable slew rate. The step-down converters operate in a low power mode at light load, and can be
forced into power mode (PWM) operation for noise sensitive applications.
The battery backup supplies consist of two low power step-down converters optimized for very light loads and
are monitored with a separate power-good signal (PGOOD_BU). The converters can be configured to operate as
always-on supplies with the addition of a coin cell battery. The state of the battery can be monitored over I2C.
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8.2 Functional Block Diagram
VDD_10 (1 V)
Battery-backup
domain supply
10 µH
L5
DCDC6 (1.8 V)
PGOOD_BU
To SOC
DCDC5_PG
DCDC6_PG
FB5
22 …F
22 …F
DCDC5
DCDC6
DCDC6 (1.8 V)
VDD_18 (1.8 V)
Battery-backup
domain supply
IN_nCC
To SOC
10 µH
L6
FB6
IN_BU
2.7-V to 5.5-V
system power
10 ꢀ
CC
SYS_BU
Coin
cell
+
1 …F
4.7 …F
œ
4.7 …F
Always-on coin-cell battery backup supplies
IN_LDO1
LDO1
IN_LS2
LS2
From 1.8-V to 5.5-V
supply
From 3-V to 5.5-V
supply
100-mA / 500-mA
load switch
0.9-V to 3.3-V analog supply
(adjustable, default 1.8 V)
LDO1
LS1
LS2
10 …F
10 …F
IN_LS1
LS1
IN_LS3
LS3
From 1.2-V to 3.3-V
supply
From 1.8-V to 10-V
supply
500-mA load
switch
LS3
200-mA load switch
10 …F
10 …F
IN_DCDC3
IN_DCDC1
From 2.7-V to 5.5-V
system power
From 2.7-V to 5.5-V
system power
4.7 …F
10 …F
4.7 …F
10 …F
10 µH
L1
L3
1.5-V DDR3 supply
(adjustable)
1.1-V core supply
(adjustable)
FB3
FB1
DCDC3
DCDC1
IN_DCDC4
L4A
IN_DCDC2
From 2.7-V to 5.5-V
system power
From 2.7-V to 5.5-V
system power
4.7 …F
4.7 …F
10 …F
10 µH
L2
1.1-V MPU supply
(adjustable)
L4B
FB2
DCDC4
DCDC2
BIAS
DCDC4
3.3-V I/O supply
(adjustable)
IN_BIAS
From 2.7-V to 5.5-V
system power
100 nF
47 …F
INT_LDO
DC34_SEL
VSELECT
VDCDC1
1 …F
Supervisor
VDCDC2
and up,
VDCDC3
VIO
(1.8 V /
3.3 V)
VIO
(1.8 V /
3.3 V)
VIO
(1.8 V /
3.3 V)
VDD_18
(DCDC6)
down
sequencer
VDCDC4
Input Power
LDO1
nPFO
OD
To SOC
To SOC
PFI
+
PGOOD
OD
VREF
œ
VIO
VIO
10 ꢀ
10 ꢀ
nWAKEUP
nINT
SCL
SDA
OD
To SOC
To SOC
From SOC
I2C
OD
From SOC
From SOC
DIGITAL
PWR_EN
GPIO1
100 kꢀ
From SOC
OD
IN_LS1
IN_BIAS
100 kꢀ
To DDR3 memory
GPIO2
GPIO3
OD
AC_DET
From external
charger
IN_BIAS
100 kꢀ
Momentary push-button
PB
From SOC
OD
Thermal
Pad
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8.3 Feature Description
8.3.1 Wake-Up and Power-Up and Power-Down Sequencing
The TPS6521815 has a predefined power-up and power-down sequence, which does not change in a typical
application. The user can define custom sequences with I2C. The power-up sequence is defined by a series of
ten strobes and nine delay times. Each output rail is assigned to a strobe to determine the order of enabling
rails. A single rail is assigned to only one strobe, but multiple rails can be assigned to the same strobe. The
delay times between strobes are between 2 ms and 5 ms.
8.3.1.1 Power-Up Sequencing
When the power-up sequence initiates, STROBE 1 occurs, and any rail assigned to this strobe is enabled. After
a delay time of DLY1, STROBE 2 occurs and the rail assigned to this strobe is powered up. The sequence
continues until all strobes occur and all DLYx times execute. Strobe assignments and delay times are defined in
the SEQx registers, and are changed under I2C control. The power-up sequence executes if one of the following
events occurs:
• From the OFF state:
– The push-button (PB) is pressed (falling edge on PB) or
– The AC_DET pin is pulled low (falling edge) or
– The PWR_EN is asserted (driven to high-level) or
– The main power is connected (IN_BIAS) and AC_DET is grounded and
– The device is not in undervoltage lockout (UVLO) or overtemperature shutdown (OTS).
• From the PRE_OFF state:
– The PB is pressed (falling edge on PB) or
– The AC_DET pin is pulled low (falling edge) or
– The PWR_EN is asserted (driven to high-level) and
– The device is not in UVLO or OTS.
• From the SUSPEND state:
– The PB is pressed (falling edge on PB) or
– The AC_DET pin is pulled low (falling edge) or
– The PWR_EN pin is pulled high (level sensitive) and
– The device is not in UVLO or OTS.
When a power-up event is detected, the device enters a WAIT_PWR_EN state and triggers the power-up
sequence. The device remains in WAIT_PWR_EN as long as the PWR_EN and either the PB or AC_DET pin
are held low. If both, the PB and AC_DET return to logic-high state and the PWR_EN pin has not been asserted
within 20 s of entering WAIT_PWR_EN state, the power-down sequence is triggered and the device returns to
OFF state. Once PWR_EN is asserted, the device advances to ACTIVE state, which is functionally equivalent to
WAIT_PWR_EN. However, the AC_DET pin is ignored and power-down is controlled by the PWR_EN pin only.
Rails not assigned to a strobe (SEQ = 0000b) are not affected by power-up and power-down sequencing and
remain in their current ON or OFF state regardless of the sequencer. A rail can be enabled and disabled at any
time by setting the corresponding enable bit in the ENABLEx register, with the exception that the ENABLEx
register cannot be accessed while the sequencer is active. Enable bits always reflect the current enable state of
the rail. For example, the sequencer sets and resets the enable bits for the rails under its control.
Note
The power-up sequence is defined by strobes and delay times, and can be triggered by the PB,
AC_DET (not shown, same as PB), or PWR_EN pin.
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PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY1
DLY2
DLY3
DLY4
DLY5
DLY6
DLY7
DLY8
DLY9
STROBE 1
STROBE 2
STROBE 3
STROBE 4
STROBE 5
STROBE 6
STROBE 7
SEQ = 0001b SEQ = 0010b SEQ = 0011b SEQ = 0100b SEQ = 0101b SEQ = 0110b SEQ = 0111b SEQ = 1000b SEQ = 1001b SEQ = 1010b
STROBE 8
STROBE 9 STROBE 10
Push-button deglitch time is not shown.
图8-1. Power-Up Sequences from OFF or SUSPEND State; PB is Power-Up Event
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY1
DLY2
DLY3
DLY4
DLY5
DLY6
DLY7
DLY8
DLY9
STROBE 1
STROBE 2
STROBE 3
STROBE 4
STROBE 5
STROBE 6
STROBE 7
SEQ = 0001b SEQ = 0010b SEQ = 0011b SEQ = 0100b SEQ = 0101b SEQ = 0110b SEQ = 0111b SEQ = 1000b SEQ = 1001b SEQ = 1010b
STROBE 8
STROBE 9 STROBE 10
图8-2. Power-Up Sequences from SUSPEND State; PWR_EN is Power-Up Event
FAULT Recovery
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY1
DLY2
DLY3
DLY4
DLY5
DLY6
DLY7
DLY8
DLY9
STROBE 1
STROBE 2
STROBE 3
STROBE 4
STROBE 5
STROBE 6
STROBE 7
SEQ = 0001b SEQ = 0010b SEQ = 0011b SEQ = 0100b SEQ = 0101b SEQ = 0110b SEQ = 0111b SEQ = 1000b SEQ = 1001b SEQ = 1010b
STROBE 8
STROBE 9 STROBE 10
图8-3. Power-Up Sequences from RECOVERY State
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8.3.1.2 Power-Down Sequencing
By default, the power-down sequence follows the reverse of the power-up sequence. When the power-down
sequence is triggered, STROBE 10 occurs and any rail assigned to STROBE 10 is shut down and its discharge
circuit is enabled. After a delay time of DLY9, STROBE 9 occurs and any rail assigned to it is shut down and its
discharge circuit is enabled. The sequence continues until all strobes occur and all DLYx times execute. The
DLYx times are extended by a factor of 10x to provide ample time for discharge, and preventing output voltages
from crossing during shut-down. The DLYFCTR bit is applied globally to all power-down delay times. Regardless
of the DLYx and DLYFCTR settings, the PMIC enters OFF, SUSPEND, or RECOVERY state 500 ms after the
power-down sequence initiates, to ensure that the discharge circuits remain enabled for a minimum of 150 ms
before the next power-up sequence starts.
A power-down sequence executes if one of the following events occurs:
• The device is in the WAIT_PWR_EN state, the PB and AC_DET pins are high, PWR_EN is low, and the 20-s
timer has expired.
• The device is in the ACTIVE state and the PWR_EN pin is pulled low.
• The device is in the WAIT_PWR_EN, ACTIVE, or SUSPEND state and the push-button is held low for > 8 s
(15 s if TRST = 1b).
• A fault occurs in the device (OTS, UVLO, PGOOD failure).
When transitioning from ACTIVE to SUSPEND state, the rails not controlled by the power-down sequencer
maintains the same ON/OFF state in SUSPEND state that it had in ACTIVE state. This allows for the selected
power rails to remain powered up when in the SUSPEND state.
When transitioning to the OFF or RECOVERY state, rails not under sequencer control are shut-down as follows:
• DCDC1, DCDC2, DCDC3, DCDC4, LDO1, and LS1 shut down at the beginning of the power-down
sequence, if not under sequencer control (SEQ = 0b).
• LS2 and LS3 shut down as the state machine enters an OFF or RECOVERY state; 500 ms after the power-
down sequence is triggered.
If the supply voltage on IN_BIAS drops below 2.5 V, the digital core is reset and all power rails are shut down
instantaneously and are pulled low to ground by their internal discharge circuitry (DCDC1-4, and LDO1). The
amount of time the discharge circuitry remains active is a function of the INT_LDO hold up time (see 节 8.3.1.6
for more details).
8.3.1.3 Strobe 1 and Strobe 2
STROBE 1 and STROBE 2 are dedicated to DCDC5 and DCDC6 which are always-on; powered up as soon as
the device exits the OFF state, and ON in any other state. STROBE 1 and STROBE 2 options are available only
for DCDC5 and DCDC6, not for any other rails.
STROBE 1 and STROBE 2 occur in every power-up sequence, regardless if the rail is already powered up. If the
rail is not to be powered up, its respective strobe setting must be set to 0x00.
When a power-down sequence initiates, STROBE 1 and STROBE 2 occur only if the FSEAL bit is 0b.
Otherwise, both strobes are omitted and DCDC5 and DCDC6 maintain state.
Note
The power-down sequence follows the reverse of the power-up sequence. STROBE2 and STROBE1
are executed only if FSEAL bit is 0b.
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PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY9
DLY8
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
STROBE 10 STROBE 9
STROBE 8
STROBE 7
STROBE 6
STROBE 5
STROBE 4
STROBE 3
SEQ = 1010b SEQ = 1001b SEQ = 1000b SEQ = 0111b SEQ = 0110b SEQ = 0101b SEQ = 0100b SEQ = 0011b SEQ = 0010b SEQ = 0001b
STROBE 2
STROBE 1
图8-4. Power-Down Sequences to OFF State; PWR_EN is Power-Down Event; FSEAL = 0b
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY9
DLY8
DLY7
DLY6
DLY5
DLY4
DLY3
STROBE 10 STROBE 9
STROBE 8
STROBE 7
STROBE 6
STROBE 5
SEQ = 1010b SEQ = 1001b SEQ = 1000b SEQ = 0111b SEQ = 0110b SEQ = 0101b SEQ = 0100b SEQ = 0011b
STROBE 4
STROBE 3
STROBE2 and STROBE1 are not shown.
图8-5. Power-Down Sequences to SUSPEND State; PWR_EN is Power-Down Event; FSEAL = 1b
PB (input)
nWAKEUP
(output)
PWR_EN
(input)
DLY9
DLY8
DLY7
DLY6
DLY5
DLY4
DLY3
STROBE 10 STROBE 9
STROBE 8
STROBE 7
STROBE 6
STROBE 5
SEQ = 1010b SEQ = 1001b SEQ = 1000b SEQ = 0111b SEQ = 0110b SEQ = 0101b SEQ = 0100b SEQ = 0011b
STROBE 4
STROBE 3
STROBE2 and STROBE1 are not shown.
图8-6. Power-Down Sequences to RECOVERY State; TSD or UV is Power-Down Event; FSEAL = 1b
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8.3.1.4 Supply Voltage Supervisor and Power-Good (PGOOD)
Power-good (PGOOD) is an open-drain output of the built-in voltage supervisor that monitors DCDC1, DCDC2,
DCDC3, DCDC4, and LDO1. The output is Hi-Z when all enabled rails are in regulation and driven low when one
or more rails encounter a fault which brings the output voltage outside the specified tolerance range. In a typical
application PGOOD drives the reset signal of the SOC.
The supervisor has two modes of operation, controlled by the STRICT bit. With the STRICT bit set to 0, all
enabled rails of the five regulators are monitored for undervoltage only with relaxed thresholds and deglitch
times. With the STRCT bit set to 1, all enabled rails of the five regulators are monitored for undervoltage and
overvoltage with tight limits and short deglitch times. 表8-1 summarizes these details.
表8-1. Supervisor Characteristics Controlled by the STRICT Bit
PARAMETER
STRICT = 0b (TYP)
STRICT =1b (TYP)
96.5% (DCDC1 and DCDC2)
95.5% (DCDC3, DCDC4, and LDO1)
Threshold (output falling)
90%
Undervoltage
monitoring
Deglitch (output falling)
Deglitch (output rising)
1 ms
50 µs
10 µs
10 µs
103.5% (DCDC1 and DCDC2)
104.5% (DCDC3, DCDC4, and
LDO1)
Threshold (output falling)
N/A
Overvoltage
monitoring
Deglitch (output falling)
Deglitch (output rising)
N/A
N/A
1 ms
50 µs
Overvoltage threshold
(output rising)
LDO1
Hysteresis
Undervoltage threshold
(output falling)
Hysteresis
Power-good comparator
output (internal signal)
Voltage droop has no effect on
PGOOD output if duration is
less than deglitch time.
Voltage droop has no effect on
PGOOD output if duration is
less than deglitch time.
PGOOD
Deglitch time
图8-7. Definition of Undervoltage, Overvoltage Thresholds, Hysteresis, and Deglitch Times
The following rules apply to the PGOOD output:
• The power-up default state for THE PGOOD is low. When all rails are disabled, the PGOOD output is driven
low.
• Only enabled rails are monitored. Disabled rails are ignored.
• Power-good monitoring of a particular rail starts 5 ms after the rail is enabled and is continuously monitored
thereafter. This allows the rail to power-up.
• The PGOOD is delayed by PGDLY time after the sequencer is finished and the last rail is enabled.
• If an enabled rail is continuously outside the monitoring threshold for longer than the deglitch time, then the
PGOOD is pulled low, and all rails are shut-down following the power-down sequence. PGDLY does not
apply.
• Disabling a rail manually by resetting the DCx_EN or LDO1_EN bit has no effect on the PGOOD pin. If all
rails are disabled, the PGOOD is driven low as the last rail is disabled.
• If the power-down sequencer is triggered, PGOOD is driven low.
• The PGOOD is driven low in the SUSPEND state, regardless of the number of rails that are enabled.
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图8-8 shows a typical power-up sequence and PGOOD timing.
VSYS
5 s (maximum)
PB
nWAKEUP
PWR_EN
(deglitched)
DLY1 + DLY2
LDO1
5 ms
DLY4 + DLY3
PG LDO1
(internal)
FAULT
DLY3 + DLY4
DCDC3
5 ms
DLY6 + DLY5
DLY7
PG DCDC3
(internal)
DLY5 + DLY6
DCDC4
5 ms
PG DCDC4
(internal)
DLY7
DCDC1
5 ms
DLY8
PG DCDC1
(internal)
DLY8
DCDC2
5 ms
DLY9
PG DCDC2
(internal)
PG_DLY
PGOOD
A. Sequence shown for TPS65218D0 variant. For other TPS65218xx variants, refer to registers SEQ1-7 in 节8.6.4 for factory-
programmed sequence order and timing.
图8-8. Typical Power-Up Sequence of the Main Output Rails for TPS65218D0
8.3.1.5 Backup Supply Power-Good (PGOOD_BU)
PGOOD_BU is a push-pull output indicating if DCDC5 and DCDC6 are in regulation. The output is driven to high
when both rails are in regulation, and driven low if at least one of the rails is below the power-good threshold.
The output-high level is equal to the output voltage of DCDC6.
PGOOD_BU is the logical and between PGOOD (DCDC5) and PGOOD (DCDC6), and has no delay time built-
in. Unlike the main power-good, a fault on DCDC5 or DCDC6 does not trigger the power-down sequencer, does
not disable any of the rails in the system, and has no effect on the PGOOD pin. DCDC5 and DCDC6 recover
automatically once the fault is removed.
Note
In this example, the power-down is triggered by a fault on DCDC3.
This timing diagram assumes each rail powers up within the strobe delay time. If a rail takes longer
than the strobe delay time to power up, the next rail will wait for the previous rail to reach its PGOOD
voltage, and then may wait an additional 1 ms until it is enabled.
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VSYS
5 s (maximum)
PB
nWAKEUP
PWR_EN
(deglitched)
DCDC6
PG DCDC6
(internal)
DLY1
DCDC5
PG DCDC5
(internal)
PGOOD_BU
A. Sequence shown for TPS65218D0 and TPS6521825 variants. For TPS6521815 variant, order and timing of DCDC5 and DCDC6 can
be modified using registers SEQ1-2 and SEQ5 in 节8.6.4 .
图8-9. Typical Power-Up Sequence of DCDC5 and DCDC6
8.3.1.6 Internal LDO (INT_LDO)
The internal LDO provides a regulated voltage to the internal digital core and analog circuitry. The internal LDO
has a nominal output voltage of 2.5 V and can support up to 10 mA of external load. During EEPROM
programming, the output voltage is elevated to 3.6 V as described in 节 8.5.1. Therefore, any external circuitry
connected to INT_LDO must be capable of supporting that voltage.
When system power fails, the UVLO comparator triggers the power-down sequence. If system power drops
below 2.3 V, the digital core is reset and all remaining power rails are shut down instantaneously and are pulled
low to ground by their internal discharge circuitry (DCDC1-4 and LDO1).
The internal LDO reverse blocks to prevent the discharging of the output capacitor (CINT_LDO) on the INT_LDO
pin. The remaining charge on the INT_LDO output capacitor provides a supply for the power rail discharge
circuitry to ensure the outputs are discharged to ground even if the system supply has failed. The amount of
hold-up time specified in 节 7.5 is a function of the output capacitor value (CINT_LDO) and the amount of external
load on the INT_LDO pin, if any. The design allows for enough hold-up time to sufficiently discharge DCDC1-4,
and LDO1 to ensure proper processor power-down sequencing.
IN_BIAS
INT_LDO
From
system
power
1 …F
UVLO
RESET
Digital Core
Power-Rail
Discharge Circuitry
EEPROM
图8-10. Internal LDO and UVLO Sensing
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8.3.1.7 Current Limited Load Switches
The TPS6521815 provides three current limited load switches with individual inputs, outputs, and enable control.
Each switch provides the following control and diagnostic features:
• The ON or OFF state of the switch is controlled by the corresponding LSx_EN bit in the ENABLE register.
• LS1 can be controlled by the sequencer or through I2C communication.
• LS2 and LS3 can only be controlled through I2C communication. The sequencer has no control over LS2 and
LS3.
• Each switch has an active discharge function, disabled by default, and enabled through the LSxDCHRG bit.
When enabled, the switch output is discharged to ground whenever the switch is disabled.
• When the PFI input drops below the power-fail threshold (the power-fail comparator trips), the load switches
are automatically disabled to shed system load. This function must be individually enabled for each switch
through the corresponding LSxnPFO bit. The switches do not turn back on automatically as the system
voltage recovers, and must be manually re-enabled.
• An interrupt (LSx_I) issues whenever a load switch actively limits the output current, such as when the output
load exceeds the current limit value. The switch remains ON and provides current to the load according to the
current-limit setting.
• All three load switches have local overtemperature sensors which disable the corresponding switch if the
power dissipation and junction temperature exceeds the safe operating value. The switch automatically
recovers once the temperature drops below the OTS threshold value minus hysteresis. The LSx_F (fault)
interrupt bit is set while the switch is held OFF by the OTS function.
8.3.1.7.1 Load Switch 1 (LS1)
LS1 is a non-reverse blocking, low-voltage (< 3.6 V), low-impedance switch intended to support DDRx self-
refresh mode by cutting off the DDRx supply to the SOC DDRx interface during SUSPEND mode. In a typical
application, the input of LS1 is tied to the output of DCDC3 while the output of LS1 is connected to the memory-
interface supply pin of the SOC. LS1 can be controlled by the internal sequencer, just as any power rail.
LS1_EN
LS1DIS
LS1nPFO
SOC
IN_LS1
LS1
DDR Memory
Interface
From DCDC3
10 …F
250 ꢀ
LS1_I
LS1_F
图8-11. Typical Application of Load Switch 1
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8.3.1.7.2 Load Switch 2 (LS2)
LS2 is a reverse-blocking, 5 V, low-impedance switch. Load switch 2 provides four different current limit values
(100/200/500/1000 mA) that are selectable through LS2ILIM[1:0] bits. Overcurrent is reported through the LS2_I
interrupt.
LS2 has its own input-undervoltage protection which forces the switch OFF if the switch input voltage (VIN_LS2) is
<2.7 V. Similar to OTS, the LS2_F interrupt is set when the switch is held OFF by the local UVLO function, and
the switch recovers automatically when the input voltage rises above the UVLO threshold.
LS2_EN
LS2DIS
LS2nPFO
LS2ILIM[1:0]
IN_LS2
LS2
+5 V
GND
5-V boost
0.1 …F
120 …F
5-V
Port
250 ꢀ
LS2_I
LS2_F
图8-12. Typical Application of Load Switch 2
8.3.1.7.3 Load Switch 3 (LS3)
LS3 is a non-reverse blocking, medium-voltage (< 10 V), low-impedance switch that can be used to provide 1.8-
V to 10-V power to an auxiliary port. LS3 has four selectable current limit values that are selectable through
LS3ILIM[1:0].
LS3_EN
LS3DIS
LS3nPFO
LS3ILIM[1:0]
IN_LS3
LS3
VPORT
GND
From any
1.8-V to 10-V supply
0.1 …F
120 …F
AUX
Port
250 ꢀ
LS3_I
LS3_F
图8-13. Typical Application of Load Switch 3
8.3.1.8 LDO1
LDO1 is a general-purpose LDO intended to provide power to analog circuitry on the SOC. LDO1 has an input
voltage range from 1.8 V to 5.5 V, and can be connected either directly to the system power or the output of a
DCDC converter. The output voltage is programmable in the range of 0.9 V to 3.4 V with a default of 1.8 V. LDO1
supports up to 200 mA at the minimum specified headroom voltage, and up to 400 mA at the typical operating
condition of VOUT = 1.8 V, VIN_LDO1 > 2.7 V.
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8.3.1.9 Coin Cell Battery Voltage Acquisition
CC
10 ꢀ
LOW (2.3 V)
+
DISABLED
+
Coin Cell
VREF
GOOD (2.6 V)
VREF
œ
œ
CC_AQ = 1
+
œ
Enable 100-kꢀ load resistor on CC
input.
Enable comparators.
CC_STAT[1:0]
IDEAL (3 V)
VREF
LOGIC CORE
+
œ
Wait 600 ms
LOAD ENABLE
Latch comparator outputs;
Store result in CC_STAT[1:0]
CC_STAT[1:0] = 00b œ VCC < VLOW; Coin cell is not present or at end-of-life (EOL).
CC_STAT[1:0] = 01b œ VLOW < VCC < VGOOD; Coin cell is LOW.
CC_STAT[1:0] = 10b œ VGOOD < VCC < VIDEAL; Coin cell is GOOD.
CC_STAT[1:0] = 11b œ VIDEAL < VCC; Coin cell voltage is IDEAL.
Disable 100-kꢀ load resistor.
Disable comparators
Restore CC_AQ bit to 0 (CC_AQ = 0)
Issue interrupt (CC_AQC = 1)
图8-14. Left: Flow Chart for Acquiring Coin Cell Battery Voltage Right: Comparator Circuit
8.3.1.10 UVLO
Depending on the slew rate of the input voltage into the IN_BIAS pin, the power rails of TPS6521815 will be
enabled at either VULVO or VULVO + VHYS
.
If the slew rate of the IN_BIAS voltage is greater than 30 V/s, then TPS6521815 will power up at VULVO. Once
the input voltage rises above this level, the input voltage may drop to the VUVLO level before the PMIC shuts
down. In this scenario, if the input voltage were to fall below VUVLO but above 2.55 V, the input voltage would
have to recover above VUVLO in less than 5 ms for the device to remain active.
If the slew rate of the IN_BIAS voltage is less than 30 V/s, then TPS6521815 will power up at VULVO + VHYS
.
Once the input voltage rises above this level, the input voltage may drop to the VUVLO level before the PMIC
shuts down. In this scenario, if the input voltage were to fall below VUVLO but above 2.5 V, the input voltage
would have to recover above VUVLO + VHYS in less than 5 ms for the device to remain active.
In either slew rate scenario, if the input voltage were to fall below 2.5 V, the digital core is reset and all remaining
power rails are shut down instantaneously and are pulled low to ground by their internal discharge circuitry
(DCDC1-4 and LDO1).
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UVLO hysteresis
UVLO threshold, supply falling
< 5 ms
VIN_BIAS
UVLO active
UVLO (internal signal)
UVLO inactive
> 5-ms
deglitch
图8-15. Definition of UVLO and Hysteresis
After the UVLO triggers, the internal LDO blocks current flow from its output capacitor back to the IN_BIAS pin,
allowing the digital core and the discharge circuits to remain powered for a limited amount of time to properly
shut-down and discharge the output rails. The hold-up time is determined by the value of the capacitor
connected to INT_LDO. See 节8.3.1.6 for more details.
8.3.1.11 Power-Fail Comparator
The power-fail comparator notifies the system host if the system supply voltage drops and the system is at risk of
shutting down. The comparator has an internal 800-mV threshold and the trip-point is adjusted by an external
resistor divider.
By default, the power-fail comparator has no impact on any of the power rails or load switches. Load switches
are configured individually, to be disabled when the PFI comparator trips to shed system load and extend hold-
up time as described in 节8.3.1.7. The power-fail comparator also triggers the power-down sequencer, such that
all or selective rails power-down when the system voltage fails. To tie the power-fail comparator into the power-
down sequence, the OFFnPFO bit in the CONTROL register must be set to 1.
The power-fail comparator cannot be monitored by software, such that no interrupt or status bit is associated to
this function.
System supply voltage
nPFO
PFI
+
Deglitch
VREF
(800 mV)
œ
PFI hysteresis
PFI threshold, supply falling
<25 µs
VPFI
nPFO inactive
nPFO (pin)
nPFO active
10-ms deglitch
25-µs deglitch
图8-16. Power-Fail Comparator Simplified Circuit and Timing Diagram
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8.3.1.12 Battery-Backup Supply Power-Path
DCDC5 and DCDC6 are supplied from either the CC (coin-cell battery) input or IN_BU (main system supply).
The power-path is designed to prioritize IN_BU to maximize coin-cell battery life. Whenever the PMIC is
powered-up (WAIT_PWR_EN, ACTIVE, SUSPEND, and RECOVERY state), the power-path is forced to select
the IN_BU input. In OFF mode the power-path selects the higher of the two inputs with a built-in hysteresis of
150 mV as shown in 图8-17.
VIN_BU
VSYS_BU
VINT_LDO
VIN_BU,
VSYS_BU
VCC
VCC
VINT_LDO = 2.5 V
150 mV
VnPUC = 2.3 V
0 V
ACTIVE STATE OFF STATE, FSEAL = 1b
VCC
VIN_BU
A. Main Supply is disconnected or decays rapidly.
B. Rapid decay of VIN_BIAS (preregulator)
图8-17. Switching Behavior of the Battery-Backup-
Supply Power-Path; Power-Path Hysteresis
图8-18. Switching Behavior of the Battery-Backup-
Supply Power-Path; Main Power Supply Removal
VIN_BU
VIN_BU
VSYS_BU
VSYS_BU
VINT_LDO
VINT_LDO
VUVLO + VHYST
VUVLO + VHYST
VCC
VINT_LDO = 2.5 V
VnPUC = 2.3 V
VCC = 2.2 V
VINT_LDO = 2.5 V
VnPUC = 2.3 V
VIN_BU
= 2.05 V
ACTIVE STATE OFF STATE, FSEAL = 1b
ACTIVE STATE OFF STATE, FSEAL = 1b
A. System is supplied by Li-Ion battery with a weak coin-cell
backup battery.
A. System is supplied by Li-Ion battery with a fresh coin-cell
backup battery.
B. VIN_BIAS slow decay
B. (VIN_BIAS slow decay)
图8-20. Switching Behavior of the Battery-Backup-
Supply Power-Path; Weakening Main Battery,
Weak Coin-Cell
图8-19. Switching Behavior of the Battery-Backup-
Supply Power-Path; Weakening Main Battery,
Strong Coin-Cell
When VIN_BIAS drops below the UVLO threshold, the PMIC shuts down all rails and enters OFF mode. At this
point the power-path selects the higher of the two input supplies. If the coin-cell battery is less than 150 mV
above the UVLO threshold, SYS_BU remains connected to IN_BU (see 图 8-19). If the coin-cell is >150 mV
above the UVLO threshold, the power-path switches to the CC input as shown in 图 8-20. With no load on the
main supply, the input voltage may recover over time to a value greater than the coin-cell voltage and the power-
path switches back to IN_BU. This is a typical behavior in a Li-Ion battery powered system.
Depending on the system load, VIN_BIAS may drop below VINT_LDO before the power-down sequence is
completed. In that case, INT_LDO is turned OFF and the digital core is reset forcing the unit into OFF mode and
the power-path switches to IN_BU as shown in 图8-18.
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8.3.1.13 DCDC3 and DCDC4 Power-Up Default Selection
INT_LDO
SOURCE ENABLE
10 µA
DC34_SEL current source disabled.
All comparators disabled.
DC34_SEL
+
V6
V5
V4
V3
V2
V1
V0
Sequence is triggered by any
RSEL
1200 mV
œ
event forcing register reset.
+
Enable 10 µA DC34_SEL current source.
Enable comparators.
825 mV
575 mV
400 mV
275 mV
163 mV
100 mV
œ
+
Wait 100 µs
œ
DCDC3[5:0]
DCDC4[5:0]
LOGIC CORE
+
Latch comparator outputs;
Depending on result, over-write
DCDC3[5:0] and / or DCDC4[5:0]
power-up default.
œ
+
œ
Disable comparators
Disable DC34_SEL current source.
+
œ
+
Start power-up sequencer
œ
图8-21. Left: Flow Chart for Selecting DCDC Power-Up Default Voltage Right: Comparator Circuit
表8-2. Power-Up Default Values of DCDC3 and DCDC4
POWER-UP DEFAULT
RSEL [KΩ]
MIN
TYP
MAX
DCDC3[5:0]
DCDC4[5:0]
Programmed default (3.3 V)
Programmed default (3.3 V)
Programmed default (3.3 V)
Programmed default (3.3 V)
0x01 (1.2 V)
0
11.8
19.5
30.9
44.4
64.8
93.6
0
7.7
Programmed default (1.2 V)
0x12 (1.35 V)
12.1
20
12.4
20.5
32.3
46.3
67.3
97.2
0x18 (1.5 V)
31.6
45.3
66.1
95.3
0x1F (1.8 V)
0x3D (3.3 V)
Programmed default (1.2 V)
Programmed default (1.2 V)
0x07 (1.35 V)
0x0D (1.5 V)
Tied to
INT_LDO
146
150
Programmed default (1.2 V)
0x14 (1.8 V)
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8.3.1.14 I/O Configuration
The device has two GPIOs and one GPO pin, which are configured as follows:
• GPIO1:
– General-purpose, open-drain output is controlled by the GPO1 user bit or sequencer.
– DDR3 reset input signal from SOC. The signal is either latched or passed-through to the GPO2 pin. See
表8-3 for details.
• GPO2:
– General-purpose output is controlled by the GPO2 user bit.
– DDR3 reset output signal. Signal is controlled by GPIO1 and PGOOD. See 表8-4 for details.
– Output buffer is configured as open-drain or push-pull.
• GPIO3:
– General-purpose, open-drain output id controlled by the GPO3 user bit or sequencer.
– Reset input-signal for DCDC1 and DCDC2.
表8-3. GPIO1 Configuration
IO1_SEL
(EEPROM)
GPO1
(USER BIT)
PGOOD
(PMIC SIGNAL)
GPIO1
(I/O PIN)
COMMENTS
0
0
0
1
X
X
0
Open-drain output, driving low
Open-drain output, HiZ
HiZ
表8-4. GPO2 Configuration
IO1_SEL
(EEPROM)
GPO2_BUF
(EEPROM)
GPO2
(USER BIT)
COMMENTS
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
X
X
GPO2 is open drain output controlled by GPO2 user bit (driving low).
GPO2 is open drain output controlled by GPO2 user bit (HiZ).
GPO2 is push-pull output controlled by GPO2 user bit (driving low).
GPO2 is push-pull output controlled by GPO2 user bit (driving high).
GPO2 is open drain output controlled by GPIO1 and PGOOD.
GPO2 is push-pull output controlled by GPIO1 and PGOOD.
表8-5. GPIO3 Configuration
DC12_RST
(EEPROM)
GPO3
(USER BIT)
GPIO3
(I/O PIN)
COMMENTS
0
0
0
1
0
Open-drain output, driving low
Open-drain output, HiZ
HiZ
GPIO3 is DCDC1 and DCDC2 reset input signal to PMIC (active low). See
节8.3.1.14.2 for details.
1
X
Active low
8.3.1.14.1 Configuring GPO2 as Open-Drain Output
GPO2 may be configured as open-drain or push-pull output. The supply for the push-pull driver is internally
connected to the IN_LS1 input pin, whereas an external pull-up resistor and supply are required in the open-
drain configuration. Because of the internal connection to IN_LS1, the external pull-up supply must not exceed
the voltage on the IN_LS1 pin, otherwise leakage current may be observed from GPO2 to IN_LS1 as shown in
图8-22.
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IN_LS1
External
pullup supply
Leakage path if external
pullup supply is > IN_LS1
GPO2
Push-Pull
Driver
Open-Drain
Driver
图8-22. GPO2 as Open-Drain Output
Note
When configured as open-drain output, the external pull-up supply must not exceed the voltage level
on IN_LS1 pin.
8.3.1.14.2 Using GPIO3 as Reset Signal to DCDC1 and DCDC2
The GPIO3 is an edge-sensitive reset input to the PMIC, when the DC12_RST bit set to 1. The reset signal
affects DCDC1 and DCDC2 only, so that only those two registers are reset to the power-up default whenever
GPIO3 input transitions from high to low, while all other registers maintain their current values. DCDC1 and
DCDC2 transition back to the default value following the SLEW settings, and are not power cycled. This function
recovers the processor from reset events while in low-power mode.
PGOOD (1 ms delayed)
GPIO1
Latch,
Gating
IO1_SEL (EEPROM: 0b = output, 1b = input)
GPO1 (user register bit, sequencer control enabled)
GPO2_BUF (EEPROM: 0b = open drain, 1b = push-pull)
IN_LS1
GPO2
EN
1
0
GPO2 (user register bit)
DC12_RST (EEPROM: 0b = disabled, 1b = enabled)
DCDC 1 and DCDC 2 reset
GPIO3
GPO3 (user register bit, sequencer control enabled)
图8-23. I/O Pin Logic
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PMIC power-up
PGOOD
GPIO1 (DDR_RESET_IN)
(coming from SOC)
1 ms
RESET_OUT follows RESET_IN
1 ms
GPO2 (DDR_RESET_OUT)
(going to DDR memory)
RESET_IN is latched
RESET_OUT follows RESET_IN
图8-24. DDR3 Reset Timing Diagram
Note
GPIO must be configured as input (IO1_SEL = 1b). GPO2 is automatically configured as output.
8.3.1.15 Push Button Input (PB)
The PB pin is a CMOS-type input used to power-up the PMIC. Typically, the PB pin is connected to a momentary
switch to ground and an external pullup resistor. The power-up sequence is triggered if the PB input is held low
for 600 ms.
<100 ms
PB pin (input)
System Power
(5.5 V)
Push
Button
100 ms
50 ms
100 kꢀ
PB deglitched
(internal signal)
PB
550 ms
Power-up event
(internal signal)
图8-25. Left: Typical PB Input Circuit Right: Push-Button Input (PB) Deglitch and Power-Up Timing
In ACTIVE mode, the TPS6521815 monitors the PB input and issues an interrupt when the pin status changes,
such as when it drops below or rises above the PB input-low or input-high thresholds. The interrupt is masked by
the PBM bit in the INT_MASK1 register.
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PB is released before
INT register is read
through I2C. INT pin
remains low,
PB is pressed, INT
pin is pulled low,
PB._STATE bit is
set.
PB is released.
INT pin is pulled
low, PB_STATE bit
is reset.
PB is pressed, INT
pin is pulled low,
PB_STATE bit is
set.
PB_STATE bit is reset.
PB pin
(50-ms deglitched input)
nWAKEUP
150 µs
PB interrupt bit
INT pin (output)
PB_STATE bit
I2C access to INT register
INT register is read
through I2C while PB
remains pressed. INT
pin is released,
INT register is read
through I2C. INT pin is
released.
INT register is read
through I2C.
PB_STATE bit remains
set.
图8-26. PB Input-Low or Input-High Thresholds
Note
Interrupts are issued whenever the PB pin status changes. The PB_STATE bit reflects the current
status of the PB input. nWAKEUP is pulled low for 150 µs on every falling edge of PB.
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8.3.1.15.1 Signaling PB-Low Event on the nWAKEUP Pin
In ACTIVE state, the nWAKEUP pin is pulled low for five 32-kHz clock cycles (approximately 150 µs) whenever a
falling edge on the PB input is detected. This allows the host processor to wakeup from DEEP SLEEP mode of
operation. It is recommended to pull-up the nWAKEUP pin to DCDC6 output through a 1-MΩresistor .
8.3.1.15.2 Push Button Reset
If the PB input is pulled low for 8 s (15 s if TRST = 1b) or longer, then all rails except for DCDC5 and DCDC6 are
disabled, and the device enters the RECOVERY state. The device powers up automatically after the 500 ms
power-down sequence is complete, regardless of the state of the PB input. Holding the PB pin low for 8 s (15 s if
TRST = 1b), only turns off the device temporarily and forces a system restart, and is not a power-down function.
If the PB is held low continuously, the device power-cycles in 8-s and 15-s intervals.
8.3.1.16 AC_DET Input (AC_DET)
The AC_DET pin is a CMOS-type input used in three different ways to control the power-up of the PMIC:
• In a battery operated system, AC_DET is typically connected to an external battery charger with an open-
drain power-good output pulled low when a valid charger supply is connected to the system. A falling edge on
the AC_DET pin causes the PMIC to power up.
• In a non-portable system, the AC_DET pin may be shorted to ground and the device powers up whenever
system power is applied to the chip.
• If none of the above behaviors are desired, AC_DET may be tied to system power (IN_BIAS). Power-up is
then controlled through the push-button input or PWR_EN input.
System Power
(5.5 V)
System Power
(5.5 V)
100 kꢀ
AC_DET
AC_DET
AC_DET
(A)
(B)
(C)
A. Portable Systems
B. Non-portable Systems
C. Disabled
图8-27. AC_DET Pin Configurations
<100 ms
AC_DET pin
(input)
100 ms
10 ms
AC_DET
deglitched
(internal signal)
Power-up event
(internal signal)
图8-28. AC_DET Input Deglitch and Power-Up Timing (Portable Systems)
In ACTIVE state, the TPS6521815 monitors the AC_DET input and issues an interrupt when the pin status
changes, such as when it drops below or rises above the AC_DET input-low or input-high thresholds. The
interrupt is masked by the ACM bit in the INT_MASK1 register.
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AC goes high before
INT register is read
through I2C. INT pin
remains low,
AC goes low, INT
pin is pulled low,
PC_STATE bit is
set.
AC goes high. INT
pin is pulled low,
AC_STATE bit is
reset.
AC goes low, INT
pin is pulled low,
AC_STATE bit is
set.
AC_STATE bit is reset.
AC_DET pin
(10-ms deglitched input)
AC interrupt bit
INT pin (output)
AC_STATE bit
I2C access to INT register
INT register is read
through I2C while AC
remains low. INT pin is
released, AC_STATE bit
remains set.
INT register is read
through I2C. INT pin is
released.
INT register is read
through I2C.
图8-29. AC_STATE Pin
Note
Interrupts are issued whenever the AC_DET pin status changes. The AC_STATE bit reflects the
current status of the AC_DET input.
8.3.1.17 Interrupt Pin (INT)
The interrupt pin signals any event or fault condition to the host processor. Whenever a fault or event occurs in
the device, the corresponding interrupt bit is set in the INT register, and the open-drain output is pulled low. The
INT pin is released (returns to Hi-Z state) and fault bits are cleared when the host reads the INT register. If a
failure persists, the corresponding INT bit remains set and the INT pin is pulled low again after a maximum of 32
µs.
The MASK register masks events from generating interrupts. The MASK settings affect the INT pin only, and
have no impact on the protection and monitor circuits.
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8.3.1.18 I2C Bus Operation
The TPS6521815 hosts a slave I2C interface (address 0x24) that supports data rates up to 400 kbps, auto-
increment addressing. 1
Slave Address + R/nW
Register Address
Data
S
S
A6 A5 A4 A3 A2 A1 A0 R/nW
A
S7 S6 S5 S4 S3 S2 S1 S0
A
D7 D6 D5 D4 D3 D2 D1 D0
A
P
Start Condition
A
P
Acknowledge
A6
S7
... A0 Device Address
... S0 Subaddress
D7 ... D0 Data
R/nW Read, Not Write
Stop Condition
图8-30. Subaddress in I2C Transmission
The I2C bus is a communications link between a controller and a series of slave terminals. The link is
established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The
serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data
communication between the controller and the slave terminals. Each device has an open drain output to transmit
data on the serial data line. An external pullup resistor must be placed on the serial data line to pull the drain
output high during data transmission.
Data transmission initiates with a start bit from the controller as shown in 图 8-32. The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon
reception of a start bit, the device receives serial data on the SDA input and checks for valid address and control
information. If the appropriate slave address is set for the device, the device issues an acknowledge pulse and
prepares to receive register address and data. Data transmission is completed by either the reception of a stop
condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high
transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must
occur during the low portion of the SCL signal. An acknowledge issues after the reception of valid slave address,
register-address, and data words. The I2C interfaces an auto-sequence through the register addresses, so that
multiple data words can be sent for a given I2C transmission. Reference I2C Data Protocol and 图 8-32 for
details.
S
SLAVE ADDRESS
W
A
REGISTER ADDRESS
A
DATAREGADDR
A
DATASUBADDR+n
A
DATASUBADDR+n+1
A
P
n bytes + ACK
S
SLAVE ADDRESS
W
A
REGISTER ADDRESS
A
S
SLAVE ADDRESS
R
A
DATAREGADDR
A
DATAREGADDR+n
A
DATAREGADDR+n+1
A
P
n bytes + ACK
From master to slave
From slave to master
R
Read (high)
Write (low)
S
P
Start
Stop
A
A
Not Acknowledge
Acknowledge
W
Top: Master Writes Data to Slave
Bottom: Master Reads Data from Slave
图8-31. I2C Data Protocol
1
Note: The SCL duty cycle at 400 kHz must be >40%.
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SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
P
START
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK/nACK
STOP
图8-32. I2C Protocol and Transmission Timing I2C Start Stop and Acknowledge Protocol
SDA
tSU;DAT
tf
tLOW
tr
tSP
tr
tHD;STA
tBUF
SCL
tHD;STA
tSU;STA
tSU;STO
tf
tHD;DAT
tHIGH
S
Sr
P
S
图8-33. I2C Protocol and Transmission Timing I2C Data Transmission Timing
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8.4 Device Functional Modes
8.4.1 Modes of Operation
External power and
Coin Cell removed
FSEAL
ANY STATE
NO POWER
ANY STATE
: 0
PB low for > 8 s ||
OTS ||
PGOOD fault
VIN_BIAS < VUVLO ||
(OFFnPFO = 1 & VPFI < power-fail threshold)
SEQ DOWN
(500 ms)
SEQ DOWN
(500 ms)
VIN_BIAS > (VUVLO + hysteresis)
DCDC1...4 = OFF
DCDC5...6 = FSEAL dependent
DCDC1...4 = OFF
DCDC5...6 = FSEAL dependent
VIN_BIAS > (VUVLO + hysteresis) &
PB = high &
AC_DET = high &
PWR_EN = low
LDO1
= OFF
= OFF
= NO
DCDC1...4 = OFF
DCDC5...6 = FSEAL dependent
LDO1
= OFF
= ON
= NO
= low
INT_LDO
I2C
PGOOD
INT_LDO
I2C
PGOOD
OTS
LDO1
= OFF
= ON
= NO
= low
OFF
PRE_OFF
= low
INT_LDO
I2C
PGOOD
PGOOD_BU = rail dependent
nWAKEUP = low
PGOOD_BU = rail dependent
nWAKEUP = low
RECOVERY
VIN_BIAS > (VUVLO + hysteresis) &
(PB (;) || AC_DET (;) ||
PWR_EN = high)
Registers
: default
PGOOD_BU = high
nWAKEUP = HiZ
Registers
: default
FSEAL
Registers
= maintains state
: default
DCDC1...4 = ON
DCDC5...6 = ON
VIN_BIAS > (VUVLO + hysteresis) &
(PB (;) ||
AC_DET (;) ||
PWR_EN = high)
LDO1
= ON
= ON
= YES
INT_LDO
I2C
PGOOD
WAIT_PWR_EN
= high (rail dependent)
PGOOD_BU = high (rail dependent)
FSEAL = can be set to 1 but not to 0
nWAKEUP = low
PWR_EN = high
20 s time-out &
PB = high &
PWR_EN = low
DCDC1...4 = ON
DCDC5...6 = ON
LDO1
= ON
= ON
INT_LDO
I2C
PGOOD
ACTIVE
= YES
= high (rail dependent)
PGOOD_BU = high (rail dependent)
FSEAL = can be set to 1 but not to 0
nWAKEUP = HiZ
PWR_EN = low
DCDC1...4 = OFF &
LDO1 = OFF
SEQ DOWN
(500 ms)
DCDC1 = ON || DCDC2 = ON ||
DCDC3 = ON || DCDC4 = ON ||
LDO1 = ON
DCDC1...4 = seq. dependent
DCDC5...6 = seq. / FSEAL dependent
LDO1
= seq. dependent
= ON
= YES
INT_LDO
I2C
PGOOD
SUSPEND
= low
PGOOD_BU = high (rail dependent)
nWAKEUP = HiZ
DCDC1 reg. : default
DCDC2 reg. : default
PWR_EN = high ||
AC_DET (;) ||
PB (;)
PB (↓) has 50 ms debounce.
AC_DET (↓) has 10 ms debounce.
(↓) = denotes falling edge of signal.
图8-34. Modes of Operation Diagram
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8.4.2 OFF
In OFF mode, the PMIC is completely shut down with the exception of a few circuits to monitor the AC_DET,
PWR_EN, and PB input. All power rails are turned off and the registers are reset to their default values. The I2C
communication interface is turned off. This is the lowest-power mode of operation. To exit OFF mode VIN_BIAS
must exceed the UVLO threshold and one of the following wake-up events must occur:
• The PB input is pulled low.
• THE AC_DET input is pulled low.
• The PWR_EN input is pulled high.
To enter the OFF state, ensure that all power rails are assigned to the sequencer, then pull the PWR_EN pin low.
Additionally, if the OFFnPFO bit is set to 1b and the PFI input falls below the power fail threshold the device
transitions to the OFF state. If the freshness seal is broken, DCDC5 and DCDC6 remains on in the OFF state. If
a PGOOD or OTS fault occurs while in the ACTIVE state, TPS6521815 will transition to the RESET state.
8.4.3 ACTIVE
This is the typical mode of operation when the system is up and running. All DCDC converters, LDOs, and load
switch are operational and can be controlled through the I2C interface. After a wake-up event, the PMIC enables
all rails controlled by the sequencer and pulls the nWAKEUP pin low to signal the event to the host processor.
The device only enters the ACTIVE state if the host asserts the PWR_EN pin within 20 s after the wake-up
event. Otherwise it will enter the OFF state. The nWAKEUP pin returns to HiZ mode after the PWR_EN pin is
asserted. The ACTIVE state can also be directly entered from the SUSPEND state by pulling the PWR_EN pin
high. See the SUSPEND state description for details. To exit the ACTIVE mode, the PWR_EN pin must be pulled
low.
8.4.4 SUSPEND
The SUSPEND state is a low-power mode of operation intended to support system standby. Typically all power
rails are turned off with the exception of any rail with an SEQ register set to 0h. DCDC5 and DCDC6 also remain
enabled if the freshness seal is broken. To enter the SUSPEND state, pull the PWR_EN pin low. All power rails
controlled by the power-down sequencer are shut down, and after 500 ms the device enters the SUSPEND
state. All rails not controlled by the power-down sequencer will maintain its state. Note: all register values are
reset as the device enters the SUSPEND state. The device enters the ACTIVE state after it detects a wake-up
event as described in the previous sections.
8.4.5 RESET
The TPS6521815 can be reset by holding the PB pin low for more than 8 or 15 s, depending on the value of the
TRST bit. All rails are shut down by the sequencer and all register values reset to their default values. Rails not
controlled by the sequencer are shut down additionally. Note: the RESET function power-cycles the device and
only temporarily shuts down the output rails. Resetting the device does not lead to an OFF state. If the PB_IN
pin is kept low for an extended amount of time, the device continues to cycle between the ACTIVE and RESET
state, entering the RESET every 8 or 15 s.
The device is also reset if a PGOOD or OTS fault occurs. The TPS6521815 remains in the RECOVERY state
until the fault is removed, at which time it transitions back to the ACTIVE state.
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8.5 Programming
8.5.1 Programming Power-Up Default Values
A consecutive write of 0x50, 0x1A, or 0xCE to the password register commits the current register settings to
EEPROM memory so they become the new power-up default values.
Note
Only bits marked with (E2) in the register map have EEPROM programmable power-up default
settings. All other bits keep the factory settings listed in the register map. Changing the power-up
default values is not recommended in production but for prototyping only.
The EEPROM of a device can only be programmed up to 1000 times. The number of programming cycles
should never exceed this amount. Contact TI for changing production settings.
EEPROM values can only be changed if the input voltage (VIN_BIAS) is greater than 4.5 V. If the input voltage is
less than 4.5 V, EEPROM values remain unchanged and the VPROG interrupt is issued. EEPROM programming
requires less than 100 ms. During this time the supply voltage must be held constant and all I2C write commands
are ignored. Completion of EEPROM programming is signaled by the EE_CMPL interrupt.
Program EEPROM Registers
IDLE
0x50, 0x1A, and 0xCE written to the PASSWORD register
Check supply voltage
VIN_BIAS ≤ 4.5 V
(VIN_BIAS)
VIN_BIAS > 4.5 V
Lock I2C Interface for write
access
INT_LDO output
adjusted to 3.6 V
Program EEPROM
EE bit permanently set to 1b
INT_LDO output
adjusted to 2.5 V
Unlock I2C Interface
Issue PRGC Interrupt
Issue PRGC Interrupt
图8-35. Flow Chart for Programming New Power-Up Default Values
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8.6 Register Maps
8.6.1 Password Protection
Registers 0x11 through 0x26 are protected against accidental write by a 8-bit password. The password must be
written prior to writing to a protected register and automatically resets to 0x00 after the next I2C transaction,
regardless of the register accessed or transaction type (read or write). The password is required for write access
only and is not required for read access.
To write to a protected register:
1. Write the address of the destination register, XORed with the protection password (0x7D), to the
PASSWORD register (0x10).
2. Write the data to the password protected register.
3. If the content of the PASSWORD register is XORed, with an address send that matches 0x7D, then the data
transfers to the protected register. Otherwise, the transaction is ignored. In either case the PASSWORD
register resets to 0x00 after the transaction.
The cycle must be repeated for any other register that is Level1 write protected.
8.6.2 Freshness Seal (FSEAL) Bit
The FSEAL (freshness seal) bit prevents accidental shut-down of the always-on supplies, DCDC5 and DCDC6.
The FSEAL bit exists in a default state of 0b, and can be set to 1b and reset to 0b once for factory testing. The
second time the bit is set to 1b, it remains 1b and cannot reset again under software control. Coin-cell battery
and main supply must be disconnected from the device to reset the FSEAL bit again. With the FSEAL bit set to
1b, DCDC5 and DCDC6 are forced ON regardless of the state of the DC5_EN and DC6_EN bit, and the rails do
not turn off when the device enters the OFF state.
A consecutive write of [0xB1, 0xFE, and 0xA3] to the password register sets the FSEAL bit to 1b. The three
bytes must be written consecutively for the sequence to be valid. No other read or write transactions are allowed
between the three bytes, or the sequence is invalid. After a valid sequence, the FSEAL bit in the STATUS
register reflects the new setting.
After setting the FSEAL bit, the device can enter the OFF state or any other mode of operation without affecting
the state of the FSEAL bit, provided the coin-cell supply remains connected to the chip.
A second write of [0xB1, 0xFE, and 0xA3] to the password register resets the FSEAL bit to 0b. The three bytes
must be written consecutively for the sequence to be valid.
A third write of [0xB1, 0xFE, and 0xA3] to the password register sets the FSEAL bit to 1b and locks it into this
state for as long as the coin-cell supply (CC) remains connected to the device.
8.6.3 FLAG Register
The FLAG register contains a bit for each power rail and GPO to keep track of the enable state of the rails while
the system is suspended. The following rules apply to the FLAG register:
• The power-up default value for any flag bit is 0.
• Flag bits are read-only and cannot be written to.
• Upon entering a SUSPEND state, the flag bits are set to same value as their corresponding ENABLE bits.
Rails and GPOs enabled in a SUSPEND state have flag bits set to 1, while all other flag bits are set to 0. Flag
bits are not updated while in the SUSPEND state or when exiting the SUSPEND state.
• The FLAG register is static in WAIT_PWR_EN and ACTIVE state. The FLAG register reflects the enable state
of DCDC1, DCDC2, DCDC3, DCDC4, and LDO1; and, reflects the enable state of GPO1, GPO2, and GPO3
during the last SUSPEND state.
The host processor reads the FLAG register to determine if the system powered up from the OFF or SUSPEND
state. In the SUSPEND state, typically the DDR memory is kept in self refresh mode and therefore the DC3_FLG
or DC4_FLG bits are set.
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8.6.4 TPS6521815 Registers
表 8-6 lists the memory-mapped registers for the TPS6521815. All register offset addresses not listed in 表 8-6
should be considered as reserved locations and the register contents should not be modified.
表8-6. TPS6521815 Registers
PASSWORD
PROTECTED
SUBADDRESS
ACRONYM
CHIPID
REGISTER NAME
R/W
SECTION
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x20
0x21
0x22
0x23
0x24
0x25
0x26
CHIP ID
R
No
节8.6.5
节8.6.6
INT1
INTERRUPT 1
INTERRUPT 2
R
No
INT2
R
No
节8.6.7
INT_MASK1
INT_MASK2
STATUS
CONTROL
FLAG
INTERRUPT MASK 1
INTERRUPT MASK 2
STATUS
R/W
R/W
R
No
节8.6.8
No
节8.6.9
No
节8.6.10
节8.6.11
节8.6.12
节8.6.13
节8.6.14
节8.6.15
节8.6.16
节8.6.17
节8.6.18
节8.6.19
节8.6.20
节8.6.21
节8.6.22
节8.6.23
节8.6.24
节8.6.25
节8.6.26
节8.6.27
节8.6.28
节8.6.29
节8.6.30
节8.6.31
CONTROL
R/W
R
No
FLAG
No
PASSWORD
ENABLE1
ENABLE2
CONFIG1
CONFIG2
CONFIG3
DCDC1
DCDC2
DCDC3
DCDC4
SLEW
PASSWORD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
No
ENABLE 1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
ENABLE 2
CONFIGURATION 1
CONFIGURATION 2
CONFIGURATION 3
DCDC1 CONTROL
DCDC2 CONTROL
DCDC3 CONTROL
DCDC4 CONTROL
SLEW RATE CONTROL
LDO1 CONTROL
SEQUENCER 1
SEQUENCER 2
SEQUENCER 3
SEQUENCER 4
SEQUENCER 5
SEQUENCER 6
SEQUENCER 7
LDO1
SEQ1
SEQ2
SEQ3
SEQ4
SEQ5
SEQ6
SEQ7
表8-7 explains the common abbreviations used in this section.
表8-7. Common Abbreviations
Abbreviation
Description
R
Read
W
R/W
E2
h
Write
Read and write capable
Backed by EEPROM
Hexadecimal notation of a group of bits
Hexadecimal notation of a bit or group of bits
Do not care reset value
b
X
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8.6.5 CHIPID Register (subaddress = 0x00) [reset = 0x15]
CHIPID is shown in 图8-31 and described in 表8-8.
Return to 表8-6.
图8-31. CHIPID Register
7
6
5
4
3
2
1
0
CHIP
R-2h
REV
R-5h
表8-8. CHIPID Register Field Descriptions
Bit
7-3
Field
Type
Reset
Description
CHIP
R
2h
Chip ID:
0h = TPS65218D0
1h = Future use
2h = TPS6521815
3h = Future use
4h = TPS6521825
5h = Future use
...
1Fh = Future use
2-0
REV
R
5h
Revision code:
0h = Revision 1.0
1h = Revision 1.1
2h = Revision 2.0
3h = Revision 2.1
4h = Revision 3.0
5h = Revision 4.0 (D0)
6h = Future use
7h = Future use
8.6.6 INT1 Register (subaddress = 0x01) [reset = 0x00]
INT1 is shown in 图8-32 and described in 表8-9.
Return to 表8-6.
图8-32. INT1 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
VPRG
R-0b
AC
PB
HOT
R-0b
CC_AQC
R-0b
PRGC
R-0b
R-0b
R-0b
表8-9. INT1 Register Field Descriptions
Bit
Field
Type
Reset
00b
0b
Description
7-6
5
RESERVED
VPRG
R
R
Programming voltage interrupt:
0b = No significance.
1b = Input voltage is too low for programming power-up default
values.
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表8-9. INT1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
AC
R
0b
AC_DET pin status change interrupt. Note: Status information is
available in STATUS register.
0b = No change in status.
1b = AC_DET status change (AC_DET pin changed high to low or
low to high).
3
PB
R
0b
Push-button status change interrupt. Note: Status information is
available in STATUS register
0b = No change in status.
1b = Push-button status change (PB changed high to low or low to
high).
2
1
HOT
R
R
0b
0b
Thermal shutdown early warning:
0b = Chip temperature is below HOT threshold.
1b = Chip temperature exceeds HOT threshold.
CC_AQC
Coin cell battery voltage acquisition complete interrupt:
0b = No significance.
1b = Backup battery status comparators have settled and results are
available in STATUS register.
0
PRGC
R
0b
EEPROM programming complete interrupt:
0b = No significance.
1b = Programming of power-up default settings has completed
successfully.
8.6.7 INT2 Register (subaddress = 0x02) [reset = 0x00]
INT2 is shown in 图8-33 and described in 表8-10.
Return to 表8-6.
图8-33. INT2 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
LS3_F
R-0b
LS2_F
R-0b
LS1_F
R-0b
LS3_I
R-0b
LS2_I
R-0b
LS1_I
R-0b
表8-10. INT2 Register Field Descriptions
Bit
Field
Type
Reset
00b
0b
Description
7-6
5
RESERVED
LS3_F
R
R
Load switch 3 fault interrupt:
0b = No fault. Switch is working normally.
1b = Load switch exceeded operating temperature limit and is
temporarily disabled.
4
3
LS2_F
LS1_F
R
R
0b
0b
Load switch 2 fault interrupt:
0b = No fault. Switch is working normally.
1b = Load switch exceeded operating temperature limit or input
voltage dropped below minimum value. Switch is temporarily
disabled.
Load switch 1 fault interrupt:
0b = No fault. Switch is working normally.
1b = Load switch exceeded operating temperature limit and is
temporarily disabled.
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表8-10. INT2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
LS3_I
R
0b
Load switch 3 current-limit interrupt:
0b = Load switch is disabled or not in current limit.
1b = Load switch is actively limiting the output current (output load is
exceeding current limit value).
1
0
LS2_I
LS1_I
R
R
0b
0b
Load switch 2 current-limit interrupt:
0b = Load switch is disabled or not in current limit.
1b = Load switch is actively limiting the output current (output load is
exceeding current limit value).
Load switch 1 current-limit interrupt:
0b = Load switch is disabled or not in current limit.
1b = Load switch is actively limiting the output current (output load is
exceeding current limit value).
8.6.8 INT_MASK1 Register (subaddress = 0x03) [reset = 0x00]
INT_MASK1 is shown in 图8-34 and described in 表8-11.
Return to 表8-6.
图8-34. INT_MASK1 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
VPRGM
R/W-0b
ACM
PBM
HOTM
R/W-0b
CC_AQCM
R/W-0b
PRGCM
R/W-0b
R/W-0b
R/W-0b
表8-11. INT_MASK1 Register Field Descriptions
Bit
Field
Type
Reset
00b
0b
Description
7-6
5
RESERVED
VPRGM
R
R/W
Programming voltage interrupt mask bit. Note: mask bit has no effect
on monitoring function:
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
4
3
2
1
ACM
R/W
R/W
R/W
R/W
0b
0b
0b
0b
AC_DET interrupt masking bit:
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
Note: mask bit has no effect on monitoring function.
PBM
PB interrupt masking bit. Note: mask bit has no effect on monitoring
function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
HOTM
CC_AQCM
HOT interrupt masking bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
C_AQC interrupt masking bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
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表8-11. INT_MASK1 Register Field Descriptions (continued)
Bit
Field
PRGCM
Type
Reset
Description
0
R/W
0b
PRGC interrupt masking bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
8.6.9 INT_MASK2 Register (subaddress = 0x04) [reset = 0x00]
INT_MASK2 is shown in 图8-35 and described in 表8-12.
Return to 表8-6.
图8-35. INT_MASK2 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
LS3_FM
R/W-0b
LS2_FM
R/W-0b
LS1_FM
R/W-0b
LS3_IM
R/W-0b
LS2_IM
R/W-0b
LS1_IM
R/W-0b
表8-12. INT_MASK2 Register Field Descriptions
Bit
Field
Type
Reset
00b
0b
Description
7-6
5
RESERVED
LS3_FM
R
R/W
LS3 fault interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
4
3
2
1
0
LS2_FM
LS1_FM
LS3_IM
LS2_IM
LS1_IM
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
LS2 fault interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
LS1 fault interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
LS3 current-limit interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
LS2 current-limit interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
LS1 current-limit interrupt mask bit. Note: mask bit has no effect on
monitoring function.
0b = Interrupt is unmasked (interrupt event pulls nINT pin low).
1b = Interrupt is masked (interrupt has no effect on nINT pin).
8.6.10 STATUS Register (subaddress = 0x05) [reset = 00XXXXXXb]
Register mask: C0h
STATUS is shown in 图8-36 and is described in 表8-13.
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Return to 表8-6.
图8-36. STATUS Register
7
6
5
4
3
2
1
0
FSEAL
R-0b
EE
AC_STATE
R-X
PB_STATE
R-X
STATE
R-X
CC_STAT
R-X
R-0b
表8-13. STATUS Register Field Descriptions
Bit
Field
Type
Reset
Description
7
FSEAL
R
0b
Freshness seal (FSEAL) status. Note: See 节8.6.2 for details.
0b = FSEAL is in native state (fresh).
1b = FSEAL is broken.
6
EE
R
0b
EEPROM status:
0b = EEPROM values have not been changed from factory default
setting.
1b = EEPROM values have been changed from factory default
settings.
5
4
AC_STATE
PB_STATE
STATE
R
R
R
X
X
X
AC_DET input status bit:
0b = AC_DET input is inactive (AC_DET input pin is high).
1b = AC_DET input is active (AC_DET input is low).
PB input status bit:
0b = Push Button input is inactive (PB input pin is high).
1b = Push Button input is active (PB input pin is low).
3-2
State machine STATE indication:
0h = PMIC is in transitional state.
1h = PMIC is in WAIT_PWR_EN state.
2h = PMIC is in ACTIVE state.
3h = PMIC is in SUSPEND state.
1-0
CC_STAT
R
X
Coin cell state of charge. Note: Coin-cell voltage acquisition must be
triggered first before status bits are valid. See CC_AQ bit in 节
8.6.11 .
0h = VCC < VLOW_LEVEL; Coin cell is not present or approaching end-
of-life (EOL).
1h = VLOW_LEVEL < VCC < VGOOD_LEVEL; Coin cell voltage is LOW.
2h = VGOOD_LEVEL < VCC <VIDEAL_LEVEL; Coin cell voltage is GOOD.
3h = VIDEAL < VCC; Coin cell voltage is IDEAL.
8.6.11 CONTROL Register (subaddress = 0x06) [reset = 0x00]
CONTROL is shown in 图8-37 and described in 表8-14.
Return to 表8-6.
图8-37. CONTROL Register
7
6
5
4
3
2
1
0
RESERVED
R-0000 00b
OFFnPFO
R/W-0b
CC_AQ
R/W-0b
表8-14. CONTROL Register Field Descriptions
Bit
7-2
Field
RESERVED
Type
Reset
Description
R
0000 00b
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表8-14. CONTROL Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
OFFnPFO
R/W
0b
Power-fail shutdown bit:
0b = nPFO has no effect on PMIC state.
1b = All rails are shut down and PMIC enters OFF state when PFI
comparator trips (nPFO is low).
0
CC_AQ
R/W
0b
Coin Cell battery voltage acquisition start bit:
0b = No significance
1b = Triggers voltage acquisition. Bit is automatically reset to 0.
8.6.12 FLAG Register (subaddress = 0x07) [reset = 0x00]
FLAG is shown in 图8-38 and described in 表8-15.
Return to 表8-6.
图8-38. FLAG Register
7
6
5
4
3
2
1
0
GPO3_FLG
R-0b
GPO2_FLG
R-0b
GPO1_FLG
R-0b
LDO1_FLG
R-0b
DC4_FLG
R-0b
DC3_FLG
R-0b
DC2_FLG
R-0b
DC1_FLG
R-0b
表8-15. FLAG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GPO3_FLG
GPO2_FLG
GPO1_FLG
LDO1_FLG
DC4_FLG
R
0b
GPO3 Flag bit:
0b = Device powered up from OFF or SUSPEND state and GPO3
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GPO3 was
enabled while in SUSPEND.
6
5
4
3
R
R
R
R
0b
0b
0b
0b
GPO2 Flag bit
0b = Device powered up from OFF or SUSPEND state and GPO2
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GPO2 was
enabled while in SUSPEND.
GPO1 Flag bit:
0b = Device powered up from OFF or SUSPEND state and GPO1
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GPO1 was
enabled while in SUSPEND.
LDO1 Flag bit:
0b = Device powered up from OFF or SUSPEND state and LDO1
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and LDO1 was
enabled while in SUSPEND.
DCDC4 Flag bit:
0b = Device powered up from OFF or SUSPEND state and DCDC4
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and DCDC4 was
enabled while in SUSPEND.
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表8-15. FLAG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
2
DC3_FLG
R
0b
DCDC3 Flag bit:
0b = Device powered up from OFF or SUSPEND state and DCDC3
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and DCDC3 was
enabled while in SUSPEND.
1
0
DC2_FLG
DC1_FLG
R
R
0b
0b
DCDC2 Flag bit:
0b = Device powered up from OFF or SUSPEND state and DCDC2
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and DCDC2 was
enabled while in SUSPEND.
DCDC1 Flag bit:
0b = Device powered up from OFF or SUSPEND state and DCDC1
was disabled while in SUSPEND.
1b = Device powered up from SUSPEND state and GDCDC1PO3
was enabled while in SUSPEND.
8.6.13 PASSWORD Register (subaddress = 0x10) [reset = 0x00]
PASSWORD is shown in 图8-39 and described in 表8-16.
Return to 表8-6.
图8-39. PASSWORD Register
7
6
5
4
3
2
1
0
PWRD
R/W-00h
表8-16. PASSWORD Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
PWRD
R/W
00h
Register is used for accessing password protected registers (see 节
8.6.1 for details). Breaking the freshness seal (see 节8.6.2 for
details). Programming power-up default values (see 节8.5.1 for
details). Read-back always yields 0x00.
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8.6.14 ENABLE1 Register (subaddress = 0x11) [reset = 0x00]
ENABLE1 is shown in 图8-40 and described in 表8-17.
Return to 表8-6.
Password protected.
图8-40. ENABLE1 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
DC6_EN
R/W-0b
DC5_EN
R/W-0b
DC4_EN
R/W-0b
DC3_EN
R/W-0b
DC2_EN
R/W-0b
DC1_EN
R/W-0b
表8-17. ENABLE1 Register Field Descriptions
Bit
Field
Type
Reset
00b
0b
Description
7-6
5
RESERVED
DC6_EN
R
R/W
DCDC6 enable bit. DCDC6 can only be disabled if FSEAL = 0. See
节8.6.2 for details.
0b = Disabled
1b = Enabled
4
DC5_EN
R/W
0b
DCDC5 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer. DCDC5 can
only be disabled if FSEAL = 0. See 节8.6.2 for details.
0b = Disabled
1b = Enabled
3
2
1
0
DC4_EN
DC3_EN
DC2_EN
DC1_EN
R/W
R/W
R/W
R/W
0b
0b
0b
0b
DCDC4 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
DCDC3 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
DCDC2 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
DCDC1 enable bit. Note: At power-up and down this bit is
automatically updated by the internal power sequencer.
0b = Disabled
1b = Enabled
8.6.15 ENABLE2 Register (subaddress = 0x12) [reset = 0x00]
ENABLE2 is shown in 图8-41 and described in 表8-18.
Return to 表8-6.
Password protected.
图8-41. ENABLE2 Register
7
6
5
4
3
2
1
0
RESERVED
GPIO3
GPIO2
GPIO1
LS3_EN
LS2_EN
LS1_EN
LDO1_EN
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图8-41. ENABLE2 Register (continued)
R-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
R/W-0b
表8-18. ENABLE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
6
RESERVED
GPIO3
R
0b
R/W
0b
General purpose output 3 / reset polarity. Note: If DC12_RST bit
(register 0x14) is set to 1 this bit has no function.
0b = GPIO3 output is driven low.
1b = GPIO3 output is HiZ.
5
4
GPIO2
GPIO1
R/W
R/W
0b
0b
General purpose output 2. Note: If IO_SEL bit (register 0x13) is set
to 1 this bit has no function.
0b = GPO2 output is driven low.
1b = GPO2 output is HiZ.
General purpose output 1. Note: If IO_SEL bit (register 0x13) is set
to 1 this bit has no function.
0b = GPO1 output is driven low.
1b = GPO1 output is HiZ.
3
2
1
LS3_EN
LS2_EN
LS1_EN
R/W
R/W
R/W
0b
0b
0b
Load switch 3 (LS3) enable bit.
0b = Disabled
1b = Enabled
Load switch 2 (LS2) enable bit.
0b = Disabled
1b = Enabled
Load switch 1 (LS1) enable bit.
0b = Disabled
1b = Enabled
Note: At power-up and down this bit is automatically updated by the
internal power sequencer.
0
LDO1_EN
R/W
0b
LDO1 enable bit.
0b = Disabled
1b = Enabled
Note: At power-up and down this bit is automatically updated by the
internal power sequencer.
8.6.16 CONFIG1 Register (subaddress = 0x13) [reset = 0x08]
CONFIG1 is shown in 图8-42 and described in 表8-19.
Return to 表8-6.
Password protected.
图8-42. CONFIG1 Register
7
6
5
4
3
2
1
0
TRST
R/W-0b
GPO2_BUF
R/W-0b
IO1_SEL
R/W-0b
PGDLY
STRICT
R/W-0b
UVLO
R/W-01b
R/W-00b
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表8-19. CONFIG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
TRST
R/W, E2
0b
Push-button reset time constant:
0b = 8 s
1b = 15 s
6
5
GPO2_BUF
R/W, E2
R/W, E2
0b
0b
GPO2 output buffer configuration:
0b = GPO2 buffer is configured as open-drain.
1b = GPO2 buffer is configured as push-pull (high-level is driven to
IN_LS1).
IO1_SEL
PGDLY
GPIO1 / GPO2 configuration bit. See 节8.3.1.14 for details.
0b = GPIO1 is configured as general-purpose, open-drain output.
GPO2 is independent output.
1b = GPIO1 is configured as input, controlling GPO2. Intended for
DDR3 reset signal control.
4-3
R/W, E2
R/W, E2
R/W, E2
01b
Power-Good delay. Note: Power-good delay applies to rising-edge
only (power-up), not falling edge (power-down or fault).
00b = 10 ms
01b = 20 ms
10b = 50 ms
11b = 150 ms
2
STRICT
0b
Supply Voltage Supervisor Sensitivity selection. See 节7.5 for
details.
0b = Power-good threshold (VOUT falling) has wider limits. Over-
voltage is not monitored.
1b = Power-good threshold (VOUT falling) has tight limits. Over-
voltage is monitored.
1-0
UVLO
00b
UVLO setting
00b = 2.75 V
01b = 2.95 V
10b = 3.25 V
11b = 3.35 V
8.6.17 CONFIG2 Register (subaddress = 0x14) [reset = 0x40]
CONFIG2 is shown in 图8-43 and described in 表8-20.
Return to 表8-6.
Password protected.
图8-43. CONFIG2 Register
7
6
5
4
3
2
1
0
DC12_RST
R/W- 0b
UVLOHYS
R/W-1b
RESERVED
R-00b
LS3ILIM
R/W-00b
LS2ILIM
R/W-00b
表8-20. CONFIG2 Register Field Descriptions
Bit
Field
DC12_RST
Type
R/W, E2
Reset
Description
7
0b
DCDC1 and DCDC2 reset-pin enable:
0b = GPIO3 is configured as general-purpose output.
1b = GPIO3 is configured as warm-reset input to DCDC1 and DCDC2.
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表8-20. CONFIG2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
6
UVLOHYS
R/W, E2
1b
UVLO hysteresis:
0b = 200 mV
1b = 400 mV
5-4
3-2
RESERVED
LS3ILIM
R
00b
00b
R/W
Load switch 3 (LS3) current limit selection:
00b = 100 mA, (MIN = 98 mA)
01b = 200 mA, (MIN = 194 mA)
10b = 500 mA, (MIN = 475 mA)
11b = 1000 mA, (MIN = 900 mA)
See the LS3 current limit specification in 节7.5 for more details.
1-0
LS2ILIM
R/W
00b
Load switch 2 (LS2) current limit selection:
00b = 100 mA, (MIN = 94 mA)
01b = 200 mA, (MIN = 188 mA)
10b = 500 mA, (MIN = 465 mA)
11b = 1000 mA, (MIN = 922 mA)
See the LS2 current limit specification in 节7.5 for more details.
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8.6.18 CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
CONFIG3 is shown in 图8-44 and described in 表8-21.
Return to 表8-6.
Password protected.
图8-44. CONFIG3 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
LS3nPFO
R/W-0b
LS2nPFO
R/W-0b
LS1nPFO
R/W-0b
LS3DCHRG
R/W-0b
LS2DCHRG
R/W-0b
LS1DCHRG
R/W-0b
表8-21. CONFIG3 Register Field Descriptions
Bit
Field
Type
Reset
00b
0b
Description
7-6
5
RESERVED
LS3nPFO
R
R/W
Load switch 3 power-fail disable bit:
0b = Load switch status is not affected by power-fail comparator.
1b = Load switch is disabled if power-fail comparator trips (nPFO is
low).
4
3
2
1
0
LS2nPFO
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
Load switch 2 power-fail disable bit:
0b = Load switch status is not affected by power-fail comparator.
1b = Load switch is disabled if power-fail comparator trips (nPFO is
low).
LS1nPFO
Load switch 1 power-fail disable bit:
0b = Load switch status is not affected by power-fail comparator.
1b = Load switch is disabled if power-fail comparator trips (nPFO is
low).
LS3DCHRG
LS2DCHRG
LS1DCHRG
Load switch 3 discharge enable bit:
0b = Active discharge is disabled.
1b = Active discharge is enabled (load switch output is actively
discharged when switch is OFF).
Load switch 2 discharge enable bit:
0b = Active discharge is disabled.
1b = Active discharge is enabled (load switch output is actively
discharged when switch is OFF).
Load switch 1 discharge enable bit:
0b = Active discharge is disabled.
1b = Active discharge is enabled (load switch output is actively
discharged when switch is OFF).
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8.6.19 DCDC1 Register (offset = 0x16) [reset = 0x80]
DCDC1 is shown in 图8-45 and described in 表8-22.
Return to 表8-6.
Note 1: This register is password protected. For more information, see 节8.6.1 .
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed
on the DCDC1 register.
Note 3: To change the output voltage of DCDC1, the GO bit or the GODSBL bit must be set to 1b in register
0x1A.
图8-45. DCDC1 Register
7
6
5
4
3
2
1
0
PFM
RESERVED
R-0b
DCDC1
R/W-1b
R/W-00h
表8-22. DCDC1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PFM
R/W
1b
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6
RESERVED
R
0b
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表8-22. DCDC1 Register Field Descriptions (continued)
Bit
Field
DCDC1
Type
Reset
Description
5-0
R/W, E2
00h
DCDC1 output voltage setting:
0h = 0.850
1h = 0.860
2h = 0.870
3h = 0.880
4h = 0.890
5h = 0.900
6h = 0.910
7h = 0.920
8h = 0.930
9h = 0.940
Ah = 0.950
Bh = 0.960
Ch = 0.970
Dh = 0.980
Eh = 0.990
Fh = 1.000
10h = 1.010
11h = 1.020
12h = 1.030
13h = 1.040
14h = 1.050
15h = 1.060
16h = 1.070
17h = 1.080
18h = 1.090
19h = 1.100
1Ah = 1.110
1Bh = 1.120
1Ch = 1.130
1Dh = 1.140
1Eh = 1.150
1Fh = 1.160
20h = 1.170
21h = 1.180
22h = 1.190
23h = 1.200
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表8-22. DCDC1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24h = 1.210
25h = 1.220
26h = 1.230
27h = 1.240
28h = 1.250
29h = 1.260
2Ah = 1.270
2Bh = 1.280
2Ch = 1.290
2Dh = 1.300
2Eh = 1.310
2Fh = 1.320
30h = 1.330
31h = 1.340
32h = 1.350
33h = 1.375
34h = 1.400
35h = 1.425
36h = 1.450
37h = 1.475
38h = 1.500
39h = 1.525
3Ah = 1.550
3Bh = 1.575
3Ch = 1.600
3Dh = 1.625
3Eh = 1.650
3Fh = 1.675
8.6.20 DCDC2 Register (subaddress = 0x17) [reset = 0x80]
DCDC2 is shown in 图8-46 and described in 表8-23.
Return to 表8-6.
Note 1: This register is password protected. For more information, see 节8.6.1 .
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed
on the DCDC2 register.
Note 3: To change the output voltage of DCDC2, the GO bit or the GODSBL bit must be set to 1b in register
0x1A.
图8-46. DCDC2 Register
7
6
5
4
3
2
1
0
PFM
RESERVED
R-0b
DCDC2
R/W-1b
R/W-00h
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表8-23. DCDC2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PFM
R/W
1b
Pulse frequency modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6
RESERVED
DCDC2
R
0b
5-0
R/W, E2
00h
DCDC2 output voltage setting:
0h = 0.850
1h = 0.860
2h = 0.870
3h = 0.880
4h = 0.890
5h = 0.900
6h = 0.910
7h = 0.920
8h = 0.930
9h = 0.940
Ah = 0.950
Bh = 0.960
Ch = 0.970
Dh = 0.980
Eh = 0.990
Fh = 1.000
10h = 1.010
11h = 1.020
12h = 1.030
13h = 1.040
14h = 1.050
15h = 1.060
16h = 1.070
17h = 1.080
18h = 1.090
19h = 1.100
1Ah = 1.110
1Bh = 1.120
1Ch = 1.130
1Dh = 1.140
1Eh = 1.150
1Fh = 1.160
20h = 1.170
21h = 1.180
22h = 1.190
23h = 1.200
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表8-23. DCDC2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24h = 1.210
25h = 1.220
26h = 1.230
27h = 1.240
28h = 1.250
29h = 1.260
2Ah = 1.270
2Bh = 1.280
2Ch = 1.290
2Dh = 1.300
2Eh = 1.310
2Fh = 1.320
30h = 1.330
31h = 1.340
32h = 1.350
33h = 1.375
34h = 1.400
35h = 1.425
36h = 1.450
37h = 1.475
38h = 1.500
39h = 1.525
3Ah = 1.550
3Bh = 1.575
3Ch = 1.600
3Dh = 1.625
3Eh = 1.650
3Fh = 1.675
8.6.21 DCDC3 Register (subaddress = 0x18) [reset = 0x80]
DCDC3 is shown in 图8-47 and described in 表8-24.
Return to 表8-6.
Note 1: This register is password protected. For more information, see 节8.6.1 .
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed
on the DCDC3 register.
Note
Power-up default may differ depending on RSEL value. See 节8.3.1.13 for details.
图8-47. DCDC3 Register
7
6
5
4
3
2
1
0
PFM
RESERVED
R-0b
DCDC3
R/W-1b
R/W-00h
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表8-24. DCDC3 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PFM
R/W
1b
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6
RESERVED
DCDC3
R
0b
5-0
R/W, E2
00h
DCDC3 output voltage setting:
0h = 0.900
1h = 0.925
2h = 0.950
3h = 0.975
4h = 1.000
5h = 1.025
6h = 1.050
7h = 1.075
8h = 1.100
9h = 1.125
Ah = 1.150
Bh = 1.175
Ch = 1.200
Dh = 1.225
Eh = 1.250
Fh = 1.275
10h = 1.300
11h = 1.325
12h = 1.350
13h = 1.375
14h = 1.400
15h = 1.425
16h = 1.450
17h = 1.475
18h = 1.500
19h = 1.525
1Ah = 1.550
1Bh = 1.600
1Ch = 1.650
1Dh = 1.700
1Eh = 1.750
1Fh = 1.800
20h = 1.850
21h = 1.900
22h = 1.950
23h = 2.000
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表8-24. DCDC3 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24h = 2.050
25h = 2.100
26h = 2.150
27h = 2.200
28h = 2.250
29h = 2.300
2Ah = 2.350
2Bh = 2.400
2Ch = 2.450
2Dh = 2.500
2Eh = 2.550
2Fh = 2.600
30h = 2.650
31h = 2.700
32h = 2.750
33h = 2.800
34h = 2.850
35h = 2.900
36h = 2.950
37h = 3.000
38h = 3.050
39h = 3.100
3Ah = 3.150
3Bh = 3.200
3Ch = 3.250
3Dh = 3.300
3Eh = 3.350
3Fh = 3.400
8.6.22 DCDC4 Register (subaddress = 0x19) [reset = 0x80]
DCDC4 is shown in 图8-48 and described in 表8-25.
Return to 表8-6.
Note 1: This register is password protected. For more information, see 节8.6.1 .
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed
on the DCDC4 register.
Note
Power-up default may differ depending on RSEL value. See 节 8.3.1.13 for details. The Reserved
setting should not be selected and the output voltage settings should not be modified while the
converter is operating.
图8-48. DCDC4 Register
7
6
5
4
3
2
1
0
PFM
RESERVED
R-0b
DCDC4
R/W-1b
R/W-00h
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表8-25. DCDC4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
PFM
R/W
1b
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode)
enable. PFM mode improves light-load efficiency. Actual PFM mode
operation depends on load condition.
0b = Disabled (forced PWM)
1b = Enabled
6
RESERVED
DCDC4
R
0b
5-0
R/W, E2
00h
DCDC4 output voltage setting:
0h = 1.175
1h = 1.200
2h = 1.225
3h = 1.250
4h = 1.275
5h = 1.300
6h = 1.325
7h = 1.350
8h = 1.375
9h = 1.400
Ah = 1.425
Bh = 1.450
Ch = 1.475
Dh = 1.500
Eh = 1.525
Fh = 1.550
10h = 1.600
11h = 1.650
12h = 1.700
13h = 1.750
14h = 1.800
15h = 1.850
16h = 1.900
17h = 1.950
18h = 2.000
19h = 2.050
1Ah = 2.100
1Bh = 2.150
1Ch = 2.200
1Dh = 2.250
1Eh = 2.300
1Fh = 2.3500
20h = 2.400
21h = 2.450
22h = 2.500
23h = 2.550
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表8-25. DCDC4 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
24h = 2.600
25h = 2.650
26h = 2.700
27h = 2.750
28h = 2.800
29h = 2.850
2Ah = 2.900
2Bh = 2.950
2Ch = 3.000
2Dh = 3.050
2Eh = 3.100
2Fh = 3.150
30h = 3.200
31h = 3.250
32h = 3.300
33h = 3.350
34h = 3.400
35h = reserved
36h = reserved
37h = reserved
38h = reserved
39h = reserved
3Ah = reserved
3Bh = reserved
3Ch = reserved
3Dh = reserved
3Eh = reserved
3Fh = reserved
8.6.23 SLEW Register (subaddress = 0x1A) [reset = 0x06]
SLEW is shown in 图8-49 and described in 表8-26.
Return to 表8-6.
Note
Slew-rate control applies to DCDC1 and DCDC2 only. If changing from a higher voltage to lower
voltage while STRICT = 1 and converters are in a no load state, PFM bit for DCDC1 and DCDC2 must
be set to 0.
图8-49. SLEW Register
7
6
5
4
3
2
1
0
GO
GODSBL
R/W-0b
RESERVED
R-000b
SLEW
R/W-6h
R/W-0b
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表8-26. SLEW Register Field Descriptions
Bit
Field
Type
Reset
Description
7
GO
R/W
0b
Go bit. Note: Bit is automatically reset at the end of the voltage
transition.
0b = No change
1b = Initiates the transition from present state to the output voltage
setting currently stored in DCDC1 and DCDC2 register. SLEW
setting does apply.
6
GODSBL
R/W
0b
Go disable bit
0b = Enabled
1b = Disabled; DCDC1 and DCDC2 output voltage changes
whenever set-point is updated in DCDC1 and DCDC2 register
without having to write to the GO bit. SLEW setting does apply.
5-3
2-0
RESERVED
SLEW
R
000b
6h
R/W
Output slew rate setting:
0h = 160 µs/step (0.0625 mV/µs at 10 mV per step)
1h = 80 µs/step (0.125 mV/µs at 10 mV per step)
2h = 40 µs/step (0.250 mV/µs at 10 mV per step)
3h = 20 µs/step (0.500 mV/µs at 10 mV per step)
4h = 10 µs/step (1.0 mV/µs at 10 mV per step)
5h = 5 µs/step (2.0 mV/µs at 10 mV per step)
6h = 2.5 µs/step (4.0 mV/µs at 10 mV per step)
7h = Immediate; slew rate is only limited by control loop response
time. Note: The actual slew rate depends on the voltage step per
code. Refer to DCDCx registers for details.
8.6.24 LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
LDO1 is shown in 图8-50 and described in 表8-27.
Return to 表8-6.
Note 1: This register is password protected. For more information, see 节8.6.1 .
Note 2: A 5-ms blanking time of the over-voltage and under-voltage monitoring occurs when a write is performed
on the LDO1 register.
图8-50. LDO1 Register
7
6
5
4
3
2
1
0
RESERVED
R-00b
LDO1
R/W-1Fh
表8-27. LDO1 Register Field Descriptions
Bit
7-6
Field
Type
Reset
Description
RESERVED
R
00b
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表8-27. LDO1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5-0
LDO1
R/W, E2
1Fh
LDO1 output voltage setting:
0h = 0.900
1h = 0.925
2h = 0.950
3h = 0.975
4h = 1.000
5h = 1.025
6h = 1.050
7h = 1.075
8h = 1.100
9h = 1.125
Ah = 1.150
Bh = 1.175
Ch = 1.200
Dh = 1.225
Eh = 1.250
Fh = 1.275
10h = 1.300
11h = 1.325
12h = 1.350
13h = 1.375
14h = 1.400
15h = 1.425
16h = 1.450
17h = 1.475
18h = 1.500
19h = 1.525
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表8-27. LDO1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1Ah = 1.550
1Bh = 1.600
1Ch = 1.650
1Dh = 1.700
1Eh = 1.750
1Fh = 1.800
20h = 1.850
21h = 1.900
22h = 1.950
23h = 2.000
24h = 2.050
25h = 2.100
26h = 2.150
27h = 2.200
28h = 2.250
29h = 2.300
2Ah = 2.350
2Bh = 2.400
2Ch = 2.450
2Dh = 2.500
2Eh = 2.550
2Fh = 2.600
30h = 2.650
31h = 2.700
32h = 2.750
33h = 2.800
34h = 2.850
35h = 2.900
36h = 2.950
37h = 3.000
38h = 3.050
39h = 3.100
3Ah = 3.150
3Bh = 3.200
3Ch = 3.250
3Dh = 3.300
3Eh = 3.350
3Fh = 3.400
8.6.25 SEQ1 Register (subaddress = 0x20) [reset = 0x00]
SEQ1 is shown in 图8-51 and described in 表8-28.
Return to 表8-6.
Password protected.
图8-51. SEQ1 Register
7
6
5
4
3
2
1
0
DLY8
R/W-0b
DLY7
R/W-0b
DLY6
R/W-0b
DLY5
R/W-0b
DLY4
R/W-0b
DLY3
R/W-0b
DLY2
R/W-0b
DLY1
R/W-0b
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表8-28. SEQ1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DLY8
R/W, E2
0b
Delay8 (occurs after Strobe 8 and before Strobe 9.)
0b = 2 ms
1b = 5 ms
6
5
4
3
2
1
0
DLY7
DLY6
DLY5
DLY4
DLY3
DLY2
DLY1
R/W, E2
R/W, E2
R/W, E2
R/W, E2
R/W, E2
R/W, E2
R/W, E2
0b
0b
0b
0b
Delay7 (occurs after Strobe 7 and before Strobe 8.)
0b = 2 ms
1b = 5 ms
Delay6 (occurs after Strobe 6 and before Strobe 7.)
0b = 2 ms
1b = 5 ms
Delay5 (occurs after Strobe 5 and before Strobe 6.)
0b = 2 ms
1b = 5 ms
Delay4 (occurs after Strobe 4 and before Strobe 5.)
0b = 2 ms
1b = 5 ms
0b
0b
0b
Delay3 (occurs after Strobe 3 and before Strobe 4.)
0b = 2 ms
1b = 5 ms
Delay2 (occurs after Strobe 2 and before Strobe 3.)
0b = 2 ms
1b = 5 ms
Delay1 (occurs after Strobe 1 and before Strobe 2.)
0b = 2 ms
1b = 5 ms
8.6.26 SEQ2 Register (subaddress = 0x21) [reset = 0x00]
SEQ2 is shown in 图8-52 and described in 表8-29.
Return to 表8-6.
Password protected.
图8-52. SEQ2 Register
7
6
5
4
3
2
1
0
DLYFCTR
R/W -0b
RESERVED
R-000 000b
DLY9
R/W -0b
表8-29. SEQ2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
DLYFCTR
R/W, E2
0b
Power-down delay factor:
0b = 1x
1b = 10x (delay times are multiplied by 10x during power-down.)
Note: DLYFCTR has no effect on power-up timing.
6-1
0
RESERVED
DLY9
R
000 000b
0b
R/W, E2
Delay9 (occurs after Strobe 9 and before Strobe 10.)
0b = 2 ms
1b = 5 ms
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8.6.27 SEQ3 Register (subaddress = 0x22)[reset = 0x00]
SEQ3 is shown in 图8-53 and described in 表8-30.
Return to 表8-6.
Password protected.
图8-53. SEQ3 Register
7
6
5
4
3
2
1
0
DC2_SEQ
R/W-0h
DC1_SEQ
R/W-0h
表8-30. SEQ3 Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
DC2_SEQ
R/W, E2
0h
DCDC2 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
3-0
DC1_SEQ
R/W, E2
0h
DCDC1 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
8.6.28 SEQ4 Register (subaddress = 0x23) [reset = 0x00]
SEQ4 is shown in 图8-54 and described in 表8-31.
Return to 表8-6.
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Password protected.
图8-54. SEQ4 Register
7
6
5
4
3
2
1
0
DC4_SEQ
R/W-0h
DC3_SEQ
R/W-0h
表8-31. SEQ4 Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
DC4_SEQ
R/W, E2
0h
DCDC4 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
3-0
DC3_SEQ
R/W, E2
0h
DCDC3 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
8.6.29 SEQ5 Register (subaddress = 0x24) [reset = 0x00]
SEQ5 is shown in 图8-55 and described in 表8-32.
Return to 表8-6.
Password protected.
图8-55. SEQ5 Register
7
6
5
4
3
2
1
0
RESERVED
DC6_SEQ
RESERVED
DC5_SEQ
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图8-55. SEQ5 Register (continued)
R-0h
R/W-0h
R-0h
R/W-0h
表8-32. SEQ5 Register Field Descriptions
Bit
7-6
5-4
Field
Type
Reset
Description
RESERVED
DC6_SEQ
R
0h
R/W, E2
0h
DCDC6 enable STROBE. Note: STROBE 1 and STROBE 2 are
executed only if FSEAL = 0. DCDC5 and 6 cannot be disabled by
sequencer once freshness seal is broken.
0h = Rail is not controlled by sequencer.
1h = Enable at STROBE 1.
2h = Enable at STROBE 2.
3h = Rail is not controlled by sequencer.
3-2
1-0
RESERVED
DC5_SEQ
R
0h
0h
R/W, E2
DCDC5 enable STROBE. Note: STROBE 1 and STROBE 2 are
executed only if FSEAL = 0. DCDC5 and 6 cannot be disabled by
sequencer once freshness seal is broken.
0h = Rail is not controlled by sequencer.
1h = Enable at STROBE 1.
2h = Enable at STROBE 2.
3h = Rail is not controlled by sequencer.
8.6.30 SEQ6 Register (subaddress = 0x25) [reset = 0x00]
SEQ6 is shown in 图8-56 and described in 表8-33.
Return to 表8-6.
Password protected.
图8-56. SEQ6 Register
7
6
5
4
3
2
1
0
LS1_SEQ
R/W-0h
LDO1_SEQ
R/W-0h
表8-33. SEQ6 Register Field Descriptions
Bit
7-4
Field
Type
Reset
Description
LS1_SEQ
R/W, E2
0h
LS1 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
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表8-33. SEQ6 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
3-0
LDO1_SEQ
R/W, E2
0h
LDO1 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
8.6.31 SEQ7 Register (subaddress = 0x26) [reset = 0x00]
SEQ7 is shown in 图8-57 and described in 表8-34.
Return to 表8-6.
Password protected.
图8-57. SEQ7 Register
7
6
5
4
3
2
1
0
GPO3_SEQ
R/W-0h
GPO1_SEQ
R/W-0h
表8-34. SEQ7 Register Field Descriptions
Bit
7-4
Field
GPO3_SEQ
Type
Reset
Description
R/W, E2
0h
GPO3 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
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表8-34. SEQ7 Register Field Descriptions (continued)
Bit
Field
GPO1_SEQ
Type
Reset
Description
3-0
R/W, E2
0h
GPO1 enable STROBE:
0h = Rail is not controlled by sequencer.
1h = Rail is not controlled by sequencer.
2h = Rail is not controlled by sequencer.
3h = Enable at STROBE 3.
4h = Enable at STROBE 4.
5h = Enable at STROBE 5.
6h = Enable at STROBE 6.
7h = Enable at STROBE 7.
8h = Enable at STROBE 8.
9h = Enable at STROBE 9.
Ah = Enable at STROBE 10.
Bh = Rail is not controlled by sequencer.
Ch = Rail is not controlled by sequencer.
Dh = Rail is not controlled by sequencer.
Eh = Rail is not controlled by sequencer.
Fh = Rail is not controlled by sequencer.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The TPS6521815 is designed to pair with various applications. The typical application in 节 9.2 is based on and
uses terminology consistent with the Sitara™ family of processors.
9.1.1 Applications Without Backup Battery
In applications that require always-on supplies but no battery backup, the CC input to the power path must be
connected to ground.
DCDC6 (1.8 V)
10 µH
VDD_10 (1 V)
Battery backup
domain supply
L5
DCDC5_PG
DCDC6_PG
PGOOD_BU
22 …F
22 …F
To SOC
To SOC
DCDC5
DCDC6
FB5
DCDC6 (1.8 V)
VDD_18 (1.8 V)
Battery backup
domain supply
10 µH
L6
IN_nCC
FB6
2.7-V to 5.5-V
system power
IN_BU
4.7 …F
CC
SYS_BU
1 …F
Always-on coin-cell battery backup supplies
IN_BIAS
From 2.7-V to 6.5-V
system power
INT_LDO
BIAS
100 nF
图9-1. CC Input to Power Path
Note
In applications without backup battery, CC input must be tied to ground.
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9.1.2 Applications Without Battery Backup Supplies
In applications that do not require always-on supplies, both inputs and the output of the power-path can simply
be grounded. All pins related to DCDC5 and DCDC6 are also tied to ground, and PGOOD_BU and IN_nCC are
kept floating. With the backup supplies completely disabled, the FSEAL bit in the STATUS register is undefined
and should be ignored.
DCDC6 (1.8 V)
L5
DCDC5_PG
DCDC6_PG
PGOOD_BU
No connect
DCDC5
DCDC6
FB5
DCDC6 (1.8 V)
L6
IN_nCC
No connect
FB6
IN_BU
CC
SYS_BU
Always-on coin-cell battery backup supplies
图9-2. DCDC5 and DCDC6 Pins
Note
In applications that do not require always-on supplies, PGOOD_BU and IN_nCC can be kept floating.
All other pins are tied to ground.
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9.2 Typical Application
VDDSHVx
for GPIOx
System Power (5.5 V)
DCDC6
VDDSHV3
Push
Button
nWAKEUP
PB
RTC_WAKEUP
nINT
GPIOx
PGOOD
PWR_EN
SCL and SDA
GPIO3
PWRONRSTn
RTC_PMIC_EN
I2C0_SCL/SDA
Digital
AC_DET
10 ꢀ
PGOOD_BU
IN_nCC
CC
RTC_PWRONRSTn
Battery Backup
Supplies
+
Coin
Cell
œ
1.0 V (DCDC5)
1.8 V (DCDC6)
DCDC5
DCDC6
CAP_VDD_RTC
VDDS_RTC
IN_BU
IN_LDO1
1.8 V
2.7-V to 5.5-V
system power
LDO1
1.8V Analog & I/O
IN_DCDC1
IN_DCDC2
IN_DCDC3
IN_DCDC4
IN_BIAS
0.95 / 1.1 V
DCDC1 (buck)
DCDC2 (buck)
VDD_CORE
VDD_MPU
0.95 / 1.1 / 1.2 / 1.26 /1.325 V
1.35 / 1.5 V
3.3 V
DCDC3 (buck)
DCDC4 (buck-boost)
3.3V Analog & I/O
DDR_RESETn
BIAS
LS1
IN_LS1
LS1
From DCDC3
VDDS_DDR
TPS65218
DDR3/L Memory
A. Block diagram shows TPS65218D0 powering AM437x processor. For TPS6521825, refer to this Tech Note. For TPS6521815, the
wiring is not predefined and is programmed for the specific processor in the application.
图9-3. Typical Application Schematic for TPS65218D0
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9.2.1 Design Requirements
表9-1 lists the design requirements.
表9-1. Design Parameters for TPS65218D0 (1)
VOLTAGE
SEQUENCE
DCDC1
1.1 V
8
9
5
7
2
1
3
DCDC2
DCDC3
DCDC4
DCDC5
DCDC6
LDO1
1.1 V
1.2 V
3.3 V
1.0 V
1.8 V
1.8 V
(1) Default output voltages shown for TPS65218D0. For other
TPS65218xx variants, refer to DCDC1-4 and LDO1 registers in
节8.6.4 .
9.2.2 Detailed Design Procedure
9.2.2.1 Output Filter Design
The step down converters (DCDC1, DCDC2, and DCDC3) on TPS6521815 are designed to operate with
effective inductance values in the range of 1 to 2.2 µH and with effective output capacitance in the range of 10 to
100 µF. The internal compensation is optimized to operate with an output filter of L = 1.5 µH and COUT = 10 µF.
The buck boost converter (DCDC4) on TPS6521815 is designed to operate with effective inductance values in
the range of 1.2 to 2.2 µH. The internal compensation is optimized to operate with an output filter of L = 1.5 µH
and COUT = 47 µF.
The two battery backup converters (DCDC5 and DCDC6) are designed to operate with effective inductance
values in the range of 4.7 to 22 µH. The internal compensation is optimized with an output filter of L = 10 µH and
COUT = 20 µF.
Larger or smaller inductor/capacitance values can be used to optimize performance of the device for specific
operation conditions.
9.2.2.2 Inductor Selection for Buck Converters
The inductor value affects its peak to peak ripple current, the PWM to PFM transition point, the output voltage
ripple, and the efficiency. The selected inductor must be rated for its DC resistance and saturation current. The
inductor ripple current (∆L) decreases with higher inductance and increases with higher VIN or VOUT. 方程式 1
calculates the maximum inductor current ripple under static load conditions. The saturation current of the
inductor should be rated higher than the maximum inductor current as calculated with 方程式 2. This is
recommended as during heavy load transient the inductor current will rise above the calculated value.
VOUT
1 œ
V
IN
DIL = VOUT
ì
L ì ƒ
(1)
(2)
DIL
ILmax = IOUTmax
where
+
2
• F = Switching frequency
• L = Inductor value
•
∆IL = Peak-to-peak inductor ripple current
• ILmax = Maximum inductor current
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The following inductors have been used with the TPS6521815 (see 表9-2).
表9-2. List of Recommended Inductors
PART NUMBER
VALUE
SIZE (mm) [L × W × H]
MANUFACTURER
INDUCTORS FOR DCDC1, DCDC2, DCDC3, DCDC4
SPM3012T-1R5M
IHLP1212BZER1R5M11
3.2 × 3.0 × 1.2
3.6 × 3.0 × 2.0
TDK
1.5 µH, 2.8 A, 77 mΩ
1.5 µH, 4.0 A, 28.5 mΩ
Vishay
INDUCTORS FOR DCDC5, DCDC6
2012 / 0805 (2.00 × 1.25 ×
1.25)
MLZ2012N100L
TDK
10 µH, 110 mA, 300 mΩ
10 µH, 100 mA, 300 mΩ
2012 / 0805 (2.00 × 1.25 ×
1.25)
LQM21FN100M80
Murata
9.2.2.3 Output Capacitor Selection
The hysteretic PWM control scheme of the TPS6521815 switching converters allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric.
At light load currents the converter operates in power save mode, and the output voltage ripple is dependent on
the output capacitor value and the PFM peak inductor current. Higher output capacitor values minimize the
voltage ripple in PFM Mode and tighten DC output accuracy in PFM mode.
The two battery backup converters (DCDC5 and DCDC6) always operate in PFM mode. For these converters, a
capacitor of at least 20 µF is recommended on the output to help minimize voltage ripple.
The buck-boost converter requires additional output capacitance to help maintain converter stability during high
load conditions. At least 40 µF of output capacitance is recommended and an additional 100-nF capacitor can be
added to further filter output ripple at higher frequencies.
表9-2 lists the recommended capacitors.
表9-3. List of Recommended Capacitors
PART NUMBER
CAPACITORS FOR VOLTAGES UP TO 5.5 V(1)
GRM188R60J105K
VALUE
SIZE (mm) [L × W × H]
MANUFACTURER
1 µF
4.7 µF
10 µF
22 µF
1608 / 0603 (1.6 × 0.8 × 0.8)
2012 / 0805 (2.0 × 1.25 × 1.25)
3216 / 1206 (3.2 × 1.6 × 1.6)
3216 / 1206 (3.2 × 1.6 × 1.6)
Murata
Murata
Murata
Murata
GRM21BR60J475K
GRM31MR60J106K
GRM31CR60J226K
CAPACITORS FOR VOLTAGES UP TO 3.3 V(1)
GRM21BR60J106K
10 µF
47 µF
2012 / 0805 (2.0 × 1.25 × 1.25)
3216 / 1206 (3.2 × 1.6 × 1.6)
Murata
Murata
GRM31CR60J476M
(1) The DC bias effect of ceramic capacitors must be considered when selecting a capacitor.
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9.2.3 Application Curves
at TJ = 25°C unless otherwise noted
100%
90
80
70
60
50
40
30
20
10
0
80%
60%
40%
20%
0
VIN = 2.8 V
VIN = 3.6 V
VIN = 5 V
VIN = 2.8 V
VIN = 3.6 V
VIN = 5 V
0
400.001
800.001 1200.001
Output Current (mA)
1600.001
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Output Current (A)
D007
VOUT = 1.1 V
VOUT = 1.2 V
图9-4. DCDC1/DCDC2 Efficiency
图9-5. DCDC3 Efficiency
90%
80%
70%
60%
50%
40%
30%
20%
10%
0
100%
80%
60%
40%
20%
0
VIN = 2.7 V
VIN = 3.6 V
VIN = 5 V
VIN = 2.8 V
VIN = 3.6 V
VIN = 5 V
0
0.2
0.4
0.6
0.8
Output Current (A)
1
1.2
1.4
1.6
1.8
0
0.2
0.4
0.6
Output Current (A)
0.8
1
1.2
1.4
1.6
D009
D010
VOUT = 1.5 V
VOUT = 3.3 V
图9-6. DCDC3 Efficiency
图9-7. DCDC4 Efficiency
90%
85%
80%
75%
70%
65%
60%
55%
50%
45%
DCDC5 (1 V)
DCDC6 (1.8 V)
40%
0
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Output Current (mA)
D011
IN_BU = 0 V
CC = 3 V
图9-8. DCDC5/DCDC6 Efficiency
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10 Power Supply Recommendations
The device is designed to operate with an input voltage supply range between 2.7 V and 5.5 V. This input supply
can be from a single cell Li-Ion battery or other externally regulated supply. If the input supply is located more
than a few inches from the TPS6521815 additional bulk capacitance may be required in addition to the ceramic
bypass capacitors. An electrolytic capacitor with a value of 47 µF is a typical choice.
The coin cell back up input is designed to operate with a input voltage supply between 2.2 V and 3.3 V This input
should be supplied by a coin cell battery with 3-V nominal voltage.
11 Layout
11.1 Layout Guidelines
Follow these layout guidelines:
• The IN_X pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical
recommended bypass capacitance is 4.7-µF with a X5R or X7R dielectric.
• The optimum placement is closest to the IN_X pins of the device. Take care to minimize the loop area formed
by the bypass capacitor connection, the IN_X pin, and the thermal pad of the device.
• The thermal pad should be tied to the PCB ground plane with a minimum of 25 vias. See 图11-2 for an
example.
• The LX trace should be kept on the PCB top layer and free of any vias.
• The FBX traces should be routed away from any potential noise source to avoid coupling.
• DCDC4 Output capacitance should be placed immediately at the DCDC4 pin. Excessive distance between
the capacitance and DCDC4 pin may cause poor converter performance.
11.2 Layout Example
VOUT
Output Filter
Capacitor
Input Bypass
Capacitor
Via to Ground Plane
Via to Internal Plane
IN
Thermal
Pad
图11-1. Layout Recommendation
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s
Recommended Thermal Pad by size
Hole size (s) = 8 mil
Diameter (d) = 16 mil
d
图11-2. Thermal Pad Layout Recommendation
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Basic Calculation of a Buck Converter's Power Stage application report
• Texas Instruments, Design Calculations for Buck-Boost Converters application report
• Texas Instruments, Empowering Designs With Power Management IC (PMIC) for Processor Applications
application report
• Texas Instruments, TPS65218EVM user's guide
• Texas Instruments, TPS65218 Power Management Integrated Circuit (PMIC) for Industrial Applications
application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
Sitara™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS6521815RSLR
TPS6521815RSLT
ACTIVE
ACTIVE
VQFN
VQFN
RSL
RSL
48
48
2500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 105
-40 to 105
T6521815
T6521815
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS6521815RSLR
TPS6521815RSLT
VQFN
VQFN
RSL
RSL
48
48
2500
250
330.0
180.0
16.4
16.4
6.3
6.3
6.3
6.3
1.1
1.1
12.0
12.0
16.0
16.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS6521815RSLR
TPS6521815RSLT
VQFN
VQFN
RSL
RSL
48
48
2500
250
367.0
210.0
367.0
185.0
38.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
A
6.1
5.9
B
PIN 1 INDEX AREA
6.1
5.9
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
4.4
13
24
44X 0.4
12
23
SYMM
49
4.5
4.3
4.4
1
36
0.25
0.15
48X
PIN 1 IDENTIFICATION
(OPTIONAL)
37
48
0.1
C A B
C
SYMM
0.5
0.3
0.05
48X
4219205/A 02/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
(
4.4)
SYMM
48
37
48X (0.6)
48X (0.2)
1
36
44X (0.4)
SYMM
(5.8)
10X (1.12)
49
6X (0.83)
(R0.05) TYP
12
25
13
6X (0.83)
24
(Ø0.2) VIA
10X (1.12)
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
0.05 MAX
0.05 MIN
ALL AROUND
ALL AROUND
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219205/A 02/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RSL0048B
PLASTIC QUAD FLATPACK- NO LEAD
(5.8)
SYMM
48
37
48X (0.6)
48X (0.2)
1
49
36
44X (0.4)
16X
(
0.92)
SYMM
8X (0.56)
(5.8)
8X (1.12)
(R0.05) TYP
12
25
13
8X (1.12)
24
METAL TYP
8X (0.56)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
70% PRINTED COVERAGE BY AREA
SCALE: 12X
4219205/A 02/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2022，德州仪器 (TI) 公司
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