TPS65235-1RUKT [TI]
采用 FCCM 模式且具有 I2C 接口的 LNB 稳压器 | RUK | 20 | -40 to 85;
| 型号： | TPS65235-1RUKT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 采用 FCCM 模式且具有 I2C 接口的 LNB 稳压器 | RUK | 20 | -40 to 85 稳压器 |
| 文件： | 总42页 (文件大小：2186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65235-1
ZHCSG04F –JANUARY 2017 –REVISED MAY 2023
TPS65235-1 LNB 稳压器，具有I2C 接口
1 特性
3 说明
• 用于LNB 和I2C 接口的完整集成解决方案
• 兼容DiSEqC 2.x 和DiSEqC 1.x
• 支持5V、12V 和15V 电源轨
TPS65235-1 专为模拟和数字卫星接收器而设计，是一
款具有I2C 接口的单片稳压器。该器件专用于向碟形天
线中的 LNB 降压转换器或多开关箱提供 13V 至 18V
电源以及 22kHz 音调信号。该器件将极少的组件数、
低功率耗散、简单设计与I2C 标准接口相结合，能够提
供一套完整的解决方案。
• 高达1000mA 的外部电阻器可调精确输出电流限制
• 升压开关峰值电流限制，与LDO 电流限制成正比
• 具有140mΩ低Rds(on) 内部电源开关的升压转换器
• 可选择1MHz 或500kHz 升压开关频率
• 在强制PWM 模式下能避免可闻噪声
• 适用于非I2C 应用的专用使能引脚
• 具有推挽式输出级的低压降(LDO) 稳压器，用于提
供VLNB 输出
• 内置精确的22kHz 音调发生器并支持外部音调输入
• 支持44kHz 和22kHz 外部音调输入
• 可调节软启动和13V 至18V 电压转换时间
• 650mV 至750mV 的22kHz 音调振幅选择
• 通过在EN 为低电平时进行访问的I2C 寄存器
• 短路动态保护
TPS65235-1 具有高功效。该升压转换器集成了一个在
1MHz 或500kHz 可选开关频率下运行的140mΩ功率
MOSFET。线性稳压器中的压降为 0.8V，能够更大限
度地降低功率损耗。TPS65235-1 提供多种方式来生成
22kHz 信号。具有推挽式输出级的集成线性稳压器可
生成 22kHz 音调信号（在输出端叠加），即使在零负
载条件下也是如此。可由外部电阻器以 ±10% 的精度
来设定线性稳压器的电流限值。通过I2C 读取的全范围
诊断可用于系统监控。
TPS65235-1 在 FCCM 模式下具有特殊设计，以避免
可闻噪声，尤其是当VIN 高于或接近VLNB 输出时。
• 输出电压电平、DiSEqC 音调输入和输出、电流电
平以及电缆连接诊断
• 具有过热保护功能
TPS65235-1 支持面向 22kHz 音调检测电路和输出接
口的高级DiSEqC 2.x 标准。
• 20 引脚WQFN 3mm x 3mm (RUK) 封装
封装信息(1)
2 应用
封装尺寸（标称值）
器件型号
TPS65235-1
封装
• 机顶盒卫星接收器
• 电视卫星接收器
• PC 卡卫星接收器
• 卫星电视
RUK（WQFN，20） 3.00mm × 3.00mm
(1) 有关所有的可用封装，请参阅数据表末尾的可订购产品附录。
TPS65235-1
100 nF
VOUT
VLNB
VCP
0.1 mF
ISET
TCAP
AGND
BOOST
PGND
2 ×
22 mF
110 kꢀ
22 nF
10 mH
VIN
LX
VCC
VIN
10 mF
1 mF
1 mF
简化原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSDP1
TPS65235-1
ZHCSG04F –JANUARY 2017 –REVISED MAY 2023
www.ti.com.cn
Table of Contents
7.5 Programming............................................................ 20
7.6 Register Maps...........................................................22
8 Application and Implementation..................................25
8.1 Application Information............................................. 25
8.2 Typical Application.................................................... 25
8.3 Power Supply Recommendations.............................31
8.4 Layout....................................................................... 31
9 Device and Documentation Support............................33
9.1 Device Support......................................................... 33
9.2 Documentation Support............................................ 33
9.3 接收文档更新通知..................................................... 33
9.4 支持资源....................................................................33
9.5 Trademarks...............................................................33
9.6 静电放电警告............................................................ 33
9.7 术语表....................................................................... 33
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................8
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................10
7.4 Device Functional Modes..........................................19
Information.................................................................... 34
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (May 2021) to Revision F (May 2023)
Page
• 通篇更新了公式格式........................................................................................................................................... 1
• Updated the ADDR pin voltage range for I2C address 0x11 in 表7-4 ............................................................. 20
• Changed all instances of legacy terminology to controller and target where I2C is mentioned........................ 20
Changes from Revision D (July 2019) to Revision E (May 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式。..................................................................................... 1
• Changed V(drop) min and max values..................................................................................................................6
• Changed I(rev_dis) min and max values................................................................................................................6
Changes from Revision C (July 2018) to Revision D (July 2019)
Page
• Changed V(drop) at TONEAMP = 0b From: MIN = 0.44 TYP = 0.7 MAX = 1 To: MIN = 0.49 TYP = 0.8 MAX =
1.1 in the Electrical Characteristics ....................................................................................................................6
• Changed V(drop) at TONEAMP = 1b From: MIN = 0.55 TYP = 0.8 MAX = 1.12 To: MIN = 0.65 TYP = 0.9 MAX
= 1.2 in the Electrical Characteristics .................................................................................................................6
Changes from Revision B (June 2018) to Revision C (July 2018)
Page
• Changed the GDR TONE_TRANS = 1b value From: MAX = 24.03V To: MAX = 24.33V in the
Electrical Characteristics ................................................................................................................................... 6
Changes from Revision A (January 2017) to Revision B (December 2017) Page
• Changed bit 4 (T125) in 表7-8 From: 0b = Die temperature > 125°C To: 0b = Die temperature > 125°C and
From: 1b = Die temperature < 125°C To: 1b = Die temperature > 125°C.........................................................24
Changes from Revision * (January 2017) to Revision A (December 2017)
Page
• Changed the VCP values From: VLNB to 7 V To: –0.3 V to 7 V in the Absolute Maximum Ratings ............... 5
• Changed the GDR values From: VLNB to VCP To: –0.3 V to 7 Vin the Absolute Maximum Ratings ..............5
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDP1
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• Changed the A(tone) TONEAMP = 0b values From: MIN = 667 TYP = 700 MAX = 746 To: MIN = 617 TYP =
650 MAX = 696 in the Electrical Characteristics ................................................................................................6
• Changed the A(tone) TONEAMP = 1b values From: MIN = 753 TYP = 800 MAX = 853 To: MIN = 703 TYP =
750 MAX = 803 in the Electrical Characteristics ................................................................................................6
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English Data Sheet: SLVSDP1
TPS65235-1
ZHCSG04F –JANUARY 2017 –REVISED MAY 2023
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5 Pin Configuration and Functions
VLNB
VCP
16
10
9
VCTRL
ADDR
FAULT
EN
17
18
19
20
Thermal
Pad
BOOST
GDR
8
7
PGND
6
ISET
Not to scale
图5-1. RUK Package 20-Pin WQFN With Exposed Thermal Pad Top View
表5-1. Pin Functions
PIN
NAME
TYPE(1)
DESCRIPTION
NO.
1
LX
I
Switching node of the boost converter
Input of internal linear regulator
2
VIN
S
Internal 6.3-V power supply. Connect a 1-μF ceramic capacitor from this pin to ground. When VIN is 5 V,
connect the VCC pin to the VIN pin.
3
VCC
O
4
5
6
AGND
TCAP
ISET
S
O
O
Analog ground. Connect all ground pins and power pad together.
Connect a capacitor to this pin to set the rise time of the LNB output.
Connect a resistor to this pin to set the LNB output current limit.
Enable this pin to enable the VLNB output. pull this pin to ground to disable the output. The output is then
pulled to ground, and, when the EN pin is low, the I2C interface can be accessed.
7
EN
I
8
FAULT
ADDR
VCTRL
SDA
O
Open drain output pin, it goes low if any fault flag is set.
Connect a different resistor to this pin to set different I2C addresses (see the 表7-4 table).
Voltage level at this pin to set the output voltage (see the 表7-3).
I2C compatible bidirectional data
9
I
I
10
11
12
I/O
I
SCL
I2C compatible clock input
External modulation logic input pin that activates the 22-kHz tone output. The feeding signal can be 22-
kHz tone or logic high or low.
13
EXTM
I
14
15
16
DOUT
DIN
O
I
Tone detection output
Tone detection input
VLNB
O
Output of the power supply connected to satellite receiver or switch
Gate drive supply voltage and output of charge pump. Connect a capacitor between this pin and the VLNB
pin.
17
VCP
O
18
19
20
BOOST
GDR
O
O
S
Output of the boost regulator and Input voltage of the internal linear regulator
Control the gate of the external MOSFET for DiSEqc 2.x support
Power ground for the boost converter
PGND
The thermal pad must be soldered to the printed circuit board (PCB) for optimal thermal performance. Use
thermal vias on the PCB to enhance power dissipation.
Thermal Pad
—
—
(1) I = input, O = output, I/O = input and output, S = power supply
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLVSDP1
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
1
MAX
30
UNIT
VIN, LX, BOOST, VLNB
VCP, GDR (referenced to VLNB pin)
7
–0.3
VCC, EN, ADDR, FAULT, SCL, SDA, VCTRL, EXTM, DOUT, DIN,
TCAP
7
Voltage
–0.3
V
ISET
3.6
0.3
–0.3
–0.3
–40
–55
PGND
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
NOM
MAX
20
UNIT
V
VIN
TA
Input operating voltage
Operating junction temperature
125
°C
–40
6.4 Thermal Information
TPS65235-1
RUK (WQFN)
20 PINS
44.8
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
47.3
16.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJT
16.4
ψJB
RθJC(bot)
3.6
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
–40°C ≤TJ ≤125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input voltage range
4.5
90
12
120
5
20
150
8.5
V
IDD(SDN)
ILDO(Q)
Shutdown supply current
LDO quiescent current
EN = 0b
µA
mA
V
EN = 1b, IO = 0 A, VVLNB = 18.2 V
VIN rising
1.5
4.15
280
4.3
480
4.45
550
UVLO
VIN undervoltage lockout
Hysteresis
mV
OUTPUT VOLTAGE
V(ctrl) = 1, IO = 500 mA
V(ctrl) = 0, IO = 500 mA
18
18.2
13.4
18.4
V
V
13.25
13.55
SCL = 1b, V(ctrl) = 1, IO = 500 mA (Non
I2C)
VOUT
Regulated output voltage
19.18
14.44
19.4
14.6
19.62
14.76
V
V
SCL = 1b, V(ctrl) = 0, IO = 500 mA (Non
I2C)
580
629
977
650
650
720
688
mA
mA
kHz
R(SET) = 200 kΩ, Full temperature
TJ = 25°C
I(OCP)
Output short circuit current limit
fSW
Boost switching frequency
Switching current limit
f = 1 MHz
1060
1134
VIN = 12 V, VOUT = 18.2 V, R(SET) = 200
kΩ
(1)
I(limitsw)
3
A
Rds(on)_LS
V(drop)
On resistance of low side FET
VIN = 12 V
90
0.44
0.55
0.9
140
0.8
0.9
5
210
1.15
1.2
8.8
65
mΩ
V
IO = 500 mA, TONEAMP = 0b
IO = 500 mA, TONEAMP = 1b
VIN = 12 V, VOUT = 13.4 V or 18.2 V
EN = 1b, VVLNB = 21 V
Linear regulator voltage dropout
V
I(cable)
I(rev)
Cable good detection current threshold
Reverse bias current
mA
mA
mA
49
58
I(rev_dis)
Disabled reverse bias current
EN = 0b, VVLNB = 21 V
2.9
4.6
6.3
LOGIC SIGNALS
Enable threshold (V(EN)), high
1.6
V
V
Enable threshold (V(EN)), low
0.8
7
V(EN) = 1.5 V
V(EN) = 1 V
5
2
6
3
µA
µA
I(EN)
Enable internal pullup current
4
VCTRL logic threshold level for high-level
input voltage
V(VCTRL_H)
V(VCTRL_L)
V(EXTM_H)
V(EXTM_L)
2
V
V
V
VCTRL logic threshold level for low-level
input voltage
0.8
EXTM logic threshold level for high-level
input voltage
2
EXTM logic threshold level for low-level
input voltage
0.8
0.4
V
V
VOL(FAULT)
TONE
FAULT output low voltage
FAULT open drain, IOL = 1 mA
22-kHz tone output
f(tone)
Tone frequency
20
22
24
kHz
mV
0 mA ≤IO ≤500 mA, CO = 100 nF,
TONEAMP = 0b
617
650
696
A(tone)
Tone amplitude
0 mA ≤IO ≤500 mA, CO = 100 nF,
TONEAMP = 1b
703
750
803
mV
D(tone)
f(EXTM)
Tone duty cycle
45%
17.6
35.2
50%
22
55%
26.4
52.8
22-kHz tone output
44-kHz tone output
kHz
kHz
External tone input frequency range
44
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English Data Sheet: SLVSDP1
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–40°C ≤TJ ≤125°C, VIN = 12 V, fSW = 1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TONE DETECTION
f(DIN)
Tone detector frequency capture range
Tone detector input amplitude
DOUT output voltage
0.4-VPP sine wave
17.6
0.3
22
26.4
1.5
kHz
V
V(DIN)
V(DOUT)
Sine wave, 22 kHz
Tone present, Iload = 2 mA
0.4
V
TONE_TRANS = 1b, V(LNB) = 18.2 V
TONE_TRANS = 0b, V(LNB) = 18.2 V
23.11
18.17
23.5
18.2
24.33
18.23
V
GDR
Bypass FET gate voltage, LNB
V
THERMAL SHUT-DOWN (JUNCTION TEMPERATURE)
T(TRIP)
Thermal protection trip point
Thermal protection hysteresis
Temperature rising
160
20
°C
°C
T(HYST)
I2C READ BACK FAULT STATUS
Feedback voltage UVP low
Feedback voltage UVP high
Feedback voltage OVP high
Feedback voltage OVP low
94%
93%
96%
94.5%
106.6%
104.6%
125
97.1%
95.5%
108%
106%
V(PGOOD)
PGOOD trip levels
104%
102%
T(warn)
Temperature warning threshold
°C
I2C INTERFACE
VIH
VIL
II
SDA,SCL input high voltage
2
–10
400
V
V
SDA,SCL input low voltage
Input current
0.8
10
µA
V
SDA, SCL, 0.4 V ≤VI ≤4.5 V
VOL
f(SCL)
SDA output low voltage
Maximum SCL clock frequency
SDA open drain, IOL = 2 mA
0.4
kHz
(1) Specified by design
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6.6 Timing Requirements
MIN
NOM
MAX
UNIT
OUTPUT VOLTAGE
tr, tf
13-V to 18-V transition rising falling time
Minimum on time for the Low side FET
C(TCAP) = 22 nF
2
ms
ns
tON(min)
TONE
75
102
130
Tone rise time
Tone fall time
0 mA ≤IO ≤500 mA, CO = 100 nF,
Control Reg1[0] = 0b
11
5.5
µs
µs
µs
µs
tr(tone)
0 mA ≤IO ≤500 mA, CO = 100 nF,
Control Reg1[0] = 1b, and EXTM has
44-kHz input
0 mA ≤IO ≤500 mA, CO = 100 nF,
Control Reg1[0] = 0b
10.8
5.4
tf(tone)
0 mA ≤IO ≤500 mA, CO = 100 nF,
Control Reg1[0] = 1b, and EXTM has
44 kHz input
OVERCURRENT PROTECTION
tON
Overcurrent protection ON time
Overcurrent protection OFF time
TIMER = 0b
TIMER = 0b
2.3
3.75
118
5.52
ms
ms
tOFF
98.5
133.5
I2C INTERFACE
Bus free time between a STOP and START
condition
tBUF
1.3
µs
tHD_STA
tSU_STO
tLOW
Hold time (repeated) START condition
Setup time for STOP condition
LOW period of the SCL clock
HIGH period of the SCL clock
Setup time for a repeated START condition
Data setup time
0.6
µs
µs
µs
µs
µs
µs
µs
ns
0.6
1
tHIGH
0.6
tSU_STA
tSU_DAT
tHD_DAT
tRCL
0.6
0.1
0
Data hold time
0.9
Rise time of SCL signal
Capacitance of one bus line (pF)
20 + 0.1 CB
300
Rise time of SCL Signal after a Repeated START Capacitance of one bus line (pF)
condition and after an acknowledge BIT
tRCL1
20 + 0.1 CB
300
ns
tFCL
tRDA
tFDA
CB
Fall time of SCL signal
Capacitance of one bus line (pF)
Capacitance of one bus line (pF)
Capacitance of one bus line (pF)
20 + 0.1 CB
20 + 0.1 CB
20 + 0.1 CB
300
300
300
400
ns
ns
ns
pF
Rise time of SDA signal
Fall time of SDA signal
Capacitance of one bus line(SCL and SDA)
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English Data Sheet: SLVSDP1
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6.7 Typical Characteristics
TA = 25°C, VIN = 12 V, fSW = 1 MHz, CBoost = (2 × 22 µF / 35 V) (unless otherwise noted)
95%
90%
85%
80%
75%
70%
65%
60%
13.45
13.44
13.43
13.42
13.41
13.4
13.39
13.38
13.37
13.36
13.35
V(LNB) = 13.4 V
V(LNB) = 18.2 V
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
D002
D001
VVLNB = 13.4 V
L = 4.7 µH
图6-2. Load Regulation
图6-1. Power Efficiency
18.3
18.28
18.26
18.24
18.22
18.2
7
6.5
6
5.5
5
18.18
18.16
18.14
18.12
18.1
4.5
4
3.5
3
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Output Current (A)
1
-40
-20
0
20
40
60
80
100 120 140
D003
Junction Temperature (èC)
D004
VVLNB =18.2 V
图6-4. Input Supply Quiescent Current vs Junction
图6-3. Load Regulation
Temperature
135
130
125
120
115
110
105
680
670
660
650
640
630
620
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Junction Temperature (èC)
Junction Temperature (èC)
D005
D006
ILOAD = 650 mA
图6-5. Shutdown Current vs Junction Temperature
图6-6. LNB Current Limit vs Junction Temperature
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7 Detailed Description
7.1 Overview
The TPS65235-1 device is the power management IC (PMIC) that integrates a boost converter, an LDO
regulator, and a 22-kHz tone generator to serve as a LNB power supply. This solution compiles the DiSEqC 2.x
standard with or without I2C interface. An external resistor allows for precise programming of the output current
limit. The 22-kHz tone signal can be generated in one of two ways, either with or without I2C. The integrated
boost features low Rds(on) MOSFET and internal compensation. A selectable switching frequency of 1 MHz or
500 kHz is designed to reduce the size of passive components and be flexible for design.
The TPS65235-1 device can support the 44-kHz tone output. When the EXTM pin has a 44-kHz tone input, and
the EXTM TONE bit in the Control Register 1 is set to 1b, the LNB tone output is 44 kHz. By default, the
TPS65235-1 device has a typical 22-kHz tone output.
7.2 Functional Block Diagram
EN
REF_Boost
Internal Regulator
VCC
PWM Controller
PGND
REF_Boost
TCAP
BOOST
VCP
REF
VCTRL
Charge Pump
VLNB
REF_LDO
SDA
SCL
I2C Interface
I2C EN
ADDR
EN
Tone
Generator
VLNB
OCP
OTP
Tone_Auto
Tone_Trans
EXTM
Fault Diagnose
PGOOD
GDR
DIN
Logic
Tone
Det
7.3 Feature Description
7.3.1 Boost Converter
The TPS65235-1 device has an internal compensated boost converter and low-dropout (LDO) linear regulator.
The boost converter tracks the LNB output voltage within 800 mV even at loading 1000 mA, which minimizes
power loss.
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The boost converter operates at 1 MHz by default. The TPS65235-1 device has internal cycle-by-cycle peak
current limit in the boost converter and DC current limit in the LNB output to help protect the device from short
circuits and over loading. When the LNB output is shorted to ground, the LNB output current is clamped at the
LDO current limit. The LDO current limit is set by the external resistor at the ISET pin. The current limit of the
boost switch is proportional to the LDO current limit. If an overcurrent condition occurs for more than 4 ms, the
boost converter enters hiccup mode and retries startup in 128 ms. This hiccup mode ON time and OFF time are
selectable through the I2C control register (address 0x01) to be either 4 ms and 128 ms or 8 ms and 256 ms,
respectively. At extremely light loads, the boost converter automatically operates in a pulse-skipping mode.
The boost converter is stable with either ceramic capacitor or electrolytic capacitor.
If two or more set-top box LNB outputs are connected together, one output voltage can be set higher than
others. The output with the lower set voltage is then effectively turned off. When the voltage drops to the set
level, the LNB output with the lower set output voltage returns to normal conditions.
7.3.2 Linear Regulator and Current Limit
The linear regulator is used to generate the 22-kHz tone signal by changing the LDO reference voltage. The
linear regulator features low-dropout voltage to minimize power loss while maintaining enough head room for the
22-kHz tone with 650-mV amplitude. The linear regulator also implements a tight current limit for overcurrent
protection. The current limit is set by an external resistor connected to ISET pin. 图 7-1 shows the relationship
between the current limit threshold and the resistor value.
550
y = 117.08x-1.267
500
450
400
350
300
250
200
150
100
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
ISET (A)
D007
图7-1. Linear Regulator Current Limit Vs Resistor
−1.267
R
kΩ = 117.08 × I
A
(1)
SET
SET
A 200-kΩresistor sets the current to 0.65 A, and 110-kΩresistor sets the current to approximately 1 A.
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7.3.3 Boost Converter Current Limit
The boost converter has the cycle-by-cycle peak current limit on the internal Power MOSFET switch to serve as
the secondary protection when LNB output is hard short. With ISW bit default setting 0b on I2C control register
0x01, the switch current limit ISW is proportional as LDO current limit I(OCP) set by ISET pin resistor, and the
relationship can be expressed as:
I
= 3 × I
+ 0.8 A
OCP
(2)
SW
For the 5 V VIN, if LNB current load is up to 1 A, the ISW bit must be written as 1b, the switch current limit ISW for
the internal Power MOSFET is:
I
= 5 × I
+ 0.8 A
OCP
(3)
SW
While due to the high power loss at 5 V, VIN, it has a chance to trigger the thermal shutdown before the loading is
up to 1 A, especially the VLNB output is high.
7.3.4 Charge Pump
The charge pump circuitry generates a voltage to drive the NMOS of the linear regulator. The voltage across the
charge pump capacitor between VLNB and VCP is about 5.4 V, so the absolute value of the VCP voltage will be
VLNB + 5.4 V.
7.3.5 Slew Rate Control
When LNB output voltage transits from 13.4 V to 18.2 V or 18.2 V to 13.4 V , the cap at pin TCAP controls the
transition time. This transition time makes sure the boost converter output to follow LNB output change. Usually
boost converter has low bandwidth and can’t response fast. The voltage at TCAP acts as the reference voltage
of the linear regulator. The boost converter’s reference is also based on TCAP with additional fixed voltage to
generate a 0.8 V above the LNB output.
The charging and discharging current is 10 µA, thus the transition time can be estimated as:
C
I
nF
μA
SS
t
ms = 0.8 ×
(4)
TCAP
SS
A 22-nF capacitor generates about 2 ms transition time.
In light load conditions, when LNB output voltage is set from 18.2 V to 13.4 V, the voltage drops very slow, which
causes wrong VOUT_GOOD (Bit 0 at status register 0x02) logic for LNB output voltage detection. TPS65235-1
has integrated a pull down circuit to pull down the output during the transition. This ensures the voltage change
can follow the voltage at TCAP. When the 22-kHz tone signal is superimposing on the LNB output voltage, the
pull down current can also provide square wave instead of a distorted waveforms.
7.3.6 Short-Circuit Protection, Hiccup, and Overtemperature Protection
The LNB output current limit can be set by an external resistor. When short circuit conditions occur or current
limit is triggered, the output current is clamped at the current limit for 4 ms with LDO on. If the condition retains,
the converter will shut down for 128 ms and then restart. This hiccup behavior prevents IC from being overheat.
The hiccup ON/OFF time can be set by I2C register. Refer to Control Register 1 for detail.
The low side MOSFET of the boost converter has a peak current limit threshold which serves as the secondary
protection. If boost converter’s peak current limit is triggered, the peak current will be clamped as high as 3.8 A
when setting ISW default and LNB current limit up to 1 A. If loading current continues to increase, output voltage
starts to drop and output power drops.
Thermal shutdown prevents the chip from operating at exceedingly high temperatures. When the junction
temperature exceeds 160°C, the output shuts down. When the die temperature drops below its lower threshold
typically 140°C, the output is enabled.
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When the chip is in overcurrent protection or thermal shutdown, the I2C interface and logic are still active. The
FAULT pin is pulled down to signal the processor. The FAULT pin signal remains low unless the following action
is taken:
1. If I2C interface is not used to control, EN pin must be recycled to pull the FAULT pin back to high.
2. If I2C interface is used, the I2C controller must read the status Control Register 2, then the FAULT pin is back
to high.
7.3.7 Tone Generation
A 22-kHz tone signal is implemented at the LNB output voltage as a carrier for DiSEqC command. This tone
signal can be generated by feeding an external 22-kHz clock at the EXTM pin, and it can also be generated with
its internal tone generator controlled by EXTM pin. If EXTM pin is toggled to high, the internal tone signal will be
superimposed at the LNB output, if EXTM pin is low, there will be no tone superimposed at the output stage of
the regulator facilitates a push-pull circuit, so even at zero loading; the 22-kHz tone at the output is still clean
without distortion.
There are two ways to generate the 22-kHz tone signal at the output.
For option1, if the EXTM has 44-kHz tone input, and the bit EXTM TONE of the Control Register 1 is set to 1b,
the LNB tone output is 44 kHz.
EXTM
TONE
VLNB(V)
Option 1. Use external tone, gated by EXTM logic pulse
EXTM
TONE
VLNB(V)
Option 2. Use internal tone, gated by EXTM logic envelop
图7-2. Two Ways to Generate 22-kHz tone
7.3.8 Tone Detection
A 22-kHz tone detector is implemented in the TPS65235-1 solution. The detector extracts the AC-coupled tone
signal from the DIN input and provides it as an open-drain signal on the DOUT pin. When the DOUTMODE bit in
the Control Register 2 is set to the default setting, if a tone is present, the DOUT output is logic low. If a tone is
not present, the internal output FET is off. If a pullup resistor is connected to the DOUT pin, the output is logic
high. The maximum tone out delay with respect to the input is one and a half of the tone cycle.
The DOUTMODE bit in the Control Register 2 is reserved and must not be used.
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7.3.9 Audio Noise Rejection
When the TPS65235-1 operates in PSM mode, locating the switching frequency at the range of audio frequency
is possible. Which causes audible noise, especially when the VLNB voltage is lower or closer to the VIN voltage,
and the current load is light.
When audible noise occurs, TI recommends setting the TPS65235-1 device to operate in force PWM mode. In
force PWM mode, a special design is implemented to avoid the audible noise.
7.3.10 Disable and Enable
The TPS65235-1 device has a dedicated EN pin to disable and enable the LNB output. In a non-I2C application,
when the EN pin is pulled high, the LNB output is enabled. When the EN pin is pulled low, the LNB output is
disabled. In an I2C application, when the EN pin is either low or high, the I2C registers can be accessed, which
allows users to change the default LNB output at system power-up. When the I2C_CON bit in the Control
Register 1 is set to 1b, the LNB output enable or disable is controlled by the EN bit in the Control Register 2. By
default, the I2C_CON bit of the control register is set to 0b, which makes the LNB output is controlled by the EN
pin. 图7-3 and 图7-4 shows the detailed control behavior.
V(EN) = 0 V
I2C_CON = 1b
I2C_CON = 0b
图7-3. VLNB Output Controlled by bit EN of
图7-4. VLNB Output Controlled by EN Pin
Control Register 2
7.3.11 Component Selection
7.3.11.1 Boost Inductor
TI recommends the TPS65235-1 device to operate with a boost inductor value of 4.7 µH or 10 µH. The boost
inductor must be able to support the peak current requirement to maintain the maximum LNB output current
without saturation. Use 方程式5 to estimate the peak current of the boost inductor (Ipeak).
I
V
× D
OUT
1
2
IN
L × f
I
=
+
×
(5)
peak
1 − D
S
where
V
IN
D = 1-
VLNB + 0.8
With a different inductance, the system has different gain and phase margins. 图 7-5 shows a Bode plot of boost
loop with 2 × 10 µF / 35 V of boost capacitor and 4.7 µH, 5.6 µH, 6.8 µH, 8.2 µH, and 10 µH of boost inductance.
As the boost inductance increases, the 0-dB crossover frequency keeps relatively constant while reducing the
phase and gain margins. With a 4.7-µH boost inductance, the phase margin is 66.96° and with a 10-µH
inductance, the phase margin is 39.63°.
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4.7 mH
5.6 mH
6.8 mH
8.2 mH
10 mH
4.7 mH, 66.96 deg
10 mH, 39.63 deg
4.7 mH
5.6 mH
6.8 mH
8.2 mH
10 mH
图7-5. Gain and Phase Margin of the Boost Loop with Different Inductance (VIN = 12 V, VOUT = 18.2 V,
ILOAD = 1 A, fSW = 1 MHz, 5 µF, Typical Bode Plot)
7.3.11.2 Capacitor Selection
The TPS65235-1 device has a 1-MHz nonsynchronous boost converter integrated and the boost converter
features the internal compensation network. The TPS65235-1 device works well with both ceramic capacitor and
electrolytic capacitor.
The recommended ceramic capacitors for the TPS65235-1 application are, at the minimum, rated as X7R/X5R,
with a 35-V rating, and a 1206 size for the achieving lower LNB output ripple. 表 7-1 lists the recommended
ceramic capacitors list for both 4.7-µH and 10-µH boost inductors.
If more cost-effictive design is needed, use a 100-µF electrolytic (low ESR) and a 10-µF or 35-V ceramic
capacitor.
表7-1. Boost Inductor and Capacitor Selections
BOOST INDUCTOR
CAPACITORS
2 × 22 µF
2 × 10 µF
2 × 22 µF
2 × 10 µF
22 µF
TOLERANCE (%)
RATING (V)
SIZE
1206
1206
1206
1206
1206
±10
±10
±10
±10
±10
35
35
35
35
35
10 µH
4.7 µH
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图 7-6 and 图 7-7 show a bode plot of boost loop with 4.7-µH and 10-µH inductance and 4 µF, 5 µF, 7.5 µF, 10
µF, 15 µF, and 20 µF of boost capacitance after degrading. As the boost capacitance increases, the phase
margin increases.
4 mF
4 mF
5 mF
7.5 mF
10 mF
20 mF
15 mF
20 mF
4 mF, 57.45 deg
20 mF, 84.49 deg
4 mF
5 mF
7.5 mF
10 mF
15 mF
20 mF
图7-6. Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT
=
18.2 V, ILOAD = 1 A, fSW = 1 MHz, 4.7 µH, Typical Bode Plot)
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5 mF
7.5 mF
10 mF
15 mF
20 mF
5 mF
20 mF
5 mF, 37.23 deg
20 mF, 78.74 deg
5 mF
7.5 mF
10 mF
15 mF
20 mF
图7-7. Gain and Phase Margin of the Boost Loop With Different Boost Capacitance (VIN = 12 V, VOUT
=
18.2 V, ILOAD = 1 A, fSW = 1 MHz, 10 µH, Typical Bode Plot)
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7.3.11.3 Surge Components
If a surge test is required for the application, the D0 and D2 diodes must be added as the external protection
components. If no surge test is required, remove the D0 and D2 diodes.表 7-2 lists the recommended surge
components.
表7-2. Surge Components
DESIGNATOR
DESCRIPTION
PART NUMBER
MANUFACTURER (1)
Fairchild Semiconductor
Diodes Inc.
D0
D2
Diode, TVS, Uni, 28 V, 1500 W, SMC
Diode, Schottky, 40 V, 2 A, SMA
SMCJ28A
B240A-13-F
(1) See Third-party Products Disclaimer
100 nF 0.1 µF
16 VLNB
VOUT
D3
D0
D2
17
VCP
BOOST
18
19
20
GDR
2x22 µF
TPS65235-1
D1
PGND
1
2
10 µH
VIN
10 µF
1 µF
图7-8. Surge Components Selection
7.3.11.4 Consideration for Boost Filtering and LNB Noise
Smaller capacitance on the BOOST pin reduces the cost of the system. However, when the inductor in system is
the same, the smaller capacitance on the boost and the larger ripple on the LNB output.
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7.4 Device Functional Modes
表7-3 is the logic table for the device.
表7-3. Logic table
EN
H
I2C_CON(1) (2) (3)
SCL
VCTRL
VLNB(4)
19.4 V
14.6 V
18.2 V
13.4 V
0
0
0
0
H
H
L
H
H
H
L
H
L
H
L
Controlled by VSET[3:0]
bits at 0x01 register(5)
X
L
1
0
X
X
X
X
0 V
(1) I2C_CON is the bit7 of the I2C control register 0x01, which is used to set the VLNB output controlled by the I2C register or not.
(2) When I2C interface is used in design, all the I2C registers are accessible even if the I2C_CON bit is 0b.
(3) When I2C_CON is 1b, the VLNB output is controlled by the I2C control register even if the EN pin is low.
(4) When I2C interface is used in design, TI recommends to set the I2C_CON with 1b, if not, the LNB output will be variable because the
SCL is toggled by the I2C register access as the clock signal.
(5) Bit EN of the control register2 is used to disable or enable the LNB output, by default , the bit EN is 1b which enable the LNB output
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7.5 Programming
7.5.1 Serial Interface Description
I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the
bus is idle, both SDA and SCL lines are pulled high external. All the I2C compatible devices connect to the I2C
bus through open drain I/O pins, SDA and SCL. A controller device, usually a microcontroller (MCU) or a digital
signal processor (DSP), controls the bus. The controller device is responsible for generating the SCL signal and
device addresses. The controller device also generates specific conditions that indicate the START and STOP of
data transfer. A target device receives, transmits data, or both on the bus under control of the controller device.
The TPS65235-1 device works as a target and supports the following data transfer modes, as defined in the
I2CBus Specification: standard mode (100 kbps), and fast mode (400 kbps). The interface adds flexibility to the
power supply solution, enabling most functions to be programmed to new values depending on the
instantaneous application requirements. Register contents remain intact as long as supply voltage remains
above 4.5 V (typical).
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as
F/S-mode in this document. The TPS65235-1 device supports 7-bit addressing; 10-bit addressing and general
call address are not supported.
The TPS65235-1 device has a 7-bit address set by ADDR pin. 表7-4 shows how to set the I2C address.
表7-4. I2C Address Selection
ADDR PIN
I2C ADDRESS
ADDRESS FORMAT (A6 ≥A0)
Connect to VCC
Floating
0x08
000 1000b
0x09
000 1001b
Connected to GND
0x10
001 0000b
Resistor divider to make ADDR pin voltage in 3.7 V - 5.9 V
0x11
001 0001b
SDA
tSU, STA
tHD, STA
tBUF
tSU, STO
tSU, DAT
tHD, DAT
tLOW
SCL
tHD, STA
tHIGH
tSP
Start
Condition
Repeated Start
Condition
Stop Start
Condition Condition
tr
tf
图7-9. I2C Interface Timing Diagram
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7.5.2 TPS65235-1 I2C Update Sequence
The TPS65235-1 requires a start condition, a valid I2C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, TPS65235-1 device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. TPS65235-1 performs an update on the falling edge of the LSB
byte.
When the TPS65235-1 is disabled (EN pin tied to ground) the device cannot be updated via the I2C interface.
7-Bit Target Address
S
0
A
A
A
P
Register Address
Data Byte
A6….A0
图7-10. I2C Write Data Format
7-Bit Target Address
S
0
A
A
Sr
1
A
Register1 Address
7-Bit Target Address
A6….A0
N
P
Data Byte
A: Acknowledge
N: Not Acknowledge
S: Start
System Host
Chip
P: Stop
Sr: Repeated Start
图7-11. I2C Read Data Format
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7.6 Register Maps
7.6.1 Control Register 1 (address = 0x00) [reset = 0x08]
图7-12. Control Register 1
7
6
5
4
3
2
1
0
I2C_CON
R/W-0b
PWM/PSM
R/W-0b
RESERVED
R/W-0b
VSET[3:0]
EXTM TONE
R/W-0b
R/W-0100b
表7-5. Control Register 1
Bit
Field
I2C_CON
Type
Reset
Description
0b = I2C control disabled
1b = I2C control enabled
7
R/W
0b
0b = PSM at light load
1b = Forced PWM
6
PWM/PSM
R/W
R/W
0b
0b
5
RESERVED
VSET[3:0]
Reserved
4-1
LNB output voltage selection
0000b = 11 V
0001b = 11.6 V
0010b = 12.2 V
0011b = 12.8 V
0100b = 13.4 V
0101b = 14 V
0110b = 14.6 V
0111b = 15.2 V
1000b = 15.8 V
1001b = 16.4 V
1010b = 17 V
R/W
0100b
1011b = 17.6 V
1100b = 18.2 V
1101b = 18.8 V
1110b = 19.4 V
1111b = 20 V
0b = EXTM 44-kHz tone input not support, with only 22-kHz tone
output at VLNB
0
EXTM TONE
R/W
0b
1b = EXTM 44-kHz tone input support, with 44-kHz tone output
at VLNB
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7.6.2 Control Register 2 (address = 0x01) [reset = 0x09]
图7-13. Control Register 2
7
6
5
4
3
2
1
0
TONEAMP
R/W-0b
TIMER
R/W-0b
ISW
FSET
R/W-0b
EN
DOUTMODE
R/W-0b
TONE_AUTO TONE_TRANS
R/W-0b R/W-1b
R/W-0b
R/W-1b
表7-6. Control Register 2
Bit
Field
TONEAMP
Type
Reset
Description
0b = 22-kHz tone amplitude is 650 mV (typ)
1b = 22-kHz tone amplitude is 750 mV (typ)
7
R/W
0b
0b = Hiccup ON time set to 4 ms and OFF time set to 128 ms
1b = Hiccup ON time set to 8 ms and OFF time set to 256 ms
6
5
TIMER
ISW
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
1b
0b
0b = Boost switch peak current limit set to 3 × IOCP + 0.8 A
1b = Boost switch peak current limit set to 5 × IOCP + 0.8 A
4
3
2
1
FSET
0b = 1-MHz switching frequency
1b = 500-kHz switching frequency
EN
0b = LNB output disabled
1b = LNB output voltage Enabled
DOUTMODE
TONE_AUTO
0b = DOUT is kept to low when DIN has the tone input
1b = Reserved, cannot set to 1b
0b = GDR (External bypass FET control) is controlled by
TONE_TRANS
R/W
R/W
0b
1b
1b = GDR (External bypass FET control) is automatically
controlled by 22-kHz tones transmit
0b = GDR output with VLNB voltage for tone receive. Bypass
FET is OFF for tone receiving from satellite
0
TONE_TRANS
1b = GDR output with VCP voltage. Bypass FET is ON for tone
transmit from TPS65235-1
表7-7. 22-kHz Tone Receive Mode Selection
TONE_AUTO
TONE_TRANS
BYPASS FET
OFF
0b
0b
1b
0b
1b
x
ON
Auto Detect
The TPS65235-1 has full range of diagnostic flags for operation and debug. Processor can read the status
register to check the error conditions. After the error happens, the flags are changed, once the errors are gone,
the flags are set back without I2C access.
If the TSD and OCP flags are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to
processor. After TSD and OCP are set to 1b, the FAULT pin logic is latched to low, processor must read this
status register to release the fault conditions.
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7.6.3 Status Register (address = 0x02) [reset = 0x29]
图7-14. Status Register
7
6
0
5
4
3
2
1
0
Reserved
R-0b
LDO_ON
R-0b
T125
R-0b
TSD
R-1b
OCP
R-0b
CABLE_GOOD VOUT_GOOD
R-0b R-1b
R-0b
表7-8. Status Register
Bit
Field
Reserved
Type
Reset
Description
7
R
0b
Reserved
0b = 22-kHz tone detected on DIN pin is out of range
1b = 22-kHz tone detected on DIN pin is in range
6
5
TDETGOOD
LDO_ON
R
R
R
0b
1b
0b
0b = Internal LDO is turned off but boost converter is on
1b = Internal LDO is turned on and boost converter is on
4
3
T125
TSD
0b = Die temperature < 125°C
1b = Die temperature > 125°C
0b = No thermal shutdown triggered
1b = Thermal shutdown triggered. The FAULT pin logic is
latched to low, processor must read this register to release the
fault conditions
R
R
1b
0b
2
OCP
0b = Overcurrent protection conditions released
1b = Overcurrent protection triggered. The FAULT pin logic is
latched to low, processor must read this register to release the
fault conditions
1
0
CABLE_GOOD
VOUT_GOOD
0b = Cable not connected
1b = Cable connection good
R
R
0b
1b
0b = LNB output voltage out of range
1b = LNB output voltage in range
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8 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers must validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The TPS65235 supports both DisEqc1.x and DisEqc2.x application. When the input voltage VIN is greater than
the expected output voltage VLNB, the linear regulator drops the voltage difference between VIN and VLNB,
which causes the lower efficiency and the higher power loss on the internal linear regulator if the current loading
is high. For care must be taken to ensure that the safe operating temperature range of the TPS65235-1 is not
exceeded. TI recommends operating the device in force PWM mode when VIN > VOUT to reduce output ripple.
8.2 Typical Application
8.2.1 DiSEqc1.x Support
TPS65235-1 can operate in I2C and non-I2C interface mode. 图 8-1 shows the application with the device in I2C
interface mode to support DiSEqC 1.x application. In non-I2C mode, the SCL, SDA, and ADDR pins can be
floating.
15
14
13
11
12
0.1 mF
100 nF
VOUT
16 VLNB
10
9
VCTRL
D0
17
VCP
ADDR
10 kꢀ
FAULT
8
TPS65235-1
BOOST
18
19
20
2 ×
22 mF
EN
7
GDR
ISET
6
PGND
110 kꢀ
1
2
3
4
5
10 mH
VIN
1 mF
22 nF
10 mF
1 mF
1 mF
图8-1. Application for DiSEqc1.x Support
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8.2.1.1 Design Requirements
For this design example, use the parameters in 表8-1.
表8-1. Design Parameters
PARAMETER
VALUE
Input voltage range, VIN
Output voltage range VLNB
Output current range
4.5 V to 20 V
11 V to 20 V
0 A to 1 A
8.2.1.2 Detailed Design Procedure
To begin the design process, the following component values must be selected:
• Inductor
– Choose the appropriate value of the inductor based on application cost requirements, ripple requirements,
and 节7.3.11.
• BOOST capacitor
– Choose the appropriate BOOST capacitor value based on application cost requirements, ripple
requirements, and 节7.3.11.
• Diodes
– The D0 and D2 diodes are used to help meet the surge-protection requirement of the application. If the
application does not require surge protection, remove these diodes. For diode component selection, refer
to 节7.3.11.3.
– The D1 diode is used for the boost loop. TI recommends a Schottky diode for D1. The application
requirements, which include input power range, output power range, and the current requirement,
determine the current and voltage capability of the D1 diode.
– The D3 diode is to help with the output protection for the VLNB voltage. TI recommends a Schottky diode
for D3. The application requirements determine the current and voltage capability of the D3 diode.
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8.2.1.3 Application Curves
TA = 25°C, VIN = 12 V, fSW = 1 MHz, CBoost = (2 × 22 µF / 35 V) (unless otherwise noted)
VVLNB = 13.4 V
VVLNB = 13.4 V
图8-2. Soft Start, Delay from EN High to LNB
图8-3. Disabled, Delay from EN Low to LNB Output
Output High
Low
VVLNB = 18.2 V
VVLNB = 18.2 V
图8-5. Disabled, Delay From EN Low to LNB
图8-4. Soft-Start, Delay from EN High to LNB
Output Low
Output High
EN = 0b
VVLNB =13.4 V
EN = 0b
VVLNB = 13.4 V
图8-6. Soft Start, Delay From I2C Enable (I2C_CON 图8-7. Delay From I2C Disable (I2C_CON = 0b) to
= 1b) to LNB Output High LNB Output Low
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VVLNB = 13.4 V
VVLNB = 13.4 V
图8-8. No Load, 22-kHz Tone Output
图8-9. 950-mA Load, 22-kHz Tone Output
VVLNB = 18.2 V
VVLNB = 18.2 V
图8-10. No Load, 22-kHz Tone Output
图8-11. 950-mA Load, 22-kHz Tone Output
图8-13. No load, 22-kHz Tone Delay from EXTM 22-
图8-12. No load, 22-kHz Tone Delay from EXTM 22-
kHz Input Turns Low to Output Tone Off
kHz Input Turns High to Output Tone On
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图8-15. No Load, 22-kHz Tone Delay from EXTM
图8-14. No Load, 22-kHz Tone Delay from EXTM
Tone Envelop Input Turns Low to Output Tone Off
Tone Envelop Input Turns High to Output Tone On
图8-16. No Load, 44-kHz Tone Delay from EXTM
图8-17. No Load, 44-kHz Tone Delay from EXTM
22-kHz Input Turns High to Output Tone On
22-kHz Input Turns Low to Output Tone Off
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8.2.2 DiSEqc2.x Support
The TPS65235-1 can support both DiSEqC 1.x application and DiSEqC 2.x application. 图 8-18 shows the
application for supporting DiSEqC 2.x application.
10 kꢀ
10 nF
10 kꢀ
15
14
13
11
12
220 mH
0.1 mF
VOUT
16 VLNB
10
9
VCTRL
100 nF
D2
22 nF
D3
17
VCP
ADDR
10 kꢀ
15 ꢀ
FAULT
8
TPS65235-1
BOOST
18
19
20
2 ×
22mF
EN
7
GDR
D1
ISET
6
PGND
110 kꢀ
1
2
3
4
5
10 mH
VIN
10 mF
1 mF
22 nF
1 mF
图8-18. Application Schematic for DiSEqc2.x Support
8.2.2.1 Design Requirements
Refer to the 节8.2.1 section for design requirements.
8.2.2.2 Detailed Design Procedure
Refer to the 节8.2.1 section for detailed design procedures.
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8.2.2.3 Application Curve
Refer to the 节 8.2.1 section for typical application curves. 图 8-19 is the unique tone-detection curve for the
DiSEqC 2.x application.
图8-19. DOUT Tone Detection Output
8.3 Power Supply Recommendations
The device is designed to operate from an input supply ranging from 4.5 V to 20 V. The input supply must be
well regulated. If the input supply is located more than a few inches from the converter, an additional bulk
capacitance, typically with a value 100 µF, can be required in addition to the ceramic bypass capacitors.
8.4 Layout
8.4.1 Layout Guidelines
The TPS65235-1 is designed to layout in 2‐layer PCB. To ensure reliability of the device, TI recommends
following common printed-circuit board layout guidelines.
• Make sure the ground of input capacitor, output capacitor, and the boost converter are connected at one point
at same layer.
• The PGND and AGND pins are located in different regions. Connect these grounds to the thermal pad. Other
components are connected the AGND pin.
• Put the BOOST capacitors as close as possible.
• The loop from the VIN inductor to the LX pin must be as short as possible.
• The loop from the VIN inductor to D1 Schottky diode to the BOOST must be as short as possible.
• The loop for boost capacitors to the PGND pin must be within the loop from the LX pin to D1 Schottky diode
to the BOOST pin.
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8.4.2 Layout Example
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
15 14 13
11
12
D3
100nF
VOUT
VLNB
16
17
VCTRL
10
9
0.1uF
D2
VCP
ADDR
10k
FAULT
8
7
6
BOOST
18
19
20
EN
GDR
2x22uF
ISET
PGND
110k
D1
1
2
3
4
5
1uF
1uF
VIN
10uH
22nF
10uF
图8-20. Layout
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9 Device and Documentation Support
9.1 Device Support
9.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
9.2 Documentation Support
9.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C Interface for
DiSEqC2.x Application user's guide
• Texas Instruments, Evaluation Module for the TPS65235-1 LNB Voltage Regulator With I2C Interface for
DiSEqC1.x Application user's guide
9.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
9.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
9.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
9.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
9.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65235-1RUKR
TPS65235-1RUKT
ACTIVE
ACTIVE
WQFN
WQFN
RUK
RUK
20
20
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
652351
652351
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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27-Mar-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65235-1RUKR
TPS65235-1RUKT
WQFN
WQFN
RUK
RUK
20
20
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS65235-1RUKR
TPS65235-1RUKT
WQFN
WQFN
RUK
RUK
20
20
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RUK0020B
WQFN - 0.8 mm max height
S
C
A
L
E
4
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
0.5
0.3
PIN 1 INDEX AREA
3.1
2.9
0.25
0.15
DETAIL
OPTIONAL TERMINAL
TYPICAL
DIMENSION A
OPTION 01
OPTION 02
(0.1)
(0.2)
C
0.8 MAX
SEATING PLANE
0.08 C
0.05
0.00
(DIM A) TYP
OPT 02 SHOWN
1.7 0.05
6
10
EXPOSED
THERMAL PAD
16X 0.4
5
11
21
SYMM
4X
1.6
1
15
SEE TERMINAL
DETAIL
0.25
20X
0.15
0.1
C A
B
20
16
PIN 1 ID
SYMM
0.05
(OPTIONAL)
0.5
0.3
20X
4222676/A 02/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RUK0020B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.7)
SYMM
20
16
20X (0.6)
1
15
20X (0.2)
(0.6)
TYP
21
SYMM
(2.8)
16X (0.4)
5
11
(R0.05)
TYP
(
0.2) TYP
VIA
6
10
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222676/A 02/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RUK0020B
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.47) TYP
16
(R0.05) TYP
20
20X (0.6)
1
15
21
20X (0.2)
(0.47)
TYP
SYMM
(2.8)
16X (0.4)
11
5
METAL
TYP
6
10
4X ( 0.75)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 21:
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4222676/A 02/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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相关型号：
TPS65250
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