TPS65280RGET [TI]

DUAL POWER DISTRIBUTION SWITCH AND MONOLITHIC SYNCHRONOUS BUCK REGULATOR WITH 5.5-V TO 18-V INPUT VOLTAGE, FIXED 5-V OUTPUT VOLTAGE AND; 双配电开关和5.5 V至18 V的输入电压，固定5V输出电压，单片式同步降压稳压器和


型号：	TPS65280RGET
厂家：	TEXAS INSTRUMENTS
描述：	DUAL POWER DISTRIBUTION SWITCH AND MONOLITHIC SYNCHRONOUS BUCK REGULATOR WITH 5.5-V TO 18-V INPUT VOLTAGE, FIXED 5-V OUTPUT VOLTAGE AND 双配电开关和5.5 V至18 V的输入电压，固定5V输出电压，单片式同步降压稳压器和稳压器开关输出元件输入元件
文件：	总32页 (文件大小：1732K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65280

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SLVSBE4 –JUNE 2012

DUAL POWER DISTRIBUTION SWITCH AND MONOLITHIC SYNCHRONOUS BUCK

REGULATOR WITH 5.5-V TO 18-V INPUT VOLTAGE, FIXED 5-V OUTPUT VOLTAGE AND

4-A MAXIMUM CURRENT

Check for Samples: TPS65280

FEATURES

•

Over Temperature Protection

INTEGRATED BUCK DC/DC CONVERTER

Wide Input Voltage Range: 5.5 V to 18 V

•

24-Lead QFN (RGE) 4-mm x 4-mm Package

•

xxx

Maximum Continuous 4-A Output Load

Current

INTEGRATED DUAL POWER DISTRIBUTION

SWITCHES

•

Fixed Output Voltage: 5 V ±1%

•

Operating Input Voltage Range: 2.5 V to 6 V

Adjustable 300-kHz to 1.4-MHz Switching

Frequency

Integrated Back-to-Back Power MOSFETs With

80-mΩ On-Resistance

•

External Clock Synchronization

•

Up to 1-A Maximum Load Current

Adjustable Soft Start and Tracking With

Built-In 1-ms Internal Soft-start Time

Current Limiting at Typical 1.2 A (0.8 A,1.6 A or

2 A Available With Manufacture Trim Options)

•

Cycle-by-Cycle Current Limit

Output Over-voltage Protection

•

Latch-off Over Current Protection Versions

Reverse Input-Output Voltage Protection

Built-In Soft-Start

APPLICATIONS

•

USB Ports and Hubs

Digital TV

4-kV HBM and 200-V MM ESD Protection at

Power Switch Output Pins

15-kV ESD Protection per IEC 61000-4-2 With

10-µF External Capacitance

xxx

Set-Top Boxes

VOIP Phones

Tablet PC

DESCRIPTION/ORDERING INFORMATION

The TPS65280 incorporates dual N-channel MOSFET power switches for USB power distribution systems that

require dual power switches in a single package. It also integrates a buck converter which regulates an accurate

5-V output voltage from a 5.5-V to 18-V power bus to supply the power for power switches. The device is

intended to provide a total USB power distribution solution for digital TV, set-top boxes, VOIP phones and tablet

PC applications, where precision current limiting is required or heavy capacitive loads or short circuits are

encountered.

A dual 85-mΩ independent power distribution switch limits the output current to a typical 1.2 A (manufacture trim

0.8 A, 1.6 A, and 2 A available options) when output current load exceeds the current limit threshold. TPS65280

device limits output current to a safe level by using a constant current mode when output load exceeds the

current limit threshold. After delitching time, TPS65280 provides circuit breaker functionality by latching off the

power switch during over-current or reverse-voltage situations. Two back-to-back power MOSFETs prevent the

current injects from output to input in shutdown. An internal reverse-voltage comparator disables the power

switch when the output voltage is driven higher than the input to protect the circuits on the input side of the

switch in normal operation. The nFAULT1/2 output asserts low during over-current and reverse-voltage

conditions.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS65280

SLVSBE4 –JUNE 2012

www.ti.com

The buck DC/DC converter integrates power MOSFETs for optimized power efficiency and reduced external

component count for a fixed 5-V output voltage. A wide 5.5-V to 18-V input supply range to buck encompasses

most intermediate bus voltages operating off a 9-V, 12-V or 15-V power bus. Constant frequency peak current

mode control simplifies the compensation and fast transient response. Equipped with enable and soft-start pins,

the DC/DC can be precisely sequenced and ramp up in order to align with other rails in the system. Cycle-by-

cycle over-current protection and operating in hiccup mode limit MOSFET power dissipation during buck output

short circuit or over loading fault conditions. The switching frequency of the converter can be programmed from

300 kHz to 1.4 MHz with an external resistor at the ROSC pin. With the ROSC pin connecting to the V7V pin,

floating, or grounding, a default fixed switching frequency can be selected to reduce the external component. The

internal oscillator can be synchronized with a free-run external clock in frequency.

When continuous heavy overload or short circuit increases power dissipation in the buck converter or power

switches, the internal thermal protection circuit shuts off both the buck regulator and power switches to prevent

damage. Recovery from a thermal shutdown is automatic once the device has cooled sufficiently.

The TPS65280 is available in a 24-lead thermally enhanced QFN (RGE) 4-mm x 4-mm thin package.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

Reel 3000

Reel 250

TPS65280RGER

–40°C to 85°C

24-Pin QFN (RGE)

TPS65280

TPS65280RGET

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

TYPICAL APPLICATION

47nF

4.7uH

+5V

22uF

100kΩ

USB Data

USB

Port1

PGND

VIN

SW_OUT1

AGND

10uF

VIN

5.5V~18V

TPS65280

USB

Port2

VIN

SW_OUT2

nFALUT1

nFALUT2

USB Data

MODE/SYNC

V7V

1uF

USB1fault signal

USB2fault signal

Enable

USB1control signal

USB2control signal

4.7nF

10kΩ

Analog Ground

Power Ground

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FUNCTION BLOCK DIAGRAM

BUCK

V7V

LDO

VIN

Voltage Reference

Current Bias

Preregulator

HS current sensing

1.25 M

BST

COMP

enable buffer

HS driver

Current Sensing

(0.1V/A)

Buck

Controller

PWM comparator

V7V

12p

420K

80 K

slope

comp

LS driver

0.8V

error amplifer

LS current sensing

1ms Internal

Soft Start

Oscillotor

Mode/Sync

10uA

PGND

ROSC

MODE/SYNC

POWER SWITCH2

enable buffer

10ms Degl .

Time

EN_SW1

1.25M

Current

Limit

Driver

nFAULT 2

SW_OUT2

1.25M

Charge

4ms Degl.

Time

Pump

current sensing

reverse voltage

comparator

SW_IN 14

AGND

UVLO

POR

SW_IN

reverse voltage

comparator

SW_OUT1

current sensing

Charge

Pump

4ms Degl.

Time

1.25M

1.25 M

Current

Limit

Driver

nFAULT 1

10ms Degl .

Time

EN_SW1

enable buffer

POWER SWITCH1

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PIN OUT

RGE PACKAGE

(TOP VIEW)

18 17 16 15 14 13

PGND

SW_OUT1

AGND

VIN

10 NC

Thermal Pad

SW_OUT2

nFAULT1

nFAULT2

MODE/SYNC 23

V7V

There is no electric signal down boned to thermal pad inside IC. Exposed thermal pad must be soldered to PCB for

optimal thermal performance.

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TERMINAL FUNCTIONS

NAME

NO.

DESCRIPTION

Enable for buck converter. Logic high enables buck converter and bias supply to power switches. Forcing

the pin below 0.4 V shuts down the entire device, reducing the quiescent current to approximately 7 µA.

There is a 1.25-MΩ pull-up resistor connecting this pin to internal 5-V power rail. Not recommend floating

this pin. The device can be automatically started up with connecting EN pin to VIN though a 10-kΩ resistor

or connecting a capacitor to program the delay of enabling the device.

COMP

Error amplifier output and Loop compensation pin for buck. Connect a series resistor and capacitor to

compensate the control loop of buck converter with peak current PWM mode.

Soft-start and tracking input for buck converter. An internal 5-µA pull-up current source is connected to this

pin. An external soft-start can be programmed by connecting a capacitor between this pin and ground.

Leave the pin floating to have a default 1 ms of soft-start time. This pin allows the start-up of buck output to

track an external voltage using an external resistor divider at this pin.

ROSC

Oscillator clock frequency control pin. Connect the pin to ground for a fixed 300-kHz switching frequency.

Connect the pin to V7V or float the pin for a fixed 600-kHz switching frequency. Other switch frequency

between 300 kHz to 1.4 MHz can be programmed using a resistor connected from this pin to ground. An

internal 10-µA pull-up current develops a voltage to be used in oscillator. Directly adjusting the ROSC pin

voltage can linearly adjust switching frequency.

EN_SW2

EN_SW1

Enable power switch 2. Logic high turns on power switch. Forcing the pin below 0.4 V shuts down power

switch. Not recommend floating this pin, though there is a 1.25-MΩ pull-up resistor connecting this pin.

Enable power switch 1. Logic high turns on power switch. Forcing the pin below 0.4 V shuts down power

switch. Not recommend floating this pin, though there is a 1.25-MΩ pull-up resistor connecting this pin.

nFAULT2

nFAULT1

SW_OUT2

Active low open drain output, asserted during over-current or reverse-voltage condition of power switch 2.

Active low open drain output, asserted during over-current or reverse-voltage condition of power switch 1.

Power switch 2 output.

No connection. Connection to ANGD recommended.

AGND

10, 11

Analog ground common to buck controller and power switch controller. Pin 10 must be routed separately

from high current power grounds to the (-) terminal of bypass capacitor of internal V7V LDO output.

SW_OUT1

SW_IN

13, 14

Power switch 1 output.

Power switch input voltage. Connect to buck output, or other power supply input.

Kelvin sensing pin for +5-V buck output voltage. Connect this pin to the (+) terminal of buck output capacitor.

The internal feedback resistor divider (420 kΩ/80 kΩ) in buck converter sets a fixed 5-V ±1% output voltage

at room temperature.

16, 17

Switching node connection to the inductor and bootstrap capacitor for buck converter. This pin voltage

swings from a diode voltage below the ground up to V^INvoltage.

BST

Bootstrapped supply to the high side floating gate driver in buck converter. Connect a capacitor (47 nF

recommended) from this pin to LX.

PGND

VIN

19, 20

21, 22

Power ground connection. Connect this pin as close as practical to the (-) terminal of input ceramic

capacitor.

Input power supply for buck. Connect this pin as close as practical to the (+) terminal of an input ceramic

capacitor (10 µF recommended).

MODE/SYNC

External synchronization input to internal clock oscillator in forced continuous mode. When an external clock

is applied to this pin, the internal oscillator will force the rising edge of clock signal to be synchronized with

the rising edge of the external clock. When not synchronizing to an external clock, connecting this pin to

ground forces a continuous current mode (CCM) operation of Buck.

V7V

Internal low-drop linear regulator (LDO) output. The internal driver and control circuits are powered from this

voltage. Decouple this pin to power ground with a minimum 1-µF ceramic capacitor. The output voltage level

of LDO is regulated to typical 6.3 V for optimal conduction on-resistances of internal power MOSFETs. In

PCB design, the power ground and analog ground should have one-point common connection at the (-)

terminal of V7V bypass capacitor.

Thermal PAD

Exposed pad beneath the IC. Connect to the power ground. Always solder thermal pad to the board, and

have as many vias as possible on the PCB to enhance power dissipation. There is no electric signal down

bonded to the thermal pad inside the IC package.

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(1)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VIN, LX

–0.3 to 18

LX (Maximum withstand voltage transient < 20ns)

BST referenced to LX pin

–1.0 to 18

–0.3 to 7

SW_IN, SW_OUT1, SW_OUT2

–0.3 to 7

EN, EN_SW1, EN_SW2, nFAULT1, nFAULT2, V7V, ROSC, MODE/SYNC

SS, COMP

–0.3 to 7

–0.3 to 3.6

–0.3 to 0.3

–40 to 125

–55 to 150

V7, R AGND, PGND

T_J

Operating virtual junction temperature range

Storage temperature range

°C

T_STG

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN

5.5

NOM

MAX

UNIT

VIN

T_A

Input operating voltage

Ambient temperature

–40

°C

ELECTROSTATIC DISCHARGE (ESD) PROTECTION⁽¹⁾

MIN

2000

500

MAX

UNIT

Human body model (HBM)

Charge device model (CDM)

(1) SW_OUT1/2 pins’ human body model (HBM) ESD protection rating 4 kV, and machine model (MM) rating 200V.

THERMAL INFORMATION

TPS65280

THERMAL METRIC⁽¹⁾

RGE

24 PINS

38.1

UNITS

θ_JA

Junction-to-ambient thermal resistance⁽²⁾

Junction-to-case (top) thermal resistance⁽³⁾

Junction-to-board thermal resistance⁽⁴⁾

Junction-to-top characterization parameter⁽⁵⁾

Junction-to-board characterization parameter⁽⁶⁾

Junction-to-case (bottom) thermal resistance⁽⁷⁾

θ_JCtop

θ_JB

45.3

16.9

°C/W

ψ_JT

0.9

ψ_JB

16.9

θ_JCbot

6.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

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ELECTRICAL CHARACTERISTICS

T_J= 25°C, V_IN= 12 V, f_SW= 600 kHz, R_nFAULTx= 100 kΩ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

INPUT SUPPLY

V_IN

Input voltage range

VIN1 and VIN2

5.5

IDD_SDN

Shutdown supply current

EN = EN_SW1 = EN_SW2 = low

µA

Switching quiescent current with no load at

DCDC output

EN = high, EN_SWx = low, FB = 6 V

With Buck not switching

IDD_{Q_NSW}

IDD_{Q_SW}

0.8

Switching quiescent current with no load at

DCDC output, Buck switching

EN = high, EN_SWx = low, FB = 5 V

With Buck switching

Rising V_IN

Falling V_IN

Hysteresis

4.25

4.50

4.25

UVLO

V_7V

V_INunder voltage lockout

Internal biasing supply

3.75

0.25

V_7Vload current = 0 A,

V_IN= 12 V

6.05

300

6.25

6.45

OSCILLATOR

f_{SW_BK}

Switching frequency range

Set by external resistor ROSC

ROSC = 51 kΩ

1400

kHz

500

1400

600

ROSC = 140 kΩ

f_SW

Programmable frequency

kHz

ROSC floating or connected to V7V

ROSC connected to ground

510

255

690

345

300

BUCK CONVERTER

V_IN

Input supply voltage

For a fixed 5-V output

V_COMP= 1.2 V, T_J= 25°C

V_COMP= 1.2 V, T_J= -40°C to 125°C

I_OUT= 2 A

5.5

4.95

4.9

5.05

5.1

V_OUT

Regulated +5-V output voltage

V_LINEREG

V_LOADREG

G_{m_EA}

G_{m_SRC}

V_ENH

Line regulation - DC

0.5

350

%/V

%/A

µs

Load regulation - DC

I_OUT= (10% - 90%) x I_{OUT_max}

-2 µA < I_COMP< 2 µA

I_LX= 0.5 A

Error amplifier trans-conductance⁽¹⁾

COMP voltage to inductor current Gm⁽¹⁾

EN high level input voltage

A/V

V_ENL

EN low level input voltage

0.4

1.5

I_SS

Soft-start charging current

4.5

µA

t_{SS_INT}

I_LIMIT

R_{dson_HS}

R_{dson_LS}

Internal soft-start time

SS pin floats

0.5

Buck peak inductor current limit

On resistance of high side FET in buck

On resistance of low side FET in buck

5.2

V_7V= 6.25 V

V_IN= 12 V

mΩ

POWER DISTRIBUTION SWITCH

V_{SW_IN}

Power switch input voltage range

2.5

2.15

2.05

2.35

2.25

V_{SW_IN}rising

V_{SW_IN}falling

Hysteresis

2.25

2.15

100

V_{UVLO_SW}

Input under-voltage lock out

V_{SW_INx}= 5 V, I_{SW_OUT}= 0.5 A, T_J= 25°C,

including bond wire resistance

100

R_{DSON_SW}

Power switch NDMOS on-resistance

Turn-on delay time

mΩ

V_{SW_Inx}= 2.5 V, I_{SW_OUT}= 0.5 A, T_J= 25°C,

includes bond wire resistance

V_{SW_IN}= 5 V, C_L= 1 µF, R_L= 100 Ω

(see Figure 1)

t_{D_on}

0.66

1.5

t_{D_off}

Turn-off delay time

Output rise time

Output fall time

1.6

1.1

1.2

1.5

t_r

t_f

Current limit threshold (maximum DC current

delivered to load) and short circuit current,

SW_OUTx connect to ground

I_{OCP_SW}

t_IOS

1.05

1.2

1.35

Response time to short circuit

V_{SW_IN}= 5 V

(1) Specified by design.

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ELECTRICAL CHARACTERISTICS (continued)

T_J= 25°C, V_IN= 12 V, f_SW= 600 kHz, R_nFAULTx= 100 kΩ (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Fault assertion or de-assertion due to over-

current condition

t_{DEGLITCH(OCP)}

Switch over current fault deglitch

V_{L_nFAULT}

V_{EN_SWH}

V_{EN_SWL}

R_DIS

nFAULTx pin output low voltage

EN_SWx high level input voltage

Discharge resistance

I_nFAULTx= 1 mA

150

EN_SW1, EN_SW2

0.4

V_{SW_IN}= 5 V, EN_SW1/EN_SW2 = 0 V

100

Ω

THERMAL SHUTDOWN

T_{TRIP_BUCK}Thermal protection trip point

T_{HYST_BUCK}Thermal protection hysteresis

Rising temperature

160

°C

50%

V_{EN_SWx}

t_{D_on}t_r

t_{D_off}t_f

90%

10%

V_{OUT_SWx}

Figure 1. Power Switches Test Circuit and Voltage Waveforms

Figure 2. Response Time to Short Circuit Waveform

Figure 3. Output Voltage vs Current Limit Threshold

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TYPICAL CHARACTERISTICS

T_J= 25°C, V_IN= 12 V, f_SW= 600 kHz, R_nFAULTx= 100 kΩ (unless otherwise noted)

Figure 4. Buck Start Up by EN Pin

With Internal Soft-Start (SS Pin Open)

Figure 5. Buck Start Up by EN Pin

With an External 22-nF SS Capacitor

Figure 6. Ramp V_INto Start Up Buck

With an External 22-nF SS Capacitor

Figure 7. Ramp V_INto Power Down

With an External 22-nF SS Capacitor

Figure 8. Buck Output Voltage Ripple

(Chan3: V_OUT, 10 mV/DIV; Chan4: I_O, 2A/DIV;

Time: 2 µs/DIV)

Figure 9. Buck Output Load Transient

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TYPICAL CHARACTERISTICS (continued)

T_J= 25°C, V_IN= 12 V, f_SW= 600 kHz, R_nFAULTx= 100 kΩ (unless otherwise noted)

Figure 10. Buck Load Regulation

Figure 11. Buck Line Regulation

Figure 12. Oscillator Frequency vs Rosc Voltage

(Note that Select ROSC Resistance = VROSC x 100 kΩ

for Desired Frequency)

Figure 13. Buck Efficiency

Figure 14. Buck Hiccup Response to Hard-Short Circuit

Figure 15. Zoom In Buck Output Hard Short Response

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TYPICAL CHARACTERISTICS (continued)

T_J= 25°C, V_IN= 12 V, f_SW= 600 kHz, R_nFAULTx= 100 kΩ (unless otherwise noted)

Figure 16. Power Switch 1 Turn On Delay and Rise Time

Figure 17. Power Switch 1 Turn Off Delay and Fall Time

R_OUT= 5 Ω, C_OUT= 22 µF

Figure 18. Power Switch 2 Turn On Delay and Rise Time

Figure 19. Power Switch 2 Turn Off Delay and Fall Time

R_OUT= 5 Ω, C_OUT= 22 µF

Figure 20. Power Switch 1 Enable Into Short Circuit

Figure 21. Power Switch 2 Enable Into Short Circuit

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TYPICAL CHARACTERISTICS (continued)

T_J= 25°C, V_IN= 12 V, f_SW= 600 kHz, R_nFAULTx= 100 kΩ (unless otherwise noted)

Figure 22. Power Switch 1 No Load to Short-Circuit

Transient Response

Figure 23. Power Switch 2 No Load to Short-Circuit

Transient Response

Figure 24. . Power Switch Reponses Time (T_IOS

to Output Hard Short

)

Figure 25. Power Switch No Load to 1-Ω

Transient Response

Figure 26. Power Switch Reverse Voltage

Protection Response

Figure 27. Bode Plot

V_IN= 12 V, V_{out_buck}= 5 V/0.5 A, I_sw1= I_sw2= 0.8 A

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TYPICAL CHARACTERISTICS (continued)

T_J= 25°C, V_IN= 12 V, f_SW= 600 kHz, R_nFAULTx= 100 kΩ (unless otherwise noted)

Figure 28. Loop Stability Bode Plot

V_IN= 12 V, Buck Loads 0.5 A,

Power Switch 1 and 2 Have No Load

Figure 29. Loop Stability Bode Plot

V_IN= 12 V, Buck Load 0.5 A,

Power Switch 1 and 2 Load 0.8 A Each

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OVERVIEW

TPS65280 PMIC integrates two independent current-limited, power distribution switches using N-channel

MOSFETs for applications where short circuits or heavy capacitive loads will be encountered and provide up to

1-A of continuous load current. Additional device features include over temperature protection and reverse-

voltage protection. The device incorporates an internal charge pump and gate drive circuitry necessary to drive

the N-channel MOSFET. The charge pump supplies power to the driver circuit and provides the necessary

voltage to pull the gate of the MOSFET above the source. The charge pump operates from the input voltage of

power switches as low as 2.5 V and requires little supply current. The driver controls the gate voltage of the

power switch. The driver incorporates circuitry that controls the rise and fall times of output voltage to limit large

current and voltage surges and provides built-in soft-start functionality. TPS65280 device limits output current to

a safe level when the output load exceeds the current limit threshold. After deglitching time, device latches off

when the load exceeds the current limit threshold. The device asserts the nFAULT1/2 signal during the over

current or reverse voltage faulty condition.

TPS65280 PMIC also integrates a synchronous step-down converter with a fixed 5-V output voltage to provide

the power for power switches in the USB ports. The synchronous buck converter incorporates an 80-mΩ high

side power MOSFET and 50-mΩ low side power MOSFET to achieve high efficiency power conversion. The

converter supports an input voltage range from 5.5 V to 18 V for a fixed 5-V output. The converter operates in

continuous conduction mode with peak current mode control for simplified loop compensation. The switching

clock frequency can be programmed from 300 kHz to 1.4 MHz from the ROSC pin connection. The peak inductor

current limit threshold is internally set at 5 A. The soft-start time can be adjusted with connecting an external

capacitor at the SS pin, or fixed at 1 ms with floating at the SS pin.

POWER SWITCH DETAILED DESCRIPTION

Over Current Condition

The TPS65280 responds to over-current conditions on power switches by limiting the output currents to the

I_{OCP_SW}level, which is fixed internally. The load current is less than the current-limit threshold and the device

does not limit current. During normal operation the N-channel MOSFET is fully enhanced, and V_{SW_OUT}= V_{SW_IN}

- (I_{SW_OUT}x R_{dson_SW}). The voltage drop across the MOSFET is relatively small compared to V_{SW_IN}, and V_{SW_OUT}

≈ V_{SW_IN}. When an over current condition is detected, the device maintains a constant output current and

reduces the output voltage accordingly. During current-limit operation, the N-channel MOSFET is no longer fully

enhanced and the resistance of the device increases. This allows the device to effectively regulate the current to

the current-limit threshold. The effect of increasing the resistance of the MOSFET is that the voltage drop across

the device is no longer negligible (V_{SW_IN}≠ V_{SW_OUT}), and V_{SW_OUT}decreases. The amount that V_{SW_OUT}

decreases is proportional to the magnitude of the overload condition. The expected V_{SW_OUT}can be calculated by

I_{OCP_SW}× R_LOAD, where I_{OCP_SW}is the current-limit threshold and R_LOADis the magnitude of the overload

condition.

The manufacture trim options are available for the current limiting thresholds at 0.8 A, 1.2 A, 1.6 A and 2 A.

Three possible overload conditions can occur as summarized in Table 1.

Table 1. Possible Overload Conditions

CONDITIONS

BEHAVIORS

The output voltage is held near zero potential with respect to ground and the TPS65280 ramps output

current to I_{OCP_SW}. The device limits the current to IOS until the overload condition is removed or the

internal deglitch time (10 ms typical) is reached and the device is turned off. The device will remain off

until power is cycled or the device enable is toggled.

Short circuit or partial short circuit present when

the device is powered up or enabled

The current rises until current limit. Once the threshold has been reached, the device switches into its

current limiting at I_{OCP_SW}. The device limits the current to IOS until the overload condition is removed or

the internal deglitch time (10 ms typical) is reached and the device is turned off. The device will remain off

until power is cycled or the device enable is toggled.

Gradually increasing load (<100 A/s) from normal

operating current to I_{OCP_SW}

The device responds to the over-current condition within time t_IOS(see Figure 3).The current sensing

amplifier is overdriven during this time, and needs time for loop response. Once t_IOShas passed, the

current sensing amplifier recovers and limits the current to I_{OCP_SW}. The device limits the current to IOS

until the overload condition is removed or the internal deglitch time (10 ms typical) is reached and the

device is turned off. The device will remain off until power is cycled or the device enable is toggled.

Short circuit, partial short circuit or fast transient

overload occurs while the device is enabled and

powered on

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Reverse Current and Voltage Protection

A power switch in the TPS65280 incorporates two back-to-back N-channel power MOSFETs as to prevent the

reverse current flowing back the input through body diode of MOSFET when power switches are off.

The reverse-voltage protection feature turns off the N-channel MOSFET whenever the output voltage exceeds

the input voltage by 135 mV (typical) for 4 ms (typical). This prevents damage to devices on the input side of the

TPS65280 by preventing significant current from sinking into the input capacitance of power switch or buck

output capacitance. The TPS65280 device keeps the power switch turned off even if the reverse-voltage

condition is removed and do not allow the N-channel MOSFET to turn on until power is cycled or the device

enable is toggled. The reverse-voltage comparator also asserts the nFAULT1/2 output (active-low) after 4 ms.

nFAULT1/2 Response

The nFAULT1/nFAULT2 open-drain output is asserted (active low) during an over current, over temperature or

reverse-voltage condition. The TPS65280 asserts the nFAULT signal during a fault condition and remains

asserted while the part is latched-off. The nFAULT signal is de-asserted once device power is cycled or the

enable is toggled and the device resumes normal operation. The TPS65280 is designed to eliminate false

nFAULT reporting by using an internal delay deglitch circuit for over current (10 ms typical) and reverse-voltage

(4 ms typical) conditions without the need for external circuitry. This ensures that nFAULT is not accidentally

asserted due to normal operation such as starting into a heavy capacitive load. Deglitching circuitry delays

entering and leaving fault conditions. Over temperature conditions are not deglitched and assert the FAULT

signal immediately.

Under-Voltage Lockup (UVLO)

The under-voltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO

turn-on threshold. Built-in hysteresis prevents unwanted on/off cycling due to input voltage drop from large

current surges.

Enable and Output Discharge

The logic enable EN_SW1/EN_SW2 controls the power switch, bias for the charge pump, driver, and other

circuits. The supply current from power switch driver is reduced to less than 1 µA when a logic low is present on

EN_SW1/2. A logic high input on EN_SW1/EN_SW2 enables the driver, control circuits, and power switch. The

enable input is compatible with both TTL and CMOS logic levels.

When enable is de-asserted, the discharge function is active. The output capacitor of power switch is discharged

through an internal NMOS that has a discharge resistance of 100 Ω. Hence, the output voltage drops down to

zero. The time taken for discharge is dependent on the RC time constant of the resistance and the output

capacitor.

Power Switch Input and Output Capacitance

Input and output capacitance improves the performance of the device. The actual capacitance should be

optimized for the particular application. It is recommended to place the output capacitor in the buck converter

between SW_IN and AGND as close to the device as possible for local noise de-coupling. Additional capacitance

may be needed on the input to reduce voltage overshoot from exceeding the absolute maximum voltage of the

device during heavy transient conditions. This is especially important during bench testing when long, inductive

cables are used to connect the input of power switches in the evaluation board to the bench power-supply.

Placing a high-value electrolytic capacitor on the output pin is recommended when large transient currents are

expected on the output.

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UNIVERSAL SERIAL BUS (USB) POWER-DISTRIBUTION REQUIREMENTS

One application for this device is for current limiting in universal serial bus (USB) applications. The original USB

interface was a 12-Mb/s or 1.5-Mb/s, multiplexed serial bus designed for low-to-medium bandwidth PC

peripherals (e.g., keyboards, printers, scanners, and mice). As the demand for more bandwidth increased, the

USB 2.0 standard was introduced increasing the maximum data rate to 480-Mb/s. The four-wire USB interface is

conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for differential data,

and two lines are provided for 5-V power distribution.

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power

is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V

from the 5-V input or its own internal power supply. The USB specification classifies two different classes of

devices depending on its maximum current draw. A device classified as low-power can draw up to 100 mA as

defined by the standard. A device classified as high-power can draw up to 500 mA. It is important that the

minimum current-limit threshold of the current-limiting power-switch exceed the maximum current-limit draw of

the intended application. The latest USB standard should always be referenced when considering the current-

limit threshold.

The USB specification defines two types of devices as hubs and functions. A USB hub is a device that contains

multiple ports for different USB devices to connect and can be self-powered (SPH) or bus-powered (BPH). A

function is a USB device that is able to transmit or receive data or control information over the bus. A USB

function can be embedded in a USB hub. A USB function can be one of three types included in the list below.

•

Low-power, bus-powered function

High-power, bus-powered function

Self-powered function

SPHs and BPHs distribute data and power to downstream functions. The TPS65280 has higher current capability

than required for a single USB port allowing it to power multiple downstream ports.

Self-Powered and Bus-Powered HUBs

A SPH has a local power supply that powers embedded functions and downstream ports. This power supply

must provide between 4.75 V and 5.25 V to downstream facing devices under full-load and no-load conditions.

SPHs are required to have current-limit protection and must report over-current conditions to the USB controller.

Typical SPHs are desktop PCs, monitors, printers, and stand-alone hubs.

A BPH obtains all power from an upstream port and often contains an embedded function. It must power up with

less than 100 mA. The BPH usually has one embedded function, and power is always available to the controller

of the hub. If the embedded function and hub require more than 100 mA on power up, the power to the

embedded function may need to be kept off until enumeration is completed. This is accomplished by removing

power or by shutting off the clock to the embedded function. Power switching the embedded function is not

necessary if the aggregate power draw for the function and controller is less than 100 mA. The total current

drawn by the bus-powered device is the sum of the current to the controller, the embedded function, and the

downstream ports, and it is limited to 500 mA from an upstream port.

Low-Power Bus-Powered and High-Power Bus-Powered Functions

Both low-power and high-power bus-powered functions obtain all power from upstream ports. Low-power

functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can

draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω

and 10 µF at power up, the device must implement inrush current limiting.

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USB Power Distribution Requirements

USB can be implemented in several ways regardless of the type of USB device being developed. Several power-

distribution features must be implemented.

SPHs must:

•

Current limit downstream ports

Report over-current conditions

BPHs must:

•

Enable/disable power to downstream ports

Power up at < 100 mA

Limit inrush current (< 44 Ω and 10 µF)

Functions must:

•

Limit inrush currents

Power up at < 100 mA

The feature set of the TPS65280 meets each of these requirements. The integrated current limiting and over-

current reporting is required by self-powered hubs. The logic-level enable and controlled rise times meet the

need of both input and output ports on bus-powered hubs and the input ports for bus-powered functions.

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BUCK DC/DC CONVERTER DETAILED DESCRIPTION

Output Voltage

The TPS65280 regulates a fixed +5-V output voltage set by an internal feedback resistor divider as shown in

Figure 30. Pin 15 is a Kelvin sensing feedback of output voltage. This pin should be directly connected to (+)

terminal of output capacitor. Great care should be taken to route the FB line away from noise sources, such as

the inductor or the LX switching node line.

SN1104041

420kΩ

12pF

80kΩ

0.8V

Reference

AGND

COMP

Figure 30. Buck Internal Feedback Resistor Divider

Switching Frequency Selection and Clock Synchronization

The selection of switching frequency is a tradeoff between efficiency and component size. Low frequency

operation increases efficiency by reducing MOSFET switching losses, but requires larger inductance and

capacitance to maintain low output ripple voltage. The switching frequency of the TPS65280 buck controller can

be selected with the connection at ROSC pin. The ROSC pin can be connected to AGND, tied to V7V, open or

programmed through an external resistor. Tying ROSC pin to AGND selects 300 kHz, while tying ROSC ping to

V7V or floating ROSC pin selects 600 kHz. Placing a resistor between ROSC and AGND allows the buck

switching frequency to be programmed between 300 kHz to 1.4 MHz, as shown in Figure 12. The programmed

clock frequency by an external resistor can be calculated with the following equation:

f_SW= 10 x R_OSC

(1)

An external clock source can be connected to the MODE/SYNC pin. The internal oscillator synchronizes the

internal clock and rising edge of the on, high side power MOSFET to the rising edge of the synchronized external

clock signal. When not using clock synchronization, always connect MODE/SYNC pin to ground.

Soft-Start Time

The start-up of buck output is controlled by the voltage on the respective SS pin. When the voltage on the SS pin

is less than the internal 0.8-V reference, the TPS65280 regulates the internal feedback voltage to the voltage on

the SS pin instead of 0.8 V. The SS pin can be used to program an external soft-start function or to allow output

of the buck to track another supply during start-up. The device has an internal pull-up current source of 4.5 µA

that charges an external soft-start capacitor to provide a linear ramping voltage at SS pin. The SN1104041 will

regulate the internal feedback voltage (and hence 5-V output of buck) according to the voltage on the SS pin,

allowing V_OUTto rise smoothly from 0 V to its final regulated 5 V value. The total soft-start time will be

approximately:

0.8 × V

Tss = Css ×

4.5 ×µA

(2)

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Internal V7V Regulator

The TPS65280 features an internal P-channel low dropout linear regulator (LDO) that supplies power at the V7V

pin from the VIN supply. V7V powers the gate drivers and much of the TPS65280’s internal circuitry. The LDO

regulates V7V to 6.3 V of over drive voltage on the power MOSFET for the best efficiency performance. The

LDO can supply a peak current of 50 mA and must be bypassed to ground with a minimum 1-µF ceramic

capacitor. The capacitor placed directly adjacent to the V7V and PGND pins is highly recommended to supply

the high transient currents required by the MOSFET gate drivers.

Short Circuit Protection

During the PWM on-time, the current through the internal high side switching MOSFET is sampled. The sampled

current is compared to a nominal 5-A over-current limit. If the sampled current exceeds the over-current limit

reference level, an internal over-current fault counter is set to 1 and an internal flag is set. Both internal high side

and low side power MOSFETs are immediately turned off and will not be turned on again until the next switching

cycle. If the over-current condition persists for eight sequential clock cycles, the over-current fault counter

overflows indicating an over-current fault condition exists. The buck regulator is shut down and stays turned off

for 10 ms. If the over-current condition clears prior to the counter reaching eight consecutive cycles, the internal

flag and counter are reset. The protection circuitry attempts to recover from the over-current condition after

10-ms power down time. The internal over-current flag and counter are reset. A normal soft-start cycle is

attempted and normal operation continues if the over-current fault condition has cleared. If the over-current fault

counter overflows during soft-start, the converter shuts down and this hiccup mode operation repeats.

Vout

Current limit threshold

I_L

8 clock cycles

V_LX

10ms

Figure 31. DC/DC Over-Current Protection

Inductor Selection

The higher operating frequency allows the use of smaller inductor and capacitor values. A higher frequency

generally results in lower efficiency because of MOSFET gate charge losses. In addition to this basic trade-off,

the effect of the inductor value on ripple current and low current operation must also be considered. The ripple

current depends on the inductor value. The inductor ripple current, i_L, decreases with higher inductance or higher

frequency and increases with higher input voltage, V_IN. Accepting larger values of i_Lallows the use of low

inductances, but results in higher output voltage ripple and greater core losses.

Use Equation 3 to calculate the value of the output inductor. LIR is a coefficient that represents inductor peak-to-

peak ripple to DC load current. It is suggested to use 0.1 ~ 0.3 for most LIR applications.

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Actual core loss of the inductor is independent of core size for a fixed inductor value, but it is dependent on the

inductance value selected. As inductance increases, core losses decrease. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses will increase. Ferrite designs have very low core loss

and are preferred for high switching frequencies, so design goals can concentrate on copper loss and preventing

saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly when the peak

design current is exceeded. It results in an abrupt increase in inductor ripple current and consequent output

voltage ripple. Do not allow the core to saturate. It is important that the RMS current and saturation current

ratings are not exceeding the inductor specification. The RMS and peak inductor current can be calculated from

Equation 5 and Equation 6.

V - V_out

V_out

L =

I_O×LIR V × fsw

(3)

(4)

V - V_out

V_out

Di_L=

I_O

V × fsw

V_out×(V

- V_out)

inmax

(

)

×L × fsw

i_Lrms

I_O²+

inmax

(5)

(6)

Di_L

I_Lpeak= I_O²×

For this design example, use LIR = 0.3, and the inductor is calculated to be 5.40 µH with V_IN= 12 V. Choose a

4.7 µH standard inductor, the peak to peak inductor ripple is about 34% of 3-A DC load current.

Output Capacitor Selection

There are two primary considerations for selecting the value of the output capacitor. The output capacitors are

selected to meet load transient and output ripple’s requirements.

Equation 7 gives the minimum output capacitance to meet the transient specification. For this example,

L_O= 4.7 µH, ΔI_OUT= 3 A – 0.0 A = 3 A and ΔV_OUT= 500 mV (10% of regulated 5 V). Using these numbers gives

a minimum capacitance of 17 µF. A standard 22 µF ceramic capacitor is used in the design.

DI_OUT²×L

Co >

V_out× DV_out

(7)

The selection of C_OUTis driven by the effective series resistance (ESR). Equation 8 calculates the minimum

output capacitance needed to meet the output voltage ripple specification. Where f_SWis the switching frequency,

ΔV_OUTis the maximum allowable output voltage ripple, and Δi_Lis the inductor ripple current. In this case, the

maximum output voltage ripple is 50 mV (1% of regulated 5 V). From Equation 4, the output current ripple is 1 A.

From Equation 8, the minimum output capacitance meeting the output voltage ripple requirement is 4.6 µF with

3-mΩ esr resistance.

Co >

DV_out

8 × fsw

- esr

Di_L

(8)

After considering both requirements, for this example, one 22 µF 6.3 V X7R ceramic capacitor with 3 mΩ of ESR

will be used.

Input Capacitor Selection

A minimum 10 µF X7R/X5R ceramic input capacitor is recommended to be added between VIN and GND. These

capacitors should be connected as close as physically possible to the input pins of the converters, as they

handle the RMS ripple current shown in Equation 9. For this example, I_OUT= 2 A, V_OUT= 5 V, minimum V_{in_min}

9.6 V. Tthe input capacitors must support a ripple current of 1 A RMS.

(

- V_out

)

V_out

inmin

= I_out

inrms

inmin

(9)

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The input capacitance value determines the input ripple voltage of the regulator. The input voltage ripple can be

calculated using Equation 10. Using the design example values, I_{out_max}= 2 A, C_IN= 10 µF, f_SW= 600 kHz, yields

an input voltage ripple of 83 mV.

I_outmax×0.25

DV =

C_in× f_sw

(10)

To prevent large voltage transients, a low ESR capacitor sized for the maximum RMS current must be used.

Output Capacitor Selection

The external bootstrap capacitor connected to the BST pins supply the gate drive voltages for the topside

MOSFETs. The capacitor between BST pin and LX pin is charged through an internal diode from V7V when the

LX pin is low. When high side MOSFETs are to be turned on, the driver places the bootstrap voltage across the

gate-source of the desired MOSFET. This enhances the top MOSFET switch and turns it on. The switch node

voltage, LX, rises to VIN and the BST pin follows. With the internal high side MOSFET on, the bootstrap voltage

is above the input supply: V_BST= V_IN+ V_7V. The selection on bootstrap capacitance is related with internal high

side power MOSFET gate capacitance. A 0.047-μF ceramic capacitor is recommended to be connected between

the BST to LX pin for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade

dielectric. The capacitor should have 10-V or higher voltage rating.

Loop Compensation

The integrated buck DC/DC converter in TPS65280 incorporates a peak current mode. The error amplifier is a

trans-conductance amplifier with a gain of 350 µA/V. A typical type II compensation circuit adequately delivers a

phase margin between 60° and 90°. C_badds a high frequency pole to attenuate high frequency noise when

needed. To calculate the external compensation components, follow these steps:

1. Select switching frequency, f_SW, that is appropriate for application depending on L and C sizes, output ripple

and EMI. Switching frequency between 500 kHz and 1 MHz gives the best trade off between performance

and cost. To optimize efficiency, a lower switching frequency is desired.

2. Set up cross over frequency, fc, which is typically between 1/5 and 1/20 of f_SW

3. RC can be determined by:

2p × fc × Vo ×Co

R_C

g_M× Vref × gm_ps

(11)

where gm is the error amplifier gain (350 µA/V) and gm_psis the power stage voltage to current conversion

gain (10 A/V).

fp =

C_O×R_L× 2p

4. Calculate C_Cby placing a compensation zero at or before the dominant pole,

R_L×Co

C_C

R_C

(12)

(13)

5. Optional C_bcan be used to cancel the zero from the ESR associated with C_O.

Resr ×Co

C_b=

R_C

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SW _IN

Buck Output : +5V

i_L

R_ESR

R_L

Current Sense

I/V Converter

g _mps= 10 A/V

C_o

R₁

C₁

420 K

12 pF

Vfb

COMP

V_ref= 0.8V

g _M= 350uS

R₂

80 K

R_c

C_b

C_c

Figure 32. DC/DC Loop Compensation

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APPLICATION INORMATION

Thermal Shutdown

The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.

The thermal shutdown forces the buck converter to stop switching when the junction temperature exceeds

thermal trip threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up

sequence. The thermal shutdown hysteresis is 20°C.

Power Dissipation and Junction Temperature

The total power dissipation inside TPS65280 should not exceed the maximum allowable junction temperature of

125°C. The maximum allowable power dissipation is a function of the thermal resistance of the package, θ_JA, and

ambient temperature. The analysis below gives an approximation in calculating junction temperature based on

the power dissipation in the package. However, it is important to note that thermal analysis is strongly dependent

on additional system level factors. Such factors include air flow, board layout, copper thickness and surface area,

and proximity to other devices dissipating power. Good thermal design practice must include all system level

factors in addition to individual component analysis.

To calculate the temperature inside the device under continuous load, use the following procedure.

1. Define the total continuous current through the buck converter (including the load current through power

switches). Make sure the continuous current does not exceed the maximum load current requirement.

2. From the graphs below, determine the expected losses (Y axis) in Watts for the buck converter inside the

device. The loss P_{D_BUCK}depends on the input supply and the selected switching frequency. Please note,

the data is measured in the provided evaluation board (EVM).

3. Determine the load current I_OUT1and I_OUT2through the power switches. Read R_DS(on)1/2of the power switch

from the typical characteristics graph.

4. The power loss through power switches can be calculated by:

P_{D_PW}= R_DS1(on)× I_OUT1+ R_DS2(on)× I_OUT2

(14)

5. The Dissipating Rating Table provides the thermal resistance, θ_JA, for specific packages and board layouts.

6. The maximum temperature inside the IC can be calculated by:

T_J= P_{D_BUCK}+ P_{D_PW}× θ_JA+ T_A

(15)

Where:

T_A= Ambient temperature (°C)

θ_JA= Thermal resistance (°C/W)

P_{D_BUCK}= Total power dissipation in buck converter (W)

P_{D_PW}= Total power dissipation in power switches (W)

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Figure 33. Buck Loss vs Output Current

Figure 34. Buck Loss vs Output Current

(V_IN= 9 V, 12 V and 15 V, f_SW= 300 kHz)

(V_IN= 9 V, 12 V and 15 V, f_SW= 600 kHz)

Figure 35. Buck Loss vs Output Current

(V_IN= 9 V, 12 V and 15 V, f_SW= 1 MHz)

Figure 36. Buck Loss vs Output Current

(V_IN= 9 V, 12 V and 15 V, f_SW= 1.4 MHz)

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Auto-Retry Functionality

Some applications require that an over-current condition disables the part momentarily during a fault condition

and re-enables after a pre-set time. This auto-retry functionality can be implemented with an external resistor and

capacitor shown in Figure 37. During a fault condition, nFAULT pulls low disabling the part. The part is disabled

when EN is pulled low, and nFAULT goes high impedance allowing CRETRY to begin charging. The part re-

enables when the voltage on EN_SW reaches the turn-on threshold, and the auto-retry time is determined by the

resistor/capacitor time constant. The part will continue to cycle in this manner until the fault condition is removed.

47nF

4.7uH

+5V

22uF

R_FAULT

100kΩ

R_FAULT

100kΩ

USB Data

USB

Port1

PGND

VIN

SW_OUT1

AGND

10uF

VIN

4.5V~18V

TPS65280

USB

Port2

VIN

SW_OUT2

nFALUT1

nFALUT2

USB Data

MODE/SYNC

V7V

1uF

Enable

4.7nF

Analog Ground

Power Ground

10kΩ

C_RETRY

0.1u

C_RETRY

0.1u

Figure 37. Auto Retry Functionality

Some applications require auto-retry functionality and the ability to enable/disable with an external logic signal.

Figure 38 shows how an external logic signal can drive EN_SW through RFAULT and maintain auto-retry

functionality. The resistor/capacitor time constant determines the auto-retry time-out period.

47nF

4.7uH

+5V

22uF

USB Data

USB

Port1

PGND

VIN

SW_OUT1

AGND

10uF

VIN

4.5V~18V

TPS65280

USB

Port2

VIN

SW_OUT2

nFALUT1

nFALUT2

C_RETRY

0.1u

USB Data

MODE/SYNC

V7V

C_RETRY

0.1u

1uF

R_{FAULT 1}

100kΩ

Enable

external logic

signal & driver

4.7nF

Analog Ground

Power Ground

10kΩ

R_FAULT

100kΩ

Figure 38. Auto Retry Functionality With External Enable Signal

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PCB Layout Recommendation

When laying out the printed circuit board, the following guidelines should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the layout diagram of Figure 39.

•

There are several signal paths that conduct fast changing currents or voltages that can interact with stray

inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help

eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass

capacitor with X5R or X7R dielectric. This capacitor provides the AC current into the internal power

MOSFETs. Connect the (+) terminal of the input capacitor as close as possible to the VIN pin, and connect

the (-) terminal of the input capacitor as close as possible to the PGND pin. Care should be taken to minimize

the loop area formed by the bypass capacitor connections, the VIN pins, and the power ground PGND

connections.

•

Since the LX connection is the switching node, the output inductor should be located close to the LX pin, and

the area of the PCB conductor minimized to prevent excessive capacitive coupling. Keep the switching node,

LX, away from all sensitive small-signal nodes.

•

Connect V7V decoupling capacitor (connected close to the IC), between the V7V and the power ground

PGND pin. This capacitor carries the MOSFET drivers’ current peaks.

Place the output filter capacitor of the buck converter close to SW_IN pins and AGND pin. Try to minimize the

ground conductor length while maintaining adequate width.

The AGND pin should be separately routed to the (-) terminal of V7V bypass capacitor to avoid switching

grounding path. A ground plane is recommended connecting to this ground path.

The compensation should be as close as possible to the COMP pins. The COMP and ROSC pins are

sensitive to noise so the components associated to these pins should be located as close as possible to the

IC and routed with minimal lengths of trace. Flood all unused areas on all layers with copper. Flooding with

copper will reduce the temperature rise of the power components. You can connect the copper areas to

PGND, AGND, VIN or any other DC rail in your system.

•

There is no electric signal internal connected to thermal pad in the device. Nevertheless connect the exposed

pad beneath the IC to ground. Always solder the thermal pad to the board, and have as many vias as

possible on the PCB to enhance power dissipation.

Figure 39. 2-Layers PCB Layout Recommendation Diagram

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Product Folder Link(s): TPS65280

PACKAGE OPTION ADDENDUM

www.ti.com

2-Jul-2012

PACKAGING INFORMATION

Status ⁽¹⁾

Eco Plan ⁽²⁾

MSL Peak Temp ⁽³⁾

Samples

Orderable Device

Package Type Package

Drawing

Pins

Package Qty

Lead/

Ball Finish

(Requires Login)

TPS65280RGER

ACTIVE

VQFN

RGE

3000

Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent

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TPS65280RGET [TI]

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