TPS65310AQRVJRQ1 [TI]
适用于汽车安全应用的汽车类 4V 至 40V、5 稳压输出电源管理 IC | RVJ | 56 | -40 to 125;
| 型号： | TPS65310AQRVJRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于汽车安全应用的汽车类 4V 至 40V、5 稳压输出电源管理 IC | RVJ | 56 | -40 to 125 |
| 文件： | 总69页 (文件大小：2896K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS65310A-Q1
ZHCSB89H –MAY 2013 –REVISED DECEMBER 2021
TPS65310A-Q1 适用于汽车类安全应用的高电压电源管理IC
• 用于控制和诊断的串行外设接口(SPI)
• 集成窗口安全装置(WD)
• 基准电压输出
• 高侧(HS) 驱动器，用于外部场效应晶体管(FET)
和发光二极管(LED) 驱动器
• 外部温度传感器输入，集成电路(IC) 在TA < -40°C
时关断
1 特性
• 符合汽车应用要求
• AEC-Q100 测试指导结果如下：
– 器件温度等级1：–40°C 至125°C 的工作环境
温度范围
– 器件HBM ESD 分类等级H1B
– 器件CDM ESD 分类等级C3B
• 输入电压范围：4V 至40V，瞬态高达60V；当使
用外部P 通道金属氧化物半导体(PMOS) 时达到
80V
• 热增强型封装
– 56 引脚QFN (RVJ)
2 应用
• 单输出同步降压控制器
• 多轨直流配电系统
• 安全关键型汽车应用
– 高级驾驶辅助系统
– 峰值栅极驱动电流0.6A
– 490kHz 固定开关频率
– 假随机跳频展频或三角模式
• 双路同步降压转换器
3 说明
TPS65310A-Q1™ 器件是一款电源管理单元，满足由
数字信号处理器(DSP) 控制的汽车系统（例如，高级
驾驶辅助系统）的要求。通过集成常用功能，
TPS65310A-Q1 器件显著降低了布板空间和系统成
本。
– 设计用于高达2A 的输出电流
– 异相开关
– 开关频率：0.98 MHz
• 可调350mA 线性稳压器
• 可调异步升压转换器
封装尺寸（标称值）
器件型号
封装
– 1A 集成开关
TPS65310A-Q1
VQFNP (56)(1)
8.00mm x 8.00mm
– 开关频率：0.98 MHz
• 所有稳压器输出的软启动功能
• 独立电压监控
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 欠压(UV) 检测和过压(OV) 保护
• 可为降压控制器、栅极驱动器、降压转换器、升压
转换器和线性稳压器输出提供短路、过流和热保护
VBAT
Protection FET
VIN
Battery
Sense
IRQ
Buck
Controller
I/O supply
VBuck1
VIO
RESN
RESET
PRESN
VBuck1
WD Trigger
Watchdog
Wake
Wake Up Input
SPI Interface
Buck
Converter
VBuck2
SPI
Reference Voltage
Buck
Converter
Reference
voltage
+
VBuck3
Comparator
VBuck1
Boost
Converter
VBooster
HS PWM Input
VINPROT
High Side
LED Driver
Linear
Regulator
VLDO
图3-1. 简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSC15
TPS65310A-Q1
ZHCSB89H –MAY 2013 –REVISED DECEMBER 2021
www.ti.com.cn
Table of Contents
8.5 Programming ........................................................... 35
8.6 Register Maps...........................................................36
9 Application and Implementation..................................44
9.1 Application Information............................................. 44
9.2 Typical Applications ................................................. 44
10 Power Supply Recommendations..............................55
11 Layout...........................................................................57
11.1 Layout Guidelines................................................... 57
11.2 Layout Example...................................................... 58
12 Device and Documentation Support..........................61
12.1 Documentation Support ......................................... 61
12.2 接收文档更新通知................................................... 61
12.3 支持资源..................................................................61
12.4 Trademarks.............................................................61
12.5 Electrostatic Discharge Caution..............................61
12.6 术语表..................................................................... 61
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 说明（续）.........................................................................4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 7
7.1 Absolute Maximum Ratings........................................ 7
7.2 ESD Ratings .............................................................. 8
7.3 Recommended Operating Conditions.........................8
7.4 Thermal Information....................................................8
7.5 Electrical Characteristics.............................................9
7.6 SPI Timing Requirements ........................................ 15
7.7 Typical Characteristics..............................................16
8 Detailed Description......................................................20
8.1 Overview...................................................................20
8.2 Functional Block Diagram.........................................21
8.3 Feature Description...................................................22
8.4 Device Functional Modes..........................................24
Information.................................................................... 62
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision G (May 2019) to Revision H (December 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 将提到SPI 的旧术语实例全局更改为控制器和外设............................................................................................1
• Shutdown comparator Reference voltage Min specification changed to 1mV from 10mV.................................9
• High-side switch current limit specification for for BUCK2/3 changed: Min spec changed to 2.4A from 2.5A
and max spec changed to 3.5A from 3.3A..........................................................................................................9
Changes from Revision F (December 2018) to Revision G (May 2019)
Page
• Changed part number to "TPS65310ASQRWERQ1" ......................................................................................62
Changes from Revision E (October 2014) to Revision F (December 2018)
Page
• Deleted lead temperature from Absolute Maximum Ratings table .................................................................... 7
• Changed the Handling Ratings table to ESD Ratings and moved the storage temperature parameter to the
Absolute Maximum Ratings table ...................................................................................................................... 8
Changes from Revision D (July 2014) to Revision E (October 2014)
Page
• 添加了RWE 封装选项........................................................................................................................................ 1
• Added the following text to the paragraph after the Compensation Settings table in the Compensation of the
BUCK2 and BUCK3 Converters section: upper resistance and effective VBUCK2/3 at higher frequencies to
the ....................................................................................................................................................................48
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Changes from Revision C (January 2014) to Revision D (July 2014)
Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 5
Changes from Revision B (December 2013) to Revision C (January 2014)
Page
• Added new IOUT = 350 mA, TJ = 150°C test condition with higher typ and max values to the VDropout
parameter and changed test condition for lower typ and max values from TJ = 150°C to TJ = 125°C ............. 9
• Changed the min value for the VHSSC_HY parameter from 1.5 to 1 and deleted the typ (2.5) and max (3.5)
values................................................................................................................................................................. 9
• Changed the max value for the tVSSENSE_BLK parameter from 20 to 35....................................................... 9
Changes from Revision A (June 2013) to Revision B (November 2013)
Page
• Added reference to the TPS65310A-Q1 Efficiency Application Report to the TYPICAL CHARACTERISTICS
condition statement...........................................................................................................................................16
• Moved the component selection portion of the Buck Controller (BUCK1) section into the Typical Applications
section ............................................................................................................................................................. 45
• Changed R1 to R3 in the Compensation of the Buck Controller section..........................................................46
• Added the Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter to the Detailed Design
Procedure in the Synchronous Buck Converters BUCK2 and BUCK3 section................................................ 48
• Changed the inductance, capacitance and FLC values from 3.3 µH, 20 µF, and 12.9 kHz to 1.5 µH, 39 µF,
and 13.7 kHz (respectively) in the For example: section of the Compensation of the BOOST Converter
section.............................................................................................................................................................. 52
• Added the Linear Regulator application section .............................................................................................. 53
Changes from Revision * (May 2013) to Revision A (June 2013)
Page
• Changed VPOR rising VIN typ value from 4.1 to 4.2............................................................................................9
• Changed VPOR_hyst values from 0.37 min, 0.5 typ, 0.63 max to 0.47 min, 0.6 typ, and 0.73 max, respectively....
9
• Changed VDropout max value from 140 to 143.....................................................................................................9
• Changed VREF_OK threshold typ and max values from 3 to 3.07 and 3.09 to 3.12, respectively. ...................... 9
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5 说明（续）
此器件采用一个高压降压控制器进行预稳压，并结合使用两个降压转换器和一个升压转换器进行后稳压。进一步
集成的低压降稳压器 (LDO) 整合了电源的概念，提供了一套带有五个独立电压轨的灵活系统设计。此器件提供一
个低功率状态（所有电源轨关闭时的 LPM0）来在系统一直连接至电池线路时减少流耗。所有输出受过载和过热
保护。
外部 PMOS 保护功能使器件能够承受高达 80V 的瞬态电压。该外部 PMOS 还可用于安全关键型应用，以在其中
一个电源轨出现故障（欠压、过压或过流）时保护系统。
内部软启动可确保所有电源的启动都能够得到控制。每个电源的输出电压均可通过外部电阻网络设置进行调节。
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6 Pin Configuration and Functions
1
42
VSSENSE
BOOT3
VIN
GPFET
VINPROT
HSCTRL
HSSENSE
WAKE
VSUP3
PH3
PGND3
VMON3
COMP3
VSENSE3
VSENSE2
COMP2
VMON2
PGND2
PH2
TOP VIEW
EXTSUP
VREG
BOOT1
GU
PH1
GL
VSUP2
14
29
PGND1
BOOT2
图6-1. RVJ Package. 56-Pin VQFN With Exposed Thermal Pad. Top View.
表6-1. Pin Functions
PIN
PULLUP
PULLDOWN
TYPE(1)
DESCRIPTION
NAME
NO.
10
BOOT1
BOOT2
I
I
The capacitor on these pins acts as the voltage supply for the high-side MOSFET gate-drive circuitry.
The capacitor on these pins act as the voltage supply for the high-side MOSFET gate drive circuitry.
—
—
29
The capacitor on these pins act as the voltage supply for the BUCK3 high-side MOSFET gate drive
circuitry.
BOOT3
42
I
—
COMP1
COMP2
COMP3
18
34
37
O
I
Error amplifier output for the switching controller. External compensation network is connected to this node.
Compensation selection for the BUCK2 switching converter
—
—
—
I
Compensation selection for the BUCK3 switching converter.
Error amplifier output for the boost switching controller. External compensation network is connected to this
node.
COMP5
20
O
—
CSN
44
55
8
I
O
I
Pullup
SPI –Chip select
DVDD
EXTSUP
GL
Internal DVDD output for decoupling
Optional LV input for gate driver supply
Gate driver –low-side FET
—
—
—
—
—
—
13
56
3
O
O
O
O
O
I
GND
Analog GND, digital GND and substrate connection
Gate driver external protection PMOS FET.
Gate driver –high-side FET
GPFET
GU
11
5
HSCTRL
HSPWM
High-side gate driver output
—
49
6
Pulldown
High side and LED PWM input
HSSENSE
IRQ
I
Sense input high side and LED
—
—
—
28
51
OD
O
Low battery interrupt output in operating mode
Linear regulated output (connect a low ESR ceramic output capacitor to this terminal)
LDO
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表6-1. Pin Functions (continued)
PIN
PULLUP
PULLDOWN
TYPE(1)
DESCRIPTION
NAME
PGND1
PGND2
PGND3
PGND5
PH1
NO.
14
32
39
22
12
31
40
23
26
27
15
16
46
45
47
24
O
O
O
O
O
O
O
O
OD
OD
I
Ground for low-side FET driver
Power ground of synchronous converter BUCK2
Power ground of synchronous converter BUCK3
Power ground boost converter
Switching node - BUCK1 (floating ground for high-side FET driver)
Switching node BUCK2
—
—
—
—
—
PH2
—
PH3
Switching node BUCK3
—
PH5
Switching node boost
—
—
PRESN
RESN
S1
Peripherals reset
System reset
—
Differential current sense inputs for BUCK1, S2 pull-down only active in RAMP and ACTIVE state
—
S2
I
Pulldown
SCK
I
Pulldown
Pulldown
SPI –Clock
SDI
I
SPI –controller out, peripheral in
SPI –controller in, peripheral out - push-pull output supplied by VIO
Booster output voltage
SDO
O
I
—
—
VBOOST
Unprotected supply input for the base functionality and band gap 1. Supplied blocks are: RESET, WD,
wake, SPI, temp sensing, voltage monitoring and the logic block.
VIN
2
4
I
I
I
—
—
—
VINPROT
VIO
Main input supply pin (gate drivers and bandgap2)
Supply input for the digital interface to the MCU. Voltage on this input is monitored. If VIO falls below UV
threshold a reset is generated and the part enters error mode.
48
VMON1
VMON2
VMON3
VREF
17
33
38
53
9
I
I
Input pin for the independent voltage monitor at BUCK1
—
—
—
—
—
Input pin for the independent voltage monitor at BUCK2
I
Input pin for the independent voltage monitor at BUCK3
O
O
Accurate reference voltage output for peripherals on the system (for example, ADC)
Internal regulator for gate driver supply (decoupling) and VREF
VREG
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground.
VSENSE1
VSENSE2
VSENSE3
VSENSE4
VSENSE5
19
35
36
52
21
I
I
I
I
I
—
—
—
—
—
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground
Input for externally sensed voltage of the output using a resistor divider network from their respective
output line to ground.
Input for externally sensed voltage of the boost output using a resistor divider network from their respective
output line to ground.
VSSENSE
VSUP2
1
I
I
I
I
Input to monitor the battery line for undervoltage conditions. UV is indicated by the IRQ pin.
Input voltage supply for switch mode regulator BUCK2
—
—
—
—
30
41
50
VSUP3
Input voltage supply for switch mode regulator BUCK3
VSUP4
Input voltage supply for linear regulator LDO
Input pin for the comparator with shutdown functionality. This input can be used to sense an external NTC
resistor to shutdown the IC in case the ambient temperature is too high or too low. Tie to GND if not in use.
VT
54
25
I
—
—
Shutdown comparator reference output. Internally connected to DVDD, current-limited. When not in use
can be connected to DVDD or left open.
VT_REF
O
WAKE
WD
7
I
I
Pulldown
Pulldown
Wake up input
43
Watchdog input pin. WD is the trigger input coming from the MCU.
(1) Description of pin type: I = Input; O = Output; OD = Open-drain output
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
80
UNIT
VIN
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
VINPROT
60
VSUP2, 3 (BUCK2 and 3)
20
Supply inputs
VSUP4 (Linear Regulator)
20
V
VBOOST
EXTSUP
VIO
20
13
5.5
60
–1
PH1
–2 for 100 ns
VSENSE1
20
20
8
–0.3
–0.3
–0.3
–0.3
–2
COMP1
GU-PH1, GL-PGND1, BOOT1-PH1
Buck controller
V
S1, S2
20
2
S1-S2
BOOT1
68
20
20
20(4)
–0.3
–0.3
–1
VMON1
BOOT2, BOOT3
–1(4)
–2 for 10 ns
PH2, PH3
VSENSE2, VSENSE3
COMP2, COMP3
VMON2, VMON3
BOOTx –PHx
LDO
20
20
20
8
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–1 (3)
–0.3
–0.3
–1 (3)
Buck controller
V
8
Linear regulator
Boost converter
V
V
VSENSE4
20
20
20
20
5.5
20
60
80
20
VSENSE5
PH5
COMP5
CSN, SCK, SDO, SDI, WD, HSPWM
RESN, PRESN, IRQ
WAKE
Digital interface
Wake input
V
V
V
GPFET
Protection FET
VIN –GPFET
60
Battery-sense input
VSSENSE
V
Transients up to 80 V(2)
VT
5.5
20
5.5
60
60
20
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
Temperature sense
Reference voltage
V
V
VT_REF
VREF
HSSENSE
High-side and LED
driver
HSCTRL
V
VINPROT-HSSENSE, VINPROT-HSCTRL
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7.1 Absolute Maximum Ratings (continued)
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–55
–55
–55
MAX
8
UNIT
V
Driver-supply decoupling VREG
Supply decoupling
DVDD
3.6
150
125
165
V
Junction temperature, TJ
Operating temperature, TA
Storage temperature, Tstg
Temperature ratings
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Internally clamped to 60-V, 20-kΩexternal resistor required, current into pin limited to 1 mA.
(3) Imax = 100 mA
(4) Maximum 3.5 A
7.2 ESD Ratings
VALUE
±1000
±150
UNIT
Human-body model (HBM), per AEC Q100-002(1)
VT pin
Electrostatic
discharge
V(ESD)
V
Charged-device model (CDM), per
AEC Q100-011
All pins except VT
±500
Corner pins (BOOT2, IRQ, S1, PGND1,
VSSENSE, GND, WD, and BOOT3)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage at VIN, VINPROT, VSSENSE
4.8
–40
–55
–40
–55
40
125
125
150
150
V
All electrical characteristics in this specification
Operating free air
temperature
TA
TJ
°C
Shutdown comparator and internal voltage regulators in this specification
All electrical characteristics in this specification
Operating virtual junction
temperature
°C
Shutdown comparator and internal voltage regulators in this specification
7.4 Thermal Information
TPS65310A-Q1
THERMAL METRIC(1)
(RVJ) (VQFN)
UNIT
56 PINS
27
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
11.2
8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ψJT
4.9
ψJB
RθJC(bot)
0.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report, SPRA953.
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7.5 Electrical Characteristics
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE-CURRENT CONSUMPTION
VIN
Device operating range
Buck regulator operating range, Voltage on VIN and VINPROT pins
4
3.5
50
3.8
V
V
Falling VIN
Rising VIN
3.6
4.2
0.6
VPOR
Power-on reset threshold
3.9
4.3
VPOR_hyst
ILPM0
Power-on reset hysteresis on VIN
LPM0 current consumption(1)
0.47
0.73
V
TA = 25°C, All off, wake active, VIN = 13 V, Total current into
VSSENSE, VIN and VINPROT
44
60
μA
LPM0 current (commercial vehicle
application) consumption(1)
TA = 130°C, All off, wake active, VIN = 24.5 V, Total current into
VSSENSE, VIN and VINPROT
ILPM0
μA
BUCK1 = on, VIN = 13 V, EXTSUP = 0 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, Total current into
VSSENSE, VIN and VINPROT
IACTIVE1
32
40
31
53
mA
BUCK1/2/3 = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, Total current into
VSSENSE, VIN and VINPROT
IACTIVE123
mA
mA
mA
ACTIVE total current consumption(2)
BUCK1/2/3, LDO, BOOST, high-side switch = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, EXTSUP = 5 V from
BOOST, Total current into VSSENSE, VIN and VINPROT
IACTIVE1235
BUCK1/2/3, LDO, BOOST, high-side switch = on, VIN = 13 V,
Qg of BUCK1 FETs = 15 nC, TA = 25°C, EXTSUP = open, Total
current into VSENSE, VIN and VINPROT
IACTIVE1235_noEXT
BUCK CONTROLLER (BUCK1)
VBUCK1
Adjustable output voltage range
3
11
V
Internal reference voltage in operating
mode
VSense1_NRM
VSENSE1 pin, load = 0 mA, Internal REF = 0.8 V
1%
–1%
Maximum sense voltage VSENSE1 = 0.75 V (low duty cycle)
Minimum sense voltage VSENSE 1 = 1 V (negative current limit)
∆VCOMP1 / ∆ (VS1 - VS2)
60
–65
4
75
–37.5
8
90
–23
12
VS1-2
ACS
VS1-2 for forward OC in CCM
mV
Current-sense voltage gain
RSTN and ERROR mode transition,
when overcurrent is detected for >
tOCBUCK1_BLK
tOCBUCK1_BLK
1
ms
tDEAD_BUCK1
Shoot-through delay, blanking time
Switching frequency
25
fOSC / 10
100
ns
MHz
ns
ƒSWBUCK1
High-side minimum on time
Maximum duty cycle
DC
Duty cycle
98.75%
EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLER
IGpeak
Gate driver peak current
Source and sink driver
VREG = 5.8 V
0.6
5
A
IG current for external MOSFET = 200 mA, VREG = 5.8 V,
VBOOT1-PH1 = 5.8 V
RDSON_DRIVER
VDIO1
10
Ω
Bootstrap diode forward voltage
0.8
60
1.1
V
IBOOT1 = –200 mA, VREG-BOOT1
ERROR AMPLIFIER (OTA) FOR BUCK CONTROLLERS AND BOOST CONVERTER
COMP1/2/3/5 = 0.8 V; source and sink = 5 µA, test in feedback
loop
gmEA
AEA
Forward transconductance
Error amplifier DC gain
0.9
m℧
dB
SYNCHRONOUS BUCK CONVERTER BUCK2/3
VSUP2/3
VBUCK2/3
RDSON-HS
RDSON-LS
Supply voltage
3
11
5.5
V
V
Regulated output voltage range
RDSON high-side switch
RDSON low-side switch
0.8
Iload = 0 to 2 A, VSUPx = VBUCK2/3 + Iload × 0.2 Ω
VBOOTx –PHx = 5.8 V
0.20
0.20
Ω
Ω
VREG = 5.8 V
Static current limit test. In application L > 1 µH at IHS-Limit and ILS-
Limit to limit dI / dt
IHS-Limit
High-side switch current limit
Low-side switch current limit
2.4
2
2.9
2.5
3.5
A
Static current limit test. In application L > 1 µH at IHS-Limit and ILS-
Limit to limit dI / dt
ILS-Limit
3
2
VSUPLkg
ƒSWLBuck2/3
VSense2/3
VSUP leakage current
Buck switching frequency
Feedback voltage
VSUP = 10 V for high side, controller disabled, TJ = 100°C
1
µA
fOSC/5
With respect to 800-mV internal reference
High-side minimum on time
Maximum duty cycle
1%
–1%
50
99.8%
20
ns
ns
DCBUCK2/3
Duty cycle
tDEAD_BUCK2/3
Shoot-through delay
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
COMP2/3HTH
COMP2/3LTH
COMP2/3 input threshold low
0.9
1.5
V
VREG –
COMP2/3 input threshold high
V
VREG –0.3
1.2
RTIEOFF COMP23
VDIO2 3
BOOST CONVERTER
COMP2/3 internal tie-off
BUCK2/3 enabled. Resistor to VREG and GND, each
70
100
1.1
130
1.2
kΩ
Bootstrap-diode forward voltage
V
IBOOT1 = –200 mA, VREG-BOOT2, VREG-BOOT3
VBoost
Boost adjustable-output voltage range
4.5
15
15
18.5
0.5
V
V
Using 3.3-V input voltage, Ieak_switch ≤1 A
VBoost
Boost adjustable-output voltage range Using 3.3-V input voltage Iloadmax = 20 mA, Ipeak_switch = 0.3 A
RDS-ON_BOOST
VSense5
Internal switch on-resistance
Feedback voltage
VREG = 5.8 V
0.3
Ω
With respect to 800-mV internal reference
1%
–1%
fSWLBOOST
Boost switching frequency
fOSC / 5
90%
MHz
A
Maximum internal-MOSFET duty cycle
at fSWLBOOST
DCBOOST
ICLBOOST
Internal switch current limit
1
1.5
LINEAR REGULATOR LDO
VSUP4
VLDO
Device operating range for LDO
Recommended operating range
IOUT = 1 mA to 350 mA
3
7
V
V
Regulated output range
0.8
5.25
DC output voltage tolerance at
VSENSE4
VSENSE4 = 0.8 V (regulated at internal reference),
VSUP4 = 3 V to 7 V, IOUT = 1 mA to 350 mA
VRefLDO
2%
2%
–2%
VSENSE4 = 0.8 V (regulated at internal reference),
IOUT = 1 mA to 101 mA, CLDO = 6 to 50 µF, trise = 1 µs
Vstep1
Load step 1
–2%
–1%
VSense4
Feedback voltage
With respect to 800-mV internal reference
IOUT = 350 mA, TJ = 25°C
1%
143
127
156
275
VDropout
Dropout voltage
IOUT = 350 mA, TJ = 125°C
IOUT = 350 mA, TJ = 150°C
VOUT in regulation
180
mV
335
IOUT
Output current
mA
mA
–350
–1
ILDO-CL
Output current limit
VOUT = 0 V, VSUP4 = 3 V to 7 V
–1000
–400
Frequency = 100 Hz
60
50
25
Vripple = 0.5 VPP, IOUT = 300 mA,
CLDO = 10 µF
PSRRLDO
Power-supply ripple rejection
Frequency = 4 kHz
dB
Frequency = 150 kHz
LDOns10-100
LDOns100-1k
CLDO
10-µF output capacitance, VLDO = 2.5 V
10-µF output capacitance, VLDO = 2.5 V
20
6
Output noise 10 Hz –100 Hz
Output noise 100 Hz –10 kHz
Output capacitor
µV/√(Hz)
µV/√(Hz)
µF
6
50
Ceramic capacitor with ESR range, CLDO_ESR = 0 to 100 mΩ
LED AND HIGH-SIDE SWITCH CONTROL
VHSSENSE
Current-sense voltage
370
4
400
430
60
mV
V
VINPROT –HSSENSE, high-side switch in current limit
Common-mode range for current
sensing
VCMHSSENSE
See VINPROT
Ramping negative
Ramping positive
5
26
10
70
88
87
20
38
35
50
VINPROT –HSSENSE open load
threshold
VHSOL_TH
mV
VHSOL_HY
tHSOL_BLK
Open load hysteresis
18
28
mV
µs
Open-load blanking time
100
92.5
90
140
96
Ramping positive
VINPROT –HSSENSE load short
detection threshold
VHS SC
% VHSSENSE
Ramping negative from load short condition
93
VINPROT –HSSENSE short circuit
hysteresis
VHSSC_HY
1
4
% VHSSENSE
Net time in current-limit to disable
driver
tHSS CL
5
6
ms
µs
V
tS HS
Current-limit sampling interval
Voltage at HSCTRL when OFF
100
VINPROT
VHSCTRLOFF
VINPROT
–0.5
Clamp voltage between HSSENSE –
HSCTRL
VGS
6.1
7.7
30
8.5
30
V
Time from rising HSPWM until high-side switch in current limitation,
±5% settling
µs
tON
Turn on time
Time from rising HSPWM until high-side switch until voltage-clamp
between HSSENSE –HSCTRL active (within VGS limits)
60
µs
VOS_HS
Overshoot during turnon
VOS_HS = VINPROT - HSSENSE
400
mV
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICL_HSCTRL
HSCTRL current limit
2
4.1
5
mA
Internal pullup resistors between
VINPROT and HSCTRL
RPU_HSCTRL
70
100
100
130
130
kΩ
kΩ
RPU_HSCTRL-
Internal pullup resistors between
HSCTRL and HSSENSE
70
2
HSSENSE
VI_high
VI_low
High level input voltage
Low level input voltage
Input voltage hysteresis
HSPWM input frequency
External sense resistor
HSPWM, VIO = 3.3 V
HSPWM, VIO = 3.3 V
HSPWM, VIO = 3.3 V
V
V
0.8
500
500
50
VI_hys
fHS_IN
RSENSE
150
100
1.5
mV
Hz
Ω
Design info, no device parameter
Design info, no device parameter
External MOSFET gate source
capacitance
CGS
CGD
100
2000
500
pF
pF
External MOSFET gate drain
capacitance
REFERENCE VOLTAGE
VREF
Reference voltage
3.3
V
VREF-tol
Reference voltage tolerance
Reference voltage current limit
Capacitive load
IVREF = 5 mA
1%
25
–1%
10
IREFCL
mA
µF
CVREF
0.6
5
REFns10-100
REFns100-1k
2.2-µF output capacitance, IVREF = 5 mA
2.2-µF output capacitance, IVREF = 5 mA
Threshold, VREF falling
20
Output noise 10 Hz–100 Hz
Output noise 100 Hz–10 kHz
µV/√(Hz)
µV/√(Hz)
V
6
2.91
14
3.07
70
3.12
140
20
VREF_OK
TREF_OK
Reference voltage OK threshold
Hysteresis
mV
Reference voltage OK deglitch time
10
µs
SHUTDOWN COMPARATOR (TJ = –55°C TO +150°C)
IVT_REF = 20 µA. Measured as drop voltage with respect to VDVDD
1
17
500
Shutdown comparator reference
VT_REF
voltage
mV
mA
IVT_REF = 600 µA. Measured as drop voltage with respect to
VDVDD. No VT_REF short-circuit detection.
200
420
1100
Shutdown comparator reference
current limit
IVT_REFCL
VT_REF = 0
0.6
0.9
1
1.4
1.8
Threshold, VT_REF falling. Measured as drop voltage with respect
to VDVDD
1.2
130
V
VVT_REF SH
VT_REF short circuit detection
Hysteresis
mV
Input voltage threshold on VT, rising
edge triggers shutdown
VTTH-H
0.48
0.46
0.50
0.52
0.52
VT_REF
This feature is specified by design to work down to –55°C.
Input voltage threshold on VT, falling
voltage enables device operation
VTTH-L
VTTOL
0.48
VT_REF
mV
This feature is specified by design to work down to –55°C.
Threshold variation
20
–50
–50
VTTH-H –VT_REF / 2, VTTH-L –VT_REF / 2
TJ = –20°C to +150°C
–20
–400
–200
IVT_leak
Leakage current
nA
V
TJ = –55°C to –20°C
Threshold, VT_REF rising. Measured as drop voltage with respect
to VDVDD
0.42
0.9
1.2
VT_REFOV
VT_REF overvoltage threshold
VT_REF fault deglitch time
Hysteresis
100
mV
µs
TVT_REF_FLT
WAKE INPUT
VWAKE_ON
Overvoltage or short condition on VT_REF
10
20
Voltage threshold to enable device
WAKE pin is a level sensitive input
3.3
10
3.7
20
V
Min. pulse width at WAKE to enable
device
tWAKE
VWAKE = 4 V to suppress short spikes at WAKE pin
µs
VBAT UNDERVOLTAGE WARNING
VSSENSETH_L
VSSENSETH_H
VSSENSE-HY
tVSSENSE_BLK
IVSLEAK
VSSENSE falling-threshold low
SPI selectable, default after reset
SPI selectable
4.3
6.2
4.7
6.8
V
V
VSSENSE falling-threshold high
VSSENSE hysteresis
Blanking time
0.2
V
10
35
1
µs
µA
µA
mA
VVSENSE < VSSENSETH_xx →IRQ asserted
LPM0 mode, VSSENSE 55 V
LPM0 mode, VSSENSE 60 V
LPM0 mode, VSSENSE 80 V
IVSLEAK60
Leakage current at VSSENSE
100
25
IVSLEAK80
5
Internal resistance from VSSENSE to
GND
RVSSENSE
VSSENSE = 14 V, disabled in LPM0 mode
0.7
1
1.3
MΩ
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIN OVERVOLTAGE PROTECTION
VIN overvoltage-shutdown threshold 1
(rising edge)
VOVTH_H
Selectable with SPI
50
36
60
38
V
V
VIN overvoltage-shutdown threshold 2
(rising edge)
VOVTH_L
Selectable with SPI, default after reset
Threshold 1
0.2
1.5
1.7
2
3
VOVHY
VIN overvoltage hysteresis
V
Threshold 2; default after reset
VIN > VOVTH_H →GPFET off
VIN > VOVTH_L →GPFET off
2.5
tOFF BLK-H
tOFF BLK-L
Overvoltage delay time
1
µs
µs
Overvoltage blanking time
10
20
WINDOW WATCHDOG
TESTSTART, TESTSTOP, VTCHECK , and RAMP mode:
Begins after entering each mode.
ACTIVE mode:
ttimeout
Timeout
230
300
370
ms
ms
WD timeout begins with rising edge of RESN
Spread spectrum disabled
Spread spectrum enable
18
20
22
22
tWD
Watchdog window time
19.8
24.2
tWD_FAIL
tWD_BLK
VI_high
VI_low
Closed window time
WD filter time
tWD / 4
0.5
µs
V
High level input voltage
Low level input voltage
Input voltage hysteresis
WD, VIO = 3.3 V
WD, VIO = 3.3 V
WD, VIO = 3.3 V
2
0.8
V
VI_hys
150
500
mV
RESET AND IRQ BLOCK
tRESNHOLD RESN hold time
1.8
0
2
2.2
0.4
ms
V
Low level output voltage at RESN,
PRESN and IRQ
VRESL
VIN ≥3 V, IxRESN = 2.5 mA
VIN = 0 V, VIO = 1.2 V, IxRESN = 1 mA
Vtest = 5.5 V
Low level output voltage at RESN and
PRESN
VRESL
0
0.4
1
V
Leakage current at RESN, PRESN and
IRQ
IRESLeak
µA
Number of consecutive reset events for
transfer to LPM0
NRES
7
tIRQHOLD
tDR IRQ PRESN
IRQ hold time
After VVSENSE < VSSENSETH for tVSSENSE_BLK
10
20
µs
µs
Rising edge delay of IRQ to rising
edge of PRESN
2
2
Falling edge delay of RESN to
PRESN / IRQ
tDF RESN_PRESN
µs
EXTERNAL PROTECTION
VCLAMP
Gate to source clamp voltage
14
15
20
25
25
V
VIN –GPFET, 100 µA
VIN = 14 V, GPFET = 2 V
VIN = 14 V, turn off
IGPFET
Gate turn on current
Gate driver strength
µA
Ω
RDSONGFET
THERMAL SHUTDOWN AND OVERTEMPERATURE PROTECTION
TSDTH
TSDHY
tSD-BLK
Thermal shutdown
Junction temperature
160
175
20
°C
°C
µs
Hysteresis
Blanking time before thermal shutdown
10
20
20
Overtemperature flag is implemented as local temp sensors and
expected to trigger before the thermal shutdown
TOTTH
TOTHY
tOT_BLK
Overtemperature flag
Hysteresis
150
165
20
°C
°C
µs
Blanking time before thermal over
temperature
10
VOLTAGE MONITORS BUCK1/2/3, VIO, LDO, BOOSTER
VMONTH_L
VMONTH_H
VMON_HY
Voltage monitor reference, falling edge REF = 0.8 V
Voltage monitor reference, rising edge REF = 0.8 V
90
92
108
2
94
%
%
%
106
110
Voltage monitor hysteresis
Undervoltage monitoring at VIO –
falling edge
VVIOMON_TH
VVIOMON_HY
tVMON_BLK
3
3.13
20
V
V
UV_VIO hysteresis
0.05
Blanking time between UV or OV
condition to RESN low
UV/OV = BUCK1/2/3 UV = VIO
10
µs
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Blanking time between undervoltage
condition to ERROR mode transition or
corresponding SPI bit
BUCK1/2/3 →ERROR mode LDO or BOOST →SPI bit set or turn
off
tVMONTHL_BLK
1
ms
Blanking time between undervoltage
condition to ERROR mode transition
tVMONTHL_BLK1
VIO only
10
10
20
20
µs
µs
Blanking time between overvoltage
condition to ERROR mode transition
tVMONTHH_BLK1
BUCK1/2/3 →ERROR mode VIO has no OV protection
Blanking time LDO and BOOST
overvoltage condition to corresponding
SPI bit or ERROR mode
LDO or BOOST (ACTIVE mode) →SPI bit set or turn off LDO
(VTCHECK or RAMP mode) →ERROR mode
tVMONTHH_BLK2
20
40
µs
GND LOSS
VGLTH-low
GND loss threshold low
GND loss threshold high
GND to PGNDx
GND to PGNDx
V
V
–0.31
–0.25
–0.19
VGLTH-high
0.19
0.25
0.31
Blanking time between GND loss
condition and transition to ERROR
state
tGL-BLK
5
20
µs
POWER-UP SEQUENCING
tSTART1
tSTART2
tSTART
Soft start time of BOOST
From start until exceeding VMONTH_L + VMON_HY Level
0.7
0.5
2.7
2
ms
ms
ms
Soft start time of BUCK1/2/3 and LDO From start until exceeding VMONTH_L + VMON_HY Level
Startup DVDD regulator
From start until exceeding VMONTH_L + VMON_HY Level
Internal SSDONE_BUCK1 signal
3
Sequencing time from start of BUCK1
to BUCK2 and BOOST
tSEQ2
3
14
4
ms
ms
ms
Startup time from entering
TESTSTART to RESN high
tWAKE-RES
GPFET = IRFR6215
Sequencing time from start of BOOST
to BUCK3
tSEQ1
Internal SSDONE_BOOST signal
1
INTERNAL VOLTAGE REGULATORS (TJ = –55°C to +150°C)
IVREG = 0 mA to 50 mA, VINPROT = 6.3 V to 40 V and
EXTSUP = 6.3 V to 12 V
VREG
Internal regulated supply
5.5
5.8
6.1
V
IVREG = 0 mA to 50 mA and EXTSUP ramping positive,
ACTIVE mode
VEXTSUP-TH
VEXTSUP-HY
VREGDROP
Switch over voltage
4.4
4.6
4.8
300
200
V
Switch over hysteresis
Dropout voltage on VREG
100
200
mV
mV
IVREG = 50 mA, EXTSUP = 5 V / VINPROT = 5 V and
EXTSUP = 0 V / VINPROT = 4 V
IREG_CL
EXTSUP = 0 V, VREG = 0 V
mA
mA
µF
V
–250
–250
1.2
–50
–50
3.3
Current limit on VREG
Capacitive load
IREG_EXTSUP_CL
CVREG
EXTSUP ≥4.8 V, VREG = 0 V
2.2
4
VREG rising
Hysteresis
3.8
4.2
VREG-OK
VREG undervoltage threshold
350
420
3.3
490
3.45
mV
V
VDVDD
Internal regulated low voltage supply
DVDD undervoltage threshold
DVDD overvoltage threshold
3.15
2.1
VDVDD UV
VDVDD OV
DVDD falling
DVDD rising
V
3.8
20
V
Blanking time from DVDD overvoltage
condition to shutdown mode transition
tDVDD OV
10
µs
GLOBAL PARAMETERS
RPU
Internal pullup resistor at CSN pin
70
70
100
100
200
130
130
260
kΩ
kΩ
kΩ
nA
Internal pulldown resistor at pins:
HSPWM , SDI, SCK, WD, S2(3)
RPD
RPD-WAKE
ILKG
Internal pulldown resistor at WAKE pin
140
Input pullup current at the VSENSE1–
5 and VMON1–3 pins
VTEST = 0.8 V
–200
–100
–50
Internal oscillator used for buck or
boost switching frequency
fOSC
4.6
4.9
5.2
MHz
MHz
fspread
SPI
Spread-spectrum frequency range
0.8 × fOSC
fOSC
VI_high
VI_low
VI_hys
VO_high
VO_low
High-level input voltage
Low-level input voltage
Input voltage hysteresis
SDO-output high voltage
SDO-output low voltage
CSN, SCK, SDI; VIO = 3.3 V
CSN, SCK, SDI; VIO = 3.3 V
CSN, SCK, SDI; VIO = 3.3 V
VIO = 3.3 V ISDO = 1 mA
2
V
V
0.8
150
3
500
mV
V
VIO = 3.3 V ISDO = 1 mA
0.2
V
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7.5 Electrical Characteristics (continued)
VIN = VINPROT 4.8 V to 40 V, VSUPx = 3 V to 5.5 V, EXTSUP = 0 V, TJ = –40°C to +150°C, unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CSDO
SDO capacitance
50
pF
(1) The quiescent current specification does not include the current flow through the external feedback resistor divider. Quiescent current
is non-switching current, measured with no load on the output with VBAT = 13 V.
(2) Total current consumption measured on the EVM includes switching losses.
(3) RAMP and ACTIVE only.
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7.6 SPI Timing Requirements
MIN
240
100
100
NOM
MAX UNIT
tSPI
SCK period
ns
ns
ns
tSCKL
tSCKH
SCK low time
SCK high time
Time between falling edge of CSN and SDO output valid (FSI Falling SDO < 0.8 V; Rising
tFSIV
80
55
ns
ns
bit)
SDO > 2 V
Falling SDO < 0.8 V; Rising
SDO > 2 V
tSDOV
Time between rising edge of SCK and SDO data valid
tSDIS
Setup time of SDI before falling edge of SCK
Hold time for SDI after falling edge of SCK
Hold time of CSN after last falling edge of SCK
Delay between rising edge of CSN and SDO tri-state
Minimum time between two SPI commands
20
20
50
ns
ns
ns
ns
µs
tSDIH
tHCS
tSDOtri
tmin2SPI
80
10
CSN
SCK
TSPI
tHcs
tFSIV
tSDOV
tSCKL
tSCKH
tSDOtri
FSI
Bit15
Bit14
Bit0
SDO
tSDIS
tSDIH
Bit15
Bit14
Bit0
SDI
图7-1. SPI Timing
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7.7 Typical Characteristics
All parameters are measured on the TI EVM, unless otherwise specified. For efficiency measurement setup,
please see to SLVA610.
Buck 1 Characteristics
图7-2. Reduction of Current Limit vs Duty Cycle
Buck 2 and 3 Characteristics
VSUP3 = 3.8 V, 25°C
810
VSUP3 = 3.3 V, 25°C
VSUP3 = 5 V, 25°C
VSUP2 = 3.8 V, 25°C
804
808
VSUP3 = 3.8 V, 140°C
VSUP2 = 5 V, 25°C
VSUP3 = 3.8 V, -40°C
806
804
802
800
798
796
794
792
790
802
800
798
796
794
792
790
VSUP2 = 3.8 V, 140°C
VSUP2 = 3.8 V, -40°C
0
0.5
1
1.5
2
0
0.5
1
1.5
2
Load Current (A)
Load Current (A)
图7-3. Load Regulation Buck2 = 3.3 V EXTSUP Pin
图7-4. Load Regulation Buck3 = 1.2 V EXTSUP Pin
Open
Open
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805
804
803
802
801
800
799
798
797
796
805
804
803
802
801
800
799
798
797
796
795
25°C
25°C
-40°C
140°C
-40°C
140°C
795
2
2
4
6
8
10
12
4
6
8
10
12
VSUP3 (V)
VSUP2 (V)
图7-5. Open-Load Line Regulation Buck2 = 3.3 V
图7-6. Open-Load Line Regulation Buck3 = 1.2 V
EXTSUP Pin Open
EXTSUP Pin Open
6
5.5
5
10
9
8
4.5
4
7
6
3.5
3
5
2.5
2
4
3
25°C
25°C
1.5
-40°C
125°C
2
1
-40°C
1
140°C
0.5
0
0
3
5
7
9
11
2
4
6
8
10
12
VSUP2 (V)
VSUP3 (V)
图7-7. Open-Load Supply Current Buck2 = 3.3 V
图7-8. Open-Load Supply Current Buck3 = 1.2 V
EXTSUP Pin Open
EXTSUP Pin Open
801
800.5
800
802
801.5
801
800.5
800
799.5
799
799.5
798.5
VSUP2 = 3.8 V, NO LOAD
VSUP3 = 3.8 V, NO LOAD
799
798
-50
-30
-10
10
30
50
70
90
110
130
150
798.5
-50
-30
-10
10
30
50
70
90
110
130
150
Temperature (°Celcius)
Temperature (°Celcius)
图7-9. Buck2 = 3.3-V VSENSE2 vs Temperature
图7-10. Buck3 = 1.2-V VSENSE3 vs Temperature
EXTSUP Pin Open
EXTSUP Pin Open
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Boost Characteristics
0.81
0.805
0.8
0.81
0.805
0.8
0.795
0.79
0.795
0.79
0
0.1
0.2
0.3
0.4
0.5
3
3.2
3.4
3.6
3.8
4
Load Current (A)
VSUP5 (V)
图7-12. Load Regulation Boost = 5 V At 25°C
Extsup Pin Open, Boost Supply Input = 3.8 V
图7-11. Open-Load Line Regulation Boost = 5 V At
25°C Extsup Pin Open, Boost Supply Input = 3.8 V
805
804
803
802
801
800
799
798
797
796
795
-50
0
50
100
150
Temperature (°Celcius)
图7-13. Boost = 5-V Vsense5 vs Temperature Extsup Pin Open, Input Supply = 3.8 V, 0.4 A Load
LDO Noise Characteristics
(2 × 3.3-µF output capacitance, LDO output = 2.5 V, VSUP4 = 3.8 V)
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10
9
8
7
6
5
4
3
2
1
0
Noise [LDO ON]
Noise [LDO OFF]
(Noisefloor)
10
100
1000
10000
Frequency (Hz)
图7-14. LDO Noise Density
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8 Detailed Description
8.1 Overview
The device includes one high-voltage buck controller for pre-regulation combined with a two-buck and one-boost
converter for post regulation. A further integrated low-dropout (LDO) regulator rounds up the power-supply
concept and offers a flexible system design with five independent-voltage rails. The device offers a low power
state (LPM0 with all rails off) to reduce current consumption in case the system is constantly connected to the
battery line. All outputs are protected against overload and over temperature. An external PMOS protection
feature makes the device capable of sustaining voltage transients up to 80 V. This external PMOS is also used in
safety-critical applications to protect the system in case one of the rails shows a malfunction (undervoltage,
overvoltage, or overcurrent).
Internal soft-start ensures controlled startup for all supplies. Each power-supply output has an adjustable output
voltage based on the external resistor-network settings.
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8.2 Functional Block Diagram
VBAT
VINPROT
IRQ
UV
OV
Protection
Warning
DVDD
+
POR
VEXTSUP-TH
VBUCK1
5.8V
VREG
VIO
UV
Monitoring
Bandgap1
Bandgap2
VREG
RESN
PRESN
WD
BOOT1
RESET
/
Window
Watchdog
Digital
Logic
GU
PH1
WAKE
Wake Up
circuit
GL
PGND1
CSN
SCK
SDO
SDI
COMP1
S1
SPI
VBUCK1
S2
+
-
Bandgap3
VREF
VSENSE1
VMON1
Voltage
Monitoring
DVDD
VT_REF
VT
Short
Protection
VBUCK1
Sync. Buck Converter
BUCK2
(low voltage)
VSUP2
BOOT2
+
-
GND
LT
VBuck2
VINPROT
PH2
Shutdown
Comparator
GND
COMP2
PGND2
HSSENSE
HSCTRL
HSPWM
VSENSE2
VMON2
LED Driver
Voltage
Monitoring
VBUCK1
VBUCK1
COMP5
Sync. Buck Converter
BUCK3
(low voltage)
VSUP3
Booster
LDO
(Low voltage)
BOOT3
PH5
VBuck3
PH3
Charge
Pump
PGND5
COMP3
PGND3
SMPS
Voltage
Mode
VBOOST
+
-
VBooster
VSENSE3
VMON3
VSENSE5
Control
Voltage
Monitoring
Voltage
Monitoring
Voltage
Monitoring
VLDO
图8-1. Detailed Block Diagram
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8.3 Feature Description
8.3.1 Buck Controller (Buck1)
8.3.1.1 Operating Modes
Mode of Operation Description
Normal Mode
(RAMP, ACTIVE)
Constant frequency current mode
Continuous or discontinuous mode
8.3.1.2 Normal Mode PWM Operation
The main buck controller operates using constant frequency peak current mode control. The output voltage is
programmable with external resistors.
The switching frequency is set to a fixed value of ƒSWBUCK1. Peak current-mode control regulates the peak
current through the inductor such that the output voltage VBUCK1 is maintained to its set value. Current mode
control allows superior line-transient response. The error between the feedback voltage VSENSE1 and the
internal reference produces an error signal at the output of the error amplifier (COMP1) which serves as target
for the peak inductor current. At S1–S2, the current through the inductor is sensed as a differential voltage and
compared with this target during each cycle. A fall or rise in load current produces a rise or fall in voltage at
VSENSE1, which causes COMP1 to rise or fall respectively, thus increasing or decreasing the current through
the inductor until the average current matches the load. In this way the output voltage VBUCK1 is maintained in
regulation.
Sense Resistor
VINPROT
L
RS
GU
HS DCR Sensing
L
RL
VBUCK1
PH
PWM
Gate
Drivers
Logic
GL
LS
RDCR
CDCR
Current
Comparator
S1
S2
Current
Sensing
VS1-S2, INT
VS1-S2, EXT
VSLOPE
Slope
Compensation
VSENSE1
COMP1
gm
C2
Error
Amp
Current Loop
(Inner Loop)
R1
C1
Voltage Loop (Outer Loop)
图8-2. Detailed Block Diagram Of Buck 1 Controller
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The high-side N-channel MOSFET is turned on at the beginning of each clock cycle and kept on until the
inductor current reaches its peak value as set by the voltage loop. Once the high external FET is turned OFF,
and after a small delay (shoot-through delay), the lower N-channel MOSFET is turned on until the start of the
next clock cycle. In dropout operation the high-side MOSFET stays on 100%. In every fourth period the duty
cycle is limited to 95% in order to charge the bootstrap capacitor at BOOT1. This allows a maximum duty cycle
of 98.75%.
The maximum value of COMP1 is clamped so that the maximum current through the inductor is limited to a
specified value. The BUCK1 controller output voltage is monitored by a central independent voltage-monitoring
circuit, which has an independent voltage-monitoring bandgap reference for safety reasons. In addition, BUCK1
is thermally protected with a dedicated temperature sensor.
8.3.2 Synchronous Buck Converters Buck2 And Buck3
Both regulators are synchronous converters operating with a fixed switching frequency ƒSW = 0.98 MHz. For
each buck converter, the output voltage is programmable with external resistors. The synchronous operation
mode improves the overall efficiency. BUCK3 switches in phase with BUCK1, and BUCK2 switches at a 216°
shift to BUCK3 to minimize input current ripple.
Each buck converter can provide a maximum current of 2 A and is protected against short circuits to ground. In
case of a short circuit to ground, the integrated cycle-by-cycle current limit turns off the high-side FET when its
current reaches IHS-Limit and the low-side FET is turned on until the end of the given cycle. When the current limit
is reached in the beginning of the cycle for five consecutive cycles, the pulse-width modulation (PWM) is forced
low for eight cycles to prevent uncontrolled current build-up. In case the low-side current limit of ILS-Limit is
reached, for example, due an output short to VSUP2/3, the low-side FET is turned off until the end of the cycle. If
this is detected shortly after the high-low PWM transition (immediately after the low-side overcurrent comparator
blanking time), both FETs are turned off for eight cycles.
The output voltages of BUCK2/3 regulators are monitored by a central independent voltage-monitoring circuit,
which has an independent voltage-monitoring bandgap reference for safety reasons. In addition BUCK2 and
BUCK3 are thermally protected with a dedicated temperature sensor.
8.3.3 BOOST Converter
The BOOST converter is an asynchronous converter operating with a fixed switching frequency ƒSW = 0.98 MHz.
It switches in phase with BUCK1. At low load, the boost regulator switches to pulse skipping.
The output voltage is programmable with external resistors.
The internal low-side switch can handle maximum 1-A current, and is protected with a current limit. In case of an
overcurrent, the integrated cycle-by-cycle current-limit turns off the low-side FET when the current reaches
ICLBOOST until the end of the given cycle. When the current-limit is reached in the beginning of the cycle for five
consecutive cycles, the PWM is forced low for eight cycles to prevent uncontrolled current build-up.
The BOOST converter output voltage is monitored by a central independent voltage-monitoring circuit, which has
an independent voltage-monitoring bandgap reference for safety reasons. If the VMONTH_L > VSENSE5 or VSENSE5
> VMONTH_H, the output is switched off and the BOOST_FAIL bit in the SPI PWR_STAT register is set. The
BOOST can be reactivated by setting BOOST_EN bit in the PWR_CONFIG register.
In addition, the BOOST converter is thermally protected with a dedicated temperature sensor. If TJ > TOTTH, the
BOOST converter is switched off and bit OT_BOOST in PWR_STAT register is set. Reactivation of the booster is
only possible if the OT_BOOST bit is 0, and the booster enable bit in the PWR_CONFIG register is set to 1.
8.3.4 Frequency-Hopping Spread Spectrum
The TPS65310A-Q1 features a frequency-hopping pseudo-random spectrum or triangular spreading
architecture. The pseudo-random implementation uses a linear feedback shift register that changes the
frequency of the internal oscillator based on a digital code. The shift register is designed in such a way that the
frequency shifts only by one step at each cycle to avoid large jumps in the buck and BOOST switching
frequencies. The triangular function uses an up-down counter. Whenever spread spectrum is enabled (SPI
command), the internal oscillator frequency is varied from one BUCK1 cycle to the next within a band of 0.8 x
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fOSC ... fOSC from a total of 16 different frequencies. This means that BUCK3 and BOOST also step through 16
frequencies. The internal oscillator can also change its frequency during the period of BUCK2, yielding a total of
31 frequencies for BUCK2.
8.3.5 Linear Regulator LDO
The LDO is a low drop out regulator with an adjustable output voltage through an external resistive divider
network. The output has an internal current-limit protection in case of an output overload or short circuit to
ground. In addition, the output is protected against overtemperature. If TJ > TOTTH, the LDO is switched off and
bit OT_LDO in PWR_STAT register is set. Reactivation of the LDO is only possible through the SPI by setting
the LDO enable bit in the PWR_CONFIG register to 1 if the OT_LDO bit is 0.
The LDO output voltage is monitored by a central independent voltage-monitoring circuit, which has an
independent voltage-monitoring bandgap reference for safety reasons. If the VMONTH_L > VSENSE4 or VSENSE4
>
VMONTH_H, the output is switched off and the LDO_FAIL bit in the SPI PWR_STAT register is set. The LDO can
be reactivated through the SPI by setting the LDO_EN bit in the PWR_CONFIG register. In case of overvoltage
in VTCHECK and RAMP mode, the GPFET is turned off and the device changes to ERROR mode.
8.3.6 Gate Driver Supply
The gate drivers of the BUCK1 controller, BUCK2 and BUCK3 converters and the BOOST converter are
supplied from an internal linear regulator. The internal linear regulator output (5.8-V typical) is available at the
VREG pin and must be decoupled using a typical 2.2-μF ceramic capacitor. This pin has an internal current-limit
protection and must not be used to power any other circuits.
The VREG linear regulator is powered from VINPROT by default when the EXTSUP voltage is lower than 4.6 V
(typical).
If the VINPROT is expected to go to high levels, there can be excessive power dissipation in this regulator when
using large external MOSFETs. In this case, it is advantageous to power this regulator from the EXTSUP pin,
which can be connected to a supply lower than VINPROT but high enough to provide the gate drive. When
EXTSUP is connected to a voltage greater than 4.6 V, the linear regulator automatically switches to EXTSUP as
its input to provide this advantage. This automatic switch-over to EXTSUP can only happen once the
TPS65310A-Q1 device reaches ACTIVE mode. Efficiency improvements are possible when one of the switching
regulator rails from the TPS65310A-Q1 device, or any other voltage available in the system is used to power
EXTSUP. The maximum voltage that must be applied to EXTSUP is 12 V.
8.4 Device Functional Modes
8.4.1 RESET
RESN and PRESN are open drain outputs which are active if one or more of the conditions listed in 表 8-1 are
valid. RESN active (low) is extended for tRESNHOLD after a reset is triggered. RESN is the main processor reset
and also asserts PRESN as a peripheral signal.
PRESN is latched and is released when window trigger mode of the watchdog is enabled (first rising edge at WD
pin).
RESN and PRESN must keep the main processor and peripheral devices in a defined state during power up and
power down in case of improper supply voltages or a critical failure condition. Therefore, for low supply voltages
the topology of the reset outputs specify that RESN and PRESN are always held at a low level when RESN and
PRESN are asserted, even if VIN falls below VPOR or the device is in SHUTDOWN mode.
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Loss of LPM clock
Thermal Shutdown
RESN
Mono
Flop
WD_RESET
Loss of GND
POR
≥1
Voltage Monitor Buck1-3 fail
Voltage Monitor VIO fail
Over Temperature BUCK1-3, VREG
Over Voltage LDO
PRESN
RESET
≥1
S
R
Q
WD Trigger
Over-Current BUCK1
图8-3. RESET Functionality
表8-1. RESET Conditions
RESET CONDITIONS
The device reinitializes all registers with their default values. Error counter
is cleared.
POR, Loss of LPM Clock, and Thermal Shutdown
Voltage Monitor BUCK 1-3
Input voltage at VMON1-3 pin out-of-bounds:
VVMON1-3 < VMONTH_L or VVMON1-3 > VMONTH_H
Over Voltage LDO
Voltage Monitor VIO
Loss of GND
Vsense4 > VMONTH_H
Input voltage at VIO pin out-of-bounds: VVIO < VVIOMON TH
Open at PGNDx or GND pin
OT BUCK1-3, VREG
WD_RESET
Overtemperature on BUCK1–3 or VREG
Watchdog window violation
Any reset event (without POR, thermal shutdown, or loss of LPM clock) increments the error counter (EC) by
one. After a reset is consecutively triggered NRES times, the device transfers to the LPM0 state, and the EC is
reset to 0. The counter is decremented by one if an SPI LPM0_CMD is received. Alternatively, the device can be
put in LOCK state once an SPI LOCK_CMD is received. Once the device is locked, it cannot be activated again
by a wake condition. The reset counter and lock function avoid cyclic start-up and shut-down of the device in
case of a persistent fault condition. The reset counter content is cleared with a POR condition, a thermal
shutdown or a loss of LPM clock. Once the device is locked, a voltage below VPOR at the VIN pin or a thermal
shutdown condition are the only ways to unlock the device.
8.4.2 Soft Start
The output voltage slopes of BUCK, BOOST and LDO regulators are limited during ramp-up (defined by tSTARTx).
During this period the target output voltage slowly settles to its final value, starting from 0 V. In consequence,
regulators that offer low-side transistors (BUCK1, BUCK2 and BUCK3) actively discharge their output rails to the
momentary ramp-value if previously charged to a higher value.
8.4.3 INIT
Coming from a power-on reset the device enters INIT mode. The configuration data from the EEPROM is loaded
in this mode. If the checksum is valid and the internal VREG monitor is indicating an undervoltage condition
(self-test VREG comparator), the device enters TESTSTART.
8.4.4 TESTSTART
TESTSTART mode is entered:
• After the INIT state (coming from power on)
• After detecting that VT > VTTH-H
• After ERROR mode and the fail condition is gone
• After a wake command in LPM0
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In this mode the OV/UV comparators of BUCK1-3, BOOST, LDO and VIO are tested. The test is implemented in
such a way that during this mode all comparators have to deliver a 1 (fail condition). If this is the case the device
enters TESTSTOP mode.
If this is not the case, the device stays in TESTSTART. If the WAKE pin is low, the device enters LPM0 after
ttimeout. If the WAKE pin is high, the part stays in TESTSTART.
8.4.5 TESTSTOP
In this mode the OV/UV comparators are switched to normal operation. It is expected that only the UV
comparators give a fail signal. In case there is an OV condition on any rail or one of the rails has an
overtemperature the device stays in TESTSTOP. If the WAKE pin is low the device enters LPM0 mode after
ttimeout. If the WAKE pin is high, the part stays in TESTSTOP. If there is no overvoltage and overtemperature
detected, the part enters VTCHECK mode.
8.4.6 VTCHECK
VTCHECK mode is used to:
1. Switch on the external GPFET in case VIN < VOVTH_L
2. Turn on the VREG regulator and VT_REF
3. Check if the voltage on pin VT < VTTH-L
4. Check if the SMPS clock is running correctly
5. Check if the VREG,VT_REF exceeds the minimum voltage
If all checks are valid the part enters the RAMP state. In case the device is indicating a malfunction and the
WAKE pin is low, the device enters LPM0 after ttimeout to reduce current consumption.
In case the voltage monitors detect an overvoltage condition on BUCK1-3/LDO, a loss of GND or an
overtemperature condition on BUCK1-3 / VREG the device enters ERROR mode and the error counter is
increased.
8.4.7 RAMP
In this mode the device runs through the power-up sequencing of the SMPS rails (see Power-Up Sequencing).
8.4.8 Power-Up Sequencing
After the power-up sequence (described in 图 8-4), all blocks are fully functional. BUCK1 starts first. After tSEQ2
elapses and BUCK1 is above the undervoltage threshold, BUCK2 and BOOST start. BUCK3 and VREF start
one tSEQ1 after BUCK2. After the release of RESN pin, the µC can enable the LDO per SPI by setting bit 4
LDO_EN in PWR_CONFIG register to 1 (per default, this LDO_EN is set to 0 after each reset to the µC).
In case any of the conditions listed below happen during power-up sequencing, the device enters ERROR mode
and the error counter (EC) is increased:
• Overtemperature on BUCK1-3 or VREG
• Overvoltage on BUCK1-3 or LDO
• Overcurrent on BUCK1
• SMPS clock fail
• VT_REF/VREG undervoltage
• Loss of GND
In case VT > VTTH-H, the device transitions to TESTSTART.
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WakeUp event through WAKE pin
VPOR
VIN
tSTART
VINPROT
VREG-OK / VVT_REF_SH
VREG/
VT_REF
VMONTH_L + VMON_HY
BUCK1
BUCK1 > VMONTH_L + VMON_HY AND tSEQ2 elapsed before BUCK2 and BOOST are enabled
tSTART2
tSEQ2
VMONTH_L + VMON_HY
BOOSTER
tSTART1
VMONTH_L + VMON_HY
BUCK2
VREF
tSTART2
VREF_OK
VMONTH_L + VMON_HY
BUCK3
LDO
LDO enabled through SPI by mC
tSEQ1
tSTART2
VMONTH_L + VMON_HY
tSTART2
tRESNHOLD
RESN
tWAKE-RES
WD
Only when device
is in ACTIVE state
PRESN
With the device in LPM0 mode, the start point of VREG/VT_REF is with the rising edge of WAKE. When input
voltage is first applied, the rising edge of the VIN pin initiates the start-up sequence even if WAKE is low, and
enters LPM0 mode if WAKE remains low through NRES timeout events.
图8-4. Power-Up Sequencing
After the power-up sequence is completed (except LDO) without detecting an error condition, the device enters
ACTIVE mode.
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8.4.9 Power-Down Sequencing
There is no dedicated power-down sequencing. All rails are switched off at the same time. The external FETs of
BUCK1 are switched off and the outputs of BUCK2/3/BOOST (PHx) and the LDO are switched in a high-
impedance state.
8.4.10 Active
This is the normal operating mode of the device. Transitions to other modes:
→ERROR
The device is forced to go to ERROR in case of:
• Any RESET event (without watchdog reset)
• VREG/VREF/VT_REF below undervoltage threshold
• SMPS clock fail
During the transition to ERROR mode the EC is incremented.
→LOCKED
In case a dedicated SPI command (SPI_LOCK_CMD) is issued.
→TESTSTART
The device moves to TESTSTART after detecting that VT < VTTH-L
.
→LPM0
The device can be forced to enter LPM0 with a SPI LPM0 command. During this transition the EC is
decremented.
If the EC reaches the NRES value, the device transitions to LPM0 mode and EC is cleared. Depending on the
state of the WAKE pin, the device remains in LMP0 (WAKE pin low) or restart to TESTSTART (WAKE pin high).
To indicate the device entered LPM0 after EC reached NRES value, a status bit EC_OF (error counter overflow,
SYS_STAT bit 3) is set. The EC_OF bit is cleared on read access to the SYS_STAT register.
A watchdog reset in ACTIVE mode only increases the EC, but it does not change the device mode.
8.4.11 ERROR
In this mode all power stages and the GPFET are switched off. The devices leave ERROR mode and enter
TESTSTART if:
• All rails indicate an undervoltage condition
• No GND loss is detected
• No overtemperature condition is detected
When the EC reaches the NRES value, the device transitions to LPM0 and the EC is cleared. To indicate the
device entered LPM0 after EC reached NRES, a status bit EC_OF (error counter overflow, SYS_STAT bit 3) is
set. The EC_OF bit is cleared on read access to the SYS_STAT register.
8.4.12 LOCKED
Entering this mode disables the device. The only way to leave this mode is through a power-on reset, thermal
shutdown, or the loss of an LPM clock.
8.4.13 LPM0
Low-power mode 0 is used to reduce the quiescent current of the system when no functionality is needed. In this
mode the GPFET and all power rails except for DVDD are switched off.
In case a voltage > VWAKE_ON longer than tWAKE is detected on the WAKE pin, the part switches to TESTSTART
mode.
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8.4.14 Shutdown
The device enters and stays in this mode, as long as TJ > TSDTH - TSDHY or VIN < VPOR or DVDD under or
overvoltage, or loss of low power clock is detected. Leaving this mode and entering INIT mode generates an
internal POR.
8.4.14.1 Power-On Reset Flag
The POR flag in the SYS_STAT SPI register is set:
• When VIN is below the VPOR threshold
• System is in thermal shutdown
• Over or undervoltage on DVDD
• Loss of low power clock
8.4.15 Wake Pin
Only when the device is in LPM0 mode, it can be activated by a positive voltage on the WAKE pin with a
minimum pulse width tWAKE. A valid wake condition is latched. Normal deactivation of the device can only occur
through the SPI Interface by sending an SPI command to enter LMP0. Once in LMP0, the device stays in LPM0
when the WAKE pin is low, or restarts to TESTSTART when the WAKE pin is high.
The WAKE pin has an internal pulldown resistance RPD-WAKE, and the voltage on the pin is not allowed to
exceed 60 V. A higher voltage compliance level in the application can be achieved by applying an external series
resistor between the WAKE pin and the external wake-up signal.
The device cannot be re-enabled by toggling the WAKE pin when the device is in LOCKED state (by SPI
command).
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PowerOn
Reset
VIN > VPOR
(EC==0)
VT>VTTH-H (if enabled)
VT_ref_ok = ”1‘
& VT<VTTH-L
& vreg_ok = ”1‘
& SMPS clock O.K.
VTCHECK
RAMP
no OV (BUCK1, LDO)
Independent voltage monitors
(IVM)
OV (BUCK1, LDO)
& Tj < TOTTH
OR OV (BUCK2,3 if
enabled)
OR Tj > TOTTH
(BUCK1-3,VREG)
OR vreg_ok = ”0‘
OR VT_ref_ok = ”0‘
OR no SMPS clock
OR BUCK1 OC
OR GND LOSS
(EC++)
Timeout**
& WAKE
pin low
INIT
OV (BUCK1, LDO)
OR Tj > TOTTH
(BUCK1-3,VREG)
OR GND LOSS
(EC++)
TESTSTOP
CRC=O.K.
& EE ready
& Vreg_ok = 0
READY****
UV and OV
Independet voltage
monitors
Timeout**
& WAKE
pin low
& VIO
Timeout**
& WAKE
pin low
Voltage Monitors < VMONTHL
& Tj < TOTTH
TESTSTART
ERROR
EC=NRES (ECã0, EC_OFã1)
Timeout**
& WAKE
pin low
WD Reset
(EC++)
VT>VTTH-H
All RESET events*** (w/o WD)
OR vreg_ok = ”0‘
(if enabled)
Wake
(WAKE pin
high)
OR vref_ok = ”0‘
OR VT_REF_ok = ”0‘
OR no SMPS clock
(EC++)
EC=NRES
(ECã0, EC_OFã1)
OR SPI LPM0 CMD
(EC--)
ACTIVE
LPM0
SPI LOCK CMD
LOCKED
Tj>TSDTH OR VIN < VPOR
OR DVDD UV/OV
OR loss of low power clock
* GPFET is turned on in VTCHECK, RAMP, ACTIVE and if
VIN<VINOV
** TIMEOUT counter will be reset with every state transition
*** RESET EVENTS : WD, GROUND LOSS, VOLTAGE
MONITOR BUCK1, MONITOR BUCK2-3(if enabled), Over
Voltage LDO (if enabled), VOLTAGE MONITOR VIO,
OVERTEMPERATURE BUCK1-3 OR VREG, BUCK1
OVERCURRENT
SHUTDOWN
Generation of
POR
**** READY = VREF_OK & not BUCK1_UV & Power Up
Sequence completed
图8-5. Operating Mode Transitions
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8.4.16 IRQ Pin
The IRQ pin has two different functions. In OPERATING mode, the pin is forced low when the voltage on the
battery line is below the VSSENSETHx threshold. The IRQ pin is low as long as PRESN is low. If PRESN goes high
and the battery line is already below the VSSENSETHx threshold, the IRQ pin is forced high for tVSSENSE_BLK
.
8.4.17 VBAT Undervoltage Warning
• Low battery condition on VSSENSE asserts IRQ output (interrupt for µC, open drain output)
• Sense input can be directly connected to VBAT through the resistor
• Detection threshold for undervoltage warning can be selected through the SPI.
• An integrated filter time avoids false reaction due to spikes on the VBAT line.
8.4.18 VIN Over Or Undervoltage Protection
• Undervoltage is monitored on the VIN line, for POR generation.
• Two VIN overvoltage shutdown thresholds (VOVTH) can be selected through the SPI. After POR, the lower
threshold is enabled.
• During LPM0, only the POR condition is monitored.
• An integrated filter time avoids false reaction due to spikes on the VIN line.
• In case of overvoltage, the external PMOS is switched off to protect the device. The BUCK1 controller is not
switched off and it continues to run until the undervoltage on VREG or BUCK1 output is detected.
VINPROT
VBAT
VSSENSE
VIN
GPFET
IRQ
UV
OV
LOCKED
ERROR
LPM0
PWR_CMD
Bit0
LV_THRES
=
=
≥1
INIT
TESTSTART
TESTSTOP
DVDD
+ POR
图8-6. Overvoltage Or Undervoltage Detection Circuitry
8.4.19 External Protection
The external PMOS switch is disabled if:
• The device detects VIN overvoltage
• The device is in ERROR, LOCKED, POR, INIT, TESTSTART, TESTSTOP or LPM0 mode
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备注
Depending on the application, the external PMOS can be omitted as long as VBAT < 40 V
VSSENSE
VIN
PCH
PCH
GPFET
VINPROT
20µA
50 œ 60V
GND
图8-7. PMOS Control Circuitry
8.4.20 Overtemperature Detection And Shutdown
There are two levels of thermal protection for the device.
Overtemperature is monitored locally on each regulator.
OT for BUCK1-3: If a thermal monitor on the buck rails reaches a threshold higher than TOTTH, the device enters
ERROR mode. Leaving ERROR mode is only possible if the temperature is below TOTTH –TOTHY
.
OT for BOOST/LDO: If the temperature monitor of the BOOST or the LDO reaches the TOTTH threshold, the
corresponding regulator is switched off.
Overtemperature Shutdown: is monitored on a central die position. In case the TSDTH is reached, the device
enters shutdown mode. It leaves shutdown when the TSD sensor is below TSDTH – TSDHY. This event internally
generates a POR.
8.4.21 Independent Voltage Monitoring
The device contains independent voltage-monitoring circuits for BUCK1–3, LDO, VIO and BOOST. The
reference voltage for the voltage monitoring unit is derived from an independent bandgap. BUCKs 1–3 use
separate input pins for monitoring. The monitoring circuit is implemented as a window comparator with an upper
and lower threshold.
If there is a violation of the upper (only LDO [RAMP, VTCHECK], or BUCK1–3) or lower threshold (only
BUCK1–3, or VIO), the device enters ERROR mode, RESN and PRESN are asserted low, the external PMOS
(main system switch) is switched off, and the EC is incremented.
In TESTSTART mode, a self-test of the independent voltage monitors is performed.
In case any of the supply rails for BUCK2/3, LDO or BOOST are not used in the application, the respective
VMON2/3 or VSENSE4/5 pin of the unused supply must be connected to VMON1. Alternatively, the VSENSE4
pin can also be connected directly to ground in case the LDO is not used.
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8.4.22 GND Loss Detection
All power grounds PGNDx are monitored. If the voltage difference to GND exceeds VGLTH-low or VGLTH-high, the
device enters ERROR mode. RESN and PRESN are asserted low, the external PMOS (main system switch) is
switched off, and the EC is incremented.
8.4.23 Reference Voltage
The device includes a precise voltage reference output to supply a system ADC. If this reference voltage is used
in the application, a decoupling capacitor between 0.6 and 5 µF must be used. If this reference voltage is not
used in the application, this decoupling capacitor can be left out. The VREF output is enabled in RAMP state.
The output is protected against a short to GND.
8.4.24 Shutdown Comparator
An auxiliary, short circuit protected output supplied from DVDD is provided at the VT_REF pin. It is used as a
reference for an external resistive divider to the VT pin. In case a voltage > VTTH is detected on the VT pin, the
main switch (external PMOS driven by GPFET) is switched off. This functionality can be used to monitor over
and under temperature (using a NTC resistor) to avoid operation below or above device specifications.
If the voltage at VT_REF falls below VVT_REF SH while the shutdown comparator is enabled, an ERROR transition
occurs. The shutdown comparator is enabled in VTCHECK state, and can be turned off by SPI. Disabling the
comparator saves power by also disabling the VT_REF output.
8.4.25 LED And High-Side Switch Control
This module controls an external PMOS in current-limited high-side switch.
The current levels can be adjusted with an external sense resistor. Enable and disable is done with the HS_EN
bit. The switch is controlled by the HSPWM input pin. Driving HSPWM high turns on the external FET.
The device offers an open load diagnostic indicated by the HS_OL flag in the SPI register PWR_STAT. Open
load is also indicated in case the voltage on VINPROT–VSSENSE does not drop below the threshold when
PWM is low (self-test).
A counter monitors the overcurrent condition to detect the risk of overheating. While HSPWM = high and HS_EN
= high the counter is incremented during overcurrent conditions, and decremented if the current is below the
overcurrent threshold at a sampling interval of tS HS (shown in 图 8-9). When reaching a net current limit time of
tHSS CL, the driver is turned off and the HS_EN bit is cleared. This feature can be disabled by SPI bit HS_CLDIS.
When HS_EN is cleared, the counter is reset.
VINPROT
VINPROT
HSPWM
VHSOL_TH
VHSSENSE
OL
HSSENSE
VHS_SC
HSCTRL
SC
ECU
Connector
图8-8. High-Side Control Circuit
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VHSPWM
PWM
VVINPROT - VHSSENSE
VHSSENSE
VHS_SC
countermax ) tHSS_CL
HS_EN
HS_CLDIS
图8-9. HS Overcurrent Counter
备注
In case the LED or High-Side Switch Control is not used in the application, HSSENSE must be
connected to VINPROT
8.4.26 Window Watchdog
WD in Operating Mode:
The WD is used to detect a malfunction of the MCU and DSP. Description:
• Timeout trigger mode with long timing starts on the rising edge at RESN
• Window trigger mode with fixed timing after the first and each subsequent rising edge at the WD pin
• Watchdog is triggered by rising edge at the WD pin
A watchdog reset happens by:
• A trigger pulse outside the WD trigger open window
• No trigger pulse during window time
After the RESN pin is released (rising edge) the DSP and MCU must trigger the WD by a rising edge on the WD
pin within a fixed time ttimeout. With this first trigger, the window watchdog functionality is released.
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Start of tWD time with a
rising edge of WD
VWD
WD Trigger fail
WD Trigger open window
tWD_FAIL_min
tWD_FAIL_max
t
tWD1_min
tWD_min
tWD_max
图8-10. WD Window Description
8.4.27 Timeout In Start-Up Modes
A timer is used to limit the time during which the device can stay in each of the start-up modes: TESTSTART,
TESTSTOP, VTCHECK and RAMP. If the device enters one of these start-up modes and VIN or VT is not in a
proper range, the part enters LPM0 after ttimeout is elapsed and the WAKE pin is low.
8.5 Programming
8.5.1 SPI
The SPI provides a communication channel between the TPS65310A-Q1 device and a controller. The
TPS65310A-Q1 device is always the peripheral. The processor/MCU is always the controller . The SPI controller
selects the TPS65310A-Q1 device by setting CSN (chip select) to low. SDI (peripheral in) is the data input, SDO
(peripheral out) is the data output, and SCK (serial clock input) is the SPI clock provided by the controller. If chip
select is not active (high), the data output SDO is high impedance. Each communication consist of 16 bits.
1 bit parity (odd) (parity is built over all bits including: R/W, CMD_ID[5:0], DATA[7:0])
1 bit R/W; read = 0 and write = 1
6 bits CMD identifier
8 bits data
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Parity
R/W
CMD_ID5 CMD_ID4 CMD_ID3 CMD_ID2 CMD_ID1 CMD_ID0 DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
图8-11. SPI Bit-Frame
Each command is valid if:
• A valid CMD_ID is sent
• The parity bit (odd) is correct
• Exactly 16 SPI clocks are counted between falling and rising edge of CSN
The response to each controller command is given in the following SPI cycle. The response address is the
CMD_ID of the previous sent message and the corresponding data byte. The response data is latched with the
previous cycle such that a response to a write command is the status of the register before the write access.
(Same response as a read access.) The response to an invalid command is the original command with the
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correct parity bit. The response to an invalid number of SPI clock cycles is a SPI_SCK_FAIL communication
(CMD_ID = 0x03). Write access to a read-only register is not reported as an SPI error and is treated as a read
access. The initial answer after the first SPI command sent is: CMD_ID[5:0] = 0x3F and Data[7:0] 0x5A.
8.5.1.1 FSI Bit
The peripheral transmits an FSI bit between the falling edge of CSN and the rising edge of SCK. If the SDO line
is high during this time, a failure occurred in the system and the MCU must use the PWR_STAT to get the root
cause. A low level of SDO indicates normal operation of the device.
The FSI bit is set when: PWR_STAT ! = 0x00, or (SYS_STAT and 0x98) ! = 0x00, or SPI_STAT ! = 0x00. The FSI
is cleared when all status flags are cleared.
8.6 Register Maps
8.6.1 Register Description
表8-2. Register Description
CMD_ID
0x00
0x03
0x11
0x12
0x21
0x22
0x23
0x24
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x31
0x32
0x33
Name
Bit7
Bit6
Bit5
Bit4
Bit3
0x00
SCK[3]
0xAA
Bit2
Bit1
Bit0
NOP
SPI_SCK_FAIL
LPM0_CMD
LOCK_CMD
PWR_STAT
SYS_STAT
SPI_STAT
1
0
0
SCK_OF
SCK[2]
SCK[1]
SCK[0]
0x55
BUCK_FAIL
WD
VREG_FAIL
POR
OT_BUCK
TestMode
OT_LDO
OT_BOOST
EC_OF
LDO_FAIL
EC2
BOOST_FAIL
EC1
HS_OL
EC0
SMPCLK_FAIL
CLOCK_FAIL
BUCK3-0
CMD_ID FAIL
BUCK2-1
PARITY FAIL
BUCK2-0
COMP_STAT
Serial Nr 1
BUCK3-1
Bit [7:0]
Serial Nr 2
Bit [15:8]
Bit [23:16]
Bit [31:24]
Bit [39:32]
Bit [47:40]
Minor3
Serial Nr 3
Serial Nr 4
Serial Nr 5
Serial Nr 6
DEV_REV
Major3
F_EN
Major2
Major1
Major0
Minor2
HS_EN
VT_EN
F2
Minor1
Minor0
IRQ_THRES
RSV
PWR_CONFIG
DEV_CONFIG
CLOCK_CONFIG
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HL_CLDIS
F3
GPFET_OV_HIGH
RSV
F1
SS_EN
SS_MODE
F4
F0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2 NOP0X00
图8-12. NOP0X00
NOP 0x00
Bit7
0
Bit6
0
Bit5
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
0
After RESET
Read
0
0
0
0
0
0
0
0
0
Write
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.1 SPI_SCK_FAIL 0x03
图8-13. SPI_SCK_FAIL 0x03
SPI_SCK_FAIL 0x03
Bit7
1
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
0
Default after
RESET
Read
1
0
0
SCK_OF
SCK[3]
SCK[2]
SCK[1]
SCK[0]
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图8-13. SPI_SCK_FAIL 0x03 (continued)
SPI_SCK_FAIL 0x03
Write
d.c.
d.c.
d.c. d.c.
d.c.
d.c.
d.c.
d.c.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
Between a falling and a rising edge of CSN, the number of SCK was greater than 16.
0:
SCK_OF
4
1:
Number of SCK cycles was > 16
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
Description
The number of rising edges on SCK between a falling and a rising edge of CSN minus 1. Saturates at 0xF if
16 or more edges are received.
SCK[3:0]
3:0
Comment: This flag is cleared after its content is transmitted to the controller.
8.6.2.2 LPMO_CMD 0x11
图8-14. LPMO_CMD 0x11
LPM0_CMD 0x11
Bit7
0
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
0
After RESET
Read
0
0
0
0
0
0
0
0
Write
0xAA
This command is used to send the device into LPM0 mode.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.3 LOCK_CMD 0x12
图8-15. LPMO_CMD 0x12
LOCK_CMD 0x12
Bit7
0
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
0
After RESET
Read
0
0
0
0
0
0
0
0
Write
0x55
Sending a lock command (0x55) brings the device into LOCK mode. Only a POR brings the device out of this state.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.4 PWR_STAT 0x21
图8-16. PWR_STAT 0x21
PWR_STAT 0x21
Bit7
0
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
0
Default after
POR
Read
Write
BUCK_FAIL VREG_FAIL
d.c. d.c.
OT_BUCK
d.c.
OT_LDO
d.c.
OT_BOOST
d.c.
LDO_FAIL BOOST_FAIL
d.c. d.c.
HS_OL
d.c.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
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Bit Name
Bit No.
Description
BUCK power fail flag
0:
BUCK_FAIL
7
1: Power stages shutdown detected caused by OC BUCK1, UV, OV, loss of GND (BOOST + all bucks)
BUCK_FAIL flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
Description
Internal voltage regulator too low
0:
VREG_FAIL
6
1:
VREG fail
VREG_FAIL flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
Description
BUCK1-3 overtemperature flag
0:
OT_BUCK
5
1:
IC power stages shutdown due to overtemperature
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
Description
LDO overtemperature flag
0:
OT_LDO
4
1:
LDO shutdown due to overtemperature
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
Description
BOOST overtemperature flag
OT_BOOST
3
0:
1: BOOST shutdown due to overtemperature
OT flag is cleared in case the fail condition is not present anymore and the flag is transmitted to the controller.
Bit Name
Bit No.
Description
LDO under or overvoltage flag
0:
LDO_FAIL
2
1:
LDO out of regulation
LDO_FAIL flag is cleared if there is no undervoltage and no overvoltage and the flag is transmitted to the controller.
Bit Name
Bit No.
Description
Booster under or overvoltage flag or loss of GND
BOOST_FAIL
1
0:
1: Booster out of regulation
BOOST_FAIL flag is cleared if there is no undervoltage and no overvoltage and the flag was transmitted to the controller.
Bit Name
Bit No.
Description
High-side switch open load condition
HS_OL
0
0:
1: Open load at high side
Bit indicates current OL condition of high side (no flag)
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8.6.2.5 SYS_STAT 0x22
图8-17. SYS_STAT 0x22
SYS_STAT 0x22
Bit7
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
0
Bit1
0
Bit0
1
Default after
POR
0
Read
Write
WD
d.c.
POR
d.c.
Testmode
d.c.
SMPCLK_FAIL
d.c.
0
EC2
d.c.
EC1
d.c.
EC0
d.c.
d.c.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
Watchdog reset flag
0:
WD
7
1:
Last reset caused by watchdog
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
Description
Power-on reset flag
0:
POR
6
1:
Last reset caused by a POR condition
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
Description
If this bit is set, the device entered test mode
0:
Testmode
5
1:
Device in Testmode
Comment: This flag is cleared after its content is transmitted to the controller and the device left the test mode.
Bit Name
Bit No.
Description
If this bit is set, the clock of the switch mode power supplies is too low.
0: Clock OK
SMPCLK_
FAIL
4
1: Clock fail
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
Description
Actual error flag counter
EC [2:0]
0-2
0:
1:
-
-
*Error Counter is only deleted with a POR
8.6.2.6 SPI_STAT 0x23
图8-18. SPI_STAT 0x23
SPI_STAT 0x23
Bit7
0
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
Bit1
Bit0
Default after RESET
0
0
0
Read
Write
0
0
0
0
0
CLOCK_FAIL
d.c.
CMD_ID FAIL
d.c.
PARITY FAIL
d.c.
d.c.
d.c.
d.c.
d.c.
d.c.
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LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
Between a falling and a rising edge of CSN, the number of SCK does not equal 16
0:
CLOCK_FAIL
2
1:
Wrong SCK
Comment: This flag is cleared after its content is transmitted to the controller.
Bit Name
Bit No.
Description
Last received CMD_ID in a reserved area
CMD_ID FAIL
1
0:
1: Wrong CMD_ID
Comment: This flag is cleared after its content is transmitted to the controller and is not set if the number of SCK cycles is incorrect.
Bit Name
Bit No.
Description
Last received command has a parity bit failure
0:
PARITY_FAIL
0
1:
Parity bit error
Comment: This flag is cleared after its content is transmitted to the controller and is not set if the number of SCK cycles is incorrect.
8.6.2.7 COMP_STAT 0x24
图8-19. COMP_STAT 0x24
COMP_STAT 0x24
Bit7
0
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
1
Bit1
1
Bit0
0
Default after
RESET
Read
Write
0
0
0
0
BUCK3-1
d.c.
BUCK3-0
d.c.
BUCK2-1
d.c.
BUCK2-0
d.c.
d.c.
d.c.
d.c.
d.c.
Register to read back the actual BUCK2 and BUCK3 compensation settings on COMP2 and COMP3. 0x1 ≥0 V 0 x 2 ≥VREG 0 x 3 ≥
open
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.8 DEV_REV 0x2F
图8-20. DEV_REV 0x2F
DEV_REV 0x2F
Bit7
Major3
Major3
d.c.
Bit6
Major2
Major2
d.c.
Bit5
Major1
Major1
d.c.
Bit4
Major0
Major0
d.c.
Bit3
Minor3
Minor3
d.c.
Bit2
Minor2
Minor2
d.c.
Bit1
Minor1
Minor1
d.c.
Bit0
Minor0
Minor0
d.c.
After RESET
Read
Write
Hard coded device revision can be read from this register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
8.6.2.9 PWR_CONFIG 0x31
图8-21. PWR_CONFIG 0x31
PWR_CONFIG 0x31
Bit7
0
Bit6
1
Bit5
1
Bit4
0
Bit3
1
Bit2
Bit1
Bit0
0
Default after RESET
Read
0
0
0
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HS_EN
GPFET_OV_HIGH
IRQ_THRES
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图8-21. PWR_CONFIG 0x31 (continued)
PWR_CONFIG 0x31
Write
0
BUCK2_EN
BUCK3_EN
LDO_EN
BOOST_EN
HS_EN
GPFET_OV_HIGH
IRQ_THRES
This register contains all power rail enable bits.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
BUCK2 enable flag
0:
BUCK2_EN
6
1: Enable BUCK2
After reset, BUCK2 is enabled
Bit Name
Bit No.
Description
Description
Description
Description
Description
BUCK3 enable flag
0:
BUCK3_EN
5
1:
After reset, BUCK3 is enabled
Enable BUCK3
Bit Name
Bit No.
LDO enable flag
LDO_EN
4
0:
1: LDO enabled
After reset, LDO is disabled
Bit Name
Bit No.
BOOST enable
0:
BOOST_EN
3
1: BOOST enabled
After reset, BOOST is enabled
Bit Name
Bit No.
LED and high-side switch enable
HS_EN
2
0:
1:
High side disabled
High side enabled
After reset, high side is disabled
Bit Name
Bit No.
Protection FET overvoltage shutdown
GPFET_OV_HIGH
1
0: Protection FET switches off at VIN > VOVTH-L
1: Protection FET switches off at VIN > VOVTH-H
After reset, the lower VIN protection threshold is enabled
Bit Name
Bit No.
Description
VSSENSE IRQ low voltage interrupt threshold select
IRQ_THRES
0
0:
1:
Low threshold selected (VSSENSETH_L
)
High threshold selected (VSSENSETH_H
)
After reset, the lower VBAT monitoring threshold is enabled
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8.6.2.10 DEV_CONFIG 0x32
图8-22. DEV_CONFIG 0x32
DEV_CONFIG 0x32
Bit7
0
Bit6
0
Bit5
0
Bit4
0
Bit3
0
Bit2
1
Bit1
1
Bit0
0
Default after RESET
Read
Write
0
0
0
0
0
VT_EN
VT_EN
RSV
1
RSV
0
d.c.
d.c.
d.c.
d.c.
d.c.
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
LED and high-side switch current limit counter disable bit
0: LED and high-side switch current limit counter enabled
1: LED and high-side switch current limit counter disabled
HS_CLDIS
3
Bit Name
Bit No.
Description
VT enable bit
VT_EN
2
0: VT monitor disabled
1: VT monitor enabled
The VT monitor cannot be turned on after it was turned off. Turn on only happens during power up in the VTCHECK state.
Bit Name
Bit No.
Description
Voltage reference enable bit
RSV
1
0:
1:
not recommended setting
default setting
Bit Name
Bit No.
Description
Reserved - keep this bit at 1
0: default setting
RSV
0
1: not recommended setting
8.6.2.11 CLOCK_CONFIG 0x33
图8-23. CLOCK_CONFIG 0x33
CLOCK_CONFIG 0x33
Bit7
Bit6
0
Bit5
0
Bit4
1
Bit3
0
Bit2
0
Bit1
0
Bit0
0
Default after
RESET
0
Read
Write
F_EN
F_EN
SS_EN
SS_EN
SS_MODE
SS_MODE
F4
F4
F3
F3
F2
F2
F1
F1
F0
F0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Name
Bit No.
Description
Frequency tuning enable register
0:
1:
F_EN
7
Off –Setting of Bit4…Bit0 are not effective, setting of Bit6 and Bit5 become effective
On –Setting of Bit4…Bit0 become effective, setting of Bit6 and Bit5 are not effective
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Bit Name
Bit No.
Description
Spread spectrum mode enable
0: Spread spectrum option for all switching regulators disabled
1: Spread spectrum option for all switching regulators enabled (only when F_EN = 0)
When enabled, the switching frequency of BUCK1, BUCK2, BUCK3 and BOOST is modulated between 0.8 × fosc and fosc
SS_EN
6
Bit Name
Bit No.
Description
Spread spectrum mode select (effective only when F_EN = 0)
SS_MODE
5
0:
1:
Pseudo random
Triangular
Bit Name
F4, F3, F2, F1, F0
Bit No.
Description
Frequency tuning register (effective only when F_EN = 1)
4-0
0x10 is default value, trim range is 25% for 0x00 setting to –20% for 0x1F setting. Frequency tuning influences the switching frequency of
BUCK1, BUCK2, BUCK3 and BOOST as well as the watchdog timing.
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The TPS65310A-Q1 device is a multi-rail power supply including one buck controller, two buck converters, one
boost converter and one linear regulator (LDO). The buck controller is typically used to convert a higher car
battery voltage to a lower DC voltage which is then used as pre-regulated input supply for the buck converters,
boost converter, and the linear regulator. Use the following design procedure and application example to select
component values for the TPS65310A-Q1 device.
9.2 Typical Applications
9.2.1 Buck Controller 1
D1
VBAT
4 V to 40 V (typ. 12 V)
VINPROT
10
BOOT1
Q2
Q3
11
12
13
14
GU
PH1
GL
PGND1
4.7 nF
TPS65310A-Q1
8.25 k
R3
18
COMP1
C1
C2 47 pF
15
16
S1
S2
VBUCK1
19
17
VSENSE1
VMON1
VBUCK1
图9-1. Buck Controller Schematic
9.2.1.1 Design Requirements
For this design example, use the parameters listed in 表9-1.
表9-1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V
3.8 V
2.5 A
Output voltage (VBUCK1)
Maximum output current (Imax_peak_coil)
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表9-1. Design Parameters (continued)
DESIGN PARAMETER
EXAMPLE VALUE
1.25A
Load Step ΔIOUT
Output current ripple IL_ripple
Output voltage ripple
500 mA
3 mV
0.228 (or 6%)
490 kHz
Allowed voltage step on output ΔVOUT
Switching frequency (fSWBUCK1)
Bandwidth (FBW)
≈60 kHz
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Adjusting the Output Voltage for the BUCK1 Controller
A resistor divider from the output node to the VSENSE1 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. Start with 16 kΩfor the R1 resistor and use 方程式1 to calculate R2 (see 图
9-1).
R1´ (VBUCK1 - 0.8 V)
R2 =
0.8 V
(1)
Therefore, for the value of VBUCK1 to equal to 3.8V, the value of R2 must be 60.4 kOhms.
For voltage monitoring of the BUCK1 output voltage, placing an additional resistive divider with the exact same
values from the output node to the VMON1 pin is recommended for safety reasons (see 图 9-1). If no safety
standard must be fulfilled in the application, the VMON1 pin can be directly connected to VSENSE1 pin without
the need for this additional resistive divider.
9.2.1.2.2 Output Inductor, Sense Resistor and Capacitor Selection for the BUCK1 Controller
An external resistor senses the current through the inductor. The current sense resistor pins (S1 and S2) are fed
into an internal differential amplifier which supports the range of VBUCK1 voltages. The sense resistor RS must
be chosen so that the maximum forward peak current in the inductor generates a voltage of 75 mV across the
sense pins. This specified typical value is for low duty cycles only. At typical duty-cycle conditions around 28%
(assuming 3.8-V output and 12-V input), 60 mV is a more reasonable value, considering tolerances and
mismatches. The typical characteristics (see Reduction of Current Limit vs Duty Cycle) provide a guide for using
the correct current-limit sense voltage.
60 mV
=
RS
Imax_peak
(2)
Optimal slope compensation which is adaptive to changes in input voltage and duty cycle allows stable operation
at all conditions. In order to specify optimal performance of this circuit, the following condition must be satisfied in
the choice of inductor and sense resistor:
L = 410´Rs
(3)
where
• L = inductor in µH
• Rs = sense resistor in Ω
The current sense pins S1 and S2 are high impedance pins with low leakage across the entire VBUCK1 range.
This allows DCR current sensing (see Detailed Block Diagram Of Buck 1 Controller) using the DC resistance of
the inductor for better efficiency.
For selecting the output capacitance and its ESR resistance, the following set of equations can be used:
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2 ´ DIOUT
COUT
COUT
RESR
>
>
<
ƒSW ´ DVOUT
IL
_
1
ripple
´
8´ ƒSW Vo _ripple
Vo _ripple
IL
_
ripple
(4)
where
• ƒsw is the 490-kHz switching frequency
• ΔIOUT is the worst-case load step from the application
• ΔVOUT is the allowed voltage step on the output
• Vo_ripple is the allowed output voltage ripple
• IL_ripple is the ripple current in the coil
9.2.1.2.3 Compensation of the Buck Controller
The main buck controller requires external type 2 compensation on pin COMP1 for normal mode operation. The
components can be calculated as follows.
1. Select a value for the bandwidth, FBW, to be between fSWBUCK1 / 6 (faster response) and fSWBUCK1 / 10 (more
conservative)
2. Use 方程式5 to select a value for R3 (see 图8-2).
2p ´ F ´ VOUT1 ´ COUT1
BW
R3 =
gm ´ KCFB ´ V
refBUCK
(5)
where
• COUT1 is the load capacitance of BUCK1
• gm is the error amplifier transconductance
• KCFB = 0.125 / Rs
• VrefBUCK is the internal reference voltage
3. Use 方程式6 to select a value for C1 (in series with R3, see 图8-2) to set the zero frequency close to FBW
/
10.
10
C1=
2p ´ R3´ F
BW
(6)
(7)
4. Use 方程式7 to select a value for C2 (parallel with R3, C1, see 图8-2) to set the second pole below
fSWBUCK1 / 2
1
C2 =
2p ´ R3´ F ´ 3
BW
For example:
fSWBUCK1 = 490 kHz, VrefBUCK = 0.8 V, FBW = 60 kHz
VOUT1 = 3.8 V, Cout 1 = 50 µF, Rs = 22 mΩ
Assuming capacitor de-rating, we select the below values:
C2 = 47pF
C1 = 0.0047uF
R3 = 8.25kOhms
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Resulting in FBW: 57 kHz
Resulting in zero frequency: 4.2 kHz
Resulting in second pole frequency: 193 kHz
Stability and load step response must be verified in measurements to fine tune the values of the compensation
components.
9.2.1.2.4 Bootstrap Capacitor for the BUCK1 Controller
The BUCK1 controller requires a bootstrap capacitor. This bootstrap capacitor must be 0.1 μF. The bootstrap
capacitor is located between the PH1 pin and the BOOT1 pin (see Buck Controller Schematic). The bootstrap
capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric for temperature stability.
9.2.1.3 BUCK 1 Application Curve
100
90
80
70
60
50
VBAT = 5 V
VBAT = 10 V
VBAT = 18 V
VBAT = 26 V
VBAT = 34 V
VBAT = 37 V
VBAT = 8.1 V
VBAT = 14 V
VBAT = 22 V
VBAT = 30 V
VBAT = 36 V
40
30
20
10
0
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
Iload (A)
C001
图9-2. Efficiency Results Of Buck1
9.2.2 Synchronous Buck Converters BUCK2 and BUCK3
VBUCK1
5 V
30
VSUP2
29
31
BOOT2
PH2
3.3 µH
VBuck2
3.3 V, 2 A max
34
32
35
33
COMP2
PGND2
VSENSE2
VMON2
TPS65310A-Q1
VBUCK1
5 V
41
VSUP3
42
40
BOOT3
PH3
3.3 µH
VBuck3
1.2 V, 2 A max
37
39
36
38
COMP3
PGND3
VSENSE3
VMON3
图9-3. Synchronous Buck Converter Schematic
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9.2.2.1 Design Requirements
For this design example, use the parameters listed in 表9-2.
表9-2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
3.8 V
3.3 V
1.2 V
Output voltage (VBUCK2/3
)
Maximum output current (Imax_peak
)
2 A
300 mA
0.98 MHz
Output current ripple ΔIL_PP
Switching frequency (fSWBUCK2/3
)
9.2.2.2 Detailed Design Procedure
9.2.2.2.1 Adjusting the Output Voltage for the BUCK2 and BUCK3 Converter
A resistor divider from the output node to the VSENSE2 to ground respectively between the VSENSE3 to ground
pin sets the output voltage (see 图 9-3). TI recommends using 1% tolerance or better divider resistors. Start by
selecting 1.6 kΩ for the value of the Rx resistor between the VSENSE2 to ground respectively between the
VSENSE3 to ground pin VSENSE3 pin and use 方程式 8 to calculate the value for the Ry resistor between
BUCK2 and BUCK3 output and the VSENSE2 to ground respectively between the VSENSE3 to ground pin.
Rx ´ (VBUCK2/3 - 0.8 V)
Ry =
0.8 V
(8)
Therefore, for VBUCK2 to equal to 3.3 V, the value of Ry must be 4.99k. For VBUCK3 to equal to 1.2 V, the value of
Ry must be 806 Ohms.
For voltage monitoring of the BUCK2 and BUCK3 output voltage, placing an additional resistive divider with
exact same values from the output node to the VMON2 and VMON3 pins is recommended for safety reasons
(see 图 9-3). If no safety standard must be fulfilled in the application, the VMON2 and VMON3 pins can be
directly connected to VSENSE2 and VSENSE3 pins without the need for this additional resistive divider.
9.2.2.2.2 Output Inductor Selection for the BUCK2 and BUCK3 Converter
The inductor value L depends on the allowed ripple current ΔIL_PP in the coil at chosen input voltage VIN and
output voltage VOUT, and given switching frequency fsw:
V
OUT ´(VIN - VOUT )
L =
DIL _PP ´ V ´ fsw
IN
(9)
For example:
VIN = 5 V
VOUT = 3.3 V
ΔIL_PP = 0.35 mA
fsw = 0.98 MHz
→L ≈3.3 μH
9.2.2.2.3 Compensation of the BUCK2 and BUCK3 Converters
The regulators operate in forced continuous mode, and have internal frequency compensation. The frequency
response can be adjusted to the selected LC filter by setting the COMP2 and COMP3 pin low, high, or floating.
After selecting the output inductor value as previously described, the output capacitor must be chosen so that
the L × COUT × VBUCK2/3 product is equal to or less than one of the three values, as listed in 表9-3.
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表9-3. Compensation Settings
COMP 2/3
= 0 V
L × COUT × VBUCK2/3
125 µF × µH × V
250 µF × µH × V
500 µF × µH × V
EXAMPLE COMPONENTS
40 µF × 2.7 µH × 1.2 V
30 µF × 3.3 µH × 2.5 V
200 µF × 2.2 µH × 1.2 V
= OPEN
= VREG
Larger output capacitors can be used if a feed-forward capacitor is placed across the upper resistance, Ry, of the
feedback divider. This works effectively for output voltages > 2 V. With an RC product greater than 10 µs, the
effective VBUCK2/3 at higher frequencies can be assumed as 0.8 V, thus allowing an output capacitor increase by
a factor equal to the ratio of the output voltage to 0.8 V.
9.2.2.2.4 Bootstrap Capacitor for the BUCK2/3 Converters
The BUCK2 and BUCK3 converters require a bootstrap capacitor. This bootstrap capacitor must be 0.1 μF. The
bootstrap capacitor is located between the PH2 pin and the BOOT2 pin and between the PH3 pin and the
BOOT3 pin (see Synchronous Buck Converter Schematic). The bootstrap capacitor must be a high-quality
ceramic type with X7R or X5R grade dielectric for temperature stability.
9.2.2.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
100
90
80
70
60
50
40
30
20
10
0
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
EFF VSUP3 = 3.8 V
EFF VSUP3 = 3.3 V
EFF VSUP3 = 5 V
EFF VSUP2 = 3.8 V
EFF VSUP2 = 5 V
LOSS VSUP2 = 3.8 V
LOSS VSUP2 = 5 V
LOSS VSUP3 = 3.8 V
LOSS VSUP3 = 3.3 V
LOSS VSUP3 = 5 V
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
Load Current (A)
Load Current (A)
图9-5. Efficiency Buck3 = 1.2 V At 25°C L = 3.3 uH,
C = 30 uF, COMP2 Pin To Ground EXTSUP Pin
Open, Measured Buck3 Output Power With
Respect To VSUP3 Input Power
图9-4. Efficiency Buck2 = 3.3 V At 25°C L = 3.3 uH,
C = 20 uF, COMP2 Pin Open EXTSUP Pin Open,
Measured Buck2 Output Power With Respect To
VSUP2 Input Power
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100
100
95
90
85
80
75
95
VSUP3 = 3.8 V, 1-A LOAD
90
VSUP2 = 3.8 V, 0.5-A LOAD
85
80
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
图9-6. Buck2 = 3.3-V Efficiency At 0.5 A vs
Temperature L = 3.3 uH, C = 20 uF, Comp2 Pin
Open EXTSUP Pin Open, Measured Buck2 Output
Power With Respect To VSUP2 Input Power
图9-7. Buck3 = 1.2-V Efficiency At 1 A vs
Temperature L = 3.3 uH, C = 30 uF, COMP2 Pin To
Ground EXTSUP Pin Open, Measured Buck3
Output Power With Respect To VSUP3 Input Power
100
100
VSUP3 = 3.8 V
95
95
90
90
85
80
VSUP2 = 3.8 V
85
80
-50
0
50
100
150
-50
0
50
100
150
Temperature (°C)
Temperature (°C)
图9-8. Buck2 = 3.3-V Peak Efficiency vs
图9-9. Buck3 = 1.2-V Peak Efficiency vs
Temperature L = 3.3 uH, C = 20 uF, COMP2 Pin
Open EXTSUP Pin Open, Measured Buck2 Output
Power With Respect To VSUP2 Input Power
Temperature L = 3.3 uH, C = 30 uF, COMP2 Pin To
Ground EXTSUP Pin Open, Measured Buck3
Output Power With Respect To VSUP3 Input Power
9.2.3 BOOST Converter
VBUCK1
2.7 nF
3.8 V
20
COMP5
12 k
23
22
PH5
PGND5 TPS65310A-Q1
D2
24
21
VBOOST
VBOOST
8.4 kW
5 V,
300 mA
VSENSE5
图9-10. BOOST Converter Schematic
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9.2.3.1 Design Requirements
For this design example, use the parameters listed in 表9-4.
表9-4. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
3.8 V
Input voltage
Output voltage (VBOOST
)
5 V
Peak coil current (Ipeak_coil
)
1 A
Maximum output current IOUT
≈400 mA
200 mA
0.98 MHz
Output current ripple ΔIL_PP
Switching frequency (fSWBOOST
)
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Adjusting the Output Voltage for the Boost Converter
A resistor divider from the output node to the VSENSE5 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. Start with a value of 1.6 kΩ for the Rx resistor and use 方程式 10 to
calculate Ry (see 图9-10).
Rx ´ (VBOOST - 0.8 V)
Ry =
0.8 V
(10)
Therefore, for the value of VBOOST to equal to 5 V, the value of Ry must be 8.4 kΩ.
9.2.3.2.2 Output Inductor and Capacitor Selection for the BOOST Converter
The inductor value L depends on the allowed ripple current ΔIL_PP in the coil at chosen input voltage VIN and
output voltage VOUT, and given switching frequency fsw:
V
IN ´(VOUT - V )
IN
L =
DIL _PP ´ VOUT ´ fsw
(11)
For example:
VIN = 3.3 V (from BUCK1)
VOUT = 5 V
ΔIL_PP = 200 mA (20% of 1-A peak current)
ƒsw = 0.98 MHz
→L ≈4.7 μH
The capacitor value COUT must be selected such that the L-C double-pole frequency FLC is in the range of
10 kHz–15 kHz. The FLC is given by 方程式12:
V
IN
F
=
LC
2´ p´ VOUT ´ L ´ COUT
(12)
The right half-plane zero FRHPZ, as given in 方程式13, must be > 200 kHz:
V2
IN
FRHPZ
=
> 200 kHz
2 ´ p L ´ IOUT ´ VOUT
(13)
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where
• IOUT represents the load current
If the condition FRHPZ > 200 kHz is not satisfied, L and therefore COUT have to be recalculated.
9.2.3.2.3 Compensation of the BOOST Converter
The BOOST converter requires an external R-C network for compensation (see 图 9-10, COMP5). The
components can be calculated using 方程式14 and 方程式15:
æ
ç
è
ö2
÷
F
BW
R = 120´ V
´
IN
F
LC ø
(14)
(15)
1
C =
2´ p´R´F
LC
where
• FBW represents the bandwidth of the regulation loop, and must be set to 30 kHz
• FLC represents the L-C double-pole frequency, as mentioned previously
For example:
VIN = 3.8 V
VOUT = 5 V
L = 4.7 μH
C = 54 uF
→FLC = 7.6 kHz
FBW = 30 kHz
→R ≈8 k
→C ≈2.7 nF
Stability and load step response must be verified in measurements to fine tune the values of the compensation
components. Like in this case, while fine tuning, it was observed on the EVM that using 12k as the
compensation resistance gave better load transient results and stability response than using 8k. The equations
serve as a good starting point for calculating compensation values.
9.2.3.2.4 Output Diode for the BOOST Converter
The BOOST converter requires an external output diode between the PH5 pin and VBOOST pin (see BOOST
Converter Schematic, component D2). The selected diode must have a reverse voltage rating equal to or greater
than the VBOOST output voltage. The peak current rating of the diode must be greater than the maximum inductor
current. The diode must also have a low forward voltage in order to reduce the power losses. Therefore,
Schottky diodes are typically a good choice for the catch diode.
Also, select a diode with an appropriate power rating, because the diode conducts the output current during the
off-time of the internal power switch.
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9.2.3.3 BOOST Converter Application Curves
100
90
250
200
150
100
50
100
95
80
70
60
Efficiency
Power Loss
90
50
40
30
20
10
0
85
80
0
-50
0
50
100
150
0.001
0.01
0.1
1
Temperature (°C)
Load Current (A)
图9-12. Boost = 5-V Peak Efficiency vs
图9-11. Efficiency BOOST = 5 V At 25°C EXTSUP
Pin Open, BOOST Supply Input = 3.8 V, Measured
BOOST Output Power With Respect To Supply
Input Power
Temperature EXTSUP Pin Open, BOOST Supply
Input = 3.8 V, Measured Boost Output Power With
Respect To Supply Input Power
9.2.4 Linear Regulator
TPS65310A-Q1
1 µF
VLDO_OUT
1.74 kW
2.5 V, max 350 mA
图9-13. Linear Regulator Schematic
9.2.4.1 Design Requirements
For this design example, use the parameters listed in 表9-5.
表9-5. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
3.3 V
Input voltage
Output voltage (VLDO_OUT
)
2.5 V
Maximum output current (IOUT
)
350 mA
9.2.4.2 Detailed Design Procedure
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9.2.4.2.1 Adjusting the Output Voltage for the Linear Regulator
A resistor divider from the output node to the VSENSE4 pin sets the output voltage. TI recommends using 1%
tolerance or better divider resistors. In order to get the minimum required load current of 1 mA for the linear
regulator, start with a value of 820 Ωfor the Rx resistor and use 方程式16 to calculate Ry (see 图9-13).
Rx ´ (VLDO _ OUT - 0.8 V)
Ry =
0.8 V
(16)
Therefore, for the value of VLDO_OUT to equal to 2.5 V, the value of Ry must be 1.74 kΩ.
9.2.4.2.2 Output Capacitance for the Linear Regulator
The linear regulator requires and external output capacitance with a value between 6 µF and 50 µF.
9.2.4.3 Linear Regulator Application Curve
10
9
Noise [LDO ON]
8
Noise [LDO OFF]
(Noisefloor)
7
6
5
4
3
2
1
0
10
100
1000
10000
Frequency (Hz)
图9-14. LDO Noise Density
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10 Power Supply Recommendations
The device is designed to operate from an input voltage supply range between 4 V and 40 V (see 图 10-1 for
reference). This input supply must be well regulated. In case the supply voltage in the application is likely to
exceed 40 V, the external PMOS protection device as explained in 节 8.4.19 must be applied between VIN and
VINPROT pins. Furthermore, if the supply voltage in the application is likely to reach negative voltage (for
example, reverse battery), a forward diode must be placed between the VSSENSE and VIN pins. A ceramic
bypass capacitor with a value of 100 μF (typical) is recommended to be placed close to the VINPROT pin. For
the VIN pin, a small ceramic capacitor of typical 1 µF is recommended. Also place 1-µF (typical) bypass
capacitors to the DVDD and VREF pins, and 100-nF (typical) bypass capacitors to VIO pin. Furthermore, the
VREG pin requires a bypass capacitor of 2.2 µF (typical).
The BUCK1 output voltage is the recommended input supply for the BUCK2, BUCK3, and BOOST regulators.
Place local, 10-µF (typical) bypass capacitors at the VSUP2 and VSUP3 pins and at the supply input of the
BOOST in front of the BOOST-inductor. Also place a local, 1-µF (typical) bypass capacitor at the VSUP4 pin.
The EXTSUP pin can be used to improve efficiency. For the EXTSUP pin to improve efficiency, a voltage of more
than 4.8 V is required in order to have VREG regulator supplied from EXTSUP pin. If the EXSUP pin is not used,
the VINPROT pin supplies the VREG regulator. The EXTSUP pin requires a 100-nF (typical) bypass capacitor.
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D1
VBAT
4 V to 40 V (typ. 12 V)
Q1
VINPROT
28
48
IRQ
VIO
VBUCK1
10
BOOT1
Q2
Q3
11
12
13
14
GU
PH1
27
26
43
RESN
PRESN
WD
GL
10 kW
WAKE
PGND1
4.7 nF
C1
44
46
47
45
8.25 k
R3
CSN
SCK
18
COMP1
SDO
SDI
C2 47 pF
15
16
S1
S2
53
VBUCK1
VREF
3.8 V, 2.5 A
19
17
VSENSE1
VMON1
25
54
VT_REF
VT
VBUCK1
30
TPS65310A-Q1
VSUP2
VINPROT
29
31
BOOT2
PH2
3.3 µH
VBuck2
6
5
HSSENSE
HSCTRL
HSPWM
3.3 V, 2 A
34
32
35
33
COMP2
PGND2
49
VSENSE2
VMON2
VBUCK1
2.7 nF
VBUCK1
20
COMP5
41
VSUP3
12 k
23
22
42
40
PH5
BOOT3
PH3
3.3 µH
PGND5
D2
1.2 V, 2 A
24
21
37
39
36
38
VBOOST
COMP3
PGND3
VBOOST
5 V,
300 mA
8.4 kW
VSENSE5
VSENSE3
VMON3
1 µF
VLDO_OUT
2.5 V, maximum 350 mA
1.74 kW
图10-1. Typical Application Schematic
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11 Layout
11.1 Layout Guidelines
11.1.1 Buck Controller
• Connect a local decoupling capacitor between the drain of Q3 and the source of Q2. The length of this trace
loop should be short.
• The Kelvin-current sensing for the shunt resistor should have traces with minimum spacing, routed in parallel
with each other. Place any filtering capacitor for noise near the S1-S2 pins.
• The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as
possible to the sensing resistor divider, and should be connected to same traces.
• Connect the boot-strap capacitance between the PH1 and BOOT1 pins, and keep the length of these trace
loops as short as possible.
• Connect the compensation network between the COMP1 pin and GND pin (IC signal ground).
• Connect a local decoupling capacitor between the VREG and PGDN1 pin, and between the EXTSUP and
PGND1 pin. The length of this trace loop should be short.
11.1.2 Buck Converter
• Connect a local decoupling capacitor between VSUP2 and PGND2 respectively VSUP3 and PGND3 pins.
The length of this trace loop should be short.
• The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces. The resistor divider for monitoring the output voltage is to be placed as close as
possible to the sensing resistor divider, and should be connected to same traces.
• Connect the boot-strap capacitance between the PH2 and BOOT2 respectively PH3 and BOOT3 pins, and
keep the length of this trace loop as short as possible.
• If COMP2 and/or COMP3 are chosen to be connected to ground, use the signal ground trace connected to
GND pin for this.
11.1.3 Boost Converter
• The path formed from the input capacitor to the inductor and the PH5 pin should have short trace length. The
same applies for the trace from the inductor to Schottky diode D2 to the output capacitor and the VBOOST
pin. Connect the negative pin of the input capacitor and the PGND5 pin together with short trace lengths.
• The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces.
• Connect the compensation network between the COMP5 pin and GND pin (IC signal ground).
11.1.4 Linear Regulator
• Connect a local decoupling capacitor between VSUP4 and GND (IC signal ground) pins. The length of this
trace loop should be short.
• The resistor divider for sensing the output voltage connects between the positive pin of the output capacitor
and the GND pin (IC signal ground). Do not locate these components and their traces near any switching
nodes or high-current traces.
11.1.5 Other Considerations
• Short PGNDx and GND to the thermal pad.
• Use a star ground configuration if connecting to a non-ground plane system. Use tie-ins for the
compensation-network ground, voltage-sense feedback ground, and local biasing bypass capacitor ground
networks to this star ground.
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11.2 Layout Example
Analog Signal Ground trace
Sense resistors LDO
VSSENSE
BOOT3
VSUP3
PH3
D1
VIN
BUCK3 output voltage
Q1
GPFET
Sense and
Monitoring
resistors
BUCK3
VINPROT
HSCTRL
HSSENSE
WAKE
PGND3
VMON3
COMP3
VSENSE3
VSENSE2
COMP2
VMON2
PGND2
PH2
Compensation connection BUCK2
(either to Analog Signal Ground, to VREG or leave open)
Exposed Thermal
Pad area
EXTSUP
VREG
Compensation connection BUCK2
(either to Analog Signal Ground, to VREG or leave open)
BOOT1
Sense and
Monitoring
resistors
BUCK2
Q2
GU
PH1
Q3
BUCK2 output voltage
GL
VSUP2
BOOT2
PGND1
Power
ground
plane
VT_REF
BOOST output
voltage
Sense and
Monitoring
resistors
BUCK1
Sense resistors
BOOST
Analog Signal Ground trace
图11-1. TPS65310-Q1 Layout Example
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备注
(1) There’s very high dI/dt in path where the switching current flows. Any inductance in this path
results in ringing on switched node. It’s very important to minimize these loop areas.
图11-2. EVM Top Layer
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图11-3. EVM Bottom Layer
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• TPS65310A-Q1 Efficiency SLVA610
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS65310AQRVJRQ1
ACTIVE
VQFN
RVJ
56
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TPS65310A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
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15-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65310AQRVJRQ1
VQFN
RVJ
56
2000
330.0
16.4
8.3
8.3
2.25
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
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15-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
VQFN RVJ 56
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TPS65310AQRVJRQ1
2000
Pack Materials-Page 2
PACKAGE OUTLINE
VQFN - 1 mm max height
RVJ0056A
PLASTIC QUAD FLATPACK- NO LEAD
8.1
7.9
A
B
0.1 MIN
8.1
7.9
(0.13)
SECTION A-A
PIN 1 INDEX AREA
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
5.2±0.1
(0.2) TYP
15
28
52X 0.5
(0.16)
14
29
SYMM
A
A
57
4X
6.5
5.2±0.1
1
42
0.30
56X
0.20
PIN 1 ID
(OPTIONAL)
43
56
0.1
C A B
C
0.55
0.35
56X
SYMM
0.05
4225251/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
VQFN - 1 mm max height
RVJ0056A
PLASTIC QUAD FLATPACK- NO LEAD
(7.75)
(5.2)
SYMM
56X (0.65)
56
43
1
42
56X (0.25)
52X (0.5)
SYMM
(7.75)
57
(5.2)
8X (1.27)
6X (1.08)
(Ø0.2) VIA
TYP
14
29
(R0.05)
TYP
15
28
8X (1.27)
6X (1.08)
LAND PATTERN EXAMPLE
SCALE: 10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225251/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
VQFN - 1 mm max height
RVJ0056A
PLASTIC QUAD FLATPACK- NO LEAD
(7.75)
SYMM
56X (0.65)
56
43
1
42
57
16X
SQ (1.07)
56X (0.25)
52X (0.5)
SYMM
(7.75)
8X (0.635)
6X (1.27)
METAL TYP
14
29
(R0.05)
TYP
15
28
8X (0.635)
6X (1.27)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 10X
4225251/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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