TPS65560RGTR [TI]

INTEGRATED PHOTO FLASH CHARGER AND IGBT DRIVER; 集成闪光灯充电器和IGBT驱动器
TPS65560RGTR
型号: TPS65560RGTR
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

INTEGRATED PHOTO FLASH CHARGER AND IGBT DRIVER
集成闪光灯充电器和IGBT驱动器

驱动器 稳压器 开关式稳压器或控制器 电源电路 开关式控制器 闪光灯 双极性晶体管 PC
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RGT  
TPS65560  
www.ti.com  
SLVS608JANUARY 2006  
INTEGRATED PHOTO FLASH CHARGER AND IGBT DRIVER  
FEATURES  
APPLICATIONS  
Digital Still Cameras  
Optical Film Cameras  
Mobile Phones With Camera  
PDAs With Camera  
Highly Integrated Solution to Reduce  
Components  
Integrated Voltage Reference  
Integrated 50-V Power Switch,  
Integrated IGBT Driver  
DESCRIPTION  
High Efficiency  
This device offers a complete solution for charging a  
photo flash capacitor from battery input, and  
subsequently discharging the capacitor to a xenon  
flash tube. The device has an integrated voltage  
reference, power switch, IGBT driver, and control  
logic blocks for charging applications and driving  
IGBT applications. Compared with discrete solutions,  
this device reduces the component count, shrinks the  
solution size, and eases designs for xenon tube  
Programmable Peak Current, 0.9 A ~ 1.8 A  
Input Battery Voltage of 1.6 V to 12 V  
Optimized Control Loop for Fast Charge Time  
Output Voltage Feedback From Primary Side  
16-Pin QFN Package  
Protection  
– MAX On Time  
applications. Additional advantages are  
charging time and high efficiency from an optimized  
PWM control algorithm.  
a
fast  
– MAX Off Time  
– Overcurrent Shutdown to Monitor VDS at the  
SW pin (OVDS  
)
Other provisions of the device includes sensing the  
output voltage from the primary side, programmable  
peak current, thermal shutdown, an output pin for  
charge completion, and input pins for charge enable  
and flash enable.  
– Thermal Disable  
VA  
VO  
D1  
T1  
VCC  
VCC  
CO  
IO  
C2  
C1  
SW  
VBAT  
VI/F  
VI/F  
CHG  
D
Q
F1  
Controller  
R1  
0 Vds  
XFULL  
or  
D
Q
F2  
U1  
ENA  
VCC  
V_FULL  
ENA  
D/A Conv  
or  
U0  
Max ON  
U2  
LOGIC  
I_PEAK  
TSD  
I_PEAK  
Ref.  
Analog  
Circuit  
Vref  
PGND  
SW  
U3  
or  
VCC  
G_IGBT  
F_ON  
ENA  
SW1  
IGBT  
U4  
NC  
Figure 1. Typical Application Circuit  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2006, Texas Instruments Incorporated  
 
TPS65560  
www.ti.com  
SLVS608JANUARY 2006  
These devices have limited built-in ESD protection. The leads should be shorted together or the device  
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION  
TA  
PACKAGE MARKING  
PACKAGE(1)  
PART NUMBER  
-35°C to 85°C  
BPR  
16-pin QFN  
TPS65560RGT  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
Web site at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range (unless otherwise noted)  
(1)  
UNIT  
VCC  
-0.6 V to 6 V  
-0.6 V to 13 V  
-0.6 V to 50 V  
3 A  
VSS  
Supply voltage  
VBAT  
V(SW)  
I(SW)  
VI  
Switch terminal voltage  
Switch current between SW and PGND, ISW  
Input voltage of CHG, I_PEAK, F_ON  
Storage temperature  
-0.3 V to VCC  
-40°C to 150°C  
125°C  
Tstg  
TJ  
Maximum junction temperature  
ESD rating  
HBM (Human Body Model) JEDEC JES22-A114  
1 kV  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING CONDITIONS  
MIN  
2.7  
NOM  
MAX  
4
UNIT  
V
Supply voltage, VCC  
VSS  
Supply voltage, VBAT  
1.6  
12  
45  
2
V
V(SW)  
I(SW)  
Switch terminal voltage,  
-0.3  
V
Switch current between SW and PGND  
Operating free-air temperature range  
High-level digital input voltage at CHG and F_ON  
Low-level digital input voltage at CHG and F_ON  
A
-35  
2
85  
°C  
V
VIH  
VIL  
0.5  
V
DISSIPATION RATINGS  
POWER RATING  
POWER RATING  
POWER RATING  
(1)  
PACKAGE  
RθJA  
TA < 25°C  
TA = 70°C  
TA = 85°C  
QFN  
47.4 °C/W  
2.11 W  
1.16 W  
844 mW  
(1) The thermal resistance, RθJA, is based on a soldered PowerPAD™ on a 2S2P JEDEC board using thermal vias.  
2
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TPS65560  
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SLVS608JANUARY 2006  
ELECTRICAL CHARACTERISTICS  
TA = 25°C, VBAT = 4.2 V, VCC = 3 V, V(SW) = 4.2 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
I(XFULL) = -1 mA  
MIN  
TYP  
MAX  
UNIT  
kΩ  
V
R(ONL)  
V(PKH)  
ON resistance of XFULL  
1.5  
3
(1)  
(1)  
Upper threshold voltage of I_PEAK VCC = 3 V  
Lower threshold voltage of I_PEAK VCC = 3 V  
2.4  
V(PKL)  
0.6  
50  
V
CHG = H, V(SW) = 0 V  
(free run by tMAX  
ICC1  
Supply current from VBAT  
Supply current from VCC  
17  
µA  
)
CHG = H, V(SW) = 0 V  
ICC2  
1.3  
3
mA  
(free run by tMAX  
)
Supply current from VCC and  
VBAT  
ICC3  
Ilkg1  
Ilkg2  
CHG = L  
1
2
1
µA  
µA  
µA  
Leakage current of SW terminal  
Leakage current of XFULL  
terminal  
V(XFULL) = 5 V  
V(I_PEAK) = 3 V, CHG: High  
V(I_PEAK) = 3 V, CHG: Low  
2
I(sink)  
Sink current at I_PEAK  
µA  
0.1  
SW ON resistance between  
SW and PGND  
R(ONSW)  
I(SW) = 1 A, VCC = 3 V  
0.4  
0.9  
R(IGBT1)  
R(IGBT2)  
I(PEAK1)  
I(PEAK2)  
G_IGBT pullup resistance  
G_IGBT pulldown resistance  
Upper peak of I(SW)  
V(G_IGBT) = 0 V, VCC = 3 V  
V(G_IGBT) = 3 V, VCC = 3 V  
V(I_IPEAK) = 3 V  
8
36  
12  
53  
19.4  
70  
A
A
1.58  
0.7  
28  
1.68  
0.8  
28.7  
29  
1.78  
0.9  
Lower peak of I(SW)  
V(I_IPEAK) = 0 V  
VBAT = 1.6V, VCC = 3 V  
VCC = 3 V  
29.4  
29.4  
60  
Charge completion detect voltage  
at V(SW)  
V(FULL)  
V(ZERO)  
V
28.6  
1
Zero current detection at V(SW)  
Thermal shutdown temperature  
Over VDS detection at V(SW)  
MAX OFF time  
20  
mV  
°C  
V
(1)  
T(SD)  
150  
0.95  
25  
160  
1.2  
50  
170  
1.45  
80  
t MIN  
tMAX  
µs  
µs  
MAX ON time  
50  
100  
160  
Pulldown resistance of CHG,  
F_ON  
R(INPD)  
VCHG = V(F_ON) = 4.2 V  
100  
kΩ  
(1) Specified by design.  
SWITCHING CHARACTERISTICS  
TA = 25°C, VBAT = 4.2 V, VCC = 3 V, V(SW) = 4.2 V (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
F_ON- G_IGBT↓  
MIN  
TYP  
MAX  
UNIT  
ns  
50  
45  
SW ON after V(SW) dips from V(ZERO)  
SW OFF after I(SW) exceeds I(PEAK)  
XFULLafter V(SW) exceeds V(FULL)  
SW ON after CHG↑  
ns  
270  
400  
12  
ns  
(1)  
tPD  
Propagation delay  
ns  
µs  
SW OFF after CHG↓  
20  
ns  
(1) Specified by design.  
3
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TPS65560  
www.ti.com  
SLVS608JANUARY 2006  
PIN ASSIGNMENT  
RGT  
(Top View)  
16 15 14 13  
1
2
3
4
12  
11  
10  
9
PGND  
PGND  
CHG  
SW  
SW  
PowerPAD  
VCC  
F_ON  
XFULL  
5
6
7
8
NC No internal connection  
TERMINAL FUNCTIONS  
PIN NUMBER  
SIGNAL  
I/O  
O
I
DESCRIPTION  
Primary side switch. Connect SW to the switched side of the transformer  
1, 2  
SW  
Power supply input. Connect VCC to an input supply from 2.7 V to 4 V. Bypass VCC to GND  
with a 1-µF ceramic capacitor as close as possible to the IC.  
3
VCC  
I
G_IGBT control input. Drives F_ON with the flash discharge signal. A logic high on F_ON  
drives G_IGBT high when CHG is Low. See the IGBT Driver Conrtol section for details.  
4
F_ON  
NC  
5, 8, 13, 16  
No internal connection  
I
Primary side peak current control input. The voltage at I_PEAK sets the peak current into  
6
7
I_PEAK  
G_IGBT  
SW. See the Programming Peak Current section for details on selecting V(I_PEAK)  
.
O
IGBT gate driver output. G_IGBT swings from PGND to VCC to drive external IGBT devices.  
Charge completion indicator output. XFULL is an open-drain output that pulls low once the  
output is fully charged. XFULL is high impedance during charging and all fault conditions.  
XFULL is reseted when CHG turns Low from High. See the Indicating Charging Status  
section for details.  
9
XFULL  
CHG  
O
I
10  
Charge control input. Drive CHG high to initiate charging of the output. Drive CHG low to  
terminate charging.  
11, 12  
14  
PGND  
Power ground. Connect to the ground plane.  
TEST_GND  
Used by TI, should be connected to PGND and ground plane.  
Battery voltage monitor input. Connect VBAT to an input supply from 1.6 V to 12 V. Bypass  
VBAT to GND with a 10-µF ceramic capacitor (C1 in Figure 1, as close as possible to the  
battery) and a 1-µF ceramic capacitor (C2 in Figure 1, as close as possible to the IC).  
15  
VBAT  
I
4
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TPS65560  
www.ti.com  
SLVS608JANUARY 2006  
FUNCTIONAL BLOCK DIAGRAM  
VCC  
VBAT  
SW  
CHG  
D
Q
F1  
0 Vds  
XFULL  
D
Q
F2  
U1  
ENA  
VCC  
V_FULL  
ENA  
U0  
Max ON  
U2  
TSD  
I_PEAK  
I_PEAK  
Ref.  
Logic  
V
PGND  
ref  
SW  
U3  
VCC  
G_IGBT  
F_ON  
ENA  
U4  
NC  
Figure 2. Functional Block Diagram  
I/O Equivalent Circuits  
CHG, F_ON  
SW  
VCC  
SW  
CHG,  
F_ON  
PGND  
PGND  
I_PEAK  
XFULL  
VCC  
XFULL  
I_PEAK  
PGND  
PGND  
G_IGBT  
VBAT  
VCC  
VBAT  
G_IGBT  
PGND  
PGND  
Figure 3. I/O Equivalent Circuits  
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TPS65560  
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SLVS608JANUARY 2006  
PRINCIPLES OF OPERATION  
CHG  
(VOUT)  
XFULL  
F_ON  
G_IGBT  
(ENA)  
TimeA  
TimeB  
TimeC  
TimeD  
TimeH  
TimeJ  
TimeE  
TimeI  
TimeF  
TimeG  
Figure 4. Whole Operation Sequence Chart  
Start/Stop Charging  
TPS65560 has one internal enable latch, F1, that holds the charge enable (ON/OFF status) of the device. See  
Figure 2.  
The only way to start charging is to input CHG(see time A/C/H in Figure 4). Each time CHGis applied, the  
TPS65560 starts charging.  
There are three trigger events to stop charging:  
1. Forced stop by inputting CHG = L from the controller (see timeB in Figure 4).  
2. Automatic stop by detecting a full charge. VOUT reaches the target value (see TimeD in Figure 4).  
3. Protected stop by detecting an over current function (OVDS) trigger at SW pin (see TimeI in Figure 4).  
Indicating Charging Status  
When the charging operation is complete, the TPS65560 drives the charge completion indicator pin, XFULL, to  
GND. A controller can detect the status of the device as a logic signal when connected through a pullup resister,  
R1 (see Figure 1).  
The XFULL output enables the controller to detect the OVDS protection status. If OVDS protection occurs, XFULL  
never goes L during CHG = H. Therefore, the controller detects OVDS protection by measuring the time from  
CHG high to XFULL low. If the time to XFULL low is longer than the maximum designed charge time, then an  
OVDS protection occurred.  
The device starts charging at timeH, and OVDS protection occurs at TimeI (see Figure 4). At TimeI, XFULL stays  
H. At TimeJ, the controller detects OVDS protection through the expiration of a timer ends and then sets CHG to  
low to terminate the operation.  
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TPS65560  
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SLVS608JANUARY 2006  
CHG  
XFULL  
SW  
SW  
OFF  
ON  
OFF  
LOGIC  
OFF  
ON  
OFF  
OFF ON  
OFF  
V
SW  
V
ZERO  
V
V
SW  
V
BAT  
V
FULL  
V
0 V  
V
V
BAT  
SW  
BAT  
V
A
V
OUT  
V
0 V  
V
OUT  
V
0 V  
V
A
V
0 V  
V
OUT  
V
A
I
I
SW  
PEAK  
I
0 A  
I
I
SW  
SW  
I
PEAK  
I
0 A  
I
OUT  
I /N  
PEAK TURN  
I
0 A  
I
I
OUT  
OUT  
I
/N  
PEAK TURN  
T
I
Time 1  
Time 3  
Time 5  
0 A  
Time 2  
Time 4  
T
Figure 5. Timing Diagram at One Switching Cycle  
Control Charging  
Figure 6. Timing Diagram at Beginning/Ending  
The TPS65560 provides three comparators to control charging. Figure 2 shows the block diagram of TPS65560  
and Figure 5 shows a timing diagram of one switch cycle. Note that emphasis is placed on Time1 and Time3 of  
the waveform in Figure 5.  
While SW is ON (Time1 to Time2 in Figure 5), U3 monitors current flow through the integrated power switch from  
SW pin to GND. When I(SW) exceeds I(PEAK), SW turns OFF (Time2 in Figure 5).  
When SW turns OFF (Time2 in Figure 5), the magnetic energy in the transformer starts discharging. Meanwhile,  
U2 monitors the kickback voltage at the SW terminal. As the energy is discharging, the kickback voltage is  
increasing according to the increase of VO (Time2 to Time3 in Figure 5). When almost all energy is discharged,  
the system cannot continue rectification via the diode, and the charging current of IO goes to zero (Times3 in  
Figure 5). After rectification stops, the small amount of energy left in the transformer is released via parasitic  
paths, and the kickback voltage reaches zero (Time3 to Time4 in Figure 5). During this period, U2 makes SW  
turn ON when (V(SW) - VBAT) dips from V(ZERO) (Time5 in Figure 5). In the actual circuit, the period between Time4  
and Time5 in Figure 5 is small or does not appear dependent on the delay time of the U2 detection to SW ON.  
U1 also monitors the kickback voltage. When (V(SW) - VBAT) exceeds V(FULL), the TPS65560 stops charging (see  
Figure 6).  
In Figure 5 and Figure 6, ON time is always the same period in every switch cycle. The ON time is calculated by  
Equation 1. L and I(PEAK) are selected to ensure that tON does not exceed the MAX ON time (tMAX).  
I
PEAK  
t
= L  
ON  
V
BAT  
(1)  
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TPS65560  
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SLVS608JANUARY 2006  
The OFF time is dependant on output voltage. As the output voltage gets higher, the OFF time gets shorter (see  
Equation 2).  
I
PEAK  
t
= N  
x L  
OFF  
TURN  
V
OUT  
(2)  
Programming Peak Current  
The TPS65560 provides a method to program the peak primary current with a voltage applied to the I_PEAK pin.  
Figure 7 shows how to program I(PEAK)  
.
The I_PEAK input is treated as a logic input below V(PKL) (0.6 V) and above V(PKH) (2.4 V). Between V(PKL) and  
V(PKH), I_PEAK input is treated as an analog input. Using this characteristic, I(PEAK) can be set by a logic signal or  
by an analog input.  
Typical usages of this function are:  
1. Setting the peak charging currents based on the battery voltage. Larger I(PEAK) for a fully charged battery and  
lower I(PEAK) for a discharged battery.  
2. Reducing I(PEAK) when powering a zooming lens motor. This avoids inadvertent shutdowns due to large  
current from the battery.  
In Figure 1, three optional connections to I_PEAK are shown.  
1. Use the controller to treat I_PEAK as the logic input pin. This option is the easiest.  
2. Use a D/A converter to force I(PEAK) to follow analog information, such as battery voltage.  
3. Use an analog circuit to achieve the same results as the D/A converter.  
I
PEAK1  
I
PEAK2  
Voltage of I_PEAK - V  
Figure 7. I_PEAK vs I(SW)  
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TPS65560  
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SLVS608JANUARY 2006  
IGBT Driver Control  
The IGBT driver is provided by the TPS65560. The driver voltage depends on VCC. TPS65560 has a mask filter  
as shown in Figure 8. The mask does not have hysteresis; therefore, there is no wait time from CHG forcing Low  
after FULL CHARGE to F_ON turning High.  
CHG  
XFULL  
F_ON  
G_IGBT  
SW On  
STANDBY  
PREACTIVE  
SW Off  
etc  
FULL CHARGE  
STANDBY  
Figure 8. IGBT Timing Diagram  
Protections  
TPS65560 provides four protection mechanisms: max on time, max off time, thermal disable, and overcurrent  
shutdown.  
MAX On Time  
To prevent a condition such as pulling current from a poor power source (i.e., an almost empty battery), and  
never reaching peak current, the TPS65560 provides a maximum ON time function. If the ON time exceeds tMAX  
the TPS5560 is forced OFF regardless of I(PEAK) detection.  
,
MAX Off Time  
To prevent a condition such as never increasing the voltage at the SW pin when the internal FET is OFF, the  
TPS65560 provides a maximum OFF time function. If the OFF time exceeds tMIN, the TPS65560 is forced ON  
regardless of V(ZERO) detection.  
Thermal Disable  
Once the TPS65560 die temperature reaches 160°C, all functions stop. Once the die cools below 160°C, the  
TPS65560 restarts charging if CHG remains high during the entire overtemperature condition.  
Overcurrent Shutdown to Monitor VDS at the SW Pin (OVDS  
)
The TPS65560 provides an overvoltage monitor function of the SW pin. The TPS65560 is latched off if the  
voltage on the SW pin is above OVDS during the switch ON time (see Figure 4 and its descriptions).  
This function protects against short-circuits on the primary side of the transformer. A short-circuit of the primary  
side shorts the battery voltage to GND. SW pin can damage the device if not protected.  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
14-Mar-2006  
PACKAGING INFORMATION  
Orderable Device  
TPS65560RGTR  
TPS65560RGTRG4  
TPS65560RGTT  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
QFN  
RGT  
16  
16  
16  
16  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
QFN  
QFN  
QFN  
RGT  
RGT  
RGT  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
TPS65560RGTTG4  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
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