TPS65735_16_技术文档

TPS65735

PMU For Active Shutter 3D Glasses

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SLVSAI6

June 2011

TPS65735

SLVSAI6–JUNE 2011

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Contents

1

2

INTRODUCTION .................................................................................................................. 5

1.1

1.2

1.3

1.4

Features ...................................................................................................................... 5

Description ................................................................................................................... 5

Pin Descriptions ............................................................................................................. 6

Package Pin Assignments ................................................................................................. 7

POWER MANAGEMENT CORE .............................................................................................. 8

2.1

2.2

2.3

2.4

Recommended Operating Conditions .................................................................................... 8

Absolute Maximum Ratings ................................................................................................ 8

Thermal Information ........................................................................................................ 9

Quiescent Current ........................................................................................................... 9

2.5

2.6

Electrical Characteristics ................................................................................................... 9

System Operation ......................................................................................................... 13

2.6.1

2.6.2

2.6.3

System Power Up .............................................................................................. 13

System Operation Using Push Button Switch .............................................................. 14

System Operation Using Slider Switch ...................................................................... 15

2.7

Linear Charger Operation ................................................................................................ 16

2.7.1

Battery and TS Detection ...................................................................................... 16

Battery Charging ................................................................................................ 16

2.7.2

2.7.2.1 Pre-charge .......................................................................................... 17

2.7.2.2 Charge Termination ................................................................................ 17

2.7.2.3 Recharge ............................................................................................ 17

2.7.2.4 Charge Timers ...................................................................................... 17

Charger Status (nCHG_STAT Pin) ........................................................................... 18

2.7.3

2.8

2.9

LDO Operation ............................................................................................................. 18

LDO Internal Current Limit .................................................................................... 18

Boost Converter Operation ............................................................................................... 19

2.8.1

2.9.1

Boost Thermal Shutdown ...................................................................................... 19

Boost Load Disconnect ........................................................................................ 20

2.9.2

2.10 Full H-Bridge Analog Switches .......................................................................................... 20

2.10.1 H-Bridge Switch Control ....................................................................................... 20

2.11 Power Management Core Control ....................................................................................... 22

2.11.1 SLEEP / Power Control Pin Function ........................................................................ 22

2.11.2 COMP Pin Functionality ....................................................................................... 22

2.11.3 SW_SEL Pin Functionality .................................................................................... 23

2.11.4 SWITCH Pin ..................................................................................................... 23

2.11.5 Slider Switch Behavior ......................................................................................... 23

2.11.6 Push-Button Switch Behavior ................................................................................. 24

APPLICATION INFORMATION ............................................................................................. 26

3

3.1

Applications Schematic ................................................................................................... 26

3.2

3.3

Reducing System Quiescent Current (I_Q) .............................................................................. 26

Boost Converter Application Information ............................................................................... 27

3.3.1

3.3.2

3.3.3

Setting Boost Output Voltage ................................................................................. 27

Boost Inductor Selection ....................................................................................... 28

Boost Capacitor Selection ..................................................................................... 28

3.4

Bypassing Default Push-Button SWITCH Functionality .............................................................. 28

2

Contents

TPS65735

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List of Figures

1-1

TPS65735 Functional Block Diagram...........................................................................................

TPS65735 Package Pin Assignments ..........................................................................................

5

7

1-2

2-1

System Power Up State Diagram .............................................................................................. 14

Push Button State Diagram..................................................................................................... 15

System Operation Using Slider Switch ........................................................................................ 15

Thermistor Detection and Circuit .............................................................................................. 16

Battery Charge Phases.......................................................................................................... 17

Boost Load Disconnect.......................................................................................................... 20

H-Bridge States................................................................................................................... 21

H-Bridge States from Oscilloscope ............................................................................................ 22

SLEEP Signal to Force System Power Off ................................................................................... 22

COMP Pin Internal Connection................................................................................................. 22

SWITCH, Slider Power On-Off Behavior...................................................................................... 24

SWITCH, Push-button Power On Behavior................................................................................... 25

SWITCH, Push-button Power Off Behavior................................................................................... 25

TPS65735 Applications Schematic ............................................................................................ 26

Reducing System I_Qwith Addition of a FET .................................................................................. 27

Boost Feedback Network Schematic .......................................................................................... 27

Bypassing Default TPS65735 Push Button SWITCH Timing............................................................... 29

SWITCH Press and SLEEP Signal to Control System Power Off ......................................................... 29

2-2

2-3

2-4

2-5

2-10

2-11

2-12

2-13

2-14

2-15

2-16

2-17

3-1

3-2

3-3

3-4

3-5

List of Figures

3

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List of Tables

1-1

1-2

2-1

2-2

2-3

2-4

2-5

2-6

3-1

Pin Descriptions ...................................................................................................................

Pin Absolute Maximum Ratings..................................................................................................

6

7

nCHG_STAT Functionality ...................................................................................................... 18

VLDO_SET Functionality........................................................................................................ 18

H-Bridge States from Inputs .................................................................................................... 21

Scaling Resistors for COMP Pin Function (V_VLDO= 2.2 V) ................................................................. 23

Scaling Resistors for COMP Pin Function (V_VLDO= 3.0 V) ................................................................. 23

SW_SEL Settings ................................................................................................................ 23

Recommended R_FB1and R_FB2Values (for I_Q(FB)= 5 µA) .................................................................... 28

4

List of Tables

TPS65735

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PMU For Active Shutter 3D Glasses

Check for Samples: TPS65735

1

INTRODUCTION

• Boost Converter

1.1 Features

– Adjustable Output Voltage: 8 V to 16 V

– Boost Output Internally Connected to

H-Bridge Analog Switches

• Full H-Bridge Analog Switches

– Controlled by an External Microcontroller for

System Operation

• Output Pin for Divided Down Battery Voltage

1

• Linear Charger

– Three Charger Phases: Pre-charge, Fast

Charge, and Charge Termination

– Externally Set Charge Current, Supports up

to 100 mA

– LED Current Sinks for Power Good and

Charger Status Indication

• LDO Supply for External Modules

Useful for ADC or Comparator Input of an MCU

(Microcontroller, RF Module, IR Module)

– LDO Continuous Output Current up to 30 mA

1.2 Description

The TPS65735 is a PMU for active shutter 3D glasses consisting of an integrated power path, linear

charger, LDO, boost converter, and full H-bridge analog switches for left and right shutter operation in a

pair of active shutter 3D glasses. In addition to the power devices, a typical 3D glasses system contains

both a microcontroller and a communications front end (IR, RF, or other) in order to handle the

communication and synchronous operation along with a 3D television.

Figure 1-1. TPS65735 Functional Block Diagram

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS65735

SLVSAI6–JUNE 2011

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1.3 Pin Descriptions

Table 1-1. Pin Descriptions

PIN NAME

I/O

PIN NO.

DESCRIPTION

POWER MANAGEMENT CORE (PMIC)

VIN

I

20

15

AC or USB Adapter Input

ISET

I/O

Fast-Charge Current Setting Resistor

Pin for 10 kΩ NTC Thermistor Connection

FLOAT IF THERMISTOR / TS FUNCTION IS NOT USED

TS

I

16

29

Open-drain Output, Charge Status Indication

CONNECT TO GROUND IF FUNCTION IS NOT USED

nCHG_STAT

O

BAT

I/O

O

I

18

19

21

22

25

26

11

13

10

8

Charger Power Stage Output and Battery Voltage Sense Input

Output Terminal to System

SYS

VLDO

LDO Output

VLDO_SET

SWITCH

SW_SEL

BST_SW

BST_FB

BST_OUT

HBR1

Sets LDO Output Voltage (see Table 2-2)

Switch Input for Device Power On/Off

Selects Type of Switch Connected to SWITCH Pin (see Table 2-6)

Boost Switch Node

I

O

I

Boost Feedback Node

O

I

Boost Output

H-Bridge Input 1 for Right LC Shutter

H-Bridge Input 2 for Right LC Shutter

H-Bridge Input 1 for Left LC Shutter

HBR2

I

9

HBL1

I

32

7

HBL2

I

H-Bridge Input 2 for Left LC Shutter

LCRN

O

6

H-Bridge Output for Right LC Shutter, "Negative" Terminal

H-Bridge Output for Right LC Shutter, "Positive" Terminal

H-Bridge Output for Left LC Shutter, "Negative" Terminal

H-Bridge Output for Left LC Shutter, "Positive" Terminal

LCRP

5

LCLN

4

LCLP

3

Scaled Battery Voltage for MCU Comparator or ADC Input (Battery Voltage Monitoring)

DO NOT CONNECT IF COMP FUNCTION IS NOT USED

COMP

O

23

SLEEP

I/O

31

1

Sleep Enable Input from an MCU (edge triggered, only for system shutdown)

Boost Enable Input from an MCU, High = Boost Enabled

BST_EN

CHG_EN

I

30

Charger Enable Input from an MCU, High = Boost Enabled

I²C Clock Pin (only used for TI debug and test)

GROUND PIN IN APPLICATION

PSCL

PSDA

I/O

28

27

I²C Data Pin (only used for TI debug and test)

GROUND PIN IN APPLICATION

PGNDBST

AGND

-

12

24

2

Boost Power Ground

Analog Ground

DGND

Digital Ground

MISC. AND PACKAGE

There is an internal electrical connection between the exposed thermal pad and the AGND ground

pin of the device. The thermal pad must be connected to the same potential as the AGND pin on

the printed circuit board. Do not use the thermal pad as the primary ground input for the device.

AGND pin must be connected to ground at all times.

Thermal PAD

N/C

-

33

14, 17

All N/C should be connected to the main system ground.

6

INTRODUCTION

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Table 1-2. Pin Absolute Maximum Ratings

VALUE / UNIT

Input voltage range on all pins (except for VIN, BST_OUT, BST_SW, BST_FB, VLDO, LCLP, LCLN, LCRP,

LCRN, AGND, DGND, and PGNDBST) with respect to AGND

-0.3 V to 7.0 V

VIN with respect to AGND

-0.3 V to 28.0 V

-0.3 V to 18.0 V

-0.3 V to 3.6 V

BST_OUT, BST_SW, LCLP, LCLN, LCRP, and LCRN with respect to PGNDBST

BST_FB with respect to PGNDBST, VLDO with respect to DGND

1.4 Package Pin Assignments

Figure 1-2. TPS65735 Package Pin Assignments

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INTRODUCTION

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2

POWER MANAGEMENT CORE

2.1 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

SUBSYSTEM AND PARAMETER

MIN

NOM

MAX

UNIT

CHARGER / POWER PATH

V_VIN

Voltage range at charger input pin

Input current at VIN pin

Capacitor on VIN pin

3.7

28

200

10

V

mA

µF

µH

V

I_VIN

C_VIN

0.1

0

L_VIN

Inductance at VIN pin

2

V_SYS

Voltage range at SYS pin

Output current at SYS pin

Capacitor on SYS pin

2.5

6.4

100

10

I_SYS(OUT)

C_SYS

mA

µF

V

0.1

2.5

4.7

320

V_BAT

Voltage range at BAT pin

Capacitor on BAT pin

6.4

10

C_BAT

µF

Ω

R_{EXT(nCHG_STAT)}

Resistor connected to nCHG_STAT pin to limit

current into pin

BOOST CONVERTER / H-BRIDGE SWITCHES

V_{IN(BST_SW)}

V_{BST_OUT}

C_{BST_OUT}

Input voltage range for boost converter

2.5

8

6.5

16

10

V

Output voltage range for boost converter

Boost output capacitor

3.3

4.7

µF

µH

(1)

L_{BST_SW}

Inductor connected between SYS and BST_SW pins

Device optimized for operation with 10 µH inductor

LDO

C_VLDO

External decoupling cap on pin VLDO

1

10

µF

POWER MANAGEMENT CORE CONTROL (LOGIC LEVELS FOR GPIOs)

V_IL(PMIC)

GPIO low level (BST_EN, CHG_EN, SW_SEL,

VLDO_SET and to switch H-Bridge inputs to a low, 0,

level)

0.4

V

V_IH(PMIC)

GPIO high level (BST_EN, CHG_EN, SW_SEL,

VLDO_SET and to switch H-Bridge inputs to a high,

1, level)

1.2

V

(1) See Section 2.9 for information on boost converter inductor selection.

2.2 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

PARAMETER

MINIMUM

MAXIMUM

UNITS

°C

Operating free-air temperature, T_A

0

60

Max Junction Temperature, T_J, Electrical Characteristics Guaranteed

Max Junction temperature, T_J, Functionality Guaranteed⁽¹⁾

85

°C

105

°C

(1) Device has a thermal shutdown feature implemented that shuts down at 105 °C

8

POWER MANAGEMENT CORE

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2.3 Thermal Information

TPS65735

RSN

32 PINS

38.9

THERMAL METRIC

UNITS

θ_JA

Junction-to-ambient thermal resistance⁽¹⁾

Junction-to-case (top) thermal resistance⁽²⁾

Junction-to-board thermal resistance⁽³⁾

Junction-to-top characterization parameter⁽⁴⁾

Junction-to-board characterization parameter⁽⁵⁾

Junction-to-case (bottom) thermal resistance⁽⁶⁾

θ_JCtop

θ_JB

26.5

9.8

°C/W

ψ_JT

0.3

ψ_JB

9.8

θ_JCbot

3.5

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

2.4 Quiescent Current

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_Q(SLEEP)

Power management core quiescent @ 25° C

8.6

10.5

µA

current in sleep mode

V_BAT= 3.6 V

V_VIN= 0 V

No load on LDO

CHG_EN, BST_EN grounded

BST_FB = 300 mV

Power management core in sleep

mode / device 'off'

I_Q(ACTIVE)

Power management core quiescent @ 25° C

current in active mode V_BAT= 3.6 V

39

53.5

µA

V_VIN= 0 V

Boost enabled but not switching,

H-bridge in grounded state

No load on LDO

Power management core in active

mode

2.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BATTERY CHARGER POWER PATH

V_UVLO(VIN)Undervoltage lockout at power path V_VIN: 0 V → 4 V

3.2

200

40

3.3

3.45

300

140

V

input, VIN pin

V_HYS-

UVLO(VIN)

Hysteresis on UVLO at power path

input, VIN pin

V_VIN: 4 V → 0 V

mV

V_IN-DT

Input power detection threshold

Input power detected if: (V_VIN> V_BAT

+ V_IN-DT);

V_BAT= 3.6 V

V_VIN: 3.5 V → 4 V

V_HYS-INDT

Hysteresis on V_IN-DT

V_BAT= 3.6 V

20

mV

V_VIN: 4 V → 3.5 V

POWER MANAGEMENT CORE

9

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OVP

Input over-voltage protection

threshold

V_VIN: 5 V → 7 V

6.4

6.6

6.8

V

V_HYS-OVP

Hysteresis on OVP

V_VIN: 11 V → 5 V

105

mV

V_DO(VIN-

SYS)

VIN pin to SYS pin dropout voltage

I_SYS= 150 mA (including I_BAT

V_VIN= 4.35 V

V_BAT= 3.6 V

)

350

150

V_VIN– V_SYS

V_DO(BAT-

SYS)

BAT pin to SYS pin dropout voltage I_SYS= 100 mA

_BAT– V_SYSV_VIN= 0 V

_BAT> 3 V

mV

V

I_VIN(MAX)

Maximum power path input current

at pin VIN

V_VIN= 5 V

200

mA

V

V_SUP(ENT)

Enter battery supplement mode

V_SYS

≤

(V_BAT- 40

mV)

V_SUP(EXIT)Exit battery supplement mode

V_SYS

≥

V

(V_BAT- 20

mV)

V_SUP(SC)

V_O(SC)

Output short-circuit limit in

supplement mode

250

mV

V

Output short-circuit detection

threshold, power-on

0.9

BATTERY CHARGER

I_CC

Active supply current into VIN pin

V_VIN= 5 V

2

mA

No load on SYS pin

V_BAT> V_BAT(REG)

I_BAT(SC)

Source current for BAT pin

short-circuit detection

1

mA

V

V_BAT(SC)

BAT pin short-circuit detection

threshold

1.6

1.8

2.0

V_BAT(REG)Battery charger output voltage

–1%

4.20

3.0

1%

3.1

V

V_LOWV

Pre-charge to fast-charge transition

threshold

2.9

I_CHG

Charger fast charge current range

I_CHG= K_ISET/ R_ISET

V_VIN= 5 V

_BAT(REG)> V_BAT> V_LOWV

5

100

mA

V

K_ISET

Battery fast charge current set factor V_VIN= 5 V

–20%

450

20%

AΩ

I_CHG= K_ISET/ R_ISET

I_VIN(MAX)> I_CHG

I_CHG= 100 mA

No load on SYS pin, thermal loop

not active.

I_PRECHG

I_TERM

Pre-charge current

0.07 ×

I_CHG

0.10 ×

I_CHG

0.15 ×

I_CHG

mA

mV

Charge current value for termination I_CHG= 100 mA

detection threshold

7

10

15

V_RCH

Recharge detection threshold

V_BATbelow nominal charger voltage,

55

100

170

V_BAT(REG)

I_BAT(DET)

t_CHG

Sink current for battery detection

1

mA

s

Charge safety timer

18000

(18000 seconds = 5 hours)

t_PRECHG

V_DPPM

Pre-charge timer

(1800 seconds = 30 minutes)

1800

s

V

DPPM threshold

V_BAT+

100 mV

I_LEAK(nCHG)Leakage current for nCHG_STAT

V_{nCHG_STAT}= 4.2 V

CHG_EN = LOW (Charger disabled)

100

60

nA

Ω

R_DSON(nCHOn resistance for nCHG_STAT

20

MOSFET switch

G)

10

POWER MANAGEMENT CORE

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_MAX(nCHG)Maximum input current to

nCHG_STAT pin

50

mA

BATTERY CHARGER NTC MONITOR

I_TSBIAS

V_COLD

TS pin bias current

75

µA

0°C charge threshold for 10kΩ NTC

(β = 3490)

2100

mV

V_HYS(COLD)Low temperature threshold

hysteresis

Battery charging and battery / NTC

temperature increasing

300

mV

V_HOT

50°C charge threshold for 10kΩ

NTC

(β = 3490)

V_HYS(HOT)High temperature threshold

hysteresis

Battery charging and battery / NTC

temperature decreasing

30

mV

BATTERY CHARGER THERMAL REGULATION

T_{J(REG_LO}Charger lower thermal regulation

75

95

°C

limit

WER)

T_{J(REG_UPP}Charger upper thermal regulation

limit

ER)

T_J(OFF)

Charger thermal shutdown

temperature

105

20

T_J(OFF-HYS)Charger thermal shutdown

hysteresis

LDO

I_MAX(LDO)

Maximum LDO output current,

V_VLDO= 2.2 V

V_SYS= 4.2 V

V_VIN= 0 V

VLDO_SET = 0 V

30

mA

Maximum LDO output current,

V_VLDO= 3.0 V

V_SYS= 4.2 V

V_VIN= 0 V

mA

VLDO_SET = V_SYS

I_SC(LDO)

V_VLDO

Short circuit current limit

LDO output voltage

30

100

mA

V

VLDO_SET = LOW

(VLDO_SET pin connected to

DGND)

3.7 V ≤ V_VIN≤ 6.5 V

I_LOAD(LDO)= -10 mA

2.13

2.2

3.0

2.27

V_VLDO

LDO output voltage

VLDO_SET = HIGH

2.91

3.09

V

(V_{VLDO_SET}= V_SYS

)

3.7 V ≤ V_VIN≤ 6.5 V

I_LOAD(LDO)= -10 mA

V_DO(LDO)

LDO Dropout voltage

Line regulation

V_VIN- V_LDOwhen in dropout

I_LOAD(LDO)= -10 mA

200

1

mV

%

3.7 V ≤ V_VIN≤ 6.5 V

I_LOAD(LDO)= -10 mA

-1

-2

Load regulation

V_VIN= 3.5 V

2

%

0.1 mA ≤ I_LOAD(LDO)≤ -10 mA

PSRR

Power supply rejection ratio

@20 KHz, I_LOAD(LDO)= 10 mA

V_DO(LDO)= 0.5 V

45

dB

C_VLDO= 10 µF

BOOST CONVERTER

I_Q(BST)Boost operating quiescent current

Boost Enabled, BST_EN = High

I_OUT(BST)= 0 mA

(boost is not switching)

V_BAT= 3.6 V

2

4.5

1.2

µA

R_DSON(BST)Boost MOSFET switch on-resistance V_IN(BST)= 2.5 V

I_SW(MAIN)= 200 mA

0.8

Ω

POWER MANAGEMENT CORE

11

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I_{LKG(BST_S}Leakage into BST_SW pin

BST_EN signal = LOW (Boost

disabled)

90

nA

(includes leakage into analog

W)

h-bridge switches)

V_{BST_SW}= 4.2 V

No load on BST_OUT pin

I_SWLIM(BST)Boost MOSFET switch current limit

V_DIODE(BSTVoltage across integrated boost

100

150

200

1.0

mA

V

BST_EN signal = HIGH

V_{BST_SW}= 16.0 V

diode during normal operation

)

I_{BST_OUT}= - 2 mA

V_REF(BST)

Boost reference voltage on BST_FB

1.17

2

1.2

2.5

6.5

1.23

3.2

8

V

%

µs

V_REFHYS(BSBoost reference voltage hysteresis

T)

on BST_FB pin

T_ON(BST)

Maximum on time detection

threshold

5

T_OFF(BST)

Minimum off time detection threshold

1.4

1.75

105

20

2.1

µs

°C

T_SHUT(BST)Boost thermal shutdown threshold

T_SHUT-

HYS(BST)

Boost thermal shutdown threshold

hysteresis

FULL H-BRIDGE ANALOG SWITCHES

I_Q(HSW)

Operating quiescent current for

h-bridge switches

5

µA

Ω

R_DSON(HSWH-bridge switches on resistance

20

40

)

T_DELAY(HSH-bridge switch propagation delay,

V_HBxy= 0 V → V_VLDO

100

ns

input switched from low to high

W-H)

state.

T_DELAY(HSH-bridge switch propagation delay,

V_HBxy= V_VLDO→ 0 V

100

ns

input switched from high to low

W-L)

state.

POWER MANAGEMENT CORE CONTROLLER

V_IL(PMIC)

Low logic level for logic signals on

power management core

(BST_EN, CHG_EN, SLEEP, HBR1, I_IN= 1 mA

HBR2, HBL1, HBL2)

IO logic level decreasing:

0.4

V

V_SYS→ 0 V

V_IH(PMIC)

High logic level for signals on power IO logic level increasing:

1.2

management core

0 V → V_SYS

(BST_EN, CHG_EN, SLEEP, HBR1, I_IN= 1 mA

HBR2, HBL1, HBL2)

V_GOOD(LDOPower fault detection threshold

)

V_VLDOdecreasing

1.96

V

mV

V

V_{GOOD_HYS}Power fault detection hysteresis

(LDO)

V_VLDOincreasing

50

1.85

1.10

V_BATCOMPCOMP pin voltage (scaled down

battery voltage)

V_BAT= 4.2 V

V_VLDO= 2.2 V

V_BAT= 2.5 V

V_VLDO= 2.2 V

V

V_BAT= 4.2 V

V_VLDO= 3.0 V

1.90

1.50

V_BAT= 3.3 V

V_VLDO= 3.0 V

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2.6 System Operation

The system must complete the power up routine before it enters normal operating mode. The specific

system operation depends on the setting defined by the state of the SW_SEL pin. The details of the

system operation for each configuration of the SW_SEL pin are contained in this section.

2.6.1 System Power Up

Figure 2-1. System Power Up State Diagram

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2.6.2 System Operation Using Push Button Switch

Figure 2-2. Push Button State Diagram

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2.6.3 System Operation Using Slider Switch

Figure 2-3. System Operation Using Slider Switch

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2.7 Linear Charger Operation

This device has an integrated Li-Ion battery charger and system power path management feature targeted

at space-limited portable applications. The architecture powers the system while simultaneously and

independently charging the battery. This feature reduces the number of charge and discharge cycles on

the battery, allows for proper charge termination, and enables the system to run with a defective or absent

battery pack. It also allows instant system turn-on even with a totally discharged battery.

The input power source for charging the battery and running the system can be an AC adapter or USB

port connected to the VIN pin as long as the input meets the device operating conditions outlined in this

datasheet. The power-path management feature automatically reduces the charging current if the system

load increases. Note that the charger input, VIN, has voltage protection up to 28 V.

2.7.1 Battery and TS Detection

To detect and determine between a good or damaged battery, the device checks for a short circuit on the

BAT pin by sourcing I_BAT(SC)to the battery and monitoring the voltage on the BAT pin. While sourcing this

current if the BAT pin voltage exceeds V_BAT(SC), a battery has been detected. If the voltage stays below

the V_BAT(SC)level, the battery is presumed to be damaged and not safe to charge.

The device will also check for the presence of a 10 kΩ NTC thermistor attached to the TS pin of the

device. The check for the NTC thermistor on the TS pin is done much like the battery detection feature

described previously. The voltage on the TS pin is compared against a defined level and if it is found to be

above the threshold, the NTC thermistor is assumed to be disconnected or not used in the system. To

reduce the system quiescent current, the NTC thermistor temperature sensing function is only enabled

when the device is charging and when the thermistor has been detected.

Figure 2-4. Thermistor Detection and Circuit

2.7.2 Battery Charging

The battery is charged in three phases: conditioning pre-charge, constant-current fast charge (current

regulation), and a constant-voltage tapering (voltage regulation). In all charge phases, an internal control

loop monitors the IC junction temperature and reduces the charge current if an internal temperature

threshold is exceeded. Figure 2-5 shows what happens in each of the three charge phases:

16

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Figure 2-5. Battery Charge Phases

In the pre-charge phase, the battery is charged with the pre-charge current that is scaled to be 10% of the

fast-charge current set by the resistor connected to the ISET pin. Once the battery voltage crosses the

V_LOWVthreshold, the battery is charged with the fast-charge current (I_CHG). As the battery voltage reaches

V_BAT(REG), the battery is held at a constant voltage of V_BAT(REG)and the charge current tapers off as the

battery approaches full charge. When the battery current reaches I_TERM, the charger indicates charging is

done by making the nCHG_STAT pin high impedance. Note that termination detection is disabled

whenever the charge rate is reduced from the set point because of the actions of the thermal loop, the

DPM loop, or the V_IN(LOWV)loop.

2.7.2.1 Pre-charge

The value for the pre-charge current is set to be 10% of the charge current that is set by the external

resistor, R_ISET. Pre-charge current is scaled to lower currents when the charger is in thermal regulation.

2.7.2.2 Charge Termination

In the fast charge state, once V_BAT≥ V_BAT(REG), the charger enters constant voltage mode. In constant

voltage mode, the charge current will taper until termination when the charge current falls below the I_(TERM)

threshold (typically 10% of the programmed fast charge current). Termination current is not scaled when

the charger is in thermal regulation. When the charging is terminated, the nCHG_STAT pin will be high

impedance (effectively turning off any LED that is connected to this pin).

2.7.2.3 Recharge

Once a charge cycle is complete and termination is reached, the battery voltage is monitored. If V_BAT

V_BAT(REG)- V_RCH, the device determines if the battery has been removed. If the battery is still present, then

the recharge cycle begins and will end when V_BAT≥ V_BAT(REG)

<

.

2.7.2.4 Charge Timers

The charger in this device has internal safety timers for the pre-charge and fast charge phases to prevent

potential damage to either the battery or the system. The default values for these timers are found as

follows: Pre-charge timer = 0.5 hours (30 minutes) and Fast charge timer = 5 hours (300 minutes).

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During the fast charge phase, the following events may increase the timer durations:

1. The system load current activates the DPM loop which reduces the available charging current

2. The input current is reduced because the input voltage has fallen to V_IN(LOW)

3. The device has entered thermal regulation because the IC junction temperature has exceeded T_J(REG)

During each of these events, the internal timers are slowed down proportionately to the reduction in

charging current.

If the pre-charge timer expires before the battery voltage reaches V_LOWV, the charger indicates a fault

condition.

2.7.3 Charger Status (nCHG_STAT Pin)

The nCHG_STAT pin is used to indicate the charger status by an externally connected resistor and LED

circuit. The pin is an open drain input and the internal switch is controlled by the logic inside of the

charger. This pin may also be connected to a GPIO of the system MCU to indicate charging status. The

table below details the status of the nCHG_STAT pin for various operating states of the charger.

Table 2-1. nCHG_STAT Functionality

Charging Status

nCHG_STAT FET / LED

Pre-charge / Fast Charge / Charge Termination

ON

Recharge

OVP

OFF

SLEEP

2.8 LDO Operation

The power management core has a low dropout linear regulator (LDO) with variable output voltage

capability. This LDO is used for supplying the microcontroller and may be used to supply either an

external IR or RF module, depending on system requirements. The LDO can supply a continuous current

of up to 30 mA.

The output voltage (V_VLDO) of the LDO is set by the state of the VLDO_SET pin. See Table 2-2 for details

on setting the LDO output voltage.

Table 2-2. VLDO_SET Functionality

VLDO_SET State

VLDO Output Voltage (V_VLDO)

Low (VLDO_SET < V_IL(PMIC)

)

2.2 V

3.0 V

High (VLDO_SET > V_IH(PMIC)

)

2.8.1 LDO Internal Current Limit

The internal current limit feature helps to protect the LDO regulator during fault conditions. During current

limit, the output sources a fixed amount of current that is defined in the electrical specification table. The

voltage on the output in this stage can not be regulated and will be V_OUT= I_LIMIT× R_LOAD. The pass

transistor integrated into the LDO will dissipate power, (V_IN- V_OUT) × I_LIMIT, until the device enters thermal

shutdown. In thermal shutdown the device will enter the "SLEEP / POWER OFF" state which means that

the LDO will then be disabled and shut off.

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2.9 Boost Converter Operation

The boost converter in this device is designed for the load of active shutter 3D glasses. This load is

typically a light load where the average current is 2 mA or lower and the peak current out of a battery is

limited in operation. This asynchronous boost converter operates with a minimum off time / maximum on

time for the integrated low side switch, these values are specified in the electrical characteristics table of

this datasheet.

The peak output voltage from the boost converter is adjustable and set by using an external resistor

divider connected between BST_OUT, the BST_FB pin, and ground. The peak output voltage is set by

choosing resistors for the feedback network such that the voltage on the BST_FB pin is V_REF(BST)= 1.2 V.

See Section 3.3 for more information on calculating resistance values for this feedback network.

The efficiency curves for various input voltages over the typical 3D glasses load range (2 mA and lower)

are shown below. All curves are for a target V_OUTof 16 V. For output voltages less than 16 V, a higher

efficiency at each operating input voltage should be expected. Note that efficiency is dependent upon the

external boost feedback network resistances, the inductor used, and the type of load connected.

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 3.0 V

0.01

V_OUT= 16.0 V

1

V_IN= 3.7 V

0.01

V_OUT= 16.0 V

1 2

0.1

2

0.1

Output Current (mA)

G000

Figure 2-6. Boost Efficiency vs. I_OUT, V_IN= 3.0 V,

Figure 2-7. Boost Efficiency vs. I_OUT, V_IN= 3.7 V,

V_OUT= 16 V

100

90

80

70

60

50

40

30

20

10

90

80

70

60

50

40

30

20

10

V_IN= 4.2 V

0.01

V_OUT= 16.0 V

1

V_IN= 5.5 V

0.01

V_OUT= 16.0 V

1 2

0

0.1

2

0.1

Output Current (mA)

G000

Figure 2-8. Boost Efficiency vs. I_OUT, V_IN= 4.2 V,

V_OUT= 16 V

Figure 2-9. Boost Efficiency vs. I_OUT, V_IN= 5.5 V,

V_OUT= 16 V

2.9.1 Boost Thermal Shutdown

An internal thermal shutdown mode is implemented in the boost converter that shuts down the device if

the typical junction temperature of 105°C is exceeded. If the device is in thermal shutdown mode, the

main switch of the boost is open and the device enters the "SLEEP / POWER OFF" state.

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2.9.2 Boost Load Disconnect

When the boost is disabled (BST_EN = LOW), the H-bridge is automatically placed into the OFF state. In

the OFF state the high side H-bridge switches are open and the low side switches of the H-bridge are

closed. The OFF state grounds and discharges the load, potentially prolonging the life of the LC shutters

by eliminating any DC content (see Section 2.10.1 for more information regarding the H-bridge states).

The disconnection of the load is done with the H-Bridge and can be seen in the next figure (Figure 2-10).

Figure 2-10. Boost Load Disconnect

An advantage to this topology for disconnecting the load is that the boost output capacitor is charged to

approximately the SYS voltage level, specifically V_SYS- V_DIODE(BST), when the boost is disabled. This

design ensures that there is not a large in-rush current into the boost output capacitor when the boost is

enabled. The boost operation efficiency is also increased because there is no load disconnect switch in

the boost output path, such a switch would decrease efficiency because of the resistance that it would

introduce.

2.10 Full H-Bridge Analog Switches

The TPS65735 has two integrated full H-bridge analog switches that can be connected to GPIOs of a host

microcontroller. There is an internal level shifter that takes care of the input signals to the H-Bridge

switches.

2.10.1 H-Bridge Switch Control

The H-Bridge switches are controlled by an external microcontroller for system operation - specifically to

control charge polarity on the LCD shutters. Depending on the state of the signals from the

microcontroller, the H-Bridge will be put into 4 different states. These states are:

•

OPEN: All Switches Opened

CHARGE+: Boost Output Voltage Present on Pins LCLP or LCRP

CHARGE-: Boost Output Voltage Present on Pins LCLN or LCRN

GROUNDED: High side switches are opened and low side switches are closed

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If CHARGE+ state is followed by the CHARGE- state, the voltage across the capacitor connected to the

H-Bridge output terminals will be reversed. The system is automatically put into the GROUNDED state

when the boost is disabled by the BST_EN pin - for more details see Section 2.6.

Table 2-3. H-Bridge States from Inputs

HBx2 [HBL2 & HBR2]

HBx1 [HBL1 & HBR1]

H-Bridge State

OPEN

0

1

0

1

0

1

CHARGE +

CHARGE -

GROUNDED

Figure 2-11. H-Bridge States

Figure 2-12. H-Bridge States from Oscilloscope

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2.11 Power Management Core Control

Various functions of the power management core can be controlled by GPIOs of an external MCU or by

setting the default state by connecting these function pins to a logic high or low level on the PCB.

2.11.1 SLEEP / Power Control Pin Function

The internal SLEEP signal between the power management device and the MSP430 can be used to

control the power down behavior of the device. This has multiple practical applications such as a

watchdog implementation for the communication between the sender (TV) and the 3D glasses (receiver)

or different required system on and off times; typically when the push-button press timing for an off event

is a few seconds in length, programmable by software in the system MCU.

If there is a requirement that the push-button press for system on and off events are different, the SLEEP

signal must be set to a logic high value (V_SLEEP> V_IH(PMIC)) upon system startup. This implementation

allows the device to power down the system on the falling edge of the SLEEP signal

(when: V_SLEEP< V_IL(PMIC)).

Figure 2-13. SLEEP Signal to Force System Power Off

2.11.2 COMP Pin Functionality

The COMP pin is used to output a scaled down voltage level related to the battery voltage for input to a

comparator of a microcontroller. Applications for this COMP feature could be to generate an interrupt on

the microcontroller when battery voltage drops under a threshold and the device can then be shut down or

indicate to the end user with an LED that the battery requires charging.

Figure 2-14. COMP Pin Internal Connection

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Table 2-4. Scaling Resistors for COMP Pin Function

(V_VLDO= 2.2 V)

Scaling Resistors for COMP Pin

Value

Function

R_BSCL1

R_BSCL2

3.0 MΩ

2.36 MΩ

Table 2-5. Scaling Resistors for COMP Pin Function

(V_VLDO= 3.0 V)

Scaling Resistors for COMP Pin

Value

Function

R_BSCL1

R_BSCL2

3.0 MΩ

2.48 MΩ

Using the designed values in Table 2-4 or Table 2-5, the voltage on the COMP pin will be: V_COMP= 0.5 ×

V_VLDO+ 300 mV. This assures that the COMP pin voltage will be close to half of the LDO output voltage

plus the LDO dropout voltage of the device. The COMP pin can also be used as the input to an ADC

channel of an external microcontroller if greater accuracy or more functionality is desired than a simple

comparison.

2.11.3 SW_SEL Pin Functionality

The SW_SEL pin is used to select what type of switch is connected to the SWITCH pin of the device.

Selection between a push-button and a slider switch can be made based on the state of this pin.

Table 2-6. SW_SEL Settings

SW_SEL State

Type of Switch Selected

Low

Slider Switch

(V_{SW_SEL}< V_IL(PMIC)

)

High

Push-button

(V_{SW_SEL}> V_IH(PMIC)

)

When the push button switch type is selected, the device will debounce the SWITCH input with a 32 ms

timer for both the ON and OFF events and either power on or off the device. Using the push-button switch

function, the on and off timings are equal; t_ON= t_OFF. If the system requirements are such that the on and

off timings should be different, t_ON≠ t_OFF, then refer to the following section for the correct system setup:

Section 3.4. When the slider switch operation is selected, the SWITCH pin must be externally pulled up to

the SYS voltage with a resistor and the output connected to the slider switch. When the SWITCH pin is

pulled to ground, the device will turn on and enter the power up sequence.

2.11.4 SWITCH Pin

The SWITCH pin behavior is defined by the SW_SEL pin (Section 2.11.3) which defines the type of switch

that is connected to the system; either a slider switch or push-button.

2.11.5 Slider Switch Behavior

If a slider switch is connected in the system then the system power state and VLDO output (which can

power an external MCU) is defined by the state of the slider switch. If the slider is in the "off" position than

the SWITCH pin should be connected to the SYS pin. If the slider is in the "on" position than the SWITCH

pin should be connected to ground. Figure 2-15 details the system operation using the slider switch

configuration.

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Figure 2-15. SWITCH, Slider Power On-Off Behavior

2.11.6 Push-Button Switch Behavior

The system is powered on or off by a push-button press after a press that is greater than 32 ms. The

following figures (Figure 2-16 and Figure 2-17) show the system behavior and the expected VLDO output

during the normal push-button operation where the on and off press timings are the same value,

t_ON= t_OFF

.

Figure 2-16. SWITCH, Push-button Power On Behavior

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Figure 2-17. SWITCH, Push-button Power Off Behavior

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3

APPLICATION INFORMATION

3.1 Applications Schematic

Figure 3-1. TPS65735 Applications Schematic

3.2 Reducing System Quiescent Current (I_Q)

This PMU device has been optimized for low power applications. If an even lower quiescent current is

desired, the following circuit and configuration can be utilized to reduce system off / sleep quiescent

current further. Please note that this will cause a slight efficiency drop to the overall system due to the

addition of the resistance of the FET that has been added. With this circuit, achieving an I_Qof less than 1

µA is possible. Please refer to the datasheet of the MCU used in the system to determine the system I_Q

that is possible.

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Figure 3-2. Reducing System I_Qwith Addition of a FET

Along with this system configuration, the MCU code must be written such that the MCU sits in the lowest

power state that can support an interrupt on a GPIO from a switch (slider or push button). After a valid

button press or switch action, the device can begin the power on sequence and open the FET in the

previous figure (Figure 3-2). This will allow power flow into the PMU and the system can then operate

normally.

3.3 Boost Converter Application Information

3.3.1 Setting Boost Output Voltage

To set the boost converter output voltage of this device, two external resistors that form a feedback

network are required. The values recommended below (in Table 3-1) are given for a desired quiescent

current of 5 µA when the boost is enabled and switching. See Figure 3-3 for the detail of the applications

schematic that shows the boost feedback network and the resistor names used in the table below.

Figure 3-3. Boost Feedback Network Schematic

APPLICATION INFORMATION

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Table 3-1. Recommended R_FB1and R_FB2Values (for I_Q(FB)= 5 µA)

(1)

Targeted V_{BST_OUT}

R_FB1

R_FB2

8 V

1.3 MΩ

1.8 MΩ

2.2 MΩ

2.4 MΩ

3.0 MΩ

240 kΩ

10 V

12 V

14 V

16 V

(1) Resistance values given in closest standard value (5% tolerance, E24 grouping).

These resistance values can also be calculated using the following information. To start, it is helpful to

target a quiescent current through the boost feedback network while the device is operating (I_Q(FB)). When

the boost output voltage and this targeted quiescent current is known, the total feedback network

resistance can be found.

The value for R_FB2can be found by using the boost feedback pin voltage (V_FB= 1.2 V, see "Electrical

Characteristics" in Section 2) and I_Q(FB)in the following equation:

R_FB1+ R_FB2= V_{BST_OUT}/ I_Q(FB)

R_FB2= (1.2 V) / I_Q(FB)

To find R_FB1, simply subtract the R_FB2from R_FB(TOT)

R_FB1= R_FB(TOT)- R_FB2

:

3.3.2 Boost Inductor Selection

The selection of the boost inductor and output capacitor is very important to the performance of the boost

converter. The boost has been designed for optimized operation when a 10 µH inductor is used. Smaller

inductors, down to 4.7 µH, may be used but there will be a slight loss in overall operating efficiency. A few

inductors that have been tested and found to give good performance can be found in the list below:

Recommended 10 µH inductors

•

TDK VLS201612ET-100M (10 µH, I_MAX= 0.53 A, R_DC= 0.85 Ω)

Taiyo Yuden CBC2016B100M (10 µH, I_MAX= 0.41 A, R_DC= 0.82 Ω)

3.3.3 Boost Capacitor Selection

The recommended minimum value for the capacitor on the boost output, BST_OUT pin, is 4.7 µF. Values

that are larger can be used with the measurable impact being a slight reduction in the boost converter

output voltage ripple while values smaller than this will result in an increased boost output voltage ripple.

Note that the voltage rating of the capacitor should be sized for the maximum expected voltage at the

BST_OUT pin.

3.4 Bypassing Default Push-Button SWITCH Functionality

If the SWITCH pin functionality is not required to power on and off the device because of different system

requirements (when the SWITCH timing requirements of system will be controlled by an external

microcontroller), then the feature can be bypassed. The following diagram shows the connections required

for this configuration, note that INT. I/O refers to an interruptible I/O on the microcontroller.

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Figure 3-4. Bypassing Default TPS65735 Push Button SWITCH Timing

In a system where a different push-button SWITCH off timing is required, the SLEEP pin is used to control

the power off of the device. After system power up, the MCU must force the SLEEP pin to a high state

(V_SLEEP> V_IH(PMIC)). Once the SWITCH push-button is pressed to shut the system down, a timer in the

MCU should be active and counting the desired t_OFFtime of the device. Once this t_OFFtime is detected,

the MCU can assert the SLEEP signal to a logic low level (V_SLEEP< V_IL(PMIC)). It is on the falling edge of

the SLEEP signal where the system will be powered off (see Figure 3-5)

Figure 3-5. SWITCH Press and SLEEP Signal to Control System Power Off

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PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS65735RSNR

QFN

RSN

32

3000

330.0

12.4

4.3

1.5

8.0

12.0

Q2

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

22-Jun-2011

*All dimensions are nominal

Device

Package Type Package Drawing Pins

QFN RSN 32

SPQ

Length (mm) Width (mm) Height (mm)

340.5 338.1 20.6

TPS65735RSNR

3000

Pack Materials-Page 2

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型号：	TPS65735_16
厂家：	TEXAS INSTRUMENTS
描述：	PMU for Active Shutter 3D Glasses
文件：	总36页 (文件大小：1684K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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