TPS658629IZWSRQ1 [TI]
汽车类 2.3V 至 5.5V, 电源管理 IC，具有 3 个降压转换器和 11 个 LDO | ZWS | 169 | -40 to 85;
| 型号： | TPS658629IZWSRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 2.3V 至 5.5V, 电源管理 IC，具有 3 个降压转换器和 11 个 LDO | ZWS | 169 | -40 to 85 转换器 |
| 文件： | 总98页 (文件大小：3838K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS658629-Q1
www.ti.com.cn
ZHCS099A –JUNE 2011–REVISED JUNE 2012
高级电源管理单元
查询样品: TPS658629-Q1
1 介绍
1.1 主要特性
1
• 符合汽车应用要求
• 主机接口
• 具有下列结果的 AEC-Q100 测试指南：
– 带有可屏蔽中断的中断控制器
– 器件温度 3 级：-40°C 至 85°C 的环境运行温度
范围
– 外部模数转换器 (ADC) 触发和降压转换器模式控
制
– 器件人体模型 (HBM) 静电放电 (ESD) 分类等级
• 系统管理
H1C
– 双输入电源路径
– 器件充电器件模型 (CDM) ESD 分类等级 C2
• 集成电源
•
•
USB 电流感测
最大 18V 过压保护
– 3 个可编程降压转换器
– 所有电源输出上的电源良好监控
– 软件复位功能
– 硬件打开/关闭和重新引导控制
– AUTOBOOT（重新引导）支持
– 11 个通道模数转换器 (ADC)，每一个都有 3 个
运行模式
•
•
•
•
受软件控制的使能/强制脉宽调制 (PWM) 模式
自动节能模式
最大 1.5A 输出（SM0 和 SM2）
最大 1.3A 输出 (SM1)
– 11 个可编程的通用低压降稳压器 (LDO)
•
•
其中 7 个的输出电压介于 1.25V 至 3.3V 之间
其中 2 个的输出电压介于 0.725V 至 1.5V 或
者 1.25V 至 2.586V 之间（厂家可配置）
•
•
•
单一转换
峰值检测
取平均值
•
1 个“常开”，输出电压介于 1.25V 至 3.3V 之
间
1.2 应用范围
•
1 个的输出电压介于 1.7V 至 2.475V 之间
•
•
便携式导航设备
• 显示支持功能
便携式媒体播放器
– 4 个带有可设定频率和占空比的 PWM 输出
– 双 RGB 发光二级管 (LED) 驱动器
– 恒定电流白光发光二级管 (WLED) 驱动器
•
•
•
25mA 时为 26.5V（最大值）
过压保护
可编程电流电平和亮度控制
1.3 说明
TPS658629-Q1 在一个小型封装内为手持器件、集成型多稳压电源、系统管理和显示功能提供了一个易于使
用、完全集成的解决方案。 I2C 接口实现了对于宽范围子系统参数的控制。 内部寄存器存有状态信息的完整
集合，从而实现了对故障状态的简便诊断和主机控制处理。
如需完整数据表，请发电子邮件到msapmu_contact@list.ti.com索取。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
版权 © 2011–2012, Texas Instruments Incorporated
English Data Sheet: SLVSAT6
TPS658629-Q1
ZHCS099A –JUNE 2011–REVISED JUNE 2012
www.ti.com
1.4 订购信息(1)
封装
标识符
TA
部件号(2) (3)
封装(4)
订购(2)
封装标识
TPS658629I
-40°C 至 85°C
TPS658629
169 引脚细间距球
状引脚栅格阵列
(nFBGA)
ZWS
TPS658629IZWSRQ1
(1) 要获得最新的封装和订购信息，请参见本文档末尾的封装选项附录，或者访问德州仪器 (TI) 的网站 www.ti.com。
(2) TPS658629 只提供卷带封装。 数量为每卷 1000 个器件。
(3) 具有唯一部件号的器件有针对电源缺省、排序和其它功能的唯一出厂配置。 针对每个部件的配置信息请查阅此配置。
(4) 这个产品与 RoHS 标准兼容，其中包括铅浓度不超过产品总重量的 0.1%，并且适合应用于特定的无铅焊接工艺中。 此外，这个产品使用
不包含卤素的封装材料，包括溴 (Br) 或者锑 (Sb) 高于产品总重量的 0.1%。
2 ELECTRICAL SPECIFICATIONS
2.1 ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
VALUE / UNITS
AC and USB with respect to AGND1
–0.3 V to 18 V
–0.3 V to 6.5 V
–0.3 V to 6.5 V
–0.3 V to 6.5 V
–0.3 V to 3.6 V
–5.5 V to 3.6 V
–0.3 V to 3.6 V
–0.3 V to 3.6 V
–0.3 V to 3.6 V
–2.3 V to 0.3 V
–0.3 V to 6.5 V
–0.3 V to 6.5 V
–0.3 V to 6.5 V
–0.3 V to 29 V
–0.3 V to 29 V
–0.3 V to 0.5 V
–0.3 V to 5.5 V
–0.3 V to 6.5 V
–0.3 V to +0.3 V
Defined by ILIM
Defined by ILIM
2500 mA
ANLG1, ANLG2, ANLG3 with respect to AGND2
V(SYS) with respect to AGND1
VIN_LDO01, VIN_LDO23, VIN_LDO4, VIN_LDO678, VIN_LDO9 with respect to AGND1
ADC_REF with respect to AGND2
RTC_OUT with respect to V(SYS)
RTC_OUT with respect to AGND1
LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9, V2V2 and TS with respect to AGND1
V32K with respect to AGND1
TS with respect to V2V2
SM0, L0, VIN_SM0 with respect to PGND0
SM1, L1, VIN_SM1 with respect to PGND1
SM2, L2, VIN_SM2 with respect to PGND2
SM3 , L3 with respect to PGND3
SM3SW with respect to PGND3
FB3 with respect to PGND3
V(BAT) with respect to AGND1, Battery power only
All other pins (except AGNDn and PGNDn) with respect to AGND1
AGND2, AGND3, , DGND1, DGND2DT, PGND0, PGND1, PGND2, PGND3 with respect to AGND1
Input Current, AC pin
Input Current, USB pin
Output continuous current, SYS, VIN_CHG pins
Output continuous current, BAT pin
–3000 mA
Continuous Current at L0, PGND0, L1, PGND1
Continuous Current at L3, PGND3
1500 mA
1000 mA
Continuous Current at L2, PGND2
2000 mA
Operating free-air temperature, TA
–40°C to 85°C
125°C
Maximum junction temperature, TJ
Storage temperature, TSTG
–65°C to 150°C
2000 V
ESD (Human Body Model) rating , all pins
ESD (Charged-Device Model) rating, all pins
ESD (Machine Model) rating, all pins
250 V
150V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
ELECTRICAL SPECIFICATIONS
Copyright © 2011–2012, Texas Instruments Incorporated
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
2.2 THERMAL INFORMATION
ZWS
UNITS
THERMAL METRIC
169 PINS
θJA
Junction-to-ambient thermal resistance(1)
Junction-to-case (top) thermal resistance(2)
Junction-to-board thermal resistance(3)
33.1
8.8
θJCtop
θJB
18
°C/W
0.2
ψJT
Junction-to-top characterization parameter(4)
Junction-to-board characterization parameter(5)
Junction-to-case (bottom) thermal resistance(6)
ψJB
17
θJCbot
n/a
(1) 在 JESD51-2a 描述的环境中，按照 JESD51-7 的规定，在一个 JEDEC 标准高 K 电路板上进行仿真，从而获得自然对流条件下的结至环
境热阻抗。
(2) 通过在封装顶部模拟一个冷板测试来获得结至芯片外壳（顶部）的热阻。 不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI 标准 G30-
88 中找到内容接近的说明。
(3) 按照 JESD51-8 中的说明，通过在配有用于控制 PCB 温度的环形冷板夹具的环境中进行仿真，以获得结至电路板的热阻。
(4) 结至顶部的特征参数，( ψJT)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第 7 章）中描述的程序从仿真数据中提取出该
参数以便获得 θJA
(5) 结至电路板的特征参数，(ψJB)，估算真实系统中器件的结温，并使用 JESD51-2a（第 6 章和第7 章）中描述的程序从仿真数据中提取出该
参数以便获得 θJA
。
。
(6) 通过在外露（电源）焊盘上进行冷板测试仿真来获得结至芯片外壳（底部）热阻。 不存在特定的 JEDEC 标准测试，但可在 ANSI SEMI
标准 G30-88 中找到了内容接近的说明。
2.3 DISSIPATION RATINGS
T
A ≤ 25°C
TA = 55°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
PACKAGE
Psi_Jb
POWER RATING
ZWS(1)
20°C/W
5000 mW
3500 mW
2750 mW
2000 mW
(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a via matrix.
2.4 RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
4
MAX
16.5(1)
5.5
UNIT
AC and USB with respect to AGND1
V(SYS) with respect to AGND1
V
V
V
V
2.9
2.9
2.15
V(BAT) with respect to AGND1, battery power only
3.25
4.6
V(BAT) with respect to AGND1, battery connected, AC or USB
power selected, Selected power source >2.9 V
ANLG1,ANLG2, ANLG3 with respect to AGND2
0
2.6
5.5
V
V
Greater of : 1.7 V OR Minimum input voltage
required for LDO/Converter operation outside
dropout region
VIN_LDO01, VIN_LDO23, VIN_LDO678, VIN_LDO4, VIN_LDO9
with respect to AGND1
Greater of : 2.3 V OR Minimum input voltage
required for LDO/Converter operation outside
dropout region. 2.9 V to meet parametric
specifications.
VIN_SM0 with respect to PGND0
5.5
V
VIN_SM1 with respect to PGND1
5.5
5.5
V
V
VIN_SM2 with respect to PGND2
SM3 with respect to PGND3
28
V
GPIOx with respect to AGND1
0
5.5
V
All other pins (except AGNDn and PGNDn) with respect to AGND1
Operating free-air temperature, TA
0
-40
5.5
V
85
°C
°C
°C
Maximum junction temperature, TJ , functional operation
Maximum junction temperature, TJ , electrical characteristics
External supply ramp rate, AC or USB pins
-40
125
0
125
1 V/mSec
1 V/μSec
(1) Thermal operating restrictions are reduced or avoided if input voltage does not exceed 5 V.
Copyright © 2011–2012, Texas Instruments Incorporated
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ELECTRICAL SPECIFICATIONS
3
Product Folder Link(s): TPS658629-Q1
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
www.ti.com
2.5 ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
QUIESCENT CURRENT – V(BAT) = 4.2V NO EXTERNAL LOADS AT SYS PIN OR SUPPLY OUTPUTS
Quiescent current, 6586x in normal or sleep
IQ(ON)
Power path active, control logic in low power mode(1)
260
375
μA
mode. All supplies and peripherals off
IQ(DIGITAL)
Quiescent current, control logic
Control logic in high power mode(2)
584
716
14
19
6
870
25
μA
μA
μA
mA
SM0, SM1: enabled, PFM mode, from SYS pin
SM2: enabled, PFM mode, from SYS pin when Vout=3.3V
SM0, SM1, SM2: enabled, PWM mode, from VINSMn pin
32
IQ(SMn)
SM0, SM1, SM2 operating quiescent current
disabled via I2C
1
μA
I(LDOx) = no external load
I(LDOx) = –1 mA
24
24
160
1
29
μA
μA
μA
μA
μA
μA
150
LDO quiescent current, All but one LDOx
disabled
IQ(LDOx)
I(LDOx) = –50 mA
LDO disabled, TJ = 85°C
SM3 enabled, not switching
Enabled, switching
3
30
15
200
IQ(SM3)
SM3 operating quiescent current(3)
ADC operating quiescent current
Disabled via I2C
1
μA
Conversion active
1
mA
Not converting, waiting for trigger
170
μA
IQ(ADC)
ADC disabled via I2C
1
μA
μA
RTC_OUT LDO enabled
27
45
15
IQ(RTC)
RTC_OUT pin quiescent current
RTC_OUT disabled via I2C, TJ = 85°C . Externally applied(4)
V(RTC_OUT) = 2 V supplies real time clock counters and xtal oscillator
μA
32k buffer enabled, 100 pF external load
Disabled via I2C
24
8
μA
μA
IQ(V32K)
V32K supply bias current , 32k buffer enabled
I2C INTERFACE TIMING – SDA, PSDA, PSCLK, SCLK(3)
tR
SCLK/SDATA rise time
SCLK/SDATA fall time
300
300
ns
ns
ns
μs
ns
ns
tF
tW(H)
tW(L)
tSU(STA)
tH(STA)
SCLK pulse width high
SCLK Pulse Width Low
Setup time for START condition
600
1.3
600
600
START condition hold time after which first clock
pulse is generated
Pull-up resistors connected to 2.2V
tSU(DAT)
tH(DAT)
Data setup time
100
0
ns
ns
ns
Data hold time
tSU(STOP)
Setup time for STOP condition
600
Bus free time between START and STOP
condition
t(BUF)
FSCL
1.3
μs
Clock Frequency
400
0.4
kHz
I2C BUFFERS – SDA, PSDA, PSCLK, SCLK
VIL(I2C)
VIH(I2C)
VOL(I2C)
IO(I2C)
Low level input voltage
High level input voltage
Low level output voltage
Maximum load current(3)
Input current
V
V
1.15
SDA, PSDA configured as output, IOL=3mA
SDA, PSDA configured as output
V(pin) = 5V or 0V
0.4
8
V
mA
μA
pF
pF
ILKG(I2C)
CI2C
1
Input pin capacitance
SDAT, SCLK, PSDAT, PSCLK pins
SDAT, SCLK, PSDAT, PSCLK
10
I2C bus capacitance
CI2CBUS
400
(1) Control logic in low power mode when all functions are off and no I2C communication is on going
(2) Control logic in high power mode when one of the following events happen: 6586x in power-up/rtc/rtc_on/supplyseq states, any
converter in PWM mode, SM3 enabled, PWM driver enabled, ADC conversion on-going, I2C communication on-going, voltage transition
for DVM supplies on-going, AC or USB supply detected.
(3) Not production tested.
(4) External voltage supplied by supercap or coin cell connected to RTC_OUT pin, see application diagram for details.
4
ELECTRICAL SPECIFICATIONS
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Product Folder Link(s): TPS658629-Q1
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUT BUFFERS: RESUME, SM0EN, SM1EN, HOTRST, LDO4EN, SYNCEN
VIL(DIG)
VIH(DIG)
ILKG(DIG)
Low level input voltage
High level input voltage
Input current
0.4
V
V
1.15
V(pin) = 5V
0.1
150
175
μA
RESUME pin , pull-down to AGND
HOTRST pin, pull-up to V2V2
55
55
100
100
RDIG
Internal resistor
kΩ
PUSH-PULL OUTPUT BUFFERS, USER SELECTABLE OUTPUT VOLTAGE – NORTC, NOPOWER
VBFRPWR
Buffer positive supply
Internally connected to V32K pin
IOL = 3 mA, V32K = 1.5 V
IOL = 10 μA, V32K > 1.1 V
IOH = 1.4 mA, V32K = 1.5 V
IOH = -10 μA, V32K = 1.1 V
IOH = 1.4 mA, V32K = 1.5 V
IOH = -10 μA, V32K = 1.1 V
V(pin) = 2.5 V
1.1 to 3.3
V
V
0.6
0.1
VOL(OBFR)
Low level output voltage
V32K-0.6
V32K-0.11
V32K-0.6
High level output voltage, referenced to output
buffer supply, NORTC
VOH(OBFR)
V
V
High level output voltage, referenced to output
buffer supply,NOPOWER
VOH(OBFR)
V32K-0.11
IOL(OBFR)
IOH(OBFR)
Maximum low level sink current load(1)
Maximum high level source current load(1)
5
mA
mA
V(pin) = 0 V
–5
OPEN DRAIN OUTPUT BUFFERS – INT
IOL = 3 mA, V32K = 1.5 V
0.6
0.1
0.1
VOL(OBFR)
Low level output voltage
V
IOL = 10 μA, V32K > 1.1 V
ILKG(OBFR)
Output leakage current
Output buffer, open-drain mode, V(pin)=5.5V
μA
PUSH-PULL OUTPUT BUFFERS – LDO4PG, SM0PG, SM1PG
IOL = 3 mA
0.6
0.1
VOL(DBFR)
Low level output voltage
V
V
IOL = 10 μA
IOH = 3 mA
IOH = –10 μA
V(pin) = 2.5 V
V(pin) = 0 V
1.5
1.8
High level output voltage , buffer configured as
push-pull via I2C
VOH(DBFR)
IOL(DBFR)
IOH(DBFR)
Maximum low level sink current load(1)
Maximum high level source current load(1)
5
mA
mA
–5
32kHz OUTPUT BUFFER , V(32K)=1.7V (min), UNLESS OTHERWISE STATED
V32B
Externally applied bias rail for output driver(1)
Buffer supply voltage
V(32K) = 1.1 V, IOL = 100 μA
V(32K) = 1.1 V, IOL = 1 mA
V(32K) = 1.5 V, IOL = 5 mA
V(32K) = 1.1 V, IOH = -1 μA
V(32K) = 1.5 V, IOH = 5 mA
32 kHz clock driving 50pF load cap
Peak to peak
1.0
3.6
0.05
0.2
V
V
VOL
Output low level
0.5
V32K-0.05
V32K-0.5
VOH
Normal operation
Rise/fall time
Output jitter
V
tF, tR
VJITTER
15
15
15
ns
ns
RMS
32kHz CLOCK AND 32K SWITCHING TIMING
Frequency within 2% of typical value, frequency defined by XTAL
characteristics
tXTAL
F32K
XTAL oscillator stabilization time(1)
Internal 32 kHz clock
320
36
ms
Frequency
28
32
kHz
INTERNAL REFERENCES AND POR
UVLO
Internal UVLO detection threshold
V(2V2) decreasing
-3%
1.85
120
2.2
3%
2.3
V
mV
V
VUVLO_HYS
VO(2V2)
ISH2V2
UVLO detection hysteresis
Output Voltage
V(2V2) increasing from decreasing trigger point
Always on,
V(2V2) = 0V
2.1
18
Short Circuit current limit
mA
(1) Not production tested.
Copyright © 2011–2012, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
5
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Product Folder Link(s): TPS658629-Q1
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
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2.6 ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RTC_OUT LDO
VO(RTC_OUT)TYP=1.25, 1.50, 1.8, 2.5,
Output Voltage, Selectable via I2C(1)
V
2.7,2.85,3.1,3.3
Dropout voltage, I(RTC_OUT) = –15 mA
V(SYS) = 2.8 V
600
mV
Total accuracy, V(AC):2V to 4.7V, –15mA load,
V(BAT1)=V(BAT2)=V(USB)=0V
VO(RTC_OUT)
RTC_OUT output voltage
Short Circuit current limit
–5%
5%
Load regulation, V(AC)=3.5V,
load: 1mA → –15mA
1%
1%
Line regulation, 5mA load,V(AC): 3.5V→18V,
V(BAT1) =V(BAT2) =V(USB) =0V
ISHRTC
20
2.3
mA
V
2.35
1.9
75
2.45
2
RTC_OUT power good fault detection
threshold
Falling RTC_OUT pin voltage, set via I2C
V(RTCGOOD)
1.8
VHYS(RTC)
Power good fault detection hysteresis
Internal RTC UVLO detection threshold
UVLO detection hysteresis
Rising RTC_OUT pin voltage (Referenced to V(RTCGOOD) threshold)
50
145
10%
200
mV
V
VUVLO_RTC
VRTC Decreasing
VRTC Increasing
–10%
100
1.5
150
VUVLO_RTC_HYS
BOOT-UP TIMING
tPOR
mV
Power-on-reset delay(2)
Boot-up time
Fixed time, measured from 2V2 > UVLO
7.2
8
8.8
ms
ms
Fixed time
75
tBOOT
Accuracy, referenced to tBOOT(tTYP)
Fixed time
–10%
675
225
2.7
10%
825
275
3.3
tHOTPLUG
tWAKEUP
tCHECK
tMAX
Hot plug deglitch time
Wakeup pulse width
RTC check wait time
RTC_ON watchdog timer
750
ms
μs
Fixed time
250
Fixed time
3
4×TNORTC
10
ms
ms
Fixed time
Fixed time
tNORTC
NORTC pin pulse width value
ms
(3)
Accuracy, relative to tNORTC
–10%
10%
(TYP)
tNOPOWER = KNOPOWER × CNOPOWER
Pulse width accuracy, CNOPOWER < 400nF
Fixed time
0.25
KNOPOWER
NOPOWER pin pulse width const.
Reboot and sleep request timeout
ms/nF
–25%
18
25%
22
tWAIT
20
5
ms
ms
ms
tWAIT1
4.5
5.5
5.5
tSYNCEND
Synchronization complete delay
Supply sync delay time
Measured from all supplies synchronized
Regulator specific. See Table 3-10
4.5
5
TSYNCDLY(TYP) = 1.25, 2.5, 3.75, 15,
20, 32, 40, 64
TSYNCDLY
ms
(3)
Accuracy, relative to TSYNCDLY(TYP)
-10
+10
POWER GOOD AND THERMAL FAULT DETECTION
Applies to all non-masked power good signals, output voltage
falling edge.
tDGL(PGFLT)
Power good deglitch time
4
5
6
ms
tSHUT
Thermal shutdown
Increasing junction temperature
Decreasing junction temperature
Rising temperature
150
30
°C
°C
μs
tHYS(SHUT)
tDGL(TSHUT)
Thermal shutdown hysteresis
Thermal shutdown detection delay
15
20
25
(1) Setting the RTC_OUT output voltage below the RTC_OUT power good threshold will result in a NORTC pulse being always generated
during reboot cycles or when exiting sleep.
Setting the RTC_OUT output voltage below VUVLO_RTC disables the use of the internal real time clock counter and xtal oscillator.
(2) Not production tested.
(3) Not production tested.
6
ELECTRICAL SPECIFICATIONS
Copyright © 2011–2012, Texas Instruments Incorporated
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESUME CONTROL TIMING
tRESUME(H)
tRESUME(L)
RESUME pulse width high(1)
RESUME pulse width low(1)
550
220
ms
ms
SEQUENCER REBOOT CONTROL
Reboot started when normal state is set and
V(HOT_RST) < VREBOOT for
t > TDT(HRST)
VHOTRST
Reboot control threshold
0.4
V
THRST(H)
HOT_RST max pulse width
60
16
ms
TDT(HRST)
HOT_RST min detection pulse width
HOT_RST deglitch
4
μs
EXTERNAL SUPPLY DETECTION AND STATUS
System voltage V(SYS) decreasing.
Total accuracy, referenced to V(LOWSYS)TYP
2.8
V
%
VLOWSYS
Minimum system voltage detection threshold
-2
2
VHYS(LOWSYS)
TDGL(LOWSYS)
Minimum system voltage detection hysteresis V(SYS) increasing from decreasing trigger point
200
5
mV
Minimum system voltage detection deglitch
V(SYS) decreasing
time
ms
Input voltage detection threshold. Input voltage AC detected when V(AC) – V(BAT) > VIN(DT) AND V(AC) > VACMIN
VIN(DT)
180
mV
increasing, referenced to battery voltage
USB detected when V(USB) – V(BAT) > VIN(DT)
AC not detected:
when V(AC) – V(BAT) < VIN(NDT) USB not detected when V(USB) –
V(BAT) < VIN(NDT)
Input voltage removal threshold. Input voltage
decreasing, referenced to battery voltage
VIN(NDT)
65
mV
V
AC voltage increasing , AC not detected when V(AC) < VACMIN
AC voltage decreasing , AC not detected when V(AC) < VACMIN
Hysteresis
3.5
3.3
3.8
3.6
VACMIN
AC detection threshold, relative to GND
185
40
mV
ms
ms
ms
V
tACSYS
AC threshold to SYS delay
AC Power detected deglitch
USB Power detected deglitch
Input over voltage detection
Input over voltage detection delay
AC=3.8V to SYS=HIGH
50
tDGLAC(DT)
tDGLUSB(DT)
VIN(OVP)
AC voltage increasing
22.5
5.5
USB voltage increasing
5.8
6.0
6.3
tDLY(INOVP)
Rising AC or USB voltage
Enabled at sleep mode
100
μs
ANALOG COMPARATOR
VCOMP
Voltage threshold
1.21
1.245
50
1.28
0.1
V
ILK(COMP)
COMP pin leakage current(1)
μA
V(COMP):0→1.5V→0, measured from input to
NOPOWER:HI→LO
tP
Propagation time
μs
(1) Not production tested.
Copyright © 2011–2012, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
7
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2.7 ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER PATH CURRENT LIMIT AND PROTECTION FUNCTIONS
–40°C < TA < 85°C
–25°C < TA < 85°C
85
92
100
100
Selected Input switch not in dropout. I2C
settings: USBMODE=HI, USBLIMIT=LO
IUSB100
mA
Selected input current limit, applies to USB input
only
Selected Input switch not in dropout. I2C settings: USBMODE=HI,
USBLIMIT=HI
IUSB500
380
500
mA
A
Input current limit range, AC input
2.75
2.11
Selected input current limit, applies to AC input
Selected input current limit, applies to USB input
Total accuracy, relative to IINLIM(TYP)
–20%
20%
IINLIM
Input current limit range, USB input configured with USBMODE=LO
Total accuracy, relative to IINLIM(TYP)
A
–12.5%
12.5%
Load at SYS pin: 80% of current limit value to 120% of regulation value
(IINLIM, IUSB100 or IUSB500). Time measured from load transient to input current
within regulation limits.
tOVSH
Input current limit transient time
20
μs
Load at SYS pin: 80% of current limit value to 120% of regulation value
IOVSHPKUSB Input current limit overshoot
(IINLIM, IUSB100 or IUSB500),
t < TOVSH
20%
VSH(SYS)
RFLT(USB)
RFLT(AC)
IBATSYS
SYS power path Short Circuit detection threshold
All power path switches set to OFF if V(SYS) < VSH(SYS)
V(SYS) < VSH(SYS), internal resistor connected from USB to SYS
V(SYS) < VSH(SYS), internal resistor connected from AC to SYS
1.6
1.8
550
550
2.0
V
Ω
Ω
A
SYS short circuit recovery pull-up resistor
SYS short circuit recovery pull-up resistor
Battery Switch over-current detection
3.0
6.0
Short circuit detection blanked for TDGL(BATSYS), measured from batt
switch: OFF->ON or initial sys power path enable
100
110
1
120
ms
ms
mA
tDGL(BATSYS) Battery Switch over-current detection delay
Battery switch already turned on or sys power path enabled
Battery Switch over-current recovery pull-up current V(BAT) –V(SYS) > VOC(SYS), internal current source connected from BAT to
IFLT(SYS)
30
source
SYS
VSUP(SYS)
Supplement detection threshold
Battery switch ON at V(BAT)-V(SYS) > VSUP(SYS)
Battery switch OFF at V(BAT)-V(SYS)<VSUPNDT(SYS)
40
7
mV
mV
VSUPNDT(SYS) Supplement mode not detected threshold
POWER PATH INTEGRATED MOSFETS CHARACTERISTICS
VACDO = V(AC)-V(SYS); V(AC)=4V AC input current limit set to 2.0A (typ)
IO(SYS) = 1.0A
VACDO
AC switch dropout voltage
USB switch dropout voltage
190
mV
mV
mV
I(SYS)+I(BAT)= 0.425A
240
240
VUSBDO = V(USB)-V(SYS);
VUSBDO
V(USB)=4.6V
I(SYS)+I(BAT)= 85mA
VBATDODCH = V(BAT)-V(SYS), V(BAT)=3V,
I(BAT)= 1A
VBATDODCH Battery Switch dropout voltage, discharge
40
155
POWER PATH TIMING CHARACTERISTICS
tSW
tSW
Switching from AC to BAT
Switching from USB to BAT
No USB, AC power removed
No AC, USB power removed
150
150
μs
μs
POWER PATH DISCHARGE SWITCHES
IDCH(AC)
AC pin discharge current
USB pin discharge current
Always ON, V(AC) > 1 V
Always ON, V(USB) > 1 V
100
100
μA
μA
IDCH(USB)
SM0, SM1, SM2 DC/DC CONVERTERS
Converter turned OFF at V(VIN_SMn) < VSMUV
Hysteresis , rising input voltage
2.0
V
Low input voltage detection threshold, input voltage
decreasing
VSMUV
100
200
200
mV
mΩ
mΩ
μA
High side MOSFET on-resistance
Low side MOSFET on-resistance
High side leakage current
VIN_SMx = 3.6V, 100% duty cycle
VIN_SMx = 3.6V, 0% duty cycle
RDS(ON)
ILK_HS
ILK_LS
1
1
TJ = 85°C
Low side leakage current
μA
SM0
1550
1550
1300
2.025
2400
2400
1900
2.25
mA
ILIM
High side and low side current limit
2.9V ≤ VIN_SMx ≤ 5.5V
SM1
SM2
fSW
Oscillator frequency
PWM mode
2.475
MHz
Power fault detection, Voltage decreasing, referenced to programmed
output voltage
–13.0%
–10% –7.0%
5%
VSMPG
Power good threshold
Hysteresis, voltage increasing, referenced to VSMPG
8
ELECTRICAL SPECIFICATIONS
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SM0, low range, 25mV
steps
VO(SMx)TYP = 0.725 to 1.50
VO(SMx)TYP = 0.725 to 1.50
VO(SMx)TYP = 3 to 4.55
SM1, low range, 25mV
steps
Adjustable output voltage range, Selectable via I2C
VIN_SMx = 2.9V to 5.5V
V
SM2, low range, 25mV
steps
VO(SMx)
VIN_SMx = 2.9V to 5.5V, PFM mode
–1%
–2%
1%
3%
2%
Output Voltage Accuracy, relative to VO(SMx)TYP
VIN_SMx = 2.9V to 5.5V, PWM mode, 0mA < IOUT< 1A
PWM mode, VIN_SMn>2.7V, Load<1A
DC output voltage load regulation
DC output voltage line regulation
0.25
0.1
%/A
%/V
VIN_SMx = VOUT + 0.5V (min. 2.5V), PWM mode VIN_SMn>2.7V, Load<1A
SM0, SM1: typical
values:Instantaneous, 0.11,
0.22, 0.44, 0.88, 1.76, 3.52,
7.04
Value set via I2C, available options:
KRAMP(SMx) Voltage change ramp constant
mV/μs
Time to start switching, measured from end of I2C command enabling
converter
tStart
Start-up time
210
μs
tRamp
RDCH
VOUT Ramp UP time
Time to ramp from 5% to 95% of VOUT
SMx disabled
250
250
μs
Discharge switch resistance
Ω
VIN_SM
x/
IPFM(ENTER) Load current to enter PFM mode
VIN_SMx = 2.9V to 5.5V, duty cycle > 85%
A
34Ω
CLC
External LC capacitor(1)
External LC inductor(1)
External Input capacitor(2)
4.7
1.5
10
22
μF
μH
μF
LLC
4.7
47
CSMINP
LDO’S : LDO0, LDO1, LDO2, LDO3, LDO4, LDO5, LDO6, LDO7, LDO8, LDO9
Electrical characteristics over the output current range IO(LDOx)
Electrical characteristics specified , max load current = 75mA
2.3
1.7
5.5
5.5
VINMIN
IO
Input voltage range(2)
Output current(2)
V
300
mA
Available output voltages:
V(LDO6)TYP = 1.20 (LDO0
only), 1.25, 1.5, 1.8, 2.5, 2.7,
2.85, 3.1,3.3
Output Voltage, Selectable via I2C. LDO6, LDO0, LDO3, LDO5,
LDO7,LDO8,LDO9
V
LDO1 Output Voltage, Selectable via I2C
LDO4 Output Voltage, Selectable via
Low range, 25mV steps
V(LDO1)TYP = 0.725 to 1.5
V(LDO4)TYP = 1.7 to 2.475
V(LDO2)TYP= 0.725 to 1.5
High range, 25mV steps
Low range, 25mV steps
V
LDO2 Output Voltage, Selectable via I2C
Dropout, V(IN) = V(LDOx)TYP - 0.1V , V(IN) = 2.3V, 250mA load. 1 LDO active at
a time per input pin group(3)
415
mV
LDOx Output Voltage, Selectable via I2C
V(LDOx)
(4)
Total accuracy, V(VIN_LDOx) = V(LDOx)TYP + 0.5V, 10mA → 250 mA
See
3.5%
0.5%
Line Regulation, 100mA load, V(VIN_LDOx)
:
–0.5%
V(LDOx) TYP + 0.5V→ 4.7V
Load regulation, load change from 10mA → 250 mA
V(VIN_LDOx) > V(LDOx) TYP + 0.5V
(5)
See
%
250mA load, 1V input to output ,CL = 4.7 μF
100mA load, 0.5V input to output, CL = 1 μF
40
40
PSRR
PSRR at 20 kHz
dB
ISC
Short circuit current limit
Discharge resistor
Output grounded
LDOnILIM=HI
310
1
700
mA
Ω
RDCH
KRAMP
LDOx disabled
415
Voltage change ramp constant
LDO2, LDO4 only. Fixed value, hardwired at top level
7.04
mV/μs
μF
load <100 mA
load>100 mA
CCOMP
External output capacitor value(2)
Stable operation
0.01μF/mA, min cap value =
1μF
Power good threshold
Hysteresis
LDO output voltage increasing
95%
5%
PGOOD
Decreasing voltage from increasing trigger
(1) Not production tested
(2) Not production tested
(3) Dropout not measured for devices with V(IN)<2.3V because minimum VIN is 2.3V
(4) MIN = –3.2 – (0.105 × ILOAD / V(LDOX)TYP), ILOAD = load current in amps
(5) MIN = –2.5 – (0.105 × ILOAD, ILOAD = load current in amps
Copyright © 2011–2012, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
9
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
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2.8 ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SM3 BOOST CONVERTER – CONTROL CIRCUIT AND POWER STAGE
VVIN(SM3)
VO(SM3)
V(OVP3)
Input Voltage range(1)
Output voltage range(1)
Output over-voltage trip
V(VIN)
2.5
VVIN(SM3)
26.5
6.5
26.5
29
V
V
V
V(SM3)
OVP detected at V(SM3) > V(OVP3) rising
28
OVP not detected at
V(SM3) < V(OVP3) – VHYS(OVP3)
VHYS(OVP3)
Output over-voltage hysteresis
FB3 voltage sense threshold(1)
1.8
V
238
248
258
mV
V
V(SM3REF)
V(FB3) below regulation point at V(FB3) < V(SM3REF)
1.237
1.25
1.263
V
(SM3REF)
FB3
IO(SM3)
LED current(1)
0
25
mA
I
O(SM3)
=
R
Current range,
D(SM3SW) = 0% to 99.96%, set via I2C,
2048 steps 0.05% minimum step
LED switch duty cycle, selectable via I2C
D(SM3SW)
Duty cycle range
%
2048 pulses within repetition rate time, repetition rate set via
I2C
F(REP_SM3)TYP = 550Hz, 366Hz, 275Hz
or 220Hz
Hz
LED switch duty cycle pattern repetition rate,
selectable via I2C
F(REP_SM3)
Total accuracy, relative to F(REP_SM3)TYP
V(VIN) = 3.8 V; I(SM3SW) = 20 mA
–12%
12%
2
RDSON(SM3SW)
ILKG(SM3SW)
RDSON(L3)
LED switch FET on-resistance(1)
LED switch FET leakage
1
1
Ω
μA
mΩ
μA
mA
μs
4
Power stage FET on-resistance
Power stage FET leakage
V(VIN) = 3.8 V; I(L3) = 200 mA
2.5V< V(IN) <5.5V
300
1
600
4
ILKG(L3)
IMAX(L3)
Power stage FET current limit
Maximum on time detection threshold
Minimum off time detection threshold
400
5
500
6
600
15
500
TSM3PWR(ON)
TSM3PWR(OFF)
310
400
ns
HIGH/LOW BRIGHTNESS CONTROL
RDSON(ISM3G) Output buffer switch on resistance
ILKG(ISM3G) Leakage current
SWITCHING FREQUENCY
V(VIN)=2.5V, I(ISM3G)=25mA
Hi-Z mode, V(ISM3G)=5V
1
2
1
Ω
μA
FSM3
Maximum switching frequency(1)
At nominal load
1
MHz
GPIO1-4 – DIGITAL OUTPUT BUFFER
IOL = 3 mA
0.6
0.1
VOL(GPIO)
Low level output voltage
V
V
IOL = 10 μA
IOH = –3 mA
IOH = –10 μA
V(GPIOn) = 2.5V
V(GPIOn) = 0V
1.5
1.8
VOH(GPIO)
High level output voltage GPIO
IOL(GPIO)
IOH(GPIO)
Maximum low level sink current
5
mA
mA
Maximum high level source current(1)
–5
GPIO1-4 – DIGITAL INPUT BUFFER
VIL(GPIO) Low level input voltage
VIH(GPIO)
0.4
0.5
V
V
High level input voltage
Input current
1.15
V(GPIOn) = 5V or 0V, GPIO configured,
GPIO input current sink OFF
ILKG(GPIO)
μA
GPIO1-4 - INPUT CURRENT SINK
ON if TPS658629-Q1 is not in sleep mode and GPIO is not
configured.
ISNK(GPIO)
Input current sink
2.5
3.5
μA
(1) Not production tested
10
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
2.9 ELECTRICAL CHARACTERISTICS (Continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PWM DRIVER, PWM OPEN DRAIN OUTPUT
IPWM
VOL
Maximum operating current(1)
PWM driver ON
200
0.2
mA
V
Low level output voltage
IOL = 100mA , V(AVDD6)=3V
Set via I2C F(PWM)TYP = 0.75, 1.5,
2.3, 3.0, 4.5, 6.7,11.7,23.4
F(PWM)
PWM driver frequency
Frequency range
kHz
D(PWM) = 6.25% to 100%, set via
I2C, 15 steps, 6.25% minimum step
D(PWM)
PWM driver duty cycle
Duty cycle range
%
ILKG(PWM)
Output off leakage current
Output voltage = 5V, driver set to OFF
1
5
μA
LED_PWM DRIVER, LED_PWM OPEN DRAIN OUTPUT
ILEDPWM
Maximum operating current(1)
LED_PWM driver duty cycle
PWM driver ON
200
mA
%
D(LEDPWM) = 0% to 99.6%, set via
I2C, 255 steps, 0.4% minimum step
Duty cycle range, 128Hz repetition rate
D(LEDPWM)
Total accuracy, relative to selected value
IOL = 50mA , V(AVDD6) = 3 V
–10%
10%
0.2
5
VOL(LEDPWM)
ILKG(LEDPWM)
Low level output voltage
Output off leakage current
V
Output voltage = 5 V, driver set to OFF
1
μA
RGB DRIVER, RED/GREEN/BLUE OPEN DRAIN OUTPUTS
TFLASH(RGB) = 1 to 8 sec, set via I2C,
0.5sec minimum step, 15 steps
TFLASH(RGB)
TFLASH(ON)
D(RGB)
RGB1, RGB2 flashing period
RGB1, RGB2 flash on time
RGB1, RGB2 duty cycle
Flashing period range
s
s
Set via I2C, TFLASH(ON) = 0.1, 0.15,
0.2, 0.25, 0.3, 0.4, 0.5, 0.6
Flash on time range, value selectable by I2C
Duty cycle range, value selectable via I2C
D(RGB) = 0% to 96.875%, set via
I2C, 3.125% minimum step
%
Sink current, set via I2C
ISINK(RGB1)TYP = 0, 3.7, 7.4, 11.1
mA
V(RED1)
V(GREEN1) =
V(BLUE1) = 0.25V
=
Absolute accuracy relative to
selected value
–35%
–10%
35%
10%
ISINK(RGB1)
RGB1 output sink current
Relative accuracy between sink
current outputs
ISINK(RGB TYP = 0, 3.7, 7.4, 11.1,
at
Sink current, set via I2C
mA
14.9, 18.6, 23.2, 27.3,
V(RED2) = V(GREEN2)
V(BLUE2) = 0.25V
=
Absolute accuracy relative to
selected value
ISINK(RGB2)
RGB2 output sink current
Low level output voltage
–35%
–10%
35%
Relative accuracy between sink
current outputs
10%
0.25
Output low voltage, RED1/GREEN1/BLUE1 pins, one current
source ON (4 or 8 or 12mA source) ON at a time, V(AVDD6)=3V
VLO(RGB1)
V
Output low voltage, 16mA load, RED2/GREEN2/BLUE2 pins,
one current source ON (4 or 8 or 16mA source) ON at a time,
V(AVDD6) =3V
VLO(RGB2)
ILKG(RGB)
Low level output voltage
Output off leakage current
0.25
2
V
Output voltage = 5V, driver set to OFF
1
μA
DIG_PWM , DIG_PWM1 DRIVER , PUSH PULL OUTPUT
Frequency range
110
–10%
1.7
125
140
Hz
F(PWM)
PWM driver frequency
Output level, HI
Total accuracy, relative to selected value
V(DIG_PWM) at I(DIG_PWM) = –5 mA
V(DIG_PWM) at I(DIG_PWM) = –10 μA
V(DIG_PWM) at I(DIG_PWM) = 5 mA
V(DIG_PWM) at I(DIG_PWM) = –10 μA
10%
VHI(DIGPWM)
V
V
2
0.5
0.1
VLO(DIGPWM)
Output level, LO
(1) Not production tested
Copyright © 2011–2012, Texas Instruments Incorporated
ELECTRICAL SPECIFICATIONS
11
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
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2.10 ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ADC REFERENCE
TA = 25°C
2.595
2.577
3.0
2.6
2.595
4.5
2.605
2.607
VREF(ADC)
Internal ADC reference voltage
V
Over full temp range
V(ADC_REF)=AGND1
ISHRT(ADCREF)
CREFADC
ADC ANALOG INPUTS
Internal reference short circuit limit
mA
Maximum capacitance for internal ADC reference
supply(1)
6.8
μF
VRNG(CH1_6)
VRNG(CH7_10)
VRNG(CH8_9)
CIN(ADC)
Full scale input range Channels 1–6(1)
Positive inputs, Full scale ~ 2.60 V
Positive inputs, Full scale ~ 4.622 V
Positive inputs , Full scale ~ 5.54 V
0
0
0
VREF(ADC)
VREF(ADC) × 1.78
VREF(ADC) × 2.13
V
V
Full scale input range Channels 7, 10(1)
Full scale input range Channels 8, 9(1)
Input capacitance (all channels)
Input resistance (all channels)
V
15
pF
MΩ
μA
RINADC(CH1_6)
ILKGADC(CH1_6)
AVDD6-V(ANLG) >= 500mV
ADC disabled
1
Leakage current (all channels)
0.1
1
ADC – DC ACCURACY
RES(ADC)
MCD(ADC)
INL(ADC)
Resolution
SAR ADC
10
None
±3
Bits
Missing codes
Integral linearity error
Differential non-linearity error
LSB
LSB
DNL(ADC)
±1
Deviation from the first code transition (00..00) to
(00.001) fro m the ideal AGND + 1LSB
OFFZERO(ADC)
OFFCH(ADC)
GAIN(ADC)
Offset error
1
1
5
5
LSB
LSB
LSB
LSB
Offset error match between channels(1)
Gain error
Deviation in code from the ideal full scale code
(11…111) for the full scale voltage
±8
2
GAINCH(ADC)
Gain error match
Any two channels
ADC THROUGHPUT SPEED
ADCCLK
Sampling clock(1)
506
562
16
619
kHz
μs
Sampling time - 9X ADCCLK
ADCTCONV
Sampling and conversion time
conversion and settling time -11X ADCCLK
20
μs
ANLGx (USER_DEFINED INPUTS) BIAS CURRENTS
00 =
0
3
ADC channel 1 bias current, set via I2C
register ADC_WAIT bits (ADICH2_1,
ADICH2_2)
01 =
10 =
11 =
μA
I(ANLGx)
ANLG1, 2, or 3 pin internal pull-up current source
10
50
Total accuracy
–20%
20%
(1) Not production tested
12
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
2.11 PIN DESCRIPTION, REQUIRED EXTERNAL COMPONENTS
2.11.1 ZWS Package Pinout (Top View)
N13
L3
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
FB3 DIG_PWM LED_PWM BLUE1 VIN_LDO9 VIN_LDO4 XTAL2 VIN_LDO01 GPIO4
GPIO2
HSK
M2
COMP
M1
M13
L3
M12
M11
M10
M9
M8
M7
M6
M5
M4
M3
SM3_SW nNOPOWER VTSBIAS GREEN1 BLUE2
LDO9
XTAL1 LDO0
GPIO3
GPIO1
ANLG3 ANLG1
L13
L12
L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
PGND3 PGND3
SM3
nINT
RED1 GREEN2
LDO4
LDO1
HSK
HSK
ANLG2
LDO4PG
RSVDC
K13
K12
K11
K10
HSK
K9
K8
K7
K6
K5
K4
K3
K2
K1
AVDD6
SM3IG
RSVDA
PWM
RED2
HSK
DGND1
HSK
AGND2 ADC_REF LDO7
LDO8
J13
TS
J12
J11
J10
J9
J8
J7
J6
J5
J4
J3
J2
J1
VREF1V25 V2V2
AGND1
HSK
HSK
HSK
HSK
HSK
PSDAT
PSCLK
SDAT VIN_LDO678
H2 H1
H13
RSVDB
G13
H12
RSVDB
G12
H11
H10
H9
H8
H7
H6
H5
HSK
G5
H4
SCLK
G4
H3
RSVDB RTC_OUT HSK
HSK
G8
HSK
G7
HSK
G6
VIN_SM1 VIN_SM1 VIN_SM1
G11
BAT
G10
BAT
G9
G3
G2
L1
G1
L1
BAT
BAT
HSK
HSK
HSK
HSK
HSK
LDO6
VIN_SM1
F13
USB
F12
F11
USB
E11
F10
SM0EN
E10
F9
F8
F7
F6
F5
F4
F3
F2
F1
USB
HSK
HSK
HSK
HSK
HSK DIG_PWM2 PGND1 PGND1 PGND1
E13
USB
D13
AC
E12
SM2
D12
AC
E9
E8
E7
HSK
D7
E6
HSK
D6
E5
HSK
D5
E4
HSK
D4
E3
E2
E1
SM1EN SYNCEN
HSK
D9
HSK
D8
PGND0 PGND0 PGND0
D11
AC
D10
HSK
D3
D2
L0
D1
L0
HSK
HSK
V32K DGND2DT
HSK
nNORTC VIN_SM0
C4 C3
C13
AC
C12
AC
C11
SYS
B11
C10
C9
L2
B9
C8
C7
C6
C5
AGND3
B5
C2
C1
VIN_SM2
B10
PGND2 OUT32K
SM1
B6
SM0 VIN_SM0 VIN_SM0 VIN_SM0
B4 B3 B2 B1
B13
B12
B8
B7
SYS
A13
SYS
SYS
A12
SYS
SYS
A11
SYS
VIN_SM2
A10
L2
A9
L2
PGND2
A8
LDO2
A7
LDO3
A6
AGND3 SM0PG LDO4EN RESUME VIN_SM0
A5 A4 A3 A2 A1
VIN_SM2
PGND2
LDO5 VIN_LDO23 SM1PG AGND3 TNOPOWERnHOT_RST VIN_SM0
PIN FUNCTIONS
EXTERNAL REQUIRED COMPONENTS
(See Application Diagram)
NAME
PIN
I/O
DESCRIPTION
SYSTEM POWER PATH
AC
C12,C13,
D11,D12,
D13
I
Adapter input voltage, connect to AC_DC adapter 1µF(minimum) capacitor to AGND1 pin to minimize over-voltage
positive output terminal (DC voltage)
transients during AC power hot-plug events.
USB
BAT
SYS
E13,F11,
F12,F13
I
USB input voltage, connect to USB port positive
power output
1μF(minimum) capacitor to AGND1 pin, to minimize over-voltage
transients during USB power hot-plug events.
G10,G11,
G12,G13
I/O
O
Battery power
Connect to battery positive terminal. Connect 4.7μF capacitor
(minimum) from BAT pin to clean analog ground plane
A11,A12,
A13,B11,
B12,B13,
C11
AC/BAT/USB power path output. Connect to
System main power rail (system power bus)
10μF capacitor to AGND1 pin
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PIN FUNCTIONS (continued)
EXTERNAL REQUIRED COMPONENTS
(See Application Diagram)
NAME
PIN
I/O
DESCRIPTION
REFERENCE SYSTEM
TNOPOWER
AVDD6
A3
K13
J11
J12
I
NOPOWER pin pulse width
Internal supply rail
Capacitor to AGND1. Capacitor value sets pulse width
O
O
O
Connect 4.7μF capacitor to AGND1. Place close to pin.
V2V2
Internal 2.2V supply rail
1μF (minimum) decoupling capacitor to AGND1. Place close to pin.
VREF1V25
Internal 1.25V reference filter capacitor
100nF (minimum) decoupling cap to AGND1. Do not exceed 1 µF.
Place close to pin.
TEMPERATURE SENSOR
TS
J13
K11
M10
I/O
I
Temperature sense input, current source output
Connect to battery pack thermistor to sense battery pack temperature
Connect to external thermistor pull-up resistor
RSVDA
VTSBIAS
O
Thermistor network bias supply, internally
connected to 2V2 via integrated switch
RSVDB
H11,H12,
H13
I/O
O
RSVDC
L2
SM3 BOOST CONVERTER
L3
M13,N13
N12
O
I
Drain of the integrated boost power stage switch
4.7μH inductor to SYS pin, external Schottky diode to SM3 pin
FB3
White LED duty cycle switch output, LED current
setting
External resistor from FB3 pin to PGND3 pin sets LED peak current.
Connect 100pF (minimum) filter capacitor to PGND3 pin.
SM3_SW
SM3IG
M12
K12
I
Integrated white LED duty cycle switch input
General purpose input/output
HI-Z Output, controlled via I2C. May be used to set SM3 current gain
step, implementing a high/low brightness control
I/O
SM3
L11
I
I
White LED driver output over-voltage detection
Power ground, SM3 converter
Connect 1μF capacitor to PGND3 pin. Connect SM3 pin to the
positive side of white LED ladder.
PGND3
DRIVERS
RED2
L12,L13
Connect to the power ground plane
K8
L8
O
O
O
O
O
O
O
Programmable LED driver, open drain output,
current sink output when active.
Connect to RED input of RGB LED
Connect to GREEN input of RGB LED
Connect to BLUE input of RGB LED
Connect to RED input of RGB LED
Connect to GREEN input of RGB LED
Connect to BLUE input of RGB LED
GREEN2
BLUE2
M8
L9
RED1
GREEN1
BLUE1
M9
N9
N10
LED_PWM
LED_PWM driver output, open drain,
programmable duty cycle.
Can be used to drive a keyboard backlight LED or other external
functions
PWM
K9
N11
F4
I
PWM driver, open drain output
PWM, digital push-pull output
PWM, digital push-pull output
May be used to control external vibrator motor
2V2 output voltage level
DIG_PWM
DIG_PWM2
O
O
2V2 output voltage level
DC/DC CONVERTERS
VIN_SM0
A1,B1,C1,
C2,C3,D3
I
I
SM0 synchronous buck converter positive supply 2 x 10μF capacitor to PGND0 pin
input
SM0
C4
SM0 synchronous buck converter output voltage
sense
LC filter: 1.5μH Inductor and 10μF Capacitor. Connect capacitor to
PGND0 pin
L0
D1,D2
O
SM0 synchronous buck converter power stage
output
1.5μH inductor to SM0 pin
PGND0
E1,E2,E3
I
I
Power ground, SM0 converter
Connect to the power ground plane
VIN_SM1
G3,H1,
H2,H3
SM1 synchronous buck converter positive supply 2 x 10μF capacitor to PGND1 pin
input
SM1
L1
C6
I
SM1 synchronous buck converter output voltage
sense
LC filter: 1.5μH Inductor and 10μF Capacitor. Connect capacitor to
PGND1 pin
G1,G2
O
SM1 synchronous buck converter power stage
output
1.5μH inductor to SM1 pin
PGND1
F1,F2,F3
I
I
Power ground, SM1 converter
Connect to the power ground plane
VIN_SM2
A10,B10,
C10
SM2 synchronous buck converter positive supply 2 x 10μF capacitor to PGND2 pin
input
SM2
E12
I
SM2 synchronous buck converter output voltage
sense
LC filter: 1.5μH Inductor, 10μF Capacitor. Connect capacitor to
PGND2 pin
14
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
PIN FUNCTIONS (continued)
EXTERNAL REQUIRED COMPONENTS
(See Application Diagram)
NAME
PIN
I/O
DESCRIPTION
L2
A9,B9,C9
O
SM2 synchronous buck converter power stage
1.5μH inductor to SM2 pin
output
PGND2
ADC
A8,B8,C8
I
Power ground pin, SM2 converter
Connect to power ground plane
AGND2
ANLG1
K4
I
I
Analog ground, ADC subsystem
Connect to analog ground plane
M1
Analog input1 to ADC, programmable current
source output
Can be used to monitor additional system or pack parameters
ANLG2
L3
M2
K3
I
I
Analog input2 to ADC, programmable current
source output
ANLG3
Analog input3 to ADC, programmable current
source output
ADC_REF
I/O
ADC internal reference filter or ADC external
reference input
Connect a maximum capacitance of 6.8uF referenced to the AGND2
pin.
EXTERNAL SYSTEM RESET AND CLOCK OUTPUTS, ADJUSTABLE LEVEL
V32K
INT
D7
I
Power supply for host interface buffers
L10
O
Interruption pin nINT pin is LO when interrupt is
requested by TPS658XX.
Open drain output
OUT32K
NOPOWER
NORTC
C7
M11
D4
O
O
O
32kHz clock from external XTAL
Push-pull output, V32K level
Host reset output, LO level, adjustable width
RTC_OUT POR pulse, LO level, fixed width
SEQUENCING CONTROL INPUTS
HOT_RST
RESUME
LDO4EN
A2
B2
I/O
Reboot cycle request
Sleep on/off request
LDO4 enable control
Supply enable control
Hardware reboot cycle control
Hardware sleep on/off control
I
I
I
B3
SM0EN
F10
Active low signal.
(CORECTRL)
SM1EN
E11
E10
I
I
Supply enable control
Supply enable control
SYNCEN
I2C INTERFACE
PSDAT
Power I2C clock line
Connect to external host power I2C clock. Connect 2K external pull-
up resistor. Connect to 2V2 pin if not used
J4
J3
J2
H4
I/O
PSCLK
I
I/O
I
I2C interface data line
I2C interface clock line
SDAT
Connect 2K external pull-up resistor.
SCLK
RTC OSCILLATOR
XTAL1
M6
N6
I
I
Xtal oscillator
Connect to external xtal
XTAL2
INPUT / OUTPUT
GPIO1
M3
I/O
General purpose input/output
General purpose input/output
Input: SM0, SM1, SM2 power saving mode and output voltage setting
control
GPIO2
GPIO3
GPIO4
COMP
N3
M4
N4
N1
B4
A5
L1
I/O
I/O
I/O
I
Input: ADC external trigger or LDO0, LDO1 enable
Input: LDO2, LDO3 enable
Input: ADC external trigger or LDO6, LDO7, LDO8 enable
General purpose comparator input, ADC input
SM0 power good status
SM0PG
SM1PG
LDO4PG
O
O
SM1 power good status
O
LDO4 power good status
LINEAR REGULATORS
VIN_LDO01
LDO0
N5
M5
L6
I
Positive supply input for LDO0, LDO1
LDO0 output
1μF (minimum) decoupling capacitor to AGND1
1μF(minimum) capacitor to AGND1
O
O
I
LDO1
LDO1 output
1μF(minimum) capacitor to AGND1
VIN_LDO23
LDO2
A6
B7
B6
Positive supply input for LDO2, LDO3
LDO2 output
1μF (minimum) decoupling capacitor to AGND1
1μF(minimum) capacitor to AGND1
O
O
LDO3
LDO3 output
1μF(minimum) capacitor to AGND1
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PIN FUNCTIONS (continued)
EXTERNAL REQUIRED COMPONENTS
(See Application Diagram)
NAME
PIN
I/O
DESCRIPTION
VIN_LDO4
LDO4
N7
L7
I
Positive supply input for LDO4
LDO4 output
1μF (minimum) decoupling capacitor to AGND1
1μF(minimum) capacitor to AGND1
O
O
I
LDO5
A7
J1
LDO5output
1μF(minimum) capacitor to AGND1
VIN_LDO678
LDO6
Positive supply input for LDO0, LDO1
LDO6 output
1μF (minimum) decoupling capacitor to AGND1
1μF(minimum) capacitor to AGND1
G4
K2
K1
N8
M7
H10
O
O
O
I
LDO7
LDO7 output
1μF(minimum) capacitor to AGND1
LDO8
LDO8 output
1μF(minimum) capacitor to AGND1
VIN_LDO9
LDO9
Positive supply input for LDO9
LDO9 output
1μF (minimum) decoupling capacitor to AGND1
1μF(minimum) capacitor to AGND1
O
O
RTC_OUT
Low leakage LDO output. Can be connected to a 1μF (minimum) capacitor to AGND1 pin or supercap
super-capacitor or secondary cell, if used as a
RTC backup output.
ANALOG AND DIGITAL GROUND PINS
DGND1
AGND1
AGND3
DGND2DT
HSK
K6
J10
I
I
Digital ground pin
Analog ground pin
Analog ground pin
Digital ground pin
Connect to digital ground plane
Connect to analog ground plane
Connect to analog ground plane
Connect to analog ground plane
A4,B5,C5
D6
I
I/O
See
N/A There is an internal electrical connection between all HSK pins of the IC. The HSK pins must be connected to the same
Package
Drawing
potential as the AGND1 pin on the printed circuit board. Do not use the HSK pins as the primary ground input for the
IC.
16
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
2.11.2 Block Diagram
TPS6586xx
PROCESSOR
POWER PATH, OVP
AND INPUT
CURRENT LIMIT,
REFSYS
DRIVERS
AC
USB
BAT
VINLDO9
VINLDO678
LDO6
LDO6
1.25-3.3V
LDO9
LDO9
1.25-3.3V
LDO7
1.25-3.3V
LDO7
LDO8
SM3IG
L3
LDO8
1.25-3.3V
SM3
WHITE LED
DRIVER
SM3_SW
FB3
RTC_OUT LDO
1.25-3.3V
PGND3
RTC_OUT
SYS
SYS
VIN_SM0
LDO5
1.25-3.3V
0.725 - 1.5V
31x25mv steps
L0
LDO5
SM0
PGND0
CONTROL
LOGIC
VINLDO4
LDO4
LDO4
1.7-2.475V,
31X25mV steps
VIN_SM1
L1
0.725 - 1.5V
31x25mv steps
SM1
PGND1
VINLDO23
LDO2
LDO2
0.725-1.5V ,
31x25mV steps
VIN_SM2
L2
3 - 4.55V
31x25mv steps
SM2
PGND2
LDO3
1.25-3.3V
LDO3
6 INTERNAL
CHANNELS
VINLDO01
LDO0
ANLG1
LDO0
1.25-3.3V
ANLG2
ANLG3
10 CHANNEL
MUX
COMP
LDO1
LDO1
0.725 -1.5V
31x25mV steps
A/D
!CONVERTER
ADC_REF
AGND2
RTC_OUT
COMP
AGND1
AGND3
HOST INTERFACE AND SEQUENCING
I2C INTERFACE
AND INTERRUPT
CONTROLLER
SEQUENCING AND RESET
CONTROLLER
I/O
DGND1
RTC
DGND2DT
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2.12 TYPICAL CHARACTERISTICS
LDO9 Vout vs. Iout (Temp. = 25°C) 1.250V
LDO9 Vout vs. Iout (Temp. = 25°C) 3.30V
3.40
3.35
3.30
3.25
3.20
3.15
3.10
1.28
1.27
1.26
1.25
1.24
1.23
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
1.22
1.21
1.20
0.10
1.00
10.00
Iout [ma]
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Figure 2-1.
Figure 2-2.
LDO0 Vout vs. Iout (Temp. = 25°C) 1.250V
LDO0 Vout vs. Iout (Temp. = 25°C) 3.30V
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
3.40
3.35
3.30
3.25
3.20
3.15
3.10
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Iout [ma]
Figure 2-3.
Figure 2-4.
18
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
(continued)
LDO1 Vout vs. Iout (Temp. = 25°C) Low Range
LDO1 Vout vs. Iout (Temp. = 25°C) High Range
0.75
0.74
0.73
0.72
0.71
0.70
0.69
0.68
0.67
0.66
2.64
2.62
2.60
2.58
2.56
2.54
2.52
2.50
Vin=Vout+0.5, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Iout [ma]
Figure 2-5.
Figure 2-6.
LDO2 Vout vs. Iout (Temp. = 25°C) Low Range
LDO2 Vout vs. Iout (Temp. = 25°C) High Range
0.75
0.74
0.73
0.72
0.71
0.70
0.69
0.68
0.67
0.66
2.65
2.63
2.61
2.59
2.57
2.55
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C]
Vin=5.5, Ta=25C
Vin=Vout+0.5v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Iout [ma]
Figure 2-7.
Figure 2-8.
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(continued)
LDO3 Vout vs. Iout (Temp. = 25°C) 1.250V
LDO3 Vout vs. Iout (Temp. = 25°C) 3.30V
3.40
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
3.35
3.30
3.25
3.20
3.15
3.10
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
Iout [ma]
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Figure 2-9.
Figure 2-10.
LDO4 Vout vs. Iout (Temp. = 25°C) 2.475V
LDO4 Vout vs. Iout (Temp. = 25°C) 1.700V
1.74
1.73
1.72
1.71
1.70
2.54
2.52
2.50
2.48
2.46
2.44
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Iout [ma]
Figure 2-11.
Figure 2-12.
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(continued)
LDO5 Vout vs. Iout (Temp. = 25°C) 3.30V
LDO5 Vout vs. Iout (Temp. = 25°C) 1.250V
3.40
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
3.35
3.30
3.25
3.20
3.15
3.10
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
Iout [ma]
100.00
1000.00
0.10
1.00
10.00
Iout [ma]
100.00
1000.00
Figure 2-13.
Figure 2-14.
LDO6 Vout vs. Iout (Temp. = 25°C) 3.30V
LDO6 Vout vs. Iout (Temp. = 25°C) 1.250V
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
3.40
3.35
3.30
3.25
3.20
3.15
3.10
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Iout [ma]
Figure 2-15.
Figure 2-16.
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(continued)
LDO7Vout vs. Iout (Temp. = 25°C) 1.250V
LDO7 Vout vs. Iout (Temp. = 25°C) 3.30V
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
3.40
3.35
3.30
3.25
3.20
3.15
3.10
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
100.00
1000.00
Iout [ma]
Iout [ma]
Figure 2-17.
Figure 2-18.
LDO8 Vout vs. Iout (Temp. = 25°C) 3.30V
LDO8 Vout vs. Iout (Temp. = 25°C) 1.250V
1.28
1.27
1.26
1.25
1.24
1.23
1.22
1.21
1.20
3.40
3.35
3.30
3.25
3.20
3.15
3.10
Vin=2.3v, Ta=25C
Vin=3.9v, Ta=25C
Vin=5.5v, Ta=25C
Vin=Vout + 0.5, Ta=25C
Vin=4.65v, Ta=25C
Vin=5.5v, Ta=25C
0.10
1.00
10.00
100.00
1000.00
0.10
1.00
10.00
Iout [ma]
100.00
1000.00
Iout [ma]
Figure 2-19.
Figure 2-20.
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(continued)
LDO2 0.725V DropOut at 25°C
LDO0 1.25V DropOut at 25°C
1.40
1.30
1.20
1.10
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.80
0.78
0.76
0.74
0.72
0.70
0.68
0.66
0.64
0.62
0.60
Temp. = 25°C
Iout = 1mA
Temp = 25°C
Iout = 1mA
Temp = 25°C
Iout = 100mA
Temp = 25°C
Iout =250mA
Temp. = 25°C
Iout = 100mA
Temp. = 25°C
Iout = 250mA
2..20
2..00
1..80
1..60
1.40
1..20
1.00
2.30 2.20 2.10 2.00 1.90 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00
Vin [V]
Vin [V]
Figure 2-21.
Figure 2-22.
Efficiency SM0 Auto PFM Vout 1.8V at 25°C
LDO0 3.3V DropOut at 25°C
100
3.50
3.40
3.30
3.20
3.10
3.00
2.90
2.80
2.70
2.60
2.50
2.40
2.30
2.20
2.10
2.00
90
80
70
60
50
2.3
2.8
3.4
3.9
4.4
4.9
5.5
6.0
2.6
3.1
3.6
4.2
4.7
5.2
5.7
40
30
20
10
0
Temp. = 25°C
Iout = 1mA
Temp. = 25°C
Iout = 100mA
Temp. = 25°C
Iout = 250mA
0.0001
0.001
0.01
0.1
1.0
10.0
3.80 3.70 3.60 3.50 3.40 3.30 3.20 3.10 3.00 2.90 2.80 2.70 2.60 2.50
Iout [A]
Vin [V]
Figure 2-23.
Figure 2-24.
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(continued)
Efficiency SM0 PWM Vout 1.8V at 25°C
Efficiency SM1 Auto PFM Vout 1.25V at 25°C
100
90
80
70
60
50
40
30
20
10
0
100
2.3
2.8
3.4
3.9
4.4
4.9
5.5
6.0
2.6
3.1
3.6
4.2
4.7
5.2
5.7
90
80
70
60
50
40
30
20
10
0
2.3
2.8
3.4
3.9
4.4
4.9
5.5
6.0
2.6
3.1
3.6
4.2
4.7
5.2
5.7
0.00100
0.10000
0.00010
0.01000
Iout [A]
1.00000
10.00000
0.00010
0.00100
0.01000
0.10000
1.00000
10.00000
Iout [A]
Figure 2-25.
Figure 2-26.
Efficiency SM2 Auto PFM Vout 3.25V at 25°C
Efficiency SM1 PWM Vout 1.250V at 25°C
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
2.3
2.8
3.4
3.9
4.4
4.9
5.5
6.0
2.6
3.1
3.6
4.2
4.7
5.2
5.7
3.0
3.4
3.9
4.3
4.7
5.1
5.6
6.0
3.2
3.6
4.1
4.5
4.9
5.4
5.8
0.001
0.01
0.10
1.0
10.0
0.0001
0.001
0.01
0.1
Iout [A]
1.0
10.0
Iout [A]
Figure 2-27.
Figure 2-28.
24
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(continued)
Efficiency SM2 PWM Vout 3.25V at 25°C
100
90
80
70
60
50
40
30
20
10
0
3.0
3.4
3.9
4.3
4.7
5.1
5.6
6.0
3.2
3.6
4.1
4.5
4.9
5.4
5.8
0.0001
0.001
0.01
0.1
1.0
10.0
Iout [A]
Figure 2-29.
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3 DETAILED DESCRIPTION
3.1 I2C INTERFACE
Two I2C configurations are implemented in the TPS658629-Q1 device:
A –Standard I2C interface (SDAT/SCLK engine) : A single I2C communication port provides a simple
way for an I2C compatible host to access system status information, reset fault modes, and set supply
output voltages. The I2C port functions as a SLAVE enabling I2C compatible hosts (MASTER) to perform
WRITES and READS to/from internal registers. The I2C port is a 2-wire bidirectional interface using the
SCLK (clock) and SDAT (data) pins. The I2C is designed to operate at SCLK frequencies up to 400 kHz.
The standard 8 bit command is supported. The CMD part of the sequence is the 8 bit register address to
read or write.
B – Power I2C interface (PSDAT/PSCLK engine): The TPS658629-Q1 supports processors that use a
dedicated I2C bus to dynamically adjust critical supply voltages by adding a second I2C bus (Power I2C)
connected to a second, dedicated I2C engine. The Power I2C port is a 2-wire bidirectional interface using
the PSCLK (clock) and PSDAT (data) pins. The Power I2C is designed to operate at PSCLK frequencies
up to 400 kHz. A multiple-byte data-register pair command protocol, not compatible with the standard I2C
protocol, is supported by the Power I2C engine. The Power I2C engine does not support read operations.
NOTE
The Standard and Power I2C engines are always reset by the sequencer when the
TPS658629-Q1 is in the POWER-UP state and when the SLEEP state is set.
3.2 I2C ADDRESS
The TPS658629-Q1 will acknowledge (ACK) addresses 0x68 (writes) and 0x69 (reads) and will NACK any
other address.
3.3 DVM REGISTER ACCESS
The sequencer state machine disables write access to specific supply voltage setting registers when the
TPS658629-Q1 is initially powered and when the integrated supplies are being sequenced. See the
sequencer functional description for details.
3.4 SCLK/SDAT AND PSCLK/PSDAT TIMEOUT
The TPS658629-Q1 monitors the SCLK/PSCLK clock lines, and it identifies a timeout condition if the clock
line is held at a logic low for longer than 30ms. The I2C engine is NOT reset when the clock line timeout is
identified.
The TPS658629-Q1 monitors the SDAT/PSDAT data lines. The I2C engine will be reset when the data line
is held at a logic low for more than 30ms.
3.5 I2C BUS RELEASE
The TPS658629-Q1 I2C engine does not create START or STOP states on the I2C bus during normal
operation.
3.6 I2C BUS ERROR RECOVERY
The I2C bus specification does not define a method to be used when recovering from a host side bus
error. During a read operation the SDAT pin can be left in a LO state if the host has not sent enough
SCLK pulses to complete a transaction (i.e. host side bus error). The TPS658629-Q1 will clear any SDAT
LO condition if 10 SCLK pulses are sent by the host, enabling recovery from host side bus error events.
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3.7 I2C COMMUNICATION PROTOCOL
The following conventions will be used when describing the communication protocol:
CONDITION
CODE
START sent from host
STOP sent from host
S
P
TPS658629-Q1 I2C slave address sent from host (WRITE)
TPS658629-Q1 register address sent from TPS658629-Q1 (READ)
Non-valid I2C slave address sent from host
hA0
hA1
hA_N
HCMD
HCMD_N
hDATA
bqDATA
hA
Valid TPS658629-Q1 register address sent from host
Non-valid TPS658629-Q1 register address sent from host
I/O data byte (8 bits) sent from host to TPS658629-Q1
I/O data byte (8 bits) sent from TPS658629-Q1 to host
Acknowledge (ACK) from host
Not acknowledge (NACK) from host
hN
Acknowledge (ACK) from TPS658629-Q1
bqA
Not acknowledge (NACK) from TPS658629-Q1
bqN
Figure 3-1. I2C Conditions
For normal data transfers, the data line (SDAT or PSDAT) is allowed to change only when the clock line
(SCLK or PSCLK) is low, and one clock pulse is used per bit of data. The data line must remain stable
whenever the clock line is high, as data changes when the clock is high are reserved for indicating the
start and stop conditions. Each data transfer is initiated with a start condition and terminated with a stop
condition.
When addressed, the TPS658629-Q1 device generates an acknowledge bit after the reception of each
byte by pulling the data line Low. The master device (microprocessor) must generate an extra clock pulse
that is associated with the acknowledge bit. After the acknowledge/not acknowledge bit, the TPS658629-
Q1 leaves the data line high, enabling a STOP condition generation.
3.8 I2C READ AND WRITE OPERATIONS
The TPS658629-Q1 supports the standard I2C one byte Write. The basic I2C read protocol has the
following steps:
1. Host sends a start and sends TPS658629-Q1 address
2. TPS658629-Q1 ACK’s that this is a valid I2C address and that the bus is configured for write
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3. Host sends TPS658629-Q1 register address
4. TPS658629-Q1 ACK’s that this is a valid register and stores the register address to be read
5. Host sends a repeated start and TPS658629-Q1 I2C slave address, reconfiguring the bus for read
6. TPS658629-Q1 ACK’s that this is a valid address and that bus is reconfigured
7. Bus is in read mode, TPS658629-Q1 starts sending data from selected register
The I2C write protocol is similar to the read, without the need for a repeated start and bus being set in
write mode. In a WRITE, it is not necessary to end each 1 byte WRITE command with a STOP as a
START will have the same effect (repeated start).
The host can complete a READ or a WRITE sequence with either a STOP or a START.
NOTE
Read operations are not supported for the PSDAT/PSCLK I2C engine.
Figure 3-2. I2C Read/Write Example
3.9 VALID WRITE SEQUENCES (SDAT/SCLK, PSDAT/PSCLK)
The TPS658629-Q1 will always ACK its own address. If CMD points to an allowable READ or WRITE
address, the device writes the address into its RAM address register and sends an ACK. If CMD points to
a non-allowed address, the device does NOT write the address into its RAM address register and sends a
NACK.
S
hA0
bqA
S
hA0
bqA
hCMD
bqA
S
hA0
bqA
hCMD_N
bqN
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3.10 ONE BYTE WRITE (SDAT/SCLK, PSDAT/PSCLK)
The data is written to the addressed register at the end of the bq ACK, ending the one byte write
sequence when the RAM address and the data byte are stored in the I2C registers. The host can cancel a
WRITE by sending a STOP or START before the trailing edge of the ACK clock pulse.
S
hA0
bqA
hCMD
bqA
hDATA
bqA
3.11 VALID READ SEQUENCES (SDAT/SCLK ONLY)
The TPS658629-Q1 will always ACK its own address.
S
hA1
bqA
Upon receiving hA1, TPS658629-Q1 starts at the current location of the RAM address register. The
START and the STOP both act as priority interrupts. If the host has been interrupted and is not sure
where it left off, it can send a STOP and reset the TPS658629-Q1 state machine to the WAIT state; once
in the WAIT state, the TPS658629-Q1 will ignore all activity on the SCLK and SDAT lines until it receives
a START. A repeated START and START in the I2C specification are both treated as a START.
S
hA0
bqA
hCMD
hA1
bqA
P
S
hA0
bqA
hCMD
bqA
S
bqA
bqDATA
hN
P
3.12 VALID READ SEQUENCES (SDAT/SCLK ONLY)
S
hA1
bqA
bqDATA
hA
hN
P
Incremental read sequences
S
hA1
bqA
bqData
hA
bqDATA
. . .
bqDATA
hN
P
3.13 NON-VALID SEQUENCES
START and non-hA0 or non-hA1 Address: A START followed by an address which is not hA0 or hA1 will
be NACKED.
S
hA_1
bqN
Attempt to Specify Non-Allowed READ Address
If the CMD points to a non-allowed READ address (reserved registers), bq will send a NACK back to the
host and it will not load the address in the RAM address register. Note that the TPS658629-Q1 NACKS
whether a stop is sent or not.
S
hA0
bqA
hCMD_N
bqA
P
S
hA0
bqA
hCMD_N
bqN
Attempt to Specify Non-Allowed WRITE Address
If the host attempts to WRITE to a READ-ONLY or non-accessible address, the TPS658629-Q1 ACKS the
CMD containing the allowed READ address, loads the address into the address register and ACKS after
the host sends the next data byte. A subsequent hA1 READ could read this address, but the data sent by
the host will not have been written.
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S
hA0
bqA
hCMD
bqA
hDATA
bqA
3.14 INCREMENTAL READ (SDAT/SCLK ONLY)
The SDAT/SCLK I2C interface supports incremental read operations. Each register must be accessed in a
single read operation. A valid WRITE address is required to write to the RAM, and a valid READ address
is required to specify the initial RAM address where the READ starts. Once a read command is received,
the RAM data for the specified address is output to the host. If the host chooses, it can loop through the
remaining addresses; the address is automatically incremented by one at the end of each read. If the loop
gets to the top address, it automatically rolls over to address 0x00 and the sequence stops.
3.15 I2C COMMUNICATION PROTOCOL – POWER I2C INTERFACE, PINS PSDAT/PSCLK
The Power I2C interface is designed to support fast write operations using multiple register-data pair
sequences. The Power I2C engine is a write-only engine, and it does not support read operations.
During a write sequence, the host sends the start command, followed by the TPS658629-Q1 address.
Then the host sends the register address byte, followed by eight bits of the data for the respective register
(Register1 Address/Data in Figure 3-3). From this point on the TPS658629-Q1 will accept all the following
2 byte pairs as a random register address, followed by the data content to be written to that register. This
process continues until the host sends a valid stop condition after the last register (Register N in Figure 3-
3) is written. A typical multi-byte sequence is shown in Figure 3-3.
Figure 3-3. Power I2C Protocol
3.16 SIMULTANEOUS STANDARD AND POWER I2C OPERATION
The TPS658629-Q1 has individual address pointers for the Power I2C engine and Standard I2C engine.
The value written to the register will be defined by the relative timing between read/write pulses when
simultaneous I2C read/write operations happen. Simultaneous write/read operations to the same register
will be handled as follows:
1. Both Standard I2C and Power I2C are executing operations accessing distinct registers at the same
time (simultaneous read/read, read/write, write/read or write/write): No conflict exists in this case.
2. Power I2C writes and Standard I2C reads the same register at the same time
(a) Standard I2C will read the old register value if the Standard I2C read pulse is generated at least
110nsec (typ) before the Power I2C write pulse happens.
(b) Standard I2C will read the new register value if the Standard I2C read pulse is generated at least
110nsec (typ) after the Power I2C write pulse happens.
3. Power I2C and Standard I2C write to the same register at the same time
(a) If both write operations are more than 110nsec (typ) apart, the register final value will be set by the
engine that executes the last write operation.
(b) a. If both write operations are less than 110nsec (typ) apart, the priority will be given to the Power
I2C engine. The value from the Power I2C engine will be written into the register, and the data
received by the Standard I2C operation is not written to the TPS658629-Q1 internal memory.
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THERE IS NO CLOCK STRETCH FUNCTION IN EITHER SCLK OR PSCLK WHEN A CONFLICT
SITUATION HAPPENS. THE CONFLICT IS HANDLED INTERNALLY BY GIVING PRIORITY TO
PSDAT/PSCLK ENGINE.
3.17 POWER PATH
3.17.1 RAM Control Bits
The power path circuit connects one of the power sources plugged into the AC, USB or BAT pins to the
SYS pin. The supply selection is made based on system parameters monitored by the power path circuit
and internal RAM control bits in register 0x4C.
Table 3-1. Power Path Control
PPATH1 [Addr 0x4C]
Bit Number
Defaults in BOLD
B0
B7
B6
B5
B4
B3
B2
B1
Bit Name
USBSUSP
USBDCH
ACDCH
CHGRNG
BOOTOFF
USBLIMIT
USBMODE
PWRSYS
USB INPUT
CURRENT LIMIT
SETTING
AUTO SYS
POWER
SELECTION
USB SUSPEND
MODE
CHARGE
USB INPUT ILIMIT
USB INPUT
CURRENT LIMIT
Function
When 0
When 1
SPARE
SPARE
VOLTAGE RANGE at BOOT PHASE
SET BY USBLIMIT
SUSPEND OFF
NOT USED
NOT USED
NOT USED
NOT USED
3.95V-4.2V
100mA
SET BY USBLIMIT
BAT TO SYS
ONLY
SET BY
USBMODE AND
USBLIMIT
AUTO MODE
ENABLED
SUSPEND ON
4.3V-4.45V
500mA
2.25 A
The input power priority is hard-wired internally, with the AC input having the higher priority, followed by
the USB input (2nd) and the battery pack (3rd). The SYS pin voltage is not regulated and it will be equal
to the input voltage (AC, USB or BAT value) minus the voltage drop across the switch that is ON when the
selected input current limit is not active.
Setting the control bit PWRSYS (bit 0) to 0, the user can override the power path priority, connecting the
battery to the SYS pin even if AC or USB are detected. When PWRSYS is 0 and the battery is removed,
the SYS pin will not be connected back to the AC or USB inputs and thereby will discharge to ground.
The USB power will be ignored when USBSUSP (bit 7) is 1, connecting only the AC or BAT power
sources to the SYS pin. If neither AC nor BAT is connected the SYS pin, it will discharge to ground.
The USB input current is limited to the maximum value programmed by the host via the I2C interface by
setting bits USBLIMIT (bit 2) and USBMODE (bit 1) as shown in Table 3-2.
Table 3-2. Power Path Current Limit
USBMODE
USBLIMIT
USB INPUT CURRENT LIMIT
100 mA max
AC INPUT CURRENT LIMIT
0
0
1
0
1
X
500 mA max
2.2 A min
2.1 A min
If the system current requirements exceed the input current limit, the SYS pin voltage will be reduced until
the power path is set in supplement mode (if pack is connected).
3.18 SYSTEM STATUS DETECTION
The TPS658629-Q1 has integrated comparators that monitor the BAT, AC, USB and SYS pin voltages.
Table 3-3 lists the system power detection conditions:
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Table 3-3. Power Path Detection Functions
SYSTEM STATUS
AC input voltage detected
USB input voltage detected
AC over-voltage detected
USB over-voltage detected
SYS pin short detected
DETECTION CONDITIONS(1)
VIN(OVP) > V(AC) > V(BAT) + VIN(DT)
VIN(OVP) > V(USB) > V(BAT) + VIN(DT)
V(AC) > VIN(OVP)
V(USB) > VIN(OVP)
V(SYS) < VSH(SYS)
Battery switch over-current detection
Supplement mode detection
I(BAT) > IBATSYS
V(SYS)<V(BAT)–VSUP(SYS) AND I(BAT)< IBATSYS
(1) VIN(DT), VSH(SYS), VBATSH, VIN(OVP), VSUP(SYS) are TPS658629-Q1 internal references, refer to the electrical characteristics for additional
details
Figure 3-4. Simplified Power Path Block
The I2C control bits and system status are used by the power path control logic to define the state of the
power path switches as shown below; a fault condition will be detected when the SYS pin is shorted or a
battery switch over-current condition is detected.
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Table 3-4. Power Path Control
FAULT
AC
USB
6586xx
MODE
AC
DETECTED
USB
DETECTED
SYS PIN
CONNECTED TO
PWRSYS
USBSUSP
DETECTE SWITCH SWITCH BATTERY SWITCH
D
UVLO
X
X
X
X
X
0
X
X
X
X
X
OFF
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
NONE
NOT UVLO
NOT UVLO
NOT UVLO
YES
NO
NO
PULL-UP RES/ISRC
YES
NO
X
ON if Supplement
mode is required,
OFF otherwise
AC
YES
OFF
USB
1
NOT UVLO
NOT UVLO
NOT UVLO
1
X
X
NO
NO
X
YES
NO
X
NO
NO
NO
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
BATTERY
BATTERY
BATTERY
0
When a fault condition is detected, the fault recovery method (resistor or current source) is defined by the
input power supply detection:
Table 3-5. Power Path Fault Recovery Control
AC DETECTED
USB DETECTED
RECOVERY METHOD
AC PULL-UP RESISTOR ON
USB PULL-UP RESISTOR ON
30mA CURRENT SOURCE ON
YES
NO
X
YES
NO
NO
3.19 POWER PATH STATUS
The power path status is available at register 0xB9, bits BATSYSON, ACSWON, USBSWON , and
register 0xBB, bits LOWSYS, ACDET, USBDET, AC_OVP and USB_OVP. See the STATUS REGISTER
section for bit function description.
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3.20 CHG1 AND CHG2 RAM REGISTERS
Table 3-6. Control Registers
CHG1 [Addr 0x49]
Bit Number
Defaults in BOLD
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD
RSVD
BATDCH
TSON
RSVD
RSVD
RSVD
RSVD
BATTERY
DISCHARGE
SWITCH
THERMISTOR
BIAS
CONTROL
Function
When 0
When 1
OFF
OFF
ENABLED
ON
CHG2 [Addr 0x4A]
Bit Number
Defaults in BOLD
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
DTCON
RSVD
TSBYP
RSVD
RSVD
RSVD
RSVD
RSVD
DYNAMIC
TIMER
FUNCTION
ENABLE
CHARGER
LDO MODE
Function
When 0
When 1
OFF
OFF
ON
ON
3.21 BATTERY DETECTION, TEMPERATURE QUALIFICATION
Battery pack insertion and battery pack temperature are detected by three comparators that monitor the
thermistor voltage. The thermistor supply is enabled via I2C when control bit TSON=HI in register CHG1.
This control bit enables the host software to turn on the thermistor bias when the pack temperature needs
to be measured via the ADC, minimizing system quiescent current when operating under battery power.
3.22 BATTERY DISCHARGE SWITCH
An internal switch will discharge the BAT pin to ground when the battery is not detected. This switch is
enabled via I2C control bit BATDCH on register CHG1.
3.23 TPS658629-Q1 OPERATING MODES
The TPS658629-Q1 has an internal state machine that sets the operating modes based on the system
status and host commands. The state machine directly controls the state of the integrated supplies during
power-up sequences and normal operation. It also can change the on/off state of all integrated power
supplies and peripherals to implement protection functions or execute external hardware control or host
software commands.
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3.24 STATE MACHINE DIAGRAM
V(AC) > VUVLO
OR
NO POWER
POWER UP(B)
ALL REGISTERS RESET TO
DEFAULT
V(USB) > VUVLO
OR
V(BAT) > VUVLO
ALL
SUPPLIES
OFF
ENABLE POWER PATH
OPERATION
nNOPOWER=LO
TPS6585X
IN UVLO
MODE
V(SYS) > VLOWSYS AND t>TPOR
V(2V2) < VUVLO
{ [ INPUT POWER(AC OR USB): NOT DETECTED Ð DETECTED] OR
[ RESUME=HI FOR 550ms (min) DETECTED ] OR [ RTC_ALARM=HI ]}
AND
CYCLE=
INITIAL POWER UP
ANY
STATE
[ V(SYS) > VLOW_SYS AND SLEEP NOT SET BY THERMAL FAULT ]
RTC(B)
ALL SUPPLIES OFF
FORCE RTC_OUT LDO OFF
nNOPOWER=LO
RESET/START TCHECK TIMER
AUTOBOOT ENABLED AND
V(SYS) > VLOW_SYS AND
SLEEP NOT SET BY THERMAL FAULT
t >TWAIT
CYCLE=POWER UP DONE
AND
HARD REBOOT
CYCLE= INITIAL POWER UP
AND
V(SYS) > VLOW_SYS AND
t > TCHECK
ALL SYNC SUPPLIES OFF
nNOPOWER=LO
RESET/START TWAIT TIMER
V(SYS) > VLOW_SYS AND
t > TCHECK
RTC_ON(B)
ALL SUPPLIES OFF
WAIT(B)
FORCE RTC_OUT LDO ON
SLEEP STATE
nNOPOWER=LO
SUPPLIES OFF
FORCE RTC_OUT LDO ON
ENABLE nNOPOWER TIMER
RESET/START TMAX TIMER
nNOPOWER=LO
ALL SUPPLIES OFF
ALL REGISTERS RESET TO DEFAULT
RTC REGISTERS RESET IF RTC_OUT < VUVLO_RTC
EE-LOADABLE REGISTERS ARE
NOT RESET (KEEP VALUES)
ALL OTHER REGISTERS RESET TO DEFAULT
RESET/START TIMERS: TNORTC
THOTPLUG, TBOOT
,
t >TWAIT
AND
REBOOT REQUEST
TO HARD REBOOT
ENABLED
BOOT TIMER EXPIRES
OR
V(RTC_OUT) > VRTCLOW
OR t > TMAX
NO I2C COMMUNICATION
[ HOTPLUG TIMER EXPIRES AND
V(SYS) < VLOW_SYS FOR 5mSEC AND
SLEEP BY LOWSYS ENABLED]
SUPPLYSEQ(B)
FORCE RTC_OUT LDO ON
RTC REGISTERS NOT RESET (KEEP VALUES)
ALL OTHER REGISTERS RESET TO DEFAULT
RESET/START TIMERS: TNORTC , THOTPLUG, TBOOT
EXECUTE SUPPLY SEQUENCING
t > TWAIT – TWAIT1
nNOPOWER=LO
RESET/START TIMER TSYNCEND WHEN
SEQUENCING IS COMPLETE
SUPPLY
BOOT TIMER EXPIRES
OR
SEQUENCING
COMPLETE
AND
[ HOTPLUG TIMER EXPIRES AND
V(SYS) < VLOW_SYS FOR 5mSEC AND
SLEEP BY LOWSYS ENABLED]
t > TWAIT1
t > TSYNCEND
POWER GOOD CHECK(B)
FORCE RTC_OUT LDO ON
PGOOD FAULT
DETECTED
NO PGOOD FAULT
NO THERMAL FAULT
AND
REBOOT SET VIA I2C OR
nHOTRST PIN LO PULSE
DETECTED
SLEEP EXIT SET VIA I2C
AND
CYCLE=POWER UP DONE
NORMAL MODE
SLEEP REQUEST
REBOOT
REQUEST
ENABLE WRITE TO DVM REGISTERS
RTC REGISTERS RESET IF RTC_OUT < VUVLO_RTC
TURN OFF ENABLE PIN PULL-DOWN RESISTORS
ENABLE SUPPLY OUTPUT DISCHARGE
RESISTORS
RESET/ START
TWAIT TIMER
RESET/ START
TWAIT TIMER
nNOPOWER=LO
ENABLE MPL RECOVERY IF
SLEEP SET BY LOWSYS
AND BAT POWER ONLY
[ RESUME = HI FOR 400ms (min) DETECTED ] OR
[PGOOD FAULT AND NORMAL MODE SET ] OR
SLEEP MODE SET VIA I2C
WHEN ANY OF THE BOOT PHASE(B) STATES ARE SET :
OR
THERMAL FAULT
[ HOTPLUG TIMER EXPIRED AND
V(SYS) < VLOW_SYS FOR 5mSEC AND
SLEEP BY LOWSYS ENABLED VIA I2C ]
1 - WRITE TO DVM REGISTERS IS DISABLED
2 - SM0EN, SM1EN, SYNCEN,LDO4EN PULL-DOWN RESISTORS ON
3 - SUPPLY OUTPUT DISCHARGE RESISTORS ON
ANY
STATE
Figure 3-5. TPS658629-Q1 Operation Mode State Machine
The state machine transitions for the TPS658629-Q1 have been defined as shown below.
1. Supply sequencing started only when LDO4EN voltage level is a logic high
2. REBOOT REQUEST state transitions to the HARD REBOOT state
3. Supply sequencing is considered complete only if SM0 is turned ON
4. Sequencer goes into sleep during initial power-up cycle
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3.25 STATE MACHINE DESCRIPTION
In a normal power-up sequence the state machine will step through the following states:
POWER-UP: If the internal digital supply (2V2) is below the internal UVLO threshold, VUVLO (2V typ), all IC
blocks are disabled and the TPS658629-Q1 is not operational. When the 2V2 supply voltage rises above
VUVLO, the POWER-UP state is entered, an internal delay (TPOR, 8ms typ) is started and the SYS power
path is enabled. The SYS pin voltage is sensed by an internal comparator, and compared to the internal
threshold VLOW_SYS. When the power-on-reset delay expires and V(SYS) > VLOW_SYS the TPS658629-Q1
enters the RTC mode.
RTC: When the RTC state is set the nNOPOWER pin is pulled to ground, discharging the external
capacitor connected to pin TNOPOWER and resetting the NOPOWER timer. The RTC_OUT LDO is
turned off, and the voltage at pin RTC_OUT is flagged as low if V(RTC_OUT) < VRTCLOW The RTC state
ends when the timer TCHECK expires.
RTC_ON: When the state RTC_ON is set the integrated current source connected to the TNOPOWER pin
and the RTC_OUT LDO are enabled. If the RTC_OUT voltage was flagged as low in the RTC state the
TNORTC timer is enabled, and the NORTC pin is pulled low until V(RTC_OUT) > VRTC_PGOOD. The TNORTC
timer starts counting when RTC_OUT > VRTCLOW, and NORTC will be set to hi when t > TNORTC
.
The TNOPOWER current source will remain ON until a new reboot cycle or sleep cycle is set, charging
the external capacitor connected to the TNOPOWER pin. The NOPOWER pin will be at a low logic level
until the TNOPOWER pin voltage is above an internal threshold (1.23v typ). When NOPOWER pin
transitions from LO→HI, a 250μsec (typ) positive going pulse is generated at CHG_STAT pin. The
TNOPOWER external capacitor is discharged whenever the sequencer sets the NOPOWER pin to a low
state.
The RTC_ON state ends when V(RTC_OUT) > VRTC_PGOOD or when the internal watchdog timer TMAX
expires.
WAIT: The TPS658629-Q1 will go into the WAIT state when exiting the RTC state during the initial power-
up cycle. To avoid undesired lockup conditions this operational mode should be used only when the boot
timer is enabled.
Three internal timers are started when the state machine enters the WAIT state. These timers run
independent of the sequencing state and have the following functionality:
•
•
•
BOOT Timer (TBOOT): Sets the TPS658629-Q1 in the SLEEP REQUEST state if it expires during WAIT
state.
HOTPLUG Timer (THOTPLUG): SLEEP REQUEST state set by V(SYS) < VLOWSYS is inhibited until this
timer expires
NORTC Timer (TNORTC): NORTC pin will be set to a logic low level until this timer expires
The BOOT timer value is set to 500ms and the NORTC pulse width is set to 10ms.
SUPPLYSEQ: During the SUPPLYSEQ state all the internal supplies, with exception of RTC_OUT, are
initially turned off and then turned on according to a pre-programmed internal sequencing. Three internal
timers are started when the state machine enters the SUPPLYSEQ state. These timers run independent
of the sequencing state and have the following functionality:
•
•
•
BOOT Timer (TBOOT): Sets the TPS658629-Q1 in the SLEEP REQUEST state if it expires during
SUPPLYSEQ state.
HOTPLUG Timer (THOTPLUG): SLEEP REQUEST state set by V(SYS) < VLOWSYS is inhibited until this
timer expires
NORTC Timer (TNORTC): NORTC pin will be set to a logic low level until this timer expires
The BOOT timer value is set to 500ms and the NORTC pulse width is set to 10ms.
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The I2C engines are available while the device is in the SUPPLYSEQ state, however write operations to
the DVM registers are disabled, refer to DVM register section for more details. The TPS658629-Q1
remains in this state until all the supplies are sequenced and the internal delay TSYNCEND (5ms typ) has
expired.
POWER GOOD CHECK: Supplies that were powered up during the SUPPLYSEQ state will have their
power good flags checked during the POWER GOOD CHECK state (with exception of RTC_OUT ldo).
The POWER GOOD CHECK state ends and the NORMAL state is set when a power good fault is not
present. If a power good fault is detected, the POWER GOOD CHECK state will move to the SLEEP
REQUEST state when the boot timer expires.
NORMAL STATE: In this state write operations to the DVM registers are enabled and the external host
controls all the TPS658629-Q1 functions. The normal state operation ends if a fault condition (defined as
either a thermal fault, V(SYS) < VLOW_SYS or a supply power good fault) is detected or if hardware or
software commands trigger a sleep or reboot request. While in NORMAL mode, the host can mask any of
the power supply power good fault detection via I2C registers PGFLTMASK1 and PGFLTMASK2. Supplies
that have their power good fault detection masked will not end the normal state operation. However, the
status bit for the supply indicates that the output voltage is out of regulation. A RTC_OUT LDO power
good fault does not trigger a transition to SLEEP REQUEST.
Table 3-7. Sequencer Power Good Fault Masking
PGFLTMASK1 [Addr 0x4D]
Defaults in BOLD
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
MASK_PLDO8 MASK_PLDO7 MASK_PLDO6 MASK_PLDO4 MASK_PLDO3 MASK_PLDO2 MASK_PLDO1 MASK_PLDO0
MASK
PGOODLDO8
MASK
PGOODLDO7
MASK
PGOODLDO6
MASK
PGOODLDO4
MASK
PGOODLDO3
MASK
PGOODLDO2
MASK
PGOODLDO1
MASK
PGOODLDO0
Function
When 0
When 1
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
MASKED
PGFLTMASK2 [Addr 0x4E]
Defaults in BOLD
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
MASK_PSM3
MASK_PSM2
MASK_PSM1
MASK_PSM0
MASK_PLDO9 MASK_PLDO5
RSVD4E1
RSVD4E0
MASK
PGOODSM3
MASK
PGOODSM2
MASK
PGOODSM1
MASK
PGOODSM0
MASK
PGOODLDO9
MASK
PGOODLDO5
Function
NOT USED
NOT USED
When 0
When 1
UNMASKED
MASKED
UNMASKED
UNMASKED
UNMASKED
UNMASKED
NOT USED
NOT USED
MASKED
UNMASKED
MASKED
MASKED
MASKED
MASKED
NOT USED
NOT USED
SLEEP REQUEST: The SLEEP REQUEST state is set at anytime when a thermal fault condition is
detected. It is also set when the TPS658629-Q1 is in the NORMAL state followed by one of the events
shown below.
1. A hardware sleep request is detected at the RESUME pin.
2. A power good fault is detected at any of the integrated supplies
3. V(SYS_IN) < VLOW_SYS and the HOTPLUG timer has expired (t > THOTPLUG
4. SLEEP MODE is 1 (register 0x14, bit B3)
)
When the SLEEP REQUEST state is set an internal timer is started and bit SLEEPREQ=1 is set in
register STAT3 (address 0xBB). Writing EXITSLREQ to 1 (0x14, bit B1) returns the TPS658629-Q1 to the
NORMAL state. If no action is taken by the host, while SLEEP_REQUEST state is set, the NOPOWER pin
is pulled low when TWAIT1 expires and the SLEEP state is entered after the TWAIT timer expires.
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Table 3-8. Sequencer Control, LDO5/LDO9 Enable
SUPPLYENE [Addr 0x14]
Defaults in BOLD
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
LDO9_ON
LDO5_ON
SYSINEN
HOTDLY
SLEEP MODE
RSVD
EXITSLREQ
SOFT RST
SYS_IN LOW
VOLTAGE
SETS SLEEP
MODE
SET
TPS658629-Q1
IN SLEEP
MODE
SLEEP
REQUEST
EXIT
SOFTWARE
RESET
CONTROL
LDO9 ON/OFF LDO5 ON/OFF
HOT RESET
DEGLITCH
Function
When 0
When 1
CONTROL
CONTROL
CONTROL
5μsec min,
16μsec max
GO TO SLEEP
at T>Twait
OFF
OFF
DISABLED
NOT ACTIVE
NOT ACTIVE
FORCE
TRANSITION
TO NORMAL
STATE
REBOOT
REQUEST
ON
ON
ENABLED
5ms
SET SLEEP
SLEEP STATE: When the SLEEP state is set all supplies are set to OFF mode (with exception of
RTC_LDO) and the NOPOWER output is pulled low. A few internal blocks are still active, enabling
detection of system status changes that trigger the SLEEP state exit.
All I2C engines are reset and all RAM registers are reset to their default condition when the SLEEP state
is set. The RAM bits that have a default set via the non-volatile memory will keep the value they had
before the SLEEP state was set.
The SLEEP state ends when one of the following sequences is executed:
A. If SLEEP was set by thermal fault: The SLEEP state will end only when all external input supplies and
battery pack are removed and an UVLO condition is detected by the TPS658629-Q1, setting the
POWER UP state.
B. If SLEEP was not set by thermal fault: The SLEEP state will end when a hardware sleep exit request is
detected at RESUME pin or the Momentary Power Loss (MLP) feature is triggered bt the conditions in
either of the following scenarios:
–
Scenario 1: If V(SYS) < VLOW_SYS for greater than 5 ms and V2V2 is above the UVLO threshold, the
part transitions from normal to SLEEP state. For the part to exit from the SLEEP state and go to the
RTC_CHECK state, the following conditions must be true 1 second after entering the SLEEP state:
–
–
–
VBAT is greater than the voltage present on the COMP pin AND
V(SYS) > VLOW_SYS AND
V2V2 > UVLO
–
Scenario 2: If V(SYS) and V2V2 drop below the UVLO threshold before or after the transition to the
SLEEP state, the part will go to the power off state. If battery is re-inserted and the part enters the
SLEEP state in the first power cycle, it was in the SLEEP state until the MPL timer (programmed to
1 second) expires. After 1 second, the part will exit from SLEEP if the following conditions are met:
–
–
–
VBAT is greater than the voltage present on the COMP pin AND
V(SYS) > VLOW_SYS AND
V2V2 > UVLO
EXITING THE SLEEP STATE USING THE RESUME PIN: The figure below shows the timing relationship
needed on the RESUME pin to exit the sleep mode. This applies for all cases where the sleep mode entry
was triggered by any event other than a thermal fault.
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TRESUME(L)
TRESUME(H)
TRESUME(H)
RESUME PIN
TPS6586xx
MODE
NORMAL MODE
SLEEP MODE
SET SLEEP
NORMAL MODE
EXIT SLEEP
ENTER/EXIT
SLEEP
Figure 3-6. Entering and Exiting Sleep Mode Resume
EXITING THE SLEEP STATE USING AUTOBOOT: With the AUTOBOOT feature enabled, the
TPS658621D will transition from SLEEP state to normal state upon power-up if the following conditions
are met:
•
•
AC/USB detected
V(SYS) > VLOW_SYS
REBOOT REQUEST: The REBOOT REQUEST state is entered from the NORMAL state. It can be set via
software (SOFT_RST set to 1, register 0x14 Bit B0) or by a VIL level detection at HOTRST pin. When the
reboot request state is set an internal timer TWAIT (10ms typ) is started, and the NOPOWER pin is pulled
to ground. The reboot request ends when t > TWAIT. The REBOOT REQUEST will transition the device
state machine to the HARD REBOOT state. The REBOOT REQUEST is set if the HOTRST low pulse
width is greater than 10μsec (typ).
The status bit COMPDET=1 (register STAT2, address 0xBA) when the NORMAL state is entered after a
reboot cycle triggered by the HOTRST pin. The status bit COMPDET=0 when the NORMAL state is
entered, after a power-up, sleep cycle or software triggered reboot cycle.
The bit COMPDET is reset to 0 when bit SPARECC0=1, in register SPARE2 (address 0xCC). After
resetting the COMPDET bit the host needs to set SPARECC0=0 to enable detection of another reboot
cycle set via the HOTRST pin.
An interrupt is generated when the TPS658629-Q1 transitions from the POWER GOOD CHECK state to
the NORMAL state , COMPDET=1 and IMASK_COMP=0 in register INTMASK4 (address 0xB3). An
interrupt request is generated after the NORMAL state is set if IMASK_COMP=0 and COMPDET value
changes from 1 to 0.
Table 3-9. Reboot Flag Control
SPARE2 [Addr 0xCC]
Defaults in BOLD
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
SPARECC7
LDO6PG
SPARECC5 SPARECC4
SPARECC3
SPARECC2
SPARECC1
SPARE
SPARECC0
RESET
REBOOT BY
HOTRST
SECONDARY
LDO6PG
MASK
Function
SPARE
SPARE
SPARE
SPARE
SPARE
STATUS BIT
DO NOT
RESET
When 0
When 1
NOT USED
UNMASKED
NOT USED NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
MASKED
NOT USED NOT USED
NOT USED
NOT USED
NOT USED
RESET
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HARD REBOOT: The HARD REBOOT state powers down all the TPS658629-Q1 supplies, with exception
of the RTC_OUT LDO.
3.26 CNOPOWER CAPACITOR DISCHARGE
The external capacitor connected to the TNOPOWER pin is always discharged when the sequencer sets
NOPOWER=LO in the following states: POWER-UP, RTC, REBOOT REQUEST, HARD REBOOT and
SLEEP. For large capacitance values (above 330nF) the external capacitor may not be fully discharged
during reboot cycles, and as a result the NOPOWER pulse width may be slightly reduced when compared
to the value indicated in the parametric tables.
3.27 SEQUENCER STATUS
Sequencer status information is available at registers 0xBA, bit COMPDET and register 0xBB bits
SLEEPREQ and RESUME. See STATUS REGISTERS section for functional description of these bits.
3.28 SUPPLY SEQUENCING AND HOST INTERFACE
3.28.1 Integrated Supply Sequencing
The TPS658629-Q1 enables the implementation of complex supply sequencing. With the exception of
RTC_OUT, the integrated power-up sequencing starts when the TPS658629-Q1 state machine enters the
SUPPLYSEQ state. The RTC_OUT LDO is always enabled in the RTC state, which occurs before the
SUPPLYSEQ state, and the output of this LDO can be used to power an external processor or circuitry in
systems where the supply sequencing is controlled externally using pins SM0EN, SM1EN or SYNCEN.
Each supply rail is controlled by a combination of its default status (ON or OFF), its assigned sequencing
trigger group (INTERNAL, SM0EN, SM1EN or SYNCEN), and a delay time.
The default status (ON or OFF) of each rail is shown in Table 3-10.
If the default for a supply rail is ON the trigger group associated to the supply determines the control
signal that initiates the delay time to the start of the rail power up. There are four trigger groups, one
internal and three external pins:
INTERNAL This group is controlled by an internal signal that goes high when the TPS658629-Q1 goes
from the RTC_ON state to the SUPPLYSEQ state.
SM0EN
SM1EN
SYNCEN
This group is controlled by the falling edge of the SM0EN pin and starts when the pin
voltage is below its VIL level.
This group is controlled by the rising edge of the SM1EN pin and starts when the pin
voltage is above its VIH level.
This group is controlled by the rising edge of the SYNCEN pin and starts when the pin
voltage is above its VIH level.
The trigger group of each rail and its associated delay is shown in Table 3-10. If a supply rail has a default
state of ON and the appropriate trigger is high, the rail will be turned on after the delay time for that rail
has expired. The delay time starts when the trigger signal for that supply has gone high, while
SUPPLYSEQ state is set. No delays are available after NORMAL mode is set.
Table 3-10. TPS658629 Integrated Supply Power-Up Defaults
TPS658629 SETTINGS
DEFAULT
STATE
DEFAULT
VOLTAGE
SUPPLY
TRIGGER
DELAY
LDO0
LDO1
LDO2
LDO3
OFF
ON
1.2V
1.1V
1.2V
3.3V
SYNCEN
INTERNAL
INTERNAL
SYNCEN
3.75ms
Value applies to LDO0, LDO1
ON
2.5ms
Value applies to LDO2, LDO3
OFF
40
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Table 3-10. TPS658629 Integrated Supply Power-Up Defaults (continued)
TPS658629 SETTINGS
DEFAULT
STATE
DEFAULT
VOLTAGE
TRIGGER
DELAY
LDO4
LDO6
LDO7
LDO8
LDO5
LDO9
SM0
ON
OFF
OFF
OFF
OFF
ON
1.8V
2.85V
3.3V
INTERNAL
SYNCEN
SYNCEN
SYNCEN
15ms
15ms
Value applies to LDO6, LDO7 and LDO8
1.8V
2.85V
2.85V
1.2V
SYNCEN
2.5ms
Trigger applies to both LDO5 and LDO9
Value applies to LDO5, LDO9
ON
SM0EN
SM1EN
3.75ms
3.75ms
0ms
SM1
OFF
ON
1.050V
3.3V
SM2
INTERNAL
3.29 INTEGRATED SUPPLY SEQUENCING – SUPPLY ENABLE CONTROL
The ON or OFF mode for each supply is defined by the supply enable RAM control bits and enable pins
SM0EN, SM1EN and LDO4EN. The supply enable bits are located in registers SUPPLYENA,
SUPPLYENB, SUPPLYENC, SUPPLYEND, SUPPLYENE (see supply functional description for more
details). The functionality of the RAM bits and enable pins is dependent on the state set in the state
machine as follows:
When the NORMAL state is NOT set : The pins SM1EN , SM0EN and LDO4EN will always control the
ON or OFF modes for all supplies that use them as triggers. The supply enable RAM bits will control the
ON or OFF modes for the supplies.
When the NORMAL state is set: The supply enable RAM bits will always control the ON or OFF modes
for the supplies. The pins SM1EN, SM0EN and LDO4EN may control the ON or OFF modes for supplies
SM1, SM0 and LDO4. The enable pins do not control the ON or OFF modes of any other supplies.
During sequencing, the following RAM bits control the supply ON/OFF mode: LDO2 RAM bits, LDO4 RAM
bits, SM0 RAM bits and SM1 RAM bits.
When the NORMAL mode is set, SM0EN controls the SM0 ON/OFF mode, SM1EN controls the SM1
ON/OFF mode and LDO4EN controls the LDO4 ON/OFF mode.
3.30 INTEGRATED SUPPLY SEQUENCING – POWER-DOWN
To start a power down sequence the SLEEP REQUEST or REBOOT REQUEST states must be set. Once
one of those two states is set the trigger pins are active again and they will control the ON/OFF state of
the supplies associated with that trigger group. The device will enter the SLEEP or HARD REBOOT state
10ms after the SLEEP REQUEST or REBOOT REQUEST is initiated. Any supply still active when the
SLEEP or HARD REBOOT state is entered will be immediately disabled. This is the default turn off
condition for any supply associated with the INTERNAL sequencing trigger group.
For example, if a supply has a default state of OFF and it has SM1EN as the selected factory trigger: this
supply will not power up during the SUPPLYSEQ state when SM1EN goes high. If it is enabled during the
NORMAL state and is still enabled when the SLEEP REQUEST or REBOOT REQUEST states are
entered, this supply will be turned off on the falling edge of SM1EN as this is its assigned trigger group
programmed at the factory.
If LDO4EN is set LO by the host when the TPS658629-Q1 enters the SLEEP REQUEST or REBOOT
REQUEST states, the LDO4 supply will turn off only when the HARD REBOOT or SLEEP states are set.
The LDO4PG pin will be pulled low when LDO4EN is below VIL, with no delay.
All the supplies are turned off at the same time when the TPS658629-Q1 enters the SLEEP or HARD
REBOOT state.
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3.31 HOST INTERFACE PINS
The TPS658629-Q1 devices have multiple signals that can be used by the external system to execute
power sequencing operations or verify the system status. Those signals are generated as follows:
1. Power supply status (2V2 logic level) : SM0PG, SM1PG, LDO4PG – A HI level indicates that the
supply is on and the regulation voltage is valid. A LO level indicates either that the supply voltage is
out of regulation or that the supply has been disabled.
2. External system and host control (V32K pin logic level): The NOPOWER, NORTC, and OUT32K pins
may be used to interface to external hosts, controlling the host reset and executing host-controlled
power-up sequencing.
3.32 EXTERNAL 32 kHz
The TPS658629-Q1 outputs a 32 kHz clock (pin OUT32K) that can be used by the external system. The
OUT32K output starts when the NORTC pin is above VIH and V32K is valid. The 32 kHz can be derived
either from an internal 32kHz oscillator or from a crystal-based clock, selectable via I2C using bit 6 of the
RTC_CTRL (Addr 0xC0) register (see the Real Time Clock section). However, only the crystal-based
clock is output to the OUT32K pin.
3.33 SUPPLY INPUT PIN CONNECTION
The input pins for all supplies (VIN_LDO01, VIN_LDO23, VIN_LDO4, VIN_LDO678, VIN_LDO9) enable
optimization of the overall system power architecture by connecting lower output voltage supplies to
intermediate rails or external rails. Care must be taken to ensure that the input pin for each integrated
supply is powered when the supply is enabled during the power-up sequencing. Failure to do so will result
in a power good fault detection with a potential lock-up situation. The input pins VIN_SM0, VIN_SM1,
VIN_SM2 must be connected to the SYS pin
3.34 HOST INTERFACE
The TPS658629-Q1 may be used in systems where the sequencing is controlled by an external host or
housekeeping circuit, as well as in systems where stand-alone sequencing is a requirement. For host
controlled systems the RTC_OUT LDO can be used as the supply that powers the external sequencing
control and the NOPOWER and NORTC pin signals are used as resets for the external circuit.
Power applied
AC, USB OR BAT
VUVLO
2V2
VLOW_SYS
HOST CONTROLLED
SEQUENCING :
SYS
RTC_OUT/BBAT
32KHZ_OUT
VRTCLOW
RTC_OUT SUPPLIES
EXTERNAL CIRCUIT
THAT DRIVES SUPPLY
POWER-UP USING
TRIGGER PINS SM0EN,
SM1EN, SYNCEN
32kHZ
X
ENABLE
PINS
NOPOWER
NORTC
X
X
Z
TPOR=8mSec
TNOPOWER
TNORTC
EXTERNAL
CONTROL
CIRCUIT RESET
6586XX POWER-UP
HOST-BASED SEQUENCING OF SUPPLIES
SEQUENCING COMPLETED
Figure 3-7. Host Controlled Startup
42
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AC, USB
or BAT
VUVLO
2V2
VLOW_SYS
SYS
VRTCLOW
RTC_OUT/BBAT
32KHZ_OUT
Stable
ALL
ENABLES
LDO4
1.25 V
TNOPOWER
Capacitor
NOPOWER
z
NORTC
TAC Deglitch = 22.5ms
TSYS Cap Charging = 10ms
TLDO4 UP = 15ms
TBOOT = 75ms
TPOR = 8ms
Check = 3ms
Internal Timing Power Up Sequencing = 121.5ms
Check = 3ms
TNOPOWER capacitor
charging up to 1.25V.
0.25 ´ capacitor value 25ꢀ
NOTE: For the 32kHz clock to stabilize by 320ms, the TNOPWER capacitor should be greater than (185ms/0.25)nF.
Figure 3-8. TPS658629-Q1 Controlled Startup
90%
95%
Output Voltage
PG Signal
5ms
Figure 3-9. Power Good Timing
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3.35 INTEGRATED SUPPLIES – ENABLE CONTROL, DVM CONTROL
3.35.1 DVM and Non-DVM Supplies
The TPS658629-Q1 has two types of voltage control for the integrated supplies:
1. DVM supplies: SM0, SM1, LDO2 and LDO4 are DVM supplies with dedicated register sets that enable
a controlled transition from an initial voltage to a final voltage. The initial voltage, final voltage, and
voltage transition start time are set via I2C. SM0 and SM1 have I2C programmable slew rate.
2. NON-DVM supplies: LDO0, LDO1, LDO3, LDO5, LDO6, LDO7, LDO8, LDO9, SM2 and RTC_OUT
outputs can be changed, but without slew rate and transition start time control. The output of these
supplies will be changed to the new value as soon as TPS658629-Q1 sends the ACK of the I2C
command setting the new output voltage.
3.35.2 DVM and Non-DVM Supply Enable
All the integrated supplies can be turned on/off by RAM enable bits. All the supplies (with exception of
LDO5, LDO9 and RTC_OUT LDO's) have two enable bits on distinct registers (registers 0x10, 0x11, 0x12,
0x13, 0x14). A supply will be enabled when ANY of its enable bits, in the registers below, are set to 1.
Each supply will be disabled when ALL of the enable bits for that supply are set to 0. For example: SM0
enabled: SM0_ENA=1 OR SM0_ENB=1, SM0 disabled: SM0_ENA=0 AND SM0_ENB=0
Table 3-11. SM0-2, LDO0-9 Control
SUPPLYENA [Addr 0x10]
Defaults in BOLD
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
RSVD107
RSVD106
RSVD105
RSVD104
LDO2_ENA1 LDO2_ENA0
SM0_ENA
SM1_ENA
LDO2
CONTROL
LDO2
CONTROL
SM0
CONTROL
SM1
CONTROL
Function
NOT USED
NOT USED
NOT USED
NOT USED
SUPPLYENB [Addr 0x11]
Defaults in BOLD
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
RSVD117
RSVD116
RSVD115
RSVD114
LDO2_ENB1 LDO2_ENB0
SM0_ENB
SM1_ENB
LDO2
CONTROL
LDO2
CONTROL
SM0
CONTROL
SM1
CONTROL
Function
NOT USED
NOT USED
NOT USED
NOT USED
SUPPLYENC [Addr 0x12]
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
SM2_ONC
LDO8_ONC
LDO7_ONC
LDO6_ONC
LDO4_ONC
LDO3_ONC
LDO1_ONC
LDO0_ONC
SM2
CONTROL
LDO8
CONTROL
LDO7
CONTROL
LDO6
CONTROL
LDO4
CONTROL
LDO3
CONTROL
LDO1
CONTROL
LDO0
CONTROL
Function
SUPPLYEND [Addr 0x13]
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
SM2_OND
LDO8_OND
LDO7_OND
LDO6_OND
LDO4_OND
LDO3_OND
LDO1_OND
LDO0_OND
SM2
CONTROL
LDO8
CONTROL
LDO7
CONTROL
LDO6
CONTROL
LDO4
CONTROL
LDO3
CONTROL
LDO1
CONTROL
LDO0
CONTROL
Function
SUPPLYENE [Addr 0x14]
Defaults in BOLD
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
SLEEP
MODE
Bit Name
LDO9_ON
LDO5_ON
SYSINEN
HOTDLY
RSVD
EXITSLREQ
SOFT RST
SYS_IN LOW
VOLTAGE
SETS SLEEP DEGLITCH Q1 IN SLEEP
SET
SLEEP
REQUEST
EXIT
LDO9
ON/OFF
CONTROL
LDO5
ON/OFF
CONTROL
SOFTWARE
RESET
CONTROL
HOT RESET TPS658629-
Function
When 0
MODE
MODE
CONTROL
GO TO
SLEEP at
T>Twait
5μsec min,
16μsec max
OFF
OFF
DISABLED
NOT ACTIVE
NOT ACTIVE
44
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Table 3-11. SM0-2, LDO0-9 Control (continued)
FORCE
TRANSITION
TO NORMAL
STATE
REBOOT
REQUEST
When 1
ON
ON
ENABLED
5ms
SET SLEEP
LDO5 and LDO9 will be turned on when LDO5_ON is 1 or LDO9_ON is 1, respectively. The RTC_OUT
LDO enable bits are located in the RTC control register, see real time clock section for details.
The supply enable defaults are unique for each device. See App Notes for device specific settings.
3.35.3 DVM Supplies - Voltage Transition Control
The output voltage for the DVM supplies can be set to one of the values programmed in the voltage
setting registers SM0V1, SM0V2, SM1V1, SM2V2, LDO2AV1, LDO2AV2, LDO2BV1, LDO2BV2, LDO4V1
and LDO4V2 as defined in registers VCC1 and VCC2.
The voltage change for the DVM supplies is usually done with 2 I2C write commands:
1. The host writes the new voltage to the voltage setting register for the supply(s) that will have an output
voltage modification.
2. The voltage change starts by setting specific control bits in registers VCC1 and VCC2.
Bits VS in registers VCC1 and VCC2 select the next voltage for the DVM supplies. A voltage change is
started when ANY of the GO bits for the supply is set to 1. At the end of the voltage transition the GO bits
are cleared by the internal logic.
Table 3-12. DVM Supply Control
VCC1 [Addr 0x20]
Defaults in BOLD
B0
Bit Number
B7
LDO4VS
B6
B5
B4
B3
B2
B1
Bit Name
LDO4GO
LDO2AVS2
LDO2AGO2
SM0VS1
SM0GO1
SM1VS1
SM1GO1
LDO4 VOLTAGE
SELECTION
Function
LDO2 VOLTAGE SELECTION SM0 VOLTAGE SELECTION SM1 VOLTAGE SELECTION
SELECT
VOLTAGE
SET BY
SELECT
VOLTAGE
SET BY
SELECT
VOLTAGE
SET BY
HOLD
CURRENT
VOLTAGE
HOLD
CURRENT
VOLTAGE
HOLD
CURRENT
VOLTAGE
HOLD
CURRENT
VOLTAGE
When 0
When 1
NOT USED
LDO4V1
SM0V1
SM1V1
RAMP TO
VOLTAGE
SELECTED
BY
SELECT
VOLTAGE
SET BY
RAMP TO
VOLTAGE
SELECTED
BY LDO4VS
SELECT
VOLTAGE
SET BY
RAMP TO
VOLTAGE
SELECTED
BY SM0VS1
SELECT
VOLTAGE
SET BY
RAMP TO
VOLTAGE
SELECTED
BY SM1VS1
NOT USED
LDO4V2
SM0V2
SM1V2
LDO2BVS1
VCC2 [Addr 0x21]
Defaults in BOLD
B0
Bit Number
B7
LDO2BVS1
B6
B5
B4
B3
B2
B1
Bit Name
LDO2BGO1
LDO2AVS1
LDO2AGO1
SM0VS2
SM0GO2
SM1VS2
SM1GO2
LDO2 VOLTAGE
SELECTION
Function
LDO2 VOLTAGE SELECTION I SM0 VOLTAGE SELECTION SM1 VOLTAGE SELECTION
SELECT
VOLTAGE
SET BY
SELECT
VOLTAGE
SET BY
SELECT
VOLTAGE
SET BY
HOLD
CURRENT
VOLTAGE
HOLD
CURRENT
VOLTAGE
HOLD
CURRENT
VOLTAGE
HOLD
CURRENT
VOLTAGE
When 0
When 1
NOT USED
LDO2BV1
SM0V1
SM1V1
RAMP TO
VOLTAGE
SELECTED
BY
RAMP TO
VOLTAGE
SELECTED
BY
SELECT
VOLTAGE
SET BY
SELECT
VOLTAGE
SET BY
RAMP TO
VOLTAGE
SELECTED
BY SM0VS2
SELECT
VOLTAGE
SET BY
RAMP TO
VOLTAGE
SELECTED
BY SM1VS2
NOT USED
LDO2BV2
SM0V2
SM1V2
LDO2BVS1
LDO2BVS1
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Table 3-13. SM0 and SM1 Voltage Selection Register Settings
SM0 OUTPUT VOLTAGE SELECTION
SM1 OUTPUT VOLTAGE SELECTION
SM1GO1=1 OR SM1GO2=1 STARTS
SM0GO1=1 OR SM0GO2=1 STARTS
VOLTAGE TRANSITION
SM0VS1 SM0VS2
SM1VS1 SM1VS2
VOLTAGE TRANSITION
TO VALUE SET BY REGISTER :
TO VALUE SET BY REGISTER
0
0
1
1
0
1
0
1
SM0V1
SM0V2
SM0V2
SM0V2
0
0
1
1
0
1
0
1
SM1V1
SM1V2
SM1V2
SM1V2
Table 3-14. SM0 Voltage Selection by SM0EN
SM0 ACTIVE LEVEL
SM0EN
SM0 OUTPUT VOLTAGE
0
0
0
1
1.2V
OFF
The SM0 output voltage value and transition is controlled by the SM0EN pin and SM0VS1/SMVS2.
NOTE
During a HI to LO transition of SM0EN (enabling SM0), the SM0 output will power up to the
pre-defined default state regardless of the setting set via I2C prior to SM0 being disabled.
Table 3-15. SM0 Output Voltage Settings Available for SM0EN Selection
RANGE
[4:0]
VOUT (V)
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
[4:0]
VOUT (V)
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
[4:0]
VOUT (V)
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
[4:0]
VOUT (V)
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
0.725V–1.50V
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Table 3-16. LDO4 Voltage Selection Register Settings
LDO4 OUTPUT VOLTAGE SELECTION
LDO4GO=1 STARTS VOLTAGE TRANSITION TO
LDO4VS
VALUE SET BY REGISTER
0
1
LDO4V1
LDO4V2
The LDO2 output voltage selection and GO bit functionality is shown below.
1. LDO2AGOn bits are not active
2. LDO2BGO1=1 starts a voltage transition to the voltage selected by LDO2BV1, LDO2BV2 and
LDO2BVS1
3. LDO2 voltage transition starts when SM0EN is set to LO
When the LDO2 output voltage is controlled by the SM0EN (CORECTRL) pin, registers LDO2AV2 and
LDO2AV1 define the output voltage:
46
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3.35.4 DVM Supply Voltage Transition
During a voltage transition the output voltage will be stepped from the currently programmed voltage to the
new target voltage as shown below. The slew rate from the initial voltage to the final voltage for SM0 and
SM1 can be selected using the I2C registers SM0SL (ADDRESS = 0x25) and SM1SL (ADDRESS = 0x28)
respectively. LDO2 and LDO4 have the slew rate fixed internally to 7mV/μSec(typ).
Figure 3-10. SM0 and SM1 Dynamic Voltage Slew Rate Example
3.36 SM0, SM1, SM2 CONVERTERS
The TPS658629-Q1 has three highly efficient step down synchronous converters. The integration of the
power stage switching FETs reduces the external component count, and only the external output inductor
and filter capacitor are required. The integrated power stage supports 100% duty cycle operation. The
converters have two possible modes of operation: a 2.25MHz fixed frequency pulse width modulation
(PWM) mode at moderate to heavy loads, and a pulse frequency modulation (PFM) mode at light loads.
The converters SM0, SM1 and SM2 output voltages are programmable via I2C registers SMnV1 and
SMnV2 (SM0 and SM1) and SUPPLYV2 (SM2):
NOTE
VIN_SM0, VIN_SM1 AND VIN_SM2 PINS SHOULD ALWAYS BE EXTERNALLY
CONNECTED TO SYS PIN
3.36.1 SM0, SM1 DVM Buck Converters - Output Voltage Registers
Table 3-17. DVM Supply Voltage and Slew Rate Selection – SM0 and SM1
SM1V1 [Addr 0x23]
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
RSVD237
NOT USED
RSVD236
NOT USED
RSVD235
NOT USED
SM1V1[4]
SM1V1[3]
SM1V1[2]
SM1V1[1]
SM1V1[0]
SM1 SUPPLY OUTPUT VOLTAGE
SM1V2 [Addr 0x24]
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Table 3-17. DVM Supply Voltage and Slew Rate Selection – SM0 and SM1 (continued)
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
RSVD247
NOT USED
RSVD246
NOT USED
RSVD245
NOT USED
SM1V2[4]
SM1V2[3]
SM1V2[2]
SM1V2[1]
SM1V2[0]
SM1 SUPPLY OUTPUT VOLTAGE
SM1SL [Addr 0x25]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
Function
RSVD257
RSVD256
NOT USED
RSVD255
NOT USED
RSVD254
NOT USED
RSVD253
NOT USED
SM1SL[2]
SM1SL[1]
SM1SL[0]
NOT USED
SM1 SUPPLY RAMP RATE
SM0V1 [Addr 0x26]
Bit Number
B7
B6
B5
B4
B3
B2
SM0V1[2]
B1
B0
Bit Name
Function
RSVD267
RSVD266
NOT USED
RSVD265
NOT USED
SM0V1[4]
SM0V1[3]
SM0V1[1]
SM0V1[0]
NOT USED
SM0 SUPPLY OUTPUT VOLTAGE
SM0V2 [Addr 0x27]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
Function
RSVD277
RSVD276
NOT USED
RSVD275
NOT USED
SM0V2[4]
SM0V2[3]
SM0V2[2]
SM0V2[1]
SM0V2[0]
NOT USED
SM0 SUPPLY OUTPUT VOLTAGE
SM0SL [Addr 0x28]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
Function
RSVD287
RSVD286
NOT USED
RSVD285
NOT USED
RSVD284
NOT USED
RSVD283
NOT USED
SM0SL[2]
SM0SL[1]
SM0SL[0]
NOT USED
SM0 SUPPLY RAMP RATE
The available output voltages and slew rates are shown below.
Table 3-18. SM0V1[4:0] / SM0V2[4:0] / Output Voltage Settings
RANGE
[4:0]
VOUT (V)
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
[4:0]
VOUT (V)
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
[4:0]
VOUT (V)
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
[4:0]
VOUT (V)
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
0.725V–1.50V
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Table 3-19. SM1V1[4:0] / SM1V2[4:0] Output Voltage Settings
RANGE
[4:0]
VOUT (V)
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
[4:0]
VOUT (V)
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
[4:0]
VOUT (V)
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
[4:0]
VOUT (V)
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
0.725V–1.50V
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
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Table 3-20. SM0SL[2:0] and SM1SL[2:0] Slew Rate Settings
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
SMxSL
[2:0]
SLEW RATE
(mV/μs)
000
100
INSTANTLY
0.88
001
101
0.11
1.76
010
110
0.22
3.52
011
0.44
111
7.04
Table 3-21. Non-DVM supply Voltage selection - SM2, LDO8
SUPPLYV2 [Addr 0x42]
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
VLDO8[2]
VLDO8[1]
VLDO8[0]
VSM2[4]
VSM2[3]
VSM2[2]
VSM2[1]
VSM2[0]
LDO8 OUTPUT VOLTAGE
SM2 OUTPUT VOLTAGE
Table 3-22. VSM2[4:0] Output Voltage Settings
RANGE
[4:0]
VOUT (V)
3.000
3.050
3.100
3.150
3.200
3.250
3.300
3.350
[4:0]
VOUT (V)
3.400
3.450
3.500
3.550
3.600
3.650
3.700
3.750
[4:0]
VOUT (V)
3.800
3.850
3.900
3.950
4.000
4.050
4.100
4.150
[4:0]
VOUT (V)
4.200
4.250
4.300
4.350
4.400
4.450
4.500
4.550
3.0V–4.55V
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
3.36.2 PWM Operation
During PWM operation the converters use a fast response voltage mode controller scheme with input
voltage feed-forward, enabling the use of small ceramic input and output capacitors. At the beginning of
each clock cycle the high side channel MOSFET switch is turned on, and the oscillator starts the voltage
ramp. The inductor current will ramp-up until the ramp voltage reaches the error amplifier output voltage,
when the comparator trips and the high-side channel MOSFET switch is turned off. Internal adaptive
break-before-make circuits turn on the integrated low-side MOSFET switch after an internal, fixed dead-
time delay, and the inductor current ramps down, until the next cycle is started. When the next cycle starts
the ramp voltage is reset to its low value and the high-side channel MOSFET switch is turned on again.
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Figure 3-11. PWM Control
3.36.3 PFM Mode Operation
The TPS658629-Q1 SM0, SM1 and SM2 buck converters can be set to operate only in PWM mode or to
switch automatically between PFM and PWM modes, via the I2C interface. While in the Pulsed Frequency
Mode the converters operate with reduced switching frequency and with a minimum quiescent current to
maintain high efficiency.
In PFM mode the converter will regulate the output voltage to 1% above the nominal output voltage. To
determine when to transition between the modes, the inductor current is monitored, and the PFM mode is
set when the inductor ripple current approaches zero. For duty cycles above 85% the PFM mode is
entered for load currents below the threshold IPFM(ENTER).
V
(VIN_SMx)
IPFM(ENTER)
=
34W
(1)
In PFM mode the output voltage is monitored by a voltage comparator, which regulates the output voltage
to the programmed value VO(SM1). If the output voltage is below VO(SM1) the PFM control circuit turns on the
power stage, applying a burst of pulses to increase the output voltage. When the output voltage exceeds
the target regulation voltage VO(SM1) the power stage is disabled, and the output voltage will drop until it is
below the regulation voltage target, when the power stage is enabled again.
The PFM operation is disabled and PWM operation set if one of the following events happens during PFM
operation:
1. The burst operation exceeds 7μs, typ.
2. The output voltage falls below 3% of the target regulation voltage in PFM mode (2% of the nominal
output voltage in PWM mode)
3.36.4 Setting the PWM/PFM Mode
In TPS658629-Q1 the PWM mode can be forced for each converter by setting the bit SMn_PWM to 1 in
the SMODE1 register. If bits SMn_GPIO is 1, the GPIO will control the PWM or PFM mode setting, and
bits SMn_PWM are ignored.
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Table 3-23. SM0,SM1, SM2 PWM/PFM Mode Selection
SMODE1 [Addr 0x47]
Default to 0
B0
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
RSVD477
SPARE
SM2_GPIO
SM1_GPIO
SM0_GPIO
RSVD473
SPARE
SM2_PWM
SM1_PWM
SM0_PWM
SM2 AUTO
PFM
SM1 AUTO
PFM
SM0 AUTO
PFM
SM2 PWM
MODE ON
SM1 PWM
MODE ON
SM0 PWM
MODE ON
CONTROL
CONTROL
CONTROL
SELECTION SELECTION SELECTION
Table 3-24 details how the GPIO control is implemented. Note that the GPIO1 polarity indicated in
Table 3-24 is controlled by bit GPIOINV, register 0x5E.
Table 3-24. GPIO1 PWM/PFM Mode Control
SMx_GPIO
SMx_PWM
GPIO1 POLARITY
GPIO1
CONVERTER MODE
Auto PWM/PFM
PWM Only
0
0
1
1
1
1
0
1
x
x
x
x
x
x
x
0
1
0
1
x
Inverted
Inverted
Not Inverted
Not Inverted
PWM Only
Auto PWM/PFM
Auto PWM/PFM
PWM Only
3.36.5 Output Discharge Switches
When the SM0, SM1 and SM2 converters are disabled, an integrated switch automatically discharges the
converter output capacitor.
The converter output discharge switches are always enabled when NORMAL state is set and during the
SUPPLYSEQ state.
3.36.6 Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It
provides more headroom for both the voltage drop at a load step and the voltage increase at a load throw-
off. This improves load transient behavior.
At light loads, in which the converter operate in PFM Mode, the output voltage is regulated typically 1%
higher than the nominal value. In case of a load transient from light load to heavy load, the output voltage
will drop until it reaches the COMP LOW threshold set to 2% below the nominal value and enters PWM
mode. During a load throw off from heavy load to light load, the voltage overshoot is also minimized due to
active regulation turning on the low-side channel switch.
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Figure 3-12. Voltage Positioning
3.36.7 Soft Start
SM0, SM1 and SM2 have an internal soft start circuit that limits the inrush current during start-up. An initial
delay (170µs typ) from the converter enabled command to the converter effectively being operational is
required to ensure that the internal circuits of the converter are properly biased. At the end of that initial
delay the soft start is initiated and the internal compensation capacitor is charged with a low value current
source. The soft start time is typically 250µs, with the output voltage ramping from 5% to 95% of the final
target value.
3.36.8 Dropout Operation at 100% Duty Cycle
The TPS658629-Q1 buck converters offer a low input to output voltage difference while still maintaining
operation when the duty cycle is set to 100%. In this mode of operation the high-side FET is constantly
turned on to enable operation with a low input voltage. The dropout operation will start if :
V(VIN_SMx) ≤ V(SMx) + ILx × (RDSON(PSMx) + RL)
(2)
where ILx is the output current plus ½ inductor ripple current and RL is the DC resistance of the inductor.
3.36.9 Output Voltage Monitoring
The output voltage of converters SM0, SM1 and SM2 is monitored by internal comparators, and an output
low voltage condition is detected when the output voltage is below 90% of the programmed value. The
power good comparator is disabled for all converters during output voltage transitions. The power
comparator on SM2 power good is also disabled when battery tracking mode is set.
3.36.10 Phase Control in PWM Mode
By default the SM0, SM1 and SM2 converters operate with phased clocking when they are in PWM mode,
with converter SM0 as the master. Converters SM0 and SM1, when enabled, will run 90 and 180 degrees
out of phase with SM0.
3.36.11 Integrated Snubber and Current Limit
The SM2 converter has an integrated electronic snubber that is used to improve transient response when
operating under conditions which cause the inductor current to flow in the negative direction (into the Ln
node).
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3.37 LINEAR REGULATORS
The TPS658629-Q1 offers ten integrated linear dropout regulators (LDOs), designed to be stable over the
operating load range with use of external ceramic capacitors. The output voltage can be programmed via
I2C. All of the LDOs, with the exception of LDO5 and RTC_OUT LDO, have uncommitted input power
supply pins (VIN_LDO01, VIN_LDO23, VIN_LDO4, VIN_LDO678, VIN_LDO9) which should be externally
connected to a number of system rails including SYS and the output of SM2.
The LDO5 and RTC_OUT regulators are internally connected to the SYS pin.
3.37.1 Output Voltage Monitoring
Internal power good comparators monitor the LDO outputs and detect when the output voltage is below
95% of the programmed value. This information is used by the TPS658629-Q1 to generate interrupts or to
trigger distinct operating modes, depending on specific I2C register settings. See interrupt and sequencing
controller section for additional details.
3.37.2 LDO2 DVM LDO - Output Voltage Registers
Registers 0x29, 0x2A, 0x2F and 0x30 set the output voltage for LDO2. The slew rate is internally fixed to
7mV/μSec (typ).
Table 3-25. DVM Supply Voltage Selection – LDO2
LDO2AV1 [Addr 0x29]
Defaults in BOLD
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
RSVD297
NOT USED
RSVD296
NOT USED
RSVD295
NOT USED
LDO2AV1[4] LDO2AV1[3] LDO2AV1[2] LDO2AV1[1] LDO2AV1[0]
LDO2 SUPPLY OUTPUT VOLTAGE (See Table 3-26)
LDO2AV2 [Addr 0x2A]
Defaults in BOLD
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
RSVD2A7
NOT USED
RSVD2A6
NOT USED
RSVD2A5
NOT USED
LDO2AV2[4] LDO2AV2[3] LDO2AV2[2] LDO2AV2[1] LDO2AV2[0]
LDO2 SUPPLY OUTPUT VOLTAGE (See Table 3-26)
LDO2BV1 [Addr 0x2F]
Defaults in BOLD
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
RSVD2F7
NOT USED
RSVD2F6
NOT USED
RSVD2F5
NOT USED
LDO2BV1[4] LDO2BV1[3] LDO2BV1[2] LDO2BV1[1] LDO2BV1[0]
LDO2 SUPPLY OUTPUT VOLTAGE (See Table 3-26)
LDO2BV2 [Addr 0x30]
Defaults in BOLD
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
RSVD307
NOT USED
RSVD306
NOT USED
RSVD305
NOT USED
LDO2BV2[4] LDO2BV2[3] LDO2BV2[2] LDO2BV2[1] LDO2BV2[0]
LDO2 SUPPLY OUTPUT VOLTAGE (See Table 3-26)
The available output voltages for LDO2 are shown below:
Table 3-26. LDO2AV1/2[4:0] and LDO2BV1/2[4:0] Settings
RANGE
[4:0]
VOUT (V)
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
[4:0]
VOUT (V)
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
[4:0]
VOUT (V)
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
[4:0]
VOUT (V)
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
0.725V–1.50V
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
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3.37.3 LDO4 DVM LDO – Output Voltage Registers
Registers 0x32 and 0x33 set the output voltage for LDO4. The slew rate is internally fixed to 7mV/μSec
(typ).
Table 3-27. DVM Supply Voltage Selection – LDO4
LDO4V1 [Addr 0x32]
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
RSVD327
NOT USED
RSVD326
NOT USED
RSVD325
NOT USED
LDO4V1[4]
LDO4V1[3]
LDO4V1[2]
LDO4V1[1]
LDO4V1[0]
LDO4 SUPPLY OUTPUT VOLTAGE (See Table 3-28)
LDO4V2 [Addr 0x33]
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
RSVD337
RSVD336
NOT USED
RSVD335
NOT USED
LDO4V2[4]
LDO4V2[3]
LDO4V2[2]
LDO4V2[1]
LDO4V2[0]
NOT USED
LDO4 SUPPLY OUTPUT VOLTAGE (See Table 3-28)
The available output voltages are shown below:
Table 3-28. LDO4V1[4:0] and LDO4V2[4:0] Output Voltage Settings
RANGE
[4:0]
VOUT (V)
1.700
1.725
1.750
1.775
1.800
1.825
1.850
1.875
[4:0]
VOUT (V)
1.900
1.925
1.950
1.975
2.000
2.025
2.050
2.075
[4:0]
VOUT (V)
2.100
2.125
2.150
2.175
2.200
2.225
2.250
2.275
[4:0]
VOUT (V)
2.300
2.325
2.350
2.375
2.400
2.425
2.450
2.475
1.7V–2.475V
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
3.37.4 LDO Output Discharge Switches
All LDO's, with exception of RTC_OUT LDO, have internal discharge resistors that are connected to
ground via internal switches when the LDO is turned OFF, thus discharging the output capacitor.
The LDO output discharge switches are always enabled when NORMAL state is set and during the
SUPPLYSEQ state.
3.37.5 Non-DVM Supply Voltage Settings
Registers SUPPLYV1, SUPPLYV2, SUPPLYV3, SUPPLYV4 and SUPPLYV6 define the voltage settings
for the non-DVM supplies.
Register SUPPLYV4 has two bits that control the RTC_OUT LDO functionality. The RTC_OUT LDO will
be enabled when LDORTC_ON is 1. The power good threshold for the RTC_OUT LDO can be set as
follows: 2.4V (RTC_PGOOD is 1), 2.0V (RTC_PGOOD is 0).
Table 3-29. Non-DVM Supply Voltage Selection
SUPPLYV1 [Addr 0x41]
Bit Name
Function
VLDO0[2]
VLDO0[1]
VLDO0[0]
VLDO1[4]
VLDO1[3]
VLDO1[2]
VLDO1[1]
VLDO1[0]
VLDO6[0]
LDO0 OUTPUT VOLTAGE (See Table 3-31)
LDO1 OUTPUT VOLTAGE (See Table 3-30)
SUPPLYV3 [Addr 0x43]
Bit Name
Function
LDO7_SW
SPARE
LDO6_SW
SPARE
VLDO7[2]
VLDO7[1]
VLDO7[0]
VLDO6[2]
VLDO6[1]
LDO7 OUTPUT VOLTAGE (See Table 3-31) LDO6 OUTPUT VOLTAGE (See Table 3-31)
SUPPLYV4 [Addr 0x44]
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Table 3-29. Non-DVM Supply Voltage Selection (continued)
Bit Name
Function
LDORTC_ON RTC_PGOOD
VRTC[2]
VRTC[1]
VRTC[0]
VLDO3[2]
VLDO3[1]
VLDO3[0]
RTC_LDO
ON/OFF
RTC_OUT
LOW
RTC OUTPUT VOLTAGE (See Table 3-31) LDO3 OUTPUT VOLTAGE (See Table 3-31)
CONTROL
VOLTAGE
THRESHOLD
SUPPLYV6 [Addr 0x46]
Bit Name
Function
RSVD467
RSVD466
VLDO9[2]
VLDO9[1]
VLDO9[0]
VLDO5[2]
VLDO5[1]
VLDO5[0]
NOT USED
NOT USED
LDO9 OUTPUT VOLTAGE (See Table 3-31) LDO5 OUTPUT VOLTAGE (See Table 3-31)
The available output voltages for the non-DVM supplies are shown below:
Table 3-30. VLDO1[4:0] Settings
RANGE
[4:0]
VOUT (V)
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
[4:0]
VOUT (V)
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
[4:0]
VOUT (V)
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
[4:0]
VOUT (V)
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
0.725V–1.50V
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Table 3-31. VLDO3/5/6/7/8/9[2:0] and VRTC[2:0] Settings
VLDOx[2:0]
000
VOUT (V)
1.25
VLDOx[2:0]
100
VOUT (V)
2.70
2.85
3.10
3.30
001
1.50
101
010
1.80
110
011
2.50
111
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Table 3-32. VLDO0[2:0] Settings
VLDOx[2:0]
000
VOUT (V)
1.20
VLDOx[2:0]
100
VOUT (V)
2.70
001
1.50
101
2.85
010
1.80
110
3.10
011
2.50
111
3.30
Setting the RTC_OUT output voltage below the RTC_OUT power good threshold will result in a NORTC
pulse always being generated during the reboot cycle or when exiting sleep. Setting the RTC_OUT output
voltage below VUVLO_RTC disables the use of the internal real time clock counter and xtal oscillator.
3.38 BOOST CONVERTER
The TPS658629-Q1 has an integrated boost converter (SM3) that is optimized to drive white LED’s
connected in a series configuration. Up to six series white LED’s can be driven, with programmable
current and duty cycle adjustable via a dedicated I2C register.
The SM3 boost Converter (SM3) has a 29v, 500mA low side integrated power stage switch, which drives
the external inductor. Another integrated 29V, 25mA switch (LED switch) is used to modulate the external
white LED’s brightness.
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Figure 3-13. Boost Converter Block Diagram
The SM3 boost converter operates in a pulse frequency modulation (PFM) scheme with constant peak
current control. This control scheme maintains high efficiency over the entire load current range and
enables the use of small external components, as the switching frequency can reach up to 1 MHz
depending on the load conditions. The LED current ripple is defined by the external inductor size.
The converter monitors the sense voltage at pin FB3, and turns on the integrated power stage switch
when V(FB3) is below the 250mV (typ) internal reference voltage. The integrated power switch turns off
when the inductor current reaches the internal peak current limit or if the switch is on for a period longer
than the maximum on-time of 6 μs (typ).
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As the integrated power switch is turned off the external Schottky diode is forward biased, delivering the
stored inductor energy to the output. The main switch remains off until the FB3 pin voltage is below the
internal 250mV reference voltage, when it is turned on again.
This PFM peak current control sets the converter in discontinuous conduction mode (DCM), and the
switching frequency depends on the inductor, input/output voltage and LED current. Lower LED currents
reduce the switching frequency, with high efficiency over the entire LED current range. This regulation
scheme is inherently stable, allowing a wide range for the selection of the inductor and output capacitor.
3.38.1 SM3 RAM Registers
Table 3-33. SM3 Control
SM3_SET0 [Addr 0x57]
Defaults in BOLD
B0
Bit Number
Bit Name
Function
When 0
B7
B6
B5
B4
B3
B2
B1
SM3_SET7
SM3_SET6
SM3_SET5
SM3_SET4
SM3_SET3
SM3_SET2
SM3_SET1
SM3_SET0
SM3 PWM SWITCH DUTY CYCLE
ADD 0 TO DUTY CYCLE
When 1
ADD 6.25%
ADD 3.125%
ADD 1.5625%
ADD 0.78125%
ADD 0.390%
ADD 0.195% ADD 0.0976%
ADD 0.048%
SM3_SET1 [Addr 0x58]
Defaults in BOLD
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
SM3SOFTOFF
SM3_ILIM
SM3_PRESC1
SM3_PRESC0
SM3_IGAIN
SM3_SET10
SM3_SET9
SM3_SET8
SM3
CURRENT
LIMIT
SM3PWM
REPETITION
RATE[1]
SM3PWM
REPETITION
RATE[0]
ISM3G
OUTPUTBUFF
ER MODE
SOFTSTART
ENABLE
Function
SM3 PWM DUTY CYCLE
SEE SM3 PWM REPETITION
TABLE
When 0
When 1
ENABLED
300 mA
Hi-Z
ADD 0 TO DUTY CYCLE
SEE SM3 PWM REPETITION
TABLE
DISABLED
500 mA
LO
ADD 50%
ADD 25%
ADD 12.5%
Table 3-34. SM3 PWM Repetition Settings
SM3PRESC[1]
SM3PRESC[0]
REPETITION RATE (Hz)
0
0
1
1
0
1
0
1
550
366
275
220
The internal LED switch, in series with the external LED’s, disconnects the LEDs from ground during
shutdown. In addition, the LED switch is driven by a PWM signal generated internally, enabling adjusting
the average LED current by setting the LED switch duty cycle. The duty cycle is adjusted with control bits
SM3_SET, on register SM3_SET0. With this control method the LED brightness depends on the LED
switch duty cycle only and is independent of the boost converter operating frequency. The duty cycle
control used in the SM3 converter LED switch is implemented by a single PWM pulse with a fixed
repetition rate. An example of distinct duty cycles is shown IN Figure 3-14
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Figure 3-14. SM3 Duty Cycle Example
The repetition period can be set using control bits SM3_PRESCn in the register SM3_SET1 to either
220/275/366/550 Hz (HI). Each repetition period has a total of 2048 steps, enabling a resolution of 0.05%
when programming the duty cycle.
3.38.2 Peak Current Control (Boost Converter)
The SM3 integrated power stage switch is turned on until the inductor current reaches the DC current limit
IMAX(L3) (500 mA or 300mA, typ), selectable via bit SM3_ILIM , register SM3_SET1. Due to internal delays,
typically around 100ns, the actual current exceeds the DC current limit threshold by a small amount. The
typical peak current limit can be calculated as follows:
VSM3
IP(typ) = IMAX(L3)
+
´ 100 ns
L
(3)
The peak current will be directly proportional to the input voltage and inversely proportional to the inductor
value. The internal current limit may be set to either 300mA or 500mA via I2C.
Note that under PWM operation the slew rate of the converter output (SM3) is dependent of the IMAX(L3)
value selected.
3.38.3 Soft Start
All inductive step-up converters exhibit high in-rush current during start-up. If no special precautions are
taken voltage drops can be observed at the input supply rail during start-up, with unpredictable results in
the overall system operation.
The SM3 boost converter limits the inrush current during start-up by increasing the current limit in two
steps, starting from IMAX(L3) /4 for 256 power stage switch cycles (1cycle=power stage switch
OFF→ON→OFF) to IMAX(L3) /2 for the next 256 power stage switch cycles and then full current limit
IMAX(L3). The softstart function can be disabled via control bit SM3SOFTOFF, in register SM3_SET1.
3.38.4 Enabling the SM3 Converter
The converter is enabled when an I2C command sets the duty cycle to a value different than zero.
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3.38.5 Overvoltage Protection
The output voltage of the boost converter is sensed at pin SM3, and the integrated power stage switch is
turned OFF when V(SM3) exceeds the internal over-voltage threshold V(OVP3). The converter returns to
normal operation when V(SM3) < V(OVP3) – VHYS(OVP3)
.
3.38.6 Under Voltage Lockout Operation
The power stage mosfet switch and the LED switch are open (off) when the TPS658629-Q1 enters the
sleep mode or if the SM3 converter is set to OFF mode.
3.38.7 SM3 Output Current - High and Low Current Settings
A dedicated, open-drain pin (ISM3G) enables I2C selection of a low and high brightness setting for the
SM3 output current, by modifying the external FB3 resistor value. See application diagram for details. This
pin is configured as an open drain and it can be turned on/off with bit SM3_IGAIN on register SM3_SET1.
3.39 RGB AND PWM DRIVERS
The TPS658629-Q1 has integrated open drain and push-pull drivers with programmable duty cycle and
frequency, targeted at driving external RGB drivers, keyboard LED's, vibrator motor and other system
peripherals.
Figure 3-15. RGB and PWM Driver Blocks
3.39.1 PWM Pin Driver
The TPS658629-Q1 offers one high current (150mA max) open-drain PWM driver. The PWM driver is
enabled when PWM_EN is 1 in register PWM.
Table 3-35. PWM Control
PWM [Addr 0x5B]
Default to 0
B0
Bit
Number
B7
B6
B5
B4
B3
B2
B1
Bit Name
PWM_EN
PWM_F[2]
PWM_F[1]
PWM_F[0] PWM_D[3] PWM_D[2]
PWM_D[1]
PWM_D[0]
Function
PWM DRIVER ON/OFF
PWM DRIVER FREQUENCY
PWM DRIVER DUTY CYCLE
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The PWM frequency and duty cycle are defined by the PWM register settings as shown below.
Table 3-36. PWM Settings
PWM_F[2:0)
000
FREQUENCY(kHz)
PWM_D[3:0]
0000
DUTY CYCLE (%)
PWM_D[3:0]
1000
DUTY CYCLE (%)
23.4
11.7
6.7
6.25
12.5
18.75
25
56.25
62.5
68.75
75
001
0001
1001
010
0010
1010
011
4.5
0011
1011
100
3.0
0100
31.25
37.5
43.75
50
1100
81.25
87.5
93.75
100
101
2.3
0101
1101
110
1.5
0110
1110
111
0.75
0111
1111
3.39.2 DIG_PWM, DIG_PWM2 Drivers
The TPS658629-Q1 provides two push-pull outputs with programmable duty cycle at pins DIGPWM and
DIGPWM2. The DIG_PWM register controls the DIGPWM pin duty cycle, register DIG_PWM2 controls the
DIGPWM2 pin duty cycle. The DIG_PWM functions and register bit controls detailed below apply to the
DIGPWM2 pin and DIG_PWM2 register as well. Both registers default to 0x00 upon power-up.
Table 3-37. DIGPWM, DIGPWM2 Control
DIG_PWM [Addr 0x5A]
Default to 0
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
DPWM_MODE
DPWM_SET[6]
DPWM_SET[5]
DPWM_SET[4]
DPWM_SET[3]
DPWM_SET[2]
DPWM_SET[1]
DPWM_SET[0]
DIG_PWM2 [Addr 0x5C]
Default to 0
B0
Bit Number
B7
DPWM2_MODE
B6
B5
B4
B3
B2
B1
Bit Name
DPWM2_SET[6]
DPWM2_SET[5]
DPWM2_SET[4]
DPWM2_SET[3]
DPWM2_SET[2]
DPWM2_SET[1]
DPWM2_SET[0]
Mode 0 (DPWM_MODE is 0): The pulse width modulated output is a single PWM pulse of the selected
duty cycle, with a nominal 250Hz repetition rate. The DIG_PWM register bits [6:0] sets the pulse width
value as shown below:
DPWM_SET[6:0]
TON(ms) =
, if DPWM_SET[6:0] £ 126
32
(4)
(5)
TON(ms) = Always On, if DPWM_SET[6:0] = 127)
Mode 1 (DPWM_MODE is 1): The bit DPWMx_SET[6] of the DIG_PWMx register selects the pulse time
range, bits DIG_PWMx[5:3] set the ON times and bits DIG_PWMx[2:0] set the off times.
Table 3-38. Digital PWM Settings, DPWM_MODE=1
DPWMx_SET[ 6] = 0
ON TIME (µs) DIG_PWMx[2:0]
DPWMx_SET[ 6] = 1
OFF TIME
(ms)
ON TIME
DIG_PWMx[5:3]
DIG_PWMx[5:3]
DIG_PWMx[2:0]
OFF TIME (ms)
(ms)
000
001
010
011
100
101
110
111
31
61
000
001
010
011
100
101
110
111
0.49
1.01
1.50
2.01
2.50
2.99
4.00
5.00
000
001
010
011
100
101
110
111
5
000
001
010
011
100
101
110
111
40
60
10
15
20
30
40
50
60
92
80
122
153
183
214
244
100
120
140
160
180
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3.39.3 LED_PWM Driver
The LED PWM open drain pin has the duty cycle set by a pulse width modulation circuit. The LED_SET
register bits (7:0) set the pulse width value in 256 steps. The pulse width modulated output is not a single
pulse of the selected duty cycle but a collection of semi-equally spaced pulses that sum to the required
duty cycle, with repetition rate of 125Hz (typ)
Table 3-39. LEDPWM Control
LED_PWM [Addr 0x59]
Default to 0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
LED_SET[7] LED_SET[6] LED_SET[5] LED_SET[4] LED_SET[3] LED_SET[2] LED_SET[1] LED_SET[0]
LED_SET[7:0]
TON(ms) =
, if LED_SET[7:0] £ 254
32
(6)
(7)
TON(ms) = Always On, if LED_SET[7:0] = 255
3.39.4 RGB Drivers
The TPS658629-Q1 has two dedicated drivers for RGB external LED's. Three outputs are available for
each driver (pins REDn, GREENn, BLUEn), with I2C selection of operation mode and LED current.
3.39.5 RGB1 Driver
The RGB1 driver is enabled when RGB1_EN=HI, in RGB1_GREEN register. Each RGB1 pin (RED1,
GREEN1 or BLUE1) will sink the current selected by RGB1_ISET[1:0], RGB1_RED register.
The RGB1 driver can be set in a flashing mode, the flash operation parameters are configured in register
RGB1FLASH. During the flashing ON time the duty cycle for each driver can be set individually using
control bits PWMIR[4:0], PWMIG[4:0] and PWMIB[4:0] on registers RGB1_RED, RGB1_GREEN and
RGB1_BLUE. The modulated output is not a single pulse of the selected duty cycle but a collection of
semi-equally spaced pulses that sum to the required duty cycle, with repetition rate of 160Hz (typ). The
start of 1 of the modulated pulses on RGB1 can be phased by 200 μs from the others so that for duty
cycles below 50% the ON times of 2 of the LEDs will not overlap. When RGB1_PHASE is 0
(RGB1_GREEN[6]), the Red and Blue are drivers are in phase and Green is out of phase. For
RGB1_PHASE is 1 the Red and Green are in phase and Blue is out of phase.
Table 3-40. RGB1 Control
RGB1FLASH [Addr 0x50]
Default is 0
B0
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
RSVD507
SPARE
FLASH1_ON[2]
FLASH1_ON[1]
FLASH1_ON[0]
FLASH1_PER[3]
FLASH1_PER[2]
FLASH1_PER[1]
FLASH1_PER[0]
RGB1 RED/BLUE/GREEN FLASHING ON-TIME
RGB1 RED/BLUE/GREEN FLASHING PERIOD
RGB1RED [Addr 0x51]
Bit Number
Default is 0
B0
B7
B6
B5
B4
B3
B2
B1
Bit Name
RSVD517
RGB1_ISET[1]
RGB1_ISET[0]
PWM1R[4]
PWM1R[3]
PWM1R[2]
PWM1R[1]
PWM1R[0]
RGB1 RED/BLUE/GREEN DRIVER
CURRENT SINK
Function
NOT USED
RGB1 RED DRIVER INTENSITY CONTROL
RGB1GREEN [Addr 0x52]
Default is 0
B0
Bit Number
B7
B6
B5
B4
B3
B2
B1
Bit Name
RGB1_EN
RGB1_PHASE
RSVD535
PWM1G[4]
PWM1G[3]
PWM1G[2]
PWM1G[1]
PWM1G[0]
RGB1 DRIVERS
ON/OFF
CONTROL
DRIVER ON TIME
PHASE CONTROL
Function
NOT USED
RGB1 GREEN DRIVER INTENSITY CONTROL
RGB1BLUE [Addr 0x53]
Default is 0
B0
Bit Number
B7
B6
B5
B4
B3
B2
B1
Bit Name
Function
RSVD537
RSVD536
NOT USED
RSVD535
NOT USED
PWM1B[4]
PWM1B[3]
PWM1B[2]
PWM1B[1]
PWM1B[0]
NOT USED
RGB1 BLUE DRIVER INTENSITY CONTROL
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Table 3-41. RGB1 Sink Current Settings
RGB1_ISET[1:0]
RGB1 SINK CURRENT (mA)
00
01
10
11
0
3.7
7.4
11.1
Table 3-42. FLASH1_ON Settings
FLASH1_ON[2:0]
000
FLASH ON TIME (s)
0.10
001
010
011
100
101
110
111
0.15
0.20
0.25
0.30
0.40
0.50
0.60
Table 3-43. FLASH1_PER Settings
FLASH1_PER[3:0]
FLASH PERIOD (s)
FLASH1_PER[3:0]
FLASH PERIOD (s)
0000
0001
0010
0011
0100
0101
0110
0111
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
1000
1001
1010
1011
1100
1101
1110
1111
5.0
5.5
6.0
6.5
7.0
7.5
8.0
Always On
Equation 8 indicates the duty cycle values for each driver, set with bit PWM1R[4:0], PWM1G[4:0] and
PWM1B[4:0]:
PWM1R/G/B[4:0]
TON(ms) =
5.4
(8)
3.39.6 RGB2 Driver
The RGB2 driver is enabled when RGB2_EN is 1, in RGB2_GREEN register. Each RGB2 pin (RED2,
GREEN2 or BLUE2) will sink the current selected by RGB2_ISET[2:0], set in RGB2_RED register.
The RGB2 does not support a flashing mode, and will be turned on when RGB2_EN is 1. When turned
ON the duty cycle for each driver can be set individually using control bits PWMIR[4:0], PWMIG[4:0] and
PWMIB[4:0] on registers RGB2_RED, RGB2_GREEN and RGB2_BLUE. The modulated output is not a
single pulse of the selected duty cycle but a collection of semi-equally spaced pulses that sum to the
required duty cycle, with repetition rate of 160Hz (typ). The start of one of the modulated pulses on RGB2
can be phased by 200 µs from the others, so that for duty cycles below 50% the ON times of 2 of the
LEDs will not overlap. When RGB2_PHASE is 0 (RGB2_GREEN[6]), the Red and Blue drivers are in
phase and Green is out of phase. When RGB2_PHASE is 1 the Red and Green are in phase and Blue is
out of phase.
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Table 3-44. RGB2 Control
RGB2RED [Addr 0x54]
Default to 0
B0
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
RGB2_ISET[2]
RGB2_ISET[1]
RGB2_ISET[0]
PWM2R[4]
PWM2R[3]
PWM2R[2]
PWM2R[1]
PWM2R[0]
RGB2 RED/BLUE/GREEN DRIVER CURRENT SINK
RGB2 RED DRIVER INTENSITY CONTROL
RGB2GREEN [Addr 0x55]
Default to 0
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
RGB2_EN
RGB2_PHASE
RSVD565
PWM2G[4]
PWM2G[3]
PWM2G[2]
PWM2G[1]
PWM2G[0]
RGB2 DRIVERS
ON TIME PHASE
CONTROL
RGB2 DRIVERS
ON/OFF CONTROL
Function
SPARE
RGB2 GREEN DRIVER INTENSITY CONTROL
RGB2BLUE [Addr 0x56]
Default to 0
B0
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
RSVD577
RSVD576
NOT USED
RSVD575
NOT USED
PWM2B[4]
PWM2B[3]
PWM2B[2]
PWM2B[1]
PWM2B[0]
NOT USED
RGB2 GREEN DRIVER INTENSITY CONTROL
Table 3-45. RGB2 Sink Current Settings
RGB2_ISET[2:0]
RGB2 SINK CURRENT (mA)
000
001
010
011
100
101
110
111
0
3.7
7.4
11.1
14.9
18.6
23.2
27.3
The on time for each driver, set with bits PWM2R[4:0], PWM2G[4:0] and PWM2B[4:0], is set by the
equation:
PWM2R/G/B[4:0]
TON(ms) =
5.4
(9)
3.40 REAL TIME CLOCK
The TPS658629-Q1 has an integrated real time clock circuit that maintains an accurate timer/counter
register under all potential operating conditions (AC power input, USB power input, main battery power,
backup coincell / SuperCap power source, or any combination of the above). The internal oscillator for the
RTC can be driven by an external 32.768 kHz crystal. The TPS658629-Q1 has also been design with
integrated, I2C selectable, capacitors which can be used with the external 32.768 kHz crystal such that a
wide range of commercial crystals can be used without the need for external load capacitors.
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VRTC_OUT
POR
RESET RTC RAM
32K CLOCK
SELECTION
PRESCALER
XTAL2
I2C
40-BIT COUNTER
(RAW RTC DATA)
I2C
Cd0
7pF
Cd1
12pF
STANDARD
I2C ONLY
RTC
RAM
ALARM
DETECTION
LOGIC
XTAL1
Cg0
7pF
Cg1
12pF
ALARM2
ALARM1
V32K
INTERRUPT
CONTROLLER
SEQUENCER
OUT32K
EN
Figure 3-16. Simplified RTC Block
The following functions are provided:
•
•
A 40-bit counter, driven by a low-power 32 kHz oscillator
The 32 kHz oscillator can be switched using I2C, RTC_CTRL Register bit 6 (OSC_SRC_SEL),
between the TPS658629-Q1 internal (RC) oscillator source and the crystal driven oscillator source.
•
•
Externally biased buffer to supply the crystal driven oscillator to an external device via the OUT32K
pin.
Selectable pre-scaler divides the raw (32KHz) oscillator output, enabling clocking the RTC counter at
1.024 kHz or 32 kHz
•
•
A 24-bit alarm register (ALARM1)
A 16-bit alarm register (ALARM2)
The RTC registers are accessible only via the I2C bus. When an I2C read access is in progress, the RTC
counter update is postponed. At the end of the I2C read access, the accumulated missing counts are
added to the RTC counter.
NOTE
The RTC registers (0xC0-0xCA) ARE NOT reset when the TPS658629-Q1 is in the POWER
DOWN or SLEEP STATE as long as V(RTC_OUT) is greater than VUVLO_RTC . All the RTC
registers will be reset to their default settings, independent of the TPS658629-Q1 state,
when V(RTC_OUT) is less than VUVLO_RTC
.
The host software must read all five RTC counter bytes when accessing the RTC counter data, as the
counter update is postponed starting at the first I2C byte read of a sequential I2C read of the five
RTC_COUNT bytes and negated on the fifth I2C byte read.
To assure proper operation of the RTC counter the following steps should always be followed:
1. The I2C address pointer must not be left pointing in the range 0xC6 to 0xCA
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2. The maximum time for the address pointer to be in this range is 1 ms
3. Always read RTC_ALARM2 in the following order to prevent the address pointer from stopping at
0xC6: RTC_ALARM2_LO, then RTC_ALARM2_HI
When the RTC_OUT voltage falls below the internal RTC circuit Power On Reset threshold, VUVLO_RTC
,
the RTC_CTRL register is reset. The host can identify this situation by reading the bit, POR_RESET_N,
which will be 0.
The clock selection is controlled by OSC_SRC_SEL (RTC_CTRL [6]). The internal 32kHz oscillator is
connected to the RTC when the OSC_SRC_SEL bit is reset. Once the processor is running, the software
can set this bit to 1, thereby connecting the 32.768 kHz crystal oscillator clock to the RTC. After being set,
the OSC_SRC_SEL bit will remain 1 selecting the crystal oscillator clock, as long as the VRTC_OUT
voltage remains above the RTC_OUT Power On Reset threshold. POR_RESET_N=HI when
OSC_SRC_SEL is set HI, indicating to the host that the crystal clock is being delivered to the RTC.
The RTC_ENABLE (RTC_CTRL [5]) bit is cleared to 0 by the RTC_OUT Power On Reset, disabling the
RTC counter. To enable incrementing of the RTC_COUNT [39:0] from an initial value set by the host, the
RTC_ENABLE bit should be written to 1 only after the RTC_OUT voltage reaches the operating range.
The RTC_ENABLE bit must be cleared to 0 before any new value is written to the RTC_COUNT register.
Table 3-46. RTC Control(1)
RTC_CTRL [Addr 0xC0]
Defaults in BOLD
B0
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
POR_RESET_N
OSC_SRC_SEL
RTC_ENABLE
BUF_ENABLE
PRE_BYPASS
CL_SEL[1]
CL_SEL[0]
RSVDC00
RESET RTC
COUNTER
32K CLOCK
SELECTION
RTC COUNTER
CLOCK AND
ALARM1/2
32KHZ BUFFER
ENABLE
RTC COUNTER INTERNAL XTAL1,
PIN
RTC_ALARM2
DETECTION
EXITS SLEEP
SCALING
USE 32K/32
USE 32K
XTAL2
CAPACITANCE
When 0
When 1
RESET RTC
COUNTER
INTERNAL 32K
DISABLED
DISABLED
SEE CL_SEL SETTINGS TABLE
SEE CL_SEL SETTINGS TABLE
DISABLED
OSC_SRC_SEL BIT =
1
CRYSTAL 32K
ENABLED
ENABLED
ENABLED
(1) B7 is READ ONLY, all other bits have Read/Write access
The selected 32KHz clock is applied to a prescaler that can divide it by 32, resulting in a timer tick
resolution of either 32,768 ticks per second (pre-scaler disabled, PRE_BYPASS is 1) or 1,024 ticks per
second (pre-scaler enabled, PRE_BYPASS is 0). The 32,768 Hz or 1024 Hz clock increments a 40 bit
counter that tracks the real time and which can be read at anytime via I2C. With the prescaler enabled, the
RTC count has a range of approximately 34 years. The RTC counter and alarm registers are shown
below, the 40 bit RTC Counter is cleared only on when RTC_OUT is below the UVLO threshold.
Table 3-47. RTC Counter
RTC_COUNT4 [Addr 0xC6]
Default to 0
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
RTC[39]
RTC[38]
RTC[37]
RTC[36]
RTC[35]
RTC[34]
RTC[33]
RTC[32]
Default to 0
RTC[24]
Default to 0
RTC[16]
Default to 0
RTC[8]
RTC_COUNT3 [Addr 0xC7]
Bit Name RTC[31]
RTC_COUNT2 [Addr 0xC8]
Bit Name RTC[23]
RTC_COUNT1 [Addr 0xC9]
Bit Name RTC[15]
RTC_COUNT0 [Addr 0xCA]
Bit Name RTC[7]
RTC[30]
RTC[22]
RTC[14]
RTC[6]
RTC[29]
RTC[21]
RTC[13]
RTC[5]
RTC[28]
RTC[20]
RTC[12]
RTC[4]
RTC[27]
RTC[19]
RTC[11]
RTC[3]
RTC[26]
RTC[18]
RTC[10]
RTC[2]
RTC[25]
RTC[17]
RTC[9]
RTC[1]
Default to 0
RTC[0]
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The alarm logic compares the RTC_ALARM1 register bits to the RTC_COUNT registers as follows:
With prescaler enabled: ALM1[23:0] is compared to RTC[23:0]
With prescaler disabled: ALM1[23:0] is compared to RTC[28:5]
An interrupt is sent to the host (if enabled via I2C, see interrupt controller section) when the alarm logic
detects that the RTC_COUNT value is equal to the pre-programmed ALARM1 register value.
The alarm logic compares the RTC_ALARM2 register bits to the RTC_COUNT registers as follows:
With prescaler enabled: ALM2[23:0] is compared to RTC[22:7]
With prescaler disabled: ALM2[15:0] is compared to RTC[27:12]
An interrupt is sent to the host (if enabled via I2C, see interrupt controller section) and the sleep mode
ends when the alarm logic detects that the RTC_COUNT value is equal to the pre-programmed ALARM2
register value.
Table 3-48. RTC Alarm
RTC_ALARM1_HI [ADDRESS=0xC1]
Default to 0
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
ALM1[23]
ALM1[22]
ALM1[21]
ALM1[20]
ALM1[19]
ALM1[18]
ALM1[17]
ALM1[16]
Default to 0
ALM1[8]
RTC_ALARM1_MID [Addr 0xC2]
Bit Name ALM1[15]
RTC_ALARM1_LO [Addr 0xC3]
Bit Name ALM1[7]
RTC_ALARM2_HI [Addr 0xC4]
Bit Name ALM2[15]
RTC_ALARM2_LO [Addr 0xC5
Bit Name ALM2[7]
ALM1[14]
ALM1[6]
ALM2[14]
ALM2[6]
ALM1[13]
ALM1[5]
ALM2[13]
ALM2[5]
ALM1[12]
ALM1[4]
ALM2[12]
ALM2[4]
ALM1[11]
ALM1[3]
ALM2[11]
ALM2[3]
ALM1[10]
ALM1[2]
ALM2[10]
ALM2[2]
ALM1[9]
ALM1[1]
ALM2[9]
ALM2[1]
Default to 0
ALM1[0]
Default to 0
ALM2[8]
Default to 0
ALM2[0]
3.41 SWITCHING BETWEEN INTERNAL AND CRYSTAL CLOCK
When switching between the internal clock to the crystal clock, an internal logic extends the LO time of the
clock sent to the counter to avoid undesired glitches. A typical clock switching timing diagram is shown
below:
SELECT CRYSTAL
CLOCK
INTERNAL 32K
CRYSTAL CLOCK
RTC CLOCK
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3.42 CRYSTAL OSCILLATOR
The crystal oscillator has internal load capacitances, in order to allow a typical 32K crystal to operate as
described in the electrical characteristics tables. The TPS658629-Q1 has four integrated capacitors that
can be connected to the XTAL1, XTAL2 pins as defined by control bits CL_SEL[1:0] in register
RTC_CTRL, effectively applying a load capacitance to the external crystal.
Table 3-49. CL_SEL[1:0] Setting
(Default in bold)
Total C_LOAD [pF]
CL_SEL[1]
CL_SEL[0]
(typ)
0
0
1
1
0
1
0
1
1.5
6.5
7.5
12.5
3.43 ADC FUNCTIONAL OVERVIEW
The TPS658629-Q1 ADC is capable of running in a variety of modes programmable via I2C. The ADC
control and data registers are accessible only by the standard I2C interface (SDA/SCLK). An internal 11:1
analog multiplexer is used to allow a single SAR converter to sequentially monitor up to 11 analog inputs,
as shown inTable 3-50.
Table 3-50. ADC Channel Settings
FULL SCALE
READING
CHANNEL
CONNECTION
PARAMETER SAMPLED
VOLTAGE RANGE
SPECIAL FEATURES
CH1
CH2
CH3
CH4
ANLG1 pin
ANLG2 pin
ANLG3 pin
RSVD
Internal pull-up current
source programmable
via
2.6 V
0–2.6V
AVDD6-V(ANLGn)>
400mV
2.6 V
User defined
N/A
I2C: 0/ 3/10/50 μA
2.6 V
N/A
—
2.6 V
Voltage proportional to pack
temperature
0V (short) to 2.2V (no
thermistor)
CH5
TS pin
—
2.6 V
CH6
CH7
CH8
CH9
RSVD
LDO_RTC pin
SYS pin
N/A
N/A
—
—
—
—
2.6 V
Internal LDO output voltage
System Power bus voltage
N/A
0V to 3.3V
0V to 5.5V
N/A
4.622 V
5.547 V
5.547 V
RSVD
Battery pack positive
terminal voltage
CH10
CH11
BAT pin
RSVD
0V to 4.6V
N/A
—
—
4.622 V
2.6 V
N/A
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A simplified block diagram for the ADC analog section is show in Figure 3-17.
RSVD
RSVD
Figure 3-17. Simplified ADC Block
3.43.1 ADC External Input Pins – Bias Current Settings
The external pins ANLG1, ANLG2 and ANLG3 may be biased using internal pull-up current sources, with
current source value set by register ADCANLG. The current sources are turned OFF when the ADC
reference is disabled.
Table 3-51. ADC Input Bias Selection
ADCANLG [Addr 0x60]
Default to 0
IANLG1[0]
ANLG2 BIAS CURRENT SOURCE ANLG1 BIAS CURRENT SOURCE
Bit Name
Function
ANLG2FLT ANLG3FLT
SPARE SPARE
IANLG3[1]
IANLG3[0]
IANLG2[1]
IANLG2[0]
IANLG1[1]
ANLG3 BIAS CURRENT SOURCE
Table 3-52. ANLG3/2/1 Current Source Settings
IANLG[1]
IANLG[0]
Current (μA)
0
0
1
1
0
1
0
1
0
3
10
50
3.43.2 ADC Timing Engine Overview
The ADC timing engine can be configured to perform either one reading, a single-trigger multiple set of
readings, or to operate continuously until high or low limits are violated on any channel.
A conversion cycle includes the following steps:
1. Program the timing engine mode (single sample, multiple sample, etc.) and triggers
2. Enable the internal ADC reference and conversion start delay
3. Select the channel to be used as the SAR input and start the conversion cycle
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The timing engine has an internal ALU that stores the converted data in an internal accumulator,
executing mathematical operations with the stored data. A conversion cycle ends when the accumulator
data is transferred to the TPS658629-Q1 ADC RAM data registers.
When the conversion cycle is completed, an interrupt request corresponding to indicate end of conversion
operation is generated. The interrupt controller subsystem will set the ACK_ADC (bit B1, register 0xB6) to
indicate the source of the interrupt was the ADC subsystem. Additional information is available in the
ADC0_INT register (0x9A).
3.43.3 Configuring the ADC Conversion Cycle
3.43.3.1 Number of Samples and ADC Input Setup
Register ADC0_SET controls the following parameters for a conversion cycle: conversion start, continuous
or fixed-interval sampling mode, number of samples to be taken and channel selection.
Setting the ADC0_EN bit to 1 will start the conversion process. While a conversion cycle is being executed
(and conversions are being taken) the ADC0_INT register cannot be externally accessed.
The ADC engine has a BUSY signal generated by the ADC Digital Control Logic to indicate this condition.
If the ADC0_EN bit is cleared to 0 during a conversion, the conversion cycle will continue until the number
of samples specified with the RD_MODE bits has been taken so that the SUM (average) value from the
accumulator will be valid. The ADC0_EN bit must be set to 0 before a new conversion configuration is set
up.
Table 3-53. ADC0 Conversion Selection
ADC0_SET [Addr 0x61]
Default in BOLD
Bit
Number
B7
ADC0_EN
B6
B5
B4
B3
B2
B1
B0
Bit Name
Function
REPEAT0
RD0_MODE[1]
RD0_MODE[0]
CHSEL0[3] CHSEL0[2] CHSEL0[1] CHSEL0[0]
ADC0 INPUT CHANNEL SELECTION
ADC0 CONVERSION
START
ADC0 REPEAT
MODE ENABLE
READINGS IN A CONVERSION
SEE ADC READING SETTINGS
When 0
When 1
DISABLED
DISABLED
SEE ADC CHANNEL SELECT SETTINGS
ENABLED
ENABLED
Table 3-54. ADC Readings Setting
(Default in bold)
NUMBER OF
READINGS
RD0_MODE[1]
RD0_MODE[0]
0
0
1
1
0
1
0
1
1
16
32
64
Table 3-55. ADC Channel Select Settings (Default in bold)
CHSELn[3:0]
CHANNEL
CH1
CHSELn[3:0]
1000
CHANNEL
CH9
0000
0001
0010
0011
0100
0101
0110
CH2
1001
CH10
CH3
1010
CH11
CH4
1011
AGND
AGND
AGND
AGND
CH5
1100
CH6
1101
CH7
1110
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Table 3-55. ADC Channel Select Settings (Default in bold) (continued)
CHSELn[3:0]
CHANNEL
CHSELn[3:0]
CHANNEL
0111
CH8
1111
AGND
Continuous sampling mode can be set by writing REPEAT to 1 and RD0_MODE[1:0]=00. With those
settings the conversions will be performed as single samples, without wait times, until the ADC_EN bit is
cleared by the host or a limit violation occurs. If fixed-interval sampling mode (REPEAT0 = 0) is chosen,
the conversion cycle will consist of a specific number of samples (1, 16, 32, or 64) as specified by the
RD0_MODE[1:0] bits. When a multiple sample conversion cycle is selected the time interval between
individual samples is defined by the WAIT bits (register ADC0_WAIT). To exit the continuous conversion
mode before a limit violation occurs, the host must first set the REPEAT bit to LO, and then set the
ADC0_EN bit to 0.
3.43.4 Timing and ADC Reference Setup
The ADC0_WAIT register controls the ADC0 timing engine reset, wait time value and the converter
internal reference voltage enable. The ADC reference and SAR are disabled when AUTO_REF=0 AND
REF_EN=0. The use of external references for the ADC is not supported.
Table 3-56. ADC0 Conversion Timing
ADC0_WAIT [Addr 0x62]
Defaults in BOLD
B0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
ADC_RESET
RSVD626
AUTO_REF
REF_EN
WAIT0[3]
WAIT0[2]
WAIT0[1]
WAIT0[0]
RESET
CONVERSION
CYCLE
WAIT TIME BETWEEN INDIVIDUAL CONVERSIONS,
REPEAT MODE ENABLED (ms)
Function
NOT USED
ADC Conversion Control
ALL ADC
ENGINES
ACTIVE
When 0
When 1
NOT USED
Function is based on ADC
Conversion Control
SEE WAIT0 SETTINGS TABLE
RESET ALL
ADC ENGINES
NOT USED
Table 3-57. ADC Conversion Control
(Default in bold)
AUTO_REF
REF_EN
DESCRIPTION
0
0
1
1
0
1
0
1
Reference and ADC disabled
Manual control of the Reference. WAIT=0 is not valid. 8ms must occur between REF_EN=1 and ADC0_EN=1
Automatic control of the Reference. Automatically enabled 8 ms before an ADC conversion is started.
Not a valid state
The relative timing between enabling the internal ADC reference / ANLGn pin bias currents and the start
of a conversion cycle is controlled by bits AUTO_REF and REF_EN. Those bits allow implementation of a
software only reference enable control or automatic reference enable control, as shown below:
Software enables ADC reference: Clear AUTO_REF bit to 0. Software must set REF_EN to 1 at least 8
ms before enabling an ADC engine and not clear REF_EN until all ADC engines are stopped.
Automatic ADC reference enable, internal or external trigger, wait time < 8ms : Set AUTO_REF bit to
1. The ADC logic will keep the ADC reference always on.
Automatic ADC reference enable, internal trigger, wait time > 8ms : Set AUTO_REF bit to 1. The ADC
logic enables the ADC reference 8 ms before the programmed wait time is reached
Setting ADC_RESET to 1 will return ALL the ADC timing engine to the idle state, ready to be re-enabled
for a new conversion cycle. During the conversion cycle the ADC_RESET bit is internally set to LO prior to
the first ADC conversion being started. WAIT[3:0] sets the time interval between samples in the case
where a multiple-sample conversion cycle is being executed. WAIT[3:0] should be set LO in single sample
conversion cycles.
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Table 3-58. ADC0 Conversion Wait Settings (Default in bold);
Valid for All Timing Engines
WAIT0[3:0]
0000
WAIT TIME (ms)
0.000
WAIT0[3:0]
1000
WAIT TIME (ms)
8.000
0001
0.062
1001
16.00
0010
0.125
1010
32.00
0011
0.250
1011
64.00
0100
0.500
1100
128.0
0101
1.000
1101
256.0
0110
2.000
1110
512.0
0111
4.000
1111
1024
3.43.5 External Trigger Setup
The ADC conversion cycle can be started via an internal or external trigger when using the ADC0 timing
engine. The trigger is selectable by setting bits ADC0_TRIG4, ADC0_TRIG2 in registers ADC0_DELAY.
Table 3-59. Trigger Settings
ADC0_DELAY [Addr 0x67]
Default to 0
B0
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
ADC0_TRIG4
ADC0_TRIG2
ADC0HOLD
ADC0_EDGE
NOT USED
RSVD673
NOT USED
DELAY0[2]
DELAY0[1]
DELAY0[0]
GPIO4 IS ADC0
EXT TRIGGER
GPIO2 IS ADC0
EXT TRIGGER
ADC HOLDOFF
ON/OFF CONTROL
ADC EXTERNAL TRIGGER DELAY (μs)
When 0
When 1
DISABLED
DISABLED
OFF
NOT USED
NOT USED
000=00 001=50 010= 100 011=150
100=200 101=250 110=350 111=450
ENABLED
ENABLED
ON
NOT USED
NOT USED
When more than one GPIO trigger source is selected the GPIO signals are OR'ed prior to trigger
detection. When both of those bits are cleared to 0 the internal trigger is selected.
ADC0_HOLDOFF (ADC0_DELAY[5]) enables the GPIOx trigger source to be used as a level-sensed
gating signal which will suspend conversion cycles when the trigger source is low. The default for this bit
is 0. When ADC0HOLD is 0, the conversion cycle will continue for the preset number of conversions
selected with the RD_MODE bits once the initial trigger occurs. If the ADC0HOLD bit is 1, any pending
conversion cycle can be suspended if the GPIO trigger goes low (and resumes once the trigger signal
goes high again and the trigger delay time has been met). ADC0_DELAY[2:0] are used to set the initial
wait interval from the trigger event until the first conversion in a cycle is started. This delay may be from 0
to 450μs.
When the GPIO's are selected as external triggers the ADC conversion start will be dependent on the
GPIO configuration. Table 3-60 shows the possible options:
Table 3-60. ADC0 GPIO Trigger Settings
ADC0_TRIG2 = 1, ADC0_TRIG4 = 0
ADC TRIGGER
ADC0_TRIG2 = 0, ADC0_TRIG4 = 1
ADC TRIGGER
WHEN
GPIO2 PIN
WHEN HOLDOFF=HI
GPIO4 PIN
SOURCE
SOURCE
HOLDOFF=HI
SUSPEND
TRIGGER at
GPIO4=LO
GPIO2
POSITIVE EDGE
SUSPEND TRIGGER at
GPIO2=LO
GPIO4
POSITIVE EDGE
NON-INVERTED
NON-INVERTED
INVERTED
GPIO2
NEGATIVE
EDGE
SUSPEND
TRIGGER at
GPIO4=HI
SUSPEND TRIGGER at
GPIO2=HI
GPIO4 NEGATIVE
EDGE
INVERTED
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ADC0_TRIG2=HI,ADC0_TRIG4=HI
GPIO4 PIN ADC TRIGGER SOURCE
GPIO2 PIN
WHEN HOLDOFF=HI
GPIO2 OR GPIO4 POSITIVE
SUSPEND TRIGGER at GPIO2
= LO AND GPIO4 = LO
NON-INVERTED
NON-INVERTED
INVERTED
NON-INVERTED
INVERTED
EDGE
GPIO2 POSITIVE EDGE OR
GPIO4 NEGATIVE EDGE
SUSPEND TRIGGER at GPIO2
= LO AND GPIO4 = HI
GPIO2 NEGATIVE EDGE OR
GPIO4 POSITIVE EDGE
SUSPEND TRIGGER at GPIO2
= HI AND GPIO4 = LO
NON-INVERTED
INVERTED
GPIO2 OR GPIO4 NEGATIVE
SUSPEND TRIGGER at GPIO2
= HI AND GPIO4 = HI
INVERTED
EDGE
The procedure to start an externally-triggered conversion cycle has the following steps:
1. Verify that the current conversion cycle has ended (ADC0_BUSY is 0, I2C register STAT4)
2. Clear ADC0_EN to 0 (ADC0_SET[7]).
3. Set the appropriate bit in the corresponding ADC0_DELAY register (example – write 1 to
ADC0_DELAY bit B7 to use GPIO4 as trigger source for ADC0). Ensure that the selected GPIOs have
the appropriate input and polarity selection – see GPIOSET1 and GPIOSET2 registers.
4. Set ADC0_EN to 1
After step 4 the ADC will be armed, waiting for an external trigger detection to start a conversion cycle. In
triggered mode the current cycle will not expire if the converter is armed and an external trigger is not
detected.
CONVERSION CYCLE
GPIO2
ON
INTERNAL ADC
CONVERSION STATUS
OFF
TWAIT(TRG)
TDLY(TRG)
1st
SAMPLE
LAST
SAMPLE
ADC CONVERSION TRIGGERED BY GPIO2, POSITIVE EDGE TRIGGERED, ACTIVE LEVEL HI , HOLDOFF = LO
CONVERSION CYCLE
GPIO2
ON
OFF
INTERNAL ADC
CONVERSION STATUS
TWAIT(TRG)
TDLY(TRG)
TDLY(TRG)
1st
SAMPLE
LAST
SAMPLE
ADC CONVERSION TRIGGERED BY GPIO2, POSITIVE EDGE TRIGGERED, ACTIVE LEVEL HI , HOLDOFF = HI, 4 SAMPLE
CYCLE
Figure 3-18. ADC Operation Example
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3.43.6 ADC ALU Unit and Result Registers
The ALU performs mathematical operations on the ADC output data. It can execute average (SUM)
calculations and minimum / maximum detection for a conversion cycle. The result of the SUM calculations
is stored in a 16 bit accumulator register (ADC0SUM2, ADC0_SUM1) and the MIN/MAX data is stored in
10-bit registers (ADC0_MAX2, ADC0_MAX1, ADC0_MIN2, ADC0_MIN1).
Equation 10 indicates how to translate the register data into a voltage reading for each channel:
ADC_OUTPUT_COUNTS = [ADC_INPUT_VOLTAGE / FULL_SCALE_READING] × 1023
(10)
Table 3-61. ADC0 Output Data
ADC0_SUM2(1) [Addr 0x94]
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
AVG[15]
AVG[14]
AVG[13]
AVG[12]
AVG[11]
AVG[10]
AVG[9]
AVG[8]
AVG[0]
MAX[8]
MAX[0]
MIN[8]
MIN[0]
ADC0_SUM1 [Addr 0x95]
Bit Name AVG[7]
ADC0_MAX2 [Addr 0x96]
Bit Name RSVD967
ADC0_MAX1 [Addr 0x97]
Bit Name MAX[7]
ADC0_MIN2 [Addr 0x98]
Bit Name RSVD987
ADC0_MIN1 [Addr 0x99]
Bit Name MIN[7]
AVG[6]
RSVD966
MAX[6]
AVG[5]
RSVD965
MAX[5]
AVG[4]
RSVD964
MAX[4]
AVG[3]
RSVD963
MAX[3]
AVG[2]
RSVD962
MAX[2]
AVG[1]
MAX[9]
MAX[1]
MIN[9]
MIN[1]
RSVD986
MIN[6]
RSVD985
MIN[5]
RSVD984
MIN[4]
RSVD983
MIN[3]
RSVD982
MIN[2]
(1) All bits in ADC0_SUM2 are read only.
3.43.7 Limit Check Setup
The ADC0 timing engine has configurable low and high thresholds to interrupt the host when conversion
values, stored in registers ADC0_MAX and ADC0_MIN exceed a pre-selected range . A limit violation will
be detected and an interrupt sent to the host when the sampled value stored in registers ADC0_MAX2,
ADC0_MAX1 exceeds the maximum value set in registers ADC0_HILIM2, ADC0_HILIM1 or when the
minimum sampled value stored in registers ADC0_MIN2, ADC0_MIN1 is lower than the minimum value
programmed in registers and ADC0_HILIM2, ADC0_HILIM1.
Limit violations can not occur if Low Limit = 0x000 and High Limit = 0xFFF.
Table 3-62. ADC0 Limit Selection
ADC0_HILIM2 [Addr 0x63]
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
RSVD637
RSVD636
RSVD635
RSVD634
HILIMA[11]
HILIMA[10]
HILIMA[9]
HILIMA[8]
ADC0_HILIM1 [Addr 0x64]
Bit Name HILIMA[7]
ADC0_LOLIM2 [Addr 0x65]
Bit Name RSVD657
ADC0_LOLIM1 [Addr 0x66]
Bit Name LOLIMA[7]
HILIMA[6]
RSVD656
LOLIMA[6]
HILIMA[5]
RSVD655
LOLIMA[5]
HILIMA[4]
RSVD654
LOLIMA[4]
HILIMA[3]
LOLIMA[11]
LOLIMA[3]
HILIMA[2]
LOLIMA[10]
LOLIMA[2]
HILIMA[1]
LOLIMA[9]
LOLIMA[1]
HILIMA[0]
LOLIMA[8]
LOLIMA[0]
The limit detection ADC conversion cycle should be configured with internal trigger and sampling
sequences as follows:
1. To detect when an individual sample violates the max/min limits: Set RD_MODE[1:0] to 00 and
REPEAT to 1. With these settings the ALU will compare the 10-bit ADC data returned from the SAR
engine to the 10 bit values loaded in the ADC0_LIMIT values. The conversion sequence will repeat
until either a violation interrupt occurs or the ADC0_EN bit is written to 0.
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2. To detect when the average value violates the max/min limits: Set RD_MODE[1:0]) to 01, 10 or 11 and
REPEAT to 1. At the end of the multiple sample conversion cycle the ALU will calculate the 12 bit
average of the sample values by shifting the AVG[15:0] register (shift right 2 if 16 samples, shift right 3
if 32 samples and shift right 4 if 64 samples) . The shifted 12-bit average value is then compared to the
value programmed in registers ADC0_LIMIT.
3.43.8 ADC Status Registers
The ADC conversion status for the timing engine is available in the ADC0_INT register. The ADC0_INT
register is read-only. Reading the ADC0_INT register clears the ADC0INT bit in the STAT4 register
(ADC0INT=0).
Table 3-63. ADC Conversion Status
ADC0_ INT [Addr 0x9A]
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
ADC0_ DONE
ADC0_
HILIM0_FLT
LOLIM0_FLT
RSVD9A3
RSVD9A2
ADC0_GPIO4ST ADC0_GPIO2ST
ERROR
Function
When 0
When 1
CONVERSION
CYCLE STATUS
ADC_STATUS
NO ERROR
ERROR
HI LIMIT
FAULT
LO LIMIT FAULT
NO DETECTED
DETECTED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
GPIO4 LEVEL
AT ADC0 EOC
GPIO2 LEVEL
AT ADC0 EOC
BUSY
DONE
NOT
DETECTED
LOW
LOW
DETECTED
HIGH
HIGH
3.44 GPIO
The TPS658629-Q1 integrates 4 general purpose push-pull ports (GPIOs) which can be configured as
selectable inputs or outputs via register GPIOSET1 bits. When the GPIO is not configured the pull-down
current source (2.5uA typ) is connected to the GPIOn pin. When configured as an input the GPIO can be
set as inverting or non-inverting via bits GPIOnINV in the GPIOSET2 register.
When configured as an output, the GPIO output level is defined by bits GPIOnOUT in the GPIOSET2
register.
Table 3-64. GPIO Control(1)
GPIOSET1 [Addr 0x5D]
Default to 0
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
GPIO4_MODE GPIO4_MODE GPIO3_MODE GPIO3_MODE GPIO2_MODE GPIO2_MODE GPIO1_MODE GPIO1_MODE
1
0
1
0
1
0
1
0
Function
GPIO4 CONFIGURATION
GPIO3 CONFIGURATION
GPIO2 CONFIGURATION
GPIO1 CONFIGURATION
GPIOSET2 [Addr 0x5E]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
Function
GPIO4INV
GPIO3INV
GPIO2INV
GPIO1INV
GPIO4OUT
GPIO3OUT
GPIO2OUT
GPIO1OUT
GPIO4 INPUT
BUFFER
GPIO3 INPUT
BUFFER
GPIO2 INPUT
BUFFER
GPIO1 INPUT
BUFFER
GPIO4
VOLTAGE,
GPIO3
VOLTAGE,
GPIO2
VOLTAGE,
GPIO1
VOLTAGE,
MODE
MODE
MODE
MODE
CONFIGURED CONFIGURED CONFIGURED CONFIGURED
AS OUTPUT
AS OUTPUT
AS OUTPUT
AS OUTPUT
When 0
When 1
NON-
INVERTING
NON-
INVERTING
NON-
INVERTING
NON-
INVERTING
LO
LO
LO
LO
INVERTING
INVERTING
INVERTING
INVERTING
HI
HI
HI
HI
(1) All GPIO's default to the same configuration.
Table 3-65. GPIO4/3/2/1_MODE Settings
GPIOx_MODE[1]
GPIOx_MODE[0]
GPIO4 Config
Not Configured
Output
GPIO3 Config
Not Configured
Output
GPIO2 Config
Not Configured
Output
GPIO1 Config
0
0
1
1
0
1
0
1
Not Configured
Output
Input ADC Trigger
Input LDO6/7/8 Enable
Input Not Used
Input LDO2/3 Enable
Input ADC Trigger
Input LDO0/1 ENABLE
Input PWM/PFM Control
Input Not Used
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3.45 STATUS REGISTERS
The system status is accessible via I2C registers listed below. The STATn registers are read only.
Table 3-66. Status Registers
ADC0_ INT [Addr 0x9A]
Bit Number
Bit Name
Function
B7
B6
B5
B4
B3
B2
B1
B0
ADC0_ DONE
ADC0_ ERROR
ADC_STATUS
HILIM0_FLT
HI LIMIT FAULT
LOLIM0_FLT
LO LIMIT FAULT
RSVD9A3
NOT USED
RSVD9A2
NOT USED
ADC0_GPIO4ST
ADC0_GPIO2ST
CONVERSION
GPIO4 LEVEL AT GPIO2 LEVEL AT
CYCLE STATUS
ADC0 EOC
ADC0 EOC
When 0
When 1
BUSY
DONE
NO ERROR
ERROR
NOT DETECTED
DETECTED
NOT DETECTED
DETECTED
NOT USED
NOT USED
NOT USED
NOT USED
LOW
LOW
HIGH
HIGH
STAT1 [Addr 0xB9]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
BATSYSON
BAT TO SYS
SWITCH ON/OFF
STATUS
ACSWON
USBSWON
USB SWITCH
ON/OFF STATUS SWITCH ON/OFF
STATUS
BATCHGSWON
BAT TO VIN_CHG
RSVDB93
SPARE
PACK_HOT
PACK_COLD
BATDET
Function
AC SWITCH ON/OFF
STATUS
PACK TEMP
EXCEEDS HOT
THRESHOLD
PACK TEMP
BELOW COLD
THRESHOLD
BATTTERY PACK
TS THERMISTOR
DETECTION
When 0
When 1
OFF
ON
OFF
ON
OFF
ON
OFF
ON
NOT USED
NOT USED
NO
NO
NOT DETECTED
DETECTED
YES
YES
STAT2 [Addr 0xBA]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVD
RSVD
RSVD
RSVD
SLEEPTSHUT
NOT USED
RSVD
RSVD
COMPDET
Function
nHOTRST PULSE
GENERATED
REBOOT CYCLE
When 0
When 1
NOT USED
NOT USED
NO
YES
STAT3 [Addr 0xBB]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
SLEEPREQ
LOWSYS
RESUME
RTC_ALARM
SPARE
ACDET
USBDET
AC_OVP
USB_OVP
Function
SLEEP REQUEST
STATE SET
LOWSYS
DETECTION
STATUS
RESUME
DETECTION
STATUS
AC INPUT POWER
STATUS
USB INPUT
POWER STATUS
AC INPUT OVP
DETECTION
USB INPUT OVP
DETECTION
When 0
When 1
NO
NOT DETECTED
DETECTED
NOT DETECTED
DETECTED
SPARE
SPARE
NOT DETECTED
DETECTED
NOT DETECTED
DETECTED
NO OVP
NO OVP
YES
OVP DETECTED
OVP DETECTED
STAT4 [Addr 0xBC]
Bit Number
B7
B6
B5
B4
B3
B2
B1
B0
Bit Name
RSVDBC7
SPARE
RSVDBC6
SPARE
RSVDBC5
SPARE
ADC0BUSY
RSVDBC3
SPARE
RSVDBC2
SPARE
RSVDBC1
SPARE
ADC0INT
Function
ADC ENGINE 0
MODE
ADC ENGINE 0
INTERRUPT
When 0
When 1
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
IDLE
SPARE
SPARE
SPARE
SPARE
SPARE
SPARE
NOT ACTIVE
ACTIVE
BUSY
3.46 INTERRUPT CONTROLLER
The interrupt controller monitors the system status bus and internal signals continuously, generating an
interrupt (INT = ‘0’) when a system status change is detected. Individual bits that generated the interrupt
will be set to 1 in the INT_ACK registers (read only registers), indicating which parameters generated the
interrupt.
All the parameters monitored by the interrupt controller can be masked by registers INT_MASK
(0=unmasked, 1=masked). Masked parameters do not generate an interrupt when their state changes.
When the host reads the INT_ACK registers, the interrupt is reset causing the INT pin to go to a logic 1
and the INT_ACK register bits are cleared.
The power good signals from the integrated supplies are level sensitive, and they will continue to cause an
interrupt until the power good condition returns or the signal is masked. For non-masked power good
parameters the INT_ACK bit will indicate the present state of the power good signals. The INTMASK
register bits are cleared to 0 upon power-up.
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Table 3-67. INT_ACK registers
INT_ACK1 [Addr 0xB5]
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
ACK_PLDO7
ACK_PLDO6
ACK_PLDO5
ACK_PLDO4
ACK_PLDO3
ACK_PLDO2
ACK_PLDO1
ACK_PLDO0
INT_ACK2 [Addr 0xB6]
Bit Name
ACK_PSM3
ACK_PSM2
ACK_CHGTEMP
RSVDB86(2)
ACK_PSM1
ACK_CHGSTAT
RSVDB85
ACK_PSM0
ACK_BATDET
RSVDB84
ACK_PLDO9
ACK_ACDET
RSVDB83
ACK_PLDO8
ACK_USBDET
ACK_RTCACM2
ACK_ADC
ACK_ COMPDET(1)
ACK_RTCALM1
ACK_RESUME
INT_ACK3 [Addr 0xB7]
Bit Name
INT_ACK4 [Addr 0xB8]
Bit Name RSVDB87
ACK_PP
ACKACUSBOVP
ACK_LOWSYS
(1) ACK_COMPDET= ACK INT BY HOTRST FLAG SET
(2) RSVDB86= ACK INT BY SLEEP REQUEST
Table 3-68. INTMASK Registers
INTMASK1 [Addr 0xB0]
Default to 1 (Masked)
IMASK_PLDO0
Bit Name
IMASK_PLDO7
IMASK_PLDO6
IMASK_PSM2
IMASKACSW
RSVD
IMASK_PLDO5
IMASK_PSM1
IMASKUSBSW
RSVD
IMASK_PLDO4
IMASK_PSM0
IMASKBCHGSW
RSVD
IMASK_PLDO3
IMASK_PLDO9
RSVDB23
IMASK_PLDO2
IMASK_PLDO1
IMASKADC
INTMASK2 [Addr 0xB1]
Default to 1 (Masked)
RSVDB10
Bit Name
IMASK_PSM3
IMASK_PLDO8
IMASK_HOT
RSVD
INTMASK3 [Addr 0xB2]
Default to 1 (Masked)
IMASKBATDET
Bit Name
IMASKSYSSW
IMASK_COLD
IMASKRTCALM2
IMASKAC_OVP
INTMASK4 [Addr 0xB3]
Bit Name
Default to 1 (Masked)
IMASK_COMP
RSVD
IMASK_TSHUT
IMASKACDET
INTMASK5 [Addr 0xB4]
Bit Name
Default to 1 (Masked)
IMASKUSB_OVP
RSVDB47
IMASKLOWSYS
IMASKRESUME
IMASKRTCALM1
IMASKUSBDET
The interrupt controller can monitor either level or edge transitions to generate the interrupt request:
PARAMETER
STATUS BIT
SET INT_ACK BIT ON
MASK reg/bit
INT_ACK reg/bit
ACK clear at
LDO0 power good fault
None
PGOOD FAULT DETECTED INTMASK1 /
IMASK_PLDO0
INT_ACK1 / ACK_LDO0
Read INT_ACK1
LDO1 power good fault
LDO2 power good fault
LDO3 power good fault
LDO4 power good fault
LDO5 power good fault
LDO6 power good fault
LDO7 power good fault
LDO8 power good fault
LDO9 power good fault
None
None
None
None
None
None
None
None
None
PGOOD FAULT DETECTED INTMASK1 /
IMASK_PLDO1
INT_ACK1 / ACK_PLDO1
INT_ACK1 / ACK_PLDO2
INT_ACK1 / ACK_PLDO3
INT_ACK1 / ACK_PLDO4
INT_ACK1 / ACK_PLDO5
INT_ACK1 / ACK_PLDO6
INT_ACK1 / ACK_PLDO7
INT_ACK2 / ACK_PLDO8
INT_ACK2 / ACK_PLDO9
Read INT_ACK1
Read INT_ACK1
Read INT_ACK1
Read INT_ACK1
Read INT_ACK1
Read INT_ACK1
Read INT_ACK1
Read INT_ACK2
Read INT_ACK2
PGOOD FAULT DETECTED INTMASK1 /
IMASK_PLDO2
PGOOD FAULT DETECTED INTMASK1 /
IMASK_PLDO3
PGOOD FAULT DETECTED INTMASK1 /
IMASK_PLDO4
PGOOD FAULT DETECTED INTMASK1 /
IMASK_PLDO5
PGOOD FAULT DETECTED INTMASK1 /
IMASK_PLDO6
PGOOD FAULT DETECTED INTMASK1 /
IMASK_PLDO7
PGOOD FAULT DETECTED INTMASK2 /
IMASK_PLDO8
PGOOD FAULT DETECTED INTMASK2 /
IMASK_PLDO9
SM0 power good fault
SM1 power good fault
SM2 power good fault
SM3 over-voltage detection
None
None
None
None
PGOOD FAULT DETECTED INTMASK2 / IMASK_PSM0 INT_ACK2 / ACK_PSM0
PGOOD FAULT DETECTED INTMASK2 / IMASK_PSM1 INT_ACK2 / ACK_PSM1
PGOOD FAULT DETECTED INTMASK2 / IMASK_PSM2 INT_ACK2 / ACK_PSM2
Read INT_ACK2
Read INT_ACK2
Read INT_ACK2
Read INT_ACK2
SM3 OVER-VOLTAGE
DETECTED
INTMASK2 / IMASK_PSM3 INT_ACK2 / ACK_PSM3
HOT RESET FLAG STATUS STAT2 bit 0
HI→LO OR LO→HI
INTMASK4 / IMASK_COMP INT_ACK2 /
ACK_COMPDET
Read INT_ACK2
BATSYS switch STATUS
ACSYS SWITCH STATUS
USBSYS SWITCH STATUS
BATCHG SW STATUS
STAT1 bit 7
STAT1 bit 6
STAT1 bit 5
STAT1 bit 4
HI→LO OR LO→HI
HI→LO OR LO→HI
HI→LO OR LO→HI
HI→LO OR LO→HI
INTMASK3 / IMASKSYSSW INT_ACK3 / ACK_PP
Read INT_ACK3
Read INT_ACK3
Read INT_ACK3
Read INT_ACK3
INTMASK3 / IMASKACSW
INT_ACK3 /ACK_PP
INTMASK3 / IMASKUSBSW INT_ACK3 /ACK_PP
INTMASK3 / IMASK_TERM INT_ACK3 /ACK_PP
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ACK clear at
PARAMETER
STATUS BIT
SET INT_ACK BIT ON
MASK reg/bit
INT_ACK reg/bit
PACK HOT DETECTION
STAT1 bit 2
HI→LO OR LO→HI
INTMASK3 /
IMASK_TSHUT
INT_ACK3
/ACK_CHGTEMP
Read INT_ACK3
Read INT_ACK3
Read INT_ACK3
Read INT_ACK3
Read INT_ACK4
PACK COLD DETECTION
BATTERY INSERTION
SLEEP and tshut detected
STAT1 bit 1
STAT1 bit 0
STAT2 bit 3
STAT3 bit7
HI→LO OR LO→HI
HI→LO OR LO→HI
HI→LO OR LO→HI
LO→HI
INTMASK3 /
IMASKCHSTAT
INT_ACK3
/ACK_CHGTEMP
INTMASK3 /
IMASKBATDET
INT_ACK3 /ACK_BATDET
INTMASK4 /
IMASK_TSHUT
INT_ACK3
/ACK_CHGSTAT
SLEEP REQUEST
DETECTED
INTMASK2/RSVDB10
INT_ACK4 / RSVDB86
AC DETection
STAT3 bit 3
STAT3 bit 2
HI→LO OR LO→HI
HI→LO OR LO→HI
INTMASK5 / IMASKACDET INT_ACK3 / ACK_ACDET
Read INT_ACK3
Read INT_ACK3
USB DETection
INTMASK5 /
INT_ACK3 /
IMAKSUSBDET
ACKACUSBOVP
AC OVP
STAT3 bit 1
STAT3 bit 0
NONE
HI→LO OR LO→HI
HI→LO OR LO→HI
ALARM1 DETECTED
ALARM2 DETECTED
HI→LO OR LO→HI
HI→LO OR LO→HI
LO→HI ONLY
INTMASK5 /
IMAKSAC_OVP
INT_ACK3 /
ACKACUSBOVP
Read INT_ACK3
Read INT_ACK3
Read INT_ACK3
Read INT_ACK4
USB OVP
INTMASK5 /
IMASKUSB_OVP
INT_ACK3 /
ACKACUSBOVP
RTC ALARM1
RTC ALARM2
RESUME command
LOWSYS detection
DADC0INT
INTMASK5 /
IMAKSRTCALM1
INT_ACK3 /
ACK_RTCALM1
NONE
INTMASK4 /
IMASKRTCALM2
INT_ACK4 /
ACK_RTCALM2
STAT3 bit 5
STAT3 bit 6
STAT4 bit 0
INTMASK5 /
IMASKRESUME
INT_ACK4 / ACK_RESUME Read INT_ACK4
INT_ACK4 / ACK_LOWSYS Read INT_ACK4
INTMASK5 /
IMASKLOWSYS
INTMASK2 / IMASKADC
INT_ACK4 / ACK_ADC
Read ADC0_INT
3.47 DEVICE ID RAM REGISTER
This device has a unique 8-bit identifier stored in the read only register VERSIONID.
Table 3-69. Device ID Register
VERSIONID [Addr 0xCD]
Bit Number
Bit Name
B7
B6
B5
B4
B3
B2
B1
B0
VCRC7
VCRC6
VCRC5
VCRC4
VCRC3
VCRC2
VCRC1
VCRC0
Device Number
TPS658629-Q1
VERSION IDENTIFICATION, FACTORY SET
1
0
1
0
0
0
0
0
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3.48 RAM MEMORY MAP
REGISTER
NAME
MEMORY AREA
ADDR
R/W DESCRIPTION
SUPPLY CONTROL AND
VOLTAGE SETTING
0x10
0x11
0x12
SUPPLYENA
SUPPLYENB
SUPPLYENC
R/W LDO2, SM0, SM1 ENABLE CONTROL
R/W LDO2, SM0, SM1 ENABLE CONTROL
R/W LDO0, LDO1. LDO3, LDO4, LDO6, LDO7, LDO8, SM2 ENABLE
CONTROL
0x13
0x14
0x20
0x21
SUPPLYEND
SUPPLYENE
VCC1
R/W LDO0, LDO1. LDO3, LDO4, LDO6, LDO7, LDO8, SM2 ENABLE
CONTROL
R/W TPS658629-Q1 OPERATION MODE, LDO5, LDO9 ENABLE
CONTROL
R/W SM0, SM1, LDO2, LDO4 VOLTAGE SELECTION / CHANGE
CONTROL
VCC2
R/W SM0, SM1, LDO2, LDO4 VOLTAGE SELECTION / CHANGE
CONTROL
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2F
0x30
0x32
0x33
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4C
SM1V1
R/W SM1 VOLTAGE SETTING #1
R/W SM1 VOLTAGE SETTING #2
R/W SM1 SLEW RATE
SM1V2
SM1SL
SM0V1
R/W SM0 VOLTAGE SETTING #1
R/W SM0 VOLTAGE SETTING #2
R/W SM0 SLEW RATE
SM0V2
SM0SL
LDO2AV1
LDO2AV2
LDO2BV1
LDO2BV2
LDO4V1
LDO4V2
SUPPLYV1
SUPPLYV2
SUPPLYV3
SUPPLYV4
SUPPLYV5
SUPPLYV6
SMODE1
SMODE2
CHG1
R/W LDO2 VOLTAGE SETTING #1
R/W LDO2 VOLTAGE SETTING #2
R/W LDO2 VOLTAGE SETTING #1
R/W LDO2 VOLTAGE SETTING #2
R/W LDO4 VOLTAGE SETTING # 1
R/W LDO4 VOLTAGE SETTING # 2
R/W LDO1, LDO0 OUPUT VOLTAGE
R/W SM2, LDO8 OUTPUT VOLTAGE
R/W LDO6, LDO7 OUTPUT VOLTAGE
R/W RTC_LDO, LDO3 OUTPUT VOLTAGE, RTC_LDO ON/OFF
R/W SPARE
CONVERTER SETTINGS
R/W LDO5, LDO9 OUTPUT VOLTAGE
R/W SM0, SM1, SM2, PWM/PFM MODE SETTING
R/W SPARE
CONTROL SETTINGS
R/W CONTROL SETTINGS
CHG2
R/W CONTROL SETTINGS
POWER PATH SETUP
RAM
PPATH2
R/W OUT POWER PATH SETTINGS
TPS658629-Q1
SEQUENCING
0x4D
0x4E
0xCC
PGFLTMSK1
PGFLTMSK2
SPARE2
R/W POWER GOOD FAULT MASK
R/W POWER GOOD FAULT MASK
R/W REBOOT CYCLE FLAG RESET
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ADDR
hex
MEMORY AREA
REGISTER NAME
ACC
DESCRIPTION
PERIPHERAL
CONTROL RAM
0X50 RGB1FLASH
0X51 RGB1RED
0X52 RGB1GREEN
0X53 RGB1BLUE
0X54 RGB2RED
0X55 RGB2GREEN
0X56 RGB2BLUE
0X57 SM3_SET0
0X58 SM3_SET1
0X59 LED_PWM
0X5A DIG_PWM
0X5B PWM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
RGB1R/G/B DRIVERS FLASH MODE SETTINGS
RGB1 RED DRIVER INTENSITY CONTROL
RGB1 GREEN DRIVER INTENSITY CONTROL
RGB1 BLUE DRIVER INTENSITY CONTROL
RGB2 RED DRIVER INTENSITY CONTROL
RGB2 GREEN DRIVER INTENSITY CONTROL
RGB2 BLUE DRIVER INTENSITY CONTROL
WHITE LED DUTY CYCLE SETTINGS
WHITE LED DUTY CYCLE SETTINGS
LED_PWM DRIVER DUTY CYCLE SETTINGS
DIG_PWM DRIVER DUTY CYCLE SETTINGS
PWM DRIVER DUTY CYCLE SETTINGS
DIG_PWM1 DRIVER DUTY CYCLE SETTINGS
GPIO CONFIGURATION
0X5C DIG_PWM1
0X5D GPIOSET1
0X5E GPIOSET2
GPIO CONFIGURATION
ADC0 ENGINE
SETUP RAM
0x60
ADCANLG
ADC INPUT BIAS AND FILTER CONTROL
ADC0 CONVERSION CYCLE SETUP
ADC0 CONVERSION CYCLE SETUP
ADC0 HI LIMIT THRESHOLD
ADC0 HI LIMIT THRESHOLD
ADC0 LO LIMIT THRESHOLD
ADC0 LO LIMIT THRESHOLD
ADC0 TRIGGER MODE
0X61 ADC0_SET
0X62 ADC0_WAIT
0X63 ADC0_HILIMIT2
0X64 ADC0_HILIMIT1
0X65 ADC0_LOLIMIT2
0X66 ADC0_LOLIMIT1
0X67 ADC0_DELAY
ADC0 ENGINE
DATA RAM
0x94
0x95
0x96
0x97
0x98
0x99
ADC0_SUM2
ADC0_SUM1
ADC0_MAX2
ADC0_MAX1
ADC0_MIN2
ADC0_MIN1
SUM OF ALL SAMPLES
R
SUM OF ALL SAMPLES
R
MAX SAMPLE VALUE
R
MAX SAMPLE VALUE
R
MIN SAMPLE VALUE
R
MIN SAMPLE VALUE
0x9A ADC0_INT
0xB0 INT_MASK1
0xB1 INT_MASK2
0xB2 INT_MASK3
0xB3 INT_MASK4
0xB4 INT_MASK5
0xB5 INT_ACK1
0xB6 INT_ACK2
0xB7 INT_ACK3
0xB8 INT_ACK4
0xB9 STAT1
R
ADC0 STATUS
INTERRUPT
CONTROL RAM
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
INT_MASK
INT MASK
INT MASK
INT MANAGEMENT
INT MANAGEMENT
INT MANAGEMENT REGISTER
INT MANAGEMENT REGISTER
INT MANAGEMENT REGISTER
INT MANAGEMENT REGISTER
POWER PATH SWITCHES, PACK STATUS
STATUS
SYSTEM
STATUS RAM
0xBA STAT2
R
0xBB STAT3
R
RTC, INPUT POWER STATUS
ADC STATUS
0xBC STAT4
R
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ADDR
hex
MEMORY AREA
RTC
REGISTER NAME
ACC
DESCRIPTION
0xC0 RTC_CTRL
R/W
RTC CONTROL REGISTER
RTC ALARM
0XC1 RTC ALARM
0xC2
0xC3
0xC4
0xC5
0xC6 RTC COUNTER
R/W
RTC DATA
0xC7
0xC8
0xC9
0xCA
DEVICE ID
0XCD VERSIONCRC
R
DEVICE IDENTIFICATION
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4 APPLICATION INFORMATION
4.1 DC/DC CONVERTER OUTPUT FILTER
4.1.1 Inductor Selection
The typical value for the converter inductor is 2.2μH output inductor. Larger or smaller inductor values can
be used to optimize the performance of the device for specific operation conditions. The selected inductor
has to be rated for its DC resistance and saturation current. The DC resistance of the inductance will
influence directly the efficiency of the converter. Therefore an inductor with lowest DC resistance should
be selected for highest efficiency. See document SLVA157 for more information on inductor selection.
Equation 11 calculates the maximum inductor current under static load conditions. The saturation current
of the inductor should be rated higher than the maximum inductor current as calculated with Equation 11.
This is recommended because during heavy load transient the inductor current will rise above the
calculated value.
Vout
1-
DIL
Vin
DIL = Vout ´
ILmax = Ioutmax +
L ´ ¦
2
(11)
with:
f = Switching Frequency (2.25MHz typical)
L = Inductor Value
ΔIL= Peak to Peak inductor ripple current
ILmax = Maximum Inductor current
The highest inductor current will occur at maximum Vin.
Open core inductors have a soft saturation characteristic and they can usually handle higher inductor
currents versus a comparable shielded inductor. A more conservative approach is to select the inductor
current rating just for the maximum switch current of the corresponding converter. It must be considered,
that the core material from inductor to inductor differs and will have an impact on the efficiency especially
at high switching frequencies.
Refer to Table 4-1 and the typical applications for possible inductors.
Table 4-1. Inductors
INDUCTANCE
TYP DIMENSIONS
[mm]
SUPPLY
INDUCTOR TYPE
SUPPLIER
[μH]
SM0
LPS4012-152
VLS4012-1R5N1R5
LPS4012-152
1.5
1.5
1.5
1.5
1.5
1.5
4.7
4.7
Coilcraft
TDK
4x4x1
4x4x1
4x4x1
4x4x1
4x4x1.5
4x4x2.5
2x2x1
3x3x1
SM1
SM2
SM3
Coilcraft
TDK
VLS4012-1R5N1R5
LPS4414-152MLx
1008PS-152Kx
Coilcraft
Coilcraft
Coilcraft
TDK
DO2010-472
VLS3012-47M1R0
4.1.2 Output Capacitor Selection
The advanced Fast Response voltage mode control scheme of the two converters allow the use of small
ceramic capacitors with a typical value of 22μF, without having large output voltage under and overshoots
during heavy load transients. Ceramic capacitors having low ESR values result in lowest output voltage
ripple and are therefore recommended. Refer to for recommended components.
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If ceramic output capacitors are used the capacitor RMS ripple current rating will always meet the
application requirements. Just for completeness the RMS ripple current is calculated as:
Vout
1-
1
Vin
IRMSCout = Vout ´
´
L ´ f
2 ´
3
(12)
At nominal load current the inductive converters operate in PWM mode and the overall output voltage
ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused
by charging and discharging the output capacitor:
Vout
1-
æ
ç
è
ö
÷
ø
1
Vin
DVout = Vout ´
´
+ ESR
L ´ ¦
8 ´ Cout ´ ¦
(13)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converters operate in Power Save Mode and the output voltage ripple is
dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay
and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.
4.1.3 Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high
input voltage spikes. The converters need a ceramic input capacitor of 10μF. The input capacitor can be
increased without any limit for better input voltage filtering.
Table 4-2. Capacitors
22 μF
22 μF
10 μF
10 μF
0805
0805
0805
0805
TDK C2012X5R0J226MT
Taiyo Yuden JMK212BJ226MG
Taiyo Yuden JMK212BJ106M
TDK C2012X5R0J106M
Ceramic
Ceramic
Ceramic
Ceramic
4.2 XTAL OSCILLATOR PCB – GENERAL GUIDELINES
Table 4-3. External Crystal Specifications
EXTERNAL CRYSTAL REQUIREMENTS [TYP CRYSTAL – EPSON MC146]
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
kHz
FOSC
Nominal crystal resonant frequency
ΔF/FOSC
32.768
Frequency Tolerance
–20
20
0.04×10–6
65
ppm
1/°C2
kΩ
B
Parabolic Temp Co
Equivalent Series Resistance
Load Capacitance
Shunt capacitance
Drive power
ESR
CLOAD
CSHUNT
PDRIVE
Aging
7
pF
0.5
–3
0.8
0.5
1.2
1
pF
μW
3
ppm/Yr
The jitter observed in the OUT32K pin is heavily dependent on the board layout close to the XTAL1 and
XTAL2 pins. The following layout/assembly procedures are recommended :
•
•
Layout a good ground plane around the oscillator pins.
Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
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•
•
•
Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the
oscillator pins.
•
External capacitance is recommended for precision real-time clock applications.
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4.3 APPLICATION CIRCUIT
4.3.1 Power Path, ADC, RTC and Ground Plane
0.22µF
1V25
TPS6586xx
XTAL1
XTAL2
4.7µF
ADC_REF
AGND2
ANLG1
ANLG2
ANLG3
4.7µF
2V2
AVDD6
AGND
2.2µF
SYSTEM CORE
POWER BUS
2V2
AGND
VSYS
22µF
SYS
AGND
FLTDPPM
+
-
GND
AC_DC ADAPTER
OUTPUT
1µF
1µF
AC
USB
+
USB POWER
-
GND
RTS
VTSBIAS
BAT
4.7µF
TS
RTS
AGNDn
ANALOG
DGNDn
DIGITAL
GROUND
PLANE
GROUND
PLANE
AGND
DGND
POWER GROUND PLANE
SUPPLY GROUND PLANE
GND
GROUND STAR
P1 P2 P3 P4
OONECTION
SEE PCB LAYOUT
GUIDELINES
Figure 4-1. Power Path, ADC, RTC Connections
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4.3.2 Integrated Supplies
VSYS
TPS6586xx
VIN_SM0
L0
LSM0
1.5µH
VSM0
VSM1
VSM2
10µF
P0
SM0
10µF
10µF
10µF
PGND0
VIN_SM1
L1
LSM1
1.5µH
10µF
P1
SM1
PGND1
VIN_SM2
L2
LSM2
1.5µH
10µF
P2
SM2
PGND2
Supercap
330
RTC_OUT
1µF
1µF
2.2µF
2.2µF
1µF
LDO5
VINLDO23
VINLDO23
LDO2
LDO3
VINLDO678
VINLDO678
LDO8
1µF
2.2µF
2.2µF
LDO6
2.2µF
2.2µF
2.2µF
LDO7
VINLDO4
VINLDO4
VIN_LDO4
LDO4
1µF
1µF
VIN_LDO01
LDO0
2.2µF
LDO1
VINLDO9
1µF
2.2µF
VLDO9
VLDO1
VLDO0
AGND
VLDO4
VLDO7
VLDO6
VLDO8
VLDO3
VLDO2
VLDO5
VRTC_OUT
(1) VIN_SMn pins must be always connected to VSYS .
(2) The supply input pins must be connected to VSYS or to the output of a supply which is powered from VSYS
Figure 4-2. Supply Rail Connections
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4.3.3 Display and Peripherals
VRAIL
2K
LED_PWM
TPS6586xx
SM3SW
L3
4.7uH
VSYS
SM3
FB3
WHITE LEDS
RFB3
33
100pF
P3
100pF
PGND3
ISM3G
RFB3A
15
PWM
VoLDOn
M
DIGPWM
TO DIGITAL INPUT
DIGPWM2
RGB LED
RED1
GREEN1
BLUE1
RGB LED
RED2
GREEN2
BLUE2
(1) PWM pin shown as driving an external vibrator motor, with vibrator supply connected to LDOn output
(2) VRAIL can be the output of any of the TPS658629-Q1 integrated supplies or the SYS pin
(3) 1. DIGPWM, DIGPWM2 are push-pull outputs
Figure 4-3. Display and PWM Connections
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4.3.4 Host Connections
VI2C
TPS6586xx
VIO
SCLK
SDAT
PSCLK
PSDAT
nINT
VIO
100kW
GPIO1
GPIO2
GPIO3
GPIO4
HOST
V32K
32KOUT
CHG_STAT
nNORTC
nNOPOWER
LDO4EN
SM1EN
SM0EN
SYNCEN
HOST SEQUENCING AND
RESET CONTROL
SM0PG
SM1PG
LDO4PG
RESUME
nHOTRST
CNOPOWER
TNOPOWER
(1) Those are generic connections only
(2) VIO should be connected to the TPS658629-Q1 rail that powers the host I/O domain
(3) VI2C should be connected to 2v2 or to the TPS658629-Q1 rail that powers the host I2C engine domain
Figure 4-4. Generic Host and Sequencing Circuit Connections
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4.3.5 Sequence Connections
TPS65862xx
V2V2
V2V2
LDO4EN
nCORECTRL
nCORECTRL
LDO4
LDO4
LDO4
V32K
SYNCEN
CPU_CTRL
SM1EN
4.3.6 Sequence Timing (TPS658629-Q1)
3.3
Power Applied
RTC_OUT
2V2
nNORTC
RESUME
1.2V
INTERNAL + 2.5ms
LDO2
SM0
1.2V
SM0EN + 3.75ms
1.8V
INTERNAL +_0ms
SM2
1.8V
INTERNAL + 15ms
LDO4
2.85V
SYNCEN + 2.5ms
LDO9
LDO1
1.1V
INTERNAL + 3.75ms
0
2.5 5.0
Power
Applied
7.5
TIME (ms)
17.5 20.0
10.0 12.5 15.0
Figure 4-5. Sequence Timing
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STABLE
OUT32k
320 ms
nNOPOWER
OUT32k + 1ms
0 ms
Figure 4-6. Sequence Timing
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ZHCS099A –JUNE 2011–REVISED JUNE 2012
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June, 2011) to Revision A
Page
•
•
•
•
•
•
•
•
将 AEC-Q100 信息添加到了特性中。 ............................................................................................. 1
Changed max value of RDIG to 175. ............................................................................................. 5
Changed max value of V(RTCGOOD) to 145. ...................................................................................... 6
Changed min value of IUSB100 to 85. ............................................................................................. 8
Changed min value of IUSB500 to 380. ........................................................................................... 8
Changed min value of ISC to 310. ................................................................................................ 9
Added rising to V(OVP3) test conditions description. ....................................................................... 10
Changed max value of TSM3PWR(OFF) to 500. ................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS658629IZWSRQ1
ACTIVE
NFBGA
ZWS
169
1000 RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
TPS658629I
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS658629IZWSRQ1
NFBGA
ZWS
169
1000
330.0
24.4
12.35 12.35
2.3
16.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Oct-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
NFBGA ZWS 169
SPQ
Length (mm) Width (mm) Height (mm)
336.6 336.6 41.3
TPS658629IZWSRQ1
1000
Pack Materials-Page 2
PACKAGE OUTLINE
ZWS0169A
NFBGA - 1.4 mm max height
SCALE 1.100
PLASTIC BALL GRID ARRAY
12.1
11.9
B
A
BALL A1 CORNER
12.1
11.9
(0.9)
0.45
1.4 MAX
C
SEATING PLANE
0.12 C
BALL TYP
TYP
0.35
9.6 TYP
SYMM
(1.2) TYP
(1.2) TYP
N
M
L
K
J
H
G
F
SYMM
9.6
TYP
E
D
C
0.55
169X
0.45
0.15
0.05
C A B
C
B
A
0.8 TYP
1
2
3
4
5
6
7
8
9 10 11 12 13
0.8 TYP
BALL A1 CORNER
4221886/C 05/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
ZWS0169A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(0.8) TYP
169X ( 0.4)
1
2
5
6
8
9
12 13
3
4
7
10 11
A
B
C
(0.8) TYP
D
E
F
SYMM
G
H
J
K
L
M
N
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
METAL UNDER
SOLDER MASK
0.05 MAX
0.05 MIN
(
0.4)
METAL
(
0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221886/C 05/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SSZA002 (www.ti.com/lit/ssza002).
www.ti.com
EXAMPLE STENCIL DESIGN
ZWS0169A
NFBGA - 1.4 mm max height
PLASTIC BALL GRID ARRAY
(
0.4) TYP
(0.8) TYP
1
2
5
6
8
9
12 13
3
4
7
10 11
A
B
C
(0.8) TYP
D
E
F
SYMM
G
H
J
K
L
M
N
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4221886/C 05/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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