TPS659119BAIPFPRQ1 [TI]
具有 3 个降压转换器和 8 个 LDO 的汽车类 1.4V 至 5.5V 电源管理 IC | PFP | 80 | -40 to 85;型号: | TPS659119BAIPFPRQ1 |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有 3 个降压转换器和 8 个 LDO 的汽车类 1.4V 至 5.5V 电源管理 IC | PFP | 80 | -40 to 85 转换器 |
文件: | 总133页 (文件大小:1700K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS659119-Q1
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
TPS659119-Q1 汽车类集成电源管理单元顶层规范
1 特性
(CLK32KOUT) 和系统复位 (NRESPWRON)
安全装置
•
•
1
•
•
符合汽车应用要求
具有符合 AEC-Q100 的下列结果:
两个开关状态 LED 脉冲发生器和一个脉宽调制
(PWM) 发生器
–
–
–
器件温度 3 级:-40°C 至 85°C 的环境运行温度
范围
2 应用范围
器件人体模型 (HBM) 静电放电 (ESD) 分类等级
2
•
•
•
•
汽车
信息娱乐
器件充电器件模型 (CDM) ESD 分类等级 C4B
自动数据采集 (ADA)
组合仪表
•
•
•
支持 EEPROM 可编程性的嵌入式电源控制器
(EPC)
两个用于处理器内核(VDD1,VDD2)且支持动态
电压调节的高效降压直流到直流 (DC-DC) 转换器
3 说明
TPS659119-Q1 器件是一款集成型电源管理 IC,专用
于所搭载应用处理器需要多个电源轨的系统。 此器件
提供三个降压转换器、一个用于控制外部转换器的接口
以及 8 个 LDO,可灵活用于支持不同的处理器和应
用。
一个用于 I/O 电源 (VIO) 的高效降压 DC-DC 转换
器
•
•
一个控制外部 DCDC 转换器 (EXTCTRL) 的接口
8 个低压降 (LDO) 电压稳压器和 1 个实时时钟
(RTC) LDO(为内部 RTC 供电)
一个高速 I2C 通用控制命令接口 (CTL-I2C)
•
•
其中两个降压转换器为双处理器内核供电,并支持通过
专用的 I2C 接口动态调节电压,从而实现最优节能。
第 3 个转换器为系统中的输入和输出 (I/O) 以及存储器
供电。 通过控制外部转换器可以针对系统中的高电流
轨对外部转换器电压进行排序和调节。
两个用于控制电源的独立使能信号 (EN1,EN2),
此信号可被用作一个高速 I2C 接口,专门用于
VDD1 和 VDD2 电压调节。
•
•
热关断保护和热模检测
一个具有以下资源的实时时钟 (RTC):
–
–
快速启动 16.384MHz 晶体振荡器
器件信息(1)
由晶体振荡器、外部 32kHz 时钟或内部 32kHz
RC 振荡器供源的可配置时钟源
部件号
封装
封装尺寸(标称值)
TPS659119-Q1
HTQFP (80)
12.00mm x 12.00mm
–
–
日期、时间和日历
闹铃功能
(1) 要了解所有可用封装,请见数据表末尾的可订购产品附录。
LDO1
320 mA
•
9 个支持复用特性的可配置通用输入输出 (GPIO)
接口:
VDD1
0.6 to 1.5
12.5-mV Step
1.5
V
A
LDO2
320 mA
–
–
–
–
其中 4 个可针对外部资源启用,包括在加电序
列之中并由状态机控制
VDD2
0.6 to 1.5
Power Control State
Machine
LDO3
200 mA
V
12.5-mV Step
1.5
A
LDO4
50 mA
作为 GPI,GPIO 支持逻辑电平检测并可针对唤
醒生成可屏蔽中断
EEPROM
Watchdog
VIO
1.5V, 1.8 V, 2.5 V, 3.3
V
1.5
A
LDO5
300 mA
其中的 2 个 GPIO 具有驱动 LED 所需的 10mA
电流吸收能力
LDO6
300 mA
EXTCTRL
V/V to 3/7 V/V
65 steps
1
Thermal Monitoring and
Shutdown
通过一个外部 3MHz 时钟实现的 DCDC 开关同
步
LDO7
300 mA
Analog
References
PLL
LDO8
300 mA
LDOVRTC
and POR
•
•
两个用于冷复位 (HDRST) 的复位输入和一个用于
热复位输入的电源初始化复位 (PWRDN)
2
2x
I
C
2x LED Pulse Generator
Real-time
Clock
16-MHz
XTAL
9x GPIO
PWM Generator
包括在电源序列衷的 32kHz 时钟输出
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SWCS106
TPS659119-Q1
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
目录
7.23 LDO8..................................................................... 27
1
2
3
4
5
6
7
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
说明(继续) ........................................................... 4
Pin Configuration and Functions......................... 4
Specifications......................................................... 7
7.1 Absolute Maximum Ratings ...................................... 7
7.2 Handling Ratings....................................................... 7
7.3 Recommended Operating Conditions....................... 8
7.4 Thermal Characteristics ............................................ 8
7.5 External Component Recommendation .................... 8
7.6 I/O Pullup and Pulldown Characteristics................. 10
7.7 Digital I/O Voltage Electrical Characteristics........... 10
7.8 I2C Interface and Control Signals ........................... 12
7.24 Timing Requirements for Boot Sequence
Example ................................................................... 28
7.25 Power Control Timing Requirements.................... 28
7.26 Device SLEEP State Control Timing
Requirements........................................................... 29
7.27 Supplies State Control Through EN1 and EN2
Timing Characteristics.............................................. 29
7.28 VDD1 Supply Voltage Control Through EN1 Timing
Requirements........................................................... 29
7.29 Typical Characteristics.......................................... 34
Detailed Description ............................................ 36
8.1 Overview ................................................................. 36
8.2 Functional Block Diagram ....................................... 37
8.3 Feature Description................................................. 38
8.4 Device Functional Modes........................................ 42
8.5 Programming........................................................... 54
8.6 Register Maps......................................................... 58
Application and Implementation ...................... 117
9.1 Application Information.......................................... 117
9.2 Typical Application ................................................ 117
8
9
7.9 Switching Characteristics—I2C Interface and Control
Signals ..................................................................... 12
7.10 Power Consumption.............................................. 13
7.11 Power References and Thresholds....................... 13
7.12 Thermal Monitoring and Shutdown....................... 13
7.13 32-kHz RTC Clock ................................................ 14
7.14 VRTC LDO............................................................ 15
7.15 VIO SMPS............................................................. 15
7.16 VDD1 SMPS ......................................................... 16
7.17 VDD2 SMPS ......................................................... 17
7.18 EXTCTRL.............................................................. 19
7.19 LDO1 AND LDO2.................................................. 20
7.20 LDO3 and LDO4 ................................................... 22
7.21 LDO5..................................................................... 24
7.22 LDO6 and LDO7 ................................................... 25
10 Power Supply Recommendations ................... 121
11 Layout................................................................. 121
11.1 Layout Guidelines ............................................... 121
11.2 Layout Example .................................................. 122
12 器件和文档支持 ................................................... 123
12.1 器件支持.............................................................. 123
12.2 商标..................................................................... 123
12.3 静电放电警告....................................................... 123
12.4 术语表 ................................................................. 124
13 机械封装和可订购信息 ........................................ 124
4 修订历史记录
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (July 2014) to Revision E
Page
•
•
Updated the PSKIP rows for the TPS659119KBIPFPRQ1 in the EEPROM Configuration table ........................................ 49
已添加 column for TPS659119LBIPFP to and removed the TOP-SIDE MARKING row from the EEPROM
CONFIGURATION table in the BOOT CONFIGURATION AND SWITCH-ON AND SWITCH-OFF SEQUENCES
section .................................................................................................................................................................................. 49
Changes from Revision C (August 2013) to Revision D
Page
•
•
已更改 CDM 分类等级从 C4A 更改为 C4B,且更新了 CDM ESD 额定值以包含边角引脚值以及其它引脚值 ....................... 1
更新了数据表格式以包含新文档流程和以下新增条目: 器件信息表、概述部分、应用和实施部分、电源相关建议部
分、布局部分、器件和文档支持部分(目前包含词汇表)以及机械、封装和可订购信息部分。 另外还删除了附录 A:
功能寄存器并将寄存器映射和说明移动到了详细说明部分...................................................................................................... 1
•
•
Deleted the PARAMETER and TEST CONDITION column headings from the Absolute Maximum Ratings,
Recommended Operating Conditions, and External Component Recommendation tables ................................................. 7
Moved storage temperature range and ESD ratings from the Absolute Maximum Ratings table into the new
Handling Ratings table .......................................................................................................................................................... 7
•
•
Changed the TYP column to NOM in the Recommended Operating Conditions table.......................................................... 7
Replaced Characteristics with Requirements in all timing table titles ................................................................................... 7
2
版权 © 2013–2014, Texas Instruments Incorporated
TPS659119-Q1
www.ti.com.cn
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
•
•
Split the DC output parameter for each LDO into output voltage, step size, and output accuracy and removed
multiple TYP values ............................................................................................................................................................... 7
已添加 column for TPS659119KBIPFP (top-side marking) to the EEPROM CONFIGURATION table in the BOOT
CONFIGURATION AND SWITCH-ON AND SWITCH-OFF SEQUENCES section............................................................. 49
•
•
已添加 pullup resistors to VDDIO on the I2C pins in the Application Schematic image..................................................... 118
已添加 在文档末尾的封装选项附录以及封装材料信息页面................................................................................................. 123
Changes from Revision B (April 2013) to Revision C
Page
•
Added Storage Temperature range to ABSOLUTE MAXIMUM RATINGS table................................................................... 7
Changes from Revision A (April 2013) to Revision B
Page
•
Changed 0x20 to 0x22 for TPS659119HAIPFPRQ1 column in EEPROM Configuration table. .......................................... 49
版权 © 2013–2014, Texas Instruments Incorporated
3
TPS659119-Q1
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
5 说明(继续)
此器件还包含 8 个通用 LDO,能够提供大范围的电压和电流能力。 其中 5 个 LDO 支持 1 至 3.3V(步长
100mV),而其它 3 个 LED 支持 1 至 3.3V(步长 50mV)。 所有 LDO 均可由 I2C 接口完全控制。
除了电源稳压器,此器件还包含九个具有复用功能的可配置 GPIO,用于支持广泛的功能。 此器件中还包含一个嵌
入式电源控制器,用于管理系统的上电排序要求。 电源排序由 EEPROM 设定。
6 Pin Configuration and Functions
PFP Package, 0.5-mm Pitch
80-Pin HTQFP With Thermal Pad
Top View
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
61
62
63
64
65
VCC1
SLEEP
VCC5
VCCS
GPIO8
LDO3
CLK32KOUT
OSCEXT32K
OSC16MOUT
OSC16MIN
GPIO1
GPIO6
NRESPWRON
VCC2
35
34
33
32
31
66
67
68
69
70
VCC2
BOOT1
GPIO5
SW2
VREF
SW2
Thermal pad
REFGND
HDRST
VFBIO
30
29
28
27
26
GND2
71
72
73
74
75
GND2
GPIO7
VFB2
GPIO4
INT1
GNDIO
GNDIO
SWIO
GPIO2
LDO5
25
24
23
22
21
76
77
78
79
80
LDO5
SWIO
VCC4
VCCIO
VCCIO
VCC8
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
4
Copyright © 2013–2014, Texas Instruments Incorporated
TPS659119-Q1
www.ti.com.cn
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
Pin Functions
PIN
NAME
TYPE
I/O
DESCRIPTION
SUPPLIES
PU / PD
NO.
LDO8
1
Power
Digital
Analog
O
I
LDO regulator output
VCC3, REFGND
VRTC, DGND
VRTC, DGND
PD 5 µA
Programmable PD
(default active)
PWRHOLD
PWRDN
2
Switch-on, switch off control signal and GPI
Reset input, for example, thermal reset
3
4
I
PD
LDO6
Power
O
LDO regulator output
VCC3, REFGND
PD 5 µA
5
VCC3
LDO7
GPIO0
6
Power
Power
Digital
I
LDO6 and LDO7 power Input
LDO regulator output
VCC3, AGND2
VCC3, REFGND
VCC7, DGND
No
7
O
PD 5 µA
OD: external PU
8
I/O
GPIO, push pull and OD as output
9
LDO2
VCC6
LDO1
Power
Power
Power
O
I
LDO regulator output
LDO1, LDO2 power Input
LDO regulator output
VCC6, REFGND
VCC6, AGND2
VCC6, REFGND
No
No
No
10
11
12
13
14
O
I2C bidirectional-data signal and serial-peripheral-
interface data input (multiplexed)
SDA_SDI
SCL_SCK
EN2
15
16
17
18
Digital
Digital
Digital
Digital
I/O
I/O
I/O
I/O
VDDIO, DGND
VDDIO, DGND
VDDIO, DGND
VDDIO, DGND
External PU
External PU
External PU
External PU
I2C bidirectional-clock signal and serial-peripheral-
interface clock input (multiplexed)
Enable for supplies and voltage scaling dedicated to
I2C data
Enable for supplies and voltage scaling dedicated to
I2C clock
EN1
VDDIO
AGND2
19
20
21
22
23
24
25
26
Power
Power
I
Digital I/O supply
Analog ground
VDDIO, DGND
AGND2
No
No
I/O
VCCIO
SWIO
Power
Power
Power
Digital
I
VIO DC-DC power Input
VIO DC-DC switched output
VIO DC-DC power ground
GPIO
VCCIO, GNDIO
VCCIO, GNDIO
VCCIO, GNDIO
VRTC, DGND
No
O
No
GNDIO
GPIO4
I/O
No
I/O
OD
I
27
OD: External PU
VFBIO
28
29
30
31
Analog
Digital
Analog
Analog
VIO feedback voltage
Cold reset
VCC7, DGND
VRTC, DGND
REFGND
PD 5 µA
PD
HDRST
REFGND
VREF
I
I/O
O
Reference ground
Bandgap voltage
No
VCC7, REFGND
No
I/O
OD
I
GPIO5
BOOT1
GPIO1
32
33
34
Digital
Digital
Digital
GPIO
VRTC, DGND
VRTC, DGND
VRTC, DGND
OD: external PU
No
Power-up sequence selection
GPIO and LED1 output
I/O
OD
OD: External PU
External PD if not in
use
OSC16MIN
35
36
37
Analog
Analog
Digital
I
O
I
16.384-MHz crystal oscillator input
16.384-MHz crystal oscillator output
External 32-kHz clock input
VCC7, DGND
VCC7, DGND
VRTC, DGND
OSC16MOUT
OSCEXT32K
No
External PD if not in
use
LDO3
VCCS
VCC5
LDO4
TESTV
38
39
40
41
42
Power
Analog
Power
Power
Analog
O
I/O
I
LDO regulator output
VCC5, REFGND
VCC7, DGND
VCC5, AGND
VCC5, REFGND
VCC7, AGND
PD 5 µA
No
VCC7 voltage sense input
LDO3 and LDO4 power Input
LDO regulator output
No
O
O
PD 5 µA
No
Analog test output (DFT)
Copyright © 2013–2014, Texas Instruments Incorporated
5
TPS659119-Q1
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
Pin Functions (continued)
PIN
TYPE
I/O
DESCRIPTION
SUPPLIES
PU / PD
NAME
NO.
I/O
OD
O
GPIO3
43
Digital
GPIO and LED2 output
VRTC, DGND
OD: External PU
PD active during
device OFF
state.External pullup
when ACTIVE
NRESPWRON2
44
Digital
Second NRESPWRON output
VRTC, DGND
OD
VBACKUP
AGND
VCC7
45
46
47
48
49
50
51
52
53
54
Power
Power
Power
Power
Power
Analog
Digital
Analog
Power
Analog
I
I/O
I
Tie this pin to AGND
VBACKUP, AGND
AGND
No
Analog ground
No
VRTC power input and analog references supply
LDO regulator output
VCC7, REFGND
VCC7, REFGND
AGNDEX
No
VRTC
O
I/O
I
PD 5 µA
No
AGNDEX
VSENSE
EN
EXTCTRL resistive divider ground
EXTCTRL resistive divider output
EXTCTRL enable signal for external converter
EXTCTRL resistive divider input
Digital ground
VOUT, AGNDEX
VCC7, DGND
VOUT, AGNDEX
DGND
No
O
I
No
VOUT
No
DGND
VFB1
I/O
I
No
VDD1 feedback voltage
VCC7, DGND
PD 5 µA
Programmable PU
(default active)
PWRON
GND1
55
Digital
Power
I
External switch-on control (ON button)
VDD1 DC-DC power ground
VCC7, DGND
VCC1, GND1
56
57
58
59
60
61
I/O
No
No
No
SW1
Power
Power
O
VDD1 DC-DC switched output
VDD1 DC-DC power Input
VCC1, GND1
VCC1, GND1
VCC1
I
I
Programmable PD
(default active)
SLEEP
GPIO8
62
63
Digital
Digital
ACTIVE-SLEEP state transition control signal
GPIO
VDDIO, DGND
VRTC, DGND
I/O,
OD
OD: External PU
PD, disabled in
ACTIVE or SLEEP
state
CLK32KOUT
64
Digital
O
32-kHz clock output
VDDIO, DGND
I/O,
OD
GPIO6
65
66
Digital
Digital
GPIO
VRTC, DGND
VDDIO, DGND
OD: External PU
PD active during
device OFF state
NRESPWRON
O
I
Power off reset
67
68
69
70
71
72
VCC2
SW2
Power
Power
VDD2 DC-DC power input
VCC2, GND2
VCC2, GND2
No
No
O
VDD2 DC-DC switched output
GND2
GPIO7
Power
Digital
I/O
VDD2 DC-DC power ground
GPIO
VCC2, GND2
VRTC, DGND
No
I/O,
OD
73
OD: External PU
VFB2
INT1
74
75
Analog
Digital
I
VDD2 DC-DC feedback voltage
Interrupt flag
VCC7, DGND
VDDIO, DGND
PD 5 µA
No
O
I/O,
OD
GPIO2
LDO5
76
Digital
Power
GPIO and DC-DC clock synchronization
LDO regulator output
VRTC, DGND
OD: External PU
PD 5 µA
77
78
79
80
O
VCC4, REFGND
VCC4
VCC8
Power
Power
I
I
LDO5 power input
LDO8 power input
VCC4, AGND2
VCC8, AGND2
No
No
6
Copyright © 2013–2014, Texas Instruments Incorporated
TPS659119-Q1
www.ti.com.cn
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–2
MAX
UNIT
V
VCC1, VCC2, VCCIO, VCC3, VCC4, VCC5, VCC7, VCC8
VCC6, VDDIO
7
3.6
V
7
V
SW1, SW2, SWIO
10 ns Transient
7
V
VFB1,VFB2,VFBIO
VOUT, VSENSE
BOOT1
–0.3
–0.3
–0.3
3.6
V
7
V
VRTCMAX + 0.3
V
SDA_SDI, SCL_SCK, EN2, EN1, SLEEP, INT1, CLK32KOUT,
NRESPWRON
–0.3
VDDIOMAX + 0.3
V
Voltage range
PWRON
–0.3
–0.3
7
7
V
V
PWRHOLD, GPIO0
OSCEXT32K, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6,
GPIO7, GPIO8(2)
–0.3
7
V
HDRST
–0.3
–0.3
–0.3
–0.3
–0.3
–5
VRTCMAX + 0.3
V
V
OSC16MIN, OSC16MOUT
NRESPWRON2(2)
PWRDN(3)
5.7
7
V
7
V
VCCS
7
V
Peak output current range All other pins than power resources
Functional junction temperature range
5
mA
°C
–45
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VRTC supplies the I/O but the I/O can also be driven from VCC7 or to VCC7 voltage level.
(3) VRTC supplies the input supplied but can also be driven from VCC7 voltage level.
7.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
Human body model (HBM), per AEC-Q100-002(1)
–55
150
°C
–2000 2000
V
V
Electrostatic
discharge
Corner pins (1, 20, 21,
40, 41, 60, 61, and 80)
V(ESD)
–750
–500
750
500
Charged device model (CDM), per AEC Q100-011
Other pins
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Note: VCC7 should be connected to highest supply that is connected to device VCCx pin.
Exception: The VCC4, VCC5, VIN, and AVIN inputs can be higher than VCC7. VCCS can be higher than VCC7 if
VMBBUF_BYPASS = 0 (buffer is enabled).
MIN
2.7
1.7
4
NOM
MAX UNIT
VCC5, VCCS
5.5
5.5
V
V
V
V
V
V
V
V
VCC3, VCC4, VCC8
VCC1, VCC2, VCCIO, VCC7
5
5.5
VCC6, VDDIO
1.4
–0.1
0
3.3
3.6
VSENSE
6.5
PWRON
3.8
VDDIO
VRTC
5.5
Input voltage range
SDA_SDI, SCL_SCK, EN2, EN1, SLEEP, INT1, CLK32KOUT
PWRHOLD, HDRTS
1.65
1.65
3.45
5.5
GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
GPIO8, PWRDN
1.65
VRTC
5.5
V
VCCS
0
0
5.5
5.5
V
V
OSCEXT32K
7.4 Thermal Characteristics
over operating free-air temperature range (unless otherwise noted)
TPS659119-Q1
PFP (80 PINS)
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
34.1
9.6
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
10.1
0.3
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
ψJB
9.9
RθJC(bot)
0.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 External Component Recommendation
For crystal oscillator components, see the 32-kHz RTC Clock section. Note: The VCC7 supply must have enough
capacitance to specify that when the supply is switched off, voltage does not fall at a rate faster than 10 mV/ms. This ensures
that RTC domain data is maintained.
MIN
NOM
MAX
UNIT
POWER REFERENCES
CO(VREF)
VREF filtering capacitor
Connected from VREF to REFGND
100
nF
VDD1 SMPS
CI(VCC1)
Input capacitor
X5R or X7R dielectric
X5R or X7R dielectric
f = 3 MHz
10
10
µF
µF
CO(VDD1)
Output filter capacitor
CO filter capacitor ESR
Inductor
4
12
10
300
mΩ
µH
mΩ
LO(VDD1)
DCRL
2.2
LO inductor dc resistor
125
VDD2 SMPS
CI(VCC2)
Input capacitor
X5R or X7R dielectric
X5R or X7R dielectric
f = 3 MHz
10
10
µF
µF
CO(VDD2)
Output filter capacitor
CO filter capacitor ESR
Inductor
4
12
10
300
mΩ
µH
mΩ
LO(VDD2)
DCRL
2.2
LO inductor dc resistor
125
8
Copyright © 2013–2014, Texas Instruments Incorporated
TPS659119-Q1
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
External Component Recommendation (continued)
For crystal oscillator components, see the 32-kHz RTC Clock section. Note: The VCC7 supply must have enough
capacitance to specify that when the supply is switched off, voltage does not fall at a rate faster than 10 mV/ms. This ensures
that RTC domain data is maintained.
MIN
NOM
MAX
UNIT
VIO SMPS
CI(VCCIO)
CO(VIO)
Input capacitor
X5R or X7R dielectric
X5R or X7R dielectric
f = 3 MHz
10
10
µF
µF
Output filter capacitor
CO filter capacitor ESR
Inductor
4
12
10
300
mΩ
µH
mΩ
LO(VIO)
DCRL
2.2
LO inductor dc resistor
125
LDO1
CI(VCC6)
CO(LDO1)
Input capacitor
X5R or X7R dielectric
4.7
2.2
µF
µF
Output filtering capacitor
CO filtering capacitor ESR
0.8
0
2.64
500
mΩ
LDO2
CO(LDO2)
Output filtering capacitor
CO filtering capacitor ESR
0.8
0
2.2
2.64
500
µF
mΩ
LDO3
CI(VCC5)
CO(LDO3)
Input capacitor
X5R or X7R dielectric
4.7
2.2
µF
µF
Output filtering capacitor
CO filtering capacitor ESR
0.8
0
2.64
500
mΩ
LDO4
CO(LDO4)
Output filtering capacitor
CO filtering capacitor ESR
0.8
0
2.2
2.64
500
µF
mΩ
LDO5
CI(VCC4)
Input capacitor
X5R or X7R dielectric
VOUT(LDOx) > 1.2 V
VOUT(LDOx) ≤ 1.2 V
4.7
2.2
2
µF
µF
0.8
0.8
0
2.64
2.2
CO(LDO5)
Output filtering capacitor
CO filtering capacitor ESR
500
mΩ
LDO6
CI(VCC3)
Input capacitor
X5R or X7R dielectric
VOUT(LDOx) > 1.2 V
VOUT(LDOx) ≤ 1.2 V
4.7
2.2
2
µF
µF
0.8
0.8
0
2.64
2.2
CO(LDO6)
Output filtering capacitor
CO filtering capacitor ESR
500
mΩ
LDO7
VOUT(LDOx) > 1.2 V
0.8
0.8
0
2.2
2
2.64
2.2
CO(LDO7)
Output filtering capacitor
CO filtering capacitor ESR
µF
VOUT(LDOx) ≤ 1.2 V
500
mΩ
LDO8
CI(VCC8)
Input capacitor
X5R or X7R dielectric
VOUT(LDOx) > 1.2 V
VOUT(LDOx) ≤ 1.2 V
4.7
2.2
2
µF
µF
0.8
0.8
0
2.64
2.2
CO(LDO8)
Output filtering capacitor
CO filtering capacitor ESR
500
mΩ
VRTC LDO
CI(VCC7)
Input capacitor
X5R or X7R dielectric
4.7
2.2
µF
µF
CO(VRTC)
Output filtering capacitor
CO filtering capacitor ESR
0.8
0
2.64
500
mΩ
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7.6 I/O Pullup and Pulldown Characteristics
over operating free-air temperature range (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
MIN
–20%
2
TYP
120
4.5
MAX
UNIT
kΩ
GPIO0-8 external pullup resistor
Connected to VDDIO
20%
15
GPIO0-8 programmable pulldown (default active except GPIO0)
at 1.8 V, VRTC = 1.8 V, OFF state
Connected to VDDIO
µA
SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1 external pullup
resistor
1.2
8
kΩ
kΩ
µA
SDA_SDI, SCL_SCK, SDASR_EN2, SCLSR_EN1 programmable
pullup (DFT, default inactive)
Grounded, VDDIO = 1.8 V
–45%
2
45%
10
at 1.8 V, VRTC = 1.8 V; TA = 25°C
for PWRHOLD
SLEEP, PWRHOLD, programmable pulldown (default active)
4.5
NRESPWRON, NRESPWRON2 pulldown
at 1.8 V, VCC7 = 5.5 V, OFF state
at 1.8 V, VRTC = 1.8 V, OFF state
Grounded, VCC7 = 5.5 V
2
2
4.5
4.5
–31
4.5
10
10
µA
µA
µA
µA
32KCLKOUT pulldown (disabled in ACTIVE-SLEEP state)
PWRON programmable pullup (default active)
HDRST programmable pulldown (default active)
–43
2
–15
10
at 1.8 V, VRTC = 1.8 V
(1) The internal pullups on the CTL-I2C and SR-I2C pins are used for test purposes or when the SR-I2C interface is not used. Discrete
pullups to the VIO supply must be mounted on the board in order to use the I2C interfaces. The internal I2C pullups must not be used for
functional applications
7.7 Digital I/O Voltage Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
0.7 x VBAT
1.3
TYP
MAX
UNIT
RELATED I/O:
PWRON
VIL
VIH
Low-level input voltage
High-level input voltage
0.3 x VBAT
V
V
RELATED I/O:
PWRHOLD, GPIO0-8, PWRDN
VIL
VIH
Low-level input voltage
High-level input voltage
0.45
V
V
VBAT
RELATED I/O:
BOOT1
Low level input – Impedance between BOOT1 and GND
High level input – Impedance between BOOT1 and VRTC
Hi-Z level input – Impedance between BOOT1 and GND
10
10
kΩ
kΩ
kΩ
500
RELATED I/O:
SLEEP
0.35 x
VDDIO
VIL
Low-level input voltage
High-level input voltage
V
V
VIH
0.65 x VDDIO
0.65 x VRTC
RELATED I/O:
HDRST
VIL
VIH
Low-level input voltage
High-level input voltage
0.35 x VRTC
V
V
RELATED I/O:
NRESPWRON, INT1, 32KCLKOUT
IOL = 100 µA
IOL = 2 mA
0.2
V
V
V
V
VOL
Low-level output voltage
High-level output voltage
0.45
IOH = 100 µA
IOH = 2 mA
VDDIO – 0.2
VDDIO – 0.45
VOH
Related I/O:
EN
IOL = 100 µA
IOL = 2 mA
0.2
0.9
V
V
VOL
Low-level output voltage
10
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TPS659119-Q1
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
Digital I/O Voltage Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
VCC7– 0.2
TYP
MAX
UNIT
V
IOH = 100 µA
VOH
High-level output voltage
IOH = 2 mA
VCC7 – 0.45
V
RELATED I/O:
GPIO0 (PUSH-PULL MODE)
IOL = 100 µA
IOL = 2 mA
0.2
V
V
V
V
VOL
Low-level output voltage
High-level output voltage
0.45
IOH = 100 µA
IOH = 2 mA
VCC7 – 0.2
VOH
VCC7 – 0.45
RELATED OPEN-DRAIN I/O:
GPIO0, GPIO2, GPIO4-8, NRESPWRON2
IOL = 100 µA
IOL = 2 mA
0.2
V
V
VOL
Low-level output voltage
0.45
RELATED OPEN-DRAIN I/O:
GPIO1, GPIO3
IOL = 100 µA
IOL = 2 mA
0.2
0.4
V
V
VOL
Low-level output voltage
I
VIL
VIH
Low-level input voltage
High-level input voltage
Hysteresis
–0.5
0.7 x VDDIO
0.1 x VDDIO
0.3 x VDDIO
V
V
V
V
V
VOL
VOL
Low-level output voltage at 3 mA (sink current), VDDIO = 1.8 V
Low-level output voltage at 3 mA (sink current), VDDIO = 3.3 V
0.2 × VDDIO
0.4 x VDDIO
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7.8 I2C Interface and Control Signals
over operating free-air temperature range (unless otherwise noted)
(2)
NO.
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
UNIT
GENERAL REQUIREMENTS
INT1 rise and fall times
CL = 5 to 35 pF
CL = 5 to 35 pF
5
5
10
10
ns
ns
NRESPWRON rise and fall times
SLAVE HIGH-SPEED MODE
SCL/EN1 and SDA/EN2 rise and fall time CL = 10 to 100 pF
Data rate
10
80
ns
Mbps
ns
3.4
I3 tsu(SDA-SCLH)
I4 th(SCLL-SDA)
I7 tsu(SCLH-SDAL)
I8 th(SDAL-SCLL)
I9 tsu(SDAH-SCLH)
Setup time, SDA valid to SCL high
Hold time, SDA valid from SCL low
Setup time, SCL high to SDA low
Hold time, SCL low from SDA low
Setup time, SDA high to SCL high
10
0
70
ns
160
160
160
ns
ns
ns
SLAVE
FAST MODE
20 +
0.1 × CL
SCL/EN1 and SDA/EN2 rise and fall time CL = 10 to 400 pF
250
400
ns
Data rate
Kbps
ns
I3 tsu(SDA-SCLH)
I4 th(SCLL-SDA)
I7 tsu(SCLH-SDAL)
I8 th(SDAL-SCLL)
Setup time, SDA valid to SCL high
Hold time, SDA valid from SCL low
Setup time, SCL high to SDA low
Hold time, SCL low from SDA low
Setup time, SDA high to SCL high
100
0
0.9
µs
0.6
0.6
0.6
µs
µs
I9 tsu(SDAH-SCLH)
SLAVE STANDARD MODE
µs
SCL/EN1 and SDA/EN2 rise and fall time CL = 10 to 400 pF
Data rate
250
100
ns
Kbps
ns
I3 tsu(SDA-SCLH)
I4 th(SCLL-SDA)
I7 tsu(SCLH-SDAL)
I8 th(SDAL-SCLL)
I9 tsu(SDAH-SCLH)
Setup time, SDA valid to SCL high
Hold time, SDA valid from SCL low
Setup time, SCL high to SDA low
Hold time, SCL low from SDA low
Setup time, SDA high to SCL high
250
0
µs
4.7
4
µs
µs
4
µs
(1) The input timing requirements are given by considering a rising or falling time of: 80 ns in high–speed mode (3.4 Mbps) 300 ns in
fast–speed mode (400 kbps) 1000 ns in Standard mode (100 kbps)
(2) SDA is SDA_SDI or EN2 signal, SCL is SCL_SCK or EN1 signal
7.9 Switching Characteristics—I2C Interface and Control Signals
over operating free-air temperature range (unless otherwise noted)
NO.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SLAVE HIGH-SPEED MODE
I1
I2
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
160
60
ns
ns
SLAVE FAST MODE
I1
I2
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
1.3
0.6
µs
µs
SLAVE STANDARD MODE
I1
I2
tw(SCLL)
tw(SCLH)
Pulse duration, SCL low
Pulse duration, SCL high
4.7
4
µs
µs
12
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TPS659119-Q1
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
7.10 Power Consumption
over operating free-air temperature range (unless otherwise noted)
All current consumption measurements are relative to the FULL chip, all VCC inputs set to VBAT voltage, COMP2 is off.
PARAMETER
TEST CONDITIONS
VBAT = 5 V, XTAL oscillator running
MIN
TYP MAX
UNIT
mA
2.5
22
Device OFF state
VBAT = 5 V, Bypass clock used
µA
VBAT = 5 V, 3 DCDCs on in PFM mode, 5 LDOs on, no load,
XTAL oscillator running
Device SLEEP state
Device ACTIVE state
2.8
mA
mA
VBAT = 5 V, 3 DCDCs on in PWM mode, 5 LDOs on, no load,
XTAL oscillator running
26.6
7.11 Power References and Thresholds
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output reference voltage (VREF pin)
Device in active or low-power mode
–1%
0.85
1%
V
Measured on pin VCC7, falling
(Triggering monitored on pin VRTC)
Main battery not present falling threshold
VBNPR
1.8
3.58
2.1
2.3
3.96
3.87
200
V
V
The POR threshold for rising VCC7
voltages
3.77
3.68
The POR threshold for falling VCC7
voltages
PORXTAL
3.50
V
Difference between rising and falling
thresholds
62.55
89.35
mV
7.12 Thermal Monitoring and Shutdown
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
113
150
TYP
117
121
125
130
10
MAX
136
UNIT
THERM_HDSEL[1:0] = 00
THERM_HDSEL[1:0] = 01
THERM_HDSEL[1:0] = 10
THERM_HDSEL[1:0] = 11
Hot-die temperature rising threshold
°C
Hot-die temperature hysteresis
°C
°C
Thermal shutdown temperature rising threshold
165
107
111
115
120
180
THERM_HDSEL[1:0] = 00
THERM_HDSEL[1:0] = 01
THERM_HDSEL[1:0] = 10
THERM_HDSEL[1:0] = 11
Thermal shutdown temperature recovery
threshold
°C
Device in ACTIVE state, Temp = 27°C,
VCC7 = 3.8 V
Ground current
6
µA
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7.13 32-kHz RTC Clock
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
GENERAL CLK32KOUT
REQUIREMENTS
CLK32KOUT rise and fall time
EXTERNAL CLOCK
CL = 35 pF
10
ns
(OSC16MIN GROUNDED, OSC16MOUT FLOATING, AND OSCEXT32K INPUT)
Input bypass clock frequency
Input bypass clock duty cycle
Input bypass clock rise and fall time
CLK32KOUT duty cycle
OSCKIN input
32
10
kHz
ns
OSCKIN input
40%
40%
60%
20
10% – 90%, OSCEXT32K input
Logic output signal
32KCLKOUT output
Bypass mode
60%
1
Bypass clock setup time
Ground current
ms
µA
1.5
CRYSTAL
OSCILLATOR (CRYSTAL BETWEEN OSC16MIN AND OSC16MOUT, OSCEXT32K GROUNDED)
Crystal frequency
Crystal tolerance
at specified load cap value
at 27°C
16.384
0
MHz
ppm
–20
–50
20
50
TJ from –40°C to 125°C, VCC7 from 4 V to 5.5 V;
excluding crystal drift
Oscillator frequency drift
ppm
Max crystal series resistor
Oscillator startup time
Drive level power
at fundamental frequency
Power on until first time slot
Steady state operation
90
13.2
120
Ω
ms
µW
mA
15
Ground current
2.5
Overall frequency tolerance
Output frequency
CLK32KOUT output
–1%
1%
CLK32KOUT output
32.768
33
kHz
µH
pF
Crystal motional inductance
Crystal shunt capacitance
According to crystal data sheet
According to crystal data sheet
23
43
4
0.5
According to crystal data sheet;
including PCB parasitic capacitance
Crystal load capacitance
9
10
11
pF
RC OSCILLATOR
(OSC16MIN AND OSCEXT32K GROUNDED, OSC16MOUT FLOATING)
Output frequency
Output frequency accuracy
Cycle jitter (RMS)
Output duty cycle
Settling time
CK32KOUT output
at 25°C
32
0
kHz
–15%
40%
15%
10%
60%
150
Oscillator contribution
50%
4
µs
Ground current
Active at fundamental frequency
µA
14
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
7.14 VRTC LDO
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
2.5
TYP
MAX
5.5
3
UNIT
On mode
Input voltage VIN
V
Backup mode
1.9
On mode, 3 V < VIN < 5.5 V
1.78
1.72
20
1.83
1.78
1.9
1.9
DC output voltage VOUT
Rated output current IOUTmax
DC load regulation
V
Backup mode, 2.3 V ≤ VIN ≤ 2.6 V
On mode
mA
mV
mV
Backup mode
0.1
On mode, IOUT = IOUTmax to 0
Backup mode, IOUT = IOUTmax to 0
On mode, VIN = 3 V to VINmax at IOUT = IOUTmax
Backup mode, VIN = 2.3 V to 5.5 V at IOUT = IOUTmax
100
100
2.5
DC line regulation
100
On mode, VIN = VINmin + 0.2 V to VINmax
IOUT = IOUTmax/2 to IOUTmax in 5 µs
and IOUT = IOUTmax to IOUTmax / 2 in 5 µs
(1)
Transient load regulation
Transient line regulation
50
mV
mV
On mode, VIN = VINmin + 0.5 V to VINmin in 30 µs
and VIN = VINmin to VINmin + 0.5 V in 30 µs,
IOUT = IOUTmax / 2
(1)
25
IOUT = 0, VIN rising from 0 up to 3.6 V, at VOUT = 0.1 V up to
VOUTmin
Turn-on time
2.2
ms
dB
f = 217 Hz
f = 50 kHz
55
35
23
3
VIN = VINDC + 100 mVpp tone, VINDC+ = VINmin
0.1 V to VINmax at IOUT = IOUTmax / 2
+
Ripple rejection
Device in ACTIVE state
Ground current
µA
Device in BACKUP or OFF state
(1) These parameters are not tested. They are used for design specification only.
7.15 VIO SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input voltage (VCCIO and VCC7)
VIN
VOUT = 1.5 V, 1.8 V, 2.5 or 3.3 V
4
5.5
V
VSEL = 00
VSEL = 01
–1.5%
–1.5%
–1.5%
–1.5%
1.5
1.8
2.5
3.3
0
3%
3%
3%
3%
DC output voltage (VOUT
)
PWM mode (VIO_PSKIP = 0) IOUT = 0 VSEL = 10
V
VSEL = 11
Power down
Rated output current IOUTmax
P-channel MOSFET
TPS659119xAIPFPRQ1
VIN = VINmin
1500
mA
300
250
mΩ
On-resistance RDS(ON)_PMOS
VIN = 4 V
400
2
P-channel leakage current
ILK_PMOS
VIN = VINMAX, SWIO = 0 V
µA
N-channel MOSFET
VIN = VMIN
VIN = 4 V
300
250
mΩ
On-resistance RDS(ON)_NMOS
400
2
N-channel leakage current
ILK_NMOS
VIN = VINmax, SWIO = VINmax
µA
VIN = VINmin to VINmax source current load; when ILIM[1:0]
= 00
700
mA
PMOS and NMOS current limit
(high side and low side)
TPS659119xAIPFPRQ1
when ILIM[1:0] = 01
1200
1700
mA
mA
when ILIM[1:0] = 10
when ILIM[1:0] = 11
> 1700
mA
DC load regulation
On mode, IOUT = 0 to IOUTmax
60
mV/A
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VIO SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
On mode, VIN = VINmin to VINmax
at IOUT = 0
DC line regulation
30
mV
VOUT = 1.8 V
Transient load regulation
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 to 1200 mA , Max slew = 100 mA/µs
50
mV
µs
ton, off to on
Overshoot
IOUT = 200 mA
350
3%
SMPS turned on
0.025 ×
VOUT
Power-save mode ripple voltage PFM (pulse skip mode) mode, IOUT = 1 mA
VPP
Switching frequency
Duty cycle
2.7
0.5
3
3.3
MHz
100%
Minimum on time TON(MIN) P-
channel MOSFET
35
1
ns
VFBIO internal resistance
MΩ
Off
1
PWM mode, IOUT = 0 mA, VIN = 3.8 V, VIO_PSKIP = 0
7500
250
PFM (pulse skipping) mode, no switching, 3-MHz clock
Ground current (IQ)
µA
on
Low-power (pulse skipping) mode, no
ST[1:0] = 11
63
switching
IOUT = 10 mA
40%
83%
85%
80%
68%
80%
85%
IOUT = 100 mA
IOUT = 400 mA
IOUT = 600 mA
IOUT = 1 mA
PWM mode, DCRL < 50 mΩ, VOUT
=
1.8 V, VIN = 3.6 V:
Conversion efficiency
PFM mode, DCRL < 50 mΩ, VOUT
=
IOUT = 10 mA
IOUT = 400 mA
1.8 V, VIN = 3.6 V:
7.16 VDD1 SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4
TYP
MAX
5.5
UNIT
V
OUT ≤ 2.7 V
Input voltage (VCC1 and VCC7)
VIN
V
VOUT > 2.7 V
4
5.5
IOUT = 0 mA, PWM; VIN = 4 V to 5.5 V; VOUT > 1 V; ON
MODE:
DC output voltage (VOUT
)
–1.5%
3%
V
DC output voltage programmable
step (VOUTSTEP
VGAIN_SEL = 00, 72 steps
12.5
250
mV
mA
mΩ
)
Rated output current IOUTmax
1500
P-channel MOSFET on-resistance
RDS(ON)_PMOS
VIN = 4 V
400
2
P-channel leakage current
ILK_PMOS
VIN = VINmax, SW1 = 0 V
VIN = 4 V
µA
N-channel MOSFET on-resistance
RDS(ON)_NMOS
250
400
2
mΩ
N-channel leakage current
ILK_NMOS
VIN = VINmax, SW1 = VINmax
µA
PMOS current limit (high side)
NMOS current limit (low side)
DC load regulation
VIN = VINmin to VINmax
1700
1700
1700
mA
VIN = VINmin to VINmax, source current load
VIN = VINmin to VINmax, sink current load
On mode, IOUT = 0 to IOUTmax
mA
60
mV/A
16
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
VDD1 SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
On mode, VIN = VINmin to VINmax
at IOUT = 0
DC line regulation
30
mV
VOUT = 1.2 V
Transient load regulation
ton, off to on
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 mA to 1.2 A , Max slew = 100 mA/µs
50
mV
µs
IOUT = 200 mA
350
TSTEP[2:0] =
001
12.5
From VOUT = 0.6 V to 1.5 V and VOUT
1.5 V to 0.6 V IOUT = 500 mA
=
TSTEP[2:0] =
011 (default)
Output voltage transition rate
7.5
mV/µs
TSTEP[2:0] =
111
2.5
3%
Overshoot
SMPS turned on
0.025 ×
VOUT
Power-save mode ripple voltage
PFM (pulse skip mode), IOUT = 1 mA
VPP
Switching frequency
Duty cycle
2.7
0.5
3
3.3
MHz
100%
Minimum on time tON(MIN) P-
channel MOSFET
35
1
ns
VFB1 internal resistance
Ground current (IQ)
MΩ
Off
1
PWM mode, IOUT = 0 mA, VIN = 3.8 V, VDD1_PSKIP = 0
Pulse skipping mode, no switching
7500
78
µA
Low-power (pulse skipping) mode, no
ST[1:0] = 11
63
35%
78%
switching
IOUT = 10 mA
IOUT = 100
mA
IOUT = 400
mA
PWM mode, DCRL < 0.1 Ω, VOUT = 1.2
V, VIN = 4 V:
80%
74%
62%
IOUT = 800
mA
Conversion efficiency
IOUT = 1500
mA
IOUT = 1 mA
59%
70%
PFM mode, DCRL < 0.1 Ω, VOUT = 1.2 V, IOUT = 10 mA
VIN = 4 V:
IOUT = 400
mA
80%
7.17 VDD2 SMPS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
4
TYP
MAX
5.5
UNIT
V
OUT ≤ 2.7 V
Input voltage (VCC2 and VCC7)
VIN
V
VOUT > 2.7 V
4
5.5
VOUT = 0 mA, PWM; VIN = 4 V to 5.5 V; VOUT > 1 V; ON
MODE:
DC output voltage (VOUT
)
–1.5%
3%
V
DC output voltage programmable
VGAIN_SEL = 00, 72 steps
12.5
250
mV
mA
mΩ
step (VOUTSTEP
)
Rated output current IOUTmax
1500
P-channel MOSFET on-
resistance RDS(ON)_PMOS
VIN = 4 V
400
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VDD2 SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
P-channel leakage current
ILK_PMOS
VIN = VINmax, SW2 = 0 V
2
400
2
µA
N-channel MOSFET on-
resistance RDS(ON)_NMOS
VIN = 4 V
250
mΩ
N-channel leakage current
ILK_NMOS
VIN = VINmax, SW2 = VINmax
µA
PMOS current limit (high side)
VIN = VINmin to VINmax, source current load
VIN = VINmin to VINmax, source current load
VIN = VINmin to VINmax, sink current load
On mode, IOUT = 0 to IOUTmax
1700
1700
1700
mA
NMOS current limit (low side)
mA
DC load regulation
DC line regulation
60
30
mV/A
mV
On mode, VIN = VINmin to VINmax at IOUT = 0
VOUT = 1.2 V
Transient load regulation
ton, Off to on
IOUT = 0 to 500 mA , Max slew = 100 mA/µs
IOUT = 700 mA to 1.2 A , Max slew = 100 mA/µs
50
mV
µs
IOUT = 200 mA
350
TSTEP[2:0] = 001
12.5
From VOUT = 0.6 V to 1.5 V and
VOUT = 1.5 V to 0.6 V IOUT = 500
mA
TSTEP[2:0] = 011
(default)
Output voltage transition rate
7.5
mV/µs
TSTEP[2:0] = 111
2.5
3%
Overshoot
SMPS turned on
0.025 ×
VOUT
Power-save mode ripple voltage PFM (pulse skip mode), IOUT = 1 mA
VPP
Switching frequency
Duty cycle
2.7
0.5
3
35
1
3.3
MHz
100%
Minimum on time
P-Channel MOSFET
VFB2 internal resistance
Off
ns
MΩ
1
PWM mode, IOUT = 0 mA, VIN = 3.8 V, VDD2_PSKIP = 0
PFM (pulse skipping) mode, no switching
7500
78
Ground current (IQ)
µA
Low-power (pulse skipping) mode,
ST[1:0] = 11
63
no switching
18
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TPS659119-Q1
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
VDD2 SMPS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOUT = 10 mA
MIN
TYP
35%
78%
80%
74%
66%
62%
59%
70%
80%
39%
85%
91%
90%
86%
84%
80%
82%
92%
MAX
UNIT
IOUT = 100 mA
IOUT = 400 mA
IOUT = 800 mA
IOUT = 1200 mA
IOUT = 1500 mA
IOUT = 1 mA
PWM mode, DCRL < 50 mΩ, VOUT
= 1.2 V, VIN = 4 V:
PFM mode, DCRL < 50 mΩ, VOUT
IOUT = 10 mA
IOUT = 400 mA
IOUT = 10 mA
IOUT = 100 mA
IOUT = 400 mA
IOUT = 800 mA
IOUT = 1200 mA
IOUT = 1500 mA
IOUT = 1 mA
= 1.2 V, VIN = 4 V:
Conversion efficiency
PWM mode, DCRL < 50 mΩ, VOUT
= 3.3 V, VIN = 5 V:
PFM mode, DCRL < 50 mΩ, VOUT
IOUT = 10 mA
IOUT = 400 mA
= 3.3 V, VIN = 5 V:
7.18 EXTCTRL
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SEL[6:0] = 0 (EN signal low)
MIN
TYP
MAX
UNIT
1
1
SEL[6:0] = 1 to 3
For SEL[6:0] = 3 to 67
Ratio = 48 / (45 + SEL[6:0])
SEL[6:0] = 4
–0.7%
–0.7%
48:49
24:25
0.7%
0.7%
Ratio of VSENSE to VOUT
(Selectable voltage divider)
SEL[6:0] = 5
V/V
...
SEL[6:0] = 35
...
–0.7%
3:5
0.7%
SEL[6:0] = 66
SEL[6:0] = 67 to 127
–0.7%
–0.7%
16:37
3:7
0.7%
0.7%
Programmable voltage step size
(with a 0.8 V reference)
16.7
mV
Output voltage transition rate
(with 0.8 V reference)
From VOUT = 0.8 V to 1.87 V and VOUT = 1.87 V to
0.8 V
100(1)
mV / 20 µs
(1) 100 mV / 20 µs reached with 50 mV / 10 µs steps
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MAX UNIT
7.19 LDO1 AND LDO2
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
GENERAL
LDO1 AND LDO2 CHARACTERISTICS
VOUT(LDO1) = 1.05 V at 320 mA and VOUT(LDO2) = 1.05
V at 160 mA
1.4
1.7
2.1
3.6
3.6
VOUT(LDO1) = 1.2 V / 1.5 V at 100 mA and VOUT(LDO2) =
1.2 V / 1.1 V / 1 V
VOUT(LDO1) = 1.5 V and VOUT (LDO1, LDO2) = 1.8 V at
200 mA
VIN
Input voltage (VCC6)
V
3.6
VOUT(LDO1) = 1.8 V and VOUT(LDO2) = 1.8 V
VOUT(LDO1) = 2.7 V
2.7
3.2
3.5
3.6
3.6
3.6
VOUT (LDO1) = VOUT(LDO2) = 3.3 V
LDO1
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0
mA,
1
3.3
3%
V
VOUT
DC output voltage
Step size
50
mV
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0
mA,
DC output voltage accuracy
Rated output current
–2.5%
On mode
320
1
IOUTmax
mA
Low-power mode
Load current limitation (short-
circuit protection)
On mode, VOUT = VOUTmin – 100 mV
330
600
1000
350
mA
mV
ON mode, VDO = VIN – VOUT
,
VDO
Dropout voltage
VIN = 1.4 V, IOUT = IOUTmax
DC load regulation
DC line regulation
On mode, IOUT = IOUTmax
17
1
mV
mV
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
ON mode, VIN = 1.5 V, VOUT = 1.05 V
Transient load regulation
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs
and IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
20
5
mV
On mode, VIN = 2.7 + 0.5 V to 2.7 in 30 µs,
and VIN = 2.7 to 2.7 + 0.5 V in 30 µs, IOUT = IOUTmax
Transient line regulation
Turn-on time
mV
µs
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
IOUT = 0, at VOUT = 0.1 V up to VOUTmax
50
75
100
420
200
300
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0
mA,
Turn-on inrush current
300
600
mA
f = 217 Hz
f = 20 kHz
70
40
VIN = VINDC + 100 mVpp tone,
VINDC+= 1.8 V, IOUT = IOUTmax / 2
Ripple rejection
dB
LDO1 internal resistance
LDO off
600
63
Ω
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode (max 85°C)
75
2000
20
Ground current
µA
22
50
2.7
LDO2
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0
mA,
1
3.3
3%
V
VOUT
DC output voltage
Step size
mV
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0
mA,
DC output voltage accuracy
Rated output current
–2.5%
On mode
320
1
IOUTmax
mA
mA
Low-power mode
Load current limitation (short-
circuit protection)
On mode, VOUT = VOUTmin – 100 mV
330
600
1000
20
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TPS659119-Q1
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
LDO1 AND LDO2 (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
ON mode, VDO = VIN – VOUT
VIN = 1.4 V, IOUT = IOUTmax
,
VDO
Dropout voltage
350
mV
DC load regulation
DC line regulation
On mode, IOUT = IOUTmax
17
1
mV
mV
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
ON mode, VIN = 1.5 V, VOUT = 1.05 V
Transient load regulation
Transient line regulation
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs
and IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
20
5
mV
mV
On mode, VIN = 2.7 + 0.5 V to 2.7 in 30 µs,
and VIN = 2.7 to 2.7 + 0.5 V in 30 µs, IOUT = IOUTmax
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
IOUT = 0, at VOUT = 0.1 V up to VOUTmax
40
75
300
300
70
100
420
600
Turn-on time
µs
mA
dB
Ω
200
Turn-on inrush current
Ripple rejection
f = 217 Hz
f = 20 kHz
VIN = VINDC + 100 mVpp tone,
VINDC+= 1.8 V, IOUT = IOUTmax / 2
40
LDO2 internal resistance
LDO off
600
63
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode (max 85°C)
75
2000
20
Ground current
µA
22
2.7
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7.20 LDO3 and LDO4
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL LDO3 AND LDO4 CHARACTERISTICS
VOUT (LDO3) = 1.8 V and VOUT (LDO4) = 1.8 V / 1.1 V / 1
V
2.7
5.5
VIN
Input voltage (VCC5)
V
VOUT (LDO3) = 2.6 V and VOUT (LDO4) = 2.5 V
VOUT (LDO3) = 2.8 V
3
5.5
3.2
5.5
LDO3
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0
mA,
1
3.3
3%
V
VOUT
DC output voltage
Step size
100
mV
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0
mA,
DC output voltage accuracy
Rated output current
–2.5%
On mode
200
1
IOUTmax
mA
Low-power mode
Load current limitation (short-
circuit protection)
On mode, VOUT = VOUTmin – 100 mV
330
550
150
650
270
mA
mV
On mode, VOUTtyp = 3.3 V, VDO = VIN – VOUT
VIN = 3.3 V, IOUT = IOUTmax
,
VDO
Dropout voltage
DC load regulation
DC line regulation
On mode, IOUT = IOUTmax
28
1
mV
mV
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
On mode, VIN = 2.7 V, VOUTtyp = 1.8 V
Transient load regulation
Transient line regulation
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs
and IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
15
mV
mV
On mode, VOUTtyp = 1.8 V, IOUT = IOUTmax,VIN = VINmin
0.5 V to VINmin in 30 µs
+
0.5
and VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT = IOUTmax
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
25
50
180
200
70
70
230
450
Turn-on time
µs
mA
dB
kΩ
IOUT = 0, at VOUT = 0.1 V up to VOUTmax
120
Turn-on inrush current
Ripple rejection
f = 217 Hz
f = 50 kHz
VIN = VINDC + 100 mVpp tone,
VINDC+ = 3.8 V, IOUT = IOUTmax / 2
40
LDO3 internal resistance
LDO off
500
65
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode
76
2000
22
Ground current
µA
14
1
LDO4
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
Step size
1
3.3
3%
V
VOUT
DC output voltage
100
mV
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0
mA,
DC output voltage accuracy
Rated output current
–2.5%
On mode
50
1
IOUTmax
mA
Low-power mode
Load current limitation (short-
circuit protection)
On mode, VOUT = VOUTmin – 100 mV
200
400
100
500
160
mA
mV
On mode, VOUTtyp = 3.3 V, VDO = VIN – VOUT
VIN = 3.3 V, IOUT = IOUTmax
VDO
Dropout voltage
DC load regulation
DC line regulation
On mode, IOUT = IOUTmax
6
1
mV
mV
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
22
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
LDO3 and LDO4 (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
On mode, VIN = 2.7 V, VOUTtyp = 1.8 V
Transient load regulation
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs
and IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
6
mV
On mode, VIN = VINmin + 0.5 V to VINmin in 30 µs
Transient line regulation
Turn-on time
0.2
mV
and VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT = IOUTmax
/ 2
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
IOUT = 0, at VOUT = 0.1 V up to VOUTmax
25
50
180
70
70
µs
120
230
f = 217 Hz
f = 50 kHz
VIN = VINDC + 100 mVpp tone,
VINDC+= 3.8 V, IOUT = IOUTmax / 2
Ripple rejection
dB
40
LDO4 internal resistance
LDO Off
500
55
kΩ
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode
65
900
µA
17
Ground current
14
1
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7.21 LDO5
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL CHARACTERISTICS
VOUT (LDO5) ≤ 1.2 V
1.7
1.7
1.9
VOUT (LDO5) > 1.2 V (See Dropout Voltage parameter for
additional constraints)
5.5
V
VIN
Input voltage (VCC4)
VOUT (LDO5) = 2.5 V
3.2
3.2
5.5
5.5
VOUT (LDO5) = 2.8 V at Iload = 200 mA
LDO5
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
1
3.3
3%
V
VOUT
DC output voltage
Step size
100
550
mV
DC output voltage accuracy
Rated output current
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
–2.5%
300
1
On mode
IOUTmax
mA
mA
Low-power mode
Load current limitation (short-
circuit protection)
On mode, VOUT = VOUTmin – 100 mV
330
650
500
400
300
700
500
300
VIN = 2.7 V,
IOUT = IOUTmax
VIN = 2.7 V,
IOUT = 250 mA
VIN = 2.7 V,
IOUT = 200 mA
On mode, VDO = VIN – VOUT
VIN = 1.7 V,
VDO
Dropout voltage
mV
IOUT = 180 mA
VIN = 1.7 V,
IOUT = 150 mA
VIN = 1.7 V,
IOUT = 100 mA
DC load regulation
DC line regulation
On mode, IOUT = IOUTmax
16
1
mV
mV
On mode, VIN = VINmin to VINmax at IOUTmax
On mode, VIN = 3.2 V, VOUTtyp = 2.8 V
Transient load regulation
Transient line regulation
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs
and IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
16
4
mV
mV
On mode, VIN = VINmin + 0.5 V to VINmin in 30 µs
and VIN = VINmin to VINmin + 0.5 V in 30 µs, IOUT = IOUTmax
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
IOUT = 0, at VOUT = 0.1 V up to VOUTmax
20
50
180
200
70
70
250
450
Turn-on time
µs
mA
dB
Ω
120
Turn-on inrush current
Ripple rejection
f = 217 Hz
f = 20 kHz
VIN = VINDC + 100 mVpp tone,
VINDC+ = 3.8 V, IOUT = IOUTmax / 2
40
LDO5 internal resistance
LDO Off
60
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode
65
76
2000
22
Ground current
µA
14
1
24
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
7.22 LDO6 and LDO7
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
GENERAL LDO6 AND LDO7 CHARACTERISTICS
VOUT (LDO6/7) ≤ 1.2 V
1.7
1.7
1.9
5.5
5.5
VOUT (LDO6/7) > 1.2 V (See Dropout Voltage parameter for
additional constraints)
VOUT(LDO7) = 2.8 V
3.2
3.6
3.2
3.6
3.6
Input voltage (VCC3 for LDO6
& LDO7)
VIN
V
VOUT(LDO7) = 3.3 V
5.5
VOUT(LDO7) = 2.8 V at 250 mA
VOUT(LDO7) = 3 V
5.5
5.5
5.5
VOUT(LDO7) = 3.3 V at 250 mA
LDO6
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
1
3.3
3%
V
VOUT
DC output voltage
Step size
100
550
mV
DC output voltage accuracy
Rated output current
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
–2.5%
300
1
On mode
IOUTmax
mA
mA
Low-power mode
Load current limitation (short-
circuit protection)
On mode, VOUT = VOUTmin – 100 mV
330
650
500
400
300
700
500
300
VIN = 2.7 V,
IOUT = IOUTmax
VIN = 2.7 V,
IOUT = 250 mA
VIN = 2.7 V,
IOUT = 200 mA
VDO
Dropout voltage
On mode, VDO = VIN – VOUT
,
mV
VIN = 1.7 V,
IOUT = 180 mA
VIN = 1.7 V,
IOUT = 150 mA
VIN = 1.7 V,
IOUT = 100 mA
DC load regulation
DC line regulation
On mode, IOUT = IOUTmin
16
1
mV
mV
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
On mode, VIN = 3.2 V, VOUTtyp = 2.8 V
Transient load regulation
Transient line regulation
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs
and IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
20
5
mV
mV
On mode, VIN = 2.7 V + 0.5 V to 2.7 V in 30 µs
and VIN = 2.7 V to 2.7 V + 0.5 V in 30 µs, IOUT = IOUTmax
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
IOUT = 0, at VOUT = 0.1 V up to VOUTmax
20
50
180
200
70
70
250
450
Turn-on time
µs
mA
dB
Ω
120
Turn-on inrush current
Ripple rejection
f = 217 Hz
f = 20 kHz
VIN = VINDC + 100 mVpp tone,
VINDC+ = 3.8 V, IOUT = IOUTmax / 2
40
LDO6 internal resistance
LDO off
60
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode
65
76
2000
22
Ground current
µA
14
1
LDO7
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
Step size
1
3.3
3%
V
VOUT
DC output voltage
100
mV
DC output voltage accuracy
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
–2.5%
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LDO6 and LDO7 (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
300
1
TYP
MAX UNIT
On mode
IOUTmax
Rated output current
mA
Low-power mode
Load current limitation (short-
circuit protection)
On mode, VOUT = VOUTmin – 100 mV
330
550
650
500
400
300
700
500
300
mA
VIN = 2.7 V,
IOUT = IOUTmax
VIN = 2.7 V,
IOUT = 250 mA
VIN = 2.7 V,
IOUT = 200 mA
VDO
Dropout voltage
On mode, VDO = VIN – VOUT,
mV
VIN = 1.7 V,
IOUT = 180 mA
VIN = 1.7 V,
IOUT = 150 mA
VIN = 1.7 V,
IOUT = 100 mA
DC load regulation
DC line regulation
On mode, IOUT = IOUTmax
24
1
mV
mV
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
On mode, VIN = 3.6 V, VOUTtyp = 3.3 V
Transient load regulation
Transient line regulation
IOUT = 0.1 × IOUTmax to 0.9 × IOUTmax in 5 µs
and IOUT = 0.9 × IOUTmax to 0.1 × IOUTmax in 5 µs
16
5
mV
mV
On mode, IOUT = IOUTmax / 2, VIN = 2.7 + 0.5 V to 2.7 in 30
µs
and VIN = 2.7 V + 0.5 V in 30 µs, IOUT = IOUTmax / 2
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
IOUT = 0, at VOUT = 0.1 V up to VOUTmax
20
50
180
200
70
70
250
450
Turn-on time
µs
mA
dB
Ω
120
Turn-on inrush current
Ripple rejection
f = 217 Hz
f = 20 kHz
VIN = VINDC + 100 mVpp tone,
VINDC+ = 3.8 V, IOUT = IOUTmax / 2
40
LDO7 internal resistance
LDO off
60
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode
65
76
2000
22
Ground current
µA
14
1
26
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
7.23 LDO8
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOUT(VLDO8) ≤ 1.2 V
1.7
1.9
VIN
Input voltage (VCC8)
V
VOUT(VLDO8) > 1.2 V (See Dropout Voltage parameter for
additional constraints)
1.7
1
5.5
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
3.3
3%
V
VOUT
DC output voltage
Step size
100
550
mV
DC output voltage accuracy
Rated output current
ON and low-power mode, VOUT < VIN – VDO , IOUT = 0 mA
–2.5%
300
1
On mode
IOUTmax
mA
mA
Low-power mode
Load current limitation (short-
circuit protection)
On mode, VOUT = VOUTmin – 100 mV
330
650
100
25
VIN = 3.3 V,
IOUT = 70 mA
VIN = 3.3 V,
IOUT = 10 mA
VIN = 2.7 V,
IOUT = IOUTmax
500
400
300
700
500
300
VIN = 2.7 V,
IOUT = 250 mA
On mode, VDO = VIN – VOUT
VIN = 2.7 V,
VDO
Dropout voltage
mV
IOUT = 200 mA
VIN = 1.7 V,
IOUT = 180 mA
VIN = 1.7 V,
IOUT = 150 mA
VIN = 1.7 V,
IOUT = 100 mA
DC load regulation
DC line regulation
On mode, IOUT = IOUTmax
26
1
mV
mV
On mode, VIN = VINmin to VINmax at IOUT = IOUTmax
On mode, VIN = 1.7 V, VOUTtyp = 1.2 V
IOUT = 10 mA to 90 mA in 5 µs and IOUT = 90 mA to 10
mA in 5 µs
Transient load regulation
Transient line regulation
7
5
mV
mV
On mode, IOUT = 100 mA, VIN = 2.7 V + 0.2 V to 2.7 V in
30 µs
and VIN = 2.7 V to 2.7 V + 0.2 V in 30 µs, IOUT = 100 mA
IOUT = 0, at VOUT = 0.1 V up to VOUTmin
IOUT = 0, at VOUT = 0.1 V up to VOUTmax
20
50
180
200
70
70
250
450
Turn-on time
µs
mA
dB
Ω
120
Turn-on inrush current
Ripple rejection
f = 217 Hz
f = 20 kHz
VIN = VINDC + 100 mVpp tone,
VINDC+ = 3.8 V, IOUT = IOUTmax / 2
40
LDO8 internal resistance
LDO off
60
On mode, IOUT = 0
On mode, IOUT = IOUTmax
Low-power mode
Off mode
65
76
2000
22
Ground current
µA
14
1
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www.ti.com.cn
7.24 Timing Requirements for Boot Sequence Example
See 图 1.
PARAMETER
MIN
NOM
66 × tCK32k = 2060
64 × tCK32k = 2000
64 × tCK32k = 2000
64 × tCK32k = 2000
64 × tCK32k = 2000
64 × tCK32k = 2000
MAX
UNIT
µs
tdsON1
tdsON2
tdsON3
tdsON4
tdsON5
tdsON6
PWRHOLD rising edge to VIO, LDO5 enable delay
VIO to VDD2 enable delay
µs
VDD2 to VDD1 enable delay
µs
VDD1 to LDO4 enable delay
µs
LDO4 to LDO3, LDO8 enable delay
LDO3 to LDO6 enable delay
µs
µs
9 × 64 × tCK32k
=
tdsON7
LDO6 to CLK32KOUT rising-edge delay
µs
18000
64 × tCK32k = 2000
32
tdsON8
tdsONT
CLK32KOUT to NRESPWON, NRESPWON2 rising-edge delay
Total switch-on delay
µs
ms
PWRHOLD falling-edge to NRESPWON, NRESPWON2 falling-
edge delay
tdsOFF1
2 × tCK32k = 62.5
µs
tdsOFF1B
tdsOFF2
NRESPWON falling-edge to CLK32KOUT low delay
3 × tCK32k = 92
5 × tCK32k = 154
µs
µs
PWRHOLD falling-edge to supplies and reference disable delay
7.25 Power Control Timing Requirements
See 图 2.
PARAMETER
MIN
NOM
100
MAX UNIT
tdbPWRONF
tdbPWRONR
PWRON falling-edge debouncing delay
PWRON rising-edge debouncing delay
µs
µs
µs
3 × tCK32k = 94
2 × tCK32k = 63
tdbPWRHOLD PWRON rising-edge debouncing delay
INT1 (internal) power-on pulse duration after PWRON low-level
(debounced) event
tdOINT1
1
s
ms
s
delay to set high PWRHOLD signal or DEV_ON control bit after
NRESPWON released to keep on the supplies
tdOINT1 – tDSONT
=
tdONPWHOLD
tdPWRONLP
tdPWRONLPTO
970(1)
PWRON falling-edge to
PWRON long-press delay
4
PWRON_LP_IT
PWROW long-press interrupt
PWRON_LP_IT to
1
s
(PWRON_LP_IT) to supplies switch-off
NRESPWRON falling-edge
(1) TdSONT = 30 ms, as in example boot sequence.
28
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
7.26 Device SLEEP State Control Timing Requirements
See 图 4.
PARAMETER
MIN
NOM
MAX UNIT
SLEEP falling-edge to supply n low-power mode (SLEEP
resynchronization delay)
2 × tCK32k
=
3 × tCK32k
=
tACT2SLP
µs
µs
µs
µs
µs
62
94
tACT2SLP + 3 ×
tCK32k
tACT2SLP
SLEEP falling-edge to CLK32KOUT low
156
188
8 × tCK32k
=
9 × tCK32k
=
tSLP2ACT
SLEEP rising edge to supply in high-power mode
SLEEP rising edge to CLK32KOUT running
250
281
tSLP2ACT + 3 ×
tCK32k
tSLP2ACTCK32K
tdSLPON1
344
281
375
312
SLEEP rising edge to time step 1 of the turn-on sequence
from SLEEP state
tSLP2ACT + 1 ×
tCK32k
TSLOT_LENGTH[1:0] = 00
0
200
TSLOT_LENGTH[1:0] = 01
TSLOT_LENGTH[1:0] = 10
TSLOT_LENGTH[1:0] = 11
turn-on sequence step
duration, from SLEEP state
tdSLPONST
µs
µs
500
2000
VDD1, VDD2, or VIO turn-on delay from turn-on sequence
time step
tdSLPONDCDC
2 × tCK32k = 62
7.27 Supplies State Control Through EN1 and EN2 Timing Characteristics
See 图 5 and 图 6
PARAMETER
MIN
NOM
MAX UNIT
NRESPWRON to to supply state change delay, EN1 or EN2
driven
tdEN
0
ms
tdOEN
EN1 or EN2 edge to supply state change delay
1 × tCK32k = 31
3 × tCK32k = 63
µs
µs
tdVDDEN
EN1 or EN2 edge to VDD1 or VDD2 DCDC turn on delay
7.28 VDD1 Supply Voltage Control Through EN1 Timing Requirements
See 图 7
PARAMETER
MIN
NOM
2 × tCK32k = 62
32
MAX UNIT
tdDVSEN
EN1 (or EN2) edge to VDD1 (or VDD2) voltage change delay
µs
TSTEP[2:0] = 001
tdDVSENL
VDD1 (or VDD2) voltage settling delay
TSTEP[2:0] = 011 (default)
TSTEP[2:0] = 111
0.4 / 7.5 = 53
160
µs
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The TPS659119-Q1 device supports one fixed boot sequence and one EEPROM-programmable boot sequence.
The Timing Requirements for Boot Sequence Example section lists and 图 1 shows an example boot sequence.
See the Boot Configuration and Switch-On and Switch-Off Sequences section for additional information on boot-
mode selection.
tpd2
PWRHOLD
tdsON1
VIO
LDO5
VDD2
tdsON2
tdsON3
VDD1
tdsON4
LDO4
tdsON5
LDO3
LDO8
tdsON6
LDO6
tdsON15
i
CLK32KOUT
NRESPWRON
NRESPWRON2
tpd1
tdsON16
tond: Switch-on sequence
Switch-off sequence
SWCS049-004
图 1. Boot Sequence Example With 2-ms Time Slot and Simultaneous Switch-Off of Resources
图 2 shows the device-state control through the PWRON signal (see the Power Control Timing Requirements
section).
30
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
PWRON
VIO
CLK32KOUT
NRESPWRON
1.8 V
Interrupt acknowledge
PWRON_IT=1
Interrupt acknowledge
PWRON_IT=1
INT1
Internal pulse t
dOINT1
PWRHOLD
tdbPWRHOLDF
Switch-off
sequence
tdbPWRONF
tdONPWHOLD
tdSONT
Switch On sequence
tdbPWRONF
SWCS049-005
NOTE: DEV_ON or AUTODEV_ON control bits can be used instead of PWRHOLD signal to maintain supplies on after
switch-on sequence.
NOTE: Internal POWER ON enable condition pulse TdOINT1 keeps device active until PWRHOLD acknowledge.
图 2. Device State Control Through PWRON Signal
PWRON
VIO
NRESPWRON
PWRON_IT=1
PWRON_LP_IT=1
INT1
PWRON_IT=1
PWRHOLD
Switch-off
sequence
tdPWRONLP
tdPWRONLPTO
tdbPWRONF
SWCS049-006
图 3. PWRON Long-Press Turn-Off
The Power Control Timing Requirements Section Lists the Power Control Timing Characteristics
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31
TPS659119-Q1
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
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tACT2SLP
tSLP2ACT
SLEEP
1.8 V
Low Power mode
1.8 V
PWM mode
1.8 V
PWM mode
VIO/VFBIO
SWIO
LDO5
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
1.8 V
Low-power mode
3.3 V
Pulse skip mode
3.3 V
Pulse skip mode
3.3 V
Low-power mode
VDD2/VFB2
SW2
tdONDCDCSLP
1.2 V
PWM mode
1.2 V
PWM mode
Off
VDD1/VFB1
SW1
Off
Off
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
LDO4
LDO3
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
1.8 V
ACTIVE mode
LDO8
LDO6
3.3 V
ACTIVE mode
3.3 V
ACTIVE mode
3.3V
Low-power mode
tSLP2ACTCK32K
CLK32KOUT
tACT2SLPCK32K
t dSLPONST
tdSLPONST
0, VDD1_SETOFF 1, LDO3_SETOFF = 1,
tdSLPON1
SWCS049-007
NOTE: Registers programming: VIO_PSKIP
=
0, VDD1_PSKIP
=
=
LDO4_SETOFF = 1, LDO8_KEEPON = 1.
图 4. Device SLEEP State Control
See the Device SLEEP State Control Timing Requirements Section
图 5 and 图 6 show the state control of the power supplies through the EN1 and EN2 signals (see the Supplies
State Control Through EN1 and EN2 Timing Characteristics section).
Switch-on sequence
Switch-off sequence
Device on
NRESPWRON
t
dEN
EN1
t
dVEN
t
dEN
LDO1
EN2
t
dSOFF2
1.2 V
t
dEN
t
dEN
Low-power mode
1.8 V
LDO4
SWCS046-009
NOTE: Register setting: LDO1_EN1 = 1, LDO4_EN2 = 1, and LDO4_KEEPON = 1.
图 5. LDO Type Supplies State Control Through EN1 and EN2
32
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
Switch-off sequence
Switch-on sequence
Device on
NRESPWRON
EN2
t
dEN
t
t
dVDDEN
dVDDEN
t
dOEN
VDD2/VFB2
0 V
3.3 V
t
dSOFF2
EN1
t
VDD1/VFB1
t
dEN
1.2 V
PWM mode
dEN
Low-power mode
PFM (pulse skipping) mode
SW1
SWCS049-010
NOTE: Register setting: VDD2_EN2 = 1, VDD1_EN1 = 1, VDD1_KEEPON = 1, VDD1_PSKIP = 0, and SEL[6:0] = hex00 in
VDD2_SR_REG.
图 6. VDD1 and VDD2 Supplies State Control Through EN1 and EN2
EN1
tdDVSEN
tdDVSENL
tdDVSEN
tdDVSENL
1.2 V
0.8 V
VDD1/VFB1
SW1
TSTEP[2:0]=001
TSTEP[2:0]=011
PFM (pulse skipping) mode
PFM (pulse
skipping) mode
PFM (pulse
skipping) mode
SWCS049-011
PWM mode
PWM mode
NOTE: Register setting: VDD1_EN1 = 1, SEL[6:0] = hex13 in VDD1_SR_REG
图 7. VDD1 Supply Voltage Control Through EN1
See the VDD1 Supply Voltage Control Through EN1 Timing Requirements Section
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TPS659119-Q1
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7.29 Typical Characteristics
7.29.1 VIO SMPS Curves
100
90
80
70
60
50
100
90
80
70
60
50
40
30
20
10
0
40
30
20
10
0
VIO, PFM
VIO, PWM
Vout = 2.5 V
Vout = 2.5 V
Vout = 1.8 V
Vout = 1.5 V
Vout = 1.8 V
Vout = 1.5 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
C005
C006
Load Current (A)
Load Current (A)
图 8. VIO Efficiency vs Load Current,
图 9. VIO Efficiency vs Load Current,
25°C VIN = 4 V, PFM
25°C, VOUT = 2.5 V, VIN = 4 V, PWM
7.29.2 VDD1 SMPS Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VDD1, PFM
VDD1 PWM
Vout = 2.5 V
Vout = 1.5 V
Vout = 1.2 V
Vout = 2.5 V
Vout = 1.5 V
Vout = 1.2 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
C001
C002
Load Current (A)
Load Current (A)
图 10. VDD1 Efficiency vs Load Current,
图 11. VDD1 Efficiency vs Load Current,
25°C, VIN = 4 V, PFM
25°C, VIN = 4 V, PWM
34
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
7.29.3 VDD2 SMPS Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VDD2, PFM
VDD2 PWM
Vout = 2.5 V
Vout = 1.5 V
Vout = 1.2 V
Vout = 2.5 V
Vout = 1.5 V
Vout = 1.2 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
C003
C004
Load Current (A)
Load Current (A)
图 12. VDD2 Efficiency vs Load Current,
图 13. VDD2 Efficiency vs Load Current,
25°C, VIN = 4 V, PFM
25°C, VIN = 4 V, PWM
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8 Detailed Description
8.1 Overview
The TPS659119-Q1 device is an integrated power-management integrated-circuit (PMIC) available in an 80-pin,
0,5-mm pitch HTQFP package with thermal pad. This device is designed for automotive applications. The device
provides three step-down converters and an interface to control an external converter. The device also provides
eight LDOs, nine configurable GPIOs, two LED pulse generators, one PWM generator, and programmability for
supporting different processors and applications.
The three step-down converters in this device are high-frequency switch-mode converters with integrated FETs.
The converters are capable of synchronizing to an external clock input and support switching frequency between
2.7 MHz and 3.3 MHz. Two of the step-down converters support dynamic voltage scaling by a dedicated I2C
interface for optimum power savings. The third converter can provide power for system I/Os, memory modules,
or both which provides four programmable output-voltage settings.
The device includes eight general-purpose LDOs providing a wide range of voltage and current capabilities. Five
of the LDOs support 1 to 3.3 V with 100-mV step and three (LDO1, LDO2, LDO4) of the LDOs support 1 to 3.3 V
with 50-mV step. All LDOs are fully controllable by the I2C interface and are supplied from either a system supply
or a pre-regulated supply.
The power-up and power-down controller is configurable and programmable through EEPROM. The TPS659119-
Q1 devices include a 32-kHz RC oscillator to sequence all resources during power up and power down. In cases
where a fast start up is needed, a 16-MHz crystal oscillator is also included to quickly generate a stable 32-kHz
for the system. The device also includes an RTC module that provides date, time, calendar, and alarm capability.
The RTC module is best used when a 16-MHz crystal or an external and high accuracy 32-kHz clock is present.
The TPS659119-Q1 device also includes nine configurable GPIOs with a multiplexed feature. Four of the GPIOs
can be configured and used as enable signals for external resources, which can be included in the power-up and
power-down sequence. Two of the GPIOs have a 10-mA current-sink capability for driving external LEDs. The
device also includes two on and two off LED-pulse generators and one PWM generator with programmable
frequency and duty cycle.
36
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
8.2 Functional Block Diagram
AGND
VCCS
VCC7
VCC1
VDD1
Sw1
VRTC
(LDO)
VRTC
and POR
GND1
0.6 to 1.5 V,
12.5-mV step,
1.5 A
AGND
VFB1
OSC16MIN
VCC2
VDD2
16M XTAL
Real
time
clock
SW2
OSC16MOUT
OSCEXT32K
GND2
DGND
0.6 to 1.5 V,
12.5-mV step,
1.5 A
CLK32KOUT
VDDIO
VFB2
VDDIO
VDDIO
TPS57114
I2C
SDA_SDI
EN
PH
VSENSE
SCL_SCK
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
EN
EXTCTRL
Bus
control
Selectable
Divider
VOUT
VSENSE
AGNDEX
1 V/V to
3/7 V/V
VDDIO
65 steps
GPIO6
GPIO7
GPIO8
I2C
VDDIO
VDDIO
VCCIO
SWIO
VIO
EN1
EN2
Power
control
state
GNDIO
INT1
SLEEP
1.5, 1.8, 2.5, 3.3 V
PWRON
VFBIO
VDDIO
1.5 A
machine
BOOT1
PWRHOLD
PWRDN
LDO1
320 mA
HDRST
NRESPWRON
NRESPWRON2
LDO1
1 to 3.3 V,
50-mV step
VREF
Analog
references
TESTV
VCC6
LDO2
REFGND
Watchdog
1 to 3.3 V,
50-mV step
LDO3
200 mA
LDO3
1 to 3.3 V,
100-mV step
Test interface
LDO2
320 mA
VCC5
LDO4
LDO7
300 mA
1 to 3.3 V,
100-mV step
LDO7
1 to 3.3 V,
50-mV step
LDO4
50 mA
VCC3
LDO6
LDO5
300 mA
LDO5
VCC4
1 to 3.3 V,
100-mV step
1 to 3.3 V,
100-mV step
LDO6
300 mA
VCC8
LDO8
1 to 3.3 V,
100-mV step
LDO8
300 mA
图 14. Top-Level Diagram
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8.3 Feature Description
8.3.1 Power Reference
The bandgap voltage reference is filtered by using an external capacitor connected across the VREF output and
the analog ground, REFGND (see the Recommended Operating Conditions section). The VREF voltage is
distributed and buffered inside the device.
8.3.2 Power Resources
The power resources provided by the TPS659119-Q1 device include inductor-based switched-mode power
supplies (SMPSs) and linear low-dropout voltage regulators (LDOs). These supply resources provide the
required power to the external processor cores and external components, and to modules embedded in the
TPS659119-Q1 device.
Two of the integrated SMPSs and the external SMPS controller (EXTCTRL) have voltage scaling capability.
These SMPSs provide independent core-voltage domains to the host processor. When changing the output
voltage, VDD1 and VDD2 reach the new value through successive steps of 2.5 to 12.5 mV. The size of the
voltage step is selected by the TSTEP bit. With a 0.8-V reference, EXTCTRL has a target slew rate of 100 mV /
20 μs. Use 公式 1 to calculate new output values which are reached in successive smaller steps.
N × LSB
where
•
•
LSB = 16.7 mV
N = 1 to 4
(1)
A suitable combination of steps is calculated internally based on the current and new target values for the output
voltage.
The VIO SMPS provides a supply voltage for the host processor I/Os.
表 1 lists the power sources provided by the TPS659119-Q1 device.
表 1. Power Sources
RESOURCE
VIO
TYPE
SMPS
SMPS
VOLTAGES
POWER
1500 mA
1500 mA
1.5, 1.8, 2.5, and 3.3 V
VDD1
0.6 to 1.5 V in 12.5-mV steps
Programmable-multiplication factor: x2, x3
0.6 to 1.5 V in 12.5-mV steps
Programmable-multiplication factor: x2, x3
1 to 3.3 V, 0.05-V step
VDD2
SMPS
1500 mA
LDO1
LDO2
LDO3
LDO4
LDO5
LDO6
LDO7
LDO8
LDO
LDO
LDO
LDO
LDO
LDO
LDO
LDO
320 mA
320 mA
200 mA
50 mA
1 to 3.3 V, 0.05-V step
1 to 3.3 V, 0.1-V step
1 to 3.3 V, 0.05-V step
1 to 3.3 V, 0.1-V step
300 mA
300 mA
300 mA
300 mA
1 to 3.3 V, 0.1-V step
1 to 3.3 V, 0.1-V step
1 to 3.3 V, 0.1-V step
8.3.3 PWM and LED Generators
The TPS659119-Q1 device has two LED ON and OFF signal generators, LED1 and LED2. The LED1 and LED2
signals have independently controllable periods from 125 ms to 8 s and an ON time from 62.5 to 500 ms. Within
the period, one or two ON pulses can be generated (control bit LED1(2)_SEQ). The user must take care to
program the period and ON time correctly because no limitation on selected values is imposed. The LED1 and
LED2 signals can be routed to GPIO1 and GPO3 open-drain outputs, respectively. These GPIOs have a current-
sink capability of 10 mA.
38
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The PWM generator frequency and duty cycle are set by the PWM_FREQ and PWM_DUTY_CYCLE bits,
respectively. The PWM generator signal can be connected to the GPIO3 or GPIO8 output. The PWM generator
uses the 3-MHz clock, which is not available in off mode. To enable the PWM in sleep mode, the
I2CHS_KEEPON bit must be set to 1.
8.3.4 Dynamic-Voltage Frequency Scaling and Adaptive-Voltage Scaling Operation
Dynamic-voltage frequency scaling (DVFS) operation A supply voltage value corresponding to a targeted
frequency of the digital core supplied is programmed in VDD1_OP_REG or VDD2_OP_REG
registers. The slew rate of the voltage supply reaching a new VDD1_OP_REG or VDD2_OP_REG
programmed value is limited to 12.5 mV/µs, fixed value.
Adaptative-voltage scaling (AVS) operation A supply voltage value corresponding to a supply voltage
adjustment is programmed in VDD1_SR_REG or VDD2_SR_REG registers. The supply voltage is
then tuned by the digital core supplied, based its performance self-evaluation. The slew rate of
VDD1 or VDD2 voltage supply reaching a new programmed value is programmable though the
VDD1_REG or VDD2_REG register, respectively.
A serial control interface (optional mode for EN1 and EN2 pins) can be dedicated to voltage scaling applications
in order to provide dedicated access to the VDD1_OP_REG, VDD1_SR_REG and VDD2_OP_REG,
VDD2_SR_REG registers.
A general-purpose serial-control interface (CTL-I2C) also gives access to these registers if the SR_CTL_I2C_SEL
control bit is set to 1 in the DEVCTRL_REG register (default inactive).
Both control interfaces are compliant with HS-I2C specification (100 Kbps, 400 Kbps, or 3.4 Mbps).
8.3.5 32-kHz RTC Clock
The TPS659119-Q1 device can provide a 32-kHz clock to the platform through the CLK32KOUT output.
Selection of the default RTC clock source is controlled by the EEPROM bit CK32K_CTRL in the DEVCTRL_REG
register. This clock must be present for any state of the EPC except the NO SUPPLY state. The following lists
the three possible sources for this clock.
Crystal Oscillator To use the crystal oscillator, a 16.384-MHz crystal should be placed between the OSC16MIN
and OSC16MOUT pins. The OSCEXT32K pin should be grounded. The 32-kHz clock is produced
by dividing the crystal oscillator output by 500. A higher-frequency crystal is used to accelerate the
start-up time of the device. 图 15 shows an essential schematic of the oscillator .
External Clock Source An external 32-kHz clock source may be used by grounding the OSC16MIN pin,
floating the OSC16MOUT pin, and applying the clock to the OSCEXT32K pin. When four clock
edges are counted on the OSCEXT32K pin, an internal clock-selection MUX selects the external
clock source rather than the crystal oscillator. A means of switching between the crystal oscillator
and the external clock source is not included in the design. Either one or the other can be used in a
given application, but not both.
Internal RC Oscillator Depending on the state of the CK32K_CTRL bit, an internal 32-kHz RC oscillator can
also be used as the clock source for the RTC if an accurate time-base is not required.
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VCC7
500:1
Divider
32.768 kHz
Clock
OSC16MIN
OSC16MOUT
DGND
16.384 MHz
C
C
OSC,IN
OSC,OUT
图 15. 16-MHz Crystal Oscillator
8.3.6 Real-Time Clock (RTC)
The RTC, which is driven by the 32-kHz clock, provides the alarm and timekeeping functions. The RTC remains
supplied when the device is in the OFF or the BACKUP state.
The main functions of the RTC block are:
•
•
•
Time information (seconds, minutes, and hours) directly in binary-coded decimal (BCD) format
Calendar information (day, month, year, and day of the week) directly in BCD code up to year 2099
Programmable interrupts generation
–
The RTC can generate two interrupts: a timer interrupt RTC_PERIOD_IT periodically (1-s, 1-m, 1-h, and
1-d period) and an alarm interrupt RTC_ALARM_IT at a precise time of the day (alarm function). These
interrupts are enabled using IT_ALARM and IT_TIMER control bits. Periodically, interrupts can be masked
during the SLEEP period to avoid host interruption and are automatically unmasked after SLEEP wakeup
(using the IT_SLEEP_MASK_EN control bit).
•
Oscillator frequency calibration and time correction
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32-kHz clock
input
Frequency
compensation
Week
Days
32-kHz
counter
Control
Days
Months
Years
Seconds
Minutes
Hours
Interrupt
Alarm
INT_ALARM
INT_TIMER
SWCS049-015
图 16. RTC Digital Section Block Diagram
8.3.7 Thermal Monitoring and Shutdown
A thermal-protection module monitors the junction temperature of the device versus two thresholds:
•
•
Hot-die temperature threshold
Thermal-shutdown temperature threshold
When the hot-die temperature threshold is reached, an interrupt is sent to software to close the noncritical
running tasks.
When the thermal-shutdown temperature threshold is reached, the TPS659119-Q1 device is set under reset and
a transition to the OFF state initiates. Then the POWER-ON enable conditions of the device are not considered
until the die temperature has decreased below the hot-die threshold. Hysteresis is applied to the hot-die and
shutdown thresholds when detecting a falling edge of temperature and both detections are debounced to avoid
any parasitic detection.
The TPS659119-Q1 device allows programming of four hot-die temperature thresholds to increase the flexibility
of the system.
By default, the thermal protection is enabled in ACTIVE state, but can be disabled through programming the
THERM_REG register. The thermal protection can be enabled in the SLEEP state programming the
SLEEP_KEEP_RES_ON register. The thermal protection is automatically enabled during an OFF-to-ACTIVE
state transition and is kept enabled in the OFF state after a switch-off sequence caused by a thermal shutdown
event. A transition to the OFF-state sequence caused by thermal shutdown event is highlighted in 表 67 (the
INT_STS_REG status register). Recovery from this OFF state is initiated (switch-on sequence) when the die
temperature falls below the hot-die temperature threshold.
Hot-die and thermal shutdown temperature threshold detection states can be monitored or masked by reading or
programming the THERM_REG register. Programming the INT_MSK_REG register can mask the hot-die
interrupt.
8.3.8 Crystal Oscillator Power-On Reset
The crystal oscillator uses a local independent power-on-reset (POR) circuit. If the crystal oscillator or external
clock input are used, then VCC7 must be higher than the rising threshold of this POR circuit (3.96 V max). If
VCC7 is not higher than the rising POR threshold, a clock is not delivered to the digital core inside the PMIC and
the device does not power up.
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8.4 Device Functional Modes
8.4.1 Embedded Power Controller
The embedded power controller (EPC) manages the state of the device and controls the power-up sequence.
8.4.1.1 State-Machine
The EPC supports the following states:
•
•
•
•
NO SUPPLY: The main battery-supply voltage is not high enough to power the VRTC regulator. A global
reset is asserted in this case. The device is turned off completely.
OFF: The main battery-supply voltage is high enough to start the power-up sequence but device power-on is
not enabled. All power supplies are in the OFF state except VRTC.
ACTIVE: Device POWER-ON enable conditions are met and regulated power supplies are on or can be
enabled with full current-capability.
SLEEP: Device SLEEP-enable conditions are met and some selected regulated power supplies are in low-
power mode.
图 17 shows the transitions for the state-machine.
AUTODEV_ON
DEV_ON
PWRHOLD
HDRST
INT1
Pulse
generator
NRESPWRON
TDOINT1
PWRON
POWER ON
ENABLE
THERM_TS
TD
NO SUPPLY
PWRON_LP_IT
DEV_OFF
DEV_OFF_RST
HDRST
VCC7 < VBNPR
PWRDN_POL
PWRDN
VCC7 > PORXTAL
VCC7 < VBNPR
VCC7 < VBNPR
OFF
SLEEPSIG_POL
SLEEP
INT1
POWER ON
enabled
POWER ON
disabled
SLEEP
ENABLE
DEV_SLP
ACTIVE
POWER ON
disabled
SLEEP
disabled
SLEEP
enabled
SLEEP
SWCS049-024
NOTE: PWRHOLD enables power-on unless the pin is programmed as a GPI pin.
图 17. Embedded Power-Control State-Machine
42
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Device Functional Modes (接下页)
8.4.1.1.1 Device POWER-ON Enable Conditions
The enable conditions of device POWER ON include the following:
•
•
None of the device POWER-ON disable conditions are met.
One of the following is met:
–
–
–
–
PWRON-signal low level
PWRHOLD signal high level
DEV_ON control bit set to 1 (default inactive)
Interrupt flag active (default INT1 low) generates a POWER ON enable condition during a fixed delay
(tDOINT1 pulse duration defined in ). Interrupt sources expected (if enabled), when the device is off:
–
RTC alarm interrupt
The active interrupt flag generates a POWER-ON enable-condition pulse of length tDOINT1 only when the device is
in the OFF state (when the NRESPWRON signal is low). The POWER-ON enable-condition pulse occurs only if
the interrupt status bit is initially low (no previous interrupt pending in the status register). The interrupt status
register must first be cleared to allow device power off during the tDOINT1 pulse duration.
The GPIO2 signal cannot be used to turn on the device, even if the associated interrupt is not masked. The
GPIO0, GPIO1, GPIO3, GPIO4, or GPIO5 signals can be used to turn on the device, if the associated interrupt is
not masked.
注
The watchdog interrupt is not a power-on event, but it wakes up the device from sleep
mode.
8.4.1.1.2 Device POWER ON Disable Conditions
The disable conditions of device POWER ON include one of the following:
•
PWRON signal low level during more than the long-press delay: PWON_LP_DELAY (can be disabled though
register programming). The interrupt corresponding to this condition is PWRON_LP_IT in the INT_STS_REG
register.
•
•
The die temperature reaches the thermal-shutdown threshold (THERM_TS = 1).
DEV_OFF or DEV_OFF_RST control bit is set to 1 (the DEV_OFF value is cleared when the device is in the
OFF state).
注
If the DEV_ON bit is set to 1, after switch-off, the device switches back on. To keep the
device off, DEV_ON must be cleared first.
8.4.1.1.3 Device SLEEP Enable Conditions
The enable conditions of the device SLEEP state include all of the following:
•
•
•
SLEEP-signal low level (default, or high level depending on the programmed polarity)
DEV_SLP control bit is set to 1.
Interrupt flag inactive (default INT1 high): no nonmasked interrupt is pending.
The SLEEP state is controlled by programming DEV_SLP and keeping the SLEEP signal floating. This state is
also controlled through the SLEEP signal by setting the DEV_SLP bit to 1 one time after device turn-on.
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Device Functional Modes (接下页)
8.4.1.1.4 Device Reset Scenarios
The device has three reset scenarios:
Full reset
All digital logic of the device is reset.
Caused by POR (power on reset) when VCC7 < VBNPR
General reset No impact on the RTC, backup registers, or interrupt status.
Caused by one of the follwoing:
•
•
•
PWON_LP_RST bit set high
DEV_OFF_RST bit set high
HDRST input set high
Turnoff
Power reinitialization in off or backup mode.
表 7 lists a mapping of the digital registers to these reset scenarios.
8.4.1.2 Boot Configuration and Switch-On and Switch-Off Sequences
The power sequence is the automated switch-on of the devices resources when an OFF-to-ACTIVE transition
occurs. The power-on sequence has 15 sequential time slots to which resources (DCDCs, LDOs, 32-kHz clock,
GPIO0, GPIO2, GPIO6, GPIO7) are assigned. The selected length of the time slot is either 0.5 ms or 2 ms. If a
resource is not assigned to any time slot, the resource is in OFF mode after the power-on sequence and the
voltage level can be changed through the register SEL bits before enabling the resource.
A power-off disables all power resources at the same time by default. By setting the PWR_OFF_SEQ control bit
to 1, power-off follows the power-up sequence in reverse order (the first resource powered on is the last resource
powered off).
The values of VDD1, VDD2, and EXTCTRL set in the boot sequence can be selected from 16 steps. For the
whole range, 100-mV steps are available: 0.6 V and 0.7 to 1.4 V and 1.5 V. From 0.8 to 1.4 V, additional values
with 50-mV step resolution can be set: 0.85 V and 1.05 V to 1.35 V.
For LDO1, LDO2, and LDO4 all levels from 1 to 3.3 V are selectable in the boot sequence with 50-mV steps. For
other LDOs, the level is selectable with 100-mV steps, from 1 to 3.3 V.
The device supports two boot configurations, which define the power sequence and several device control bits.
The boot configuration is selectable by the device BOOT1 pin.
BOOT1
Boot Configuration
0
1
Fixed boot mode
EEPROM boot mode
The BOOT1 input pad is disabled after the boot mode is read at power up, to save power.
表 2 and 表 3 list the power sequence and general control bits defined in the boot sequence, respectively.
Fixed boot mode is the same in all orderable devices while EEPROM boot mode is different in each. 表 2 lists
the boot configuration for power sequence control bits and 表 3 lists the boot configuration for general control
bits. Refer to 表 4 for EEPROM boot-mode descriptions for specific orderable devices.
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表 2. Boot Configuration: Power-Sequence Control Bits
TPS659119-Q1
REGISTER
BIT
DESCRIPTION
FIXED BOOT
EEPROM BOOT
EXTCTRL ratio selection for boot. Levels available:
0.6, 0.7, 0.8, 0.85, 0.9, 0.95 … 1.35, 1.4, and 1.5 V
VDD1 gain selection, x1 or x2
VDD1_OP_REG/VDD1_SR_REG
1.2 V
x
VDD1_REG
EEPROM
VGAIN_SEL
x1
3
x
x
x
VDD1 time slot selection
DCDCCTRL_REG
VDD1_PSKIP
VDD1 pulse skip mode enable
Enable skip
VDD2 voltage level selection for boot. Levels available:
0.6, 0.7, 0.8, 0.85, 0.9 … 0.95 to 1.35, 1.4, and 1.5 V
VDD2 gain selection, x1 or x3
VDD2_OP_REG/VDD2_SR_REG
1.5 V
x
VDD2_REG
EEPROM
VGAIN_SEL
x1
x
x
x
x
x
x
VDD2 time slot selection
6
DCDCCTRL_REG
VIO_REG
VDD2_PSKIP
SEL[3:2]
VDD2 pulse skip mode enable
Enable skip
1.8 V
VIO voltage selection
EEPROM
VIO time slot selection
4
DCDCCTRL_REG
VIO_PSKIP
VIO pulse skip mode enable
Enable skip
EXTCTRL voltage level selection for boot. Levels
available include:
EXTCTRL_OP_REG/EXTCTRL_SR_REG
Off
x
SEL[6:0] = 3, 11, 19, 23, 27, … 59, 63, 67
Where: Ratio = 48 / (45 + SEL[6:0])
EEPROM
LDO1_REG
EEPROM
EXTCTRL time slot selection
LDO1 voltage selection
LDO1 time slot
Off
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
SEL[7:2]
SEL[7:2]
SEL[6:2]
SEL[7:2]
SEL[6:2]
SEL[6:2]
SEL[6:2]
SEL[6:2]
1.05 V
Off
LDO2_REG
EEPROM
LDO2 voltage selection
LDO2 time slot
1.2 V
7
LDO3_REG
EEPROM
LDO3 voltage selection
LDO3 time slot
LDO3 voltage: 1 V
Off
LDO4_REG
EEPROM
LDO4 voltage selection
LDO4 time slot
1.2 V
2
LDO5_REG
EEPROM
LDO5 voltage selection
LDO5 time slot
LDO5 voltage: 1 V
Off
LDO6_REG
EEPROM
LDO6 voltage selection
LDO6 time slot
LDO6 voltage: 1 V
Off
1.2 V
5
LDO7_REG
EEPROM
LDO7 voltage selection
LDO7 time slot
LDO8_REG
LDO8 voltage selection
1 V
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表 2. Boot Configuration: Power-Sequence Control Bits (接下页)
TPS659119-Q1
EEPROM BOOT
REGISTER
BIT
DESCRIPTION
FIXED BOOT
EEPROM
CLK32KOUT pin
NRESPWRON, NRESPWRON2 pin
GPIO0 pin
LDO8 time slot
7
5
x
x
x
x
x
x
x
CLK32KOUT time slot
NRESPWRON time slot
GPIO0 time slot
10
1
GPIO2 pin
GPIO2 time slot
Off
6
GPIO6 pin
GPIO6 time slot
GPIO7 pin
GPIO7 time slot
5
46
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表 3. Boot Configuration: General Control Bits
TPS659119-Q1
REGISTER
BIT
DESCRIPTION
FIXED BOOT
EEPROM BOOT
0: VRTC LDO is in low-power mode during OFF state.
VRTC_REG
VRTC_OFFMASK
CK32K_CTRL
DEV_ON
0
x
1: VRTC LDO is in full-power mode during OFF state.
0: Clock source is crystal / external clock.
1: Clock source is internal RC oscillator.
0: No impact
DEVCTRL_REG
DEVCTRL_REG
Crystal
0
x
x
1: Maintains device on, in ACTIVE or SLEEP state
Boot sequence time slot duration:
0: 0.5 ms
DEVCTRL2_REG
TSLOTD
2 ms
x
1: 2 ms
0: Turn off device after PWRON long-press not allowed.
1: Turn off device after PWRON long-press.
0: No impact
DEVCTRL2_REG
DEVCTRL2_REG
DEVCTRL2_REG
PWON_LP_OFF
PWON_LP_RST
IT_POL
1
1
0
x
x
x
1: Reset digital core when device is off
0: INT1 signal is active-low.
1: INT1 signal is active-high.
0: Device automatically switches on at NO SUPPLY-to-
OFF or BACKUP-to-OFF transition
INT_MSK_REG
VMBHI_IT_MSK
1
x
1: Start-up reason required before switch-on
0: GPIO5 falling-edge detection interrupt not masked
1: GPIO5 falling-edge detection interrupt masked
0: GPIO5 rising-edge detection interrupt not masked
1: GPIO5 rising-edge detection interrupt masked
0: GPIO4 falling-edge detection interrupt not masked
1: GPIO4 falling-edge detection interrupt masked
0: GPIO4 rising-edge detection interrupt not masked
1: GPIO4 rising-edge detection interrupt masked
0: GPIO0 configured as push-pull output
INT_MSK3_REG
INT_MSK3_REG
INT_MSK3_REG
INT_MSK3_REG
GPIO0_REG
GPIO5_F_IT_MSK
GPIO5_R_IT_MSK
GPIO4_F_IT_MSK
GPIO4_R_IT_MSK
GPIO_ODEN
1
x
x
x
x
x
x
0
1
0
Push-pull
1
1: GPIO0 configured as open-drain output
0: Watchdog disabled
WATCHDOG_REG
WATCHDOG_EN
1: Watchdog enabled, periodic operation with 100 s
0: Enable input buffer for external resistive divider
1: In single-cell system, disable buffer for low lower
EEPROM boot sequence version number
VMBCH_REG
VMBBUF_BYPASS
BOOTSEQVER_SEL
Disable buffer
0x20
x
x
BOOTSEQVER_REG
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表 3. Boot Configuration: General Control Bits (接下页)
TPS659119-Q1
FIXED BOOT EEPROM BOOT
REGISTER
BIT
DESCRIPTION
0: PWRHOLD pin is used as PWRHOLD feature.
1: PWRHOLD pin is GPI. After power on, DEV_ON set
high internally, no processor action needed to maintain
supplies.
EEPROM
EEPROM
AUTODEV_ON
1, PWRHOLD pin is GPI
Active-low
x
x
0: PWRDN signal is active-low.
1: PWRDN signal is active-high.
PWRDN_POL
48
版权 © 2013–2014, Texas Instruments Incorporated
TPS659119-Q1
www.ti.com.cn
BOOTSEQVER:
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 4. EEPROM Configuration
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_REG
= 0x1C
BOOTSEQVER_
REG
= 0x24
= 0x26
= 0x30
= 0x20
= 0x28
= 0x2A
= 0x22
= 0x1A
ORDERABLE DEVICE
NUMBER:
TPS659119AIPFP
RQ1
TPS659119CAIPFP
RQ1
TPS659119BAIPFP TPS659119DAIPFP
TPS659119EAIPFP
RQ1
TPS659119FAIPFP
RQ1
TPS659119HAIPFP
RQ1
TPS659119KBIPFP
RQ1
TPS659119LBIPFP
RQ1
RQ1
RQ1
VDD1_SLOT
Slot 15
Slot 8
Slot 3
Slot 1
Slot 15
Slot 6
OFF
Slot 12
Slot 4
Slot 4
Slot 3
Slot 5
Slot 5
Slot 2
Slot 5
OFF
Slot 11
Slot 12
Slot 7
Slot 10
Slot 5
Slot 4
Slot 6
Slot 4
Slot 7
Slot 6
Slot 8
Slot 3
Slot 9
Slot 7
Slot 12
Slot 9
Slot 11
Slot 14
1.2 V
OFF
Slot 15
Slot 8
Slot 3
Slot 1
Slot 15
Slot 6
OFF
Slot 15
Slot 8
Slot 3
Slot 1
Slot 15
Slot 6
Slot 3
Slot 1
Slot 11
Slot 7
Slot 12
OFF
OFF
Slot 15
Slot 8
Slot 3
Slot 1
Slot 15
Slot 6
Slot 3
Slot 1
Slot 11
Slot 7
Slot 12
OFF
OFF
VDD2_SLOT
Slot 8
Slot 3
Slot 1
OFF
Slot 8
Slot 3
Slot 1
OFF
Slot 8
Slot 3
Slot 1
OFF
VIO_SLOT
EXTCTRL_SLOT
VDIG1_SLOT (LDO1)
VDIG2_SLOT (LDO2)
VDAC_SLOT (LDO3)
VPLL_SLOT (LDO4)
VAUX1_SLOT (LDO5)
VMMC_SLOT (LDO6)
VAUX33_SLOT (LDO7)
VAUX2_SLOT (LDO8)
GPIO0_SLOT
Slot 5
OFF
Slot 6
OFF
Slot 6
OFF
OFF
Slot 1
Slot 11
Slot 7
Slot 12
OFF
OFF
Slot 1
Slot 11
Slot 7
Slot 12
OFF
Slot 1
Slot 11
Slot 7
Slot 12
OFF
Slot 11
Slot 7
Slot 12
OFF
Slot 11
Slot 7
Slot 12
OFF
Slot 13
Slot 6
Slot 14
Slot 1
Slot 4
Slot 10
OFF
Slot 5
OFF
Slot 6
OFF
Slot 5
OFF
Slot 5
OFF
Slot 5
OFF
Slot 5
OFF
Slot 5
OFF
GPIO2_SLOT
GPIO6_SLOT
OFF
OFF
OFF
OFF
Slot 15
Slot 15
Slot 10
Slot 14
1.05 V
1.5 V
OFF
Slot 15
Slot 15
Slot 10
Slot 14
1.05 V
1.5 V
GPIO7_SLOT
OFF
OFF
OFF
OFF
OFF
CLK32KOUT_SLOT
NRESPWRON_SLOT
VDD1_VSEL
Slot 10
Slot 14
1.05 V
1.5 V
1.8 V
Slot 7
Slot 10
1.05 V
1.5 V
Slot 10
Slot 14
1.05 V
1.5 V
1.8 V
Slot 10
Slot 14
1.05 V
1.5 V
1.8 V
Slot 10
Slot 14
1.05 V
1.5 V
Slot 10
Slot 14
1.05 V
1.5 V
VDD2_VSEL
1.2 V
VIO_VSEL
1.8 V
3.3 V
1.8 V
1.8 V
1.8 V
1.8 V
EXTCTRL_VSEL (Ratio) EXTCTRL Divider
Ratio = 2/3
EXTCTRL Divider
Ratio = 12/19
EXTCTRL Divider
Ratio = 2/3
EXTCTRL Divider
Ratio = 1/2
EXTCTRL Divider
Ratio = 12/19
EXTCTRL Divider
Ratio = 12/19
EXTCTRL Divider
Ratio = 12/19
EXTCTRL Divider Ratio
= 12/19
EXTCTRL Divider Ratio
= 12/19
VDIG1_VSEL (LDO1)
VDIG2_VSEL (LDO2)
VDAC_VSEL (LDO3)
VPLL_VSEL (LDO4)
VAUX1_VSEL (LDO5)
VMMC_VSEL (LDO6)
VAUX33_VSEL (LDO7)
VAUX2_VSEL (LDO8)
VDD1_GAINSEL
1.05 V
1.2 V
1 V
1 V
1.8 V
1.8 V
3.3 V
1.8 V
3.3 V
3.3 V
3.3 V
1.8 V
1×
1.05 V
1.2 V
1 V
1.05 V
1.2 V
1 V
1.05 V
1.2 V
1.8 V
1.2 V
1 V
1.05 V
1.2 V
1 V
1.05 V
1.2 V
1.8 V
1.2 V
1 V
1.05 V
1.2 V
1 V
1.2 V
1.2 V
1.8 V
3.2 V
1.8 V
2.8 V
2.8 V
1×
0.8 V
1 V
1.25 V
1 V
0.8 V
1 V
1.2 V
1 V
1.2 V
1 V
1.8 V
2.8 V
1 V
1.8 V
2.8 V
1 V
1.8 V
2.8 V
1 V
1.8 V
2.8 V
1 V
1.8 V
2.8 V
1 V
1.8 V
2.8 V
1 V
1.8 V
2.8 V
1 V
1×
1×
1×
1×
1×
1×
1×
VDD2_GAINSEL
1×
1×
1×
1×
1×
1×
1×
1×
1×
VDD1_PSKIP
VDD1 PFM mode
enabled
VDD1 in PWM mode
only
VDD1 in PWM
mode only
VDD1 PFM mode
enabled
VDD1 PFM mode
enabled
VDD1 PFM mode
enabled
VDD1 PFM mode
enabled
VDD1 PFM mode
enabled
VDD1 PFM mode
enabled
VDD2_PSKIP
VDD2 PFM mode
enabled
VDD2 in PWM mode
only
VDD2 in PWM
mode only
VDD2 PFM mode
enabled
VDD2 PFM mode
enabled
VDD2 PFM mode
enabled
VDD2 PFM mode
enabled
VDD2 PFM mode
enabled
VDD2 PFM mode
enabled
版权 © 2013–2014, Texas Instruments Incorporated
49
TPS659119-Q1
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
表 4. EEPROM Configuration (接下页)
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_
REG
BOOTSEQVER_REG
= 0x1C
BOOTSEQVER_
REG
BOOTSEQVER:
= 0x24
= 0x26
= 0x30
= 0x20
= 0x28
= 0x2A
= 0x22
= 0x1A
ORDERABLE DEVICE
NUMBER:
TPS659119AIPFP
RQ1
TPS659119CAIPFP
RQ1
TPS659119BAIPFP TPS659119DAIPFP
TPS659119EAIPFP
RQ1
TPS659119FAIPFP
RQ1
TPS659119HAIPFP
RQ1
TPS659119KBIPFP
RQ1
TPS659119LBIPFP
RQ1
RQ1
RQ1
VIO_PSKIP
VIO PFM mode
enabled
VIO in PWM mode
only
VIO in PWM mode
only
VIO PFM mode
enabled
VIO PFM mode
enabled
VIO PFM mode
enabled
VIO PFM mode
enabled
VIO PFM mode enabled
VIO PFM mode enabled
TSLOTD
0.5 ms
0.5 ms
2 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
0.5 ms
CLK32K_CTRL
CLK32KOUT
derived from XTAL
oscillator
CLK32KOUT derived
from XTAL oscillator
CLK32KOUT
derived from XTAL
oscillator
CLK32KOUT derived
from XTAL oscillator
CLK32KOUT derived
from XTAL oscillator
CLK32KOUT derived
from XTAL oscillator
CLK32KOUT derived
from XTAL oscillator
CLK32KOUT derived
from XTAL oscillator
CLK32KOUT derived
from XTAL oscillator
ITPOL
INT1 output active-
low
INT1 output active-low INT1 output active-
low
INT1 output active-low INT1 output active-low INT1 output active-low INT1 output active-low INT1 output active-low
INT1 output active-low
PWRDN_POL
PWRDN input
active-low
PWRDN input active-
low
PWRDN input
active-high
PWRDN input active-
low
PWRDN input active-
low
PWRDN input active-
low
PWRDN input active-
low
PWRDN input active-low PWRDN input active-low
WATCHDOG
Watchdog disabled
Digital core reset
Watchdog disabled
Watchdog disabled
Watchdog disabled
Watchdog disabled
Watchdog disabled
Watchdog disabled
Watchdog disabled
Watchdog disabled
PWRON_LP_RST
Digital core reset when Digital core reset
Digital core reset when Digital core reset when Digital core reset when Digital core reset when Digital core reset when
Digital core reset when
device is OFF
when device is OFF device is OFF
when device is OFF device is OFF
device is OFF
device is OFF
device is OFF
device is OFF
GPIO0_ODEN
GPIO0 is push-pull
GPIO0 is push-pull
GPIO0 is push-pull
GPIO0 is push-pull
GPIO0 is push-pull
GPIO0 is push-pull
GPIO0 is push-pull
GPIO0 is push-pull
GPIO0 is push-pull
GPIO5_R_IT_MSK
GPIO5 rising-edge
interrupt enabled
GPIO5 rising-edge
interrupt masked
GPIO5 rising-edge
interrupt masked
GPIO5 rising-edge
interrupt enabled
GPIO5 rising-edge
interrupt enabled
GPIO5 rising-edge
interrupt enabled
GPIO5 rising-edge
interrupt enabled
GPIO5 rising-edge
interrupt enabled
GPIO5 rising-edge
interrupt enabled
GPIO5_F_IT_MSK
GPIO4_R_IT_MSK
GPIO4_F_IT_MSK
VMBHI_IT_MSK
GPIO5 falling-edge
interrupt masked
GPIO5 falling-edge
interrupt masked
GPIO5 falling-edge
interrupt masked
GPIO5 falling-edge
interrupt masked
GPIO5 falling-edge
interrupt masked
GPIO5 falling-edge
interrupt masked
GPIO5 falling-edge
interrupt masked
GPIO5 falling-edge
interrupt masked
GPIO5 falling-edge
interrupt masked
GPIO4 rising-edge
interrupt enabled
GPIO4 rising-edge
interrupt masked
GPIO4 rising-edge
interrupt masked
GPIO4 rising-edge
interrupt enabled
GPIO4 rising-edge
interrupt enabled
GPIO4 rising-edge
interrupt enabled
GPIO4 rising-edge
interrupt enabled
GPIO4 rising-edge
interrupt enabled
GPIO4 rising-edge
interrupt enabled
GPIO4 falling-edge
interrupt masked
GPIO4 falling-edge
interrupt masked
GPIO4 falling-edge
interrupt masked
GPIO4 falling-edge
interrupt masked
GPIO4 falling-edge
interrupt masked
GPIO4 falling-edge
interrupt masked
GPIO4 falling-edge
interrupt masked
GPIO4 falling-edge
interrupt masked
GPIO4 falling-edge
interrupt masked
VCCS > VMBHI is
NOT a power-on
enable condition
VCCS > VMBHI is
NOT a power-on
enable condition
VCCS > VMBHI is
NOT a power-on
enable condition
VCCS > VMBHI is
NOT a power-on
enable condition
VCCS > VMBHI is
NOT a power-on
enable condition
VCCS > VMBHI is
NOT a power-on
enable condition
VCCS > VMBHI is
NOT a power-on
enable condition
VCCS > VMBHI is NOT
a power-on enable
condition
VCCS > VMBHI is NOT
a power-on enable
condition
VMBBUF_BYPASS
AUTO_DEVON
PWRON_LP_OFF
DEV_ON
VCCS buffer
disabled
VCCS buffer disabled
VCCS buffer
disabled
VCCS buffer disabled
VCCS buffer disabled
VCCS buffer disabled
VCCS buffer disabled
VCCS buffer disabled
VCCS buffer disabled
PWRHOLD pin
keeps PMIC on
PWRHOLD pin keeps
PMIC on
PWRHOLD pin
keeps PMIC on
PWRHOLD pin keeps
PMIC on
PWRHOLD pin keeps
PMIC on
PWRHOLD pin keeps
PMIC on
PWRHOLD pin keeps
PMIC on
PWRHOLD pin keeps
PMIC on
PWRHOLD pin keeps
PMIC on
PWRON long-press PWRON long-press
turnoff ENABLED
PWRON long-press PWRON long-press
turnoff DISABLED
PWRON long-press
turnoff ENABLED
PWRON long-press
turnoff ENABLED
PWRON long-press
turnoff ENABLED
PWRON long-press
turnoff ENABLED
PWRON long-press
turnoff ENABLED
turnoff DISABLED
turnoff ENABLED
DEV_ON bit NOT
set by default
DEV_ON bit NOT set
by default
DEV_ON bit NOT
set by default
DEV_ON bit NOT set
by default
DEV_ON bit NOT set
by default
DEV_ON bit NOT set
by default
DEV_ON bit NOT set
by default
DEV_ON bit NOT set by
default
DEV_ON bit NOT set by
default
VRTC_OFFMASK
VRTC in low-power
mode during OFF
state
VRTC in low-power
mode during OFF
state
VRTC in low-power
mode during OFF
state
VRTC in low-power
mode during OFF
state
VRTC in low-power
mode during OFF
state
VRTC in low-power
mode during OFF
state
VRTC in full-power
mode during OFF
state
VRTC in low-power
mode during OFF state
VRTC in full-power mode
during OFF state
50
版权 © 2013–2014, Texas Instruments Incorporated
TPS659119-Q1
www.ti.com.cn
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
8.4.1.3 Control Signals
8.4.1.3.1 SLEEP
When none of the device SLEEP-disable conditions are met, a falling edge (default or rising edge, depending on
the programmed polarity) of this signal causes an ACTIVE-to-SLEEP state transition of the device. A rising edge
(default or falling edge, depending on the programmed polarity) causes a transition back to the ACTIVE state.
This input signal is level-sensitive and no debouncing is applied.
While the device is in the SLEEP state, predefined resources are automatically set in the low-power mode or off.
Resources can be kept in the active mode (full-load capability) by programming the SLEEP_KEEP_LDO_ON and
the SLEEP_KEEP_RES_ON registers. These registers contain 1 bit per power resource. If the bit is set to 1,
then that resource stays in active mode when the device is in the SLEEP state.
The CLK32KOUT pin is also included in the SLEEP_KEEP_RES_ON register and the 32-kHz clock output is
maintained in the SLEEP state if the corresponding mask bit is set.
The status (low or high) of GPO0, GPO6, GPO7, and GPO8 is also controlled by the SLEEP signal, to allow
enabling and disabling of external resources during sleep.
8.4.1.3.2 PWRHOLD
The PWRHOLD pin can be used as a PWRHOLD signal input or as a general purpose input (GPI). The mode is
selected by the AUTODEV_ON bit, which is part of the boot configuration. When AUTODEV_MODE = 0, the
PWRHOLD feature is selected.
Configured as PWRHOLD, when none of the device POWER ON disable conditions are met, a high level of this
signal causes an OFF-to-ACTIVE state transition of the device and a low level causes a transition back to the
OFF state.
This input signal is level-sensitive and no debouncing is applied. The rising edge, falling edge, or both of
PWRHOLD is highlighted through an associated interrupt if interrupt is unmasked.
When AUTODEV_ON = 1, the pin is used as a GPI. As a GPI, this input can generate a maskable interrupt from
a rising or falling edge of the input. When AUTODEV_ON = 1, a rising edge of NRESPWRON also automatically
sets the DEV_ON bit to 1 to maintain supplies after the switch-on sequence, thus removing the need for the
processor to set the PWRHOLD signal or the DEV_ON bit.
8.4.1.3.3 BOOT1
This signal determines with which processor the device is working and, hence, which power-up sequence is
needed. For more details, see . There is no debouncing on this input signal.
8.4.1.3.4 NRESPWRON, NRESPWRON2
The NRESPWRON signal is used as the reset to the processor and is in the VDDIO domain. This signal is held
low until the ACTIVE state is reached. For more details, see .
The NRESPWRON2 signal is a second reset output. This signal follows the state of NRESPWRON but has an
open-drain output with external pullup. The supply for the external pullup must not be activated before the
TPS659119-Q1 device is in control of the output state (that is, not earlier than during first power-up sequence
slot). In off mode, the NRESPWRON2 output has a weak internal pulldown.
8.4.1.3.5 CLK32KOUT
This signal is the output of the 32-K oscillator, which can be enabled during the power-on sequence, depending
on the boot mode. This signal is enabled and disabled by a register bit during the ACTIVE state of the device.
The CLK32KOUT output can also be enabled during the SLEEP state of the device depending on the
programming of the SLEEPMASK register.
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51
TPS659119-Q1
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
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8.4.1.3.6 PWRON
The PWRON input is connected to an external button. If the device is in the OFF or SLEEP state, a debounced
falling edge (PWRON input low for minimum of 100 µs) causes an OFF-to-ACTIVE state or a SLEEP-to-ACTIVE
state transition of the device. If the device is in active mode, then a low level on this signal generates an
interrupt. If the PWRON signal is low for more than the PWON_TO_OFF_DELAY delay and the corresponding
interrupt is not acknowledged by the processor within 1 s, the device enters the OFF state. See 图 2 and 图 3 for
PWRON behavior.
8.4.1.3.7 INT1
The INT1 signal (default active low) warns the host processor of any event that has occurred on the TPS659119-
Q1 device. The host processor can then poll the interrupt from the interrupt status register through I2C to identify
the interrupt source. A low level (default setting) indicates an active interrupt, highlighted in the INT_STS_REG
register. The polarity of INT1 can be set programming the IT_POL control bit. INT1 flag active is a POWER ON
enable condition during a fixed delay, tDOINT1 (only), when the device is in the OFF state (when NRESPWRON is
low).
Any of the interrupt sources can be masked programming the INT_MSK_REG register. When an interrupt is
masked its corresponding interrupt status bit is still updated, but the INT1 flag is not activated. Interrupt source
masking can be used to mask a device switch-on event. Because interrupt flag active is a POWER ON enable
condition, during tDOINT1 delay, any interrupt not masked must be cleared to allow immediate turn off of the
device.
For a description of interrupt sources, see 表 6.
8.4.1.3.8 EN2 and EN1
EN2 and EN1 are the data and clock signals of the serial-control interface dedicated to voltage-scaling
applications.
These signals can also be programmed as enable signals of one or several supplies when the device is on
(NRESPWRON high). A resource assigned to EN2 or EN1 control automatically disables the serial control
interface.
For the EN1_LDO_ASS_REG, EN2_LDO_REG, and SLEEP_KEEP_LDO_ON_REG registers, the EN1 and EN2
signals can be used to control the ACTIVE or SLEEP state of any LDO-type supplies.
For the EN1_SMPS_ASS_REG, EN2_SMPS_ASS_REG, and SLEEP_KEEP_RES_ON registers, the EN1 and
EN2 signals can be used to control the ACTIVE or LOW-POWER state (PFM mode) of SMPS-type supplies.
The EN2 and EN1 signals can set the output voltage of the VDD1 and VDD2 SMPS from a roof to a floor value,
preprogrammed in the VDD1_OP_REG, VDD2_OP_REG and VDD1_SR_REG, VDD2_SR_REG registers.
When a supply is controlled through the EN1 or EN2 signals, the state of the supply is no longer driven by the
device SLEEP state.
8.4.1.3.9 GPIO0–8
GPIO0, GPIO2, and GPIO6–7 can be programmed as part of the power-up sequence and used as enable
signals for external resources.
GPIO0 is a configurable I/O in the VCC7 domain. By default, the output of GPIO0 is push-pull, driving low.
GPIO0 can also be configured as an open-drain output with an external pullup.
GPIO1 through GPIO8 are configurable open-drain digital I/Os in the VRTC domain. GPIO directivity, debouncing
delay, and internal pullup can be programmed. By default, all are inputs with weak internal pulldown because
open-drain output an external pullup is required.
GPIO0–1 and GPIO3–5 can turn on the device if the corresponding interrupt is not masked. When configured as
an input, GPIO2 cannot be used to turn on the device, even if the associated interrupt is not masked. The GPIO
interrupt is level sensitive. When an interrupt is detected, before clearing the interrupt, it should first be disabled
by masking it.
GPIO1 and GPIO3 have a current-sink capability of 10 mA, and can also drive LEDs connected to a 5-V supply.
52
版权 © 2013–2014, Texas Instruments Incorporated
TPS659119-Q1
www.ti.com.cn
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
GPIO2 can be used for synchronizing DCDCs to an external clock. Programming DCDCCKEXT = 1, VDD1,
VDD2, and VIO DC-DC switching can be synchronized using a 3-MHz clock set though the GPIO2 pin. VDD1
and VDD2 are in-phase and VIO is phase shifted by 180 degrees.
Not connecting noisy switching signals to GPIO4 and GPIO5 is recommended.
8.4.1.3.10 HDRST Input
HDRST is a cold reset input for the PMIC. A high level at the input forces the TPS659119-Q1 into off mode,
causing a general reset of the device to the default settings. The default state is defined by the register reset
state and boot configuration. An HDRST high level keeps the device in off mode. When reset is released and
HDRST input goes low, the device automatically transitions to active mode. The device is kept in active mode for
the period tDONIT1, after which another power-on enable reason is required to keep the device on.
The HDRST input is in the VRTC domain and has a weak internal pulldown which is active by default.
8.4.1.3.11 PWRDN
The PWRDN input is a reset input with selectable polarity (PWRDN_POL). A high level with active-low polarity at
the input forces the TPS659119-Q1 device into off mode, causing a power-off reset. Off mode is maintained until
PWRDN is released and a start-up reason is detected such as a PWRON button press or DEV_ON = 1. An
interrupt is generated to indicate the cause for shutdown. The PWRDN input is in the VRTC domain, but can
tolerate a 5-V input.
8.4.1.3.12 Watchdog
The watchdog has two modes of operation.
In periodic operation an interrupt is generated with a regular period defined by the WTCHDG_TIME setting. The
IC initiates WTCHDOG shutdown if the interrupt is not cleared within the period. The watchdog interrupt
WTCHDOG counter is reinitialized when NRESPWRON is low.
In interrupt mode the IC initiates WTCHDOG counter when an interrupt is pending and is cleared when the
interrupt is acknowledged. If the interrupt is not cleared before watchdog expiration within WTCHDG_TIME, the
device enters off mode.
By default, periodic watchdog functionality is enabled with the maximum WTCHDG_TIME period.
Periodic mode:
WTCHDG_CNT
0
1
N
0
1
N
WTCHDG_IT
WTCHDG_OFF
WTCHDG_IT clearing
interrupt clearing
Interrupt mode:
WTCHDG_CNT
WTCHDG_OFF
0
1
i
0
1
N
SWCS049-013
图 18. Watchdog Signals
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53
TPS659119-Q1
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
www.ti.com.cn
8.4.1.3.13 Tracking LDO
LDO4 has an optional mode where the output level follows that of VDD1, from 0.6 to 1.5 V, when VDD1 is active.
When VDD1 is set to off, the LDO4 output is defined by the SEL[7:2] bits in LDO4_REG, and can be set from 0.8
to 1.5 V.
Tracking mode is enabled by setting TRACK = 1 in DCDCCTRL_REG. In initial activation, VDD1 must be
enabled and allowed to settle before enabling tracking mode. After initial activation, tracking mode can remain
enabled while VDD1 is turned off. The value of TRACK is set to the default (0) after any turnoff event.
TRACK bit
Setting
time tON
VDD1 enable
LDO4
LDO4
LDO4
LDO4
LDO4 MODE
No Tracking 1 to 3.3 V
Tracking 0.6 to 1.5 V
Tracking 0.8 V to 1.5 V
Tracking 0.6 V
(LDO4 has same
level as VDD1)
(LDO4 has same
level as VDD1)
SWCS049-019
图 19. Tracking LDO
8.5 Programming
8.5.1 Time-Calendar Registers
All time and calendar information is available in these dedicated registers, called TC registers. Values of the TC
registers are written in BCD format.
1. Year data ranges from 00 to 99
–
–
Leap year = year divisible by four (2000, 2004, 2008, 2012, and so on)
Common year = other years
2. Month data ranges from 1 to 12
3. Day data ranges from the following:
–
–
–
–
1 to 31 when months are 1, 3, 5, 7, 8, 10, 12
1 to 30 when months are 4, 6, 9, 11
1 to 29 when month is 2 and year is a leap year
1 to 28 when month is 2 and year is a common year
4. Week data ranges from 0 to 6
5. Hour data ranges from 00 to 23 in 24-hour mode and ranges from 1 to 12 in AM/PM mode
6. Minute data ranges from 0 to 59
7. Second data ranges from 0 to 59
To modify the current time, software writes the new time into TC registers to fix the time-calendar information.
The processor can write to the TC registers without stopping the RTC. In addition, software can stop the RTC by
clearing the STOP_RTC bit of the control register, checking the RUN bit of the status to ensure that the RTC is
frozen, updating the TC values, and restarting the RTC by setting STOP_RTC bit. An example follows.
54
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Programming (接下页)
表 5 lists the previous register values for the following example:
Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5
表 5. Real-Time Clock Registers Example
REGISTER
SECONDS_REG
MINUTES_REG
HOURS_REG
DAYS_REG
VALUE
0x36
0x54
0x90
0x05
0x09
0x08
MONTHS_REG
YEARS_REG
The user can round to the closest minute by setting the ROUND_30S register bit. TC values are set to the
closest minute value at the next second. The ROUND_30S bit is automatically cleared when the rounding time is
performed. Two examples follow:
•
•
If the current time is 10H59M45S, a round operation changes time to 11H00M00S.
if the current time is 10H59M29S, a round operation changes time to 10H59M00S.
8.5.2 General Registers
Software can access the RTC_STATUS_REG and RTC_CTRL_REG registers at any time. The only exception is
that software cannot access the RTC_CTRL_REG[5] bit which must be changed only when the RTC is stopped.
8.5.3 Compensation Registers
The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers must be updated before each compensation
process. For example, software can load the compensation value into these registers after each hour event
during an available access period.
Hours
3
4
6
Seconds
58 59
0
1
2
58 59
0
1
2
Compensation event
Hours
3
4
59
0
1
Seconds
Compensation event
SWCS046-016
图 20. RTC Compensation Scheduling
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This drift can be balanced to compensate for any inaccuracy of the 32-kHz oscillator. Software must calibrate the
oscillator frequency, calculate the drift compensation versus 1-h time period, and load the compensation registers
with the drift compensation value. If the AUTO_COMP_EN bit in the RTC_CTRL_REG is enabled, the value of
COMP_REG (in twos-complement) is added to the RTC 32-kHz counter at the first second of each hour. When
COMP_REG is added to the RTC 32-kHz counter, the duration of the current second becomes (32768 –
COMP_REG) / 32768 s; so, the RTC can be compensated with a 1 / 32768 s/hour time unit accuracy.
注
The compensation is considered when written into the registers.
8.5.4 Backup Registers
As part of the RTC, the device contains five 8-bit registers that can be used for storage by the application
firmware when the external host is powered down. These registers retain the content as long as the VRTC is
active.
8.5.5 I2C Interface
A general-purpose serial-control interface (CTL-I2C) allows read and write access to the configuration registers of
all resources of the system.
A second serial-control interface (optional mode for EN1 and EN2 pins) can be dedicated to DVFS.
Both control interfaces are compliant with the HS-I2C specification.
These interfaces support the standard slave mode (100 Kbps), fast mode (400 Kbps), and high-speed mode (3.4
Mbps). The general-purpose I2C module using one slave hard-coded address (ID1 = 2Dh). The voltage scaling
dedicated I2C module uses one slave hardcoded address (ID0 = 12h). The master mode is not supported.
8.5.5.1 Addressing
The device supports seven-bit mode addressing.
It does not support the following features:
•
•
10-bit addressing
General call
8.5.5.2 Access Protocols
Access protocols or compatibility, the I2C interfaces in the TPS659119-Q1 device use the same read and write
protocol as other TI power ICs, based on an internal register size of 8 bits. Supported transactions are described
below.
8.5.5.2.1 Single-Byte Access
A write access is initiated by a first byte including the address of the device (7 MSBs) and a write command
(LSB), a second byte provides the address (8 bits) of the internal register, and the third byte represents the data
to be written in the internal register (see 图 21).
A read access is initiated by:
•
•
•
A first byte, including the address of the device (7 MSBs) and a write command (LSB)
A second byte, providing the address (8 bits) of the internal register
A third byte, including again the device address (7 MSBs) and the read command (LSB)
The device replies by sending a fourth byte which represents the content of the internal register (see 图 22).
56
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
DAD: Device address
S
W
R
I
T
E
D
A
D
6
D
D
A
D
4
D
A
D
3
D
A
D
2
D
A
D
1
D
A
D
0
R
A
D
7
R
A
D
6
R
A
D
5
R
A
D
4
R
A
D
3
R
A
D
2
R
A
D
1
R
A
D
0
D
A
T
7
D
A
T
6
D
A
T
5
D
A
T
4
D
A
T
3
D
A
T
2
D
A
T
1
D
A
T
0
S
T
O
P
A
C
K
A
C
K
A
C
K
T
A
R
T
A
D
5
RAD: Register address
DAT: Data
SCL
SDA
Master drives SDA
Slave drives SDA
SWCS049-020
图 21. I2C Write-Access Single Byte
S
T
A
R
T
W
R
I
S
D
D
D
A
D
4
D
A
D
3
D
D
D
A
D
0
R
R
A
D
6
R
A
D
5
R
A
D
4
R
A
D
3
R
A
D
2
R
A
D
1
R
A
D
0
D
A
D
7
D
A
D
6
D
A
D
5
D
A
D
4
D
A
D
3
D
A
D
2
D
A
D
1
D
R
E
A
D
D
A
T
7
D
D
A
T
5
D
A
T
4
D
A
T
3
D
A
T
2
D
A
T
1
D
A
T
0
S
T
A
A
C
K
A
C
K
A
C
K
T
A
R
T
A
D
6
A
D
5
A
D
2
A
D
1
A
D
7
A
D
0
A
T
6
C
O
P
T
E
K
SCL
SDA
SWCS049-021
图 22. I2C Read-Access Single Byte
8.5.5.2.2 Multiple-Byte Access To Several Adjacent Registers
A write access is initiated by:
•
•
A first byte, including the address of the device (7 MSBs) and a write command (LSB)
A second byte, providing the base address (8 bits) of the internal registers
The following N bytes represent the data to be written in the internal register starting at the base address and
incremented by one at each data byte (see 图 23).
A read access is initiated by:
•
•
•
A first byte, including the address of the device (7 MSBs) and a write command (LSB)
A second byte, providing the base address (8 bits) of the internal register
A third byte, including again the device address (7 MSBs) and the read command (LSB)
The device replies by sending a fourth byte, which represents the content of the internal registers, starting at the
base address and next consecutive ones (see 图 24).
S
T
A
R
T
W
R
I
D
A
D
6
D
A
D
5
D
A
D
4
D
A
D
3
D
A
D
2
D
A
D
1
D
A
D
0
R
A
D
7
R
A
D
6
R
A
D
5
R
A
D
4
R
A
D
3
R
A
D
2
R
A
D
1
R
A
D
0
D
A
T
7
D
A
T
6
D
A
D
5
D
A
T
4
D
A
T
3
D
A
T
2
D
A
T
1
D
A
T
0
D
A
T
7
D
A
T
6
D
A
T
5
D
A
T
4
D
A
T
3
D
A
T
2
D
A
T
1
D
A
T
0
S
T
A
C
K
A
C
K
A
C
K
A
C
K
O
P
T
E
SCL
SDA
SWCS049-022
图 23. I2C Write-Access Multiple Bytes
S
T
A
R
T
W
S
D
A
D
6
D
D
A
D
4
D
D
D
A
D
1
D
R
R
A
D
6
R
A
D
5
R
R
A
D
3
R
A
D
2
R
A
D
1
R
A
D
0
D
A
D
7
D
A
D
6
D
A
D
5
D
A
D
4
D
A
D
3
D
A
D
2
D
A
D
1
D
A
D
0
R
E
A
D
D
A
T
7
D
A
T
6
D
A
T
5
D
D
D
A
T
2
D
A
T
1
D
D
D
D
A
T
5
D
D
D
A
T
2
D
A
T
1
D
A
T
0
S
T
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
R
I
T
A
R
T
A
D
5
A
D
3
A
D
2
A
D
0
A
D
7
A
D
4
A
T
4
A
T
3
A
T
0
A
T
7
A
T
6
A
T
4
A
T
3
O
P
T
E
SCL
SDA
SWCS049-023
图 24. I2C Read-Access Multiple Bytes
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8.5.6 Interrupts
表 6. Interrupt Sources
INTERRUPT
DESCRIPTION
RTC alarm event: Occurs at programmed determinate date and time
(running in ACTIVE, OFF, and SLEEP state, default inactive)
RTC_ALARM_IT
RTC_PERIOD_IT
RTC periodic event: Occurs at programmed regular period of time (every second or minute) (running in
ACTIVE, OFF, and SLEEP state, default inactive)
The embedded thermal monitoring module detects a die temperature above the hot-die detection
threshold (running in ACTIVE and SLEEP state).
HOT_DIE_IT
Level sensitive interrupt.
PWRHOLD_R_IT
PWRHOLD_F_IT
PWRHOLD signal rising edge
PWRHOLD signal falling-edge
PWRON is low during more than the long-press delay: PWON_TO_OFF_DELAY (can be disable though
register programming).
PWRON_LP_IT
PWRON_IT
GPIO0_R_IT
GPIO0_F_IT
GPIO1_R_IT
GPIO1_F_IT
GPIO2_R_IT
GPIO2_F_IT
GPIO3_R_IT
GPIO3_F_IT
GPIO4_R_IT
GPIO4_F_IT
GPIO5_R_IT
GPIO5_F_IT
WTCHDG_IT
PWRDN_IT
PWRON is low while the device is on (running in ACTIVE and SLEEP state). Level-sensitive interrupt.
GPIO_CKSYNC rising-edge detection
GPIO_CKSYNC falling-edge detection
GPIO1 rising-edge detection
GPIO1 falling-edge detection
GPIO2 rising-edge detection
GPIO2 falling-edge detection
GPIO3 rising-edge detection
GPIO3 falling-edge detection
GPIO4 rising-edge detection
GPIO4 falling-edge detection
GPIO5 rising-edge detection
GPIO5 falling-edge detection
Watchdog interrupt
PWRDN reset interrupt
8.6 Register Maps
8.6.1 Functional Registers
The possible device reset domains are:
•
Full reset: All digital of device is reset.
Caused by Power On Reset (POR) when VCCS < VBNPR
General reset: No impact on RTC, backup registers or interrupt status.
–
•
–
–
–
Caused by PWON_LP_RST bit set high or
DEV_OFF_RST bit set high or
HDRST input set high
•
Turnoff OFF: Power reinitialization in off or backup mode.
In following register description, reset domain for each register is defined at the register table heading.
注
The DCDCCTRL_REG and DEVCTRL2_REG have bits in two reset domains.
The comment, Default value: See boot configuration, indicates that the default value of the
bit is set in boot configuration and not by register reset value.
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Register Maps (接下页)
8.6.2 TPS659119-Q1_FUNC_REG Register Mapping Summary
表 7. TPS659119-Q1_FUNC_REG Register Summary(1)
REGISTER WIDTH
(BITS)
REGISTER NAME
SECONDS_REG
TYPE
REGISTER RESET
ADDRESS OFFSET
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
0x00
0x00
0x00
0x01
0x01
0x00
0x00
0x00
0x00
0x00
0x01
0x01
0x00
0x00
0x80
0x00
0x00
0x00
0x27
0x00
0x00
0x00
0x00
0x00
0x00
0x1F
0x01
0x01
0x05
0x0D
0x33
0x33
0x0D
0x4B
0x4B
0x00
0x03
0x03
0x15
0x15
0x00
0x09
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x30
0x31
0x32
0x33
0x34
MINUTES_REG
HOURS_REG
DAYS_REG
MONTHS_REG
YEARS_REG
WEEKS_REG
ALARM_SECONDS_REG
ALARM_MINUTES_REG
ALARM_HOURS_REG
ALARM_DAYS_REG
ALARM_MONTHS_REG
ALARM_YEARS_REG
RTC_CTRL_REG
RTC_STATUS_REG
RTC_INTERRUPTS_REG
RTC_COMP_LSB_REG
RTC_COMP_MSB_REG
RTC_RES_PROG_REG
RTC_RESET_STATUS_REG
BCK1_REG
BCK2_REG
BCK3_REG
BCK4_REG
BCK5_REG
PUADEN_REG
REF_REG
VRTC_REG
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
VIO_REG
VDD1_REG
VDD1_OP_REG
VDD1_SR_REG
VDD2_REG
VDD2_OP_REG
VDD2_SR_REG
EXTCTRL_REG
EXTCTRL_OP_REG
EXTCTRL_SR_REG
LDO1_REG
LDO2_REG
LDO5_REG
LDO8_REG
LDO7_REG
(1) Register reset values are for fixed boot mode.
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Register Maps (接下页)
表 7. TPS659119-Q1_FUNC_REG Register Summary(1) (接下页)
REGISTER WIDTH
(BITS)
REGISTER NAME
TYPE
REGISTER RESET
ADDRESS OFFSET
LDO6_REG
LDO4_REG
LD03_REG
THERM_REG
BBCH_REG
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
0x21
0x00
0x35
0x36
0x37
0x38
0x39
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x50
0x51
0x52
0x53
0x54
0x55
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x80
0x00
0x0D
0x00
DCDCCTRL_REG
DEVCTRL_REG
0x39
0x0000 0014
0x0000 0036
0x00
DEVCTRL2_REG
SLEEP_KEEP_LDO_ON_REG
SLEEP_KEEP_RES_ON_REG
SLEEP_SET_LDO_OFF_REG
SLEEP_SET_RES_OFF_REG
EN1_LDO_ASS_REG
EN1_SMPS_ASS_REG
EN2_LDO_ASS_REG
EN2_SMPS_ASS_REG
INT_STS_REG
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x06
INT_MSK_REG
0xFF
0xA8
0xFF
0x5A
0xFF
0x07
INT_STS2_REG
INT_MSK2_REG
INT_STS3_REG
INT_MSK3_REG
GPIO0_REG
GPIO1_REG
0x08
GPIO2_REG
0x08
GPIO3_REG
0x08
GPIO4_REG
0x08
GPIO5_REG
0x08
GPIO6_REG
0x05
GPIO7_REG
0x05
GPIO8_REG
0x08
WATCHDOG_REG
BOOTSEQVER_REG
VMBCH2_REG
0x07
0x1E
0x00
LED_CTRL1_REG
LED_CTRL2_REG1
PWM_CTRL1_REG
PWM_CTRL2_REG
SPARE_REG
0x00
0x00
0x00
0x00
0x00
VERNUM_REG
0x00
60
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8.6.3 TPS659119-Q1_FUNC_REG Register Descriptions
表 8. SECONDS_REG
Address Offset
Physical Address
Description
Type
0x00
Instance
(RESET DOMAIN: FULL RESET)
RTC register for seconds
RW
7
6
5
4
3
2
2
2
1
0
Reserved
SEC1
SEC0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
Reserved bit
RO
R returns
0s
0
6:4
3:0
SEC1
SEC0
Second digit of seconds (range is 0 up to 5)
First digit of seconds (range is 0 up to 9)
RW
RW
0x0
0x0
表 9. MINUTES_REG
Address Offset
Physical Address
Description
Type
0x01
Instance
(RESET DOMAIN: FULL RESET)
RTC register for minutes
RW
7
6
5
4
3
1
0
Reserved
MIN1
MIN0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
Reserved bit
RO
R returns
0s
0
6:4
3:0
MIN1
MIN0
Second digit of minutes (range is 0 up to 5)
First digit of minutes (range is 0 up to 9)
RW
RW
0x0
0x0
表 10. HOURS_REG
Address Offset
Physical Address
Description
Type
0x02
Instance
(RESET DOMAIN: FULL RESET)
RTC register for hours
RW
7
6
5
4
3
1
0
PM_NAM
Reserved
HOUR1
HOUR0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
PM_NAM
Only used in PM_AM mode (otherwise it is set to 0)
RW
0
0 is AM
1 is PM
6
Reserved
Reserved bit
RO
R returns
0s
0
5:4
3:0
HOUR1
HOUR0
Second digit of hours(range is 0 up to 2)
First digit of hours (range is 0 up to 9)
RW
RW
0x0
0x0
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表 11. DAYS_REG
Address Offset
Physical Address
Description
Type
0x03
Instance
(RESET DOMAIN: FULL RESET)
RTC register for days
RW
7
6
5
4
3
2
2
2
1
0
Reserved
DAY1
DAY0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5:4
3:0
DAY1
DAY0
Second digit of days (range is 0 up to 3)
First digit of days (range is 0 up to 9)
RW
RW
0x0
0x1
表 12. MONTHS_REG
Address Offset
Physical Address
Description
Type
0x04
Instance
(RESET DOMAIN: FULL RESET)
RTC register for months
RW
7
6
5
4
3
1
0
Reserved
MONTH1
MONTH0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:5
Reserved
Reserved bit
RO
R returns
0s
0x0
4
MONTH1
MONTH0
Second digit of months (range is 0 up to 1)
First digit of months (range is 0 up to 9)
RW
RW
0
3:0
0x1
表 13. YEARS_REG
Address Offset
Physical Address
Description
Type
0x05
Instance
(RESET DOMAIN: FULL RESET)
RTC register for day of the week
RW
7
6
5
4
3
1
0
YEAR1
YEAR0
BITS
7:4
FIELD NAME
DESCRIPTION
TYPE
RW
RESET
0x0
YEAR1
YEAR0
Second digit of years (range is 0 up to 9)
First digit of years (range is 0 up to 9)
3:0
RW
0x0
62
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 14. WEEKS_REG
Address Offset
Physical Address
Description
Type
0x06
Instance
(RESET DOMAIN: FULL RESET)
RTC register for day of the week
RW
7
6
5
4
3
2
1
0
Reserved
WEEK
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:3
Reserved
Reserved bit
RO
R returns
0s
0x00
2:0
WEEK
First digit of day of the week (range is 0 up to 6)
RW
0
表 15. ALARM_SECONDS_REG
Address Offset
Physical Address
Description
Type
0x08
Instance
(RESET DOMAIN: FULL RESET)
RTC register for programming seconds in the alarm setting
RW
7
6
5
4
3
2
1
0
Reserved
ALARM_SEC1
ALARM_SEC0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7
Reserved bit
RO
0
R returns
0s
6:4
3:0
ALARM_SEC1
ALARM_SEC0
Second digit for programming seconds in the alarm setting (range is 0 up
to 5)
RW
0x0
0x0
First digit for programming seconds in the alarm setting (range is 0 up to
9)
RW
表 16. ALARM_MINUTES_REG
Address Offset
Physical Address
Description
Type
0x09
Instance
(RESET DOMAIN: FULL RESET)
RTC register for programming minutes in the alarm setting
RW
7
6
5
4
3
2
1
0
Reserved
ALARM_MIN1
ALARM_MIN0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7
Reserved bit
RO
0
R returns
0s
6:4
3:0
ALARM_MIN1
ALARM_MIN0
Second digit for programming minutes in the alarm setting (range is 0 up
to 5)
RW
0x0
0x0
First digit for programming minutes in the alarm setting (range is 0 up to
9)
RW
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表 17. ALARM_HOURS_REG
Address Offset
Physical Address
Description
Type
0x0A
Instance
(RESET DOMAIN: FULL RESET)
RTC register for programming hours in the alarm setting
RW
7
6
5
4
3
2
1
0
Reserved
ALARM_HOUR1
ALARM_HOUR0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
ALARM_PM_NAM
Only used in PM_AM mode for programming the AM/PM in the alarm
RW
0
setting (otherwise it is set to 0)
0 is AM
1 is PM
6
Reserved
Reserved bit
RO
R returns
0s
0
5:4
3:0
ALARM_HOUR1
ALARM_HOUR0
Second digit for programming hours in the alarm setting (range is 0 up to
2)
RW
0x0
0x0
First digit for programming hours in the alarm setting (range is 0 up to 9)
RW
表 18. ALARM_DAYS_REG
Address Offset
Physical Address
Description
Type
0x0B
Instance
RTC register for programming days in the alarm setting
RW
(RESET DOMAIN: FULL RESET)
7
6
5
4
3
2
1
0
Reserved
ALARM_DAY1
ALARM_DAY0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
Reserved bit
RO
0x0
R Special
5:4
3:0
ALARM_DAY1
ALARM_DAY0
Second digit for programming days in the alarm setting (range is 0 up to
3)
RW
0x0
0x1
First digit for programming days in the alarm setting (range is 0 up to 9)
RW
64
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 19. ALARM_MONTHS_REG
Address Offset
Physical Address
Description
Type
0x0C
Instance
(RESET DOMAIN: FULL RESET)
RTC register for programming months in the alarm setting
RW
7
6
5
4
3
2
1
0
Reserved
ALARM_MONTH0
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:5
Reserved bit
RO
R returns
0s
0x0
4
ALARM_MONTH1
ALARM_MONTH0
Second digit for programming months in the alarm setting(range is 0 up
to 1)
RW
0
3:0
First digit for programming months in the alarm setting(range is 0 up to 9)
RW
0x1
表 20. ALARM_YEARS_REG
Address Offset
Physical Address
Description
Type
0x0D
Instance
RTC register for programming years in the alarm setting
RW
(RESET DOMAIN: FULL RESET)
7
6
5
4
3
2
1
0
ALARM_YEAR1
ALARM_YEAR0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:4
ALARM_YEAR1
Second digit for programming years in the alarm setting (range is 0 up to
9)
RW
0x0
3:0
ALARM_YEAR0
First digit for programming years in the alarm setting (range is 0 up to 9)
RW
0x0
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表 21. RTC_CTRL_REG
Address Offset
Physical Address
Description
0x10
Instance
(RESET DOMAIN: FULL RESET)
RTC control register:
Note: A dummy read of this register is necessary before each I2C read in order to update the
ROUND_30S bit value.
Type
RW
7
6
5
4
3
2
1
0
RTC_V_OPT
GET_TIME
TEST_MODE
MODE_12_24
AUTO_COMP
ROUND_30S
STOP_RTC
BITS
FIELD NAME
RTC_V_OPT
DESCRIPTION
TYPE
RESET
7
RTC date and time register selection:
RW
0
0: Read access directly to dynamic registers (SECONDS_REG,
MINUTES_REG, HOURS_REG, DAYS_REG, MONTHS_REG,
YEAR_REG, WEEKS_REG)
1: Read access to static shadowed registers: (see GET_TIME bit).
6
GET_TIME
When writing a 1 into this register, the content of the dynamic registers
(SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG,
MONTHS_REG, YEAR_REG and WEEKS_REG) is transferred into
RW
0
static shadowed registers. Each update of the shadowed registers needs
to be done by re-asserting GET_TIME bit to 1 (In effect: reset it to 0 and
then re-write it to 1)
5
4
3
SET_32_COUNTER
TEST_MODE
0: No action
RW
RW
RW
0
0
0
1: set the 32-kHz counter with COMP_REG value.
It must only be used when the RTC is frozen.
0: functional mode
1: test mode (Auto compensation is enable when the 32-kHz counter
reaches at the end of the counter)
MODE_12_24
0: 24-hours mode
1: 12-hours mode (PM-AM mode)
Switching between the two modes at any time without disturbing the RTC
is possible. Read or write are always performed with the current mode.
2
1
AUTO_COMP
ROUND_30S
0: No auto compensation
1: Auto compensation enabled
RW
RW
0
0
0: No update
1: When a one is written, the time is rounded to the closest minute.
This bit is a toggle bit, the micro-controller can only write one and RTC
clears it. If the micro-controller sets the ROUND_30S bit and then read it,
the micro-controller reads one until the rounded to the closet.
0
STOP_RTC
0: RTC is frozen
1: RTC is running
RW
0
66
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表 22. RTC_STATUS_REG
Address Offset
Physical Address
Description
0x11
Instance
(RESET DOMAIN: FULL RESET)
RTC status register:
Note: A dummy read of this register is necessary before each I2C read in order to update the status
register value.
Type
RW
7
6
5
4
3
2
1
0
POWER_UP
ALARM
EVENT_1D
EVENT_1H
EVENT_1M
EVENT_1S
RUN
Reserved
BITS
FIELD NAME
POWER_UP
DESCRIPTION
TYPE
RESET
7
Indicates that a reset occurred (bit cleared to 0 by writing 1).
POWER_UP is set by a reset, is cleared by writing one in this bit.
RW
1
6
ALARM
Indicates that an alarm interrupt is generated (bit clear by writing 1).
The alarm interrupt keeps its low level, until the micro-controller write 1 in
the ALARM bit of the RTC_STATUS_REG register.
RW
0
The timer interrupt is a low-level pulse (15 µs duration).
5
4
3
2
1
EVENT_1D
EVENT_1H
EVENT_1M
EVENT_1S
RUN
One day has occurred
One hour has occurred
One minute has occurred
One second has occurred
RO
RO
RO
RO
RO
0
0
0
0
0
0: RTC is frozen
1: RTC is running
This bit shows the real state of the RTC, because STOP_RTC signal
was resynchronized on 32-kHz clock, the action of this bit is delayed.
0
Reserved
Reserved bit
RO
R returns
0s
0
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表 23. RTC_INTERRUPTS_REG
Address Offset
Physical Address
Description
Type
0x12
Instance
(RESET DOMAIN: FULL RESET)
RTC interrupt-control register
RW
7
6
5
4
3
2
1
0
Reserved
IT_ALARM
IT_TIMER
EVERY
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:5
Reserved bit
RO
0x0
R returns
0s
4
IT_SLEEP_MASK_E 1: Mask periodic interrupt while the TPS659119-Q1 device is in SLEEP
RW
0
N
mode. The interrupt event is back up in a register and occurs as soon as
the TPS659119-Q1 device is no longer in SLEEP mode.
0: Normal mode, no interrupt masked
3
2
IT_ALARM
IT_TIMER
Enable one interrupt when the alarm value is reached (TC ALARM
registers) by the TC registers
RW
RW
0
0
Enable periodic interrupt
0: interrupt disabled
1: interrupt enabled
1:0
EVERY
Interrupt period
00: every second
01: every minute
10: every hour
11: every day
RW
0x0
表 24. RTC_COMP_LSB_REG
Address Offset
Physical Address
Description
0x13
Instance
(RESET DOMAIN: FULL RESET)
RTC compensation register (LSB)
Note: This register must be written in twos-complement.
Which means that to add one 32-kHz oscillator period every hour, the microcontroller muse write FFFF
into RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
To remove one 32-kHz oscillator period every hour, the microcontroller needs to write 0001 into
RTC_COMP_MSB_REG & RTC_COMP_LSB_REG.
The 7FFF value is forbidden.
Type
RW
7
6
5
4
3
2
1
0
RTC_COMP_LSB
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:0
RTC_COMP_LSB
This register contains the number of 32-kHz periods to be added into the
32-kHz counter every hour [LSB]
RW
0x00
68
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表 25. RTC_COMP_MSB_REG
Address Offset
Physical Address
Description
0x14
Instance
(RESET DOMAIN: FULL RESET)
RTC compensation register (MSB)
Notes: See RTC_COMP_LSB_REG Notes.
Type
RW
7
6
5
4
3
2
1
0
RTC_COMP_MSB
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:0
RTC_COMP_MSB
This register contains the number of 32-kHz periods to be added into the
32-kHz counter every hour [MSB]
RW
0x00
表 26. RTC_RES_PROG_REG
Address Offset
Physical Address
Description
Type
0x15
Instance
RTC register containing oscillator resistance value
RW
(RESET DOMAIN: FULL RESET)
7
6
5
4
3
2
1
0
Reserved
SW_RES_PROG
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5:0
SW_RES_PROG
Value of the oscillator resistance
RW
0x27
表 27. RTC_RESET_STATUS_REG
Address Offset
Physical Address
Description
Type
0x16
Instance
(RESET DOMAIN: FULL RESET)
RTC register for reset status
RW
7
6
5
4
3
2
1
0
Reserved
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:1
Reserved bit
RO
R returns
0s
0x0
0
RESET_STATUS
This bit can only be set to one and is cleared when a manual reset or a
POR (VBAT < 2.1) occur. If this bit is reset the RTC lost its configuration.
RW
0
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表 28. BCK1_REG
Address Offset
Physical Address
Description
0x17
Instance
(RESET DOMAIN: FULL RESET)
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers retain content as long as the VRTC is active.
Type
RW
7
6
6
6
5
4
3
2
1
0
BCKUP
BITS
FIELD NAME
BCKUP
DESCRIPTION
TYPE
RESET
7:0
Backup bit
RW
0x00
表 29. BCK2_REG
Address Offset
Physical Address
Description
0x18
Instance
(RESET DOMAIN: FULL RESET)
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers retain content as long as the VRTC is active.
Type
RW
7
5
4
3
2
1
0
BCKUP
BITS
FIELD NAME
BCKUP
DESCRIPTION
TYPE
RESET
7:0
Backup bit
RW
0x00
表 30. BCK3_REG
Address Offset
Physical Address
Description
0x19
Instance
(RESET DOMAIN: FULL RESET)
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers retain content as long as the VRTC is active.
Type
RW
7
5
4
3
2
1
0
BCKUP
BITS
FIELD NAME
BCKUP
DESCRIPTION
TYPE
RESET
7:0
Backup bit
RW
0x00
70
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表 31. BCK4_REG
Address Offset
Physical Address
Description
0x1A
Instance
(RESET DOMAIN: FULL RESET)
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers retain content as long as the VRTC is active.
Type
RW
7
6
5
4
3
2
1
0
BCKUP
BITS
FIELD NAME
BCKUP
DESCRIPTION
TYPE
RESET
7:0
Backup bit
RW
0x00
表 32. BCK5_REG
Address Offset
Physical Address
Description
0x1B
Instance
(RESET DOMAIN: FULL RESET)
Backup register which can be used for storage by the application firmware when the external host is
powered down. These registers retain content as long as the VRTC is active.
Type
RW
7
6
5
4
3
2
1
0
BCKUP
BITS
FIELD NAME
BCKUP
DESCRIPTION
TYPE
RESET
7:0
Backup bit
RW
0x00
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表 33. PUADEN_REG
Address Offset
0x1C
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
Pullup and pulldown control register.
RW
7
6
5
4
3
2
1
0
Reserved
I2CCTLP
I2CSRP
PWRONP
SLEEPP
PWRHOLDP
HDRSTP
BITS
FIELD NAME
DESCRIPTION
TYPE
RO
RESET
7
6
Reserved
I2CCTLP
0
0
SDACTL and SCLCTL pullup control:
1: Pullup is enabled
RW
0: Pullup is disabled
5
4
3
2
1
0
I2CSRP
SDASR and SCLSR pullup control:
1: Pullup is enabled
0: Pullup is disabled
RW
RW
RW
RW
RW
RW
0
1
1
1
1
1
PWRONP
SLEEPP
PWRON-pad pullup control:
1: Pullup is enabled
0: Pullup is disabled
SLEEP-pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
PWRHOLDP
HDRSTP
PWRHOLD-pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
HDRST-pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
NRESPWRON2P
NRESPWRON2 pad control:
1: Pulldown is enabled
0: Pulldown is disabled
72
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表 34. REF_REG
Address Offset
0x1D
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
Reference control register
RO
7
6
5
4
3
2
1
0
Reserved
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:2
Reserved
Reserved bit
RO
R returns
0s
0x00
1:0
ST
Reference state:
RO
0x1
ST[1:0] = 00: Off
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Reserved
ST[1:0] = 11: On low power (SLEEP)
(Write access available in test mode only)
表 35. VRTC_REG
Address Offset
0x1E
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
VRTC internal regulator control register
RW
7
6
5
4
3
2
1
0
Reserved
Reserved
ST
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:4
Reserved bit
RO
R returns
0s
0x0
3
VRTC_OFFMASK
VRTC internal regulator off mask signal:
RW
0
When set to 1, the regulator keeps its full-load capability during device
OFF state.
When set to 0, the regulator enters in low-power mode during device
OFF state.
Note that VRTC enters low-power mode when the device is on backup
even if this bit is set to 1 (Default value: See boot configuration)
2
Reserved
ST
Reserved bit
RO
R returns
0s
0
1:0
Reference state:
RO
0x1
ST[1:0] = 00: Reserved
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Reserved
ST[1:0] = 11: On low power (SLEEP)
(Write access available in test mode only)
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表 36. VIO_REG
Address Offset
0x20
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
VIO control register
RW
7
6
5
4
3
2
1
0
ILIM
Reserved
SEL
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
ILIM
Current-limit threshold selection:
ILIM[1:0] = 00: 0.7 A
ILIM[1:0] = 01: 1.2 A
RW
0x0
TPS6591
19xAIPF
PRQ1
ILIM[1:0] = 10: 1.7 A
ILIM[1:0] = 11: > 1.7 A
5:4
3:2
Reserved
SEL
Reserved bit
RO
R returns
0s
0x0
0x0
Output voltage selection (EEPROM bits):
SEL[1:0] = 00: 1.5 V
RW
SEL[1:0] = 01: 1.8 V
SEL[1:0] = 10: 2.5 V
SEL[1:0] = 11: 3.3 V
(Default value: see boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: OFF
RW
0x0
ST[1:0] = 01: ON high power (ACTIVE)
ST[1:0] = 10: OFF
ST[1:0] = 11: ON low power (SLEEP)
74
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表 37. VDD1_REG
Address Offset
0x21
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
VDD1 control register
RW
7
6
5
4
3
2
1
0
VGAIN_SEL
ILMAX
TSTEP
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
VGAIN_SEL
Select output voltage multiplication factor: G (EEPROM bits):
When set to 00: x1
RW
0x0
When set to 01: TBD
When set to 10: x2
When set to 11: x3
(Default value: see boot configuration)
5:4
3:2
ILMAX
TSTEP
Select current limit threshold:
When set to 0: 1.2 A
When set to 1: > 1.7 A
RW
RW
0
Time step: when changing the output voltage, the new value is reached
through successive 12.5-mV voltage steps (if not bypassed). The
equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)
0x3
TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)
TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)
TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)
TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: OFF
RW
0x0
ST[1:0] = 01: ON, high-power mode
ST[1:0] = 10: OFF
ST[1:0] = 11: ON, low-power mode
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表 38. VDD1_OP_REG
Address Offset
0x22
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
VDD1 voltage selection register.
This register can be accessed by both control and voltage-scaling I2C interfaces depending on the
SR_CTL_I2C_SEL register bit value.
RW
7
6
5
4
3
2
1
0
CMD
SEL
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
CMD
When set to 0: VDD1_OP_REG voltage is applied
When set to 1: VDD1_SR_REG voltage is applied
RW
0
6:0
SEL
Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1,
RW
0x00
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
VOUT = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
(Default value: See boot configuration)
表 39. VDD1_SR_REG
Address Offset
0x23
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
VDD1 voltage selection register.
This register can be accessed by both control and voltage scaling dedicated I2C interfaces depending
on SR_CTL_I2C_SEL register bit value.
RW
7
6
5
4
3
2
1
0
Reserved
SEL
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
Reserved bit
RO
R returns
0s
0
6:0
SEL
Output voltage selection with GAIN_SEL = 00 (G = 1, 12.5 mV per LSB):
RW
0x00
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
VOUT = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
(Default value: See boot configuration)
76
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表 40. VDD2_REG
Address Offset
0x24
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
VDD2 control register
RW
7
6
5
4
3
2
1
0
VGAIN_SEL
ILMAX
TSTEP
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
VGAIN_SEL
Select output voltage multiplication factor (x1, x3 included in EEPROM
RW
0x0
bits): G
When set to 00: x1
When set to 01: TBD
When set to 10: x2
When set to 11: x3
5:4
3:2
ILMAX
TSTEP
Select current limit threshold
When set to 0: 1.2 A
When set to 1: > 1.7 A
RW
RW
0
Time step: when changing the output voltage, the new value is reached
through successive 12.5-mV voltage steps (if not bypassed). The
equivalent programmable slew rate of the output voltage is then:
TSTEP[2:0] = 000: step duration is 0, step function is bypassed
TSTEP[2:0] = 001: 12.5 mV/µs (sampling 3 MHz)
0x1
TSTEP[2:0] = 010: 9.4 mV/µs (sampling 3 MHz × 3/4)
TSTEP[2:0] = 011: 7.5 mV/µs (sampling 3 MHz × 3/5) (default)
TSTEP[2:0] = 100: 6.25 mV/µs(sampling 3 MHz/2)
TSTEP[2:0] = 101: 4.7 mV/µs(sampling 3 MHz/3)
TSTEP[2:0] = 110: 3.12 mV/µs(sampling 3 MHz/4)
TSTEP[2:0] = 111: 2.5 mV/µs(sampling 3 MHz/5)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: OFF
RW
0x0
ST[1:0] = 01: ON, high-power mode
ST[1:0] = 10: OFF
ST[1:0] = 11: ON, low-power mode
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表 41. VDD2_OP_REG
Address Offset
0x25
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
VDD2 voltage selection register.
This register can be accessed by both control-dedicated and voltage-scaling-dedicated I2C interfaces
depending on the SR_CTL_I2C_SEL register bit value.
RW
7
6
5
4
3
2
1
0
CMD
SEL
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
CMD
Command:
RW
0
When set to 0: VDD2_OP_REG voltage is applied
When set to 1: VDD2_SR_REG voltage is applied
6:0
SEL
Output voltage (4 EEPROM bits) selection with GAIN_SEL = 00 (G = 1,
RW
0x00
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0.0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
VOUT = (SEL[6:0] × 12.5 mV + 0.5625 V) × G
表 42. VDD2_SR_REG
Address Offset
0x26
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
VDD2 voltage selection register.
This register can be accessed by both control-dedicated and voltage-scaling-dedicated I2C interfaces
depending on the SR_CTL_I2C_SEL register bit value.
RW
7
6
5
4
3
2
1
0
Reserved
SEL
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
Reserved bit
RO
R returns
0s
0
6:0
SEL
Output voltage (EEPROM bits) selection with GAIN_SEL = 00 (G = 1,
RW
0x00
12.5 mV per LSB):
SEL[6:0] = 1001011 to 1111111: 1.5 V
...
SEL[6:0] = 0111111: 1.35 V
...
SEL[6:0] = 0110011: 1.2 V
...
SEL[6:0] = 0000001 to 0000011: 0.6 V
SEL[6:0] = 0000000: Off (0 V)
Note: from SEL[6:0] = 3 to 75 (dec)
VOUT= (SEL[6:0] × 12.5 mV + 0.5625 V) × G
78
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 43. EXTCTRL_REG
Address Offset
0x27
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
EXTCTRL, external converter voltage controller
RW
7
6
5
4
3
2
1
0
Reserved
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:2
Reserved
Reserved bit
RO
R returns
0s
0x00
1:0
ST
Supply state (EEPROM dependent):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On
ST[1:0] = 10: Off
ST[1:0] = 11: On
表 44. EXTCTRL_OP_REG
Address Offset
0x28
Physical Address
Instance
(RESET DOMAIN: TURN OFF
RESET)
Description
Type
EXTCTRL voltage-selection register.
This register can be accessed by both control-dedicated and voltage-scaling-dedicated I2C interfaces
depending on the SR_CTL_I2C_SEL register bit value.
RW
7
6
5
4
3
2
1
0
CMD
SEL
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
CMD
Command:
RW
0
When set to 0: EXTCTRL_OP_REG voltage is applied
When set to 1: EXTCTRL_SR_REG voltage is applied
6:0
SEL
Resistive divider ratio selection (4 EEPROM bits):
For SEL[6:0] = 3 to 67,
Ratio = 48 / (45 + SEL[6:0])
SEL[6:0] = 67 to 127: 3/7 V/V
SEL[6:0] = 66: 16/37 V/V
...
RW
0x00
SEL[6:0] = 35: 3/5 V/V
...
SEL[6:0] = 5: 24/25 V/V
SEL[6:0] = 4: 48/49 V/V
SEL[6:0] = 1 to 3: 1 V/V
SEL[6:0] = 0 (EN signal low)
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表 45. EXTCTRL_SR_REG
Address Offset
0x29
Physical Address
Instance
(RESET DOMAIN: TURN OFF
RESET)
Description
Type
EXTCTRL voltage selection register.
This register can be accessed by both control-dedicated and voltage-scaling-dedicated I2C interfaces
depending on the SR_CTL_I2C_SEL register bit value.
RW
7
6
5
4
3
2
1
0
Reserved
SEL
BITS
7
FIELD NAME
DESCRIPTION
TYPE
RO
RESET
0
Reserved
SEL
6:0
Resistive divider ratio selection (4 EEPROM bits):
For SEL[6:0] = 3 to 67,
Ratio = 48 / (45 + SEL[6:0])
SEL[6:0] = 67 to 127: 3/7 V/V
SEL[6:0] = 66: 16/37 V/V
...
RW
0x03
SEL[6:0] = 35: 3/5 V/V
...
SEL[6:0] = 5: 24/25 V/V
SEL[6:0] = 4: 48/49 V/V
SEL[6:0] = 1 to 3: 1 V/V
SEL[6:0] = 0 (EN signal low)
表 46. LDO1_REG
Address Offset
0x30
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
LDO1 regulator control register
RW
7
6
5
4
3
2
1
0
SEL
ST
BITS
FIELD NAME
SEL
DESCRIPTION
TYPE
RESET
7:2
Supply voltage (EEPROM bits):
SEL[7:2] = 00000: 000011: 1 V
SEL[7:2] = 000100: 1 V
SEL[7:2] = 000101: 1.05 V
...
RW
0x0
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
(Default value: See boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
80
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表 47. LDO2_REG
Address Offset
0x31
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
LDO2 regulator control register
RW
7
6
5
4
3
2
1
0
SEL
ST
BITS
FIELD NAME
SEL
DESCRIPTION
TYPE
RESET
7:2
Supply voltage (EEPROM bits):
SEL[7:2] = 00000: 000011: 1 V
SEL[7:2] = 000100: 1 V
SEL[7:2] = 000101: 1.05 V
...
RW
0x0
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
(Default value: See boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
表 48. LDO5_REG
Address Offset
0x32
Physical Address
Instance
(RESET DOMAIN: TUROFF
RESET)
Description
Type
LDO5 regulator control register
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
RO
R returns
0s
0
6:2
SEL
Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
RW
0x00
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
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表 49. LDO8_REG
Address Offset
0x33
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
LDO8 regulator control register
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
RO
R returns
0s
0
6:2
SEL
Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
RW
0x00
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
表 50. LDO7_REG
Address Offset
0x34
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
LDO7 regulator control register
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
RO
R returns
0s
0
6:2
SEL
Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
RW
0x00
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
82
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表 51. LDO6_REG
Address Offset
0x35
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
LDO6 regulator control register
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
RO
R returns
0s
0
6:2
SEL
Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
RW
0x00
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
表 52. LDO4_REG
Address Offset
0x36
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
LDO4 regulator control register
RW
7
6
5
4
3
2
1
0
SEL
ST
BITS
FIELD NAME
SEL
DESCRIPTION
TYPE
RESET
7:2
Supply voltage (EEPROM bits):
SEL[7:2] = 00000: 00000: 0.8 V
SEL[7:2] = 00000: 000001: 0.85 V
SEL[7:2] = 00000: 000010: 0.9 V
SEL[7:2] = 000100: 1 V
RW
0x00
SEL[7:2] = 000101: 1.05 V
...
SEL[7:2] = 110001: 3.25 V
SEL[7:2] = 110010: 3.3 V
Applicable voltage selection
TRACK LDO 0: 1 V to 3.3 V
TRACK LDO 1: 0.8 V to 1.5 V
(Default value: See boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
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表 53. LDO3_REG
Address Offset
0x37
Physical Address
Instance
(RESET DOMAIN: TURNOFF OFF
RESET)
Description
Type
LDO3 regulator control register
RW
7
6
5
4
3
2
1
0
Reserved
SEL
ST
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
RO
R returns
0s
0
6:2
SEL
Supply voltage (EEPROM bits):
SEL[6:2] = 00000: 1 V
SEL[6:2] = 00001: 1 V
SEL[6:2] = 00010: 1 V
SEL[6:2] = 00011: 1.1 V
...
RW
0x00
SEL[6:2] = 11000: 3.2 V
SEL[6:2] = 11001: 3.3 V
(Default value: See boot configuration)
1:0
ST
Supply state (EEPROM bits):
ST[1:0] = 00: Off
RW
0x0
ST[1:0] = 01: On high power (ACTIVE)
ST[1:0] = 10: Off
ST[1:0] = 11: On low power (SLEEP)
84
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表 54. Therm_REG
Address Offset
Physical Address
Description
Type
0x38
Instance
(RESET DOMAIN:
Thermal control register
RW
bits[5:2}: GENERAL RESET
bit[0] TURNOFF OFF RESET)
7
6
5
4
3
2
1
0
Reserved
THERM_HD
THERM_TS
THERM_HDSEL
Reserved
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
Reserved bit
RO
R returns
0s
0x0
5
4
THERM_HD
THERM_TS
Hot die detector output:
When set to 0: the hot die threshold is not reached
When set to 1: the hot die threshold is reached
RO
RO
RW
0
0
Thermal shutdown detector output:
When set to 0: the thermal shutdown threshold is not reached
When set to 1: the thermal shutdown threshold is reached
3:2
THERM_HDSEL
Temperature selection for hot-die detector:
When set to 00: Low temperature threshold
…
0x3
When set to 11: High temperature threshold
1
0
Reserved
RO
R returns
0s
0
1
THERM_STATE
Thermal shutdown module enable signal:
RW
When set to 0: thermal shutdown module is disable
When set to 1: thermal shutdown module is enable
表 55. BBCH_REG
Address Offset
0x39
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
Back-up battery charger control register
RW
7
6
5
4
3
2
1
0
Reserved
BBSEL
BBCHEN
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:3
Reserved
Reserved bit
RO
R returns
0s
0x00
2:1
0
BBSEL
Back up battery charge voltage selection:
BBSEL[1:0] = 00: 3 V
BBSEL[1:0] = 01: 2.52 V
BBSEL[1:0] = 10: 3.15 V
BBSEL[1:0] = 11: VBAT
RW
0x0
0
BBCHEN
Back up battery charge enable
RW
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表 56. DCDCCTRL_REG
Address Offset
0x3E
Physical Address
Instance
RESET DOMAIN:
bits [7:3]: TURNOFF OFF RESET
bits [2:0]: GENERAL RESET
Description
Type
DCDC control register
RW
7
6
5
4
3
2
1
0
Reserved
TRACK
VDD2_PSKIP
VDD1_PSKIP
VIO_PSKIP
DCDCCKEXT
DCDCCKSYNC
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
Reserved bit
RO
R returns
0s
0
6
TRACK
1: Tracking mode: LDO4 output follows VDD1 setting when VDD1 active.
RW
0
See the Functional Registers section for more information.
0: Normal LDO operation without tracking
5
4
3
2
VDD2_PSKIP
VDD1_PSKIP
VIO_PSKIP
VDD2 pulse skip mode enable (EEPROM bit)
Default value: See boot configuration
RW
RW
RW
RW
1
1
1
0
VDD1 pulse skip mode enable (EEPROM bit)
Default value: See boot configuration
VIO pulse skip mode enable (EEPROM bit)
Default value: See boot configuration
DCDCCKEXT
This signal control the muxing of the GPIO2 pad:
When set to 0: this pad is a GPIO
When set to 1: this pad is used as input for an external clock used for the
synchronization of the DCDCs
1:0
DCDCCKSYNC
DC-DC clock configuration:
RW
0x1
DCDCCKSYNC[1:0] = 00: no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 01: DCDC synchronous clock with phase shift
DCDCCKSYNC[1:0] = 10: no synchronization of DCDC clocks
DCDCCKSYNC[1:0] = 11: DCDC synchronous clock
86
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表 57. DEVCTRL_REG
Address Offset
0x3F
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
Device control register
RW
7
6
5
4
3
2
1
0
RTC_PWDN
CK32K_CTRL
DEV_ON
DEV_SLP
DEV_OFF
BITS
FIELD NAME
PWR_OFF_SEQ
DESCRIPTION
TYPE
RESET
7
When set to 1, power-off is sequential, reverse of power-on sequence
(first resource to power on is the last to power off).
RW
0
When set to 0, all resources disabled at the same time
6
5
RTC_PWDN
When set to 1, disable the RTC digital domain (clock gating and reset of
RTC registers and logic).
This register bit is not reset in BACKUP state.
RW
RW
0
0
CK32K_CTRL
Internal 32-kHz clock source control bit (EEPROM bit):
When set to 0, either the crystal oscillator or the external clock is used as
the internal 32-kHz clock source
When set to set to 1, the internal RC oscillator is used as the 32-kHz
clock source.
4
SR_CTL_I2C_SEL
Voltage scaling registers access control bit:
RW
1
When set to 0: access to registers by voltage scaling I2C
When set to 1: access to registers by control I2C. The voltage scaling
registers are: VDD1_OP_REG, VDD1_SR_REG, VDD2_OP_REG,
VDD2_SR_REG, EXTCTRL_OP_REG, and EXTCTRL_SR_REG.
3
2
DEV_OFF_RST
DEV_ON
Writing 1 starts an ACTIVE-to-OFF or SLEEP-to-OFF device state
transition (switch-off event) and activate reset of the digital core.
This bit is cleared in OFF state.
RW
RW
0
0
Writing 1 maintains the device on (ACTIVE or SLEEP device state) (if
DEV_OFF = 0 and DEV_OFF_RST = 0).
EEPROM bit
(Default value: See boot configuration)
1
0
DEV_SLP
DEV_OFF
Writing 1 allows SLEEP device state (if DEV_OFF = 0 and
DEV_OFF_RST = 0).
Writing 0 starts an SLEEP-to-ACTIVE device state transition (wake-up
event) (if DEV_OFF = 0 and DEV_OFF_RST = 0). This bit is cleared in
OFF state.
RW
RW
0
0
Writing 1 starts an ACTIVE-to-OFF or SLEEP-to-OFF device state
transition (switch-off event). This bit is cleared in OFF state.
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表 58. DEVCTRL2_REG
Address Offset
0x40
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
Device control register
RW
7
6
5
4
3
2
1
0
Reserved
TSLOT_LENGTH
IT_POL
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7
RO
0
R returns
0s
6
DCDC_SLEEP_LVL
TSLOT_LENGTH
When set to 1, DCDC output level in SLEEP mode is VDDx_SR_REG, to
be other than 0 V.
When set to 0, no effect
RW
0
5:4
Time slot duration programming (EEPROM bit):
When set to 00: 0 µs
RW
0x3
When set to 01: 200 µs
When set to 10: 500 µs
When set to 11: 2 ms
(Default value: See boot configuration)
3
2
SLEEPSIG_POL
PWON_LP_OFF
When set to 1, SLEEP signal active-high
When set to 0, SLEEP signal active-low
RW
RW
0
1
When set to 1, allows device turn-off after a PWON Long Press (signal
low) (EEPROM bits).
(Default value: See boot configuration)
1
0
PWON_LP_RST
IT_POL
When set to 1, allows digital core reset when the device is OFF
(EEPROM bit).
(Default value: See boot configuration)
RW
RW
0
0
INT1 interrupt pad polarity control signal (EEPROM bit):
When set to 0, active low
When set to 1, active high
(Default value: See boot configuration)
88
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 59. SLEEP_KEEP_LDO_ON_REG
Address Offset
0x41
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
When corresponding control bit = 0 in EN1_ LDO_ASS register (default setting): Configuration Register
keeping the full load capability of LDO regulator (ACTIVE mode) during the SLEEP state of the device.
When control bit = 1, LDO regulator full load capability (ACTIVE mode) is maintained during device
SLEEP state.
When control bit = 0, the LDO regulator is set or stay in low-power mode during device SLEEP state(but
then supply state can be overwritten programming ST[1:0]). There is no control bit value effect if the
LDO regulator is off.
When corresponding control bit = 1 in EN1_ LDO_ASS register: Configuration register setting the LDO
regulator state driven by SCLSR_EN1 signal low level (when SCLSR_EN1 is high the regulator is on,
full power):
- the regulator is set off if the corresponding Control bit = 0 in SLEEP_KEEP_LDO_ON register (default)
- the regulator is set in low-power mode if its corresponding control bit = 1 in SLEEP_KEEP_LDO_ON
register
Type
RW
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
LDO3_KEEPON
LDO4_KEEPON
LDO7_KEEPON
LDO8_KEEPON
LDO5_KEEPON
LDO2_KEEPON
LDO1_KEEPON
LDO6_KEEPON
Setting supply state during device SLEEP state or when SCLSR_EN1 is
low
RW
0
6
5
4
3
2
1
0
Setting supply state during device SLEEP state or when SCLSR_EN1 is
low
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
Setting supply state during device SLEEP state or when SCLSR_EN1 is
low
Setting supply state during device SLEEP state or when SCLSR_EN1 is
low
Setting supply state during device SLEEP state or when SCLSR_EN1 is
low
Setting supply state during device SLEEP state or when SCLSR_EN1 is
low
Setting supply state during device SLEEP state or when SCLSR_EN1 is
low
Setting supply state during device SLEEP state or when SCLSR_EN1 is
low
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表 60. SLEEP_KEEP_RES_ON_REG
Address Offset
Physical Address
Description
0x42
Instance
Configuration Register keeping, during the SLEEP state of the device (but then supply state can be
overwritten programming ST[1:0]):
- the full load capability of LDO regulator (ACTIVE mode),
- The PWM mode of DC-DC converter
- 32-kHz clock output
- Register access though I2C interface (keeping the internal high speed clock on)
- Die thermal monitoring is on
There is no control bit value effect if the resource is off.
Type
RW
7
6
5
4
3
2
1
0
Reserved
VIO_KEEPON
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
THERM_KEEPON
When set to 1, thermal monitoring is maintained during device SLEEP
RW
0
state.
When set to 0, thermal monitoring is turned off during device SLEEP
state.
6
5
4
CLKOUT32K_KEEPON When set to 1, CLK32KOUT output is maintained during device
RW
RW
RW
0
0
0
SLEEP state.
When set to 0, CLK32KOUT output is set low during device SLEEP
state.
VRTC_KEEPON
I2CHS_KEEPON
When set to 1, LDO regulator full load capability (ACTIVE mode) is
maintained during device SLEEP state.
When set to 0, the LDO regulator is set or stays in low-power mode
during device SLEEP state.
When set to 1, high speed internal clock is maintained during device
SLEEP state.
When set to 0, high speed internal clock is turned off during device
SLEEP state.
3
2
Reserved
RO
0
0
VDD2_KEEPON
When set to 1, VDD2 SMPS-PWM mode is maintained during device
SLEEP state. No effect if VDD2 working mode is PFM.
When set to 0, VDD2 SMPS-PFM mode is set during device SLEEP
state.
RW
1
0
VDD1_KEEPON
VIO_KEEPON
When set to 1, VDD1 SMPS-PWM mode is maintained during device
SLEEP state. No effect if VDD1 working mode is PFM.
When set to 0, VDD1 SMPS-PFM mode is set during device SLEEP
state.
RW
RW
0
0
When set to 1, VIO SMPS-PWM mode is maintained during device
SLEEP state. No effect if VIO working mode is PFM.
When set to 0, VIO SMPS-PFM mode is set during device SLEEP
state.
90
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 61. SLEEP_SET_LDO_OFF_REG
Address Offset
0x43
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Configuration register turning-off LDO regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON register should be 0 to make this
*_SET_OFF control bit effective
Type
RW
7
6
5
4
3
2
1
0
LDO4_SETOFF LDO7_SETOFF LDO8_SETOFF LDO5_SETOFF LDO2_SETOFF LDO1_SETOFF LDO6_SETOFF
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
LDO3_SETOFF
When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect
RW
0
6
5
4
3
2
1
0
LDO4_SETOFF
LDO7_SETOFF
LDO8_SETOFF
LDO5_SETOFF
LDO2_SETOFF
LDO1_SETOFF
LDO6_SETOFF
When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect
When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect
When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect
When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect
When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect
When set to 1, LDO regulator is turned off during device SLEEP state.
When set to 0, No effect
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表 62. SLEEP_SET_RES_OFF_REG
Address Offset
0x44
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Configuration Register turning-off SMPS regulator during the SLEEP state of the device.
Corresponding *_KEEP_ON control bit in SLEEP_KEEP_RES_ON2 register should be 0 to make this
*_SET_OFF control bit effective. Supplies voltage expected after the wake-up (SLEEP-to-ACTIVE state
transition) can also be programmed.
Type
RW
7
6
5
4
3
2
1
0
Reserved
VIO_SETOFF
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
DEFAULT_VOLT
When set to 1, default voltages (register value after switch-on) are
applied to all resources during SLEEP-to-ACTIVE transition.
When set to 0, voltages programmed before the ACTIVE-to-SLEEP state
transition are used to turned-on supplies during SLEEP-to-ACTIVE state
transition.
RW
0
6:5
Reserved
RO
R returns
0s
0x0
4
3
SPARE_SETOFF
Spare bit
RW
RW
0
0
EXTCTRL_SETOFF
When set to 1, SMPS is turned off during device SLEEP state.
When set to 0, No effect.
2
1
0
VDD2_SETOFF
VDD1_SETOFF
VIO_SETOFF
When set to 1, SMPS is turned off during device SLEEP state.
When set to 0, No effect.
RW
RW
RW
0
0
0
When set to 1, SMPS is turned off during device SLEEP state.
When set to 0, No effect.
When set to 1, SMPS is turned off during device SLEEP state.
When set to 0, No effect.
92
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 63. EN1_LDO_ASS_REG
Address Offset
0x45
Physical Address
Instance
(RESET DOMAIN: TURNOFF
RESET)
Description
Configuration Register setting the LDO regulators, driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, LDO regulator state is driven by the SCLSR_EN1 control signal and is also defined
though SLEEP_KEEP_LDO_ON register setting:
When SCLSR_EN1 is high the regulator is on,
When SCLSR_EN1 is low:
- the regulator is off if the corresponding control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low-power mode if the corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 disables the I2C SR Interface functionality
Type
RW
7
6
5
4
3
2
1
0
LDO3_EN1
LDO4_EN1
LDO7_EN1
LDO8_EN1
LDO5_EN1
LDO2_EN1
LDO1_EN1
LDO6_EN1
BITS
FIELD NAME
LDO3_EN1
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
Setting supply-state control though the SCLSR_EN1 signal
Setting supply-state control though the SCLSR_EN1 signal
Setting supply-state control though the SCLSR_EN1 signal
Setting supply-state control though the SCLSR_EN1 signal
Setting supply-state control though the SCLSR_EN1 signal
Setting supply-state control though the SCLSR_EN1 signal
Setting supply-state control though the SCLSR_EN1 signal
Setting supply-state control though the SCLSR_EN1 signal
0
0
0
0
0
0
0
0
LDO4_EN1
LDO7_EN1
LDO8_EN1
LDO5_EN1
LDO2_EN1
LDO1_EN1
LDO6_EN1
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表 64. EN1_SMPS_ASS_REG
Address Offset
0x46
Physical Address
Instance
(RESET DOMAIN: TURNOFF
RESET)
Description
Configuration register setting the SMPS supplies driven by the multiplexed SCLSR_EN1 signal.
When control bit = 1, SMPS supply state and voltage is driven by the SCLSR_EN1 control signal and is
also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: SMPS Supply state is driven though registers programming and the
device state.
Any control bit of this register set to 1 disables the I2C SR Interface functionality
Type
RW
7
6
5
4
3
2
1
0
Reserved
SPARE_EN1 EXTCTRL_EN1
VDD2_EN1
VDD1_EN1
VIO_EN1
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:5
RO
R returns
0s
0x0
4
3
SPARE_EN1
Spare bit
RW
RW
0
0
EXTCTRL_EN1
When control bit = 1:
When EN1 is high the supply voltage is programmed though
EXTCTRL_OP_REG register, and it can also be programmed off.
When EN1 is low the supply voltage is programmed though
EXTCTRL_SR_REG register, and it can also be programmed off.
When control bit = 0: No effect: Supply state is driven though registers
programming and the device state
2
1
0
VDD2_EN1
VDD1_EN1
VIO_EN1
When control bit = 1:
RW
RW
RW
0
0
0
When SCLSR_EN1 is high the supply voltage is programmed though
VDD2_OP_REG register, and it can also be programmed off.
When SCLSR_EN1 is low the supply voltage is programmed though
VDD2_SR_REG register, and it can also be programmed off.
When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is
working in low-power mode, if not tuned off through VDD2_SR_REG
register.
When control bit = 0 No effect: the supply state is driven though registers
programming and the device state
When 1:
When SCLSR_EN1 is high the supply voltage is programmed though
VDD1_OP_REG register, and it can also be programmed off.
When SCLSR_EN1 is low the supply voltage is programmed though
VDD1_SR_REG register, and it can also be programmed off.
When SCLSR_EN1 is low and SLEEP_KEEP_RES_ON = 1 the SMPS is
working in low-power mode, if not tuned off though VDD1_SR_REG
register.
When control bit = 0 no effect: supply state is driven though registers
programming and the device state
When control bit = 1, the supply state is driven by the SCLSR_EN1
control signal and is also defined though the SLEEP_KEEP_RES_ON
register setting:
When SCLSR_EN1 is high the supply is on,
When SCLSR_EN1 is low:
- the supply is off (default) or the SMPS is working in low-power mode if
the corresponding control bit = 1 in SLEEP_KEEP_RES_ON register
When control bit = 0 No effect: SMPS state is driven though registers
programming and the device state
94
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 65. EN2_LDO_ASS_REG
Address Offset
0x47
Physical Address
Instance
(RESET DOMAIN: TURNOFF
RESET)
Description
Configuration Register setting the LDO regulators, driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, LDO regulator state is driven by the SDASR_EN2 control signal and is also
defined though SLEEP_KEEP_LDO_ON register setting:
When SDASR_EN2 is high the regulator is on,
When SCLSR_EN2 is low:
- the regulator is off if the corresponding control bit = 0 in SLEEP_KEEP_LDO_ON register
- the regulator is working in low-power mode if the corresponding control bit = 1 in
SLEEP_KEEP_LDO_ON register
When control bit = 0 no effect: LDO regulator state is driven though registers programming and the
device state
Any control bit of this register set to 1 disables the I2C SR Interface functionality
Type
RW
7
6
5
4
3
2
1
0
LDO3_EN2
LDO4_EN2
LDO7_EN2
LDO8_EN2
LDO5_EN2
LDO2_EN2
LDO1_EN2
LDO6_EN2
BITS
FIELD NAME
LDO3_EN2
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
Setting supply-state control though the SDASR_EN2 signal
Setting supply-state control though the SDASR_EN2 signal
Setting supply-state control though the SDASR_EN2 signal
Setting supply-state control though the SDASR_EN2 signal
Setting supply-state control though the SDASR_EN2 signal
Setting supply-state control though the SDASR_EN2 signal
Setting supply-state control though the SDASR_EN2 signal
Setting supply-state control though the SDASR_EN2 signal
0
0
0
0
0
0
0
0
LDO4_EN2
LDO7_EN2
LDO8_EN2
LDO5_EN2
LDO2_EN2
LDO1_EN2
LDO6_EN2
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表 66. EN2_SMPS_ASS_REG
Address Offset
0x48
Physical Address
Instance
(RESET DOMAIN: TURNOFF
RESET)
Description
Configuration Register setting the SMPS Supplies driven by the multiplexed SDASR_EN2 signal.
When control bit = 1, the SMPS Supply state and voltage is driven by the SDASR_EN2 control signal
and is also defined though SLEEP_KEEP_RES_ON register setting.
When control bit = 0 no effect: the SMPS Supply state is driven though registers programming and the
device state
Any control bit of this register set to 1 disables the I2C SR Interface functionality
Type
RW
7
6
5
4
3
2
1
0
Reserved
SPARE_EN2 EXTCTRL_EN2
VDD2_EN2
VDD1_EN2
VIO_EN2
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:5
RO
R returns
0s
0x0
4
3
SPARE_EN2
Spare bit
RW
RW
0
0
EXTCTRL_EN2
When control bit = 1:
When EN2 is high the supply voltage is programmed though
EXTCTRL_OP_REG register, and it can also be programmed off..
When EN2 is low the supply voltage is programmed though
EXTCTRL_SR_REG register, and it can also be programmed off.
When EN2 is low and EXTCTRL_KEEPON = 1 the SMPS is working in
low-power mode, if not tuned off though EXTCTRL_SR_REG register.
When control bit = 0 no effect: the supply state is driven though registers
programming and the device state
2
1
0
VDD2_EN2
VDD1_EN2
VIO_EN2
When control bit = 1:
RW
RW
RW
0
0
0
When SDASR_EN2 is high the supply voltage is programmed though
VDD2_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though
VDD2_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS
is working in low-power mode, if not tuned off though VDD2_SR_REG
register.
When control bit = 0 no effect: the supply state is driven though registers
programming and the device state
When control bit = 1:
When SDASR_EN2 is high the supply voltage is programmed though
VDD1_OP_REG register, and it can also be programmed off.
When SDASR_EN2 is low the supply voltage is programmed though
VDD1_SR_REG register, and it can also be programmed off.
When SDASR_EN2 is low and SLEEP_KEEP_RES_ON = 1 the SMPS
is working in low-power mode, if not tuned off though VDD1_SR_REG
register.
When control bit = 0 no effect: the supply state is driven though registers
programming and the device state
When control bit = 1,
supply state is driven by the SCLSR_EN2 control signal and is also
defined though SLEEP_KEEP_RES_ON register setting:
When SDASR _EN2 is high the supply is on,
When SDASR _EN2 is low :
- the supply is off (default) or the SMPS is working in low-power mode if
its corresponding control bit = 1 in SLEEP_KEEP_RES_ON register
When control bit = 0 no effect: the SMPS state is driven though registers
programming and the device state
96
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www.ti.com.cn
ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 67. INT_STS_REG
Address Offset
Physical Address
Description
0x50
Instance
(RESET DOMAIN: FULL RESET)
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. The interrupt-status
bit is cleared by writing 1.
Type
RW
7
6
5
4
3
2
1
0
HOTDIE_IT
PWRON_LP_IT
PWRON_IT
Reserved
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
RTC_PERIOD_IT
RTC_ALARM_IT
HOTDIE_IT
RTC-period-event interrupt status
RTC-alarm-event interrupt status
Hot-die-event interrupt status
RW
W1 to Clr
0
6
5
4
3
2
1
0
RW
W1 to Clr
0
0
0
0
0
0
0
RW
W1 to Clr
PWRHOLD_R_IT
PWRON_LP_IT
PWRON_IT
Rising-PWRHOLD-event interrupt status
PWRON-long-press event interrupt status
PWRON-event interrupt status
RW
W1 to Clr
RW
W1 to Clr
RW
W1 to Clr
Reserved
Reserved, always clear
RW
W1 to Clr
PWRHOLD_F_IT
Falling-PWRHOLD-event interrupt status
RW
W1 to Clr
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表 68. INT_MSK_REG
Address Offset
0x51
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
1
0
Reserved
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
RTC_PERIOD_IT_MS RTC-period-event interrupt mask
K
RW
1
6
RTC_ALARM_IT_MS RTC-alarm-event interrupt mask
K
RW
1
5
4
HOTDIE_IT_MSK
Hot-die-event interrupt mask
RW
RW
1
1
PWRHOLD_R_IT_MS PWRHOLD rising-edge-event interrupt mask
K
3
2
1
0
PWRON_LP_IT_MSK PWRON long-press-event interrupt mask
RW
RW
RW
RW
1
1
1
1
PWRON_IT_MSK
Reserved
PWRON-event interrupt mask
Reserved, always masks
PWRHOLD_F_IT_MS PWRHOLD falling-edge-event interrupt mask
K
98
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 69. INT_STS2_REG
Address Offset
Physical Address
Description
0x52
Instance
(RESET DOMAIN: FULL RESET)
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. Interrupt status bit is
cleared by writing 1.
Type
RW
7
6
5
4
3
2
1
0
GPIO3_F_IT
GPIO3_R_IT
GPIO2_F_IT
GPIO2_R_IT
GPIO1_F_IT
GPIO1_R_IT
GPIO0_F_IT
GPIO0_R_IT
BITS
FIELD NAME
GPIO3_F_IT
DESCRIPTION
TYPE
RESET
7
GPIO3 falling-edge-detection interrupt status
GPIO3 rising-edge-detection interrupt status
GPIO2 falling-edge-detection interrupt status
GPIO2 rising-edge-detection interrupt status
GPIO1 falling-edge-detection interrupt status
GPIO1 rising-edge-detection interrupt status
GPIO0 falling-edge-detection interrupt status
GPIO0 rising-edge-detection interrupt status
RW
W1 to Clr
0
6
5
4
3
2
1
0
GPIO3_R_IT
GPIO2_F_IT
GPIO2_R_IT
GPIO1_F_IT
GPIO1_R_IT
GPIO0_F_IT
GPIO0_R_IT
RW
W1 to Clr
0
0
0
0
0
0
0
RW
W1 to Clr
RW
W1 to Clr
RW
W1 to Clr
RW
W1 to Clr
RW
W1 to Clr
RW
W1 to Clr
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表 70. INT_MSK2_REG
Address Offset
0x53
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
1
0
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
GPIO3_F_IT_MSK
GPIO3_R_IT_MSK
GPIO2_F_IT_MSK
GPIO2_R_IT_MSK
GPIO1_F_IT_MSK
GPIO1_R_IT_MSK
GPIO0_F_IT_MSK
GPIO0_R_IT _MSK
GPIO3 falling-edge-detection interrupt mask
GPIO3 rising-edge-detection interrupt mask
GPIO2 falling-edge-detection interrupt mask
GPIO2 rising-edge-detection interrupt mask
GPIO1 falling-edge-detection interrupt mask
GPIO1 rising-edge-detection interrupt mask
GPIO0 falling-edge-detection interrupt mask
GPIO0 rising-edge-detection interrupt mask
1
1
1
1
1
1
1
1
100
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表 71. INT_STS3_REG
Address Offset
Physical Address
Description
0x54
Instance
(RESET DOMAIN: FULL RESET)
Interrupt status register:
The interrupt status bit is set to 1 when the associated interrupt event is detected. The interrupt-status
bit is cleared by writing 1.
Type
RW
7
6
5
4
3
2
1
0
PWRDN_IT
Reserved
Reserved
WTCHDG_IT
GPIO5_F_IT
GPIO5_R_IT
GPIO4_F_IT
GPIO4_R_IT
BITS
FIELD NAME
PWRDN_IT
DESCRIPTION
TYPE
RESET
7
PWRDN reset input high detected
RW
0
W1 to Clr
6
5
4
3
2
1
0
Reserved
Always clear
RW
W1 to Clr
0
0
0
0
0
0
0
Reserved
Always clear
RW
W1 to Clr
WTCHDG_IT
GPIO5_F_IT
GPIO5_R_IT
GPIO4_F_IT
GPIO4_R_IT
Watchdog interrupt status
RW
W1 to Clr
GPIO5 falling-edge-detection interrupt status
GPIO5 rising-edge-detection interrupt status
GPIO4 falling-edge-detection interrupt status
GPIO4 rising-edge-detection interrupt status
RW
W1 to Clr
RW
W1 to Clr
RW
W1 to Clr
RW
W1 to Clr
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表 72. INT_MSK3_REG
Address Offset
0x55
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Interrupt mask register:
When *_IT_MSK is set to 1, the associated interrupt is masked: INT1 signal is not activated, but *_IT
interrupt status bit is updated.
When *_IT_MSK is set to 0, the associated interrupt is enabled: INT1 signal is activated, *_IT is
updated.
Type
RW
7
6
5
4
3
2
1
0
Reserved
Reserved
BITS
FIELD NAME
DESCRIPTION
TYPE
RW
RW
RW
RW
RW
RW
RW
RW
RESET
7
6
5
4
3
2
1
0
PWRDN_IT_MSK
Reserved
PWRDN interrupt mask
Always clear
1
1
1
1
1
1
1
1
Reserved
Always clear
WTCHDG_IT_MSK
GPIO5_F_IT_MSK
GPIO5_R_IT_MSK
GPIO4_F_IT_MSK
GPIO4_R_IT_MSK
Watchdog interrupt mask
GPIO5 falling-edge-detection interrupt mask
GPIO5 rising-edge-detection interrupt mask
GPIO4 falling-edge-detection interrupt mask
GPIO4 rising-edge-detection interrupt mask
102
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表 73. GPIO0_REG
Address Offset
0x60
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO0 configuration register
RW
7
6
5
4
3
2
1
0
GPIO_SLEEP
Reserved
GPIO_ODEN
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
GPIO_SLEEP
DESCRIPTION
TYPE
RESET
7
1: as GPO, force low
RW
0
0: No impact, keep as in active mode
6
5
Reserved
Reserved bit
RO
R returns
0s
0
0
GPIO_ODEN
Selection of output mode, EEPROM bit
0: Push-pull output
RW
1: Open-drain output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit is set to 1 by a TURNOFF
reset
4
3
2
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate
RW
RW
RW
0
0
0
GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
(Default value: See boot configuration)
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit is in TURNOFF reset
RW
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表 74. GPIO1_REG
Address Offset
0x61
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO1 configuration register
RW
7
6
5
4
3
2
1
0
Reserved
GPIO_SEL
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
RO
R returns
0s
0x0
5
4
3
2
GPIO_SEL
GPIO_DEB
GPIO_PDEN
GPIO_CFG
Select signal to be available at GPIO when configured as output:
0: GPIO_SET
1: LED1 out
RW
RW
RW
RW
0
0
1
0
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate
GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
Value set on the GPIO output when configured in output mode
RW
104
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表 75. GPIO2_REG
Address Offset
0x62
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO2 configuration register
RW
7
6
5
4
3
2
1
0
GPIO_SLEEP
Reserved
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
GPIO_SLEEP
DESCRIPTION
TYPE
RESET
7
1: as GPO, force low
RW
0
0: no impact, keep as in active mode
6:5
4
Reserved
RO
R returns
0s
0x0
0
GPIO_DEB
GPIO_PDEN
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate
RW
3
GPIO pad pulldown control:
RW
1
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit is set to 0 by a TURNOFF
reset
2
GPIO_CFG
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit is set to 1 by a TURNOFF
reset
RW
0
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit is in TURNOFF reset
RW
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表 76. GPIO3_REG
Address Offset
0x63
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO3 configuration register
RW
7
6
5
4
3
2
1
0
Reserved
GPIO_SEL
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7
Reserved
RO
R returns
0s
0
6:5
GPIO_SEL
Select signal to be available at GPIO when configured as output:
RW
0x0
00: GPIO_SET
01: LED2 out
10: PWM out
4
3
2
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate
RW
RW
RW
0
1
0
GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
Value set on the GPIO output when configured in output mode
RW
表 77. GPIO4_REG
Address Offset
0x64
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO4 configuration register
RW
7
6
5
4
3
2
1
0
Reserved
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:5
RO
R returns
0s
0x0
4
3
2
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate
RW
RW
RW
0
1
0
GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
Value set on the GPIO output when configured in output mode
RW
106
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 78. GPIO5_REG
Address Offset
0x65
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO5 configuration register
RW
7
6
5
4
3
2
1
0
Reserved
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:5
RO
R returns
0s
0x0
4
3
2
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate
RW
RW
RW
0
1
0
GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
Value set on the GPIO output when configured in output mode
RW
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表 79. GPIO6_REG
Address Offset
0x66
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO6 configuration register
RW
7
6
5
4
3
2
1
0
GPIO_SLEEP
Reserved
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
GPIO_SLEEP
DESCRIPTION
TYPE
RESET
7
1: as GPO, force low
RW
0
0: no impact, keep as in active mode
6:5
4
Reserved
RO
R returns
0s
0x0
0
GPIO_DEB
GPIO_PDEN
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate
RW
3
GPIO pad pulldown control:
RW
1
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit is set to 0 by a TURNOFF
reset
2
GPIO_CFG
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
(Default value: See boot configuration)
GPIO assigned to power-up sequence, this bit is set to 1 by a TURNOFF
reset
RW
0
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
Value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit is in TURNOFF reset
RW
108
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表 80. GPIO7_REG
Address Offset
0x67
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO7 configuration register
RW
7
6
5
4
3
2
1
0
GPIO_SLEEP
Reserved
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
GPIO_SLEEP
DESCRIPTION
1: as GPO, force low
TYPE
RESET
7
RW
0
0: no impact, keep as is in active mode
6:5
4
Reserved
RO
R returns
0s
0x0
0
GPIO_DEB
GPIO_PDEN
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to1, the debouncing is 150 ms using a 50-ms clock rate
RW
3
GPIO pad pulldown-control:
RW
1
1: Pulldown is enabled
0: Pulldown is disabled
GPIO assigned to power-up sequence, this bit is set to 0 by a TURNOFF
reset
2
GPIO_CFG
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
(Default value: See boot configuration )
GPIO assigned to power-up sequence, this bit is set to 1 by a TURNOFF
reset
RW
0
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
The value set on the GPIO output when configured in output mode
GPIO assigned to power-up sequence, this bit is in TURNOFF reset
RW
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表 81. GPIO8_REG
Address Offset
0x68
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
GPIO8 configuration register
RW
7
6
5
4
3
2
1
0
Reserved
GPIO_SEL
GPIO_DEB
GPIO_PDEN
GPIO_CFG
GPIO_STS
GPIO_SET
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
RO
R returns
0s
0x0
5
4
3
2
GPIO_SEL
GPIO_DEB
GPIO_PDEN
GPIO_CFG
Select signal to be available at GPIO when configured as output:
0: GPIO_SET
1: LED1 out
RW
RW
RW
RW
0
0
1
0
GPIO input debouncing time configuration:
When set to 0, the debouncing is 91.5 µs using a 30.5-µs clock rate
When set to 1, the debouncing is 150 ms using a 50-ms clock rate
GPIO pad pulldown control:
1: Pulldown is enabled
0: Pulldown is disabled
Configuration of the GPIO pad direction:
When set to 0, the pad is configured as an input
When set to 1, the pad is configured as an output
1
0
GPIO_STS
GPIO_SET
Status of the GPIO pad
RO
1
0
Value set on the GPIO output when configured in output mode
RW
110
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表 82. WATCHDOG_REG
Address Offset
0x69
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
Watchdog
RW
7
6
5
4
3
2
1
0
Reserved
WTCHDG_TIME
BITS
FIELD NAME
Reserved
DESCRIPTION
TYPE
RESET
7:4
RO
R returns
0s
0x0
3
WTCHDG_MODE
0: Periodic operation:
RW
0
A periodical interrupt is generated based on WTCHDG_TIME setting.
The IC generates WTCHDOG shutdown if an interrupt is not cleared
during the period.
1: Interrupt mode:
The IC generates WTCHDOG shutdown if an interrupt is pending (no
cleared) more than WTCHDG_TIME s.
2:0
WTCHDG_TIME
000: Watchdog disabled
001: 5 seconds
RW
0x0
010: 10 seconds
011: 20 Seconds
100: 40 seconds
101: 60 seconds
110: 80 seconds
111: 100 seconds (EEPROM bit)
(Default value: See boot configuration)
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表 83. BOOTSEQVER_REG
Address Offset
0x6A
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
Comparator control register
RW
7
6
5
4
3
2
1
0
Reserved
BOOTSEQVER_SEL
Reserved
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
RO
0x0
R returns
0s
5:1
0
BOOTSEQVER_SEL EEPROM boot-sequence version
Reserved
RW
0x00
0
RO
R returns
0s
表 84. RESERVED
Address Offset
0x6B
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
Reserved
RW
7
6
5
4
3
2
1
0
Reserved
Reserved
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
RO
R returns
0s
0x0
5:1
0
Reserved
Reserved
RW
RW
0x00
0
112
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表 85. LED_CTRL1_REG
Address Offset
0x6C
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
LED ON and OFF control register.
RW
7
6
5
4
3
2
1
0
Reserved
LED2_PERIOD
LED1_PERIOD
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
RO
R returns
0s
0x0
5:3
LED2_PERIOD
Period of LED2 signal:
000: LED2 OFF
001: 0.125 s
010: 0.25 s
...
RW
0x0
110: 4 s
111: 8 s
2:0
LED1_PERIOD
Period of LED1 signal:
000: LED1 OFF
001: 0.125 s
010: 0.25 s
...
RW
0x0
10: 2 s
110: 4 s
111: 8 s
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表 86. LED_CTRL2_REG1
Address Offset
0x6D
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
LED ON and OFF control register.
RW
7
6
5
4
3
2
1
0
Reserved
LED2_SEQ
LED1_SEQ
LED2_ON_TIME
LED1_ON_TIME
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:6
Reserved
RO
0x0
R returns
0s
5
4
LED2_SEQ
LED1_SEQ
When set to 1, LED2 repeats two pulse sequences: ON (ON_TIME) -
OFF (ON TIME) - ON (ON TIME) - OFF remainder of the period
When set to 0, LED2 generates one pulse: ON (ON_TIME) - OFF (ON
TIME))
RW
RW
RW
0
0
When set to 1, LED1 repeats two pulse sequence: ON (ON_TIME) - OFF
(ON TIME) - ON (ON TIME) - OFF remainder of the period.
When set to 0, LED1 generates one pulse: ON (ON_TIME) - OFF (ON
TIME))
3:2
LED2_ON_TIME
LED1_ON_TIME
LED2 ON time:
00: 62.5 ms
01: 125 ms
10: 250 ms
11: 500 ms
0x0
1:0
LED1 ON time:
00: 62.5 ms
01: 125 ms
10: 250 ms
11: 500 ms
RW
0x0
114
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
表 87. PWM_CTRL1_REG
Address Offset
0x6E
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
PWM frequency
RW
7
6
5
4
3
2
1
0
Reserved
PWM_FREQ
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:2
Reserved
Reserved bit
RO
R returns
0s
0x00
1:0
PWM_FREQ
Frequency of PWM:
00: 500 Hz
RW
0x0
01: 250 Hz
10: 125 Hz
11: 62.5 Hz
表 88. PWM_CTRL2_REG
Address Offset
0x6F
Physical Address
Instance
(RESET DOMAIN: GENERAL
RESET)
Description
Type
PWM duty cycle.
RW
7
6
5
4
3
2
1
0
FREQ_DUTY_CYCLE
BITS
FIELD NAME
DESCRIPTION
TYPE
RESET
7:0
FREQ_DUTY_CYCLE Duty cycle of PWM:
RW
0x00
00000000: 0/256
...
11111111: 255/256
表 89. SPARE_REG
Address Offset
Physical Address
Description
Type
0x70
Instance
(RESET DOMAIN: FULL RESET)
Spare functional register
RW
7
6
5
4
3
2
1
0
SPARE
BITS
FIELD NAME
SPARE
DESCRIPTION
TYPE
RESET
7:0
Spare bits
RW
0x00
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表 90. VERNUM_REG
Address Offset
Physical Address
Description
Type
0x80
Instance
(RESET DOMAIN: FULL RESET)
Silicon version number
RW
7
6
5
4
3
2
1
0
READ_BOOT
Reserved
VERNUM
BITS
FIELD NAME
READ_BOOT
DESCRIPTION
TYPE
RESET
7
This bit enables the read of the BOOT mode in order to enter JTAG
RW
0
mode.
0: Disabled
1: Enabled
6:4
3:0
Reserved
VERNUM
Reserved bit
RO
R returns
0s
0x0
0x0
Value depending on silicon version number
0000 - Revision 1.0
RO
116
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The TPS659119-Q1 device is an integrated power-management integrated circuit (PMIC) that comes in an 80-
pin, 0.5-mm pitch, LQFP package with thermal pad. This device was designed specifically for automotive
applications and is dedicated to designs powered from a 5-V input supply that require multiple power rails. The
device provides three step-down converters along with an interface to control an external converter and eight
LDO regulators. The device can support a variety of different processors and applications. Two of the step-down
converters support dynamic voltage scaling through a dedicated I2C interface to provide optimum power savings.
The third converter provides power for the I/Os and memory in the system.
In addition to the power resources, the device contains an embedded power controller (EPC) to manage the
power sequencing requirements of systems. The power sequencing is programmable through EEPROM. The
device also contains nine configurable GPIOs, a real-time clock module, an internal watchdog circuit, and two
LED ON and OFF signal generators.
Details on how to use this device in automotive applications are described throughout this device specification.
The following sections provide the typical application use-case with the recommended external components and
layout guidelines.
9.2 Typical Application
Following the typical application schematic (see 图 25) and the list of recommended external components will
allow the TPS659119-Q1 device to achieve accurate and stable regulation with the step-down converters and
LDO regulators. These devices are internally compensated and have been designed to operate most effectively
with the component values listed in 表 91. Deviating from these values is possible but is not recommended.
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Typical Application (接下页)
AGND
VCCS
VCC7
VCC1
Sw1
VDD1
C1
L1
C9
VRTC
(LDO)
VRTC
and POR
GND1
C10
C2
0.6 to 1.5 V,
12.5-mV step,
1.5 A
AGND
VFB1
OSC16MIN
C3
VCC2
SW2
Y1
VDD2
C4
16M XTAL
L2
Real
time
clock
C11
OSC16MOUT
OSCEXT32K
GND2
C12
DGND
0.6 to 1.5 V,
12.5-mV step,
1.5 A
CLK32KOUT
VFB2
VDDIO
VDDIO
VDDIO
TPS57114
EN
L3
I2C
SDA_SDI
PH
VSENSE
SCL_SCK
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
EN
EXTCTRL
C13
Bus
control
Selectable
Divider
VOUT
VSENSE
AGNDEX
1 V/V to
3/7 V/V
65 steps
GPIO5
VDDIO
GPIO6
GPIO7
GPIO8
I2C
VDDIO
VDDIO
EN1
VCCIO
SWIO
VIO
L4
C14
EN2
Power
control
state
GNDIO
INT1
SLEEP
C15
1.5, 1.8, 2.5, 3.3 V
PWRON
VFBIO
VDDIO
1.5 A
machine
BOOT1
PWRHOLD
PWRDN
LDO1
320 mA
HDRST
NRESPWRON
NRESPWRON2
LDO1
1 to 3.3 V,
C16 50-mV step
VREF
Analog
references
TESTV
VCC6
LDO2
C5
REFGND
LDO3
Watchdog
1 to 3.3 V,
50-mV step
LDO3
200 mA
1 to 3.3 V,
100-mV step
Test interface
LDO2
320 mA
C6
C17
VCC5
LDO4
LDO7
300 mA
1 to 3.3 V,
100-mV step
LDO7
1 to 3.3 V,
50-mV step
C7
LDO4
50 mA
C18
VCC3
LDO6
LDO5
300 mA
LDO5
VCC4
1 to 3.3 V,
100-mV step
1 to 3.3 V,
100-mV step
LDO6
300 mA
C8
C19
VCC8
LDO8
1 to 3.3 V,
100-mV step
LDO8
C20
300 mA
图 25. Application Schematic
118
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Typical Application (接下页)
9.2.1 Design Requirements
For this design example, use the parameters listed in 表 91.
表 91. Design Parameters
REFERENCE DESIGNATOR
COMPONENT FUNCTION
Input-supply decoupling capacitor
VRTC output capacitor
VALUE(1)
4.7 µF, 10 V
2.2 µF, 6.3 V
C1
C2
C3
Crystal load capacitors
VREF filtering capacitor
10 pF, 50 V
100 nF
C4
C5
C6
C7
C8
C16
C17
C18
C19
C20
C9
LDO output capacitors
2.2 µF, 6.3 V
C11
C14
C10
C12
C15
C13
L1
Step-down converter input capacitors
10 µF, 10 V
Step-down converter output capacitors
External-converter output capacitor
10 µF, 10 V
22 µF, 10 V (×2)
L2
Step-down converter inductors
Crystal
2.2 µH, 2.6 A
16.384 MHz
L3
L4
Y1
(1) Component minimum, maximum, or typical values are specified in the electrical-parameter section of each IP (see the External
Component Recommendation section).
9.2.2 Detailed Design Procedure
9.2.2.1 Step-down Converter Input Capacitors
All step-down converter inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 10-
V, 10-µF capacitor for each step-down converter input is recommended. Depending on the input voltage of the
step-down converter, a 6.3-V or 10-V capacitor can be used.
For optimal performance, the input capacitors should be placed as close to the step-down converter-input pins as
possible. See the Layout Guidelines section for more information about component placement.
9.2.2.2 Step-down Converter Output Capacitors
All step-down converter outputs require an output capacitor to hold up the output voltage during a load step or a
change to the input voltage. To ensure stability across the entire switching frequency range, the TPS659119-Q1
device requires an output capacitance value between 4 µF and 12 µF. To meet this requirement across
temperature and DC bias voltage, using a 10-µF capacitor for each step-down converter is recommended.
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9.2.2.3 Step-down Converter Inductors
Again, to ensure stability across the entire switching frequency range, TI recommends to use a 2.2-µH inductor
on each step-down converter. Because the maximum DC current for each step-down converter is 1.5-A,
selecting an inductor with a saturation current of at least 2.3-A is important.
9.2.2.4 LDO Input Capacitors
All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 10-V, 4.7-µF
capacitor on each LDO input voltage supply (VCC3, VCC4, VCC5, and VCC6) is recommended. Depending on
the input voltage of the LDO, a 6.3-V or 10-V capacitor can be used.
For optimal performance, the LDO input capacitors should be placed as close as possible to the LDO input pins.
See the Layout Guidelines section for more information about component placement.
9.2.2.5 LDO Output Capacitors
All LDO outputs require an output capacitor to hold up the voltage during a load step or changes to the input
voltage. Using a 6-V, 2.2-µF capacitor is recommended for each LDO.
9.2.2.6 VCC7
The VCC7 pin is the input supply for VRTC as well as the analog references of the device. This pin requires a
4.7-µF decoupling capacitor.
9.2.3 Application Curves
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIO, PFM
Vout = 2.5 V
VIO, PWM
Vout = 2.5 V
Vout = 1.8 V
Vout = 1.5 V
Vout = 1.8 V
Vout = 1.5 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
C005
C006
Load Current (A)
Load Current (A)
图 26. VIO Efficiency vs Load Current,
图 27. VIO Efficiency vs Load Current,
25°C VIN = 4 V, PFM
25°C, VOUT = 2.5 V, VIN = 4 V, PWM
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VDD1, PFM
VDD1 PWM
Vout = 2.5 V
Vout = 1.5 V
Vout = 1.2 V
Vout = 2.5 V
Vout = 1.5 V
Vout = 1.2 V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
C001
C002
Load Current (A)
Load Current (A)
图 28. VDD1 Efficiency vs Load Current,
图 29. VDD1 Efficiency vs Load Current,
25°C, VIN = 4 V, PFM
25°C, VIN = 4 V, PWM
120
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
100
90
80
70
60
50
40
30
20
10
100
90
80
70
60
50
40
30
20
10
0
VDD2, PFM
VDD2 PWM
Vout = 2.5 V
Vout = 1.5 V
Vout = 1.2 V
Vout = 2.5 V
Vout = 1.5 V
Vout = 1.2 V
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
C003
C004
Load Current (A)
Load Current (A)
图 30. VDD2 Efficiency vs Load Current,
图 31. VDD2 Efficiency vs Load Current,
25°C, VIN = 4 V, PFM
25°C, VIN = 4 V, PWM
10 Power Supply Recommendations
The TPS659119-Q1 device is designed to work with an analog supply voltage range of 4-V to 5.5-V. Typically, a
stable 5-V supply is provided to the VCC7 pin as well as the step-down converter and LDO input pins with the
appropriate bypass capacitors. If the input supply is located more than a few inches from the TPS659119-Q1
device, additional capacitance may be required in addition to the recommended input capacitors at the VCC7 pin
and the step-down converter and LDO input pins.
11 Layout
11.1 Layout Guidelines
As in every switch-mode-supply design, general layout rules apply.
•
•
•
•
Use a solid ground plane for power ground (PGND).
Use an independent ground for logic, LDOs, and analog (AGND).
Connect those grounds at a star point ideally underneath the IC.
Place the input capacitors as close as possible to the input pins of the IC.
注
This guideline is the most important and is more important than the output loop.
•
•
•
Place the inductor and output capacitor as close as possible to the phase node (or switch node) of the IC
Keep the loop area formed by the phase node, inductor, output capacitor, and PGND as small as possible.
For traces and vias on power lines, keep inductance and resistance as low as possible by using wide traces
and plane shapes. Avoid switching layers, but if needed, use plenty of vias.
The goal of the previously listed guidelines is a layout that minimizes emissions, maximizes EMI immunity, and
maintains a safe operating area of the IC.
To minimize the spiking at the phase node for both the high-side (VIN – SWx) as well as the low-side (SWx –
PGND), the decoupling of VIN is critical. Appropriate decoupling and thorough layout practices should ensure
that the spikes never exceed the absolute maximum rating of the respective pin.
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11.2 Layout Example
VDD1
Output
5-V Analog
Input Supply
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40
39
38
37
36
61
VCC1
VCC5
VCCS
62 SLEEP
63
64
65
GPIO8
LDO3
CLK32KOUT
OSCEXT32K
GPIO6
OSC16MOUT
OSC16MIN
35
66 NRESPWRON
67 VCC2
GPIO1 34
BOOT1 33
VCC2
SW2
SW2
68
69
70
32
31
GPIO5
VREF
VDD2 Output
Thermal pad
REFGND
30
GND2
GND2
GPIO7
71
72
73
74
75
PGND
HDRST 29
VFBIO
28
VFB2
INT1
GPIO4 27
GNDIO 26
PGND
VIO Output
GNDIO
25
GPIO2
LDO5
LDO5
76
77
78
79
80
SWIO
SWIO
24
23
22
21
VCC4
VCC8
VCCIO
VCCIO
5-V Analog
Input Supply
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20
图 32. TPS659119-Q1 Layout Example
122
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ZHCSCN5E –MARCH 2013–REVISED SEPTEMBER 2014
12 器件和文档支持
12.1 器件支持
12.1.1 器件命名规则
表 92. 首字母缩写词、缩略语和定义
首字母缩写词
DDR
ES
定义
双倍数据速率(存储器)
工程样品
ESD
FET
静电放电
场效应晶体管
嵌入式电源控制器
有限状态机
EPC
FSM
GND
GPIO
HBM
HD
接地
通用 I/O
人体模型
热模
高速 I2C
HS-I2C
I2C
内部集成电路
集成电路
IC
ID
标识
IDDQ
IEEE
IR
静态电源电流
电气电子工程师协会
指令寄存器
I/O
输入/输出
JEDEC
JTAG
LBC7
LDO
LP
联合电子器件工程设计委员会
联合测试行动组
Lin Bi-CMOS 7 (360nm)
低压降线性稳压器
低功耗应用模式
最低有效位
LSB
MMC
MOSFET
NVM
OD
多媒体卡
金属氧化物半导体场效应晶体管
非易失性内存
开漏
OMAP™
RTC
SMPS
SPI
开放式多媒体应用平台™
实时时钟
开关模式电源
串行外设接口
上电复位中添加了 T659119KB 器件标识信息
POR
12.2 商标
OMAP is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
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12.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
13 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本,请查阅左侧的导航栏。
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Copyright © 2014, 德州仪器半导体技术(上海)有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS659119AIPFPRQ1
TPS659119BAIPFPRQ1
TPS659119CAIPFPRQ1
TPS659119DAIPFPRQ1
TPS659119EAIPFPRQ1
TPS659119FAIPFPRQ1
TPS659119HAIPFPRQ1
TPS659119KBIPFPRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
PFP
PFP
PFP
PFP
PFP
PFP
PFP
PFP
80
80
80
80
80
80
80
80
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
T659119A1
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
T659119BA
T659119CA
T659119DA
T659119EA
T659119FA
T659119HA
T659119KB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS659119AIPFPRQ1
HTQFP
PFP
PFP
PFP
PFP
PFP
PFP
PFP
PFP
80
80
80
80
80
80
80
80
1000
1000
1000
1000
1000
1000
1000
1000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
24.4
24.4
24.4
24.4
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
15.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
24.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
TPS659119BAIPFPRQ1 HTQFP
TPS659119CAIPFPRQ1 HTQFP
TPS659119DAIPFPRQ1 HTQFP
TPS659119EAIPFPRQ1 HTQFP
TPS659119FAIPFPRQ1 HTQFP
TPS659119HAIPFPRQ1 HTQFP
TPS659119KBIPFPRQ1 HTQFP
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS659119AIPFPRQ1
TPS659119BAIPFPRQ1
TPS659119CAIPFPRQ1
TPS659119DAIPFPRQ1
TPS659119EAIPFPRQ1
TPS659119FAIPFPRQ1
TPS659119HAIPFPRQ1
TPS659119KBIPFPRQ1
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
PFP
PFP
PFP
PFP
PFP
PFP
PFP
PFP
80
80
80
80
80
80
80
80
1000
1000
1000
1000
1000
1000
1000
1000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
55.0
55.0
55.0
55.0
55.0
55.0
55.0
55.0
Pack Materials-Page 2
www.ti.com
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