TPS6591286_技术文档

TPS659128

SLVSGB7A – MAY 2021 – REVISED JUNE 2021

TPS659128 PMU for Processor Power

1 Features

3 Description

•

Four step-down converters:

The TPS659128x device provides four configurable

step-down converters with up to 2.5-A output current

and ten LDO regulators for external use. These

LDOs can be supplied from either a battery or a

preregulated supply. Each specific part number has

a different factory programmed power-up and power-

down sequence.

– Input voltage (V_IN) range from 2.7 V to 5.5 V

– Power save mode at light load current

– Output voltage accuracy in PWM mode ±2%

– Typical 26-μA quiescent current per converter

– Dynamic voltage scaling

– 100% duty cycle for lowest dropout

Ten LDOs:

•

The TPS659128x device integrates a 32-kHz RC

oscillator to sequence all resources during power up

or power down. All LDOs and DC-DC converters

can be controlled by an I²C or SPI interface or

basic enable pins after boot. Additionally, a voltage-

scaling interface allows for transitioning the DC-DC

converters to a different voltage through I²C or basic

roof-floor control. Three LED drivers with an advanced

dimming feature are integrated inside the device.

General-purpose input-output (GPIO) functionality is

multiplexed with various pins, including LED pins,

ENx pins, and SPI pins when not used. Each

GPIO can be configured as part of the power-up

sequence to control external resources. One SLEEP

pin enables switching between the active mode and

preprogrammed sleep mode for power optimization.

The TPS659128x device comes in a 9-pin × 9-pin

DSBGA package (3.6 mm × 3.6 mm) with a 0.4-mm

pitch.

– 8 general-purpose LDOs

– Output voltage range from 0.8 V to 3.3 V

– Typical 32-μA quiescent current per LDO

– 2 low-noise RF-LDOs

– Output voltage range from 1.6 V to 3.3 V

– Preregulation support by separate power inputs

– Eco-mode^™control scheme

– V_INrange of LDOs respective to the following

voltage ranges:

•

1.8 V to 3.6 V

3 V to 5.5 V

•

Three LED drivers:

– Internal dimming using I²C

– Up to 20 mA per current sink

Thermal monitoring

– High temperature warning

– Thermal shutdown

Bypass switch

Device Information⁽¹⁾

– Used with DCDC4 in applications powering a

Radio Frequency Power Amplifier (RF-PA)

Interface

PART NUMBER

PACKAGE

BODY SIZE

TPS6591286

TPS6591287

– I²C interface

DSBGA (81)

3.60 mm × 3.60 mm

– Power I²C interface for Dynamic Voltage

Scaling (DVS)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

– Serial Peripheral Interface (SPI)

32-kHz RC oscillator

Undervoltage lockout, battery fault comparator,

and long button-press detection

3.6-mm × 3.6-mm DSBGA package with 0.4-mm

pitch

•

2 Applications

•

Smart phones

Wireless routers and switches

Tablets

Industrial applications

LTE modem

GPS

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS659128

SLVSGB7A – MAY 2021 – REVISED JUNE 2021

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 7

6.1 Absolute Maximum Ratings........................................ 7

6.2 ESD Ratings............................................................... 7

6.3 Recommended Operating Conditions.........................8

6.4 Thermal Characteristics..............................................9

6.5 Electrical Characteristics – DCDC1, DCDC2,

and DCDC3...................................................................9

6.6 Electrical Characteristics – DCDC4.......................... 11

6.7 Electrical Characteristics – LDOs............................. 12

6.8 Electrical Characteristics – Digital Inputs, Digital

Outputs........................................................................15

6.9 Electrical Characteristics – VMON Voltage

7 Parameter Measurement Information..........................24

7.1 I²C Timing Diagrams.................................................24

7.2 SPI Timing Diagram..................................................25

8 Detailed Description......................................................26

8.1 Overview...................................................................26

8.2 Functional Block Diagram.........................................27

8.3 Feature Description...................................................28

8.4 Device Functional Modes..........................................31

8.5 Register Maps...........................................................60

9 Application and Implementation................................145

9.1 Application Information........................................... 145

9.2 Typical Application.................................................. 145

10 Layout.........................................................................155

10.1 Layout Guidelines................................................. 155

10.2 Layout Example.................................................... 156

11 Power Supply Recommendations............................157

12 Device and Documentation Support........................158

12.1 Device Support..................................................... 158

12.2 Documentation Support........................................ 158

12.3 Receiving Notification of Documentation Updates158

12.4 Support Resources............................................... 158

12.5 Trademarks...........................................................158

12.6 Electrostatic Discharge Caution............................158

12.7 Glossary................................................................158

13 Mechanical, Packaging, and Orderable

Monitor, VDDIO, Undervoltage Lockout (UVLO),

and LDOAO.................................................................15

6.10 Electrical Characteristics – Load Switch.................16

6.11 Electrical Characteristics – LED Drivers................. 16

6.12 Electrical Characteristics – Thermal Monitoring

and Shutdown............................................................. 16

6.13 Electrical Characteristics – 32-kHz RC Clock.........17

6.14 SPI Timing Requirements....................................... 17

6.15 I²C Interface Timing Requirements.........................17

6.16 Typical Characteristics............................................19

Information.................................................................. 159

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (May 2021) to Revision A (June 2021)

Page

•

Changed TPS6591287 from PREVIEW to ACTIVE........................................................................................... 1

2

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5 Pin Configuration and Functions

Figure 5-1 shows the 81-pin YFF Die-Size Ball-Grid Array pin assignments.

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

VLDO7

VINLDO67

VLDO6

VDCDC4

PGND4

SW4

VINDCDC4

LSO

LEDC/GPIO5 LEDB/GPIO4 LEDA/GPIO3 VDCDC4_GND

PGND4

SW4

VINDCDC4

LSI

VINDCDC2

SW2

EN4/DCDC4 EN3/DCDC3

_SEL _SEL

VINDCDC

_ANA

VINDCDC3

EN_LS1

CONFIG2

CONFIG1

VDCDC3

EN_LS0

nPWRON

DGND

GPIO2__CE

GPIO1_MISO

SDA_MOSI

AGND

EN2/DCDC2

_SEL

SW3

SCL_SCK PWRHOLD_ON VDCDC2

SCL_AVS

/CLK_REQ1

SDA_AVS

/CLK_REQ2

DEF_SPI

_I2C-GPIO

EN1/DCDC1

_SEL

PGND3

VINLDO4

VLDO4

PGND2

VLDO3

VLDO5

VLDO8

OMAP_WDI

_32k_OUT

AGND

VCON_PWM VCON_CLK

VDDIO

VINLDO3

VINLDO5

VINLDO8

VINLDO9

nRESPWRON/

VSUP_OUT

VCCS/VIN

_MON

SLEEP/PWR

INT1

G

H

J

LDOAO

CPCAP_WDI

VINDCDC1

_REQ

VLDO2

VCC

VREF1V25 VDCDC1_GND

PGND1

SW1

VLDO10

VINLDO1210

VLDO1

VDCDC1

VLDO9

Not to scale

Figure 5-1. 81-Pin YFF DSBGA (Bottom View)

Table 5-1. Pin Functions

I/O

DESCRIPTION

NAME

REFERENCE

ALT NAME

NO.

Internal reference voltage. Connect a 100-nF capacitor from this pin to

AGND. Do not load this pin externally.

VREF1V25

—

H3

O

Analog-ground (AGND) connection. Connect this pin to the power-

ground (PGND) plane on the printed circuit board (PCB).

AGND

F3, C7

—

DRIVERS AND LIGHTING

LEDA/GPIO3

—

B3

I/O

General-purpose I/O or LED driver output

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Table 5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

LEDB/GPIO4

ALT NAME

NO.

—

B2

B1

I/O

General-purpose I/O or LED driver output

LEDC/GPIO5

STEP-DOWN CONVERTERS

Analog supply input for the DC-DC converters. This pin must

be connected to the VINDCDC1, VINDCDC2, VINDCDC3 and

VINDCDC4 pins.

VINDCDC_ANA

—

C8

I

Power input to the DCDC1 converter. Connect this pin to the

VINDCDC2, VINDCDC3, VINDCDC4, and VINDCDC_ANA pins.

VINDCDC1

VDCDC1

—

H7, J7

J4

I

Remote positive voltage sense (feedback) input for the DCDC1

converter

Remote negative voltage sense (feedback) input for DCDC1. Tie this

pin to the GND plane or to the AGND plane. Alternatively, tie this pin

to the GND pad of the output capacitor.

VDCDC1_GND

—

H4

I

Switch node of the DCDC1 converter. Connect this pin to the output

inductor.

SW1

—

H6, J6

H5, J5

F4

O

—

I

PGND1

Power GND connection for the DCDC1 converter

Pulse-width modulation (PWM) period signal for dynamic voltage

scaling on the DCDC1 converter if using VCON

VCON_PWM

Clock signal for dynamic voltage scaling on the DCDC1 converter if

using VCON

VCON_CLK

—

F5

I

Power input to the DCDC2 converter. Connect this pin to the

VINDCDC1, VINDCDC3, VINDCDC4, and VINDCDC_ANA pins.

VINDCDC2

VDCDC2

SW2

—

C9

D7

I

Remote voltage sense (feedback) input for the DCDC2 converter

Switch node of the DCDC2 converter. Connect this pin to the output

inductor.

D9

O

—

I

PGND2

E9

Power GND connection for the DCDC2 converter

Power input to the DCDC3 converter. Connect this pin to the

VINDCDC1, VINDCDC2, VINDCDC4, and VINDCDC_ANA pins.

VINDCDC3

VDCDC3

SW3

C1

F2

I

Remote voltage sense (feedback) input for the DCDC3 converter

Switch node of the DCDC3 converter. Connect this pin to the output

inductor.

D1

O

—

I

PGND3

E1

Power GND connection for the DCDC3 converter

Power input to the DCDC4 converter. Connect this pin to the

VINDCDC1, VINDCDC2, VINDCDC3, and VINDCDC_ANA pins.

VINDCDC4

A7, B7

Remote positive voltage sense (feedback) input for the DCDC4

converter

VDCDC4

VDCDC4_GND

SW4

—

A4

B4

I

Remote negative voltage sense (feedback) input the DCDC4

converter. Tie this pin to the GND plane or to the AGND plane.

Alternatively, tie this pin to the GND-pad of the output capacitor.

Switch node of the DCDC4 converter. Connect this pin to the output

inductor.

—

A6, B6

A5, B5

O

PGND4

LOAD SWITCH

LSI

—

Power GND connection for the DCDC4 converter

—

B8, B9

A8, A9

I

Input of the load switch

Output of the load switch

LSO

O

Load switch enable pin. The status of this pin is copied to the

ENABLE0 bit in the LOADSWITCH register in the CONFIG state.

EN_LS0

EN_LS1

—

C3

C2

I

Load switch enable pin. The status of this pin is copied to the

ENABLE1 bit in the LOADSWITCH register in the CONFIG state.

LOW-DROPOUT REGULATORS

VINLDO1210

—

J2

I

Power input for the LDO1, LDO2, and LDO10 regulators

4

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Table 5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

ALT NAME

NO.

VINLDO3

VINLDO4

VINLDO5

VINLDO67

VINLDO8

VINLDO9

—

F8

F1

G8

A2

H8

J8

I

Power input for the LDO3 regulator

Power input for the LDO4 regulator

Power input for the LDO5 regulator

Power input for the LDO6 and LDO7 regulators

Power input for the LDO8 regulator

Power input for the LDO9 regulator

LDO always on internal supply. Connect this pin to the buffer

capacitor.

LDOAO

—

G3

O

VLDO1

VLDO2

—

J3

H1

F9

G1

G9

A3

A1

H9

J9

O

LDO1 output

LDO2 output

LDO3 output

LDO4 output

LDO5 output

LDO6 output

LDO7 output

LDO8 output

LDO9 output

LDO10 output

VLDO3

VLDO4

VLDO5

VLDO6

VLDO7

VLDO8

VLDO9

VLDO10

J1

STANDARD INTERFACE

Digital input that defines whether SPI is available or I²C and GPIOs

are available on the C4, D4, E4, D5 pins. Shorting this pin to GND

selects SPI. Shorting this pin to LDOAO selects I²C, and GPIO1 and

GPIO2

DEF_SPI_I2C-GPIO

—

E7

I

SCL_SCK

SCK

D5

E4

I

I²C SCL or SPI SCK based on DEF_SPI_I2C-GPIO

I²C SDA or SPI master-out slave-in device (MOSI) based on

DEF_SPI_I2C-GPIO

SDA_MOSI

MOSI

I/O

GPIO1 or SPI master-out slave-in device (MISO) based on

DEF_SPI_I2C-GPIO

GPIO1_MISO

GPIO2_ CE

MISO

CE

D4

C4

I/O

GPIO2 or SPI chip enable (CE) active high based on DEF_SPI_I2C-

GPIO

ENABLE AND VOLTAGE SCALING

Enable pin for EN1_SETx assigned resources or voltage-scaling pin

that changes the output of a converter or a group of converters

between two predefined values

EN1/DCDC1_SEL⁽¹⁾

EN2/DCDC2_SEL⁽¹⁾

EN3/DCDC3_SEL⁽¹⁾

EN4/DCDC4_SEL⁽¹⁾

SCL_AVS/CLK_REQ1⁽²⁾

DCDC1_SEL

E8

D8

C6

C5

E5

I

Enable pin for EN2_SETx assigned resources or voltage-scaling pin

that changes the output of a converter or a group of converters

between two predefined values

DCDC2_SEL

DCDC3_SEL

DCDC4_SEL

CLK_REQ1

Enable pin for EN3_SETx assigned resources or voltage-scaling pin

that changes the output of a converter or a group of converters

between two predefined values

Enable pin for EN4_SETx assigned resources or voltage-scaling pin

that changes the output of a converter or a group of converters

between two predefined values

Clock pin of power I²C for dynamic voltage scaling or clock request

input signal 1 used to enable and disable power resources using

EN2_SETx registers.

Data pin of power I²C for dynamic voltage scaling or clock request

input signal 2 used to enable and disable power resources using

EN3_SETx registers.

SDA_AVS/CLK_REQ2⁽²⁾

SLEEP/PWR_REQ⁽²⁾

CLK_REQ2

PWR_REQ

E6

G4

I/O

I

SLEEP state request input or power request input signal used to

enable and disable power resources using EN1_SETx registers.

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Table 5-1. Pin Functions (continued)

I/O

DESCRIPTION

NAME

ALT NAME

NO.

Active low reset output to disable processor until power-up sequence

completes or the output of the input voltage monitor

nRESPWRON/VSUP_OUT

VSUP_OUT

G6

O

VCCS/VIN_MON

PWRHOLD_ON

INT1

VIN_MON

G2

D6

G5

I

Voltage sense for input voltage monitoring

POWERHOLD or ON. This pin is an enable input.

Interrupt output

ON

—

O

Active-low, debounced power-on input or power-request input to start

the power-up sequencing. Alternatively, this pin is the active-low reset

input to the PMIC that is debounced by 10 ms (OTP option). Tie this

pin to the LDOAO pin for a logic high if not used.

nRESIN (OTP

option)

nPWRON

D3

I

Always used as 32KCLKOUT. Leave this pin floating if not using

32KCLKOUT.

OMAP_WDI_32k_OUT

CPCAP_WDI

32KCLKOUT

—

F6

O

G7

—

No connect, leave this pin floating.

Selects the predefined startup options and default voltages. Use this

pin to choose from two internal OTP settings. Tie this pin to GND or

the LDOAO pin.

CONFIG1

—

E2

D2

I

Selects between two device modes. With the CONFIG2 tied to

LDOAO, the primary functions of the pins (ENx, SCL_AVS, SDA_AVS,

and SLEEP) and SLEEP state is usable. With the CONFIG2 tied

to GND, the alternate functions of the pins are used (DCDCx_SEL,

CLK_REQx, and PWR_REQ) and SLEEP state is not used.

CONFIG2

—

VCC

—

H2

F7

I

Digital supply input

Supply voltage input for GPIOs and output stages that sets the high-

level voltage (I/O voltage)

VDDIO

Digital GND connection. Tie this pin to the AGND and PGNDx on the

PCB.

DGND

—

E3

–

(1) The DCDCx_SEL pin function is selected by pulling the CONFIG2 pin to GND which also selects the CLK_REQx and PWR_REQ pin

functions as enable resources.

(2) The CLK_REQ1, CLK_REQ2, and PWR_REQ pin functions are selected by puling the CONFIG2 pin to GND.

6

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

UNIT

All pins except AGND pins, PGND pins, and pins listed below with respect

to AGND

–0.3

6

VLDO1, VLDO2, VLDO3, VLDO4, VLDO5, VLDO6, VLDO7, VLDO8,

VLDO9, VLDO10, VINLDO1210, VINLDO3, EN1/DCDC1_SEL, EN2/

DCDC2_SEL, EN3/DCDC3_SEL, EN4/DCDC4_SEL, SLEEP/PWR_REQ,

CLK_REQ1, CLK_REQ2, VDDIO, CONFIG1, CONFIG2, DEF_SPI_I2C-

GPIO, EN_LS0, EN_LS1, OMAP_WDI, CPCAP_WDI, VCON_CLK with

–0.3

3.6

Voltage

V

respect to AGND

VDCDC1, VDCDC2, VDCDC3, VDCDC4 with respect to AGND

–0.3

3.8

SDA_SDI, SCL_CLK, GPIO1_MISO, GPIO1_CE, SDA_AVS, SCL_AVS,

INT1, 32KCLKOUT, GPIO3 and GPIO4 and GPIO5 if defined as GPIOs with

push-pull output (otherwise it is 6-V rated), nRESPWRON if nRESPWRON

is push-pull output (otherwise it is 6-V rated) with respect to AGND

VDDIO + 0.3

V_CC

VDDIO

6

5

All non-power pins

Power pins (per pin)

mA

A

Current

2

Operating free-air temperature, T_A

Maximum junction temperature, T_J

Storage temperature, T_stg

–40

–65

85

125

150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions (Section 6.3) is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect

device reliability.

6.2 ESD Ratings

VALUE

1000

250

UNIT

V

Human body model (HBM), per ANSI/ESDA/JEDEC JS001⁽¹⁾

Charged device model (CDM), per JESD22-C101⁽²⁾

V_ESD

Electrostatic discharge

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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MAX UNIT

SLVSGB7A – MAY 2021 – REVISED JUNE 2021

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

DC-DC CONVERTERS

VIN1, VIN2,

Input voltage for step-down converter DCDC1, DCDC2, DCDC3, DCDC4

VIN3, VIN4

2.7

5.5

V

Output voltage for step-down converter DCDC1, DCDC2, DCDC3, DCDC4⁽¹⁾

0.5

10

3.8

1.3

V

Inductance at L1, L2, L3, L4

1

22

10

22

μH

μF

C_IN1, C_IN4

C_IN2, C_IN3

C_OUTDCDC1,2,3

C_OUTDCDC4

LDOs

Input capacitance at VIN1 and VIN4 (on each pin)

Input capacitance at VIN2 and VIN3 (on each pin)

Output capacitance at DCDC1, DCDC2 and DCDC3

Output capacitance at DCDC4

4.7

10

22

47

VINLDO1210

VINLDO4

Input voltage for LDO1, LDO2 and LDO10

Input voltage for LDO4

1.7

1.9

3.6

5.5

V

VINLDO5

Input voltage for LDO5

V_LDO1, V_LDO2,

V_LDO3

V_{LDO6 ,}

V_LDO7,V_{LDO8 ,}

V_LDO9,V_LDO10

,

Output voltage for general purpose (GP) LDOs⁽¹⁾

Output voltage for RF-LDOs

0.8

1.6

3.3

V

V_LDO4,V_LDO5,

C_INLDO1210

C_INLDO3,

C_INLDO4,

C_INLDO5,

C_INLDO67,

C_INLDO8,

C_INLDO8

,

Input capacitance on LDO supply pins

Output capacitance on LDO4 and LDO5

0.5

μF

C_OUTDO4,

C_OUTLDO5

2.2

0.5

1

10

μF

C_OUTLDO1,

C_OUTLDO2,

C_OUTLDO3,

C_OUTLDO6,

C_OUTLDO7,

C_OUTLDO8

Output capacitance LDO1, LDO2, LDO3, LDO6, LDO7, LDO8

These LDOs are capless, the required capacitance can be placed at the load

C_OUTLDO9,

C_OUTLDO10

Output capacitance LDO9 and LDO10

These LDOs are capless, the required capacitance can be placed at the load

10

C_OUTLDOAO

C_{VINDCDC_ANA}

C_VCC

Output capacitance on LDOAO

Input capacitance on VINDCDC_ANA

Input capacitance on VCC

0.5

100

–40

μF

nF

°C

C_VDDIO

C_VREF

Input capacitance on VDDIO

Output capacitance on VREF1V25

Operating ambient temperature

Operating junction temperature

T_A

85

T_J

125

(1) The maximum output voltage of DCDC1 to DCDC4 and LDO1 to LDO4 can be reduced by an OTP setting to adopt the maximum

voltage to the requirements (or maximum ratings) of the load powered. This setting helps protect the processor from exceeding the

maximum ratings for the core voltage. The value is set in nonvolatile memory (OTP) by TI upon customer request with sufficient

business case.

8

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6.4 Thermal Characteristics

TPS659128

THERMAL METRIC⁽¹⁾

YFF (DSBGA)

UNIT

81 PINS

41.3

0.1

R_θJA

R_θJCtop

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

Junction-to-board thermal resistance

5.2

Junction-to-top characterization parameter

Junction-to-board characterization parameter

0.7

ψ_JB

5.2

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics – DCDC1, DCDC2, and DCDC3

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

2.3

0.5

0.7

0.5

TYP

MAX UNIT

V_IN

Input voltage range

5.5

1.2875

1.4875

2.075

3.80

V

Option1; in 12.5-mV steps; RANGE[1:0] = 00b

Option2; in 12.5-mV steps; RANGE[1:0] = 01b

Option3; in 25-mV steps; RANGE[1:0] = 10b

Option4; in 50-mV steps; RANGE[1:0] = 11b

DCDC1 (VINDCDC1 ≥ 2.8 V)

V_DCDC1

V_DCDC2

V_DCDC3

DCDCx output

voltage Range

2500

750

DCDC2 (VINDCDC2 ≥ 2.8 V)

Continuous output

current

I_OUT(DCDCx)

mA

DCDC3 (VINDCDC3 ≥ 2.8 V)

1200

1600

DCDC3 for 2.8 V ≤ V_IN≤ 4.5 V; VDCDC3(max) = 1.4875 V

I_LOAD= 0 mA, DCDCx_MODE = 0b, Device not switching,

for DCDC1

26

8

55

μA

mA

μA

mA

μA

I_LOAD= 0 mA, DCDCx_MODE = 1b, Device switching, for

DCDC1

I_LOAD< 1 mA, Device not switching, ECO = 1b AND

DCDCx_MODE = 0b, for DCDC1

9

I_Q

Quiescent current

I_LOAD= 0 mA, DCDCx_MODE = 0b, Device not switching,

for DCDC2 or DCDC3

26

8

40

I_LOAD= 0 mA, DCDCx_MODE = 1b, Device switching, for

DCDC2 or DCDC3

I_LOAD< 1 mA, Device not switching; ECO = 1b AND

DCDCx_MODE = 0b, for DCDC2 or DCDC3

3

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6.5 Electrical Characteristics – DCDC1, DCDC2, and DCDC3 (continued)

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

DCDCx_MODE = 1b, VINDCDCx = 3.6 V, I_LOAD= 0 mA,

T_A= 25°C, ECO = 0

–2%

DCDCx_MODE = 1b, VINDCDCx = 3.6 V, I_LOAD= 0 mA,

–40°C ≤ T_A≤ 85°C, ECO = 0

Accuracy

–2.5%

–3%

DCDCx_MODE = 0b, VINDCDCx = 3.6 V, I_LOAD= 0 mA,

T_A= 25°C, ECO = 0

VINDCDCx = 3.6 V, I_LOAD= 0 mA, –40°C ≤ T_A≤ 85°C;

ECO = 1b AND DCDCx_MODE = 0b

ECO mode accuracy

–5%

5%

DCDCx_MODE = 1b, VINDCDCx = 3.6 V, 120 mA ≤ I_LOAD

≤ 1080 mA, for DCDC1

V_DCDC1/2/3

0.01

DCDCx_MODE = 1b, VINDCDCx = 3.6 V, 120 mA ≤ I_LOAD

≤ to 1080 mA, for DCDC3

Load regulation

%/A

DCDCx_MODE = 1b, VINDCDCx = 3.6 V, 50 mA ≤ I_LOAD

450 mA, for DCDC2

≤

DCDCx_MODE = 1b, 2.5 V ≤ VINDCDCx ≤ 5.5 V, I_LOAD

0 mA, for DCDC1

=

Line regulation

%/V

DCDCx_MODE = 1b, 2.5 V ≤ VINDCDCx ≤ 5.5 V, I_LOAD

0 mA, for DCDC2 or DCDC3

=

DCDCx_MODE = 0b

3500 kHz

kHz

f_SW

Switching frequency

DCDCx_MODE = 1b, VINDCDCx = 3.6 V, VDCDCx = 1.8

V

2800

60

for DCDC1 with VINDCDCx = 3.6 V, D = 100%

100

190

100

160

20

mΩ

High-side FET on-

resistance

R_DS(ON)

I_{LK_HS}

I_{LK_LS}

for DCDC2 and DCDC3 with VINDCDCx = 3.6 V, D =

100%

120

60

for DCDC1 with VINDCDCx = 3.6 V, D = 100%

Low-side FET on-

resistance

for DCDC2 and DCDC3 with VINDCDCx = 3.6 V, D =

100%

100

T_J= 85°C, DCDC1, VINDCDC1 = 4.2 V

High-side FET

leakage current

μA

T_J= 85°C, DCDC2 or DCDC3, VINDCDC2 = VINDCDC3 =

4.2 V

3

T_J= 85°C, DCDC1, VINDCDC1 = 4.2 V

20

Low-side FET

leakage current

T_J= 85°C, DCDC2 or DCDC3, VINDCDC2 = VINDCDC3 =

4.2 V

1

VINDCDC1 = 3.6 V, DCDC1

VINDCDC2 = 3.6 V, DCDC2

VINDCDC3 = 3.6 V, DCDC3

VINDCDC1 = 3.6 V, DCDC1

VINDCDC2 = 3.6 V, DCDC2

VINDCDC3 = 3.6 V, DCDC3

3200

1250

2100

3200

1200

1875

4280

1667

2800

4280

1600

2500

5300

2083

3500

5300

2000

3125

High-side forward

current limit

I_{HS_LIMF}

mA

Low-side forward

current limit

I_{LS_LIMF}

mA

ns

Minimum high-side

FET off time

t_OFF(MIN)

VINDCDCx = 3.6 V

30

VDCDCx falling

VDCDCx rising

86%

90%

94%

98%

Power-good

threshold

V_DCDCPG

Power-good

threshold deglitch

time

t_DCDCPG

1

ms

μs

Time to start switching, measured from end of I²C

command enabling converter

t_Start

Start-up time

32

55

100

t_Ramp

V_OUTramp up time

Discharge resistor

Time to ramp from 5% to 95% of VDCDCx

100

250

160

400

250

500

μs

Ω

R_Discharge

10

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6.5 Electrical Characteristics – DCDC1, DCDC2, and DCDC3 (continued)

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

MAX UNIT

PWM clock period for

VCON_CLK

T_pwm

30

300

ns

T_su

T_hd

VCON setup time

VCON hold time

VCON_PWM to rising edge of VCON_CLK

VCON_PWM from rising edge of VCON_CLK

7

ns

6.6 Electrical Characteristics – DCDC4

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

2.3

0.5

0.7

0.5

TYP

MAX UNIT

V_IN

Input voltage range

5.5

1.2875

1.4875

2.075

3.80

V

Option1, in 12.5-mV steps, RANGE[1:0] = 00b

Option2, in 12.5-mV steps, RANGE[1:0] = 01b

Option3, in 25-mV steps, RANGE[1:0] = 10b

Option4, in 50-mV steps, RANGE[1:0] = 11b

DCDC4 output voltage

range

V_DCDC4

V

I_OUT(DCDC4)Continuous output current DCDC4 (VINDCDC4 ≥ 2.8 V)

I_LOAD= 0 mA, DCDC4_MODE = 0b, Device not switching

2500

55

mA

μA

26

8

I_LOAD= 0 mA, DCDC4_MODE = 1b, Device switching,

EN_LS[1:0] = 00 or 01

mA

μA

I_Q

Quiescent current

I_LOAD< 1 mA, Device not switching, ECO = 1b AND

DCDC4_MODE = 0b

9

DCDC4_MODE = 1b, VINDCDC4 = 3.6 V, I_LOAD= 0 mA,

T_A= 25°C, EN_LS[1:0] = 00b or 01b

–2%

–2.5%

–3%

2%

2.5%

3%

DCDC4_MODE = 1b, VINDCDC4 = 3.6 V, I_LOAD= 0 mA,

–40°C ≤ T_A≤ 85°C, EN_LS[1:0] = 00b or 01b

Accuracy

DCDC4_MODE = 0b, VINDCDC4 = 3.6 V, I_LOAD= 0 mA,

T_A= 25°C

DCDC4_MODE = 0b, VINDCDC4 = 3.6 V, I_LOAD= 0 mA,

–40°C ≤ T_A≤ 85°C

V_DCDCx

–3%

3%

ECO = 1b AND DCDCx_MODE = 0b, VINDCDC4 = 3.6

V, I_LOAD= 0 mA, –40°C ≤ T_A≤ 85°C

ECO mode accuracy

Load regulation

Line regulation

–5%

5%

DCDC4_MODE = 1b, VINDCDC4 = 3.6 V, EN_LS[1:0] =

00b or 01b, 250 mA ≤ I_LOAD≤ 2250 mA

0.01

%/A

%/V

DCDC4_MODE = 1b, 2.5 V ≤ VINDCDC4 ≤ 5.5 V, I_LOAD

0 mA, EN_LS[1:0] = 00b or 01b

=

DCDC4_MODE = 0b

3500 kHz

kHz

f_SW

Switching frequency

DCDC4_MODE = 1b, VINDCDC4 = 3.6 V, VDCDC4 = 1.8

V, EN_LS[1:0] = 00b or 01b

2800

60

High-side MOSFET on-

resistance

VINDCDC4 = 3.6 V, 100% duty cycle

VINDCDC4 = 3.6 V, 0% duty cycle

100

mΩ

R_DS(ON)

Low-side MOSFET on-

resistance

60

I_{LK_HS}

I_{LK_LS}

I_LIM

High-side leakage current

Low-side leakage current

High-side current limit

Low-side current limit

T_J= 85°C, VINDCDC4 = 4.2 V

2.9 V ≤ VINDCDC4 ≤ 5.5 V

20

μA

3000

4400

3700

5000

4300

mA

I_LIM

Minimum high-side FET off

time

t_OFF(MIN)

VINDCDC4 = 3.6 V

30

ns

VDCDC4 falling

VDCDC4 rising

86%

90%

94%

98%

V_DCDCPG

Power good threshold

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6.6 Electrical Characteristics – DCDC4 (continued)

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

t_DCDCPG

Power good deglitch time

1

ms

RAMP_TIME = 0b, Time to start switching, measured

from end of I²C command enabling converter

32

4

55

7

100

μs

t_Start

Start-up time

RAMP_TIME = 1b, Time to start switching, measured

from end of I²C command enabling converter

14

RAMP_TIME = 0b, Time to ramp from 5% to 95% of

VDCDC4,

VDCDC4 = 3.4 V

106

160

250

μs

t_Ramp

V_OUTramp-up time

Discharge resistor

RAMP_TIME = 1b, Time to ramp from 5% to 95% of

VDCDC4,

25

40

66

VDCDC4 = 3.4 V

R_Discharge

Vbyp-on

250

400

500

Ω

Bypass mode turnon duty

cycle

For ENABLE[1:0] = 10b, turnon is based on the duty

cycle of the PWM signal of DCDC4

90% 97.5% 99.5%

Bypass mode turnoff output For ENABLE[1:0] = 10b, turnoff is based on output

voltage threshold voltage above the nominal value

Vbyp-off

8%

12%

15%

6.7 Electrical Characteristics – LDOs

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

1.7

1.9

1.8

1.7

TYP

MAX UNIT

LDO1

LDO2

LDO3

LDO4

LDO5

LDO6

LDO7

LDO8

LDO9

LDO10

3.6

5.5

V

5.5

V_IN

Input voltage

5.5

3.6

LDO output voltage for

general-purpose LDOs⁽¹⁾

0.8

1.6

3.3

V

LDO output voltage for

RF_LDOs

V_LDOx

ECO = 0b

ECO = 1b

LDO1

–2%

–5%

100

250

100

300

100

300

2.5%

5%

LDO voltage accuracy

LDO2

LDO3

LDO4

LDO5

I_OUT(LDOx

LDO continuous output current

mA

)

LDO6

LDO7

LDO8

LDO9

LDO10

12

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6.7 Electrical Characteristics – LDOs (continued)

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITION

LDO1, LDO2, LDO3, LDO6, LDO8

LDO4, LDO5

MIN

100

250

300

TYP

MAX UNIT

420

650

mA

750

I_SHORT(LD

LDO current limit

Ox)

LDO7

LDO9, LDO10

750

500

200

I_OUT(LDO1)= 50 mA, VINLDO1 = 1.7 V

I_OUT(LDO2)= 100 mA, VINLDO2 = 1.7 V

I_OUT(LDO3)= 80 mA, VINLDO3 = 1.5 V

I_OUT(LDO4)= 200 mA, VINLDO4 = 2.0 V

I_OUT(LDO5)= 200 mA, VINLDO5 = 3.0 V

I_OUT(LDO6)= 100 mA, VINLDO6 = 3.2 V

I_OUT(LDO7)= 200 mA, VINLDO7 = 3.2 V

I_OUT(LDO8)= 100 mA, VINLDO8 = 2.9 V

I_OUT(LDO9)= 300 mA (LDO9), VINLDO9 = 3.1 V

I_OUT(LDO10)= 300 mA (LDO10), VINLDO10 = 2 V

V_IN= V_LDO+ 0.5 V and I_LOAD= 50 mA

300

mV

200

V_DO(LDOx

Dropout voltage⁽²⁾

)

200

1%

Line regulation

Load regulation;

–1%

LDO1, LDO2, LDO3, LDO6, LDO8: ECO = 0b, 1 mA ≤

I_LOAD≤ 100 mA

–0.5%

0.5%

LDO5, LDO7: ECO = 0b, 1 mA ≤ I_LOAD≤ 200 mA

LDO4, LDO9, LDO10: ECO = 0b, 1 mA ≤ I_LOAD≤ 300 mA

LDO1 to LDO10: ECO = 1b, 0 mA ≤ I_LOAD≤ 1 mA

dV/dt = ±0.5 V/μs

–1%

–1.5%

–5%

1%

1.5%

5%

Line transient response

Load transient response

–50

50

mV

dI/dt = 100 mA/μs, 10% to 90% load step

–110

110

LDO1 to LDO3 and LDO6 to LDO10: 10 Hz ≤ f ≤ 1 kHz,

VINLDOx – VLDOx ≥ 0.5 V,

10 mA ≤ I_LOAD≤ 0.75 × I_LOAD(MAX)

47

63

PSRR

Power supply rejection ratio

dB

LDO4 and LDO5: 10 Hz ≤ f ≤ 1 kHz, VINLDOx – VLDOx ≥

0.5 V,

10 mA ≤ I_LOAD≤ 0.75 × I_LOAD(MAX)

LDO1 to LDO3 and LDO6 to LDO10: 10 Hz ≤ f ≤ 100 kHz,

VINLDOx – VLDOx ≥ 0.5 V, I_LOAD≥ 10 mA

150

50

LDO1 to LDO3 and LDO6 to LDO10: 10 Hz ≤ f ≤ 10 kHz,

VINLDOx – VLDOx ≥ 0.5 V, I_LOAD≥ 10 mA

Output voltage noise

µVrms

LDO4 and LDO5: 10 Hz ≤ f ≤ 100 kHz, VINLDOx – VLDOx

≥ 0.5 V, I_LOAD≥ 10 mA

30

LDO4 and LDO5: 10 Hz ≤ f ≤ 10 kHz, VINLDOx – VLDOx

≥ 0.5 V, I_LOAD≥ 10 mA

15

ECO = 1b, I_LOAD≤ 1 mA for LDO1, LDO2, LDO3, LDO6,

LDO7, LDO8, LDO9, LDO10

8

16

ECO = 1b, I_LOAD≤ 1 mA for LDO4, LDO5

I_q

Quiescent current

µA

ECO = 0b, I_LOAD≤ 1 mA for LDO1, LDO2, LDO3, LDO6,

LDO7, LDO8, LDO9, LDO10

32

ECO = 0b, I_LOAD≤ 1 mA for LDO4, LDO5

40

Minimum wait time before the full current can be drawn

after ECO is set 0b

ECO exit time

50

µs

t_Ramp

V_OUTramp-up time

Time to ramp from 5% to 95% of VLDOx , I_OUT= 100 mA

VLDOx ≤ V_TARGET, VLDOx falling

V_LDOxrising

170

87% 90.6% 94.5%

V_LDOPGPG trigger

98%

1

t_LDOPG

Power good deglitch time

ms

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6.7 Electrical Characteristics – LDOs (continued)

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITION

MIN

TYP

Discharge resistance at LDO

output

R_Discharge

LDO disabled

200

325

450

Ω

(1) LDO Output voltages are programmed separately

(2) V_DO= V_IN– V_OUT, where V_OUT= V_OUT(NOM)– 2%

14

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6.8 Electrical Characteristics – Digital Inputs, Digital Outputs

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

V_IL

Low-level input voltage

0

0.4

V

All pins except digital interfaces and

configuration pins listed below

1.1

V_CC

For CONFIG1, CONFIG2, DEF_SPI_I2C-

GPIO, EN_LS0, EN_LS1, EN1/DCDC1_SEL,

EN2/DCDC2_SEL, EN3/DCDC3_SEL,

EN4/DCDC4_SEL, SLEEP/PWR_REQ,

CPCAP_WDI, VCON_CLK, CLK_REQ1,

CLK_REQ2

1.1

3.3

V_IH

High-level input voltage

V

For SDA, SCL, SDA_AVS, SCL_AVS

For MOSI

0.7 × VDDIO

1.1

VDDIO

I_OL= 1 mA, except SDA, SCL, SDA_AVS,

SCL_AVS

0

0.2

0.2 × VDDIO

0.4

I_OL= 3 mA, for SDA, SCL, SDA_AVS,

SCL_AVS, for VDDIO = 1.8 V

V_OL

Low-level output voltage

0

V

I_OL= 3 mA, for SDA, SCL, SDA_AVS,

SCL_AVS, for 2 V < VDDIO ≤ 3.6 V

For pins configured as push-pull output to

VDDIO, I_OH= 1 mA

VDDIO – 0.2

VDDIO

V_OH

High-level output voltage

Low-level output current

V

For pins configured as open-drain output

Except SCL, SDA, AVS_SCL, AVS_SDA

For SCL, SDA, AVS_SCL, AVS_SDA

V_CC

1

I_OL

mA

5

I_OH

High-level output current

Input-leakage current

1

mA

µA

I_LKG

Input pins tied to V_ILor V_IH

0.5

6.9 Electrical Characteristics – VMON Voltage Monitor, VDDIO, Undervoltage Lockout (UVLO),

and LDOAO

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Voltage monitor threshold for VMON_SEL[1:0] = 00b, rising

voltage

–2%

3.1

2%

V

Voltage monitor threshold for VMON_SEL[1:0] = 01b, rising

voltage

–2%

2.9

2.8

VMON

Voltage monitor threshold for VMON_SEL[1:0] = 10b, rising

voltage

Voltage monitor threshold for VMON_SEL[1:0] = 11b, rising

voltage

2.7

V

mV

V

VMON hysteresis

For falling voltage

250

Voltage applied to VDDIO pin to set the high level voltage of

push-pull output stages

VDDIO voltage range

1.63

1.4

3.6

VDDIO undervoltage lockout

(UVLO) threshold

1.625

V

Internal undervoltage lockout threshold (supply voltage rising)

Internal UVLO threshold hysteresis

2.5

200

2.5

V

mV

V

UVLO

VLDOAO

Output voltage for LDOAO (LDO always on)

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6.10 Electrical Characteristics – Load Switch

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

Voltage between LSI and LSO

5.5

115

100

520

V

ILIM[1:0] = 00b, 2.7 V ≤ V_(LSI)≤ 5.5 V

75

85

90

mA

ILIM[1:0] = 00b, 4.5 V ≤ V_(LSI)≤ 5.5 V, –10°C ≤ T_A≤ 85°C

ILIM[1:0] = 01b, 2.7 V ≤ V_(LSI)≤ 5.5 V

450

485

ILIM[1:0] = 01b, V(LSI) = 4.5 V ≤ V_(LSI)≤ 5.5 V, –10°C ≤ T_A

≤ 85°C

460

485

500

mA

LSI input current limit

ILIM[1:0] = 10b, 2.7 V ≤ V_(LSI)≤ 5.5 V

720

750

820

920

900

mA

ILIM[1:0] = 10b, 2.7 V ≤ V_(LSI)≤ 5.5 V, –10°C ≤ T_A≤ 85°C

ILIM[1:0] = 11b, 2.7 V ≤ V_(LSI)≤ 5.5 V, not tested in

production

2000

2500

10

3000

mA

µs

Current-limit response time

Resistance from LSI to LSO

When switch closed and operated as load switch with

ILIM[1:0] = 11b

20

40

mΩ

When switch closed and operated as load switch with

ILIM[1:0] = 00b or 01b or 10b

Resistance from LSI to LSO

200

20

mΩ

µA

V

Leakage current from LSI to LSO

When load switch is open

Load switch over-voltage protection on

the output (sensed at VDCDC4)

For EN_LS[1:0] = 10b or 11b, when load switch is used as

BYPASS switch

4.18

6.11 Electrical Characteristics – LED Drivers

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_(LEDA)= V_(LEDB)= V_(LEDC)= 0.25 V

Absolute accuracy

MIN

2

TYP

MAX UNIT

LEDx output sink

current

20

9.5%

0.25

mA

I_SINK(LEDx)

Accuracy

–8%

Low-level output

voltage

V_LO(LEDx)

I_LKG(LEDx)

Output low voltage at LEDx pins, 20 mA

V

Output off leakage

current

Output voltage = 5 V, driver set to OFF

1

μA

6.12 Electrical Characteristics – Thermal Monitoring and Shutdown

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

113

TYP

117

121

125

130

10

MAX UNIT

THERM_HDSEL[1:0] = 00b

136

THERM_HDSEL[1:0] = 01b

THERM_HDSEL[1:0] = 10b

THERM_HDSEL[1:0] = 11b

Hot-die temperature rising threshold

°C

136

°C

Hot-die temperature hysteresis

Thermal shutdown temperature rising

threshold

136

148

160

°C

Thermal shutdown temperature hysteresis

Ground current

10

6

°C

Device in ACTIVE state, T_A= 27°C, V_CCS= 3.8 V

µA

16

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6.13 Electrical Characteristics – 32-kHz RC Clock

–40°C ≤ T_A≤ 85°C, typical values are at T_A= 25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

32KCLKOUT rise and fall time

C_L= 35 pF

10

ns

Output-frequency low-level output voltage 32KCLKOUT output

32

0%

kHz

Output-frequency accuracy

Output duty cycle

Settling time

T_A= 25°C

–20%

40%

15%

60%

150

50%

µs

6.14 SPI Timing Requirements

For the SPI timing diagram, see Figure 7-3.

MIN

30

65

20

5

MAX

UNIT

t_cesu

t_cehld

t_ckper

t_ckhigh

t_cklow

t_sisu

Chip select setup time

ns

pF

Chip select hold time

Clock cycle time

Clock high typical pulse duration

Clock low typical pulse duration

Input data setup time, before clock active edge

Input data hold time, after clock active edge

Data retention time

t_sihld

t_dr

5

15

30

t_CE

Time from CE going low to CE going high

Capacitive load on pin GPIO1_MISO

65

6.15 I²C Interface Timing Requirements

Specified by design. Not tested in production. For the high-speed mode timing diagram, see Figure 7-2.

MIN

MAX

100

UNIT

kHz

Standard mode

Fast mode

400

kHz

High-speed mode (write operation), C_B– 100 pF

maximum

3.4

1.7

MHz

High-speed mode (read operation), C_B– 100 pF

maximum

f_(SCL)

SCL clock frequency

High-speed mode (write operation), C_B– 400 pF

maximum

High-speed mode (read operation), C_B– 400 pF

maximum

Standard mode

4.7

1.3

4

μs

ns

μs

ns

Bus free time between a STOP

and START condition

t_BUF

Fast mode

Standard mode

Hold time (repeated) START

condition

t_HD, t_STA

Fast mode

600

160

4.7

1.3

160

320

High-speed mode

Standard mode

Fast mode

t_LOW

LOW period of the SCL clock

High-speed mode, C_B– 100 pF maximum

High-speed mode, C_B– 400 pF maximum

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6.15 I²C Interface Timing Requirements (continued)

Specified by design. Not tested in production. For the high-speed mode timing diagram, see Figure 7-2.

MIN

MAX

UNIT

μs

ns

μs

ns

μs

ns

µs

ns

pF

Standard mode

4

Fast mode

600

t_HIGH

HIGH period of the SCL clock

High-speed mode, C_B– 100 pF maximum

High-speed mode, C_B– 400 pF maximum

Standard mode

60

120

4.7

Setup time for a repeated START

condition

t_SU, t_STA

Fast mode

600

High-speed mode

160

Standard mode

250

t_SU, t_DAT

Data setup time

Data hold time

Fast mode

100

High-speed mode

10

Standard mode

0

3.45

0.9

Fast mode

0

t_HD, t_DAT

High-speed mode, C_B– 100 pF maximum

High-speed mode, C_B– 400 pF maximum

Standard mode

0

70

0

150

1000

300

40

20 + 0.1 C_B

Fast mode

20 + 0.1 C_B

t_RCL

Rise time of SCL signal

High-speed mode, C_B– 100 pF maximum

High-speed mode, C_B– 400 pF maximum

Standard mode

10

20

80

20 + 0.1 C_B

1000

300

80

Rise time of SCL signal after a

repeated START condition and

after an acknowledge bit

Fast mode

20 + 0.1 C_B

t_RCL1

High-speed mode, C_B– 100 pF maximum

High-speed mode, C_B– 400 pF maximum

Standard mode

10

20

160

300

40

20 + 0.1 C_B

Fast mode

20 + 0.1 C_B

t_FCL

Fall time of SCL signal

Rise time of SDA signal

Fall time of SDA signal

High-speed mode, C_B– 100 pF maximum

High-speed mode, C_B– 400 pF maximum

Standard mode

10

20

80

20 + 0.1 C_B

1000

300

80

Fast mode

20 + 0.1 C_B

t_RDA

High-speed mode, C_B– 100 pF maximum

High-speed mode, C_B– 400 pF maximum

Standard mode

10

20

160

300

80

20 + 0.1 C_B

Fast mode

20 + 0.1 C_B

t_FDA

High-speed mode, C_B– 100 pF maximum

High-speed mode, C_B– 400 pF maximum

Standard mode

10

20

160

4

t_SU, t_STO

Setup time for STOP condition

Capacitive load for SDA and SCL

Fast mode

600

160

High-speed mode

C_B

400

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6.16 Typical Characteristics

100

90

80

70

60

50

40

30

20

10

0

V

= 3 V

I

90

80

70

60

50

40

30

20

10

V

= 3 V

I

V

= 3.6 V

I

V

= 4.2 V

I

V

= 3.6 V

I

V

= 4.2 V

V

= 5 V

I

V

= 5 V

I

0

0.0001

0.001

0.01

0.1

1

10

0.0001

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 0.9 V

DFE252012P-1R0

PFM Mode

T_A= 25°C

V_OUT= 0.9 V

DFE252012P-1R0

PWM Mode

T_A= 25°C

Figure 6-1. DCDC1 Efficiency vs Output Current

Figure 6-2. DCDC1 Efficiency vs Output Current

100

V

= 3 V

I

90

80

70

60

50

40

30

20

10

90

80

70

60

50

40

30

20

10

V

= 3 V

I

V

= 3.6 V

I

V

I

= 3.6 V

V

= 4.2 V

I

V

= 4.2 V

I

V

= 5 V

I

V

= 5 V

I

0

0.0001

0

0.0001

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 1.1375 V

PWM Mode

T_A= 25°C

V_OUT= 1.1375 V

DFE252012P-1R0

PFM Mode

T_A= 25°C

DFE252012P-1R0

Figure 6-4. DCDC1 Efficiency vs Output Current

Figure 6-3. DCDC1 Efficiency vs Output Current

100

V

= 3 V

I

90

80

70

60

50

40

30

20

10

90

80

V

= 3.6 V

V

= 3 V

I

70

60

50

40

30

20

10

V

= 4.2 V

I

V

= 5 V

V

= 3.6 V

I

V

= 4.2 V

I

V

= 5 V

I

0

0.0001

0

0.0001

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 1.2 V

PWM Mode

T_A= 25°C

V_OUT= 1.2 V

PFM Mode

T_A= 25°C

LQM2MPN-1R0

Figure 6-6. DCDC1 Efficiency vs Output Current

Figure 6-5. DCDC1 Efficiency vs Output Current

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6.16 Typical Characteristics (continued)

100

90

80

70

60

50

40

30

20

V

= 3 V

I

V

= 3.6 V

I

90

80

70

60

50

40

30

20

10

0

V

= 4.2 V

I

V

= 3 V

I

V

= 5 V

V

= 3.6 V

I

V

= 4.2 V

I

V

= 5 V

I

10

0

0.0001

0.001

0.01

0.1

1

10

0.0001

0.001

0.01

0.1

1

10

Output Current (A

Output Current (A)

V_OUT= 1.8 V

PFM Mode

T_A= 25°C

V_OUT= 1.8 V

PWM Mode

T_A= 25°C

LQM2MPN-1R0

Figure 6-7. DCDC2 Efficiency vs Output Current

Figure 6-8. DCDC2 Efficiency vs Output Current

100

90

V

= 3 V

I

80

70

60

50

40

30

20

10

V

= 3 V

I

V

= 3.6 V

I

V

= 4.2 V

I

V = 3.6 V

I

70

60

50

40

30

20

10

V

= 5 V

I

V

= 4.2 V

I

V

= 5 V

I

0

0.0001

0

0.0001

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 2.25 V

VLS201612-1R0

PFM Mode

T_A= 25°C

V_OUT= 2.25 V

PWM Mode

T_A= 25°C

VLS201612-1R0

Figure 6-9. DCDC2 Efficiency vs Output Current

Figure 6-10. DCDC2 Efficiency vs Output Current

100

90

100

V

= 3 V

I

90

80

70

60

50

40

30

20

10

V

= 3 V

80

70

60

50

40

30

20

10

I

V

= 3.6 V

I

V

= 4.2 V

I

V

= 3.6 V

I

V

= 5 V

I

V

= 4.2 V

I

V

= 5 V

I

0

0.0001

0

0.0001

0.001

0.01

0.1

1

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 2.95 V

PFM Mode

T_A= 25°C

V_OUT= 2.95 V

VLS201612-1R0

PWM Mode

T_A= 25°C

VLS201612-1R0

Figure 6-11. DCDC2 Efficiency vs Output Current

Figure 6-12. DCDC2 Efficiency vs Output Current

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6.16 Typical Characteristics (continued)

100

90

80

70

60

50

40

30

20

10

0

V

= 3 V

I

V

= 3.6 V

I

90

80

70

60

50

40

30

20

10

V

= 4.2 V

I

V

= 3 V

I

V

= 3.6 V

I

V

= 4.2 V

I

V

= 5 V

I

V

= 5 V

I

0

0.0001

0.001

0.01

0.1

1

10

0.0001

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 1.1375 V

DFE252012-1R0

PFM Mode

T_A= 25°C

V_OUT= 1.1375 V

DFE252012-1R0

PWM Mode

T_A= 25°C

Figure 6-13. DCDC3 Efficiency vs Output Current

Figure 6-14. DCDC3 Efficiency vs Output Current

100

V

= 3 V

I

90

80

70

60

50

40

30

20

10

90

80

V

= 3.6 V

V

= 3 V

I

V

= 4.2 V

I

V

= 5 V

70

60

50

40

30

20

10

I

V

= 3.6 V

I

V

= 4.2 V

I

V

= 5 V

I

0

0.0001

0

0.0001

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 2.1 V

PFM Mode

T_A= 25°C

V_OUT= 2.1 V

PWM Mode

T_A= 25°C

LQM2MPN-1R0

Figure 6-15. DCDC3 Efficiency vs Output Current

Figure 6-16. DCDC3 Efficiency vs Output Current

100

V

= 4.2 V

I

90

80

70

60

50

40

30

20

10

0

90

80

V

= 5 V

70

I

V

= 4.2 V

I

60

50

40

30

20

10

V

= 5 V

I

0

0.0001

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 3.2 V

PFM Mode

T_A= 25°C

V_OUT= 3.2 V

PWM Mode

T_A= 25°C

DFE25012-1R0

DEF25012-1R0

Figure 6-17. DCDC3 Efficiency vs Output Current

Figure 6-18. DCDC3 Efficiency vs Output Current

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6.16 Typical Characteristics (continued)

100

90

80

70

60

50

40

30

20

V

= 3 V

I

90

80

70

60

50

40

30

20

10

0

V

= 3.6 V

I

V

= 4.2 V

V

= 3 V

I

V

= 3.6 V

I

V

= 4.2 V

V

= 5 V

I

V

= 5 V

I

10

0

0.0001

0.001

0.01

0.1

1

10

0.0001

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 1.1375 V

DEF322512-1R0

PWM Mode

T_A= 25°C

V_OUT= 1.1375 V

DEF25012-1R0

PFM Mode

T_A= 25°C

Figure 6-20. DCDC4 Efficiency vs Output Current

Figure 6-19. DCDC4 Efficiency vs Output Current

100

90

V

= 4.2 V

I

V

= 3.8 V

I

80

70

60

50

40

30

20

10

80

V

= 5 V

I

70

V

= 3.8 V

I

60

50

40

30

20

10

V

= 4.2 V

I

V

= 5 V

I

0

0.0001

0

0.0001

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

Output Current (A)

V_OUT= 3.3 V

PFM Mode

T_A= 25°C

V_OUT= 3.3 V

PWM Mode

T_A= 25°C

DEF322512-1R0

Figure 6-21. DCDC4 Efficiency vs Output Current

Figure 6-22. DCDC4 Efficiency vs Output Current

100

90

80

70

60

50

40

30

20

10

0

90

VIN_LDO = 1.8 V, VOUT = 1.2 V, IOUT = 10 mA

80

70

60

50

40

30

VIN_LDO = 1.8 V, VOUT = 1.2 V, IOUT = 100 mA

20

10

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

Figure 6-23. LDO1, LDO2, LDO3 PSRR vs Frequency

V_IN= 3.2 V

I_OUT= 225 mA

Figure 6-24. LDO4 and LDO5 PSRR vs Frequency

V_OUT= 2.7 V

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6.16 Typical Characteristics (continued)

100

90

80

70

60

50

40

30

20

VIN_LDO = 5 V, VOUT = 3.3 V, IOUT = 10 mA

90

VIN_LDO = 3.3 V, VOUT = 1.8 V, IOUT = 10 mA

80

70

60

50

VIN_LDO = 3.3 V, VOUT = 2.85 V, IOUT = 10 mA

VIN_LDO = 3.3 V, VOUT = 1.8 V, IOUT = 100 mA

VIN_LDO = 5 V, VOUT = 3.3 V, IOUT = 100 mA

40

30

20

VIN_LDO = 3.3 V, VOUT = 2.85 V, IOUT = 100 mA

10

0

10

0

10

100

1k

10k

100k

1M

10M

10

100

1k

10k

100k

1M

10M

Frequency (Hz

Frequency (Hz)

Figure 6-25. LDO4 PSRR vs Frequency

Figure 6-26. LDO6 and LDO8 PSRR vs Frequency

100

90

80

VIN_LDO9 = 3.3 V, VOUT = 2.85 V, IOUT = 10 mA

70

60

50

40

30

20

VIN_LDO9 = 3.3 V, VOUT = 2.85 V, IOUT = 300 mA

10

0

10

100

1k

10k

100k

1M

10M

Frequency (Hz)

Figure 6-27. LDO9 PSRR vs Frequency

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7 Parameter Measurement Information

7.1 I²C Timing Diagrams

SDA

t_f

t_BUF

t_r

t_LOW

T_su:DAT

t_f

t_hd:STA

t_r

SCL

t_hd:DAT

t_SU:STA

S

P

T_su:STO

T_hd:STA

High

Figure 7-1. Serial Interface Timing Diagram for FS-Mode

Sr

P

t_fDA

t_rDA

SDAH

t_hd;DAT

t_su;STA

t_hd;STA

T_su;STO

t_su;DAT

SCLH

t_fCL

t_rCL1

t_rCL

t_LOW

See Note A

t_HIGH

t_LOW

t_HIGH

See Note A

A. First rising edge of the SCLH signal after Sr and after each acknowledge bit.

Figure 7-2. Serial Interface Timing Diagram for HS-Mode

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7.2 SPI Timing Diagram

SPI Chip Select

t_ckper

t_ckhigh

t_cehld

t_cklow

t_cesu

SPI Clock Enable

t_sisu

t_sihld

SPI Data Input

R/W

Address (8 bits)

Unused bits (7 bits)

t_dr

Data (8 bits)

SPI Data Output

ERROR (15 bits)

Figure 7-3. SPI Timing

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8 Detailed Description

8.1 Overview

The TPS659128x device is an integrated power-management integrated circuit (PMIC), available in an 81-pin,

0.4-mm pitch, 3.6-mm × 3.6-mm DSBGA package. The device is designed for applications including data

cards, smart phones, wireless routers and switchers, LTE modems, industrial applications, GPS, and tablets.

The device provides four, configurable step-down converter rails with a power save mode for light loads.

The TPS659128x device also provides ten external LDO rails. Eight are general purpose LDOs and two are

low-noise RF-LDOs. The device also comes with two I²C interface channels or one SPI channel, five GPIOs, a

32-kHz RC oscillator, and a programmable power sequencer and control for supporting different processors and

applications. The four, step-down converter rails are consisting of four, high-frequency switch-mode converters

with integrated FETs. The rails are capable of synchronizing to an external clock input and supports a switching

frequency from 2.8 MHz to 3.5 MHz. The DCDC4 rail also includes a bypass switch that can be used to turn

on and turn off high current loads. In addition, the DCDC rails support dynamic voltage scaling with a dedicated

I²C interface. The eight general LDOs support an output from 0.8 V to 3.3 V. The two low-noise LDOs support

an output from 1.6 V to 3.3 V. All LDOs and step-down converters can be controlled by the SPI or I²C interface.

The power-up and power-down controller is configurable and programmable through one-time programmable

(OTP) memory. The TPS659128x device includes a 32-kHz RC oscillator to sequence all resources during

power up and power down. Configurable GPIOs with a multiplexed feature are available on the TPS659128x

device. The GPIOs can be configured and used as enable signals for external resources, which can be included

in the power-up and power-down sequence. Lastly, the device includes a long button-press detection that allows

startup of the device with the hold of a button.

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8.2 Functional Block Diagram

TPS65912

VCC

VINDCDC1

Digital Core

DCDC1

0.5to 1.2875 V

CONFIG1

SW1

CONFIG2

0.7to 1.4875 V

0.5to 2.075V

0.5to 3.8 V

DEF_SPI_I2C-GPIO

VDCDC1

VDCDC1_GND

PGND1

2.5A

SCL_SCK

OTP Bank 0

CONFIG1 = 0

OTP Bank 1

CONFIG1 = 1

SDA_MOSI

I²C and SPI

GPIO1_MISO

VINDCDC2

DCDC2

GPIO2_CE

0.5to 1.2875 V

0.7to 1.4875 V

0.5to 2.075V

0.5to 3.8 V

SCL_AVS/CLK_REQ1

SCL_SDA/CLK_REQ2

EN1/DCDC1_SEL

EN2/DCDC2_SEL

EN3/DCDC3_SEL

EN4/DCDC4_SEL

nRESPWRON/VSUP_OUT

INT1

SW2

VDCDC2

PGND2

0.75 A

VINDCDC3

DCDC3

PG Monitor

0.5to 1.2875 V

0.7to 1.4875 V

0.5to 2.075V

0.5to 3.8 V

SW3

VDCDC3

PGND3

SLEEP/PWR_REQ1

nPWRON (nResin)

OMAP_WDI_32k_OUT

VCON_PWM

1.6A

VINDCDC4

SW4

VCON_CLK

Sequencer

ENx, SLEEP

DCDC4

PWRHOLD_ON

CPCAP_WDI

0.5to 1.2875 V

0.7to 1.4875 V

0.5to 2.075V

0.5to 3.8 V

EN_LS0

VDCDC4

VDCDC4_GND

PGND4

EN_LS1

2.5A

VINDCDC_ANA

VDDIO

LSI

VREF1V25

AGND

Interrupt

Management

BIAS

Load Switch

90to 2500mA

LSO

AGND

DGND

VINLDO1210

VLDO1

LDO1

0.8to 3.3 V

100 mA

VCCS/VIN_MON

+

LDO2

0.8to 3.3 V

100 mA

V_TH

GPIO

Controller

VLDO2

œ

LEDA/GPIO3

LDO10

0.8to 3.3 V

300 mA

VLDO10

LEDB/GPIO4

LED Driver

VINLDO3

VLDO3

LEDC/GPIO5

LDO3

0.8to 3.3 V

100 mA

LED

Controller

VINLDO4

VLDO4

32-kHz RC

Oscillator

LDO4(Low Noise)

1.6to 3.3 V

250 mA

VINLDO5

VLDO5

Thermal

Warning and

Shutdown

LDO5(Low Noise)

1.6to 3.3 V

250 mA

VINLDO67

VLDO6

LDO6

0.8to 3.3 V

100 mA

LDO9

0.8to 3.3 V

300 mA

LDO8

0.8to 3.3 V

100 mA

LDO7

0.8to 3.3 V

300 mA

Always-On

Internal LDO

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8.3 Feature Description

8.3.1 Linear Regulators

The power-management core has 10 low-dropout (LDO) regulators with various output voltage and current

capabilities. Each LDO output voltage can be set independently through the communication bus (see Table

8-85). The transition occurs immediately if the LDO regulator is enabled.

8.3.1.1 Low Quiescent Current Mode (Eco-mode™)

Each LDO regulator is equipped with a low quiescent-current mode that can be enabled or disabled separately.

When the ECO bit is set to 1b, the LDOx Eco-mode control scheme is enabled if the proper conditions are met.

8.3.1.2 Output Discharge

Each LDO regulator is equipped with an output discharge bit located in the DISCHARGEx registers. When the

LDOx_DISCHARGE bit is set to 1b, the output of the LDO is discharged to ground with the equivalent of a 300-Ω

resistor. If the LDO regulator is enabled, the discharge bit is ignored.

8.3.1.3 Thermal Shutdown

Global thermal-shutdown protection is available for all step-down converters and LDO regulators. The thermal

sensor generates an early warning depending on the setting of the THRM_REG register. This can generate an

interrupt on the INT pin if the HOTDIE interrupt is not masked in the INT_MSK register. If the temperature rises

above the thermal shutdown threshold, the device is powered down to the OFF state.

8.3.1.4 LDO Enable

The LDO enable and disable is part of the flexible power-up and power-down state machine. Each LDO

regulator can be factory programmed such that it is powered up automatically in one of the 15 time slots after

a power-on condition occurs or is controlled by a dedicated pin. More details on the startup sequencing is

available in Section 8.4.3. The EN1, EN2, EN3, EN4, CLK_REQ1, CLK_REQ2, and PWR_REQ (SLEEP) pins

can be mapped to any resource (LDO, DC-DC converter, 32-kHz clock output, or GPIO) to enable or disable the

resource if the proper conditions are met.

8.3.1.5 LDO Voltage Range

The output voltage range for the standard LDO regulators is 0.8 V to 3.3 V. For the RF-LDO regulators, LDO4

and LDO5, the output voltage range is 1.6 V to 3.3 V. The most significant bit for the voltage settings (the SEL[5]

bit) on LDO4 and LDO5 is ignored and is internally set to 1b.

8.3.1.6 LDO Power-Good Comparator

The output voltage of each LDO regulator is supervised by an internal power-good comparator. The output of the

comparator is set and cleared by the power-good bits in the PGOOD and PGOOD2 registers. The power-good

bits are not valid if the LDO regulator is enabled but the input voltage to the LDO is less than 1 V.

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8.3.2 Step-Down Converters

The synchronous step-down converter used in the power-management core includes a unique, hysteric PWM-

controller scheme which enables switch frequencies over 3 MHz, excellent transient and AC load regulation, and

operation with tiny and cost-competitive external components.

The controller topology supports forced PWM mode as well as power save mode operation. Power save mode

operation reduces the quiescent current consumption and ensures high conversion efficiency at light loads by

skipping switch pulses.

A significant advantage of this architecture compared to other hysteretic PWM-controller topologies is its

excellent DC and AC load regulation capability in combination with low output-voltage ripple over the entire

load range which makes this device well suited for audio and RF applications.

When the output voltage falls below the threshold of the error comparator, a switch pulse is initiated and the

high-side switch is turned on. The switch remains turned on until a minimum on time expires and the output

voltage trips the threshold of the error comparator or the inductor current reaches the current limit of the

high-side switch. When the high-side switch turns off, the low-side switch rectifier is turned on and the inductor

current ramps down until the high-side switch turns on again or the inductor current reaches zero.

8.3.2.1 PWM and PFM Mode

In forced PWM mode, the device avoids pulse skipping and allows easy filtering of the switch noise by external

filter components. PWM mode is forced by setting the DCDCx_MODE bit to 1b. If this bit is not set, the DCDCx

outputs are in auto mode, which can switch to a low-current PFM mode when a light load occurs and sufficient

headroom is present between the DCDCx input and output rails.

8.3.2.2 Low Quiescent Current Mode

Each step-down converter can be individually controlled to enter a low quiescent-current mode. This mode can

be entered when the ECO bit is set to 1b and the proper conditions are met. In Eco-mode, the quiescent current

is reduced and the output voltage is supervised by a comparator while most parts of the control circuitry are

disabled to save power. Eco-mode should only be enabled when a converter has less than 2 mA of load current.

In addition, the Eco-mode should be disabled prior to a load transient step to allow the converter to respond

in a timely manner to the excess current draw. Setting the step-down converter into PWM mode by setting the

DCDCx_MODE bit to 1b disables Eco-mode independently from the setting of the ECO bit.

8.3.2.3 Output Voltage Monitoring

Internal power-good comparators monitor the switching regulator outputs and detect when the output voltage is

less than 90% of the programmed value. This information is used by the power-management core to generate

interrupts depending on specific I²C register settings. For more information, see Section 8.4.8. An individual

power-good comparator of the switching regulator is blanked when the regulator is disabled or when the voltage

of the regulator is transitioning from one set point to another.

8.3.2.4 Output Discharge

Each switching regulator is equipped with an output discharge enable bit located in the DISCHARGE2 register.

When the DCDCx_DISCHARGE bit is set to 1b, the output of the regulator is discharged to ground with the

equivalent of a 400-Ω resistor. If the enable bit of the regulator is set, the discharge bit is ignored.

8.3.2.5 Thermal Shutdown

Global thermal-shutdown protection is available for all step-down converters and LDOs. The thermal sensor

generates an early warning depending on the setting of the THRM_REG register. If the temperature rises above

the thermal shutdown threshold, the device is powered down to the OFF state.

8.3.2.6 Step-Down Converter Enable

The step-down converter enable and disable is part of the flexible power-up and power-down state machine.

Each converter can be factory programmed such that it is powered up automatically in one of the 15 time slots

after a power-on condition occurs or is controlled by a dedicated pin. The EN1, EN2, EN3, EN4, CLK_REQ1,

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CLK_REQ2, and PWR_REQ (SLEEP) pins can be mapped to any resource (LDO, DC-DC converter, 32 kHz

clock output, or GPIO) to enable or disable the resource.

8.3.2.7 Step-Down Converter Soft Start

The step-down converters in the TPS659128x device have an internal soft-start circuit that controls the ramp-up

of the output voltage. The output voltage ramps up from 5% to 95% of its nominal value within a time defined in

Section 6. This ramp time limits the inrush current in the converter during start-up and prevents possible input

voltage drops when a battery or high-impedance power source is used. The soft-start circuit is enabled after the

start-up time, t_Start, has expired. The DCDC4 converter has an option to set two different values for the start-up

and ramp time. For applications that require a fast response, set the DCDC4_CTRL:RAMP_TIME bit to 1b.

During soft start, the output voltage ramp up is controlled as shown in Figure 8-1.

EN

95%

5%

V_OUT

t_Start

t_RAMP

Figure 8-1. Soft Start

8.3.3 GPIOs

The TPS659128x device has five GPIOs. GPIO1 and GPIO2 are shared with the SPI and therefore they are

not available if the SPI is used. GPIO3, GPIO4, and GPIO5 are for general-purpose use and are shared with

the LED driver. The input and output stages of GPIO1 and GPIO2 are similar to GPIO3 however, they do not

contain the LED current sink. If the output stage is programmed as a push-pull output, it pulls to the high-voltage

set by the VDDIO pin. With the VDDIO supply voltage being less than the VDDIO UVLO threshold voltage, the

high-side driver is disabled and the output is set to open drain.

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VDDIO

Output enable

GPIO_CFG

Open drain-enable

GPIO_ODEN

Backgate

Switch

GPIOx / LEDx

DATA IN

4.7 kꢀ

LED

current

sink

DATA OUT

Pulldown enable

GPIO_PDEN

LED_PWM

Figure 8-2. GPIO Block for GPIO3, GPIO4, and GPIO5

8.4 Device Functional Modes

8.4.1 Power State Machine

The embedded power controller (EPC) manages the state of the device and controls the power-up sequence.

The transitions for the state machine are shown in Figure 8-3 through Figure 8-8.

The EPC supports the following states:

NO

SUPPLY

The main battery-supply voltage is not high enough to power the LDOAO (LDO Always ON)

regulator in this state. A global reset is asserted in this case. Everything on the device is off.

CONFIG

This state is entered either from the NO SUPPLY state automatically or from the ACTIVE or

SLEEP state when the TPS659128x device is configured accordingly by the LOAD-OTP bit (bit 6)

in the DEVCTRL register. When the CONFIG state is entered, all registers are set to their default

value and the nRESPWRON pin is asserted.

OFF

The LDOAO regulator is on and internal logic is active in this state. All power supplies are off. The

device can detect and execute a power-up sequence. The nRESPWRON pin is asserted.

ACTIVE

SLEEP

Device POWER-ON enable conditions are met and regulated power supplies are ON or can be

enabled with full current capability in this state. A reset is released and the interfaces are active.

Device SLEEP enable conditions are met and selected regulated power supplies are in low-power

or off mode in this state. Only used when CONFIG2 is shorted to GND.

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8.4.2 Transition Conditions

The device transition conditions are:

•

The device performs POWER ON transition when any of the following power on conditions are met:

– nPWRON signal low level

– PWRHOLD signal high level

– PWRHLD bit in the DEVCTRL register set to 1b (OTP dependent default)

– Interrupt flag active (default INT1 low) will generate a POWER ON enable condition for 5 seconds. During

this time period, the processor or system is required to set PWRHOLD pin to high or set the PWRHLD

bit in the DEVCTRL register to 1b to keep the device on. Interrupt sources generate POWER ON enable

conditions only if they are not masked (OTP and register setting dependent).

•

The device POWER ON transition will not occur if any of the following conditions are present:

– nPWRON signal low level for more than the Long Press delay of 5 s. This can be disabled by

setting the PWRON_LP_OFF and PWRON_LP_OFF_RST bits in the DEVCTRL2 register to 0b. The

interrupt corresponding to this condition is the PWRON_LP_IT in INT_STS_REG register. The interrupt is

generated after 4 s to allow processor to mask PWRON_LP_OFF if desired.

– Die temperature has reached the thermal shutdown threshold (THERM_TS bit in THRM_REG register is

1b)

•

Device performs POWER OFF transition from ACTIVE state if none of the POWER ON conditions are met,

if long key press takes priority, the DEV_OFF bit is set to 1b, or die temperature reaches thermal shutdown

threshold.

Device performs ACTIVE to SLEEP transition when all of the following happen:

– The interrupt flag is inactive, meaning there are no unmasked interrupts pending

– The SLEEP_ENABLE bit in the DEVCTRL2 register is set to 1b

– The SLEEP pin is active (polarity depending on SLEEP_POL bit in the DEVCTRL2 register)

Alternatively, as long as no interrupts are pending, the DEV_SLP bit can also put the device into the SLEEP

state with higher priority than the SLEEP pin. When the DEV_SLP bit is used, there must be an unmasked

interrupt to cause SLEEP to ACTIVE transition, otherwise device will remain in SLEEP until set to OFF state

and the DEV_SLP bit is cleared. It is not recommended to use the DEV_SLP bit when the CONFIG2 pin is

shorted to LDOAO.

•

The device has two different reset scenarios:

– Full reset: all digital of device is reset

•

This reset is caused by a power-on reset (POR) when VCCS < UVLO.

– General reset, where only OTP backed register bits are reloaded:

•

This reset is caused by a turnoff event while the LOAD-OTP bit is set to 1b.

A turnoff event happens when the PWRON_LP_OFF_RST bit is set to 1b.

The nPWRON pin can also be set in OTP to cause reset when pulled low longer than 100 ms.

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VCCS < UVLO

NO SUPPLY

UVLO: 2.6-V rising voltage

POWER ON disabled

OR

VCCS < VMON_SEL[1:0] œ 200 mV

AND LOAD-OTP = 1b

OR

Load default settings

from OTP and pins.

THERM_TS = 1b AND LOAD-OTP = 1b

CONFIG < 200-µs

delay

POWER ON disabled

OR

VCCS < VMON_SEL[1:0] œ 200 mV AND

LOAD-OTP = 0b

OFF

POWER ON disabled

OR

VCCS < VMON_SEL[1:0] œ 200 mV

AND LOAD-OTP = 0b

OR

POWER ON enabled⁽¹⁾⁽²⁾

AND

VCCS > VMON_SEL[1:0]

THERM_TS = 1b AND LOAD-OTP = 0b

ACTIVE

SLEEP

disabled

SLEEP

enabled

POWER ON disabled

OR

VCSS < VMON_SEL[1:0] œ 200 mV

AND LOAD-OTP = 1b

SLEEP

A. Alternatively, the PWRHLD bit in the DEVCTRL register can be factory programmed to 1b in OTP, causing immediate power up. In this

case, the bit must be set to 0b to allow normal device shutdown.

B. SLEEP state only applies when CONFIG2 is shorted to GND.

Figure 8-3. EPC State Machine

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VCCS < UVLO

NO SUPPLY

UVLO: 2.6-V rising voltage

Load default settings from OTP load status of the CONFIG1,

CONFIG2, DEF_SPI_12C_GPIO pins.

Copy status of EN_LS0 and EN_LS1 pins to register.

CONFIG < 200-µs

delay

SPI and I²C interfaces in reset

Wait for power-on event by

PWRON pulled low

OR PWRHOLD = HIGH

OFF

SPI and I²C interfaces in reset

Power-up primary resources as defined in OTP within 16

timeslots of DEVCTRL2:TSLOTLENGTH[1:0]

Run Start-Up

Sequencing

Example: DCDC2 - DCDC1 - DCDC4 - DCDC3 - LDO9 -

release nRESPWRON

SPI and I²C interfaces gated by nRESPWRON

Continuously check the status of the enable pins to power-up

the secondary resources driven by the pins

Example:

ACTIVE

EN1 pin is mapped to LDO1 by EN1_SET1:LDO1_EN = 0x01

EN2 is mapped to LDO2 and LDO4 by EN_SET2[7:0] = 0x0A

SPI and I²C interfaces active

Figure 8-4. STARTUP Flow for CONFIG2 Pin Shorted to LDOAO

Figure 8-4 is valid when the CONFIG2 pin is shorted to LDOAO. The EN1, EN2, EN3, and EN4 pins are used

as enable pins to enable one or several resources. The EN1_SET1 and EN1_SET2 registers define which

converters or LDO regulators are controlled by the EN1 pin. The EN2, EN3, and EN4 are configured similarly.

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VCCS < UVLO

NO SUPPLY

UVLO: 2.6-V rising voltage

Load default settings from OTP

Load status of CONFIG1, CONFIG2, DEF_SPI_I2C_GPIO pins

Copy status of EN_LS0 and EN_LS1 to register

For CONFIG2 pin shorted to ground:

Maps ENx pins to be DCDCx_SEL pin to define the output voltage of

DC-DC converter x, LDOs, or both (defined by DEF_VOLT_MAPPING)

Maps PWR_REQ1 pin to EN1_SET register

CONFIG < 200-µs

delay

Maps CLK_REQ1 pin to EN2_SET register

Maps CLK_REQ2 pin to EN3_SET register

SPI and I²C interfaces in reset

Wait for power-on event by

PWRON pulled low

OR PWRHOLD = HIGH

OFF

SPI and I²C interfaces in reset

Power-up primary resources as defined in OTP within 16 timeslots of

DEVCTRL2:TSLOTLENGTH[1:0]

Output voltage is defined by DCDCx_SEL pins

Run Start-Up

Sequencing

Example: DCDC3 œ DCDC2 œ LDO10 - wait for VSUP_OUT = HIGH œ delay

rising VSUP_OUT signal to pin by 10 ms

SPI and I²C interfaces gated by nRESPWRON (VSUP_OUT)

Continuously check status of CLK_REQx, PWR_REQ and DCDCx_SEL pins

to enable or disable resources or change the output voltage between the value

defined by _OP and _AVS registers

Example:

DCDC1_SEL = 0b: Output voltage of DCDC1 is defined by DCDC1_OP

register

DCDC1_SEL = 1b: Output voltage of DCDC1 is defined by DCDC1_AVS

register

ACTIVE

EN1_SET1:LDO1_EN = 1b: PWR_REQ pin is mapped to LDO1

EN_SET2[7:0] = 0x0A: CLK_REQ1 pin is mapped to LDO2 and LDO4

EN_SET3[7:0] = 0x0A: CLK_REQ2 pin is mapped to LDO2 and LDO4

: LDO1 is enabled and disabled by pin PWR_REQ

: LDO2 and LDO4 are enabled if pin CLK_REQ1 = 1 OR CLK_REQ2 = 1

SPI and I²C interfaces active

Figure 8-5. STARTUP Flow for CONFIG2 Pin Shorted to GND

Figure 8-5 is valid when the CONFIG2 pin is shorted to GND. The EN1, EN2, EN3, and EN4 pins are remapped

as DCDCx_SEL pins, defining which register is used to set the output voltage on a specific DC-DC converter.

For example, connecting the DCDC1_SEL pin to GND sets the output voltage of the DCDC1 converter to what is

defined by the DCDC1_OP register. Connecting the DCDC1_SEL pin to a logic level high sets the output voltage

to what is defined by the DCDC1_AVS register. The DCDC2 voltage is defined by the DCDC2_SEL pin and so

forth.

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The LDO1 to LDO4 regulators can be mapped to the DCDCx_SEL pins. The DEF_VOLT_MAPPING register

defines which LDO regulator is controlled by which DCDCx_SEL pin.

Additionally, shorting the CONFIG2 pin to GND also remaps the SCL_AVS, SDA_AVS, and SLEEP pins as

CLK_REQ1, CLK_REQ2, and PWR_REQ pins. The functionality is similar to the ENx pins.

The EN1_SET1 and EN1_SET2 registers define which resource is controlled by the PWR_REQ pins, the

EN2_SETx register defines the resource controlled by the CLK_REQ1 pin, and the EN3_SETx register defines

the resources controlled by the CLK_REQ2 pin.

Define SLEEP pin polarity

Define SLEEP state behavior with the following registers:

KEEP_ON

ACTIVE

SET_OFF

DEF_VOLT

Process pending interrupts or mask interrupts

Enable SLEEP function: Set SLEEP_ENABLE = 1b

Activate the SLEEP state with the

SLEEP pin (active HIGH or LOW)

Mask the INT output (no interrupt possible in the SLEEP

state)

Set any of the following defined resources to SLEEP:

Process

Sleep sequence

• Set to Eco-mode

• Set OFF

• Keep ACTIVE

• Change voltage

Disable interfaces and thermal monitor

SLEEP

Wait for the SLEEP signal to go inactive.

1) Enable interfaces and thermal monitor

2) Wake-up resources from Eco-mode

3) Enable resources which were OFF according to the

power-up sequence

4) Wake-up of all resources that were enabled by software

before entering the SLEEP state

5) Unmask the interrupt output pin

Process

Exit sleep

sequence

Deactivate the SLEEP state with the

SLEEP pin (active HIGH or LOW)

ACTIVE

Figure 8-6. SLEEP Flow for CONFIG2 Pin Shorted LDOAO

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CONFIG2 pin shorted to LDOAO

ACTIVE

Turn-off event

(PWRHOLD = 0b)

1) Assert nRESPWRON

2) Disable resources based on the

PWR_OFF_SEQ bit in the DEVCTRL register

3) Disable interfaces and thermal monitor

Process

turn-off sequence

LOAD_OTP = 1b

LOAD_OTP = 0b

CONFIG < 200-µs

delay

Load settings from OTP and configuration pins.

OFF

Figure 8-7. SHUTDOWN Flow for CONFIG2 Pin Shorted to LDOAO

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CONFIG2 shorted to GND

Unmask VMON Interrupt (VMON_IT_MSK bit in

register INT_MSK set to 0b)

ACTIVE

Turn-off event (VMON_IN

below threshold)

Generate Interrupt

Set INT1 pin LOW

Delay by VMON_DELAY[1:0]

1) Assert nRESPWRON (VMON_OUT = LOW)

2) Wait 2 ms

3) Disable all resources based on the

PWR_OFF_SEQ bit in the DEVCTRL register

4) Disable interfaces and thermal monitor

Process turn-off

sequence

LOAD_OTP = 0b

LOAD_OTP = 1b

nRESIN set low for > 10 ms if the nPWRON

pin configured as nRESIN in OTP

CONFIG < 200-µs

delay

Load settings from OTP and configuration pins

OFF

Figure 8-8. SHUTDOWN Flow for CONFIG2 Pin Shorted to GND

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8.4.3 Implementation of Internal Power-Up and Power-Down Sequencing

The TPS659128x can internally enable resources during power up (going to the ON state) and power down

(going to the OFF state), and for entering and exiting the SLEEP state. The internal power sequencing is defined

in the factory programmed OTP memory. The sequencing can enable resources in 15 time slots during power

up and power down. A resource can be associated to any of these 15 time slots that will be processed in the

opposite direction during power down. Four settings are programmable for the delay and are effective for all 15

time slots:

Table 8-1. TSLOT_LENGTH Delay Options

Bits

00b

01b

10b

11b

Delay

30 µs

200 µs

500 µs

2 ms

Resources can include:

•

Step-down converters

LDO regulators

32-kHz clock output

nRESPWRON output

Resources that are not part of the automatic sequencing can be configured such that they are enabled by

external pins or by their enable bit in the register set once the device is in the ACTIVE or SLEEP states.

Resources that are enabled automatically should not be assigned to an external enable pin. A break point

can be defined which stops power-up sequencing and allows power-up sequencing to resume once voltage

monitoring conditions are met. This break point prevents power up until the voltage of the voltage monitors

exceeds a certain limit.

As shown in Figure 8-9, resources can be mapped to any of the time slots with none, one, or multiple resources

for any time slot.

Note

Figure 8-9 is an example of the programmability of the sequencing and does not match the settings

for a particular OTP of the device. For individual part-number settings, refer to the application report

specific for each orderable part number.

For entry to the SLEEP state and exit from the SLEEP state, only three time slots are used with a 120-µs delay

between time slots.

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Power Up

Power Down

1

2

3

4

5

14

15

DCDC1 DCDC3

DCDC2 LDO3

nRES-

PWRON

DCDC4 LDO5

PWRHOLD

V_DCDC1

V_DCDC2

V_DCDC3

V_LDO3

TSLOT_LENGTH[1:0]

V_DCDC4

V_LDO5

nRESPWRON

Figure 8-9. Internal Power-Up Example

8.4.4 Summary of CONFIG2, Device State, and Enable Pin Settings on Regulators

The behavior of the regulators is impacted by the state of various settings which can be modified by hardware,

software, and part number specific settings. The LDOs are more simplistic and are shown first. The DCDCs are

shown second and include an additional resource mode (force PWM). Both cases also indicate which voltage

setting register (xxx_OP or xxx_AVS) is used. The following tables assume the LDOx_ENABLE bit or DCDCx

ENABLE bit is set to 1b. Setting this bit to 0b will cause the resource to be off in all cases.

8.4.4.1 LDO Mode Summary

The LDO regulators can be off, on in normal-mode, or on in Eco-mode. Which mode the regulator is in depends

on several variables which can be defined by the part-number specific settings, the host processor software,

and the hardware configuration. The configurations are best broken into two categories. The first configuration

applies when a regulator has been assigned to an external pin by the host processor or by OTP in any of the

ENx_SETx registers. This configuration has few dependencies. The second configuration applies to all other

cases. A summary of these two can be found in the following tables.

Table 8-2. LDO Mode Summary - Assigned LDO

Assigned Pin(s)

KEEP_ON Bit⁽²⁾

SET_OFF Bit⁽²⁾

Resource Mode

State⁽¹⁾

Low

0b

1b

Off

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Table 8-2. LDO Mode Summary - Assigned LDO (continued)

Assigned Pin(s)

KEEP_ON Bit⁽²⁾

SET_OFF Bit⁽²⁾

Resource Mode

State⁽¹⁾

Low

0b

1b

x

0b

x

Eco

Low

Normal

High

x

(1) This is an OR of all assigned pins. If any of the assigned pins goes high, the pin state is considered high.

(2) There is a separate bit for each regulator.

Table 8-3. LDO Mode Summary - Unassigned LDO

KEEP_ON

CONFIG2

Device State

SET_OFF Bit⁽¹⁾

ECO Bit⁽¹⁾

Resource Mode

Bit⁽¹⁾

GND

—

x

0

1

x

0

1

x

0

1

0

1

x

0

1

Normal

Eco

GND

—

LDOAO

ACTIVE

SLEEP

Normal

Eco

Off

Normal

Eco

(1) There is a separate bit for each regulator.

8.4.4.2 DCDC Mode Summary

The DCDC regulators are similar to the LDO regulators, but they have an additional on state option to choose

between auto and force PWM modes.

Table 8-4. DCDC Mode Summary - Assigned DCDC

Assigned

KEEP_ON

Bit⁽²⁾

DCDCx_MODE Bit⁽²⁾

SET_OFF Bit⁽²⁾

Resource Mode

Pin(s) State⁽¹⁾

Low

High

x

0

1

0

1

0

1

0

1

x

1

0

x

0

x

Off

Eco

Auto

PWM

Auto

PWM

(1) This is an OR of all assigned pins. If any of the assigned pins goes high, the pin state is considered high.

(2) There is a separate bit for each regulator.

Table 8-5. DCDC Mode Summary - Unassigned DCDC

KEEP_ON

CONFIG2

Device State

SET_OFF Bit⁽¹⁾

DCDCx_MODE Bit⁽¹⁾ECO Bit⁽¹⁾

Resource Mode

Bit⁽¹⁾

GND

—

x

0

x

0

1

0

1

0

1

0

1

x

0

1

x

0

1

x

Auto

Eco

—

GND

—

PWM

Auto

Eco

LDOAO

ACTIVE

SLEEP

PWM

Eco

PWM

Off

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Table 8-5. DCDC Mode Summary - Unassigned DCDC (continued)

KEEP_ON

Bit⁽¹⁾

CONFIG2

Device State

SET_OFF Bit⁽¹⁾

DCDCx_MODE Bit⁽¹⁾ECO Bit⁽¹⁾

Resource Mode

LDOAO

SLEEP

1

x

0

1

0

1

x

Auto

Eco

PWM

(1) There is a separate bit for each regulator.

8.4.4.3 Voltage Selection Summary

All four DCDC regulators have two voltage register options, one located in the DCDCx_OP register and one

in the DCDCx_AVS register. The first four LDOs (LDO1, LDO2, LDO3, and LDO4) also have LDOx_OP and

LDOx_AVS registers. The selection of which voltage is used can be summarized in the following table.

Table 8-6. Voltage Selection Summary

Assigned Pin(s) State or

Device State⁽¹⁾

SELREG

Bit⁽²⁾

CONFIG2

DEF_VOLT Bit⁽²⁾

DCDCx_SEL Pin⁽³⁾

Voltage

GND

—

x

1

0

1

0

x

1

0

1

_AVS

_OP

GND

—

0

LDOAO

High or ACTIVE

0 or SLEEP

—

_AVS

_OP

_AVS

_OP

(1) For any regulators which are set in an ENx_SETx register, this is an OR of all assigned pins. If any of the assigned pins goes high, the

pin state is considered high. For any regulators which are not set in an ENx_SETx register, the device state is used.

(2) There is a separate bit for each regulator.

(3) For LDO1, LDO2, LDO3, and LDO4, this is based on the DEF_VOLT_MAPPING register.

8.4.5 Details of CONFIG2, Device State, and Enable Pin Settings on Regulators

The full details of the behavior of the device based on the above signals and settings is outlined below.

8.4.5.1 EN1, EN2, EN3, and EN4 Resources Control

The ENx control signals can turn resources on and off as well as setting them into Eco-mode or changing the

output voltage register from _AVS to _OP. Assigning several resources to one ENx control signal is possible.

Assigning a resource to several ENx control signals is also possible. The inputs are connected to an OR gate, so

if any assigned ENx pin is high, the assigned resource is considered enabled. Default configuration of the ENx

control signals is done in OTP memory; however, changing the ENx settings after power up is possible through

the ENx_SETx registers. The ENx control signals are effective only in the ACTIVE or SLEEP state. For more

information on how the pin status on the ENx pin is interpreted, see Section 8.4.5.4.

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ENx_SET

(EPROM)

ENABLE RESx

EN1

RESx_REG

ENx

RESx_REG

Figure 8-10. ENx Architecture

8.4.5.2 Device SLEEP State Control

The sleep control input on the SLEEP pin is used to move the device into the SLEEP state where the resources

behavior (DC-DC converters, LDO regulators, 32-kHz clock output, and thermal monitor) are defined by the

SET_OFF, KEEP_ON, and DEF_VOLT registers. The SLEEP pin is only active if the SLEEP_ENABLE bit in the

DEVCTRL2 register is set to 1b and all unmasked interrupts are cleared. Otherwise, the state of the SLEEP

pin is ignored. Additionally, the polarity of the SLEEP pin is controlled by the SLEEP_POL bit in the DEVCTRL2

register.

8.4.5.3 SET_OFF, KEEP_ON, and DEF_VOLT Registers Used in SLEEP State with CONFIG2 Pin Shorted

to LDOAO

The DCDC1, DCDC2, DCDC3, and DCDC4 converters and LDO1, LDO2, LDO3, and LDO4 regulators allow

changing the output voltage depending on the ACTIVE state versus SLEEP state. To program the SET_OFF,

KEEP_ON, and DEF_VOLT registers:

•

Keep the resource enabled in the SLEEP state by setting the KEEP_ON bit to 1b. The SET_OFF bit is

ignored in this case. The DEF_VOLT bit will determine whether _OP (0b) or _AVS (1b) voltage is used in this

case.

•

Set the resource to Eco-mode in the SLEEP state by setting the SET_OFF bit to 0b and the KEEP_ON bit to

0b. The DEF_VOLT bit will determine whether _OP (0b) or _AVS (1b) voltage is used in this case.

Turn the resource off in the SLEEP state by setting the SET_OFF bit to 1b and the KEEP_ON bit to 0b.

8.4.5.4 SET_OFF, KEEP_ON, and DEF_VOLT Registers Used for Resources Assigned to an External

Enable Pin with CONFIG2 Pin Shorted to LDOAO

As described in Section 8.4.3, a resource can be assigned to an enable pin. In this case, the SLEEP state of

the device has no effect on an assigned resource. Instead, the behavior of the resource is defined by the state

of the enable pin. The SET_OFF, KEEP_ON, and DEF_VOLT registers are remapped and used to define how a

resource functions when the enable pin is set low or is set high. When the resource's assigned ENx pin is high,

the assigned resource behaves as if the device was in the ACTIVE state. When the resource's assigned ENx pin

is low, the assigned resource behaves as if the device was in the SLEEP state. To control the resource:

•

The resource is enabled when the ENx pin is set high. The SET_OFF and KEEP_OFF bits are ignored in this

case.

Enable the resource when the ENx pin is set low by setting the KEEP_ON bit to 1b. The SET_OFF bit is

ignored in this case.

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•

Disable the resource when the ENx pin is set low by setting the SET_OFF bit to 1b and the KEEP_ON bit to

0b.

Set the resource to Eco-mode when the ENx pin is set low by setting the SET_OFF bit to 0b and the

KEEP_ON bit to 0b.

Change the output voltage of a resource when the ENx pin is set low:

– Set the DEF_VOLT bit to 0b and the voltage will be defined by the _OP register.

– Set the DEF_VOLT bit to 1b and the voltage will be defined by the _AVS register.

8.4.5.5 SET_OFF, KEEP_ON, and DEF_VOLT Registers Used for Resources Assigned to Pins PWR_REQ,

CLK_REQ1 and CLK_REQ2 with CONFIG2 pin shorted to GND

With the CONFIG2 pin tied to GND, the ENx pins are used as the voltage-select pins (DCDCx_SEL) for the

DC-DC converters and LDO regulators assigned to these pins by the DEF_VOLT_MAPPING register. These

pins are only used to switch the output voltage between two values as defined in the _OP (DCDCx_SEL pin set

to 0) and _AVS (DCDCx_SEL pin set to 1) registers.

The basic function of enabling or disabling resources is remapped to the PWR_REQ, CLK_REQ1, and

CLK_REQ2 pins. The pin function is managed by the ENx_SETx registers in the following list.

•

PWR_REQ: EN1_SETx

CLK_REQ1: EN2_SETx

CLK_REQ2: EN3_SETx

The EN4_SETx register is not used and should be set 0h.

8.4.5.6 Configuration Pins CONFIG1, CONFIG2, and DEF_SPI_I2C-GPIO

The TPS659128x device contains two banks of OTP memory that define the programmed default settings. The

CONFIG1 pin selects between these two banks of memory. The logic level at the CONFIG1 pin in the CONFIG

state determines which of the OTP banks is used. The content of that OTP bank is then copied to the user

registers to set all OTP configurable options, such as default voltages and power-up timing.

The CONFIG2 bit is used to remap functions to pins. When the CONFIG2 pin is shorted to LDOAO, the EN1,

EN2, EN3, EN4, SCL_AVS, SDA_AVS, and SLEEP pins are active. When the CONFIG2 pin is shorted to GND,

these pins are used as DCDCx_SEL, CLK_REQ1, CLK_REQ2, and PWR_REQ pins. Table 8-7 lists the default

and alternative pin functions.

Table 8-7. Pin Configuration Based on CONFIG2 Pin

CONFIG2

PINSHORTED TO GND;

CONFIG2 PIN

SHORTED TO LDOAO;

DEFAULT PIN USAGE

DEFAULT FUNCTION

ALTERNATE FUNCTION

ALTERNATE PIN

USAGE

Enable pin for a set of DC-DC converters and LDOs

defined by register EN1_SET1 and EN1_SET2 for

resources that are mapped to a pin, SET_OFFx,

KEEP_ONx and DEF_VOLT define behavior for the

case when EN1=0

DCDC1_SEL = 1b: output voltage is defined by

DCDC1_AVS register

DCDC1_SEL = 0b: output voltage is defined by

DCDC1_OP register

EN1

EN2

EN3

DCDC1_SEL

DCDC2_SEL

DCDC3_SEL

Enable pin for a set of DC-DC converters and LDOs

defined by register EN2_SET1 and EN2_SET2 for

resources that are mapped to a pin, SET_OFFx,

KEEP_ONx and DEF_VOLT define behavior for the

case when EN2=0

DCDC2_SEL = 1b: output voltage is defined by

DCDC2_AVS register

DCDC2_SEL = 0b: output voltage is defined by

DCDC2_OP register

Enable pin for a set of DC-DC converters and LDOs

defined by register EN3_SET1 and EN3_SET2 for

resources that are mapped to a pin, SET_OFFx,

KEEP_ONx and DEF_VOLT define behavior for the

case when EN3=0

DCDC3_SEL = 1b: output voltage is defined by

DCDC3_AVS register

DCDC3_SEL = 0b: output voltage is defined by

DCDC3_OP register

Enable pin for a set of DC-DC converters and LDOs

defined by register EN4_SET1 and EN4_SET2 for

resources that are mapped to a pin, SET_OFFx,

KEEP_ONx and DEF_VOLT define behavior for the

case when EN4=0

DCDC4_SEL = 1b: output voltage is defined by

DCDC4_AVS register

DCDC4_SEL = 0b: output voltage is defined by

DCDC4_OP register

EN4

DCDC4_SEL

PWR_REQ

Used to transition the device between the ACTIVE

and SLEEP states when there are no pending

interrupts and the SLEEP_ENABLE bit is set to 1b.

Polarity controlled by the SLEEP_POL bit.

Enable pin for a set of DC-DC converters and LDOs

Defined by register EN1_SET1 and EN1_SET2

SLEEP

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Table 8-7. Pin Configuration Based on CONFIG2 Pin (continued)

CONFIG2

PINSHORTED TO GND;

ALTERNATE PIN

USAGE

CONFIG2 PIN

SHORTED TO LDOAO;

DEFAULT PIN USAGE

DEFAULT FUNCTION

ALTERNATE FUNCTION

Clock input of the voltage scaling (AVS) I²C

interface

Enable pin for a set of DC-DC converters and LDOs

Defined by register EN2_SET1 and EN2_SET2

SCL_AVS

SDA_AVS

CLK_REQ1

CLK_REQ2

Data input/output of the voltage scaling (AVS) I²C

interface

Enable pin for a set of DC-DC converters and LDOs

Defined by register EN3_SET1 and EN3_SET2

The DEF_SPI_I2C-GPIO pin defines whether the SPI or the I²C interface is used as the standard

communication interface. Setting the DEF_SPI_I2C-GPIO to 0 defines SPI as the standard interface

associated to the SCL_SCK, SDA_MOSI, GPIO1_MISO, and GPIO2_CE pins. The CONFIG1, CONFIG2, and

DEF_SPI_I2C-GPIO pins should be tied to GND for a low level and to the LDOAO pin for a logic high level.

The CONFIG1, CONFIG2, and DEF_SPI_I2C-GPIO pins should not be switched in operation but hardwired to a

logic-low level (GND) or a logic-high level by connecting the pins to the LDOAO voltage.

8.4.6 Active Voltage Scaling Control

The output voltage of all the DCDC regulators, LDO1, LDO2, LDO3, and LDO4 can be changed during operation

to match the system requirements. For example, this feature is useful for processors looking to minimize power

loss or maximize performance. Alternatively, it can be used to select between different voltages based on the

system configuration. For example, if different DDR options are available, then voltage can be selected to match

the requirement of the DDR. The voltage can be changed in two different ways, outlined below.

8.4.6.1 Voltage-Scaling Interface Control Using _OP and _AVS Registers With SPI or I²C Interface

Typically, the standard SPI or I²C interface is used to communicate with the part. If there is a potential that the

added voltage scaling bus traffic would interfere with other operations, a dedicated I²C interface is available for

voltage scaling functionality. Resources are assigned to this interface by setting the DCDCx_AVS bits in the

I2C_SPI_CFG register. The interface works in three different modes.

•

With CONFIG2 shorted to LDOAO, the standard I²C or SPI voltage scaling interface can be used where

output voltage is set in the resource's AVS and OP registers and the SELREG and DEF_VOLT bits are used

to switch between the two voltage values.

•

With CONFIG2 shorted to LDOAO, the power-I²C voltage scaling interface can be used instead. It operates

the same as standard I²C but access to the DCDCx_OP and DCDCx_AVS registers of the assigned

regulators use an alternate I²C address and cannot be accessed through the standard I²C bus. This is

enabled with the DCDCx_AVS bits in the I2C_SPI_CFG register.

•

With CONFIG2 shorted to GND, DCDCx_SEL pins can be used as roof or floor configuration where the

DC-DC voltage switches between the value defined in the DCDCx_OP register and the DCDCx_AVS register.

The voltage slew rate of the DCDCx regulators reaching a new programmed value is programmable though the

TSTEP bits located in the DCDCx_CTRL registers.

Both I²C interfaces are compliant with HS-I²C specification (100 kbits/s, 400 kbits/s, or 3.4 Mbits/s)

Shorting the CONFIG1 pin to GND selects OTP option A. Shorting the CONFIG1 pin to LDOAO selects the OTP

option B. These values are loaded only during the device CONFIG state.

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AVS and GP

I²C Select

Step

AVS I²C

GP I²C

AVS Voltage

OP Voltage

Dcdc_ctrl

Discharge

(check if needed)

Current Voltage

Ramp

OTP Option B

SLEEP or CMD

OTP Option A

CONFIG1

Figure 8-11. DC-DC Voltage Scaling Architecture

8.4.6.2 Voltage Scaling Using the VCON Decoder on VCON_PWM and VCON_CLK Pins

For specific processors, there is an option to set the voltage using analog signals, rather than I²C or SPI. For

such processors, the output voltage control for the DCDC1 converter can be controlled by the VCON pins when

the VCON_ENABLE bit in the DCDC1_CTRLregister is set to 1b.

When enabled, VCON sets the voltage based on the VCON_PWM signal duration during 32 cycles of the

VCON_CLK signal. The VCON decoder validates that the generated output voltage does not exceed 1.1 V when

a 25-mV step size is selected. For PWM ratios 0:32 to 7:32, the output voltage is fixed at 1.1 V. Four ranges can

be selected by setting the VCON_RANGE[1:0] bits in the DCDC1_CTRL register.

The VCON_CLK and VCON_PWM signal must be active and one complete frame (32 clock cycles) must

be received by the TPS659128x device before it is enabled with the VCON_ENABLE bit. When the

VCON_ENABLE bit is set to 0b, the voltage setting is reverted back to the DCDC1_AVS or DCDC1_OP register

depending on the pins summarized in Table 8-6 and the range bits also revert back to the value set in the

DCDC1_LIMIT register. For VCON mode, the RANGE bits and MAX_SEL bits in the DCDC1_LIMIT register are

ignored.

The function calculates the desired converter voltage based on the incoming PWM information. The maximum

CLK frequency is 30 MHz. The period of the PWM signal is 1/32 of VCON_CLK. The decoding follows Equation

1.

V_OUT= V_{RANGE_MAX}– Count × Step Size

(1)

where

•

V_OUTis the resulting converter voltage.

V_{RANGE_MAX}is the maximum voltage from the voltage range selected in the VCON_RANGE bits.

Count is the number of VCON_CLK cycles during which VCON_PWM is high within 32 clock cycles of

VCON_CLK.

•

Step Size is the step size from the voltage range selected in the VCON_RANGE bits

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0

1

2

3

4

5

6

7

30

31

0

1

VCON_CLK

VCON_PWM

Count = 1

VCON_PWM

Count = 2

VCON_PWM

Count = 31

Figure 8-12. VCON Voltage Scaling Architecture

8.4.7 VDDIO Voltage for Push-Pull Output Stages

A number of outputs are available that are push-pull outputs or can be configured as push-pull outputs. Any pin

with a push-pull output stage generates its output high level by the voltage applied to the VDDIO pin. The input

voltage range on the VDDIO pin is 1.6 V to 3.3 V with an UVLO threshold below 1.6 V. With a VDDIO voltage

below the UVLO threshold, the high-side driver of the push-pull output stages is disabled and the output default

goes back to open drain. The affected pins include:

•

nRESPWRON / VSUP_OUT push-pull or open drain defined by the nRESPWRON_OUTPUT bit in the

DEVCTRL register

•

INT1 push-pull or open drain defined by the INT_OUTPUT bit in the DEVCTRL2 register

GPIO1, GPIO2: push-pull only

GPIO3, GPIO4, GPIO5: push-pull or open drain managed by the GPIOx registers

OMAP_WDI_32k_OUT

8.4.8 Digital Signal Summary

The digital signals are defined as:

SLEEP

When all SLEEP conditions are met (the CONFIG2 pin is shorted to LDOAO, no pending

interrupts, and SLEEP_ENABLE bit set to 1b), the SLEEP pin can be used to enter the

SLEEP state which impacts LDO regulator and DC-DC converter behavior based on the

settings defined in the SET_OFF, KEEP_ON, and DEF_VOLT registers. An interrupt or a

change in the SLEEP pin level causes a transition back to the ACTIVE state. This input

signal is level sensitive and no debouncing is applied. The SLEEP pin is configurable and

is disabled by default, so at power up, its status is ignored. The SLEEP_ENABLE bit in the

DEVCTRL2 register is used to make the SLEEP pin active and its active level is changed

between active HIGH or active LOW using the SLEEP_POL bits. The SLEEP state can also

be entered using the DEV_SLP bit in the DEVCTRL register as long as no interrupts are

pending, however an interrupt must be unmasked to trigger a SLEEP-to-ACTIVE transition or

else the device will stay in the SLEEP state until the device enters the OFF state.

PWRHOLD

The PWRHOLD pin can be used as ON/OFF signal input when the nPWRON pin and

interrupt are not used or in parallel with these power-on conditions. The PWRHOLD pin can

also be used as an acknowledge (maintain power) of a power-up sequence triggered by

an interrupt or the falling edge of the nPWRON pin. The PWRHOLD input signal is level

sensitive and no debouncing is applied. The rising edge, falling edge, or both edges of the

PWRHOLD pin are highlighted through an associated interrupt if the interrupt is unmasked.

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NRESPWRON/ The NRESPWRON signal is used as the reset to the processor and is in the VDDIO domain.

VSUP_OUT

The signal is held low until the ACTIVE state is reached. For detailed timing, see the relevant

application note for the part number specific settings.

The VSUP_OUT signal is the output of the voltage monitor that can alternatively be used as

a reset to a processor. It can be included in the power sequencing such that the power-up

sequence is delayed until its output is HIGH or the device powers down when the output is

LOW.

32KCLKOUT

nPWRON

This signal is the output of the 32-kHz RC oscillator, which can be enabled during the power-

on sequence. This signal can be enabled and disabled by setting the CLK32KOUT_EN bit in

the CLK32KOUT register when the device is in the ACTIVE state.

The nPWRON input is generally connected to an external button. A debounced falling edge

on this signal causes a transition from the OFF state to the ACTIVE state. If the device is in

the ACTIVE or SLEEP state, then a low level on this signal can generate an interrupt. If the

nPWRON signal is low for more than 5 seconds, one of the PWRON_LP_OFF bits are set

to 1b, and the corresponding PWRON_LP_IT interrupt is not acknowledged by the external

processor in 1 second, then the device goes to the OFF state. An OTP option is available to

have falling edge of nPWRON pin cause device reset. When used this way, it is described as

nRESIN.

INT1

The INT1 signal (active low) warns the host processor of any event that occurred on the

TPS659128x device. The host processor can then poll the interrupt from the interrupt status

register through I²C to identify the interrupt source. If the INT_POL bit is set to 0b, a low

level indicates an active interrupt, highlighted in the INT_STSx registers. An active Interrupt

flag generates a POWER ON enable condition pulse of 5 seconds only when the device is

in the OFF state (when the NRESPWRON signal is low). The POWER ON enable condition

pulse will occur only if the interrupt status bit is initially inactive (no previous interrupt pending

in the status register). The interrupt status register must be cleared first to allow device to

power off during the 5 second pulse duration. Any of the interrupt sources can be masked

programming INT_MSKx registers. The default setting is masking all interrupts. When an

interrupt is masked, its corresponding interrupt status bit is still updated, but the INT1 flag is

not activated. Interrupt source masking can be used to mask a device switch-on event. The

INT output can be programmed as push-pull or open drain output stage with either active

LOW or active HIGH output defined by two OTP settings.

GPIO1, GPIO2, The GPIOx signals are muxed with the LED and SPI. The GPIOx signal can be used for

GPIO3, GPIO4, event detection or control of external resources during power up.

GPIO5

VCCS/VIN_MON This signal is the input for the internal UVLO monitor. The block provides a selectable

low-battery warning as well as a undervoltage shutdown.

VCON_CLK,

VCON_PWM

These signals are the clock and data inputs for voltage scaling of the DCDC1 converter

using a custom PWM type voltage scaling. The feature is enabled by the VCON_ENABLE bit

in the DCDC1_CTRL register. When enabled, voltage scaling through the DCDC1_OP and

DCDC1_AVS registers is blocked.

CLK, MOSI,

MISO, CE

These signals are the clock, chip enable (CE), master-in slave-out (MISO), and master-out

slave-in (MOSI) pins for the SPI . The pins are shared with the standard I²C interface SCL

and SDA and GPIO1 and GPIO2.

DEF_SPI_I2C-

GPIO

This signal defines whether multifunction pins are used for the SPI or for the I²C interface

and GPIOs. When the DEF_SPI_I2C-GPIO pin is set to low, the function is assigned to the

SPI on the CLK, MOSI, MISO, and CE pins. When the DEF_SPI_I2C-GPIO pin is set to

high, the function is assigned to the I²C interface and GPIOs on the SCL, SDA, GPIO1, and

GPIO2 pins.

SCL_AVS,

SDA_AVS

These signals are used in the power I²C interface, typically used for DVS on the step-down

converters. Each step-down converter has a bit to switch the voltage scaling registers from

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the standard I²C interface or SPI to the power-I²C interface. When switched to the power-I²C,

the register is blocked for access through the standard interface.

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8.4.9 Load Switch

The load switch on the TPS659128x device can be used as the following:

•

Bypass switch for the DCDC4 converter

Current limited switch if the TPS659128x device is used in USB-powered applications

A switch to turn on and off high current loads such as SD cards

V_(LDOAO)

V_CC

nPWRON

1 …F

V_(LDOAO)

PWRHOLD⁽¹⁾

LSI

From USB

(5 V)

LSO

Load Switch

C⁽²⁾

V_(LDOAO)

EN_LS0

EN_LS1

VINDCDC_ANA

VINDCDC1,2,3,4

(To force the

load switch ON)

C_INx

4x 10 µF

Lx

1 µH

SWx

DCDCx

C_OUTDCDCx

VDCDCx

PGNDx

A. Tie the PWRHOLD pin to LDOAO voltage to turn on automatically when 5 V is applied.

B. The capacitor size is dependent on buffer requirements.

Figure 8-13. Load Switch Connected as USB Input Current Limited Switch

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V_CC

1 …F

VINDCDC_ANA

LSI

Input Voltage

Battery

LSO

Load Switch

EN_LS0⁽¹⁾

V_(LDOAO)

EN_LS1⁽¹⁾

VINDCDC1,2,3,4

C_INx

4x 10 µF

1 µH

SW4

DCDC4

C_OUTDCDC4

VDCDC4

PGND4

A. The EN_LS1 pin must be high and the EN_LS0 pin must be low to auto-enable the load switch based on the comparator in DCDC4.

Figure 8-14. Load Switch Connected as BYPASS Switch for DCDC4

The LOADSWITCH register allows the load switch to be used as a bypass switch on the DCDC4 converter or

as a current limited switch. Four programmable current limits are available from 90 mA (typical) to 2.5 A with

the default current defined by an OTP setting. The enable bits are mapped to the external pins, EN_LS0 and

EN_LS1. The status of the pins is copied to the register in the CONFIG state and therefore the usage of the load

switch can be externally predefined. In the ACTIVE state (or SLEEP state) the functionality of the load switch

is controlled by the ENABLE0 and ENABLE1 bits only to turn the load switch on, turn it off, or assign it to a

comparator as a bypass switch for the DCDC4 converter. When the enable function is set to the comparator, it is

auto-enabled based on the voltage differential of V_INto V_OUTon the DCDC4 step-down converter.

Two additional features are available in case the load switch is used as a bypass switch for the DCDC4

converter. The following features are enabled with the LOADSWITCH:ENABLE[1:0] bit by setting it to either 10b

or 11b:

•

Forced PWM mode of the DCDC4 converter is blocked if the bypass switch is closed

The bypass switch is opened automatically when a overvoltage condition happens. The

LOADSWITCH:ENABLE[1:0] bit is automatically set 00b in an overvoltage event so the switch is opened.

In applications where the load switch is used as an USB-input current limited switch or as a load switch on

the output of a DC-DC converter to LDO regulator, the previously listed features must be disabled. This case

happens when the load switch is enabled by setting the LOADSWITCH:ENABLE[1:0] bit to 01b.

For more information, see the LOADSWITCH register in Register Descriptions.

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OVP threshold

approximately 4.18 V

Approximately 250-mV hysteresis

LSI

V_DCDC4

I²C or SPI

LOADSWITCH:ENABLE[1:0]

00b

11b

00b

DCDC4_MODE = 1b

Effective force PWM

OVP

Bypass switch enabled

A. OVP enable = LOADSWITCH:ENABLE[1:0] = 10b or 11b LOADSWITCH:ENABLE[1] = 0b → OVP enable = OVP = 0 If OVP hysteresis

< V_DCDC4< OVP when LOADSWITCH:ENABLE[1] goes high, OVP indicates V_DCDC4< OVP

Figure 8-15. Load Switch Timing for LOADSWITCH:ENABLE[1:0] = 10b or 11b

8.4.10 LED Driver

The GPIO3, GPIO4, and GPIO5 resources can alternatively be configured to drive the LEDs by setting

the GPIO_SEL bit to 1b in the GPIOx register. This setting switches the output stage to a current sink

controlled by the LED control registers (LEDx_CTRLx, LED_RAMP_UP_TIME, LED_RAMP_DOWN_TIME, and

LED_SEQ_EN). The LEDs are enabled in the LED_SEQ_EN register. The LED current sink is pulse-width

modulated with the duty cycle defined by the LEDx_PWM[4:0] bit in the LEDx_CTRL7 register. All three GPIOs

should either be assigned as an LED driver or as a standard GPIO.

To turn on LEDA with a constant current of 10 mA:

•

Set the GPIO as an LED current sink output by setting the GPIOA:GPIO_SEL bit to 1.

Set the constant current to 10 mA by setting the LEDA_CTRL1:LEDA_CURRENT[3:0] bit to 0100b.

Set the PWM duty cycle to 100% by setting the LEDA_CTRL7:LEDA_PWM[4:0] bit to 11111b.

Enable the LEDA current sink by setting the LED_SEQ_EN:LEDA_EN bit to 1b.

In addition to turning on and turning off an LED, the LED driver allows the user to set LED sequence to perform

a flash sequence in the hardware by enabling the flash sequencer. Setting the LEDx_SEQ_EN bit enables the

flash sequencer for each of the three LEDs.

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LED Sequence

T1

T2

T3

T4

TP

Zoom

Current = LED_CURRENT[3:0]

Current = 1

Current = 0

LED_IOUT[3:0]

Current = 0

LED_ON

Led_on_time

Ramp_up_step_time

Ramp_down_step_time

T1, T2, T3, T4 : 0, 1 ...127 × 64 ms : reg ledx_t1, ledx_t2 ….

Tp

: 0, 1 …127 × 64 ms : reg ledx_tp

Ramp step time : 0, 1 … 31 × 8 ms : reg led_ramp_up_time, led_ramp_down_time

Figure 8-16. LED Sequencer

The LED driver allows the user to set a DC current from 2 mA to 20 mA for each LED. In addition to this ability,

an LED flash sequence is programmable and defined by the time slots T1, T2, T3, T4, and TP. Within these

time slots, the LED can be turned on as defined by the LEDx_ON_TIME bit with a defined ramp-up slope set

by the LED_RAMP_UP register and a defined ramp-down slope set by the LED_RAMP_DOWN register. The

slopes are set to the same value for all three LEDs but other parameters are programmable independently.

Figure 8-16 shows an LED flash cycle. The ramp enable bits define whether the current immediately steps to

its defined value (set by the LEDx_CURRENT[3:0] bit) or ramps with a certain slope. If the LEDx_RAMP_EN bit

is set to 0b during a sequence, the current immediately goes to the value defined by the LEDx_I[3:0] bit. If the

LEDx_RAMP_EN bit is set to 1b during a sequence, the current steps up and down to the value defined by the

LEDx_I[3:0] bit with a certain slope.

In addition, the LED current is pulse-width modulated with a duty cycle defined in the LEDx_CTRL7 register.

For the LED driver to operate properly, the time for RAMP_UP + LED_ON + RAMP_DOWN must be smaller

than the sequence Tn (with n = 1, 2, 3, 4, P).

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8.4.11 Thermal Monitoring and Shutdown

Two thermal-protection modules monitor the junction temperature of the device against the respective

thresholds:

•

Hot-die temperature threshold

Thermal shutdown temperature thresholds

When the hot-die temperature threshold is reached, an interrupt is sent to the software (SW) to close the

noncritical running tasks.

The output of both thermal protection modules is logically ORed. When the thermal shutdown temperature

threshold is reached, the TPS659128x device is set under reset and a transition to the OFF state is initiated.

Then the POWER ON enable conditions of the device are not taken into consideration until the die temperature

has decreased below the hot-die threshold. A hysteresis is applied to the hot-die and shutdown threshold when

detecting a falling edge of temperature, and both detections are debounced to avoid any parasitic detection. The

TPS659128x device allows the user to program four hot-die temperature thresholds to increase the flexibility of

the system.

By default, the thermal protection is enabled in the ACTIVE state, but it can be disabled through programming

the THRM_REG register. The thermal protection is automatically enabled during a transition from the OFF state

to the ACTIVE state and is kept enabled in the OFF state after a switch-off sequence caused by a thermal

shutdown event. A transition to the OFF state sequence caused by a thermal shutdown event is highlighted in

the INT_STS_REG status register. Recovery from this OFF state is initiated (switch-on sequence) when the die

temperature falls below the hot-die temperature threshold.

The threshold detection state for the hot-die and thermal shutdown temperature can be monitored or masked

by reading or programming the THRM_REG register. A hot-die interrupt can be masked by programming the

INT_MSK_REG register.

8.4.12 Interfaces

The TPS659128x device has three available interfaces which are a high-speed I²C interface that has access

to all register, a SPI that can optionally be used to access all registers, and a high-speed power I²C interface

that can be used to dynamically change the output voltage of the DC-DC converters. The power I²C interface

only has access to the voltage scaling registers of the DC-DC converters. If it is activated by a selection bit, the

registers it is using are blocked for the general-purpose I²C or SPI. All interfaces are active only in the ACTIVE

state. In all other states, the interfaces are held in a reset and cannot be used to access the device.

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8.4.12.1 Serial Peripheral Interface

The serial peripheral interface (SPI ) uses four signals: a chip enable (SPI_CE), the clock from the bus master

(SPI_CLK), an input port (SPI_MOSI), and an output port (SPI_MISO). The read-write (R/W) bit is followed by an

8-bit register address followed by 7 bits of unused bits followed by the data bits. The MISO output is set to high

impedance when the TPS659128x device is not addressed by setting the CE pin LOW which allows multiple

slaves on the SPI bus.

Single Write

SPI Chip

Enable

SPI Clock

SPI Data Input

(MOSI)

W/nR

Address (8 bits)

Unused bits (7 bits)

Data (8 bits)

SPI Data Output

(MISO)

ERROR (15 bits)

Single Read

SPI Chip

Enable

SPI Clock

SPI Data Input

(MOSI)

Address (8 bits)

Unused bits (7 bits)

ERROR (bits)

Don‘t care

W/nR

SPI Data Output

(MISO)

Data (8 bits)

Figure 8-17. SPI READ and WRITE Protocol

Burst Write

SPI Clock Chip

Enable

SPI Clock

SPI Data Input

(MOSI)

Unused bit (7 bits)

Data (8 bits)

Address (8 bits)

Data (8 bits)

Data (8)

Data (8 bits)

W/nR

SPI Data Input

(MISO)

Don‘t care

Burst Read

SPI Clock Chip

Enable

SPI Clock

SPI Data Input

(MOSI)

Address (8 bits)

Unused bit (7 bits)

Don‘t care

W/nR

SPI Data Input

(MISO)

Don‘t care

Data (8 bits)

Figure 8-18. SPI BURST READ and BURST WRITE Protocol

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8.4.12.2 I²C Interface

I²C is a 2-wire serial interface developed by NXP (formerly Philips Semiconductor) (see I²C-Bus Specification

and user manual). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When

the bus is idle, both the SDA and SCL lines are pulled high. All the I²C-compatible devices connect to the I²C

bus through open-drain I/O pins, the SDA pin, and the SCL pin. A master device, usually a microcontroller or

a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device

addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A

slave device receives, transmits data, or does both on the bus under control of the master device.

The TPS659128x device works as a slave and supports the following data transfer modes, as defined in the

I²C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (up to 3.4

Mbps in write mode). The interface adds flexibility to the power-supply solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents are

loaded when voltage is applied to the TPS659128x device that is higher than the UVLO level of 2.4 V. When the

device is in the ACTIVE state and is turned off, the LOAD-OTP bit [bit 6 in the DEVCONTROL register] forces

a reload of the registers when the LOAD-OTP bit is set to 1b (default). When the LOAD-OTP bit is set to 0b,

register content is not changed unless the supply voltage drops below the UVLO threshold. The I²C interface

runs off of an internal oscillator that is automatically enabled when an access to the interface happens.

The data transfer protocol for standard and fast modes is exactly the same, therefore, they are referred to as

F/S-mode in this document. The protocol for high-speed mode is different from the F/S mode, and it is referred to

as HS mode. The TPS659128x device supports 7-bit addressing; 10-bit addressing and general call address are

not supported.

8.4.12.2.1 I²C Implementation

Two I²C interfaces are available on the TPS659128x device. One interface is for general purpose use and is

referred to as the general-purpose or standard I²C interface. The other interface is exclusively used for voltage

scaling on the DC-DC converters and is referred to as AVS- or power-I²C interface.

The TPS659128x device has a 7-bit address with the LSB factory programmable.

The device address for the STANDARD-I²C interface is typically set to 0101101b.

The device address for the AVS-I²C interface is typically set to 0010011b.

Other default addresses can be factory programmed.

8.4.12.2.2 F/S-Mode Protocol

The master device initiates data transfer by generating a start condition. The start condition is when a high-to-

low transition occurs on the SDA line while the SCL pin is high (see Figure 8-19). All I²C-compatible devices

should recognize a start condition.

The master device then generates the SCL pulses, and transmits the 7-bit address followed by the read-write

direction (R/W bit) on the SDA line. During all transmissions, the master device ensures that data is valid. A valid

data condition requires the SDA line to be stable during the entire high period of the clock pulse (see

Figure 8-20). All devices recognize the address sent by the master and compare it to their internal fixed

addresses. Only the slave device with a matching address generates an acknowledge (see Figure 8-21) by

pulling the SDA line low during the entire high period of the ninth SCL cycle. This acknowledge confirms to the

master that the communication link with the slave has been established.

The master device generates further SCL cycles to either transmit data to the slave device (R/W bit set to 0b) or

receive data from the slave device (R/W bit set to 1b). In either case, the receiver must acknowledge the data

sent by the transmitter. An acknowledge signal can either be generated by the master device or by the slave

device, depending on which one is the receiver. Valid 9-bit data sequences consisting of 8-bit data and 1-bit

acknowledge can continue for as long as necessary.

To signal the end of the data transfer, the master device generates a stop condition by pulling the SDA line

from low to high while the SCL line is high (see Figure 8-19). This process releases the bus and stops the

communication link with the addressed slave. All I²C-compatible devices must recognize the stop condition.

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Upon the receipt of a stop condition, the bus is released, and all slave devices wait for a start condition followed

by a matching address

Attempting to read data from register addresses not listed in Register Descriptions results in a readout of FFh.

8.4.12.2.3 H/S-Mode Protocol

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup devices.

The master device generates a start condition followed by a valid serial byte containing the HS master code

00001XXX. This transmission is made in F/S mode at no more than 400 Kbps. No device is allowed to

acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support

3.4-Mbps operation.

The master device then generates a repeated start condition (a repeated start condition has the same timing

as the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 3.4 Mbps are allowed. A stop condition ends the HS mode and switches all the

internal settings of the slave devices to support the F/S mode. Instead of using a stop condition, repeated start

conditions are used to secure the bus in HS mode.

Attempting to read data from register addresses not listed in Register Descriptions results in a readout of FFh.

DATA

CLK

P

S

Stop

Condition

Start

Condition

Figure 8-19. START and STOP Conditions

Start Condition

DATA

CLK

Data Line Stable;

Data Valid

Change of Data Allowed

Figure 8-20. Bit Transfer on the Serial Interface

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Data Output

by Transmitter

Not Acknowledge

Acknowledge

Data Output

by Receiver

SCL From

Master

1

2

8

9

S

Clock Pulse for

Acknowledgement

Start

Condition

Figure 8-21. Acknowledge on the I²C Bus

Recognize START

or REPEATED

START Condition

Recognize STOP

or REPEATED

START Condition

Generate ACKNOWLEDGE

Signal

P

SDA

MSB

Acknowledgement

Signal From Slave

Sr

Address

R/W

SCL

1

2

7

8

9

1

2

3 - 8

9

ACK

Sr

Or

Sr

S

Or

Sr

Clock Line Held Low While

Interrupts are Serviced

START or

Repeated START

Condition

STOP or

REPEATED

START Condition

Figure 8-22. Bus Protocol

. . .

SCLK

SDAT

A5

A4 . . .

. . .

A6

A0

ACK

0

R7

ACK

A6

R0

ACK

0

D7

D6

D5

D0

ACK

R/W

0

1

0

Start

Stop

Data

Slave Address

Register Address

NOTE: SLAVE=TPS65912x

Figure 8-23. I²C Interface WRITE to TPS659128x; F/S Mode

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. . .

SCLK

SDAT

. . .

A6

A0

R/W ACK

R7

R0

ACK

0

A6

A0

R/W ACK

D7

D0

ACK

. . .

0

1

0

Start

Stop

Master Drives

ACK and

Stop

Slave Address

Slave Drives

the Data

Slave Address

Register Address

Repeated

Start

NOTE: SLAVE=TPS65912x

Figure 8-24. I²C Interface READ from TPS659128x; F/S Mode

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8.5 Register Maps

8.5.1 Register Descriptions

8.5.1.1 DCDC Registers (00h to 0Fh)

Table 8-8 lists the memory-mapped registers for the DCDC registers. All register offset addresses not listed in

Table 8-8 should be considered as reserved locations and the register contents should not be modified.

Table 8-8. DCDC Registers

Offset

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

Acronym

Register Name

Section

DCDC1_CTRL

DCDC2_CTRL

DCDC3_CTRL

DCDC4_CTRL

DCDC1_OP

DCDC1 Control Register

DCDC2 Control Register

DCDC3 Control Register

DCDC4 Control Register

DCDC1 OP Register

DCDC1 AVS Register

DCDC1 Limit Register

DCDC2 OP Register

DCDC2 AVS Register

DCDC2 Limit Register

DCDC3 OP Register

DCDC3 AVS Register

DCDC3 Limit Register

DCDC4 OP Register

DCDC4 AVS Register

DCDC4 Limit Register

Section 8.5.1.1.1

Section 8.5.1.1.2

Section 8.5.1.1.3

Section 8.5.1.1.4

Section 8.5.1.1.5

Section 8.5.1.1.6

Section 8.5.1.1.7

Section 8.5.1.1.8

Section 8.5.1.1.9

Section 8.5.1.1.10

Section 8.5.1.1.11

Section 8.5.1.1.12

Section 8.5.1.1.13

Section 8.5.1.1.14

Section 8.5.1.1.15

Section 8.5.1.1.16

DCDC1_AVS

DCDC1_LIMIT

DCDC2_OP

DCDC2_AVS

DCDC2_LIMIT

DCDC3_OP

DCDC3_AVS

DCDC3_LIMIT

DCDC4_OP

DCDC4_AVS

DCDC4_LIMIT

Complex bit access types are encoded to fit into small table cells. Table 8-9 shows the codes that are used for

access types in this section.

Table 8-9. DCDC Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

-OTP

-X

Bit reset value is defined in the

OTP memory

Bit determined by external

connection

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8.5.1.1.1 DCDC1_CTRL Register (Offset = 00h) [reset = OTP]

DCDC1_CTRL is shown in Table 8-10 and described in Table 8-11.

Return to Summary Table.

Register is reset on a POR event.

Table 8-10. DCDC1_CTRL Register

7

6

5

4

3

2

1

0

VCON_ENABL

E

VCON_RANGE[1:0]

R/W-OTP

TSTEP[2]

R/W-000b

DCDC1_MODE

R/W-OTP

RSVD

R-0b

R/W-OTP

Table 8-11. DCDC1_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

0b = Voltage scaling is done by the I²C registers or DCDC1_SEL pin

1b = Voltage scaling is done by the VCON pins, VCON_PWM and

VCON_CLK; the voltage table is automatically forced to RANGE[1:0]

= 00b; register contents in voltage scaling registers are ignored

7

VCON_ENABLE

R/W

OTP

6-5

VCON_RANGE[1:0]

R/W

OTP

00b = Sets output voltage range for VCON operation: 500 mV to

1100 mV with 25 mV steps; 24 steps

01b = Sets output voltage range for VCON operation: 700 mV to

1100 mV with 12.5 mV steps; 32 steps

10b = Sets output voltage range for VCON operation: 600 mV to

1000 mV with 12.5 mV steps; 32 steps

11b = Sets output voltage range for VCON operation: 500 mV to 900

mV with 12.5 mV steps; 32 steps

4-2

TSTEP[2:0]

R/W

000b

Time step: when changing the output voltage, the new value is

reached through successive voltage steps (if not bypassed). Table

8-18 shows the equivalent programmable slew rate of the output

voltage.

1

0

DCDC1_MODE

RSVD

R/W

R

OTP

0b

0b = Auto mode or Eco mode

1b = Force PWM mode

Unused bit, should be written to 0b.

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8.5.1.1.2 DCDC2_CTRL (Offset = 01h) [reset = OTP]

DCDC2_CTRL is shown in Table 8-12 and described in Table 8-13.

Return to Summary Table.

Register is reset on a POR event.

Table 8-12. DCDC2_CTRL Register

7

6

5

4

3

2

1

0

RSVD

R-000b

TSTEP[2:0]

R/W-000b

DCDC2_MODE

R/W-1b

RSVD

R-0b

Table 8-13. DCDC2_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

R

000b

7-5

4-2

RSVD

Unused bit, should be written to 0b.

R/W

000b

Time step: when changing the output voltage, the new value is

reached through successive voltage steps (if not bypassed). Table

8-18 shows the equivalent programmable slew rate of the output

voltage.

TSTEP[2:0]

R/W

R

OTP

0b

0b = Auto mode or Eco mode

1b = Force PWM

1

0

DCDC2_MODE

RSVD

Unused bit, should be written to 0b.

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8.5.1.1.3 DCDC3_CTRL Register (Offset = 02h) [reset = OTP]

DCDC3_CTRL is shown in Table 8-14 and described in Table 8-15.

Return to Summary Table.

Register is reset on a POR event.

Table 8-14. DCDC3_CTRL Register

7

6

5

4

3

2

1

0

RSVD

TSTEP[2:0]

R/W-000b

DCDC3_MODE

R/W-OTP

RSVD

R-0b

R/W-000b

Table 8-15. DCDC3_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-2

RSVD

R/W

000b

Unused bit, should be written to 0b.

TSTEP[2:0]

R/W

000b

Time step: when changing the output voltage, the new value is

reached through successive voltage steps (if not bypassed). Table

8-18 shows the equivalent programmable slew rate of the output

voltage.

1

0

DCDC3_MODE

RSVD

R/W

R

OTP

0b

0b = Auto mode or Eco mode

1b = Force PWM

Unused bit, should be written to 0b.

8.5.1.1.4 DCDC4_CTRL Register (Offset = 03h) [reset = OTP]

DCDC4_CTRL is shown in Table 8-16 and described in Table 8-17.

Return to Summary Table.

Register is reset on a POR event.

Table 8-16. DCDC4_CTRL Register

7

6

5

4

3

2

1

0

RSVD

R-000b

TSTEP[2:0]

R/W-000b

DCDC4_MODE RAMP_TIME

R/W-OTP R/W-OTP

Table 8-17. DCDC4_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-2

RSVD

R

000b

Unused bit, should be written to 0b.

TSTEP[2:0]

R/W

000b

Time step: when changing the output voltage, the new value is

reached through successive voltage steps (if not bypassed). Table

8-18 shows the equivalent programmable slew rate of the output

voltage.

1

0

DCDC4_MODE

RAMP_TIME

R/W

OTP

0b = Auto mode or Eco mode

1b = Force PWM

For additional options for DCDC4, see the SPARE register (address

63h).

0b = Ramp time for initial start up is 200-µs minimum

1b = Ramp time for initial start up is 60-µs maximum

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Table 8-18. DCDCx TSTEP Settings

TSTEP[2:0]

Slew Rate (mV/µs)

000b

30

12.5

9.4

001b

010b

011b

7.5

100b

6.25

4.7

101b

110b

3.12

2.5

111b

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8.5.1.1.5 DCDC1_OP Register (Offset = 04h) [reset = OTP]

DCDC1_OP is shown in Table 8-19 and described in Table 8-20.

Return to Summary Table.

Register is reset on a POR event.

Table 8-19. DCDC1_OP Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SELREG

R/W-0b

SEL[5:0]

R/W-OTP

Table 8-20. DCDC1_OP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit, should be written to 0b.

6

SELREG

SEL[5:0]

R/W

0b

See Table 8-6

5-0

OTP

DCDC1 output voltage selection based on the RANGE[1:0] bit in the

DCDC1 register selections shown in Table 8-44 through Table 8-47.

8.5.1.1.6 DCDC1_AVS Register (Offset = 05h) [reset = OTP]

DCDC1_AVS is shown in Table 8-21 and described in Table 8-22.

Return to Summary Table.

Register is reset on a POR event.

Table 8-21. DCDC1_AVS Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-22. DCDC1_AVS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = DCDC1 disabled

1b = DCDC1 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.4.4.2

5-0

SEL[5:0]

OTP

DCDC1 output voltage selection based on the RANGE[1:0] bit in the

DCDC1 register selections shown in Table 8-44 through Table 8-47.

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8.5.1.1.7 DCDC1_LIMIT Register (Offset = 06h) [reset = OTP]

DCDC1_LIMIT is shown in Table 8-23 and described in Table 8-24.

Return to Summary Table.

Register is reset on a POR event.

Table 8-23. DCDC1_LIMIT Register

7

6

5

4

3

2

1

0

RANGE[1:0]

R/W-OTP

MAX_SEL[5:0]

R/W-OTP

Table 8-24. DCDC1_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RANGE[1:0]

R/W

OTP

Selects the output range. For more information, see Table 8-43.

5-0

MAX_SEL[5:0]

R/W

OTP

This bit defines the maximum value the output voltage in the

DCDC1_AVS or DCDC1_OP register can be programmed to; values

exceeding MAX_SEL will be replaced by the value defined in

MAX_SEL.

If the MAX_SEL bit is set by I²C or default OTP setting to any value

other than 0x3F or 0x00, the RANGE bits and the MAX_SEL bits are

locked until OTP is reloaded.

8.5.1.1.8 DCDC2_OP Register (Offset = 07h) [reset = OTP]

DCDC2_OP is shown in Table 8-25 and described in Table 8-26.

Return to Summary Table.

Register is reset on a POR event.

Table 8-25. DCDC2_OP Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SELREG

R/W-0b

SEL[5:0]

R/W-OTP

Table 8-26. DCDC2_OP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit, should be written to 0b.

6

SELREG

SEL[5:0]

R/W

0b

See Table 8-6

5-0

OTP

DCDC2 output voltage selection based on the RANGE[1:0] bit in the

DCDC2 register selections shown in Table 8-44 through Table 8-47.

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8.5.1.1.9 DCDC2_AVS Register (Offset = 08h) [reset = OTP]

DCDC2_AVS is shown in Table 8-27 and described in Table 8-28.

Return to Summary Table.

Register is reset on a POR event.

Table 8-27. DCDC2_AVS Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-28. DCDC2_AVS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = DCDC2 disabled

1b = DCDC2 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.4.4.2

5-0

SEL[5:0]

OTP

DCDC2 output voltage selection based on the RANGE[1:0] bit in the

DCDC2 register selections shown in Table 8-44 through Table 8-47.

8.5.1.1.10 DCDC2_LIMIT Register (Offset = 09h) [reset = OTP]

DCDC2_LIMIT is shown in Table 8-29 and described in Table 8-30.

Return to Summary Table.

Register is reset on a POR event.

Table 8-29. DCDC2_LIMIT Register

7

6

5

4

3

2

1

0

RANGE[1:0]

R/W-OTP

MAX_SEL[5:0]

R/W-OTP

Table 8-30. DCDC2_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-0

RANGE[1:0]

R/W

OTP

Selects the output range. For more information, see Table 8-43.

MAX_SEL[5:0]

R/W

OTP

This bit defines the maximum value the output voltage in the

DCDC2_AVS or DCDC2_OP register can be programmed to; values

exceeding MAX_SEL will be replaced by the value defined in

MAX_SEL.

If the MAX_SEL bit is set by I²C or default OTP setting to any value

other than 0x3F or 0x00, the RANGE bits and the MAX_SEL bits are

locked until OTP is reloaded.

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8.5.1.1.11 DCDC3_OP Register (Offset = 0Ah) [reset = OTP]

DCDC3_OP is shown in Table 8-31 and described in Table 8-32.

Return to Summary Table.

Register is reset on a POR event.

Table 8-31. DCDC3_OP Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SELREG

R/W-0b

SEL[5:0]

R/W-OTP

Table 8-32. DCDC3_OP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit, should be written to 0b.

6

SELREG

SEL[5:0]

R/W

0b

See Table 8-6

5-0

OTP

DCDC3 output voltage selection based on the RANGE[1:0] bit in the

DCDC3 register selections shown in Table 8-44 through Table 8-47.

8.5.1.1.12 DCDC3_AVS Register (Offset = 0Bh) [reset = OTP]

DCDC3_AVS is shown in Table 8-33 and described in Table 8-34.

Return to Summary Table.

Register is reset on a POR event.

Table 8-33. DCDC3_AVS Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-34. DCDC3_AVS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = DCDC3 disabled

1b = DCDC3 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.4.4.2

5-0

SEL[5:0]

OTP

DCDC3 output voltage selection based on the RANGE[1:0] bit in the

DCDC3 register selections shown in Table 8-44 through Table 8-47.

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8.5.1.1.13 DCDC3_LIMIT Register (Offset = 0Ch) [reset = OTP]

DCDC3_LIMIT is shown in Table 8-35 and described in Table 8-36.

Return to Summary Table.

Register is reset on a POR event.

Table 8-35. DCDC3_LIMIT Register

7

6

5

4

3

2

1

0

RANGE[1:0]

R/W-OTP

MAX_SEL[5:0]

R/W-OTP

Table 8-36. DCDC3_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-0

RANGE[1:0]

R/W

OTP

Selects the output range. For more information, see Table 8-43.

MAX_SEL[5:0]

R/W

OTP

This bit defines the maximum value the output voltage in the

DCDC3_AVS or DCDC3_OP register can be programmed to; values

exceeding MAX_SEL will be replaced by the value defined in

MAX_SEL.

If the MAX_SEL bit is set by I²C or default OTP setting to any value

other than 0x3F or 0x00, the RANGE bits and the MAX_SEL bits are

locked until OTP is reloaded.

8.5.1.1.14 DCDC4_OP Register (Offset = 0Dh) [reset = OTP]

DCDC4_OP is shown in Table 8-37 and described in Table 8-38.

Return to Summary Table.

Register is reset on a POR event.

Table 8-37. DCDC4_OP Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SELREG

R/W-0b

SEL[5:0]

R/W-OTP

Table 8-38. DCDC4_OP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit, should be written to 0b.

6

SELREG

SEL[5:0]

R/W

0b

See Table 8-6

5-0

OTP

This bit is for the DCDC4 output voltage selection based on the

RANGE[1:0] bit in the DCDC4 register selections shown in Table

8-44 through Table 8-47.

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8.5.1.1.15 DCDC4_AVS Register (Offset = 0Eh) [reset = OTP]

DCDC4_AVS is shown in Table 8-39 and described in Table 8-40.

Return to Summary Table.

Register is reset on a POR event.

Table 8-39. DCDC4_AVS Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-40. DCDC4_AVS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = DCDC4 disabled

1b = DCDC4 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.4.4.2

5-0

SEL[5:0]

OTP

This bit is for the DCDC4 output voltage selection based on the

RANGE[1:0] bit in the DCDC4 register selections shown in Table

8-44 through Table 8-47.

8.5.1.1.16 DCDC4_LIMIT Register (Offset = 0Fh) [reset = OTP]

DCDC4_LIMIT is shown in Table 8-41 and described in Table 8-42.

Return to Summary Table.

Register is reset on a POR event.

Table 8-41. DCDC4_LIMIT Register

7

6

5

4

3

2

1

0

RANGE[1:0]

R/W-OTP

MAX_SEL[5:0]

R/W-OTP

Table 8-42. DCDC4_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-0

RANGE[1:0]

R/W

OTP

Selects the output range. For more information, see Table 8-43.

MAX_SEL[5:0]

R/W

OTP

This bit defines the maximum value the output voltage in the

DCDC4_AVS or DCDC4_OP register can be programmed to; values

exceeding MAX_SEL will be replaced by the value defined in

MAX_SEL.

If the MAX_SEL bit is set by I²C or default OTP setting to any value

other than 0x3F or 0x00, the RANGE bits and the MAX_SEL bits are

locked until OTP is reloaded.

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8.5.1.1.17 V_DCDCxRange Settings

Table 8-43. V_DCDCxRange Settings

RANGE[1:0]

Output Voltage Range

00b

01b

10b

11b

0.5 V to 1.2875 V in 12.5 mV steps (See Table 8-44)

0.7 V to 1.4875 V in 12.5 mV steps (See Table 8-45)

0.5 V to 2.075 V in 25 mV steps (See Table 8-46)

0.5 V to 3.8 V in 50 mV steps (See Table 8-47)

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8.5.1.1.18 DCDCx Voltage Settings

Table 8-44. DCDCx Voltage Settings (RANGE[1:0] = 00b)

SEL(DCDCx)[5:0]

000000b

000001b

000010b

000011b

000100b

000101b

000110bb

000111b

001000b

001001b

001010b

001011b

001100b

001101b

001110b

001111b

010000b

010001b

010010b

010011b

010100b

010101b

010110b

010111b

011000b

011001b

011010b

011011b

011100b

011101b

011110b

011111b

VDCDCx (V)

0.5000

0.5125

0.5250

0.5375

0.5500

0.5625

0.5750

0.5875

0.6000

0.6125

0.6250

0.6375

0.6500

0.6625

0.6750

0.6875

0.7000

0.7125

0.725

SEL(DCDCx)[5:0]

100000b

100001b

100010b

100011b

100100b

100101b

100110b

100111b

101000b

101001b

101010b

101011b

101100b

101101b

101110b

101111b

110000b

110001b

110010b

110011b

110100b

110101b

110110b

110111b

111000b

111001b

111010b

111011b

111100b

111101b

111110b

111111b

VDCDCx (V)

0.9000

0.9125

0.9250

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.025

1.0375

1.0500

1.0625

1.0750

1.0875

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.2250

1.2375

1.2500

1.2625

1.2750

1.2875

0.7375

0.7500

0.7625

0.7750

0.7875

0.8000

0.8125

0.8250

0.8375

0.8500

0.8625

0.8750

0.8875

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Table 8-45. DCDCx Voltage Settings (RANGE[1:0] = 01b)

SEL(DCDCx)[5:0]

000000b

000001b

000010b

000011b

000100b

000101b

000110b

000111b

001000b

001001b

001010b

001011b

001100b

001101b

001110b

001111b

010000b

010001b

010010b

010011b

010100b

010101b

010110b

010111b

011000b

011001b

011010b

011011b

011100b

011101b

011110b

011111b

VDCDCx (V)

0.7000

0.7125

0.7250

0.7375

0.7500

0.7625

0.7750

0.7875

0.8000

0.8125

0.8250

0.8375

0.8500

0.8625

0.8750

0.8875

0.9000

0.9125

0.925

SEL(DCDCx)[5:0]

100000b

100001b

100010b

100011b

100100b

100101b

100110b

100111b

101000b

101001b

101010b

101011b

101100b

101101b

101110b

101111b

110000b

110001b

110010b

110011b

110100b

110101b

110110b

110111b

111000b

111001b

111010b

111011b

111100b

111101b

111110b

111111b

VDCDCx (V)

1.1000

1.1125

1.1250

1.1375

1.1500

1.1625

1.1750

1.1875

1.2000

1.2125

1.225

1.2375

1.2500

1.2625

1.2750

1.2875

1.3000

1.3125

1.3250

1.3375

1.3500

1.3625

1.3750

1.3875

1.4000

1.4125

1.4250

1.4375

1.4500

1.4625

1.4750

1.4875

0.9375

0.9500

0.9625

0.9750

0.9875

1.0000

1.0125

1.0250

1.0375

1.0500

1.0625

1.0750

1.0875

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Table 8-46. DCDCx Voltage Settings (RANGE[1:0] = 10b)

SEL(DCDCx)[5:0]

000000b

000001b

000010b

000011b

000100b

000101b

000110b

000111b

001000b

001001b

001010b

001011b

001100b

001101b

001110b

001111b

010000b

010001b

010010b

010011b

010100b

010101b

010110b

010111b

011000b

011001b

011010b

011011b

011100b

011101b

011110b

011111b

VDCDCx (V)

0.500

0.525

0.550

0.575

0.600

0.625

0.650

0.675

0.700

0.725

0.750

0.775

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

SEL(DCDCx)[5:0]

100000b

100001b

100010b

100011b

100100b

100101b

100110b

100111b

101000b

101001b

101010b

101011b

101100b

101101b

101110b

101111b

110000b

110001b

110010b

110011b

110100b

110101b

110110b

110111b

111000b

111001b

111010b

111011b

111100b

111101b

111110b

111111b

VDCDCx (V)

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.875

1.900

1.925

1.950

1.975

2.000

2.025

2.050

2.075

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Table 8-47. DCDCx Voltage Settings (RANGE[1:0] = 11b)

SEL(DCDCx)[5:0]

000000b

000001b

000010b

000011b

000100b

000101b

000110b

000111b

001000b

001001b

001010b

001011b

001100b

001101b

001110b

001111b

010000b

010001b

010010b

010011b

010100b

010101b

010110b

010111b

011000b

011001b

011010b

011011b

011100b

011101b

011110b

011111b

VDCDCx (V)

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

1.95

2.00

2.05

SEL(DCDCx)[5:0]

100000b

100001b

100010b

100011b

100100b

100101b

100110b

100111b

101000b

101001b

101010b

101011b

101100b

101101b

101110b

101111b

110000b

110001b

110010b

110011b

110100b

110101b

110110b

110111b

111000b

111001b

111010b

111011b

111100b

111101b

111110b

111111b

VDCDCx (V)

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

2.75

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

3.25

3.30

3.35

3.40

3.45

3.50

3.55

3.60

3.80

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8.5.1.2 LDO Registers (10h to 21h)

Table 8-48 lists the memory-mapped registers for the LDO registers. All register offset addresses not listed in

Table 8-48 should be considered as reserved locations and the register contents should not be modified.

Table 8-48. LDO Register Memory Map

Offset

10h

11h

Acronym

LDO1_OP

LDO1_AVS

LDO1_LIMIT

LDO2_OP

LDO2_AVS

LDO2_LIMIT

LDO3_OP

LDO3_AVS

LDO3_LIMIT

LDO4_OP

LDO4_AVS

LDO4_LIMIT

LDO5

Register Name

Section

LDO1 OP Register

LDO1 AVS Register

LDO1 Limit Register

LDO2 OP Register

LDO2 AVS Register

LDO2 Limit Register

LDO3 OP Register

LDO3 AVS Register

LDO3 Limit Register

LDO4 OP Register

LDO4 AVS Register

LDO4 Limit Register

LDO5 Register

Section 8.5.1.2.1

Section 8.5.1.2.2

Section 8.5.1.2.3

Section 8.5.1.2.4

Section 8.5.1.2.5

Section 8.5.1.2.6

Section 8.5.1.2.7

Section 8.5.1.2.8

Section 8.5.1.2.9

Section 8.5.1.2.10

Section 8.5.1.2.11

Section 8.5.1.2.12

Section 8.5.1.2.13

Section 8.5.1.2.14

Section 8.5.1.2.15

Section 8.5.1.2.16

Section 8.5.1.2.17

Section 8.5.1.2.18

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

LDO6

LDO6 Register

LDO7

LDO7 Register

LDO8

LDO8 Register

LDO9

LDO9 Register

LDO10

LDO10 Register

Complex bit access types are encoded to fit into small table cells. Table 8-49 shows the codes that are used for

access types in this section.

Table 8-49. LDO Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

-OTP

-X

Bit reset value is defined in the

OTP memory

Bit determined by external

connection

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8.5.1.2.1 LDO1_OP Register (Offset = 10h) [reset = OTP]

LDO1_OP is shown in Table 8-50 and described in Table 8-51.

Return to Summary Table.

Register is reset on a POR event.

Table 8-50. LDO1_OP Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SELREG

R/W-0b

SEL[5:0]

R/W-OTP

Table 8-51. LDO1_OP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit, should be written to 0b

6

SELREG

SEL[5:0]

R/W

0b

See Table 8-6

5-0

OTP

Table 8-85 shows the supply-voltage settings.

8.5.1.2.2 LDO1_AVS Register (Offset = 11h) [reset = OTP]

LDO1_AVS is shown in Table 8-52 and described in Table 8-53.

Return to Summary Table.

Register is reset on a POR event.

Table 8-52. LDO1_AVS Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-53. LDO1_AVS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO1 disabled

1b = LDO1 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-85 shows the supply-voltage setting.

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8.5.1.2.3 LDO1_LIMIT Register (Offset = 12h) [reset = OTP]

LDO1_LIMIT is shown in Figure 8-25 and described in Table 8-54.

Return to Summary Table.

Register is reset on a POR event.

Figure 8-25. LDO1_LIMIT Register

7

6

5

4

3

2

1

0

RSVD

R-00b

MAX_SEL[5:0]

R/W-OTP

Table 8-54. LDO1_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-0

RSVD

R

00b

Unused bit, should be written to 0b

MAX_SEL[5:0]

R/W

OTP

This bit defines the maximum value the output voltage in the

LDO1_AVS or LDO1_OP register can be programmed to; values

exceeding MAX_SEL will be replaced by the value defined in

MAX_SEL.

If the MAX_SEL bit is set by I²C or default OTP setting to any value

other than 0x3F or 0x00, the RANGE bits and the MAX_SEL bits are

locked until OTP is reloaded.

8.5.1.2.4 LDO2_OP Register (Offset = 13h) [reset = OTP]

LDO2_OP is shown in Table 8-55 and described in Table 8-56.

Return to Summary Table.

Register is reset on a POR event.

Table 8-55. LDO2_OP Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SELREG

R/W-0b

SEL[5:0]

R/W-OTP

Table 8-56. LDO2_OP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit, should be written to 0b

6

SELREG

SEL[5:0]

R/W

0b

See Table 8-6

5-0

OTP

Table 8-85 shows the supply-voltage setting.

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8.5.1.2.5 LDO2_AVS Register (Offset = 14h) [reset = OTP]

LDO2_AVS is shown in Table 8-57 and described in Table 8-58.

Return to Summary Table.

Register is reset on a POR event.

Table 8-57. LDO2_AVS Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-58. LDO2_AVS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO2 disabled

1b = LDO2 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-85 shows the supply-voltage setting.

8.5.1.2.6 LDO2_LIMIT Register (Offset = 15h) [reset = OTP]

LDO2_LIMIT is shown in Table 8-59 and described in Table 8-60.

Return to Summary Table.

Register is reset on a POR event.

Table 8-59. LDO2_LIMIT Register

7

6

5

4

3

2

1

0

RSVD

R-00b

MAX_SEL[5:0]

R/W-OTP

Table 8-60. LDO2_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-0

RSVD

R

00b

Unused bit, should be written to 0b

MAX_SEL[5:0]

R/W

OTP

This bit defines the maximum value the output voltage in the

LDO2_AVS or LDO2_OP register can be programmed to; values

exceeding MAX_SEL will be replaced by the value defined in

MAX_SEL.

If the MAX_SEL bit is set by I²C or default OTP setting to any value

other than 0x3F or 0x00, the RANGE bits and the MAX_SEL bits are

locked until OTP is reloaded.

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8.5.1.2.7 LDO3_OP Register (Offset = 16h) [reset = OTP]

LDO3_OP is shown in Table 8-61 and described in Table 8-62.

Return to Summary Table.

Register is reset on a POR event.

Table 8-61. LDO3_OP Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SELREG

R/W-0b

SEL[5:0]

R/W-OTP

Table 8-62. LDO3_OP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit, should be written to 0b

6

SELREG

SEL[5:0]

R/W

0b

See Table 8-6

5-0

OTP

Table 8-85 shows the supply-voltage setting.

8.5.1.2.8 LDO3_AVS Register (Offset = 17h) [reset = OTP]

LDO3_AVS is shown in Table 8-63 and described in Table 8-64.

Return to Summary Table.

Register is reset on a POR event.

Table 8-63. LDO3_AVS Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-64. LDO3_AVS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO3 disabled

1b = LDO3 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-85 shows the supply-voltage setting.

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8.5.1.2.9 LDO3_LIMIT Register (Offset = 18h) [reset = OTP]

LDO3_LIMIT is shown in Table 8-65 and described in Table 8-66.

Return to Summary Table.

Register is reset on a POR event.

Table 8-65. LDO3_LIMIT Register

7

6

5

4

3

2

1

0

RSVD

R-00b

MAX_SEL[5:0]

R/W-OTP

Table 8-66. LDO3_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-0

RSVD

R

00b

Unused bit, should be written to 0b

MAX_SEL[5:0]

R/W

OTP

This bit defines the maximum value the output voltage in the

LDO3_AVS or LDO3_OP register can be programmed to; values

exceeding MAX_SEL will be replaced by the value defined in

MAX_SEL.

If the MAX_SEL bit is set by I²C or default OTP setting to any value

other than 0x3F or 0x00, the RANGE bits and the MAX_SEL bits are

locked until OTP is reloaded.

8.5.1.2.10 LDO4_OP Register (Offset = 19h) [reset = OTP]

LDO4_OP is shown in Table 8-67 and described in Table 8-68.

Return to Summary Table.

Register is reset on a POR event.

Table 8-67. LDO4_OP Register

7

6

5

4

3

2

1

0

RSVD

R-0b

SELREG

R/W-0b

SEL[5:0]

R/W-OTP

Table 8-68. LDO4_OP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit, should be written to 0b

6

SELREG

SEL[5:0]

R/W

0b

See Table 8-6

5-0

OTP

Table 8-86 shows the supply-voltage setting. The SEL[5] bit is

internally set to 1b on LDO4 to reflect the programmable output

voltage range from 1.6 V to 3.3 V.

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8.5.1.2.11 LDO4_AVS Register (Offset = 1Ah) [reset = OTP]

LDO4_AVS is shown in Table 8-69 and described in Table 8-70.

Return to Summary Table.

Register is reset on a POR event.

Table 8-69. LDO4_AVS Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-70. LDO4_AVS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO4 disabled

1b = LDO4 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-86 shows the supply-voltage setting. The SEL[5] bit is

internally set to 1b on LDO4 to reflect the programmable output

voltage range from 1.6 V to 3.3 V.

8.5.1.2.12 LDO4_LIMIT Register (Offset = 1Bh) [reset = OTP]

LDO4_LIMIT is shown in Table 8-71 and described in Table 8-72.

Return to Summary Table.

Register is reset on a POR event.

Table 8-71. LDO4_LIMIT Register

7

6

5

4

3

2

1

0

RSVD

R-00b

MAX_SEL[5:0]

R/W-OTP

Table 8-72. LDO4_LIMIT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5-0

RSVD

R

00b

Unused bit, should be written to 0b

MAX_SEL[5:0]

R/W

OTP

This bit defines the maximum value the output voltage in the

LDO4_AVS or LDO4_OP register can be programmed to; values

exceeding MAX_SEL will be replaced by the value defined in

MAX_SEL.

If the MAX_SEL bit is set by I²C or default OTP setting to any value

other than 0x3F or 0x00, the RANGE bits and the MAX_SEL bits are

locked until OTP is reloaded.

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8.5.1.2.13 LDO5 Register (Offset = 1Ch) [reset = OTP]

LDO5 is shown in Table 8-73 and described in Table 8-74.

Return to Summary Table.

Register is reset on a POR event.

Table 8-73. LDO5 Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-74. LDO5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO5 disabled

1b = LDO5 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-86 shows the supply-voltage setting. The SEL[5] bit is

internally set to 1b on LDO5 to reflect the programmable output

voltage range from 1.6 V to 3.3 V.

8.5.1.2.14 LDO6 Register (Offset = 1Dh) [reset = OTP]

LDO6 is shown in Table 8-75 and described in Table 8-76.

Return to Summary Table.

Register is reset on a POR event.

Table 8-75. LDO6 Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-OTP

R/W-0b

Table 8-76. LDO6 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO6 disabled

1b = LDO6 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-85 shows the supply-voltage setting.

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8.5.1.2.15 LDO7 Register (Offset = 1Eh) [reset = OTP]

LDO7 is shown in Table 8-77 and described in Table 8-78.

Return to Summary Table.

Register is reset on a POR event.

Table 8-77. LDO7 Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-78. LDO7 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO7 disabled

1b = LDO7 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-85 shows the supply-voltage setting.

8.5.1.2.16 LDO8 Register (Offset = 1Fh) [reset = OTP]

LDO8 is shown in Table 8-79 and described in Table 8-80.

Return to Summary Table.

Register is reset on a POR event.

Table 8-79. LDO8 Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-OTP

R/W-0b

Table 8-80. LDO8 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO8 disabled

1b = LDO8 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-85 shows the supply-voltage setting.

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8.5.1.2.17 LDO9 Register (Offset = 20h) [reset = OTP]

LDO9 is shown in Table 8-81 and described in Table 8-82.

Return to Summary Table.

Register is reset on a POR event.

Table 8-81. LDO9 Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-0b

R/W-OTP

Table 8-82. LDO9 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO9 disabled

1b = LDO9 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-85 shows the supply-voltage setting.

8.5.1.2.18 LDO10 Register (Offset = 21h) [reset = OTP]

LDO10 is shown in Table 8-83 and described in Table 8-84.

Return to Summary Table.

Register is reset on a POR event.

Table 8-83. LDO10 Register

7

6

5

4

3

2

1

0

ENABLE

R/W-OTP

ECO

SEL[5:0]

R/W-OTP

R/W-0b

Table 8-84. LDO10 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ENABLE

R/W

OTP

0b = LDO10 disabled

1b = LDO10 enabled unless it is being disabled by SET_OFF mode

6

ECO

R/W

0b

See Section 8.3.1.1

5-0

SEL[5:0]

OTP

Table 8-85 shows the supply-voltage setting.

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8.5.1.2.19 LDO Voltage Settings

Table 8-85. LDO Voltage Settings; Except LDO4 and LDO5

SEL[5:0]

000000b

000001b

000010b

000011b

000100b

000101b

000110b

000111b

001000b

001001b

001010b

001011b

001100b

001101b

001110b

001111b

010000b

010001b

010010b

010011b

010100b

010101b

010110b

010111b

011000b

011001b

011010b

011011b

011100b

011101b

011110b

011111b

LDOx Output (V)

0.800

0.825

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1.100

1.125

1.150

1.175

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

SEL[5:0]

100000b

100001b

100010b

100011b

100100b

100101b

100110b

100111b

101000b

101001b

101010b

101011b

101100b

101101b

101110b

101111b

110000b

110001b

110010b

110011b

110100b

110101b

110110b

110111b

111000b

111001b

111010b

111011b

111100b

111101b

111110b

111111b

LDOx Output (V)

1.600

1.650

1.700

1.750

1.800

1.850

1.900

1.950

2.000

2.050

2.100

2.150

2.200

2.250

2.300

2.350

2.400

2.450

2.500

2.550

2.600

2.650

2.700

2.750

2.800

2.850

2.900

2.950

3.000

3.100

3.200

3.300

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Table 8-86. LDO Voltage Settings for LDO4 and

LDO5

SEL[5:0]

100000b

100001b

100010b

100011b

100100b

100101b

100110b

100111b

101000b

101001b

101010b

101011b

101100b

101101b

101110b

101111b

110000b

110001b

110010b

110011b

110100b

110101b

110110b

110111b

111000b

111001b

111010b

111011b

111100b

111101b

111110b

111111b

LDOx Output (V)

1.600

1.650

1.700

1.750

1.800

1.850

1.900

1.950

2.000

2.050

2.100

2.150

2.200

2.250

2.300

2.350

2.400

2.450

2.500

2.550

2.600

2.650

2.700

2.750

2.800

2.850

2.900

2.950

3.000

3.100

3.200

3.300

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8.5.1.3 DEVCTRL Registers (22h to 64h)

Table 8-87 lists the memory-mapped registers for the DEVCTRL registers. All register offset addresses not listed

in Table 8-87 should be considered as reserved locations and the register contents should not be modified.

Table 8-87. DEVCTRL Register Memory Map

Offset

22h

23h

24h

25h

26h

27h

28h

29h

2Ah

(2Bh)

2Ch

2Dh

2Eh

2Fh

30h

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

3Dh

3Eh

3Fh

40h

41h

42h

43h

44h

45h

46h

47h

48h

49h

4Ah

4Bh

Acronym

Register Name

Section

THRM_REG

CLK32KOUT

DEVCTRL

DEVCTRL2

I2C_SPI_CFG

KEEP_ON1

KEEP_ON2

SET_OFF1

SET_OFF2

DEF_VOLT

DEF_VOLT_MAPPING

DISCHARGE1

DISCHARGE2

EN1_SET1

EN1_SET2

EN2_SET1

EN2_SET2

EN3_SET1

EN3_SET2

EN4_SET1

EN4_SET2

PGOOD

Thermal Register

Section 8.5.1.3.1

Section 8.5.1.3.2

Section 8.5.1.3.3

Section 8.5.1.3.4

Section 8.5.1.3.5

Section 8.5.1.3.6

Section 8.5.1.3.7

Section 8.5.1.3.8

Section 8.5.1.3.9

Section 8.5.1.3.10

Section 8.5.1.3.12

Section 8.5.1.3.13

Section 8.5.1.3.14

Section 8.5.1.3.15

Section 8.5.1.3.16

Section 8.5.1.3.17

Section 8.5.1.3.18

Section 8.5.1.3.19

Section 8.5.1.3.20

Section 8.5.1.3.21

Section 8.5.1.3.22

Section 8.5.1.3.23

Section 8.5.1.3.24

Section 8.5.1.3.25

Section 8.5.1.3.26

Section 8.5.1.3.27

Section 8.5.1.3.28

Section 8.5.1.3.29

Section 8.5.1.3.30

Section 8.5.1.3.31

Section 8.5.1.3.32

Section 8.5.1.3.33

Section 8.5.1.3.34

Section 8.5.1.3.35

Section 8.5.1.3.36

Section 8.5.1.3.37

Section 8.5.1.3.38

Section 8.5.1.3.39

Section 8.5.1.3.40

Section 8.5.1.3.41

Section 8.5.1.3.42

Section 8.5.1.3.43

32-kHz Clock Output Register

Device Control Register

Device Control 2 Register

I²C-SPI Configuration Register

LDO Keep-On Register

DCDC Keep-On Register

LDO Set Off Register

DCDC Set Off Register

Default Voltage Register

Default Voltage Mapping Register

LDO Discharge Register

DCDC Discharge Register

LDO EN1 Pin Setting Register

DCDC EN1 Pin Setting Register

LDO EN2 Pin Setting Register

DCDC EN2 Pin Setting Register

LDO EN3 Pin Setting Register

DCDC EN3 Pin Setting Register

LDO EN4 Pin Setting Register

DCDC EN4 Pin Setting Register

Power Good Register

PGOOD2

Power Good 2 Register

Interrupt Mask Register

Interrupt Status Register

Interrupt Status 2 Register

Interrupt Mask 2 Register

Interrupt Status 3 Register

Interrupt Mask 3 Register

Interrupt Status 4 Register

Interrupt Mask 4 Register

GPIO1 Register

INT_STS

INT_MSK

INT_STS2

INT_MSK2

INT_STS3

INT_MSK3

INT_STS4

INT_MSK4

GPIO1

GPIO2

GPIO2 Register

GPIO3

GPIO3 Register

GPIO4

GPIO4 Register

GPIO5

GPIO5 Register

VMON

Voltage Monitor Register

LEDA Control 1 Register

LEDA Control 2 Register

LEDA Control 3 Register

LEDA Control 4 Register

LEDA Control 5 Register

LEDA_CTRL1

LEDA_CTRL2

LEDA_CTRL3

LEDA_CTRL4

LEDA_CTRL5

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Table 8-87. DEVCTRL Register Memory Map (continued)

Offset

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

54h

55h

56h

57h

58h

59h

5Ah

5Bh

5Ch

5Dh

5Eh

5Fh

60h

61h

62h

63h

64h

Acronym

Register Name

Section

LEDA_CTRL6

LEDA_CTRL7

LEDA_CTRL8

LEDB_CTRL1

LEDB_CTRL2

LEDB_CTRL3

LEDB_CTRL4

LEDB_CTRL5

LEDB_CTRL6

LEDB_CTRL7

LEDB_CTRL8

LEDC_CTRL1

LEDC_CTRL2

LEDC_CTRL3

LEDC_CTRL4

LEDC_CTRL5

LEDC_CTRL6

LEDC_CTRL7

LEDC_CTRL8

LED_RAMP_UP_TIME

LED_RAMP_DOWN_TIME

LED_SEQ_EN

LOADSWITCH

SPARE

LEDA Control 6 Register

LEDA Control 7 Register

LEDA Control 8 Register

LEDB Control 1 Register

LEDB Control 2 Register

LEDB Control 3 Register

LEDB Control 4 Register

LEDB Control 5 Register

LEDB Control 6 Register

LEDB Control 7 Register

LEDB Control 8 Register

LEDC Control 1 Register

LEDC Control 2 Register

LEDC Control 3 Register

LEDC Control 4 Register

LEDC Control 5 Register

LEDC Control 6 Register

LEDC Control 7 Register

LEDC Control 8 Register

LED Ramp-Up Time Register

LED Ramp-Down Time Register

LED Sequence Enable Register

Load Switch Register

Section 8.5.1.3.44

Section 8.5.1.3.45

Section 8.5.1.3.46

Section 8.5.1.3.47

Section 8.5.1.3.48

Section 8.5.1.3.49

Section 8.5.1.3.50

Section 8.5.1.3.51

Section 8.5.1.3.52

Section 8.5.1.3.53

Section 8.5.1.3.54

Section 8.5.1.3.55

Section 8.5.1.3.56

Section 8.5.1.3.57

Section 8.5.1.3.58

Section 8.5.1.3.59

Section 8.5.1.3.60

Section 8.5.1.3.61

Section 8.5.1.3.62

Section 8.5.1.3.63

Section 8.5.1.3.64

Section 8.5.1.3.65

Section 8.5.1.3.67

Section 8.5.1.3.68

Section 8.5.1.3.69

Spare Register

VERNUM

Version Number Register

Complex bit access types are encoded to fit into small table cells. Table 8-88 shows the codes that are used for

access types in this section.

Table 8-88. DEVCTRL Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

Reset or Default Value

-n

Value after reset or the default

value

-OTP

-X

Bit reset value is defined in the

OTP memory

Bit determined by external

connection

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8.5.1.3.1 THRM_REG Register (Offset = 22h) [reset = 0Dh]

THRM_REG is shown in Table 8-89 and described in Table 8-90.

Return to Summary Table.

Register is reset on a POR event.

Table 8-89. THRM_REG Register

7

6

5

4

3

2

1

0

RSVD

R-00b

THERM_HD

R-0b

THERM_TS

R-0b

THERM_HDSEL[1:0]

R/W-11b

RSVD

R-0b

THERM_EN

R/W-1b

Table 8-90. THRM_REG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

THERM_HD

R

0b

0b = Hot die threshold is not reached

1b = Hot die threshold is reached

4

THERM_TS

R

0b

Thermal shutdown detector output

0b = Indicates thermal shutdown not reached (typically 150°C)

1b = Indicates thermal shutdown reached

3-2

THERM_HDSEL

R/W

11b

Temperature selection for hot die detector

00b = T = 117°C

01b = T = 121°C

10b = T = 125°C

11b = T = 130°C

1

0

RSVD

R

0b

1b

Unused bit

THERM_EN

R/W

Thermal shutdown module

0b = Disabled

1b = Enabled

8.5.1.3.2 CLK32KOUT Register (Offset = 23h) [reset = OTP]

CLK32KOUT is shown in Table 8-91 and described in Table 8-92.

Return to Summary Table.

Register is reset on a POR event.

Table 8-91. CLK32KOUT Register

7

6

5

4

3

2

1

0

CLK32KOUT_E

N

RSVD

R-0000000b

R/W-OTP

Table 8-92. CLK32KOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7-1

0

RSVD

R

0000000b

Unused bit read returns 0b.

CLK32KOUT_EN

R/W

OTP

0b = 32KCLKOUT disabled

1b = 32KCLKOUT enabled

90

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8.5.1.3.3 DEVCTRL Register (Offset = 24h) [reset = OTP]

DEVCTRL is shown in Table 8-93 and described in Table 8-94.

Return to Summary Table.

Register is reset on a POR event.

Table 8-93. DEVCTRL Register

7

6

5

4

3

2

1

0

PWR_OFF_SE

Q

nRESPWRON_

OUTPUT

LOAD-OTP

R/W-OTP

LOCK_LDO9

R-OTP

RSVD

R-0b

PWRHLD

R/W-OTP

DEV_SLP

R/W-0b

DEV_OFF

R/W-0b

R/W-OTP

Table 8-94. DEVCTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PWR_OFF_SEQ

LOAD-OTP

LOCK_LDO9

RSVD

R/W

OTP

0b = All resources disabled at the same time

1b = Power-off will be sequential, reverse of power-on sequence

(first resource to power on will be the last to power off)

6

5

R/W

R

OTP

0b = Register contents are kept in the OFF state

1b = Register default values are reloaded from OTP when in the OFF

state

0b = LDO9 bits are allowed to be changed

1b = LDO9 bits are locked; LDO9 is enabled in the startup sequence

and disabled in the OFF state; no further control allowed

4

3

R

0b

Unused bit read returns 0b.

nRESPWRON_OUTPUT R/W

OTP

0b = NRESPWRON output is open drain

1b = NRESPWRON output is push-pull to VDDIO

2

PWRHLD

DEV_SLP

R/W

OTP

0b

0b = Cleared in the OFF state.

1b = Writing 1b will maintain the device on (ACTIVE or SLEEP

device state) unless one of the power off events occur (DEV_OFF,

long key press if not masked, or thermal shutdown).

1

0b = This bit is cleared in the OFF state.

1b = Writing 1b will starts an ACTIVE-to-SLEEP transition as long

as no unmasked interrupts are pending. If set to 1b, the device

will require an unmasked interrupt to occur to perform SLEEP-to-

ACTIVE transition or will need to transition to OFF to clear this bit.

0

DEV_OFF

R/W

0b

0b = This bit is cleared in the OFF state.

1b = Writing 1b will start an ACTIVE-to-OFF or SLEEP-to-OFF

device state transition (switch-off event). This event has priority over

PWRHLD bit and PWRHOLD pin. Device will restart if either is high

once transition to OFF state is complete.

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8.5.1.3.4 DEVCTRL2 Register (Offset = 25h) [reset = OTP]

DEVCTRL2 is shown in Table 8-95 and described in Table 8-96.

Return to Summary Table.

Register is reset on a POR event.

Table 8-95. DEVCTRL2 Register

7

6

5

4

3

2

1

0

SLEEP_ENABL

E

PWRON_LP_O PWRON_LP_

INT_OUTPUT

R/W-OTP

TSLOT_LENGTH[1:0]

R/W-OTP

SLEEP_POL

R/W-0b

INT_POL

R/W-OTP

FF

OFF_RST

R/W-0b

R/W-OTP

Table 8-96. DEVCTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

SLEEP_ENABLE

R/W

0b

0b = SLEEP signal is ignored; default for power-up and should

remain this way for CONFIG2 shorted to GND.

1b = SLEEP signal is unmasked and the device can enter SLEEP

state if there are no pending interrupts and the SLEEP pin

(CONFIG2 tied to LDOAO) is active as defined by the SLEEP_POL

bit

6

INT_OUTPUT

R/W

OTP

0b = Interrupt output is open drain

1b = Interrupt output is push-pull to VDDIO

5-4

TSLOT_LENGTH[1:0]

Time slot duration programming; selects length of the timeslots for

startup or shutdown timing

00b = 30 µs

01b = 200 µs

10b = 500 µs

11b = 2 ms

3

2

SLEEP_POL

R/W

0b

0b = SLEEP signal active high

1b = SLEEP signal active low

PWRON_LP_OFF

OTP

0b = No effect

1b = Allows device turnoff after an nPWRON long press (signal low).

After the nPWRON pin is low for 4 s, an interrupt is generated. After

1 additional second, the device performs the power-off sequence.

1

PWRON_LP_OFF_RST

R/W

OTP

0b = No effect

1b = Allows device turnoff after an nPWRON long press (signal low).

After the nPWRON pin is low for 4 s, an interrupt is generated. After

1 additional second, the device performs the power-off sequence and

registers are loaded with their default values, regardless of LOAD-

OTP bit value. This bit has priority over the PWRON_LP_OFF bit and

the LOAD-OTP bit.

0

INT_POL

R/W

OTP

0b = INT1 interrupt pad-polarity control signal is active low

1b = INT1 interrupt pad-polarity control signal is active high

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8.5.1.3.5 I2C_SPI_CFG Register (Offset = 26h) [reset = OTP]

I2C_SPI_CFG is shown in Table 8-97 and described in Table 8-98.

Return to Summary Table.

Register is reset on a POR event.

Table 8-97. I2C_SPI_CFG Register

7

6

5

4

3

2

1

0

I2CAVS_ID_SEL[1:0]

R-OTP

I2CGP_ID_SEL[1:0]

R-OTP

DCDC4_AVS

R/W-OTP

DCDC3_AVS

R/W-OTP

DCDC2_AVS

R/W-OTP

DCDC1_AVS

R/W-OTP

Table 8-98. I2C_SPI_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

I2CAVS_ID_SEL[1:0]

R

OTP

Device address for the AVS-I2C interface

00b = 12h

01b = 13h

10b = 14h

11b = 15h

5-4

I2CGP_ID_SEL1[1:0]

R

OTP

Device address for the standard-I2C interface

00b = 2Dh

01b = 2Eh

10b = 2Fh

11b = 30h

3

2

1

0

DCDC4_AVS

DCDC3_AVS

DCDC2_AVS

DCDC1_AVS

R/W

OTP

Interface assignment for the DCDC4_OP and DCDC4_AVS registers

0b = Standard interface

1b = AVS- interface

Interface assignment for the DCDC3_OP and DCDC3_AVS registers

0b = Standard interface

1b = AVS- interface

Interface assignment for the DCDC2_OP and DCDC2_AVS registers

0b = Standard interface

1b = AVS- interface

Interface assignment for the DCDC1_OP and DCDC1_AVS registers

0b = Standard interface

1b = AVS- interface

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8.5.1.3.6 KEEP_ON1 Register (Offset = 27h) [reset = OTP]

KEEP_ON1 is shown in Table 8-99 and described in Table 8-100.

Return to Summary Table.

Register is reset on a POR event.

Settings shown in Table 8-109

Table 8-99. KEEP_ON1 Register

7

6

5

4

3

2

1

0

LDO8_KEEPO LDO7_KEEPO LDO6_KEEPO LDO5_KEEPO LDO4_KEEPO LDO3_KEEPO LDO2_KEEPO LDO1_KEEPO

N

R/W-OTP

Table 8-100. KEEP_ON1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO8_KEEPON

LDO7_KEEPON

LDO6_KEEPON

LDO5_KEEPON

LDO4_KEEPON

LDO3_KEEPON

LDO2_KEEPON

LDO1_KEEPON

R/W

OTP

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

6

5

4

3

2

1

0

R/W

OTP

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

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8.5.1.3.7 KEEP_ON2 Register (Offset = 28h) [reset = OTP]

KEEP_ON2 is shown in Table 8-101 and described in Table 8-102.

Return to Summary Table.

Register is reset on a POR event.

Settings shown in Table 8-109

Table 8-101. KEEP_ON2 Register

7

6

5

4

3

2

1

0

DCDC4_

KEEPON

DCDC3_

KEEPON

DCDC2_

KEEPON

DCDC1_

KEEPON

LDO10_

KEEPON

LDO9_

KEEPON

RSVD

R-00b

R/W-OTP

Table 8-102. KEEP_ON2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bits

DCDC4_KEEPON

DCDC3_KEEPON

DCDC2_KEEPON

DCDC1_KEEPON

R/W

OTP

0b = Set in Eco-mode in the SLEEP state, unless DCDC4_MODE =

1b

1b = Keep active in the SLEEP state

4

3

2

R/W

OTP

0b = Set in Eco-mode in the SLEEP state, unless DCDC3_MODE =

1b

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state, unless DCDC2_MODE =

1b

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state, unless DCDC1_MODE =

1b

1b = Keep active in the SLEEP state

1

0

LDO10_KEEPON

LDO9_KEEPON

R/W

OTP

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

0b = Set in Eco-mode in the SLEEP state

1b = Keep active in the SLEEP state

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8.5.1.3.8 SET_OFF1 Register (Offset = 29h) [reset = OTP]

SET_OFF1 is shown in Table 8-103 and described in Table 8-104.

Return to Summary Table.

Register is reset on a POR event.

Settings shown in Table 8-109

Table 8-103. SET_OFF1 Register

7

6

5

4

3

2

1

0

LDO8_SET_OF LDO7_SET_OF LDO6_SET_OF LDO5_SET_OF LDO4_SET_OF LDO3_SET_OF LDO2_SET_OF LDO1_SET_OF

F

R/W-OTP

Table 8-104. SET_OFF1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO8_SET_OFF

LDO7_SET_OFF

LDO6_SET_OFF

LDO5_SET_OFF

LDO4_SET_OFF

LDO3_SET_OFF

LDO2_SET_OFF

LDO1_SET_OFF

R/W

OTP

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

6

5

4

3

2

1

0

R/W

OTP

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

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8.5.1.3.9 SET_OFF2 Register (Offset = 2Ah) [reset = OTP]

SET_OFF2 is shown in Table 8-105 and described in Table 8-106.

Return to Summary Table.

Register is reset on a POR event.

Settings shown in Section 8.5.1.3.11.

Table 8-105. SET_OFF2 Register

7

6

5

4

3

2

1

0

THERM_

KEEP_ON

CLK32KOUT_

KEEPON

DCDC4_

SET_OFF

DCDC3_

SET_OFF

DCDC2_

SET_OFF

DCDC1_

SET_OFF

LDO10_

SET_OFF

LDO9_

SET_OFF

R/W-OTP

Table 8-106. SET_OFF2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

THERM_KEEP_ON

CLK32KOUT_KEEPON

DCDC4_SET_OFF

DCDC3_SET_OFF

DCDC2_SET_OFF

DCDC1_SET_OFF

LDO10_SET_OFF

LDO9_SET_OFF

R/W

OTP

0b = Enabled in the SLEEP state

1b = Set off in the SLEEP state

6

5

4

3

2

1

0

R/W

OTP

0b = Enabled in the SLEEP state

1b = Set off in the SLEEP state

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

0b = Defined by the KEEP_ON register

1b = Set off in the SLEEP state if the KEEP_ON bit set to 0b

8.5.1.3.10 DEF_VOLT Register (Offset = 2Bh) [reset = OTP]

DEF_VOLT is shown in Table 8-107 and described in Table 8-108.

Return to Summary Table.

Register is reset on a POR event.

Settings shown in Table 8-109

Table 8-107. DEF_VOLT Register

7

6

5

4

3

2

1

0

LDO4_DEF_VO LDO3_DEF_VO LDO2_DEF_VO LDO1_DEF_VO DCDC4_DEF_V DCDC3_DEF_V DCDC2_DEF_V DCDC1_DEF_V

LT

OLT

R/W-OTP

Table 8-108. DEF_VOLT Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

OTP

Description

LDO4_DEF_VOLT

LDO3_DEF_VOLT

LDO2_DEF_VOLT

LDO1_DEF_VOLT

DCDC4_DEF_VOLT

DCDC3_DEF_VOLT

See Table 8-6

6

5

4

3

2

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Table 8-108. DEF_VOLT Register Field Descriptions (continued)

Bit

1

Field

Type

R/W

Reset

Description

See Table 8-6

DCDC2_DEF_VOLT

DCDC1_DEF_VOLT

OTP

0

OTP

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8.5.1.3.11 LDO Sleep Mode Behavior

Table 8-109. LDO SLEEP MODE BEHAVIOR

CONFIG BITS

LDO IS SET TO Eco-mode

LDO STAYS ACTIVE

LDO IS SET TO OFF

0b = Voltage defined by the _OP 0b = Voltage defined by the _OP

0b = Voltage defined by the _OP register

1b = Voltage defined by the _AVS register

register

DEF_VOLT

1b = Voltage defined by the _AVS 1b = Voltage defined by the _AVS

register

0b

KEEP ON

SET OFF

0b

1b

x

1b

8.5.1.3.12 DEF_VOLT_MAPPING Register (Offset = 2Ch) [reset = OTP]

DEF_VOLT_MAPPING is shown in Table 8-110 and described in Table 8-111.

Return to Summary Table.

Register is reset on a POR event.

Table 8-110. DEF_VOLT_MAPPING Register

7

6

5

4

3

2

1

0

LDO4_VOLT_MAPPING[1:0]

R/W-OTP

LDO3_VOLT_MAPPING[1:0]

R/W-OTP

LDO2_VOLT_MAPPING[1:0]

R/W-OTP

LDO1_VOLT_MAPPING[1:0]

R/W-OTP

Table 8-111. DEF_VOLT_MAPPING Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

LDO4_VOLT_MAPPING[1 R/W

:0]

OTP

Maps a DCDCx_SEL pin to the voltage scaling function to select

either LDO4_OP or LDO4_AVS as the register defining the output

voltage for LDO4 for when CONFIG2 is tied to GND.

DEF_VOLT bit set and cleared by the status of the:

00b = DCDC1_SEL pin

01b = DCDC2_SEL pin

10b = DCDC3_SEL pin

11b = DCDC4_SEL pin

5-4

LDO3_VOLT_MAPPING[1 R/W

:0]

OTP

Maps a DCDCx_SEL pin to the voltage scaling function to select

either LDO3_OP or LDO3_AVS as the register defining the output

voltage for LDO3.

DEF_VOLT bit set and cleared by the status of the:

00b = DCDC1_SEL pin

01b = DCDC2_SEL pin

10b = DCDC3_SEL pin

11b = DCDC4_SEL pin

3-2

LDO2_VOLT_MAPPING[1 R/W

:0]

OTP

Maps a DCDCx_SEL pin to the voltage scaling function to select

either LDO2_OP or LDO2_AVS as the register defining the output

voltage for LDO2.

DEF_VOLT bit set and cleared by the status of the:

00b = DCDC1_SEL pin

01b = DCDC2_SEL pin

10b = DCDC3_SEL pin

11b = DCDC4_SEL pin

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Table 8-111. DEF_VOLT_MAPPING Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1-0

LDO1_VOLT_MAPPING[1 R/W

:0]

OTP

Maps a DCDCx_SEL pin to the voltage scaling function to select

either LDO1_OP or LDO1_AVS as the register defining the output

voltage for LDO1.

DEF_VOLT bit set and cleared by the status of the:

00b = DCDC1_SEL pin

01b = DCDC2_SEL pin

10b = DCDC3_SEL pin

11b = DCDC4_SEL pin

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8.5.1.3.13 DISCHARGE1 Register (Offset = 2Dh) [reset = OTP]

DISCHARGE1 is shown in Table 8-112 and described in Table 8-113.

Return to Summary Table.

Register is reset on a POR event.

Table 8-112. DISCHARGE1 Register

7

6

5

4

3

2

1

0

LDO8_

LDO7_

LDO6_

LDO5_

LDO4_

LDO3_

LDO2_

LDO1_

DISCHARGE

R/W-OTP

Table 8-113. DISCHARGE1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO8_DISCHARGE

LDO7_DISCHARGE

LDO6_DISCHARGE

LDO5_DISCHARGE

LDO4_DISCHARGE

LDO3_DISCHARGE

LDO2_DISCHARGE

LDO1_DISCHARGE

R/W

OTP

0b = LDO8 output is not discharged when disabled

1b = LDO8 output is discharged when disabled

6

5

4

3

2

1

0

R/W

OTP

0b = LDO7 output is not discharged when disabled

1b = LDO7 output is discharged when disabled

0b = LDO6 output is not discharged when disabled

1b = LDO6 output is discharged when disabled

0b = LDO5 output is not discharged when disabled

1b = LDO5 output is discharged when disabled

0b = LDO4 output is not discharged when disabled

1b = LDO4 output is discharged when disabled

0b = LDO3 output is not discharged when disabled

1b = LDO3 output is discharged when disabled

0b = LDO2 output is not discharged when disabled

1b = LDO2 output is discharged when disabled

0b = LDO1 output is not discharged when disabled

1b = LDO1 output is discharged when disabled

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8.5.1.3.14 DISCHARGE2 Register (Offset = 2Eh) [reset = OTP]

DISCHARGE2 is shown in Table 8-114 and described in Table 8-115.

Return to Summary Table.

Register is reset on a POR event.

Table 8-114. DISCHARGE2 Register

7

6

5

4

3

2

1

0

DCDC4_

DISCHARGE

DCDC3_

DISCHARGE

DCDC2_

DISCHARGE

DCDC1_

DISCHARGE

LDO10_

DISCHARGE

LDO9_

DISCHARGE

RSVD

R-00b

R/W-OTP

Table 8-115. DISCHARGE2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

DCDC4_DISCHARGE

DCDC3_DISCHARGE

DCDC2_DISCHARGE

DCDC1_DISCHARGE

LDO10_DISCHARGE

LDO9_DISCHARGE

R/W

OTP

0b = DCDC4 output is not discharged when disabled

1b = DCDC4 output is discharged when disabled

4

3

2

1

0

0b = DCDC3 output is not discharged when disabled

1b = DCDC3 output is discharged when disabled

0b = DCDC2 output is not discharged when disabled

1b = DCDC2 output is discharged when disabled

0b = DCDC1 output is not discharged when disabled

1b = DCDC1 output is discharged when disabled

0b = LDO10 output is not discharged when disabled

1b = LDO10 output is discharged when disabled

0b = LDO9 output is not discharged when disabled

1b = LDO9 output is discharged when disabled

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8.5.1.3.15 EN1_SET1 Register (Offset = 2Fh) [reset = OTP]

EN1_SET1 is shown in Table 8-116 and described in Table 8-117.

Return to Summary Table.

Register is reset on a POR event.

Table 8-116. EN1_SET1 Register

7

6

5

4

3

2

1

0

LDO8_EN1

R/W-OTP

LDO7_EN1

R/W-OTP

LDO6_EN1

R/W-OTP

LDO5_EN1

R/W-OTP

LDO4_EN1

R/W-OTP

LDO3_EN1

R/W-OTP

LDO2_EN1

R/W-OTP

LDO1_EN1

R/W-OTP

Table 8-117. EN1_SET1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO8_EN1

LDO7_EN1

LDO6_EN1

LDO5_EN1

LDO4_EN1

LDO3_EN1

LDO2_EN1

LDO1_EN1

R/W

OTP

0b = EN1 pin has no effect on LDO8 enable

1b = EN1 pin is controlling LDO8

6

5

4

3

2

1

0

R/W

OTP

0b = EN1 pin has no effect on LDO7 enable

1b = EN1 pin is controlling LDO7

0b = EN1 pin has no effect on LDO6 enable

1b = EN1 pin is controlling LDO6

0b = EN1 pin has no effect on LDO5 enable

1b = EN1 pin is controlling LDO5

0b = EN1 pin has no effect on LDO4 enable

1b = EN1 pin is controlling LDO4

0b = EN1 pin has no effect on LDO3 enable

1b = EN1 pin is controlling LDO3

0b = EN1 pin has no effect on LDO2 enable

1b = EN1 pin is controlling LDO2

0b = EN1 pin has no effect on LDO1 enable

1b = EN1 pin is controlling LDO1

8.5.1.3.16 EN1_SET2 Register (Offset = 30h) [reset = OTP]

EN1_SET2 is shown in Table 8-118 and described in Table 8-119.

Return to Summary Table.

Register is reset on a POR event.

Table 8-118. EN1_SET2 Register

7

6

5

4

3

2

1

0

RSVD

R-00b

DCDC4_EN1

R/W-OTP

DCDC3_EN1

R/W-OTP

DCDC2_EN1

R/W-OTP

DCDC1_EN1

R/W-OTP

LDO10_EN1

R/W-OTP

LDO9_EN1

R/W-OTP

Table 8-119. EN1_SET2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

DCDC4_EN1

R/W

OTP

0b = EN1 pin has no effect on DCDC4 enable

1b = EN1 pin is controlling DCDC4

4

DCDC3_EN1

R/W

OTP

0b = EN1 pin has no effect on DCDC3 enable

1b = EN1 pin is controlling DCDC3

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Table 8-119. EN1_SET2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

DCDC2_EN1

R/W

OTP

0b = EN1 pin has no effect on DCDC2 enable

1b = EN1 pin is controlling DCDC2

2

1

0

DCDC1_EN1

LDO10_EN1

LDO9_EN1

R/W

OTP

0b = EN1 pin has no effect on DCDC1 enable

1b = EN1 pin is controlling DCDC1

0b = EN1 pin has no effect on LDO10 enable

1b = EN1 pin is controlling LDO10

0b = EN1 pin has no effect on LDO9 enable

1b = EN1 pin is controlling LDO9

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8.5.1.3.17 EN2_SET1 Register (Offset = 31h) [reset = OTP]

EN2_SET1 is shown in Table 8-120 and described in Table 8-121.

Return to Summary Table.

Register is reset on a POR event.

Table 8-120. EN2_SET1 Register

7

6

5

4

3

2

1

0

LDO8_EN2

R/W-OTP

LDO7_EN2

R/W-OTP

LDO6_EN2

R/W-OTP

LDO5_EN2

R/W-OTP

LDO4_EN2

R/W-OTP

LDO3_EN2

R/W-OTP

LDO2_EN2

R/W-OTP

LDO1_EN2

R/W-OTP

Table 8-121. EN2_SET1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO8_EN2

LDO7_EN2

LDO6_EN2

LDO5_EN2

LDO4_EN2

LDO3_EN2

LDO2_EN2

LDO1_EN2

R/W

OTP

0b = EN2 pin has no effect on LDO8 enable

1b = EN2 pin is controlling LDO8

6

5

4

3

2

1

0

R/W

OTP

0b = EN2 pin has no effect on LDO7 enable

1b = EN2 pin is controlling LDO7

0b = EN2 pin has no effect on LDO6 enable

1b = EN2 pin is controlling LDO6

0b = EN2 pin has no effect on LDO5 enable

1b = EN2 pin is controlling LDO5

0b = EN2 pin has no effect on LDO4 enable

1b = EN2 pin is controlling LDO4

0b = EN2 pin has no effect on LDO3 enable

1b = EN2 pin is controlling LDO3

0b = EN2 pin has no effect on LDO2 enable

1b = EN2 pin is controlling LDO2

0b = EN2 pin has no effect on LDO1 enable

1b = EN2 pin is controlling LDO1

8.5.1.3.18 EN2_SET2 Register (Offset = 32h) [reset = OTP]

EN2_SET2 is shown in Table 8-122 and described in Table 8-123.

Return to Summary Table.

Register is reset on a POR event.

Table 8-122. EN2_SET2 Register

7

6

5

4

3

2

1

0

RSVD

R-00b

DCDC4_EN2

R/W-OTP

DCDC3_EN2

R/W-OTP

DCDC2_EN2

R/W-OTP

DCDC1_EN2

R/W-OTP

LDO10_EN2

R/W-OTP

LDO9_EN2

R/W-OTP

Table 8-123. EN2_SET2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

DCDC4_EN2

R/W

OTP

0b = EN2 pin has no effect on DCDC4 enable

1b = EN2 pin is controlling DCDC4

4

DCDC3_EN2

R/W

OTP

0b = EN2 pin has no effect on DCDC3 enable

1b = EN2 pin is controlling DCDC3

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Table 8-123. EN2_SET2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

DCDC2_EN2

R/W

OTP

0b = EN2 pin has no effect on DCDC2 enable

1b = EN2 pin is controlling DCDC2

2

1

0

DCDC1_EN2

LDO10_EN2

LDO9_EN2

R/W

OTP

0b = EN2 pin has no effect on DCDC1 enable

1b = EN2 pin is controlling DCDC1

0b = EN2 pin has no effect on LDO10 enable

1b = EN2 pin is controlling LDO10

0b = EN2 pin has no effect on LDO9 enable

1b = EN2 pin is controlling LDO9

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8.5.1.3.19 EN3_SET1 Register (Offset = 33h) [reset = OTP]

EN3_SET1 is shown in Table 8-124 and described in Table 8-125.

Return to Summary Table.

Register is reset on a POR event.

Table 8-124. EN3_SET1 Register

7

6

5

4

3

2

1

0

LDO8_EN3

R/W-OTP

LDO7_EN3

R/W-OTP

LDO6_EN3

R/W-OTP

LDO5_EN3

R/W-OTP

LDO4_EN3

R/W-OTP

LDO3_EN3

R/W-OTP

LDO2_EN3

R/W-OTP

LDO1_EN3

R/W-OTP

Table 8-125. EN3_SET1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO8_EN3

LDO7_EN3

LDO6_EN3

LDO5_EN3

LDO4_EN3

LDO3_EN3

LDO2_EN3

LDO1_EN3

R/W

OTP

0b = EN3 pin has no effect on LDO8 enable

1b = EN3 pin is controlling LDO8

6

5

4

3

2

1

0

R/W

OTP

0b = EN3 pin has no effect on LDO7 enable

1b = EN3 pin is controlling LDO7

0b = EN3 pin has no effect on LDO6 enable

1b = EN3 pin is controlling LDO6

0b = EN3 pin has no effect on LDO5 enable

1b = EN3 pin is controlling LDO5

0b = EN3 pin has no effect on LDO4 enable

1b = EN3 pin is controlling LDO4

0b = EN3 pin has no effect on LDO3 enable

1b = EN3 pin is controlling LDO3

0b = EN3 pin has no effect on LDO2 enable

1b = EN3 pin is controlling LDO2

0b = EN3 pin has no effect on LDO1 enable

1b = EN3 pin is controlling LDO1

8.5.1.3.20 EN3_SET2 Register (Offset = 34h) [reset = OTP]

EN3_SET2 is shown in Table 8-126 and described in Table 8-127.

Return to Summary Table.

Register is reset on a POR event.

Table 8-126. EN3_SET2 Register

7

6

5

4

3

2

1

0

RSVD

R-00b

DCDC4_EN3

R/W-OTP

DCDC3_EN3

R/W-OTP

DCDC2_EN3

R/W-OTP

DCDC1_EN3

R/W-OTP

LDO10_EN3

R/W-OTP

LDO9_EN3

R/W-OTP

Table 8-127. EN3_SET2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

DCDC4_EN3

R/W

OTP

0b = EN3 pin has no effect on DCDC4 enable

1b = EN3 pin is controlling DCDC4

4

DCDC3_EN3

R/W

OTP

0b = EN3 pin has no effect on DCDC3 enable

1b = EN3 pin is controlling DCDC3

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Table 8-127. EN3_SET2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

DCDC2_EN3

R/W

OTP

0b = EN3 pin has no effect on DCDC2 enable

1b = EN3 pin is controlling DCDC2

2

1

0

DCDC1_EN3

LDO10_EN3

LDO9_EN3

R/W

OTP

0b = EN3 pin has no effect on DCDC1 enable

1b = EN3 pin is controlling DCDC1

0b = EN3 pin has no effect on LDO10 enable

1b = EN3 pin is controlling LDO10

0b = EN3 pin has no effect on LDO9 enable

1b = EN3 pin is controlling LDO9

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8.5.1.3.21 EN4_SET1 Register (Offset = 35h) [reset = OTP]

EN4_SET1 is shown in Table 8-128 and described in Table 8-129.

Return to Summary Table.

Register is reset on a POR event.

Table 8-128. EN4_SET1 Register

7

6

5

4

3

2

1

0

LDO8_EN4

R/W-OTP

LDO7_EN4

R/W-OTP

LDO6_EN4

R/W-OTP

LDO5_EN4

R/W-OTP

LDO4_EN4

R/W-OTP

LDO3_EN4

R/W-OTP

LDO2_EN4

R/W-OTP

LDO1_EN4

R/W-OTP

Table 8-129. EN4_SET1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO8_EN4

LDO7_EN4

LDO6_EN4

LDO5_EN4

LDO4_EN4

LDO3_EN4

LDO2_EN4

LDO1_EN4

R/W

OTP

0b = EN4 pin has no effect on LDO8 enable

1b = EN4 pin is controlling LDO8

6

5

4

3

2

1

0

R/W

OTP

0b = EN4 pin has no effect on LDO7 enable

1b = EN4 pin is controlling LDO7

0b = EN4 pin has no effect on LDO6 enable

1b = EN4 pin is controlling LDO6

0b = EN4 pin has no effect on LDO5 enable

1b = EN4 pin is controlling LDO5

0b = EN4 pin has no effect on LDO4 enable

1b = EN4 pin is controlling LDO4

0b = EN4 pin has no effect on LDO3 enable

1b = EN4 pin is controlling LDO3

0b = EN4 pin has no effect on LDO2 enable

1b = EN4 pin is controlling LDO2

0b = EN4 pin has no effect on LDO1 enable

1b = EN4 pin is controlling LDO1

8.5.1.3.22 EN4_SET2 Register (Offset = 36h) [reset = OTP]

EN4_SET2 is shown in Table 8-130 and described in Table 8-131.

Return to Summary Table.

Register is reset on a POR event.

Table 8-130. EN4_SET2 Register

7

6

5

4

3

2

1

0

RSVD

R-00b

DCDC4_EN4

R/W-OTP

DCDC3_EN4

R/W-OTP

DCDC2_EN4

R/W-OTP

DCDC1_EN4

R/W-OTP

LDO10_EN4

R/W-OTP

LDO9_EN4

R/W-OTP

Table 8-131. EN4_SET2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

DCDC4_EN4

R/W

OTP

0b = EN4 pin has no effect on DCDC4 enable

1b = EN4 pin is controlling DCDC4

4

DCDC3_EN4

R/W

OTP

0b = EN4 pin has no effect on DCDC3 enable

1b = EN4 pin is controlling DCDC3

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Table 8-131. EN4_SET2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

DCDC2_EN4

R/W

OTP

0b = EN4 pin has no effect on DCDC2 enable

1b = EN4 pin is controlling DCDC2

2

1

0

DCDC1_EN4

LDO10_EN4

LDO9_EN4

R/W

OTP

0b = EN4 pin has no effect on DCDC1 enable

1b = EN4 pin is controlling DCDC1

0b = EN4 pin has no effect on LDO10 enable

1b = EN4 pin is controlling LDO10

0b = EN4 pin has no effect on LDO9 enable

1b = EN4 pin is controlling LDO9

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8.5.1.3.23 PGOOD Register (Offset = 37h) [reset = OTP]

PGOOD is shown in Table 8-132 and described in Table 8-133.

Return to Summary Table.

Register is reset on a POR event.

Table 8-132. PGOOD Register

7

6

5

4

3

2

1

0

PGOOD_DCDC PGOOD_DCDC PGOOD_DCDC PGOOD_DCDC

PGOOD_LDO4 PGOOD_LDO3 PGOOD_LDO2 PGOOD_LDO1

R-0b R-0b R-0b R-0b

4

3

2

1

R-0b

Table 8-133. PGOOD Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

4

3

PGOOD_LDO4

PGOOD_LDO3

PGOOD_LDO2

PGOOD_LDO1

PGOOD_DCDC4

R

0b

The bit is set or cleared by the power-good comparator in the LDO

converter block

0b = LDO4 output voltage is below its target regulation voltage or

disabled

1b = LDO4 output voltage is in regulation

R

0b

The bit is set or cleared by the power-good comparator in the LDO

converter block

0b = LDO3 output voltage is below its target regulation voltage or

disabled

1b = LDO3 output voltage is in regulation

The bit is set or cleared by the power-good comparator in the LDO

converter block

0b = LDO2 output voltage is below its target regulation voltage or

disabled

1b = LDO2 output voltage is in regulation

The bit is set or cleared by the power-good comparator in the LDO

converter block

0b = LDO1 output voltage is below its target regulation voltage or

disabled

1b = LDO1 output voltage is in regulation

The bit is set or cleared by the power-good comparator in the DC-DC

converter block

The PGOOD_LDO4 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = DCDC4 output voltage is below its target regulation voltage or

disabled

1b = DCDC4 output voltage is in regulation

2

PGOOD_DCDC3

R

0b

The bit is set or cleared by the power-good comparator in the DC-DC

converter block

The PGOOD_LDO3 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = DCDC3 output voltage is below its target regulation voltage or

disabled

1b = DCDC3 output voltage is in regulation

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Table 8-133. PGOOD Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

1

PGOOD_DCDC2

R

0b

The bit is set or cleared by the power-good comparator in the DC-DC

converter block

The PGOOD_LDO2 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = DCDC2 output voltage is below its target regulation voltage or

disabled

1b = DCDC2 output voltage is in regulation

0

PGOOD_DCDC1

R

0b

The bit is set or cleared by the power-good comparator in the DC-DC

converter block

The PGOOD_LDO1 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = DCDC1 output voltage is below its target regulation voltage or

disabled

1b = DCDC1 output voltage is in regulation

8.5.1.3.24 PGOOD2 Register (Offset = 38h) [reset = OTP]

PGOOD2 is shown in Table 8-134 and described in Table 8-135.

Return to Summary Table.

Register is reset on a POR event.

Table 8-134. PGOOD2 Register

7

6

5

4

3

2

1

0

PGOOD_LDO1

0

RSVD

R-00b

PGOOD_LDO9 PGOOD_LDO8 PGOOD_LDO7 PGOOD_LDO6 PGOOD_LDO5

R-0b R-0b R-0b R-0b R-0b

R-0b

Table 8-135. PGOOD2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

PGOOD_LDO10

R

0b

The bit is set or cleared by the power-good comparator in the LDO

converter block

The PGOOD_LDO10 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = LDO10 output voltage is below its target regulation voltage or

disabled

1b = LDO10 output voltage is in regulation

4

PGOOD_LDO9

R

0b

The bit is set or cleared by the power-good comparator in the LDO

converter block

The PGOOD_LDO9 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = LDO9 output voltage is below its target regulation voltage or

disabled

1b = LDO9 output voltage is in regulation

112

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Table 8-135. PGOOD2 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3

PGOOD_LDO8

R

0b

The bit is set or cleared by the power-good comparator in the LDO

converter block

The PGOOD_LDO8 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = LDO8 output voltage is below its target regulation voltage or

disabled

1b = LDO8 output voltage is in regulation

2

1

0

PGOOD_LDO7

PGOOD_LDO6

PGOOD_LDO5

R

0b

The bit is set or cleared by the power-good comparator in the LDO

converter block

The PGOOD_LDO7 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = LDO7 output voltage is below its target regulation voltage or

disabled

1b = LDO7 output voltage is in regulation

The bit is set or cleared by the power-good comparator in the LDO

converter block

The PGOOD_LDO6 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = LDO6 output voltage is below its target regulation voltage or

disabled

1b = LDO6 output voltage is in regulation

The bit is set or cleared by the power-good comparator in the LDO

converter block

The PGOOD_LDO5 bit is not valid if the LDO is enabled but the

supply voltage to the LDO is below 1 V.

0b = LDO5 output voltage is below its target regulation voltage or

disabled

1b = LDO5 output voltage is in regulation

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8.5.1.3.25 INT_STS Register (Offset = 39h) [reset = 00h]

INT_STS is shown in Table 8-136 and described in Table 8-137.

Return to Summary Table.

Register is reset on a POR event.

Table 8-136. INT_STS Register

7

6

5

4

3

2

1

0

PWRHOLD_R_I

T

PWRHOLD_F_I

T

GPIO1_F_IT

R/W-0b

GPIO1_R_IT

R/W-0b

HOTDIE_IT

R/W-0b

PWRON_LP_IT

R/W-0b

PWRON_IT

R/W-0b

VMON_IT

R/W-0b

Table 8-137. INT_STS Register Field Descriptions

Bit

Field

GPIO1_F_IT

Type

Reset

Description

7

R/W

0b

0b = No falling edge occurred

1b = GPIO1 falling edge detection interrupt status; write 1b to clear

the interrupt flag

6

GPIO1_R_IT

R/W

0b

0b = No rising edge occurred

1b = GPIO1 rising edge detection interrupt status; write 1b to clear

the interrupt flag

5

4

HOTDIE_IT

R/W

0b

0b = No hot die event occurred

1b = Hot die event interrupt status; write 1b to clear the interrupt flag

PWRHOLD_R_IT

0b = No rising edge on the PWRHOLD pin is detected

1b = Rising PWRHOLD event interrupt status; write 1b to clear the

interrupt flag

3

2

1

PWRON_LP_IT

PWRON_IT

VMON_IT

R/W

0b

0b = No nPWRON long press key detected

1b = nPWRON long press event interrupt status; write 1b to clear the

interrupt flag

0b = No nPWRON event detected

1b = nPWRON event interrupt status; write 1b to clear the interrupt

flag

0b = No VMON event detected

1b = falling edge detection for VMON; voltage at VMON is below the

VMON_SEL[1:0] threshold; no delay; write 1b to clear the interrupt

flag

0

PWRHOLD_F_IT

R/W

0b

0b = No PWRHOLD event detected

1b = Falling PWRHOLD event interrupt status; write 1b to clear the

interrupt flag

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8.5.1.3.26 INT_MSK Register (Offset = 3Ah) [reset = FFh]

INT_MSK is shown in Table 8-138 and described in Table 8-139.

Return to Summary Table.

Register is reset on a POR event.

Table 8-138. INT_MSK Register

7

6

5

4

3

2

1

0

GPIO1_F_

IT_MSK

GPIO1_R_

IT_MSK

HOTDIE_

IT_MSK

PWRHOLD_R_ PWRON_LP_

PWRON_

IT_MSK

VMON_

IT_MSK

PWRHOLD_F_

IT_MSK

R/W-OTP

Table 8-139. INT_MSK Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO1_F_IT_MSK

GPIO1_R_IT_MSK

HOTDIE_IT_MSK

R/W

OTP

0b = Interrupt not masked

OTP = GPIO1 falling edge detection interrupt masked

6

5

4

3

2

1

0

R/W

OTP

0b = Interrupt not masked

OTP = GPIO1 rising edge detection interrupt masked

0b = Interrupt not masked

OTP = Hot die event interrupt masked

PWRHOLD_R_IT_MSK

PWRON_LP_IT_MSK

PWRON_IT_MSK

0b = Interrupt not masked

OTP = Rising PWRHOLD event interrupt masked

0b = Interrupt not masked

OTP = nPWRON Long Press event interrupt masked

0b = Interrupt not masked

OTP = nPWRON event interrupt masked

VMON_IT_MSK

0b = Interrupt not masked

OTP = VMON event interrupt masked.

PWRHOLD_F_IT_MSK

0b = Interrupt not masked

OTP = PWRHOLD falling edge event interrupt masked

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8.5.1.3.27 INT_STS2 Register (Offset = 3Bh) [reset = 00h]

INT_STS2 is shown in Table 8-140 and described in Table 8-141.

Return to Summary Table.

Register is reset on a POR event.

Table 8-140. INT_STS2 Register

7

6

5

4

3

2

1

0

GPIO5_F_IT

R/W-0b

GPIO5_R_IT

R/W-0b

GPIO4_F_IT

R/W-0b

GPIO4_R_IT

R/W-0b

GPIO3_F_IT

R/W-0b

GPIO3_R_IT

R/W-0b

GPIO2_F_IT

R/W-0b

GPIO2_R_IT

R/W-0b

Table 8-141. INT_STS2 Register Field Descriptions

Bit

Field

GPIO5_F_IT

Type

Reset

Description

7

R/W

0b

0b = No falling edge occurred

1b = GPIO5 falling edge detection interrupt status; write 1b to clear

the interrupt flag

6

5

4

3

2

1

0

GPIO5_R_IT

GPIO4_F_IT

GPIO4_R_IT

GPIO3_F_IT

GPIO3_R_IT

GPIO2_F_IT

GPIO2_R_IT

R/W

0b

0b = No rising edge occurred

1b = GPIO5 rising edge detection interrupt status; write 1b to clear

the interrupt flag

0b = No falling edge occurred

1b = GPIO4 falling edge detection interrupt status; write 1b to clear

the interrupt flag

0b = No rising edge occurred

1b = GPIO4 rising edge detection interrupt status; write 1b to clear

the interrupt flag

0b = No falling edge occurred

1b = GPIO3 falling edge detection interrupt status; write 1b to clear

the interrupt flag

0b = No rising edge occurred

1b = GPIO3 rising edge detection interrupt status; write 1b to clear

the interrupt flag

0b = No falling edge occurred

1b = GPIO2 falling edge detection interrupt status; write 1b to clear

the interrupt flag

0b = No rising edge occurred

1b = GPIO2 rising edge detection interrupt status; write 1b to clear

the interrupt flag

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8.5.1.3.28 INT_MSK2 Register (Offset = 3Ch) [reset = OTP]

INT_MSK2 is shown in Table 8-142 and described in Table 8-143.

Return to Summary Table.

Register is reset on a POR event.

Table 8-142. INT_MSK2 Register

7

6

5

4

3

2

1

0

GPIO5_F_

IT_MSK

GPIO5_R_

IT_MSK

GPIO4_F_

IT_MSK

GPIO4_R_

IT_MSK

GPIO3_F_

IT_MSK

GPIO3_R_

IT_MSK

GPIO2_F_

IT_MSK

GPIO2_R_

IT_MSK

R/W-OTP

Table 8-143. INT_MSK2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO5_F_IT_MSK

GPIO5_R_IT_MSK

GPIO4_F_IT_MSK

GPIO4_R_IT_MSK

GPIO3_F_IT_MSK

GPIO3_R_IT_MSK

GPIO2_F_IT_MSK

GPIO2_R_IT_MSK

R/W

OTP

0b = Interrupt not masked

1b = GPIO5 falling edge detection interrupt masked

6

5

4

3

2

1

0

R/W

OTP

0b = Interrupt not masked

1b = GPIO5 rising edge detection interrupt masked

0b = Interrupt not masked

1b = GPIO4 falling edge detection interrupt masked

0b = Interrupt not masked

1b = GPIO4 rising edge detection interrupt masked

0b = Interrupt not masked

1b = GPIO3 falling edge detection interrupt masked

0b = Interrupt not masked

1b = GPIO3 rising edge detection interrupt masked

0b = Interrupt not masked

1b = GPIO2 falling edge detection interrupt masked

0b = Interrupt not masked

1b = GPIO2 rising edge detection interrupt masked

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8.5.1.3.29 INT_STS3 Register (Offset = 3Dh) [reset = OTP]

INT_STS3 is shown in Table 8-144 and described in Table 8-145.

Return to Summary Table.

Register is reset on a POR event.

Table 8-144. INT_STS3 Register

7

6

5

4

3

2

1

0

PGOOD_LDO4 PGOOD_LDO3 PGOOD_LDO2 PGOOD_LDO1 PGOOD_DCDC PGOOD_DCDC PGOOD_DCDC PGOOD_DCDC

_IT

4_IT

3_IT

2_IT

1_IT

R/W-0b

Table 8-145. INT_STS3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PGOOD_LDO4_IT

PGOOD_LDO3_IT

PGOOD_LDO2_IT

PGOOD_LDO1_IT

PGOOD_DCDC4_IT

R/W

0b

0b = No status change occurred

1b = PGOOD_LDO4 falling edge detection interrupt status; masked

by the ENABLE bit, therefore not triggered if the output voltage drops

when the LDO is disabled; write 1b to clear the interrupt flag

6

5

4

3

R/W

0b

0b = No status change occurred

1b = PGOOD_LDO3 falling edge detection interrupt status; masked

by the ENABLE bit, therefore not triggered if the output voltage drops

when the LDO is disabled; write 1b to clear the interrupt flag

0b = No status change occurred

1b = PGOOD_LDO2 falling edge detection interrupt status; masked

by the ENABLE bit, therefore not triggered if the output voltage drops

when the LDO is disabled; write 1b to clear the interrupt flag

0b = No status change occurred

1b = PGOOD_LDO1 falling edge detection interrupt status; masked

by the ENABLE bit, therefore not triggered if the output voltage drops

when the LDO is disabled; write 1b to clear the interrupt flag

0b = No status change occurred

1b = PGOOD_DCDC4 falling edge detection interrupt status;

masked by the ENABLE bit, therefore not triggered if the output

voltage drops when the converter is disabled; write 1b to clear the

interrupt flag

2

1

0

PGOOD_DCDC3_IT

PGOOD_DCDC2_IT

PGOOD_DCDC1_IT

R/W

0b

0b = No status change occurred

1b = PGOOD_DCDC3 falling edge detection interrupt status;

masked by the ENABLE bit, therefore not triggered if the output

voltage drops when the converter is disabled; write 1b to clear the

interrupt flag

0b = No status change occurred

1b = PGOOD_DCDC2 falling edge detection interrupt status;

masked by the ENABLE bit, therefore not triggered if the output

voltage drops when the converter is disabled; write 1b to clear the

interrupt flag

0b = No status change occurred

1b = PGOOD_DCDC1 falling edge detection interrupt status;

masked by the ENABLE bit, therefore not triggered if the output

voltage drops when the converter is disabled; write 1b to clear the

interrupt flag

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8.5.1.3.30 INT_MSK3 Register (Offset = 3Eh) [reset = FFh]

INT_MSK3 is shown in Table 8-146 and described in Table 8-147.

Return to Summary Table.

Register is reset on a POR event.

Table 8-146. INT_MSK3 Register

7

6

5

4

3

2

1

0

PGOOD_LDO4 PGOOD_LDO3 PGOOD_LDO2 PGOOD_LDO1 PGOOD_DCDC PGOOD_DCDC PGOOD_DCDC PGOOD_DCDC

_

4_

3_

2_

1_

IT_MSK

R/W-1b

Table 8-147. INT_MSK3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PGOOD_LDO4_IT_MSK R/W

PGOOD_LDO3_IT_MSK R/W

PGOOD_LDO2_IT_MSK R/W

PGOOD_LDO1_IT_MSK R/W

PGOOD_DCDC4_IT_MSK R/W

PGOOD_DCDC3_IT_MSK R/W

PGOOD_DCDC2_IT_MSK R/W

PGOOD_DCDC1_IT_MSK R/W

1b

0b = Interrupt not masked

1b = PGOOD_LDO4 falling edge detection interrupt status; masked

by the ENABLE bit, therefore not triggered if the output voltage drops

when the LDO is disabled

6

5

4

3

2

1

0

1b

0b = Interrupt not masked

1b = PGOOD_LDO3 falling edge detection interrupt status; masked

by the ENABLE bit, therefore not triggered if the output voltage drops

when the LDO is disabled

0b = Interrupt not masked

1b = PGOOD_LDO2 falling edge detection interrupt status; masked

by the ENABLE bit, therefore not triggered if the output voltage drops

when the LDO is disabled

0b = Interrupt not masked

1b = PGOOD_LDO1 falling edge detection interrupt status; masked

by the ENABLE bit, therefore not triggered if the output voltage drops

when the LDO is disabled

0b = Interrupt not masked

1b = PGOOD_DCDC4 falling edge detection interrupt status;

masked by the ENABLE bit, therefore not triggered if the output

voltage drops when the LDO is disabled

0b = Interrupt not masked

1b = PGOOD_DCDC3 falling edge detection interrupt status;

masked by the ENABLE bit, therefore not triggered if the output

voltage drops when the LDO is disabled

0b = Interrupt not masked

1b = PGOOD_DCDC2 falling edge detection interrupt status;

masked by the ENABLE bit, therefore not triggered if the output

voltage drops when the LDO is disabled

0b = Interrupt not masked

1b = PGOOD_DCDC1 falling edge detection interrupt status;

masked by the ENABLE bit, therefore not triggered if the output

voltage drops when the LDO is disabled

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8.5.1.3.31 INT_STS4 Register (Offset = 3Fh) [reset = 00h]

INT_STS4 is shown in Table 8-148 and described in Table 8-149.

Return to Summary Table.

Register is reset on a POR event.

Table 8-148. INT_STS4 Register

7

6

5

4

3

2

1

0

PGOOD_LDO1 PGOOD_LDO9 PGOOD_LDO8 PGOOD_LDO7 PGOOD_LDO6 PGOOD_LDO5

RSVD

0_IT

_IT

R/W-00b

R/W-0b

Table 8-149. INT_STS4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R/W

00b

Unused bit read returns 0b.

PGOOD_LDO10_IT

PGOOD_LDO9_IT

PGOOD_LDO8_IT

PGOOD_LDO7_IT

PGOOD_LDO6_IT

PGOOD_LDO5_IT

R/W

0b

0b = No status change occurred

1b = PGOOD_LDO10 falling or rising edge detection interrupt status;

write 1b to clear the interrupt flag

4

3

2

1

0

0b = No status change occurred

1b = PGOOD_LDO9 falling or rising edge detection interrupt status;

write 1b to clear the interrupt flag

0b = No status change occurred

1b = PGOOD_LDO8 falling or rising edge detection interrupt status;

write 1b to clear the interrupt flag

0b = No status change occurred

1b = PGOOD_LDO7 falling or rising edge detection interrupt status;

write 1b to clear the interrupt flag

0b = No status change occurred

1b = PGOOD_LDO6 falling or rising edge detection interrupt status;

write 1b to clear the interrupt flag

0b = No status change occurred

1b = PGOOD_LDO5 falling or rising edge detection interrupt status;

write 1b to clear the interrupt flag

8.5.1.3.32 INT_MSK4 Register (Offset = 40h) [reset = FFh]

INT_MSK4 is shown in Table 8-150 and described in Table 8-151.

Return to Summary Table.

Register is reset on a POR event.

Table 8-150. INT_MSK4 Register

7

6

5

4

3

2

1

0

PGOOD_LDO1 PGOOD_LDO9 PGOOD_LDO8 PGOOD_LDO7 PGOOD_LDO6 PGOOD_LDO5

RSVD

0_

_

IT_MSK

R/W-11b

R/W-1b

Table 8-151. INT_MSK4 Register Field Descriptions

Bit

7-6

Field

Type

Reset

Description

RSVD

R/W

11b

Unused bit read returns 0b.

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Table 8-151. INT_MSK4 Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5

PGOOD_LDO10_IT_MSK R/W

1b

0b = Interrupt not masked

1b = PGOOD_LDO10 falling or rising edge detection interrupt

masked

4

3

2

1

0

PGOOD_LDO9_IT_MSK R/W

PGOOD_LDO8_IT_MSK R/W

PGOOD_LDO7_IT_MSK R/W

PGOOD_LDO6_IT_MSK R/W

PGOOD_LDO5_IT_MSK R/W

1b

0b = Interrupt not masked

1b = PGOOD_LDO9 falling or rising edge detection interrupt masked

0b = Interrupt not masked

1b = PGOOD_LDO8 falling or rising edge detection interrupt masked

0b = Interrupt not masked

1b = PGOOD_LDO7 falling or rising edge detection interrupt masked

0b = Interrupt not masked

1b = PGOOD_LDO6 falling or rising edge detection interrupt masked

0b = Interrupt not masked

1b = PGOOD_LDO5 falling or rising edge detection interrupt masked

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8.5.1.3.33 GPIO1 Register (Offset = 41h) [reset = OTP]

GPIO1 is shown in Table 8-152 and described in Table 8-153.

Return to Summary Table.

Register is reset on a POR event.

Table 8-152. GPIO1 Register

7

6

5

4

3

2

1

0

GPIO_SLEEP

R/W-OTP

RSVD

R-00b

GPIO_DEB

R/W-OTP

RSVD

R-0b

GPIO_CFG

R/W-OTP

GPIO_STS

R-x

GPIO_SET

R/W-OTP

Table 8-153. GPIO1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO_SLEEP

R/W

OTP

0b = No impact, keep as in ACTIVE state

1b = When in the SLEEP state and GPIO in output mode, force

output low

6-5

4

RSVD

R

00b

Unused bit read returns 0b.

GPIO_DEB

R/W

OTP

GPIO input debouncing time

0b = 94 µs

1b = 156 µs

3

2

RSVD

R

0b

Unused bit

GPIO_CFG

R/W

OTP

Configuration of the GPIO pad direction

0b = The GPIO pad is configured as an input

1b = The GPIO pad is configured as an output, GPIO assigned to

power-up sequence

1

0

GPIO_STS

GPIO_SET

R

x

This bit has no reset value, it is generated based on GPIO pad

voltage in real-time

0b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

1b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

R/W

OTP

0b = Value set to logic 0b on the GPIO output when configured in

output mode

1b = Value set to logic 1b on the GPIO output when configured in

output mode

8.5.1.3.34 GPIO2 Register (Offset = 42h) [reset = OTP]

GPIO2 is shown in Table 8-154 and described in Table 8-155.

Return to Summary Table.

Register is reset on a POR event.

Table 8-154. GPIO2 Register

7

6

5

4

3

2

1

0

GPIO_SLEEP

R/W-OTP

RSVD

R-00b

GPIO_DEB

R/W-OTP

RSVD

R-0b

GPIO_CFG

R/W-OTP

GPIO_STS

R-x

GPIO_SET

R/W-OTP

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Table 8-155. GPIO2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO_SLEEP

R/W

OTP

0b = No impact, keep as in ACTIVE state

1b = When in the SLEEP state and GPIO in output mode, force

output low

6-5

4

RSVD

R

00b

Unused bit read returns 0b.

GPIO_DEB

R/W

GPIO input debouncing time

0b = 94 µs

1b = 156 µs

3

2

RSVD

R

0b

Unused bit

GPIO_CFG

R/W

OTP

Configuration of the GPIO pad direction

0b = The GPIO pad is configured as an input

1b = The GPIO pad is configured as an output, GPIO assigned to

power-up sequence

1

0

GPIO_STS

GPIO_SET

R

x

This bit has no reset value, it is generated based on GPIO pad

voltage in real-time

0b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

1b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

R/W

OTP

0b = Value set to logic 0b on the GPIO output when configured in

output mode

1b = Value set to logic 1b on the GPIO output when configured in

output mode

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8.5.1.3.35 GPIO3 Register (Offset = 43h) [reset = OTP]

GPIO3 is shown in Table 8-156 and described in Table 8-157.

Return to Summary Table.

Register is reset on a POR event.

Table 8-156. GPIO3 Register

7

6

5

4

3

2

1

0

GPIO_SLEEP

R/W-OTP

GPIO_SEL

R/W-OTP

GPIO_ODEN

R/W-OTP

GPIO_DEB

R/W-OTP

GPIO_PDEN

R/W-OTP

GPIO_CFG

R/W-OTP

GPIO_STS

R-x

GPIO_SET

R/W-OTP

Table 8-157. GPIO3 Register Field Descriptions

Bit

Field

GPIO_SLEEP

Type

Reset

Description

7

R/W

OTP

0b = No impact, keep as in ACTIVE state

1b = When in the SLEEP state and GPIO in output mode, force

output low

6

GPIO_SEL

R/W

OTP

0b = GPIO_SET to be available at the GPIO pin when configured as

output

1b = LEDA out to be available at the GPIO pin when configured as

output

5

4

GPIO_ODEN

GPIO_DEB

R/W

OTP

0b = Push-pull output mode, GPIO assigned to power-up sequence

1b = Open drain output mode

GPIO input debouncing time

0b = 94 µs

1b = 156 µs

3

2

GPIO_PDEN

GPIO_CFG

R/W

OTP

GPIO pad pulldown control

0b = Pulldown is disabled

1b = Pulldown is enabled

Configuration of the GPIO pad direction

0b = The GPIO pad is configured as an input

1b = The GPIO pad is configured as an output, GPIO assigned to

power-up sequence

1

0

GPIO_STS

GPIO_SET

R

x

This bit has no reset value, it is generated based on GPIO pad

voltage in real-time

0b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

1b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

R/W

OTP

0b = Value set to logic 0b on the GPIO output when configured in

output mode

1b = Value set to logic 1b on the GPIO output when configured in

output mode

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8.5.1.3.36 GPIO4 Register (Offset = 44h) [reset = OTP]

GPIO4 is shown in Table 8-158 and described in Table 8-159.

Return to Summary Table.

Register is reset on a POR event.

Table 8-158. GPIO4 Register

7

6

5

4

3

2

1

0

GPIO_SLEEP

R/W-OTP

GPIO_SEL

R/W-OTP

GPIO_ODEN

R/W-OTP

GPIO_DEB

R/W-OTP

GPIO_PDEN

R/W-OTP

GPIO_CFG

R/W-OTP

GPIO_STS

R-x

GPIO_SET

R/W-OTP

Table 8-159. GPIO4 Register Field Descriptions

Bit

Field

GPIO_SLEEP

Type

Reset

Description

7

R/W

OTP

0b = No impact, keep as in ACTIVE state

1b = When in the SLEEP state and GPIO in output mode, force

output low

6

GPIO_SEL

R/W

OTP

0b = GPIO_SET to be available at the GPIO pin when configured as

output

1b = LEDB out to be available at the GPIO pin when configured as

output

5

4

GPIO_ODEN

GPIO_DEB

R/W

OTP

0b = Push-pull output mode, GPIO assigned to power-up sequence

1b = Open drain output mode

GPIO input debouncing time

0b = 94 µs

1b = 156 µs

3

2

GPIO_PDEN

GPIO_CFG

R/W

OTP

GPIO pad pulldown control

0b = Pulldown is disabled

1b = Pulldown is enabled

Configuration of the GPIO pad direction

0b = The pad is configured as an input

1b = The GPIO pad is configured as an output, GPIO assigned to

power-up sequence

1

0

GPIO_STS

GPIO_SET

R

x

This bit has no reset value, it is generated based on GPIO pad

voltage in real-time

0b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

1b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

R/W

OTP

0b = Value set to logic 0b on the GPIO output when configured in

output mode

1b = Value set to logic 1b on the GPIO output when configured in

output mode

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8.5.1.3.37 GPIO5 Register (Offset = 45h) [reset = OTP]

GPIO5 is shown in Table 8-160 and described in Table 8-161.

Return to Summary Table.

Register is reset on a POR event.

Table 8-160. GPIO5 Register

7

6

5

4

3

2

1

0

GPIO_SLEEP

R/W-OTP

GPIO_SEL

R/W-OTP

GPIO_ODEN

R/W-OTP

GPIO_DEB

R/W-OTP

GPIO_PDEN

R/W-OTP

GPIO_CFG

R/W-OTP

GPIO_STS

R-x

GPIO_SET

R/W-OTP

Table 8-161. GPIO5 Register Field Descriptions

Bit

Field

GPIO_SLEEP

Type

Reset

Description

7

R/W

OTP

0b = No impact, keep as in ACTIVE state

1b = When in the SLEEP state and GPIO in output mode, force

output low

6

GPIO_SEL

R/W

OTP

0b = GPIO_SET to be available at the GPIO pin when configured as

output

1b = LEDC out to be available at the GPIO pin when configured as

output

5

4

GPIO_ODEN

GPIO_DEB

R/W

OTP

0b = Push-pull output mode, GPIO assigned to power-up sequence

1b = Open drain output mode

GPIO input debouncing time

0b = 94 µs

1b = 156 µs

3

2

GPIO_PDEN

GPIO_CFG

R/W

OTP

GPIO pad pulldown control

0b = Pulldown is disabled

1b = Pulldown is enabled

Configuration of the GPIO pad direction

0b = The pad is configured as an input

1b = The GPIO pad is configured as an output, GPIO assigned to

power-up sequence

1

0

GPIO_STS

GPIO_SET

R

x

This bit has no reset value, it is generated based on GPIO pad

voltage in real-time

0b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

1b = Voltage on GPIO pad is greater than V_IHif configured as an

input, V_OHif configured as an output

R/W

OTP

0b = Value set to logic 0b on the GPIO output when configured in

output mode

1b = Value set to logic 1b on the GPIO output when configured in

output mode

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8.5.1.3.38 VMON Register (Offset = 46h) [reset = OTP]

VMON is shown in Table 8-162 and described in Table 8-163.

Return to Summary Table.

Register is reset on a POR event.

Table 8-162. VMON Register

7

6

5

4

3

2

1

0

RSVD

R-0b

VMON_DELAY[1:0]

R/W-OTP

VSUP_MASK

R/W-OTP

RSVD

R-0b

VSUP_OUT

R-x

VMON_SEL[1:0]

R/W-OTP

Table 8-163. VMON Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6

VMON_DELAY[1:0]

R/W

OTP

Delays the output signal at the VSUP_OUT pin for a falling input

voltage on the VMON_IN pin to allow an interrupt to be generated

before the VSUP_OUT pin goes low

00b = No falling edge delay

01b = 50-µs falling edge delay

10b = 100-µs falling edge delay

11b = 250-µs falling edge delay

5

VSUP_MASK

R/W

OTP

0b = The output of the voltage monitor is not used as a switch-off

event

1b = The output of the voltage monitor is used as a switch-off event

4

3

RSVD

R

0b

x

Unused bit

VSUP_OUT

This bit has no reset value, it is generated based on the status output

of the voltage monitor:

0b = The voltage at the VCCS/VIN_MON pin is below the VMON

threshold

1b = The voltage at the VCCS/VIN_MON pin is above the VMON

threshold

2

VMON_SEL[1:0]

R/W

OTP

Battery voltage comparator threshold:

00b = VMON threshold is 3.1 V (rising voltage)

01b = VMON threshold is 2.9 V (rising voltage)

10b = VMON threshold is 2.8 V (rising voltage)

11b = VMON threshold is 2.7 V (rising voltage)

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8.5.1.3.39 LEDA_CTRL1 Register (Offset = 47h) [reset = 00h]

LEDA_CTRL1 is shown in Table 8-164 and described in Table 8-165.

Return to Summary Table.

Register is reset on a POR event.

Table 8-164. LEDA_CTRL1 Register

7

6

5

4

3

2

1

0

LEDA_RAMP_

ENABLE

RSVD

R-00b

RSVD

R-0b

LEDA_CURRENT[3:0]

R/W-0000b

R/W-0b

Table 8-165. LEDA_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

LEDA_RAMP_ENABLE

R/W

0b

0b = No ramp

1b = Ramp enabled

4

RSVD

R

0b

Unused bit

3-0

LEDA_CURRENT[3:0]

R/W

0000b

LEDA DC current. See Table 8-218

8.5.1.3.40 LEDA_CTRL2 Register (Offset = 48h) [reset = 00h]

LEDA_CTRL2 is shown in Table 8-166 and described in Table 8-167.

Return to Summary Table.

Register is reset on a POR event.

Table 8-166. LEDA_CTRL2 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDA_T1[6:0]

R/W-0000000b

Table 8-167. LEDA_CTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDA_T1[6:0]

R/W

0000000b

LEDA T1 sequence length = LEDA_T1[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.41 LEDA_CTRL3 Register (Offset = 49h) [reset = 00h]

LEDA_CTRL3 is shown in Table 8-168 and described in Table 8-169.

Return to Summary Table.

Register is reset on a POR event.

Table 8-168. LEDA_CTRL3 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDA_T2[6:0]

R/W-0000000b

Table 8-169. LEDA_CTRL3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDA_T2[6:0]

R/W

0000000b

LEDA T2 sequence length = LEDA_T2[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

8.5.1.3.42 LEDA_CTRL4 Register (Offset = 4Ah) [reset = 00h]

LEDA_CTRL4 is shown in Table 8-170 and described in Table 8-171.

Return to Summary Table.

Register is reset on a POR event.

Table 8-170. LEDA_CTRL4 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDA_T3[6:0]

R/W-0000000b

Table 8-171. LEDA_CTRL4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDA_T3[6:0]

R/W

0000000b

LEDA T3 sequence length = LEDA_T3[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.43 LEDA_CTRL5 Register (Offset = 4Bh) [reset = 00h]

LEDA_CTRL5 is shown in Table 8-172 and described in Table 8-173.

Return to Summary Table.

Register is reset on a POR event.

Table 8-172. LEDA_CTRL5 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDA_T4[6:0]

R/W-0000000b

Table 8-173. LEDA_CTRL5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDA_T4[6:0]

R/W

0000000b

LEDA T4 sequence length = LEDA_T4[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

8.5.1.3.44 LEDA_CTRL6 Register (Offset = 4Ch) [reset = 00h]

LEDA_CTRL6 is shown in Table 8-174 and described in Table 8-175.

Return to Summary Table.

Register is reset on a POR event.

Table 8-174. LEDA_CTRL6 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDA_TP[6:0]

R/W-0000000b

Table 8-175. LEDA_CTRL6 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDA_TP[6:0]

R/W

0000000b

LEDA TP sequence length = LEDA_TP[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.45 LEDA_CTRL7 Register (Offset = 4Dh) [reset = 00h]

LEDA_CTRL7 is shown in Table 8-176 and described in Table 8-177.

Return to Summary Table.

Register is reset on a POR event.

Table 8-176. LEDA_CTRL7 Register

7

6

5

4

3

2

1

0

RSVD

R-000b

LEDA_PWM[4:0]

R/W-00000b

Table 8-177. LEDA_CTRL7 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RSVD

R

000b

Unused bit read returns 0b.

LEDA_PWM[4:0]

R/W

00000b

LEDA_ON duty-cycle: ([LEDA_PWM] +1) × 1 / 32 × 8-ms period

00000b = 1 / 2 × 8 ms (LEDA_ON is high for 250 µs, low for 7.75 ms)

11111b = 32 / 32 × 8 ms (LEDA_ON is always high)

8.5.1.3.46 LEDA_CTRL8 Register (Offset = 4Eh) [reset = 00h]

LEDA_CTRL8 is shown in Table 8-178 and described in Table 8-179.

Return to Summary Table.

Register is reset on a POR event.

Table 8-178. LEDA_CTRL8 Register

7

6

5

4

3

2

1

0

RSVD

R-000b

LEDA_ON_TIME[4:0]

R/W-00000b

Table 8-179. LEDA_CTRL8 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RSVD

R

000b

Unused bit read returns 0b.

LEDA_ON_TIME[4:0]

R/W

00000b

LEDA ON-TIME: LEDA_ON_TME[4:0] × 64 ms

00000b = 0 × 64 ms

11111b = 31 × 64 ms

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8.5.1.3.47 LEDB_CTRL1 Register (Offset = 4Fh) [reset = 00h]

LEDB_CTRL1 is shown in Table 8-180 and described in Table 8-181.

Return to Summary Table.

Register is reset on a POR event.

Table 8-180. LEDB_CTRL1 Register

7

6

5

4

3

2

1

0

LEDB_RAMP_

ENABLE

RSVD

R-00b

RSVD

R-0b

LEDB_CURRENT[3:0]

R/W-0000b

R/W-0b

Table 8-181. LEDB_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

LEDB_RAMP_ENABLE

R/W

0b

0b = No ramp

1b = Ramp enabled

4

RSVD

R

0b

Unused bit

3-0

LEDBA_CURRENT[3:0]

R/W

0000b

LEDB DC current. See Table 8-218

8.5.1.3.48 LEDB_CTRL2 Register (Offset = 50h) [reset = 00h]

LEDB_CTRL2 is shown in Table 8-182 and described in Table 8-183.

Return to Summary Table.

Register is reset on a POR event.

Table 8-182. LEDB_CTRL2 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDB_T1[6:0]

R/W-0000000b

Table 8-183. LEDB_CTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDB_T1[6:0]

R/W

0000000b

LEDB T1 sequence length = LEDB_T1[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.49 LEDB_CTRL3 Register (Offset = 51h) [reset = 00h]

LEDB_CTRL3 is shown in Table 8-184 and described in Table 8-185.

Return to Summary Table.

Register is reset on a POR event.

Table 8-184. LEDB_CTRL3 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDB_T2[6:0]

R/W-0000000b

Table 8-185. LEDB_CTRL3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

000b

Unused bit read returns 0b.

6-0

LEDB_T2[6:0]

R/W

0000000b

LEDB T2 sequence length = LEDB_T2[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

8.5.1.3.50 LEDB_CTRL4 Register (Offset = 52h) [reset = 00h]

LEDB_CTRL4 is shown in Table 8-186 and described in Table 8-187.

Return to Summary Table.

Register is reset on a POR event.

Table 8-186. LEDB_CTRL4 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDB_T3[6:0]

R/W-0000000b

Table 8-187. LEDB_CTRL4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDB_T3[6:0]

R/W

0000000b

LEDB T3 sequence length = LEDB_T3[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.51 LEDB_CTRL5 Register (Offset = 53h) [reset = 00h]

LEDB_CTRL5 is shown in Table 8-188 and described in Table 8-189.

Return to Summary Table.

Register is reset on a POR event.

Table 8-188. LEDB_CTRL5 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDB_T4[6:0]

R/W-0000000b

Table 8-189. LEDB_CTRL5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

000b

Unused bit read returns 0b.

6-0

LEDB_T4[6:0]

R/W

0000000b

LEDB T4 sequence length = LEDB_T4[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

8.5.1.3.52 LEDB_CTRL6 Register (Offset = 54h) [reset = 00h]

LEDB_CTRL6 is shown in Table 8-190 and described in Table 8-191.

Return to Summary Table.

Register is reset on a POR event.

Table 8-190. LEDB_CTRL6 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDB_TP[6:0]

R/W-0000000b

Table 8-191. LEDB_CTRL6 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDB_TP[6:0]

R/W

0000000b

LEDB TP sequence length = LEDB_TP[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.53 LEDB_CTRL7 Register (Offset = 55h) [reset = 00h]

LEDB_CTRL7 is shown in Table 8-192 and described in Table 8-193.

Return to Summary Table.

Register is reset on a POR event.

Table 8-192. LEDB_CTRL7 Register

7

6

5

4

3

2

1

0

RSVD

R-000b

LEDB_PWM[4:0]

R/W-00000b

Table 8-193. LEDB_CTRL7 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RSVD

R

000b

Unused bit read returns 0b.

LEDB_PWM[4:0]

R/W

00000b

LEDB_ON duty-cycle: ([LEDB_PWM] +1) × 1 / 32 × 8-ms period

00000b = 1 / 32 × 8 ms (LEDB_ON is high for 250 µs, low for 7.75

ms)

11111b = 32 / 32 × 8 ms (LEDB_ON is always high)

8.5.1.3.54 LEDB_CTRL8 Register (Offset = 56h) [reset = 00h]

LEDB_CTRL8 is shown in Table 8-194 and described in Table 8-195.

Return to Summary Table.

Register is reset on a POR event.

Table 8-194. LEDB_CTRL8 Register

7

6

5

4

3

2

1

0

RSVD

R-000b

LEDB_ON_TIME[4:0]

R/W-00000b

Table 8-195. LEDB_CTRL8 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RSVD

R

000b

Unused bit read returns 0b.

LEDB_ON_TIME[4:0]

R/W

00000b

LEDB ON-TIME: LEDB_ON_TME[4:0] × 64 ms

00000b = 0 × 64 ms

11111b = 31 × 64 ms

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8.5.1.3.55 LEDC_CTRL1 Register (Offset = 57h) [reset = 00h]

LEDC_CTRL1 is shown in Table 8-196 and described in Table 8-197.

Return to Summary Table.

Register is reset on a POR event.

Table 8-196. LEDC_CTRL1 Register

7

6

5

4

3

2

1

0

LEDC_RAMP_

ENABLE

RSVD

R-00b

RSVD

R-0b

LEDC_CURRENT[3:0]

R/W-0000b

R/W-0b

Table 8-197. LEDC_CTRL1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-6

5

RSVD

R

00b

Unused bit read returns 0b.

LEDC_RAMP_ENABLE

R/W

0b

0b = No ramp

1b = Ramp enabled

4

RSVD

R

0b

Unused bit

3-0

LEDCA_CURRENT[3:0]

R/W

0000b

LEDC DC current. See Table 8-218

8.5.1.3.56 LEDC_CTRL2 Register (Offset = 58h) [reset = 00h]

LEDC_CTRL2 is shown in Table 8-198 and described in Table 8-199.

Return to Summary Table.

Register is reset on a POR event.

Table 8-198. LEDC_CTRL2 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDC_T1[6:0]

R/W-0000000b

Table 8-199. LEDC_CTRL2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDC_T1[6:0]

R/W

0000000b

LEDC T1 sequence length = LEDC_T1[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.57 LEDC_CTRL3 Register (Offset = 59h) [reset = 00h]

LEDC_CTRL3 is shown in Table 8-200 and described in Table 8-201.

Return to Summary Table.

Register is reset on a POR event.

Table 8-200. LEDC_CTRL3 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDC_T2[6:0]

R/W-0000000b

Table 8-201. LEDC_CTRL3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDC_T2[6:0]

R/W

0000000b

LEDC T2 sequence length = LEDC_T2[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

8.5.1.3.58 LEDC_CTRL4 Register (Offset = 5Ah) [reset = 00h]

LEDC_CTRL4 is shown in Table 8-202 and described in Table 8-203.

Return to Summary Table.

Register is reset on a POR event.

Table 8-202. LEDC_CTRL4 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDC_T3[6:0]

R/W-0000000b

Table 8-203. LEDC_CTRL4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDC_T3[6:0]

R/W

0000000b

LEDC T3 sequence length = LEDC_T3[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.59 LEDC_CTRL5 Register (Offset = 5Bh) [reset = 00h]

LEDC_CTRL5 is shown in Table 8-204 and described in Table 8-205.

Return to Summary Table.

Register is reset on a POR event.

Table 8-204. LEDC_CTRL5 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDC_T4[6:0]

R/W-0000000b

Table 8-205. LEDC_CTRL5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDC_T4[6:0]

R/W

0000000b

LEDC T4 sequence length = LEDC_T4[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

8.5.1.3.60 LEDC_CTRL6 Register (Offset = 5Ch) [reset = 00h]

LEDC_CTRL6 is shown in Table 8-206 and described in Table 8-207.

Return to Summary Table.

Register is reset on a POR event.

Table 8-206. LEDC_CTRL6 Register

7

6

5

4

3

2

1

0

RSVD

R-0b

LEDC_TP[6:0]

R/W-0000000b

Table 8-207. LEDC_CTRL6 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6-0

LEDC_TP[6:0]

R/W

0000000b

LEDC TP sequence length = LEDC_TP[6:0] × 64 ms

0000000b = 0 × 64 ms

1111111b = 127 × 64 ms

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8.5.1.3.61 LEDC_CTRL7 Register (Offset = 5Dh) [reset = 00h]

LEDC_CTRL7 is shown in Table 8-208 and described in Table 8-209.

Return to Summary Table.

Register is reset on a POR event.

Table 8-208. LEDC_CTRL7 Register

7

6

5

4

3

2

1

0

RSVD

R-000b

LEDC_PWM[4:0]

R/W-00000b

Table 8-209. LEDC_CTRL7 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RSVD

R

000b

Unused bit read returns 0b.

LEDC_PWM[4:0]

R/W

00000b

LEDC_ON duty-cycle: ([LEDC_PWM] +1) × 1 / 32 × 8-ms period

00000b = 1 / 32 × 8 ms (LEDC_ON is high for 250 µs, low for 7.75

ms)

11111b = 32 / 32 × 8 ms (LEDC_ON is always high)

8.5.1.3.62 LEDC_CTRL8 Register (Offset = 5Eh) [reset = 00h]

LEDC_CTRL8 is shown in Table 8-210 and described in Table 8-211.

Return to Summary Table.

Register is reset on a POR event.

Table 8-210. LEDC_CTRL8 Register

7

6

5

4

3

2

1

0

RSVD

R-000b

LEDC_ON_TIME[4:0]

R/W-00000b

Table 8-211. LEDC_CTRL8 Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RSVD

R

000b

Unused bit read returns 0b.

LEDC_ON_TIME[4:0]

R/W

00000b

LEDC ON-TIME: LEDC_ON_TME[4:0] × 64 ms

00000b = 0 × 64 ms

11111b = 31 × 64 ms

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8.5.1.3.63 LED_RAMP_UP_TIME Register (Offset = 5Fh) [reset = 00h]

LED_RAMP_UP_TIME is shown in Table 8-212 and described in Table 8-213.

Return to Summary Table.

Register is reset on a POR event.

Table 8-212. LED_RAMP_UP_TIME Register

7

6

5

4

3

2

1

0

RSVD

R-000b

LED_RAMP_UP[4:0]

R/W-00000b

Table 8-213. LED_RAMP_UP_TIME Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RSVD

R

000b

Unused bit read returns 0b.

LED_RAMP_UP[4:0]

R/W

00000b

LED ramp up time for LEDA, LEDB and LEDC: LED_RAMP_UP[4:0]

× 8 ms

00000b = 0 × 8 ms

11111b = 31 × 8 ms

8.5.1.3.64 LED_RAMP_DOWN_TIME Register (Offset = 60h) [reset = 00h]

LED_RAMP_DOWN_TIME is shown in Table 8-214 and described in Table 8-215.

Return to Summary Table.

Register is reset on a POR event.

Table 8-214. LED_RAMP_DOWN_TIME Register

7

6

5

4

3

2

1

0

RSVD

R-000b

LED_RAMP_DOWN[4:0]

R/W-00000b

Table 8-215. LED_RAMP_DOWN_TIME Register Field Descriptions

Bit

Field

Type

Reset

Description

7-5

4-0

RSVD

R

000b

Unused bit read returns 0b.

LED_RAMP_DOWN[4:0] R/W

00000b

LED ramp-down time for LEDA, LEDB and LEDC:

LED_RAMP_DOWN[4:0] × 8 ms

00000b = 0 × 8 ms

11111b = 31 × 8 ms

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8.5.1.3.65 LED_SEQ_EN Register (Offset = 61h) [reset = 00h]

LED_SEQ_EN is shown in Table 8-216 and described in Table 8-217.

Return to Summary Table.

Register is reset on a POR event.

Table 8-216. LED_SEQ_EN Register

7

6

5

4

3

2

1

0

LEDC_SEQ_E

N

RSVD

R-0b

LEDA_EN

R/W-0b

LEDB_EN

R/W-0b

LEDC_EN

R/W-0b

RSVD

R-0b

LEDA_SEQ_EN LEDB_SEQ_EN

R/W-0b R/W-0b

R/W-0b

Table 8-217. LED_SEQ_EN Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RSVD

R

0b

Unused bit read returns 0b.

6

5

4

LEDA_EN

LEDB_EN

LEDC_EN

R/W

0b

0b = LEDA is disabled

1b = LEDA is enabled

0b = LEDB is disabled

1b = LEDB is enabled

0b = LEDC is disabled

1b = LEDC is enabled

3

2

RSVD

R

0b

Unused bit

LEDA_SEQ_EN

R/W

0b = LEDA sequencer is disabled

1b = LEDA sequencer is enabled

1

0

LEDB_SEQ_EN

LEDC_SEQ_EN

R/W

0b

0b = LEDB sequencer is disabled

1b = LEDB sequencer is enabled

0b = LEDC sequencer is disabled

1b = LEDC sequencer is enabled

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8.5.1.3.66 LEDx DC current

Table 8-218. LEDx DC current

LEDx_CURRENT[3:0]

LED CURRENT (mA)

0000b

2

0001b

0010b

4

6

0011b

8

0100b

10

12

14

16

18

20

0101b

0110b

0111b

1000b

1001b

1010b to 1111b

8.5.1.3.67 LOADSWITCH (Offset = 62h) [reset = OTP]

LOADSWITCH is shown in Table 8-219 and described in Table 8-220.

Return to Summary Table.

Register is reset on a POR event.

Table 8-219. LOADSWITCH Register

7

6

5

4

3

2

1

0

RSVD

ILIM[1:0]

ENABLE[1:0]

R/W-X

R-0000b

R/W-OTP

Table 8-220. LOADSWITCH Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3-2

RSVD

R

0000b

Unused bit read returns 0b.

ENABLE[1:0]

R/W

OTP

00b = Load switch is OFF

01b = Load switch is forced ON

10b = Load switch in bypass switch operation: It is automatically

enabled by comparators in DCDC4; forced PWM mode of DCDC4

is blocked and the bypass switch is disabled (ENABLE[1:0] is set to

00b) if the voltage on the VDCDC4 pin exceeds typically 4.18 V

11b = Load switch in bypass switch operation: Switch is forced ON;

forced PWM mode of DCDC4 is blocked and the bypass switch is

disabled (ENABLE[1:0] is set to 00b) if the voltage on the VDCDC4

pin exceeds typically 4.18 V

1-0

ILIM[1:0]

R/W

X

ENABLE[1] reset value is set by the EN_LS1 pin. ENABLE[0] reset

value is set by the EN_LS0 pin.

00b = Current limit is 100 mA maximum

01b = Current limit is 500 mA maximum

10b = Current limit is 750 mA ±10%

11b = Current limit is 2.5 A ±20%

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8.5.1.3.68 SPARE Register (Offset = 63h) [reset = OTP]

SPARE is shown in Table 8-221 and described in Table 8-222.

Return to Summary Table.

Register is reset on a POR event.

Table 8-221. SPARE Register

7

6

5

4

3

2

1

0

9MHZ OSC

OFF

DCDC4_

SEL DELAY

DCDC4_

IMMEDIATE

CLK32k_

OD_EN

SPARE[3:0]

R/W-OTP

Table 8-222. SPARE Register Field Descriptions

Bit

Field

Type

Reset

Description

7-4

3

SPARE[3:0]

R/W

OTP

Unused bit read returns 0b.

9 MHz OSC OFF

R/W

OTP

0b = 9-MHz oscillator enabled in ON state

1b = 9-MHz oscillator is disabled based on the PWR_REQ and

CLK_REQ1 pins as listed below:

PWR_REQ = 0b and CLK_REQ1 = 0b: oscillator OFF

PWR_REQ = 0b and CLK_REQ1 = 1b: oscillator ON

PWR_REQ = 1b and CLK_REQ1 = 0b: oscillator ON

PWR_REQ = 1b and CLK_REQ1 = 1b: oscillator ON

2

1

DCDC4_SEL DELAY

DCDC4_IMMEDIATE

R/W

OTP

0b = DELAY is (0.5 to 1.5) × (1 / 32 kHz) for a falling output voltage

1b = NO DELAY on the DCDC4_SELbit

0b = A voltage change in registers DCDC4_OP or DCDC4_AVS is

done with the slew rate defined in DCDC4_CTRL:TSTEP[2:0]

1b = A voltage change in registers DCDC4_OP or DCDC4_AVS is

done immediately without limiting it by the slew rate control

0

CLK32K_OD_EN

R/W

OTP

0b = 32KCLKOUT is configured as a push-pull output to VDDIO

1b = 32KCLKOUT is configured as an open drain output

8.5.1.3.69 VERNUM (Offset = 64h) [reset = OTP]

VERNUM is shown in Table 8-223 and described in Table 8-224.

Return to Summary Table.

Register is reset on a POR event.

Table 8-223. VERNUM Register

7

6

5

4

3

2

1

0

OTP_VERSION[7:4]

R-OTP

VERNUM[3:0]

R-OTP

Table 8-224. VERNUM Register Field Descriptions

Bit

7-4

Field

Type

Reset

Description

OTP_VERSION[7:4]

R

OTP

Value varies based on OTP.

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Table 8-224. VERNUM Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

3-0

VERNUM[3:0]

R

OTP

Value depending on silicon revision

00000000b = Revision 1.0

00000001b = Revision 1.1

00000010b = Revision 1.2

00000011b = Revision 1.3

00000100b = Revision 1.4

00000101b = Revision 1.5

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

The TPS659128x device is an integrated power-management integrated circuit (PMIC) that comes in an

81-pin, 0.4-mm pitch, DSBGA package. This device was designed for personal electronics, industrial, and

communication applications and is typically powered from a 5-V input supply. The device provides four step-

down converters along with an interface to control ten external LDO regulators. The device can support a variety

of different processors and applications. The step-down converters can also support dynamic voltage scaling

(DVS) through a dedicated I²C interface to provide optimum power savings. In addition to the power resources,

the device contains an embedded power controller (EPC) to manage the power sequencing requirements

of systems. The power sequencing is programmable through OTP memory. The device also contains five

configurable GPIOs and three LED drivers. The following sections provide the typical application use-case with

the recommended external components and layout guidelines.

9.2 Typical Application

The first item to evaluate is the use of the CONFIG1 and CONFIG2 pins. For more information on implementing

a device in a given system, refer to the application report for a specific orderable part number.

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Figure 9-1. Typical Application Schematic

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9.2.1 Design Requirements

For a typical application shown in Figure 9-1, Table 9-1 lists sample key design parameters of the power

resources. Voltages and currents will vary based on the application use case, the provided values are just an

example.

Table 9-1. Design Parameters

DESIGN PARAMETER

VALUE

2.7 V to 5.5 V

Up to 3.5 MHz

1.1 V

Supply voltage

Switching frequency

DCDC1 voltage

DCDC1 current

DCDC2 voltage

DCDC2 current

DCDC3 voltage

DCDC3 current

DCDC4 voltage

DCDC4 current

LDO1 voltage

LDO1 current

LDO2 voltage

LDO2 current

LDO3 voltage

LDO3 current

LDO4 voltage

LDO4 current

LDO5 voltage

LDO5 current

LDO6 voltage

LDO6 current

LDO7 voltage

LDO7 current

LDO8 voltage

LDO8 current

LDO9 voltage

LDO9 current

LDO10 voltage

LDO10 current

Up to 2.5 A

2.0 V

Up to 0.75 A

3.2 V

Up to 1.6 A

3.6 V

Up to 2.5 A

850 mV or 900 mV

Up to 100 mA

850 mV or 900 mV

Up to 100 mA

1.2 V

Up to 100 mA

1.7 V or 1.8 V

Up to 250 mA

2.7 V

Up to 250 mA

1.8 V or 3.0 V

Up to 100 mA

3.0 V

Up to 300 mA

3.1 V

Up to 100 mA

3.0 V

Up to 300 mA

1.8 V

Up to 300 mA

9.2.2 Detailed Design Procedure

Table 9-2 lists the recommended external components.

Table 9-2. Recommended External Components

REFERENCE

COMPONENTS

EIA SIZE

MASS

COMPONENT⁽¹⁾

MANUFACTURER

PART NUMBER

VALUE

SIZE (mm)

CODE⁽⁴⁾

PRODUCTION⁽²⁾

INPUT POWER SUPPLIES EXTERNAL COMPONENTS

GRM188R71A225

KE15

1.6 × 0.8 ×

0.8

C_VCC, C_{VINDCDC_ANA}Power input capacitors

C_VDDIOI/O input capacitor

Murata

2.2 µF, 10 V

4.7 µF, 6.3 V

0603

Available⁽³⁾

GRM188R60J475K

E19

1.6 × 0.8 ×

0.8

RGB LED EXTERNAL COMPONENTS

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Table 9-2. Recommended External Components (continued)

REFERENCE

COMPONENTS

EIA SIZE

MASS

COMPONENT⁽¹⁾

Yellow LED

Green LED

Red LED

MANUFACTURER

PART NUMBER

LTST-C190YKT

LTST-C190GKT

LTST-C190CKT

VALUE

SIZE (mm)

CODE⁽⁴⁾

PRODUCTION⁽²⁾

1.6 × 0.8 ×

0.8

LEDA

LEDB

LEDC

Lite On

20mA, 2.1 V

0603

Available ⁽³⁾

1.6 × 0.8 ×

0.8

Lite On

1.6 × 0.8 ×

0.8

Lite On

DCDC EXTERNAL COMPONENTS

C_IN1, C_IN2, C_IN3

C_IN4

,

GRM188R60J106

ME47

1.6 × 0.8 ×

0.8

Input capacitor

Murata

10 µF, 6.3 V

0603

Available ⁽³⁾

GCM32ER70J476

KE19 (Two

capacitors per rail)

C_OUTDCDC1

C_OUTDCDC4

,

1.6 × 0.8 ×

0.8

Output capacitor

C_OUTDCDC2

C_OUTDCDC3

GRM188R60J106

ME47

1.6 × 0.8 ×

0.8

Output capacitor

Inductor

Murata

Toko

10 µF, 6.3 V

1 µH

Available ⁽³⁾

Available⁽³⁾

1239AS-

H-1R0N=P2

L1, L2, L3, L4

2 × 2.5

LDO EXTERNAL COMPONENTS

C_INLDO1210, C_INLDO3

,

GRM188R71A225

KE15

1.6 × 0.8 ×

0.8

C_INLDO67, C_INLDO8

,

Input capacitor

Murata

2.2 µF, 10 V

4.7 µF, 6.3 V

0603

Available⁽³⁾

C_INLDO9

GRM188R60J475K

E19

1.6 × 0.8 ×

0.8

C_INLDO4, C_INLDO5

Input capacitor

C_OUTLDO3

C_OUTLDO1

C_OUTLDO2

C_OUTLDO6

C_OUTLDO7

C_OUTLDO8

C_OUTLDO9

,

GRM188R71A225

KE15

1.6 × 0.8 ×

0.8

Output capacitor

Murata

2.2 µF, 10 V

0603

Available⁽³⁾

C_OUTLDO10

,

C_OUTLDOAO

GRM188R60J475K

E19

1.6 × 0.8 ×

0.8

C_OUTLDO4, C_OUTLDO5Output capacitor

C_VREFOutput capacitor

Murata

4.7 µF, 6.3 V

220 nF, 6.3 V

0603

0201

Available⁽³⁾

Available

GRM033R60J224

ME15D

0.6 × 0.3 ×

0.33

(1) Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP.

(2) This column refers to the criteria.

(3) Component used on the validation boards.

(4) The PACK column describes the external component package type.

9.2.2.1 Output Filter Design (Inductor and Output Capacitor)

9.2.2.1.1 Inductor Selection

The step-down converters are designed to operate with small external components such as 1-μH output

inductors. The values given in the Recommended Operating Conditions (see Section 6.3) include tolerances

and saturation effects and must not be violated for stable operation. The selected inductor must be rated for its

DC resistance and saturation current. The DC resistance of the inductor will directly influence the efficiency of

the converter. Therefore an inductor with lowest DC resistance should be selected for highest efficiency.

Use Equation 3 to calculate the maximum inductor current under static load conditions. The saturation current

of the inductor should be rated higher than the maximum inductor current as calculated with Equation 3. This

recommendation is because during heavy load transients, the inductor current rises above the calculated value.

V_OUT

1-

V

IN

DI_L= V_OUT

where

ì

L ì f

(2)

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•

ΔI_Lis the peak-to-peak inductor ripple current.

L is the inductor value.

f is the switching frequency.

DI_L

2

I_Lmax= I_OUTmax

ì

(3)

where

I_Lmaxis the maximum inductor current.

The highest inductor current will occur at the maximum input voltage, V_IN.

•

Open-core inductors have a soft saturation characteristic and they can usually support higher inductor currents

versus a comparable shielded inductor.

A more conservative approach is to select the inductor-current rating just for the maximum switch current of

the corresponding converter. The core material from inductor to inductor differs and will have an impact on the

efficiency especially at high switching frequencies, and therefore the core material must be considered when

selecting an inductor.

For possible inductors, refer to Table 9-3 and Table 9-2.

Table 9-3. Tested Inductors

INDUCTOR TYPE

DFE252012

NOMINAL INDUCTANCE

SUPPLIER

Toko

1 μH

DFE322510

Toko

DFE322512

Toko

VLS201612ET-1R0

SPM3012T-1R0

TDK

9.2.2.1.2 Output Capacitor Selection

The control scheme of the DC-DC converters allow the use of small ceramic capacitors with a typical value as

given in the Recommended Operating Conditions (see Section 6.3), without having a large output voltage under

and overshoots during heavy load transients. Ceramic capacitors having low ESR values which result in the

lowest output voltage ripple and are therefore recommended.

If ceramic output capacitors are used, the RMS ripple-current rating of the capacitor (I_RMSCOUT) always meets

the application requirements. Use Equation 4 to calculat the RMS ripple current.

V_OUT

1-

V

1

IN

I_RMSCout= V_OUT

ì

L ì f

2 ì

3

(4)

At the nominal load current, the inductive converters operate in PWM mode and the overall output-voltage ripple

is the sum of the voltage spike caused by the ESR of the output capacitor plus the voltage ripple caused by

charging and discharging the output capacitor. Use Equation 5 to calculate the output-voltage ripple (ΔV_OUT).

V_OUT

1-

≈

∆

«

’

÷

◊

V

1

IN

DV_OUT= V_OUT

ì

+ ESR

L ì f

8 ì C_OUTì f

(5)

The highest output voltage ripple occurs at the highest input voltage, V_IN.

At light load currents, the converters operate in power save mode and the output-voltage ripple is dependent

on the value of the output capacitor. The output-voltage ripple is set by the internal comparator delay and the

external capacitor. The typical output-voltage ripple is less than 1% of the nominal output voltage.

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9.2.2.1.3 Input Capacitor Selection and Input Voltage

Because of the nature of the step-down converter having a pulsating input current, a low-ESR input capacitor

is required for best input voltage filtering and minimizing the interference with other circuits caused by high

input-voltage spikes. The converters require a ceramic input capacitor of 10 μF. The value of the input capacitor

can be increased without any limit for better input voltage filtering. Ceramic capacitors suffer from the so-called

DC bias effect. A DC voltage applied at a ceramic capacitor will change the effective capacitance to a value

lower than the nominal value. Curves about that behavior are available from the capacitor manufacturers and

must be considered when using the capacitors in applications where a DC voltage is applied and a minimum

capacitance must be maintained for proper functionality of the circuit. The values given in the Recommended

Operating Conditions for the TPS659128x device are for the capacitance; however, the actual capacitor used

may have a larger nominal value that drops with the voltage applied to what is recommended. The capacitance

drop depends on the voltage applied, therefore, higher voltages, such as the output voltage of a DC-DC

converter or LDO, must be considered when choosing a proper capacitor.

The input voltage for the step-down converters must be connected to the VINDCDC1, VINDCDC2, VINDCDC3,

and VINDCDC4 pins. These pins must be tied together with the VINDCDC_ANA pin to the power source. The

VCC pin must be tied to the highest voltage in the system. If the load switch is used as a switch on the output,

the VCC pin must be tied to the input voltage of the VINDCDCx and VINDCDC_ANA pins. If the load switch is

used as a current limited switch on the input, the VCC pin must be connected to the LSI pin while the LSO pin

is connected to the VINDCDCx and VINDCDC_ANA pins. The four step-down converters must not be supplied

from different input voltages.

9.2.2.1.4 Output Capacitor Table

The DC-DC converters are designed for an output capacitance as given in the Recommended Operating

Conditions (see Section 6.3). A ceramic capacitor, such as a X5R or X7R type, is required at the output. Table

9-4 lists capacitors used for the TPS659128x device.

Table 9-4. Example Capacitors

MATERIAL AND

VALUE

SIZE

SUPPLIER

RATING

47 µF / 6.3 V

22 µF / 6.3 V

10 µF / 10 V

4.7 µF / 6.3 V

0805

0603

0402

Murata GRM21BR60J476ME15

Murata GRM21BR60J226M

Ceramic X5R

Murata GRM188R61A106ME69

Murata GRM188R60J475KE19

Murata GRM155R60J475ME87

9.2.2.1.5 Voltage Change on DCDC1 to DCDC4

The output voltage of the DC-DC converters can be changed during operation by either the digital interfaces,

by toggling the DCDCx_SEL pin, or by entering SLEEP state if the resources are configured to change voltage

based on the device state.

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9.2.3 Application Curves

IOUT = 250 mA to 2250 mA

IOUT = 75 mA to 675 mA

VDCDC2 (Offset:VOUT)

VDCDC1 (Offset: VOUT)

V_IN= 3.6 V

V_O= 1.1375 V

V_IN= 3.6 V

V_O= 2.25 V

Figure 9-2. DCDC1 Load Transient Response

Figure 9-3. DCDC2 Load Transient Response

IOUT = 300 mA to 2700 mA

IOUT = 150 mA to 1350 mA

VDCDC4 (Offset: VOUT)

VDCDC3 (Offset: VOUT)

V_IN= 3.6 V

V_O= 1.1375 V

V_IN= 3.6 V

V_O= 1.1375 V

Figure 9-4. DCDC3 Load Transient Response

Figure 9-5. DCDC4 Load Transient Response

V_IN= 3.6 V to 5 V to 3.6 V

VDCDC2 (Offset: VOUT)

VDCDC1 (Offset: VOUT)

V_O= 1.8 V

I_O= 750 mA

V_O= 1.1375 V

I_O= 2500 mA

Figure 9-7. DCDC2 Line Transient Response

Figure 9-6. DCDC1 Line Transient Response

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V_IN= 3.6 V to 5 V to 3.6 V

VDCDC3 (Offset: VOUT)

VDCDC4 (Offset: VOUT)

V_O= 1.1375 V

I_O= 1500 mA

V_O= 1.1375 V

I_O= 3000 mA

Figure 9-8. DCDC3 Line Transient Response

Figure 9-9. DCDC4 Line Transient Response

I_O= 10 mA to 90 mA to 10 mA

VLDO (Offset: VOUT)

V_IN= 3.3 V

V_O= 3 V

V_IN= 1.8 V

V_O= 1.2 V

Figure 9-10. LDO1, LDO2, LDO3 Load Transient

Response

Figure 9-11. LDO1, LDO2, LDO3 Load Transient

Response

V_IN= 1.7 V to 3.6 V to 1.7 V

I_O= 20 mA to 180 mA to 20 mA

VLDO (Offset: VOUT)

I_O= 100 mA

V_O= 1.2 V

V_IN= 2 V

V_O= 1.7 V

Figure 9-12. LDO1, LDO2, LDO3 Line Transient

Response

Figure 9-13. LDO4, LDO5 Load Transient Response

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I_O= 20 mA to 180 mA to 20 mA

V_IN= 3.6 V to 5 V to 3.6 V

VLDO (Offset: VOUT)

I_O= 100 mA

V_O= 1.7 V

V_IN= 3.2 V

V_O= 2.7 V

Figure 9-15. LDO4, LDO5 Line Transient Response

Figure 9-14. LDO4, LDO5 Load Transient Response

I_O= 10 mA to 90 mA to 10 mA

V_IN= 3.6 V to 5 V to 3.6 V

VLDO (Offset: VOUT)

I_O= 100 mA

V_O= 3 V

V_IN= 3.3 V

V_O= 1.8 V

Figure 9-16. LDO4, LDO5 Line Transient Response Figure 9-17. LDO6, LDO8 Load Transient Response

I_O= 10 mA to 90 mA to 10 mA

V_IN= 3.6 V to 5 V to 3.6 V

VLDO (Offset: VOUT)

V_IN= 3.3 V

V_O= 2.85 V

I_O= 100 mA

V_O= 1.8 V

Figure 9-18. LDO6, LDO8 Load Transient Response

Figure 9-19. LDO6, LDO8 Line Transient Response

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I_O= 20 mA to 180 mA to 20 mA

V_IN= 3.6 V to 5 V to 3.6 V

VLDO (Offset: VOUT)

I_O= 100 mA

V_O= 2.85 V

V_IN= 3.2 V

V_O= 3 V

Figure 9-20. LDO6, LDO8 Line Transient Response

Figure 9-21. LDO7 Load Transient Response

I_O= 30 mA to 270 mA to 30 mA

VLDO (Offset: VOUT)

V_IN= 3.3 V

V_O= 2.85 V

V_IN= 3.3 V

V_O= 1.8 V

Figure 9-22. LDO9 Load Transient Response

Figure 9-23. LDO10 Load Transient Response

V_IN= 2.2 V to 3.6 V to 2.2 V

VLDO (Offset: VOUT)

I_O= 300 mA

V_O= 1.8 V

Figure 9-24. LDO10 Line Transient Response

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10 Layout

10.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. Proper functionality of the

device demands careful attention to PCB layout. Care must be taken in board layout to get the specified

performance. If the layout is not carefully done, the regulators may show poor line regulation, load regulation, or

both and stability issues, as well as EMI problems. Providing a low-impedance ground path is critical. Therefore,

use wide and short traces for the main current paths. The input capacitors must be placed as close as possible

to the device pins as well as the inductor and output capacitor.

Keep the common path to the GND pins, which returns the small signal components, and the high current of the

output capacitors as short as possible to avoid ground noise. The VDCDCx trace should be connected directly

to the output capacitor and routed away from noisy components and traces (for example, the L1, L2, L3, and L4

traces).

The most critical connections are:

•

PGNDx

VDCDCx (positive output-voltage sense connection)

VDCDCx_GND (ground-sense connection)

AGND

VINDCDCx, VINDCDC_ANA, VCC

The PGNDx pins are the ground connections of the power stages, so they will carry high DC-peak and AC-peak

currents. A low impedance connection to the GND plane is required, which must be independent from other pins

to not couple noise into other pins. Other pins must not be connected to PGNDx pins.

The VDCDCx pins are the positive-sense connections for the feedback loop. The connection must be made

directly to the positive terminal pad of the output capacitor. Do not tie the pin to the pad of the output inductor or

anywhere in between the inductor and capacitor. Shielding the connection by GND traces or a GND plane is a

best practice.

The VDCDCx_GND pin is a sense connection for GND and is only available for the DCDC1 and DCDC4

convertors. The connection can be made either to the GND pad of the output capacitor (preferred) or to the

GND plane directly if a solid connection of the GND-plane to the output capacitor exists. The pin must not be

connected to the PGNDx pins as this will couple switching noise into the feedback loop.

The AGND (analog ground) pin is the main GND connection for internal analog circuitry. A proper connection

must be made to a GND plane directly by a via. The AGND and DGND pins (located next to each other) can be

connected and a via each be used to the GND plane.

The VINDCDCx, VINDCDC_ANA, and VCC pins are supply-voltage-input terminals and must be properly

bypassed by their input capacitors. The required capacitance is given in the Recommended Operating

Conditions (see Section 6.3). As ceramic capacitors will change their capacitance based on the voltage applied,

temperature and age, the influence of these parameters must be considered when choosing the value of a

capacitor. The input capacitors are ideally placed on the same layer as the device, so the connection can be

made short and directly on the same layer with multiple vias used from the GND terminal to the GND-plane.

For more information about the layout for the TPS659128x device, refer to the TPS65912xEVM-081 User's

Guide.

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10.2 Layout Example

Figure 10-1. Layout Example

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11 Power Supply Recommendations

The TPS659128x device is designed to work with an analog supply voltage range from 2.7 V to 5.5 V. The input

supply should be well regulated and connected to the VCC pin, as well as the DCDC and LDO input pins. If

the input supply is located more than a few inches from the device, additional capacitance may be required in

addition to the recommended input capacitors at the VCC pin and the DCDC and LDO input pins.

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

TI offers an extensive line of development tools, including tools to evaluate the performance of the processors,

generate code, develop algorithm implementations, and fully integrate and debug software and hardware

modules. The tool's support documentation is electronically available within the Code Composer Studio^™

Integrated Development Environment (IDE).

The following products support development of the TPS659128x device applications:

Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE): including

Editor C/C++/Assembly Code Generation, and Debug plus additional development tools Scalable, Real-Time

Foundation Software ( DSP/BIOS^™), which provides the basic run-time target software needed to support any

TPS659128x device application.

Hardware Development Tools: Extended Development System ( XDS^™) Emulator

For a complete listing of development-support tools for the TPS659128x platform, visit the Texas Instruments

website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office or

authorized distributor.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation see the following:

•

Texas Instruments, Basic Calculation of a Buck Converter's Power Stage

Texas Instruments, Empowering Designs With Power Management IC (PMIC) for Processor Applications

application report

•

Texas Instruments, TPS65912xEVM-081 User's Guide

12.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on

Subscribe to updates to register and receive a weekly digest of any product information that has changed. For

change details, review the revision history included in any revised document.

12.4 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.5 Trademarks

Eco-mode^™, Code Composer Studio^™, DSP/BIOS^™, and XDS^™are trademarks of Texas Instruments.

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE MATERIALS INFORMATION

www.ti.com

13-Jun-2021

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS6591286YFFR

TPS6591287YFFR

DSBGA

YFF

81

3000

330.0

12.4

3.79

0.71

8.0

12.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

13-Jun-2021

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS6591286YFFR

TPS6591287YFFR

DSBGA

YFF

81

3000

335.0

25.0

Pack Materials-Page 2

D: Max = 3.684 mm, Min =3.624 mm

E: Max = 3.628 mm, Min =3.568 mm

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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

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TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS6591286
厂家：	TEXAS INSTRUMENTS
描述：	TPS659128 PMU for Processor Power
文件：	总165页 (文件大小：4580K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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