TPS65940400RWERQ1_技术文档

TPS6594-Q1

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SLVSEA7A – DECEMBER 2019 – REVISED APRIL 2021

TPS6594-Q1 Power Management IC (PMIC) with 5 Bucks and 4 LDOs for Safety-

Relevant Automotive Applications

– 0.6 V to 3.3 V Output Range with 50 mV Steps

1 Features

in Linear Regulation Mode

•

Qualified for Automotive Applications

AEC-Q100 Qualified with the Following Results:

– Device Operates from 3 V to 5.5 V Input Supply

– Device Temperature Grade 1: –40°C to +125°C

Ambient Operating Temperature Range

– Device HBM Classification Level 2

– Device CDM Classification Level C4A

SafeTI Semiconductor Component

– Designed for Functional Safety Applications

– Documentation Available to Aid ISO 26262

System Design up to ASIL D

– 1.7 V to 3.3 V Output Range in Bypass Mode

– 500 mA Capability With Short-Circuit and Over-

Current Protection

One Low-Dropout (LDO) Linear Regulator with

Low-Noise Performance

– 1.2 V to 3.3 V Output Range in 25 mV Steps

– 300 mA Capability With Short-Circuit and Over-

Current Protection

•

Power Sequence Control:

– Configurable Power-Up and Power-Down

Sequences between Power States (NVM)

– Digital Output Signals can be Included in the

Power Sequences

– Systematic Capability and Hardware Integrity

up to ASIL D

– Input Supply Monitor and Over-Voltage

Protection

– Digital Input Signals can be used to trigger

Power Seqence Transitions

– Windowed Voltage and Over-Current Monitors

– Integrated Q&A or Trigger Mode Watchdog

Module

– Dual Channel Level or PWM Error Signal

Monitoring (ESM) Supporting Processors with

Integrated Safety-MCU

•

32 kHz Crystal Oscillator with Option to Output a

Buffered 32-kHz Clock Output

Real-Time Clock (RTC) with Alarm and Periodic

Wake-Up Mechanism

One SPI or Two I²C Control Interfaces, with

Second I²C Interface Dedicated for Q&A Watchdog

Communication

– Thermal Monitoring With High Temperature

Warning and Thermal Shutdown

•

Package Option:

– NVM Bit-Integrity Error Detection With Options

to Proceed or Hold Power-Up Sequence and

Reset Release

– 8-mm × 8-mm 56-pin VQFNP With 0.5-mm

Pitch

2 Applications

•

Low-Power Consumption

– 2 μA Typical Shutdown Current

– 7 μA Typical in Back Up Supply Only Mode

– 20 μA Typical in Low Power Standby Mode

Five Step-Down Switched-Mode Power Supply

(BUCK) Regulators:

– 0.3 V to 3.34 V Output Range in 5, 10, or 20

mV Steps

– One with 4 A, Three with 3.5 A, and One with 2

A Capability

•

Automotive Infotainment and Digital Cluster

Automotive Advanced Driver Assistance System

(ADAS)

Automotive Navigation Systems

Automotive Telematics

•

Automotive Body Electronics & Lighting

3 Description

The TPS6594-Q1 device provides four flexible multi-

phase configurable step-down converters with 3.5 A

per phase, and one additional step-down converter

with 2 A capability.

– Four of the Bucks with Flexible Multi-Phase

Capability which can Source up to 14 A from

a Single Rail

– Short-Circuit Protection and Over-Current

Protection

– Internal Soft-Start for In-Rush Current

Limitation

Table 3-1. Device Information Table ⁽¹⁾

PART NUMBER

PACKAGE

BODY SIZE (NOM)

TPS6594-Q1

VQFNP (56)

8.00 mm × 8.00 mm

– 2.2 MHz / 4.4 MHz Switching Frequency

– Ability to Synchronize to External Clock Input

Three Low-Dropout (LDO) Linear Regulators With

Configurable Bypass Mode

(1) See the orderable addendum at the end of the data sheet for

all available packages.

•

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

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4 Functional Diagram

OVPGDRV

nINT

I²C and SPI

VSYS Monitor

VSYS_SENSE

128-kHz RC Oscillator

OSC32KCAP

OSC32KIN

nPWRON/ENABLE

Interrupt Handler

Real-Time Clock

(RTC) With Calendar

32-kHz Crystal Oscillator

VBACKUP

OSC32KOUT

Backup Supply

Management

VCCA

WAKEn

nSLEEPn

SYNCCLKOUT/CLK32KOUT

VOUT_LDOVRTC

LDO

RTC

Bandgap

VRTC

20-MHz Monitor Oscillator

20-MHz RC Oscillator

Clock Controller

& Monitor

Fixed

State Machine

(FFSM)

VDIG

LDO

INT

Bandgap

VINT

VOUT_LDOVINT

Trigger Mode or

Question and Answer

(Q&A) Watchdog

FSD

Clock

DPLL with

Dividers and

SSM

SYNCCLKIN

(GPIO10)

Pre-

Configurable

State

Machine

(PFSM)

Mux

VIN Monitor

GPIO3,7

Level or PWM Mode

Error Signal Monitors

OVP

UVLO

Bandgap

Single or Multiphase

BUCK1

PVIN_B1

SW_B1

FB_B1

Power-Good Monitor

for Buck and LDO

Regulators

Resource Controller

3.5 A

SRAM

Over-Current Monitor,

Short Circuit Monitor,

SW Short Monitor

PVIN_B5

Power Good

Controller & Monitor

VIN Monitor

OVP

Bandgap

UVLO

Registers

CRC

BUCK2

PVIN_B2

SW_B2

FB_B2

3.5 A

I2C/SPI/

GPIO/

SPMI

Thermal Monitor

LDO1, Bypass

Thermal

Controller

Over-Current Monitor,

Short Circuit Monitor,

SW Short Monitor

Register Map

VOUT_LDO1

PVIN_LDO12

Nonvolatile Memory

(NVM)

LBIST

ABIST

Over-Current Monitor,

Short Circuit Monitor

BUCK3

PVIN_B3

SW_B3

FB_B3

SPMI

I²C and SPI

CRC

3.5 A

LDO2, Bypass

Over-Current Monitor,

Short Circuit Monitor,

SW Short Monitor

BIST and CRC

Over-Current Monitor,

Short Circuit Monitor

VOUT_LDO2

Slave

Master

I2C1 I2C2

SPI

LDO3, Bypass

PVIN_LDO3

VOUT_LDO3

BUCK4

PVIN_B4

SW_B4

FB_B4

Over-Current Monitor,

Short Circuit Monitor

4 A (Single-Phase)

or 3.5 A

Over-Current Monitor,

Short Circuit Monitor,

SW Short Monitor

LDO4

(Low Noise)

Over-Current Monitor,

Short Circuit Monitor

PVIN_LDO4

VOUT_LDO4

BUCK5

PVIN_B5

SW_B5

FB_B5

2 A

GPIO Control

Over-Current Monitor,

Short Circuit Monitor,

SW Short Monitor

VIO_IN

Safety

Bandgap

AMUXOUT

nRST_OUT

EN_DRV

VCCA

Functional Diagram

2

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Table of Contents

1 Features............................................................................1

2 Applications.....................................................................1

3 Description.......................................................................1

4 Functional Diagram.........................................................2

5 Revision History.............................................................. 3

6 Description (continued).................................................. 4

7 Pin Configuration and Functions...................................5

7.1 Digital Signal Descriptions........................................ 10

8 Specifications................................................................ 17

8.1 Absolute Maximum Ratings ..................................... 17

8.2 ESD Ratings ............................................................ 18

8.3 Recommended Operating Conditions ......................18

8.4 Thermal Information .................................................19

8.5 General Purpose Low Drop-Out Regulators

(LDO1, LDO2, LDO3) .................................................20

8.6 Low Noise Low Drop-Out Regulator (LDO4) ........... 21

8.7 Internal Low Drop-Out Regulators (LDOVRTC,

LDOVINT) ...................................................................23

8.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5

Regulators ..................................................................23

8.9 Reference Generator (BandGap) .............................29

8.10 Monitoring Functions ..............................................30

8.11 Clocks, Oscillators, and PLL .................................. 32

8.12 Thermal Monitoring and Shutdown ........................34

8.13 System Control Thresholds ....................................34

8.14 Current Consumption .............................................35

8.15 Backup Battery Charger .........................................36

8.16 Digital Input Signal Parameters ............................. 37

8.17 Digital Output Signal Parameters ...........................38

8.18 I/O Pullup and Pulldown Resistance ......................39

8.19 I²C Interface ...........................................................39

8.20 Serial Peripheral Interface (SPI) ............................ 40

9 Typical Characteristics................................................. 41

10 Detailed Description....................................................45

10.1 Overview.................................................................45

10.2 Functional Block Diagram.......................................46

10.3 Feature Description.................................................47

10.4 Device Functional Modes......................................115

10.5 Control Interfaces..................................................144

10.6 Configurable Registers......................................... 150

10.7 Register Maps.......................................................152

11 Application and Implementation.............................. 351

11.1 Application Information..........................................351

11.2 Typical Application................................................ 351

11.3 Power Supply Recommendations.........................370

11.4 Layout................................................................... 370

12 Device and Documentation Support........................372

12.1 Third-Party Products Disclaimer........................... 372

12.2 Device Support..................................................... 372

12.3 Documentation Support........................................ 372

12.4 Receiving Notification of Documentation Updates372

12.5 Support Resources............................................... 372

12.6 Trademarks...........................................................372

12.7 Electrostatic Discharge Caution............................373

12.8 Glossary................................................................373

13 Mechanical, Packaging, and Orderable

Information.................................................................. 373

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (December 2019) to Revision A (April 2021)

Page

•

Updated the numbering format for tables, figures, and cross-references throughout the document .................1

Changed the status of the document from: advanced information to: publication data .....................................1

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6 Description (continued)

All of the bucks can be synchronized to an internal 2.2 MHz or 4.4 MHz or an external 1 MHz, 2 MHz, or 4 MHz

clock signal. An integrated spread-spectrum modulation can be added to the synchronized buck switching clock

signal to improve the device's EMC performance, which can also be made available to external devices through

a GPIO output pin. The device provides four LDOs: three with 500 mA capability, which can be configured as

load switches; one with 300 mA capability and low-noise performance.

Non-volatile memory (NVM) is used to control the default power sequences and default configurations, such

as output voltage and GPIO configurations. The NVM is pre-programmed to allow start-up without external

programming. Most static configurations can be changed from the default through SPI or I²C registers to

configure the device to meet many different system needs. As a safety feature, the NVM contains a bit-integrity-

error detection feature to stop the power-up sequence if an error is detected, preventing the system from starting

in an unknown state.

The TPS6594-Q1 includes a 32 kHz crystal oscillator, which generates an accurate 32 kHz clock for the

integrated RTC module. A backup-battery management provides power to the crystal oscillator and the RTC

module from a coin cell battery or a super-cap in the event of power loss from the main supply.

The TPS6594-Q1 device includes protection and diagnostic mechanisms such as register and interface CRC,

short-circuit protection, thermal monitoring, and shutdown. The device also includes a Q&A or trigger mode

watchdog to monitor for software lockup, and 2 system error monitoring inputs with fault injection options to

monitor the error signals from the attached SoC or MCU. The TPS6594-Q1 can notify the processor of these

events through the interrupt handler, allowing the processor to take action in response.

4

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7 Pin Configuration and Functions

Figure 7-1 shows the 56-pin RWE plastic quad-flatpack no-lead (VQFNP) pin assignments and thermal pad.

GPIO10

AMUXOUT

VOUT_LDOVINT

VOUT_LDOVRTC

VCCA

1

42

41

40

39

38

37

36

35

34

33

32

31

30

29

GPIO8

2

OSC32KCAP

OSC32KOUT

OSC32KIN

FB_B5

3

4

REFGND1

5

REFGND2

6

VBACKUP

PVIN_B5

VOUT_LDO4

PVIN_LDO4

VOUT_LDO3

PVIN_LDO3

VOUT_LDO2

PVIN_LDO12

VOUT_LDO1

nINT

7

Thermal

Pad

(GND)

8

SW_B5

9

GPIO2

10

11

12

13

14

GPIO1

SCL_I2C1/SCK_SPI

SDA_I2C1/SDI_SPI

EN_DRV

Not to scale

Figure 7-1. 56-Pin RWE (VQFNP) Package, 0.5-mm Pitch, With Thermal Pad (Top View)

Table 7-1. Pin Attributes

CONNECTION IF

NOT USED

I/O

DESCRIPTION

NAME

NO.

STEP-DOWN CONVERTERS (BUCKs)

Output voltage-sense (feedback) input for BUCK1 or differential voltage-

sense (feedback) positive input for BUCK12/123/1234 in multi-phase

configuration.

FB_B1

FB_B2

22

21

I

Ground

Output voltage-sense (feedback) input for BUCK2 or differential voltage-

sense (feedback) negative input for BUCK12/123/1234 in multi-phase

configuration.

Output voltage-sense (feedback) input for BUCK3 or differential voltage-

sense (feedback) positive input for BUCK34 in dual-phase configuration.

FB_B3

FB_B4

49

50

I

Ground

Output voltage-sense (feedback) input for BUCK4 or differential voltage-

sense (feedback) negative input for BUCK34 in dual-phase configuration.

FB_B5

37

26

17

45

54

I

Output voltage-sense (feedback) input for BUCK5

Power input for BUCK1

Ground

VCCA

PVIN_B1

PVIN_B2

PVIN_B3

PVIN_B4

Power input for BUCK2

Power input for BUCK3

Power input for BUCK4

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Table 7-1. Pin Attributes (continued)

CONNECTION IF

NOT USED

I/O

DESCRIPTION

NAME

NO.

35

27

28

15

16

43

44

55

56

34

PVIN_B5

SW_B1

SW_B2

SW_B3

SW_B4

SW_B5

I

Power input for BUCK5

Switch node of BUCK1

Switch node of BUCK2

Switch node of BUCK3

Switch node of BUCK4

Switch node of BUCK5

VCCA

O

Floating

LOW-DROPOUT REGULATORS

PVIN_LDO3

PVIN_LDO4

PVIN_LDO12

VOUT_LDO1

VOUT_LDO2

VOUT_LDO3

VOUT_LDO4

10

8

I

Power input voltage for LDO3 regulator

Power input voltage for LDO4 regulator

Power input voltage for LDO1 and LDO2 regulator

LDO1 output voltage

VCCA

I

12

13

11

9

I

VCCA

O

Floating

LDO2 output voltage

LDO3 output voltage

7

LDO4 output voltage

LOW-DROPOUT REGULATORS (INTERNAL)

LDOVINT output for connecting to the filtering capacitor. Not for external

loading.

VOUT_LDOVINT

2

3

O

—

LDOVRTC output for connecting to the filtering capacitor. Not for external

loading.

VOUT_LDOVRTC

CRYSTAL OSCILLATOR

OSC32KCAP

Filtering capacitor for the 32 KHz crystal Oscillator, connected to VRTC

through an internal 100 Ω resistor.

40

O

Floating

OSC32KIN

38

39

I

32-KHz crystal oscillator input

32-KHz crystal oscillator output

Ground

Floating

OSC32KOUT

SYSTEM CONTROL

AMUXOUT

O

1

O

Buffered bandgap output

Floating

Enable Drive output pin to indicate the device entering safe state (set low

when ENABLE_DRV bit is '0').

EN_DRV

29

Primary function: General-purpose input⁽¹⁾and output

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: SCL_I2C2, which is the Q&A WatchDog I²C serial

clock (external pull-up).

I

Ground

Floating

I

Alternative function: CS_SPI, which is the SPI chip enable signal.

GPIO1

32

Alternative function: nRSTOUT_SoC, which is the SoC reset or power on

output (Active Low).

O

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Ground

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

6

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Table 7-1. Pin Attributes (continued)

CONNECTION IF

NOT USED

I/O

DESCRIPTION

NO.

Primary function: General-purpose input⁽¹⁾and output

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: SDA_I2C2, which is the Q&A WatchDog I²C serial

bidirectional data (external pull-up).

I/O

Ground

Floating

Ground

O

I

Alternative function: SDO_SPI, which is the SPI output data signal.

GPIO2

33

Alternative function: TRIG_WDOG, which is the watchdog trigger input

signal for Watchdog Trigger mode.

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Ground

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

Primary function: General-purpose input⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: nERR_SoC, which is the system error count down

input signal from the SoC (Active Low).

I

Floating

Ground

Alternative function: CLK32KOUT, which is the output of the 32 KHz

crystal oscillator clock.

O

GPIO3

46

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of

processing a wake-up request for the device to go to higher power states

while the device is in LP STANDBY state. They can also be used as

I

Ground

regular WKUP1 or WKUP2 pins while the device is in mission states.

Primary function: General-purpose input⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: CLK32KOUT, which is the output of the 32 KHz

crystal oscillator clock.

O

Floating

Ground

GPIO4

47

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Alternative function: LP_WKUP1 or LP_WKUP2, which are capable of

processing a wake-up request for the device to go to higher power states

while the device is in LP STANDBY state. They can also be used as

I

Ground

regular WKUP1 or WKUP2 pins while the device is in mission states.

Primary function: General-purpose input⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: SCLK_SPMI, which is the Multi-PMIC SPMI serial

I/O interface clock signal. It's an output pin for the master SPMI device, and

an input pin for the slave SPMI device.

Floating

GPIO5

23

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Ground

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

I

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Table 7-1. Pin Attributes (continued)

CONNECTION IF

NOT USED

I/O

DESCRIPTION

NAME

NO.

Primary function: General-purpose input⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: SDATA_SPMI, which is the Multi-PMIC SPMI serial

interface bidirectional data signal.

I/O

Floating

Ground

GPIO6

24

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

I

Primary function: General-purpose input ⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: nERR_MCU, which is the system error count down

input signal from the MCU (Active Low).

I

Floating

Ground

GPIO7

18

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

I

Primary function: General-purpose input⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: SYNCCLKOUT, which is a clock output synchronized

to the switching clock signals for the bucks in the device.

O

Floating

Ground

Alternative function: DISABLE_WDOG, which is the input to disable the

watchdog monitoring function.

I

GPIO8

41

Alternative function: CLK32KOUT, which is the output of the 32 KHz

crystal oscillator clock.

O

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

I

Primary function: General-purpose input⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: PGOOD, which is the indication signal for valid

regulator output voltages and currents

O

Floating

Ground

Alternative function: SYNCCLKOUT, which is the internal fallback

switching clock for BUCK.

O

GPIO9

19

Alternative function: DISABLE_WDOG, which is the input to disable the

watchdog monitoring function.

I

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

I

8

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Table 7-1. Pin Attributes (continued)

CONNECTION IF

NOT USED

I/O

DESCRIPTION

NO.

Primary function: General-purpose input⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: SYNCCLKIN, which is the external switching clock

input for BUCK.

I

Floating

Ground

Alternative function: SYNCCLKOUT, which is the internal fallback

switching clock for BUCK.

O

GPIO10

42

Alternative function: CLK32KOUT, which is the output of the 32 KHz

crystal oscillator clock.

O

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

I

Primary function: General-purpose input⁽¹⁾and output.

I/O When configured as an output pin, it can be included as part of the power

sequencer output signal to enable an external regulator.

Input: Ground

Output: Floating

Alternative function: TRIG_WDOG, which is the watchdog trigger input

signal for Watchdog Trigger mode.

I

Ground

Floating

Ground

GPIO11

53

Alternative function: nRSTOUT_SoC, which is the SoC reset or power on

output (Active Low).

O

Alternative function: nSLEEP1 or nSLEEP2, which are the sleep request

signals for the device to go to lower power states (Active Low).

I

Alternative function: WKUP1 or WKUP2, which are the wake-up request

signals for the device to go to higher power states.

I

Ground

Floating

nINT

14

20

O

I

Maskable interrupt output request to the host processor (Active Low)

NPWRON_SEL = '0': ENABLE- Level sensitive input pin to power up the

device, with configurable polarity

nPWRON/ENABLE

NPWRON_SEL = '1': nPWRON - Active low edge sensitive button press

pin to power up the device

I

Ground

OVPGDRV

nRSTOUT

52

25

O

I

Gate drive output for input over voltage protection FET

Floating

Ground

MCU reset or power on reset output (Active Low)

If SPI is the default interface: SCL_I2C1 - I²C serial clock (external pullup)

If I²C is the default interface: CLK_SPI - SPI clock signal

SCL_I2C1/SCK_SPI

SDA_I2C1/SDI_SPI

31

30

I

If SPI is the default interface: SDA_I2C1 - I²C serial bidirectional data

(external pullup)

I/O

I

Ground

If I²C is the default interface: SDI_SPI - SPI input data signal

POWER SUPPLIES AND REFERENCE GROUNDS

Power Ground, which is also the thermal pad of the package. Connect to

PCB ground planes with multiple vias.

PGND/ThermalPad

—

REFGND1

REFGND2

VBACKUP

VCCA

5

6

—

System reference ground

—

System reference ground

36

4

I

Backup power source input pin

Ground

—

Analog input voltage for the internal LDOs and other internal blocks

Digital supply input for GPIOs and I/O supply voltage

Analog input sense pin

VIO_IN

48

51

—

VSYS_SENSE

Ground

(1) Default option before NVM settings are loaded into the device.

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8 Specifications

8.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted). Voltage level is with reference to the thermal/ground

pad of the device.⁽¹⁾

POS

MIN

–0.3

MAX UNIT

M1.1

Voltage on power supply sense pin

Voltage on overvoltage (OV) gate drive

Voltage on OV protected supply input pin

VSYS_SENSE

OVPGDRV⁽²⁾

VCCA⁽³⁾

12.5

6

V

M1.2

M1.3

Voltage on all buck supply voltage input

pins

M1.4

PVIN_Bx⁽³⁾

–0.3

–0.5

–0.3

6

V

Voltage difference between supply input

pins

M1.4a

M1.5a

Between VCCA and each PVIN_Bx

SW_Bx pins

0.5

PVIN_Bx + 0.3

V, up to 6 V

Voltage on all buck switch nodes

M1.5b

M1.6

M1.7

SW_Bx pins, 10-ns transient

FB_Bx

–2

–0.3

10

4

V

Voltage on all buck voltage sense nodes

Voltage on all LDO supply voltage input pins PVIN_LDOx⁽³⁾

6

PVIN_LDOx +

0.3 V, up to 6 V

M1.8

M1.9

M1.10

Voltage on all LDO output pins

Voltage on internal LDO output pins

Voltage on I/O supply pin

VOUT_LDOx

–0.3

V

VOUT_LDOVINT, VOUT_LDOVRTC

VIO_IN with respect to ground pad

2

VCCA + 0.3 V,

up to 6 V

Voltage on logic pins (input or output) in VIO I²C and SPI pins, nRSTOUT, and nINT pins, and all

M1.11

M1.12

M1.13

M1.14

M1.15

–0.3

6

V

domain

GPIO output buffers except GPO5 & GPO6

Voltage on logic pins (input or output) in

LDOVINT domain

GPO5 & GPO6, and all GPIO input buffers except

GPI3 & GPI4

Voltage on logic pins (input) in LDOVRTC

domain

GPI3 & GPI4

Voltage on logic pins (input or output) in

VCCA domain

nPWRON/ENABLE & EN_DRV

AMUXOUT

VCCA + 0.3 V,

up to 6 V

Voltage on analog mux output pin

M1.16

M1.17

M1.18

M2.1a

M2.1b

M2.2

Voltage on back-up power supply input

Voltage on crystal oscillator pins

Voltage on REFGND pins

VBACKUP

–0.3

6

2

V

OSC32KIN, OSC32KOUT, & OSC32KCAP

REFGND1 & REFGND2

0.3

VCCA, PVIN_Bx (voltage below 2.7 V)

VIO (only when VCCA < 2 V)

Between VSYS_SENSE & VCCA

All pins other than power resources

60 mV/µs

Voltage rise slew-rate on input supply pins

Current through input protection FET

15

20

A

M2.3a

mA

Buck1/2/3/4 regulators: PVIN_Bx and SW_Bx per

phase

M2.3b

Peak output current

5

A

M2.3c

M2.4a

Buck5 regulator: PVIN_B5 and SW_B5

GPIOx pins, source current

3

A

mA

GPIO1/2/5/6, SDA_I2C1/SDI_SPI, EN_DRV, nINT,

and nRSTOUT pins, sink current

M2.4b

8

mA

Average output current, 100 k hour, T_J=

M2.4c

M2.4d

M2.4e

M3

125℃

GPIO3/4/7/8/9/10/11 pins, sink current

LDO1/2/3 regulators

3

350

210

160

150

mA

°C

LDO4 regulators

Junction temperature, T_J

Storage temperature, T_stg

–45

–65

M4

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at conditions beyond those indicated under Recommended Operating

Conditions. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.

(2) The voltage at OVPGDRV can exceed the 12 V absolute max condition for a short period of time in the case of steep rising of the

voltage at the VSYS_SENSE pin, but must remain less than 14 V.

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(3) The voltage at VCCA and PVIN pins can exceed the 6 V absolute max condition for a short period of time, but must remain less than 8

V. VCCA at 8 V for a 100 ms duration is equivalent to approximately 8 hours of aging for the device at room temperature.

8.2 ESD Ratings

POS

M5

M6

VALUE

UNIT

Electrostatic

discharge

V_(ESD)

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

±2000

V

Electrostatic

discharge

±500

V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordancewith the ANSI/ESDA/JEDEC JS-001 specification.

8.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted). Voltage leve is in reference to the thermal/ground pad of

the device.

POS

MIN

VCCA_UV

0

NOM

MAX UNIT

R1.1

Voltage on power supply sense pin

Voltage on OV gate drive

VSYS_SENSE

OVPGDRV

5.5

12

V

R1.2

R1.3

Voltage on OV protected supply input pin

Voltage on all buck supply input pins

Voltage difference between supply input pins

Voltage on all buck switch nodes

VCCA

VCCA_UV

2.8

5.5

R1.4

PVIN_Bx

5.5

R1.4a

R1.5

Between VCCA and each PVIN_Bx

SW_Bx pins

–0.2

0.2

3.3

5.5

R1.6

Voltage on all buck voltage sense nodes⁽¹⁾

FB_Bx

0

1.2

2.2

0

V_{OUT_Bn,max}

VCCA

3.3

R1.7a

R1.7b

R1.8

PVIN_LDO12, PVIN_LDO3

PVIN_LDO4

3.3

Voltage on all LDO supply voltage input pins

Voltage on all LDO output pins⁽¹⁾

Voltage on internal LDO output pins

Voltage on reference ground pins

VOUT_LDOx

R1.9

VOUT_LDOVINT, VOUT_LDOVRTC

REFGNDx

1.65

–0.3

1.7

1.95

R1.10

R1.11

0.3

V_{VIO_IN}= 1.8 V

1.8

3.3

1.9

Voltage on I/O supply pin

V

VCCA, up to

3.465V

R1.12

R1.13

V_{VIO_IN}= 3.3 V

3.135

0

I²C and SPI pins, nRSTOUT & nRSTOUT_SoC

pins, GPIO1, GPIO2, GPIO7, GPIO8, GPIO9,

GPIO10, and GPIO11 pins

Voltage on logic pins (input or output) in VIO

domain

V_{VIO_IN}

V_{VIO_IN,max}

Full Battery, up

to 5.5V

R1.14

R1.15

R1.16

R1.17

R1.18

Voltage on backup supply pin

Voltage on crystal oscillator pins

VBACKUP

0

V

V_{OUT_LDOVRTC,}

OSC32KIN, OSC32KOUT, OSC32KCAP

With fail-safe⁽³⁾: GPIO3 & GPIO4

With fail-safe⁽³⁾: GPIO5 & GPIO6

nPWRON/ENABLE, EN_DRV

max

Voltage on logic pins (input or output) in

LDOVRTC domain

V_{OUT_LDOVRTC,}

1.8

max

Voltage on logic pins (input or output) in

LDOVINT domain

V_{OUT_LDOVINT,m}

ax

Voltage on logic pins (input or output) in VCCA

domain

V_VCCA

R1.19

R1.20

Operating free-air temperature⁽²⁾

Junction temperature, T_J

–40

25

125

150

°C

Operational

(1) The maximum output voltage of BUCK1 to BUCK5 and LDO1 to LDO4 can be reduced by an NVM setting to adopt the maximum

voltage to the requirements (or maximum ratings) of the load. This protects the processor from exceeding the maximum ratings of the

core voltage. The default value is defined in the nonvolatile memory (NVM) and can be updated by software through I2C/SPI interface

after device startup.

(2) Additional cooling strategies may be necessary to keep junction temperature at recommended limits.

(3) The input buffer of a fail-safe GPIO pin is isolated from its input signal. Therefore the input voltage to a fail-safe pin can be as high as

5.5 V.

18

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8.4 Thermal Information

TPS6594-Q1

THERMAL METRIC⁽¹⁾

RWE (VQFNP)

UNIT

56 PINS

21.5

9.5

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-board thermal resistance

6.2

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

0.1

ψ_JB

6.2

R_θJC(bot)

0.7

(1) For more information about traditional and new thermal metrics, see the Semiconductor and ICPackage Thermal Metrics application

report.

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8.5 General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad

of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

Connected from PVIN_LDOn to GND, Shared input

tank capacitance (depending on platform requirements)

1.1a

C_IN(LDOn)

Input filtering capacitance⁽¹⁾

1

2.2

µF

Output filtering effective

capacitance⁽²⁾

1.1b

1.1c

1.1d

1.2a

1.2b

C_OUT(LDOn)

Connected from VOUT_LDOn to GND

1 MHz ≤ f ≤ 10 MHz

LDO mode

4

20

µF

mΩ

µF

V

C_ESR(LDOn) Filtering capacitor ESR⁽³⁾

C_{OUT_TOTAL}(L Total capacitance at output

DOn)

20

(Local + POL)⁽⁵⁾

V_IN(LDOn)

LDO Input voltage

1.2

1.7

VCCA

V_{IN(LDOn)_bypas}LDO Input voltage in bypass

VCCA,

upto 3.6 V

Bypass mode

V

mode

s

LDO output voltage

V_OUT(LDOn)

1.3

LDO mode, with 50-mV steps

0.6

3.3

1%

V

configurable range

Total DC output voltage

accuracy, including voltage

LDO mode, V_IN(LDOn)- V_OUT(LDOn)> 300 mV,

V_OUT(LDOn)≥ 1V

1.4a

–1%

T_DCOV(LDOn)

references, DC load and

line regulations, process and

temperation variations

LDO mode, V_IN(LDOn)- V_OUT(LDOn)> 300 mV, V_OUT(LDOn)

< 1V

1.4b

–10

700

10

mV

1.6

1.7

I_OUT(LDOn)

Output current

V_IN(LDOn)min≤ V_IN(LDOn)≤ V_IN(LDOn)max

LDO mode and bypass mode

LDOn_BYPASS = 0

500

1800

1500

mA

I_SHORT(LDOn)

LDO current limitation

1.8a

I_{IN_RUSH(LDOn)}LDO inrush current

mA

LDOx_BYPASS = 1, with maximum 50-µF load

connected to VOUT_LDOn

1500

65

Pulldown discharge resistance Active only when converter is disabled. Also applies to

at LDO output bypass mode. LDOn_PLDN = '00'

1.11a R_DIS(LDOn)

1.11b R_DIS(LDOn)

1.11c R_DIS(LDOn)

1.11d R_DIS(LDOn)

1.12a

35

60

50

125

250

500

60

kΩ

Ω

Pulldown discharge resistance Active only when converter is disabled. Also applies to

at LDO output bypass mode. LDOn_PLDN = '01'

200

400

800

Pulldown discharge resistance Active only when converter is disabled. Also applies to

at LDO output bypass mode. LDOn_PLDN = '10'

120

240

Ω

Pulldown discharge resistance Active only when converter is disabled. Also applies to

at LDO output

Ω

bypass mode. LDOn_PLDN = '11'

f = 1 kHz, V_IN(LDOx)= 3.3 V, V_OUT= 2.8 V, I_OUT= 500

mA

f = 10 kHz, V_IN(LDOx)= 3.3 V, V_OUT= 2.8 V, I_OUT= 500

mA

1.12b

50

Power supply ripple rejection

from V_IN(LDOn)

PSRR_VIN(LDOn)

dB

f = 100 kHz, V_IN(LDOx)= 3.3 V, V_OUT= 2.8 V, I_OUT= 500

mA

1.12c

1.12d

1.13

35

f = 1 MHz, V_IN(LDOx)= 3.3 V, V_OUT= 2.8 V, I_OUT= 500

mA

24

For LDO1, LDO2, & LDO3, VCCA = V_IN(LDOn)= 3.3 V,

T_J= 25°C

I_Qoff(LDOn)

I_Qon(LDOn)

T_LDR(LDOn)

Quiescent current, off mode

2

µA

1.14a

1.14b

LDOn_BYPASS = 0, I_LOAD= 0 mA , T_J= 25°C

LDOn_BYPASS = 1, I_LOAD= 0 mA , T_J= 25°C

78

68

Quiescent current, on mode

Transient load regulation,

LDOn_BYPASS = 0, I_OUT= 20% to 80% of I_OUTmax, t_r=

t_f= 1 µs

1.15

1.16

25

-2

mV

(4)

ΔV_OUT

Transient regulation due to

Bypass Mode to Linear Mode

Transition

T_{BYPASS_to_LD}

V_IN(LDOn)= 3.3V, I_OUT=I_OUT(LDOn)max, LDOn_BYPASS bit

switches between 1 and 0

mV

O(LDOn)

100 Hz < f ≤ 100 kHz, V_IN= 3.3 V, V_OUT= 1.8 V, I_OUT

300 mA

=

1.17

1.18

1.19a

V_NOISE(LDOn)

RMS Noise

Ripple

250

µV_RMS

mV_PP

From the internal charge pump

5

3.1 V ≤ V_IN(LDOn)≤ 3.5 V, PVIN_LDOx ≤ VCCA, I_OUT

500 mA, LDOx_BYPASS = 1

=

200

R_BYPASS(LDOn)Bypass resistance

mΩ

1.7 V ≤ V_IN(LDOn)≤ 1.9 V, I_OUT= 500 mA,

LDOn_BYPASS = 1

1.19c

250

20

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8.5 General Purpose Low Drop-Out Regulators (LDO1, LDO2, LDO3) (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad

of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Threshold voltage for Short

Circuit and Residual Voltage

Detection

V_{TH_SC_RV(LDO}

1.20

LDOn_EN = 0 and LDOn_RV_SEL = 1

140

150

160

mV

n)

Timing Requirements

Time between enable of the LDOn to within OV/UV

monitor level

19.1

t_on(LDOn)

Turnon time

500

µs

VOUT from 0.3 V to 90% of LDOn_VSET.

LDOn_SLOW_RAMP = 0

19.2a

19.2b

25 mV/µs

t_ramp(LDOn)

Ramp up slew rate

VOUT from 0.3 V to 90% of LDOn_VSET.

LDOn_SLOW_RAMP = 1

3

35

44

mV/µs

µs

19.3a t_{delay_OC(LDOn)}Over-current detection delay

Detection singal delay when I_OUT> ILIM

t_{deglitch_OC(LDOn}Over-current detection signal

19.3b

Digital deglitch time for the over-current detection signal

38

µs

deglitch time

)

t_{latency_OC(LDOn}Over-current signal total

19.4

Total delay from I_out> ILIM to interrupt or PFSM trigger

79

µs

latency time

)

(1) Input capacitors must be placed as close as possible to the device pins.

(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of

the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of

regulators.

(3) Ceramic capacitors recommended

(4) Load transient voltage must be considered when selecting UV/OV threshold levels for the LDO output

(5) Additional capacitance, including local and POL, beyond the specifiied value can cause the LDO to become unstable

8.6 Low Noise Low Drop-Out Regulator (LDO4)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

Connected from PVIN_LDO4 to GND, Shared input

tank capacitance (depending on platform requirements)

2.1a

2.1b

2.1c

C_IN(LDO4)

Input filtering capacitance⁽¹⁾

Output filtering capacitance⁽²⁾

1

2.2

µF

C_OUT(LDO4)

C_ESR(LDO4)

Connected from VOUT_LDO4 to GND

1 MHz ≤ f ≤ 10 MHz

4

µF

Input and output capacitor

ESR⁽³⁾

20

mΩ

2.1d

2.1e

2.2

1 MHz ≤ f ≤ 10 MHz, fast ramp

1 MHz ≤ f ≤ 10 MHz, slow ramp

15

30

µF

V

C_{OUT_TOTAL}

Total capacitance at output

(Local + POL)⁽⁴⁾

(LDO4)

V_IN(LDO4)

LDO Input voltage

2.2

1.2

5.5

LDO output voltage

configurable range

2.3

V_OUT(LDO4)

with 25-mV steps

3.3

1%

V

Total DC output voltage

accuracy, including voltage

references, DC load and

line regulations, process and

temperature

2.5

T_DCOV(LDO4)

V_IN(LDO4)- V_OUT(LDO4)> 300 mV

–1%

400

2.7

2.8

2.9

I_OUT(LDO4)

Output current

V_IN(LDO4)min≤ V_IN(LDO4)≤ V_IN(LDO4)max

V_IN= 3.3V when LDO is enabled

300

900

650

mA

I_SHORT(LDO4)

LDO current limit

I_{IN_RUSH(LDO4)}LDO inrush current

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8.6 Low Noise Low Drop-Out Regulator (LDO4) (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

f = 1 kHz, V_IN(LDO4)= 3.3 V, V_OUT= 2.8 V, I_OUT= 300

mA

2.13a

70

f = 10 kHz, V_IN(LDO4)= 3.3 V, V_OUT= 2.8 V, I_OUT= 300

mA

2.13b

2.13c

2.13d

2.12a

2.12b

2.12c

2.12d

2.14

70

62

PSRR_(LDO4)

Power supply ripple rejection

dB

f = 100 kHz, V_IN(LDO4)= 3.3 V, V_OUT= 2.8 V, I_OUT= 300

mA

f = 1 MHz, V_IN(LDO4)= 3.3 V, V_OUT= 2.8 V, I_OUT= 300

mA

15

Active only when converter is disabled, LDO4_PLDN =

'00'

35

60

50

65

200

400

800

2

kΩ

Ω

Active only when converter is disabled, LDO4_PLDN =

'01'

125

250

500

Pulldown discharge resistance

at LDO output

R_DIS(LDO4)

Active only when converter is disabled, LDO4_PLDN =

'10'

120

240

Ω

Active only when converter is disabled, LDO4_PLDN=

'11'

Ω

For all LDO regulators, VCCA = V_IN(LDO4)= 3.8 V, T_J=

25℃

I_Qoff(LDO4)

Leakage current in off mode

Quiescent current

µA

I_LOAD= 0 mA ,LDO4 under valid operating condition_,T_J

= 25℃

2.15

I_Qon(LDO4)

40

µA

Transient load regulation,

ΔV_OUT

V_IN(LDO4)= 3.3V, V_OUT(LDO4)= 2.80V, I_OUT= 20% of

I_{OUT_MAX}to 80% of I_{OUT_MAX}in 1us, C_OUT(LDO4)= 2.2uF

2.16

T_LDR(LDO4)

T_LNR(LDO4)

V_NOISE(LDO4)

–25

-25

25

mV

µV_RMS

Transient line regulation,

ΔV_OUT/ V_OUT

On mode, not under dropout condition, V_INstep = 600

mV_PP, t_r= t_f= 10 µs

2.17

25

100 Hz < f ≤ 100 kHz, V_IN= 3.3 V, V_OUT= 1.8 V, I_OUT

300 mA

=

2.18

RMS Noise

15

Threshold voltage for Short

Circuit and Residual Voltage

Detection

V_{TH_SC_RV(LDO}

2.19

LDO4_EN = 0 and LDO4_RV_SEL = 1

140

150

160

mV

4)

Timing Requirements

19.11a t_START(LDO4)

19.12

Time from completion of enable command to output

voltage at 0.5 V

Start Time

150

350

2.3

µs

Measured from 0.5 V to 90% of

LDO4_VSET. LDO4_SLOW_RAMP = 0

a1

t_RAMP(LDO4)

Ramp Time

19.12

Measured from 0.5 V to 90% of

LDO4_VSET. LDO4_SLOW_RAMP = 1

ms

a2

19.12

b

VOUT from 0.5 V to 90% of LDO4_VSET.

LDO4_SLOW_RAMP = 0

27 mV/µs

t_{RAMP_SLEW(LD}

Ramp up slew rate

O4)

VOUT from 0.5 V to 90% of LDO4_VSET.

LDO4_SLOW_RAMP = 1

19.12c

3

35

44

79

mV/µs

µs

19.13

a

t_{delay_OC(LDO4)}Over-current detection delay

Detection singal delay when I_OUT> ILIM

19.13 t_{deglitch_OC(LDO4}Over-current detection signal

b

Digital deglitch time for the over-current detection signal

Total delay from I_out> ILIM to interrupt or PFSM trigger

38

µs

deglitch time

)

t_{latency_OC(LDO4}Over-current signal total

19.14

µs

latency time

)

(1) Input capacitors must be placed as close as possible to the device pins.

(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of

the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given dc voltage at the outputs of

regulators.

(3) Ceramic capacitors recommended

(4) Additional capacitance, including local and POL, beyond the specifiied value can cause the LDO to become unstable

22

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8.7 Internal Low Drop-Out Regulators (LDOVRTC, LDOVINT)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

C_{OUT(LDOinternal}

3.1

Output filtering capacitance⁽¹⁾

Connected from VOUT_LDOx to GND

1

2.2

4

µF

)

3.3a

3.3b

3.7a

3.7b

V_OUT(LDOVRTC)

LDOVRTC

1.8

V

LDO output voltage

V_OUT(LDOVINT)

LDOVINT

LDOVRTC, VCCA = 3.3 V, T_J= 25℃

LDOVINT, VCCA = 3.3 V, T_J= 25℃

2

I_{Qoff(LDOinternal)}Leakage current, off mode

I_{Qon(LDOinternal)}Quiescent current, on mode

µA

LDOVRTC under valid operating condition, I_LOAD= 0

mA

3.8a

3.8b

3.9

3

10

µA

Ω

LDOVINT under valid operating condition, I_LOAD= 0 mA

LDOx disabled

Pulldown discharge resistance

R_{DIS(LDOinterna;)}

60

125

190

at LDO output

(1) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of

the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of

regulators.

8.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad

of the device except for V_{OUT_Bn}in multiphase configurations, in which case, the voltage level is referenced to the negative

FB_Bn pin of the differential pair.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics - Output Voltage

4.1a

1-phase output

0.3

3.34

1.9

V

V_{VOUT_Bn}

Output voltage configurable range

4.1b

4.2a

4.2b

4.2c

4.2d

Multi-phase output

V

0.3 V ≤ V_{VOUT_Bn}< 0.6 V

0.6 V ≤ V_{VOUT_Bn}< 1.1 V

1.1 V ≤ V_{VOUT_Bn}< 1.66 V

1.66 V ≤ V_{VOUT_Bn}< 3.34 V

20

5

mV

V_{VOUT_Bn_Step}Output voltage configurable step size

V_{DROPOUT_Bn}Input and output voltage difference

10

20

Minimum voltage between PVIN_Bn and

VOUT_Bn to fulfill the electrical characteristics

4.4

0.7

V

4.5a

4.5b

4.5c

4.5d

4.5e

4.5f

BUCKn_SLEW_RATE[2:0] = 000b

BUCKn_SLEW_RATE[2:0] = 001b

BUCKn_SLEW_RATE[2:0] = 010b

BUCKn_SLEW_RATE[2:0] = 011b

BUCKn_SLEW_RATE[2:0] = 100b

BUCKn_SLEW_RATE[2:0] = 101b

BUCKn_SLEW_RATE[2:0] = 110b

BUCKn_SLEW_RATE[2:0] = 111b

26.6

17

33.3

20

36.6 mV/µs

22 mV/µs

9

10

11 mV/µs

4.5

5

5.5 mV/µs

2.75 mV/µs

1.38 mV/µs

0.69 mV/µs

0.344 mV/µs

Output voltage slew-rate configurable

V_{OUT_SR_Bn}

range^{(5) (8)}

2.25

1.12

0.56

2.5

1.25

0.625

4.5g

4.5h

0.281 0.3125

Electrical Characteristics - Output Current, Limits and Thresholds

4.7a

4.7b

4.7c

1-phase, BUCK5

1-phase, BUCK4

1-phase, BUCK1, BUCK2, BUCK3

2-phase

2

4

A

3.5

7

I_{OUT_Bn}

Output current^{(3) (4)}

4.7d

4.7e

4.7f

3-phase

10.5

14

4-phase

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8.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad

of the device except for V_{OUT_Bn}in multiphase configurations, in which case, the voltage level is referenced to the negative

FB_Bn pin of the differential pair.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Mismatch between phase current and average

phase current, 1A/phase < I_{OUT_Bn}≤ 2A / phase

4.8a

4.8b

20%

Current balancing for multi-phase

output

I_{OUT_MP_Bal}

Mismatch between phase current and average

phase current, I_{OUT_Bn}> 2 A / phase

10%

4.9a

4.9b

Forward current limit (peak during

each switching cycle) configurable

range

BUCK5

2.5

3.5

5.5

A

I_{LIM_FWD_PEAK}

_ Range

BUCK1, BUCK2, BUCK3, BUCK4

I_{LIM_FWD_PEAK}

4.10

Forward current limit step Size

1

A

_Step

I_{LIM_FWD}= 2.5 A or 3.5 A, 3.0 V ≤ V_{PVIN_Bn}≤ 5.5

V

4.11a

4.11b

4.11c

4.11d

4.12

-0.55

–15%

–10%

1.5

0.55

10%

2.8

I_{LIM_FWD}= 4.5 A, 3.0 V ≤ V_{PVIN_Bn}≤ 5.5 V V,

BUCK1, BUCK2, BUCK3, BUCK4

I_{LIM_FWD_PEAK}

Forward current limit accuracy

_Accuracy

I_{LIM_FWD}= 5.5 A, 3.0 V ≤ V_{PVIN_Bn}≤ 4.5 V,

BUCK1, BUCK2, BUCK3, BUCK4

I_{LIM_FWD}= 5.5 A, 4.5 V ≤ V_{PVIN_Bn}≤ 5.5 V,

BUCK1, BUCK2, BUCK3, BUCK4

Negative current limit (peak during

each switching cycle)

I_{LIM_NEG}

2

A

4.15a

4.15b

4.15c

4.16a

4.16b

4.16c

4.16d

4.16e

4.16f

From 1-phase to 2-phase

2.0

4.0

6.0

1.3

2.7

3.5

0.7

1.3

2.5

A

I_ADD

Phase adding level (multi-phase rails) From 2-phase to 3-phase

From 3-phase to 4-phase

From 2-phase to 1-phase

Phase shedding level (multi-phase

From 3-phase to 2-phase

rails)

I_SHED

From 4-phase to 3-phase

Hysteresis from 2-phase to 1-phase

Phase shedding hysteresis (multi-

phase rails)

I_{SHED_Hyst}

Hysteresis from 3-phase to 2-phase

Hysteresis from 4-phase to 3-phase

Electrical Characteristics - Current Consumption, On-Resistance, and Output Pulldown Resistance

4.17

I_off

Shutdown current, BUCKn disabled

Auto mode quiescent current

VCCA = V_{PVIN_Bn}= 3.3 V. T_J= 25°C

1

µA

I_{OUT_Bn}= 0 mA, not switching, first single phase

or master phase, T_J= 25°C

4.18a

80

I_{OUT_Bn}= 0 mA, not switching, secondary single

phase or master phase, T_J= 25°C

4.18b

I_{Q_AUTO}

60

µA

I_{OUT_Bn}= 0 mA, not switching, slave phase, T_J=

25°C

4.18c

4.19a

4.19b

4.20a

4.20b

30

55

52

41

30

µA

mΩ

I_{OUT_Bn}= 1 A, BUCK5

110

100

70

R_{DS(ON) HS FET}On-resistance, high-side FET

R_{DS(ON) LS FET}On-resistance, low-side FET

I_{OUT_Bn}= 1 A, BUCK1, BUCK2, BUCK3,

BUCK4

I_{OUT_Bn}= 1 A, BUCK5

I_{OUT_Bn}= 1 A, BUCK1, BUCK2, BUCK3,

BUCK4

55

Regulator disabled, per phase, BUCKn_PLDN =

1

4.21

4.22

R_{DIS_Bn}

R_{SW_SC}

Output pulldown discharge resistance

50

2

100

4.5

150

20

Ω

Short circuit detection resistance

threshold at the SW pin

Electrical Characteristics - 4.4 MHz V_OUTLess than 1.9 V, Multiphase or High C_OUTSingle Phase

4.31

4.32

4.33a

V_{PVIN_Bn}

V_{VOUT_Bn}

C_{IN_Bn}

Input voltage range

3.0

0.3

3

3.3

5.5

1.9

V

Output voltage configurable range

Input filtering capacitance⁽¹⁾

22

µF

C_OUT-

4.33b

Output capacitance, local⁽²⁾

Per phase

10

µF

Local(Buckn)

24

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8.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad

of the device except for V_{OUT_Bn}in multiphase configurations, in which case, the voltage level is referenced to the negative

FB_Bn pin of the differential pair.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Output capacitance, total (local and

POL)⁽²⁾

4.33c

C_{OUT-TOTAL_Bn}

Per phase

70

250

286

µF

4.34a

4.34b

4.35

Inductance

DCR

154

220

10

nH

mΩ

mA

mV

L_Bn

Power inductor

I_{Q_PWM}

PWM mode Quiescent current

Per phase, I_{OUT_Bn}= 0 mA

V_{VOUT_Bx}< 1 V, PWM mode

V_{VOUT_Bx}≥ 1 V, PWM mode

V_{VOUT_Bx}< 1 V, PFM mode

19

4.160a

4.160b

4.160c

–10

–1%

–20

10

1%

25

DC output voltage accuracy, includes

voltage reference, DC load and line

regulations and temperature

V_{OUT_DC_Bx}

mV

-1% - 10

mV

1% + 15

mV

4.160d

4.37a

V_{VOUT_Bx}≥ 1 V, PFM mode

0.3 V ≤ V_{VOUT_Bn}< 0.6 V, I_{OUT_Bn}= 1 mA to 400

mA / phase, t_r= t_f= 1 µs, PWM mode

10

15

mV

0.6 V ≤ V_{VOUT_Bn}< 1.5 V, I_{OUT_Bn}= 1 mA

to 1.75A / phase, t_r= t_f= 1 µs, PWM mode,

BUCK1, BUCK2, BUCK3, BUCK4

4.37ba

4.37bb

4.37ca

0.6 V ≤ V_{VOUT_Bn}< 1.5 V, I_{OUT_Bn}= 1 mA to 1

A / phase, t_r= t_f= 1 µs, PWM mode, BUCK5

T_{LDSR_MP}

Transient load step response⁽⁷⁾

15

1.5 V ≤ V_{VOUT_Bn}≤ 1.9 V, I_{OUT_Bn}= 1 mA to

1.75 A / phase, t_r= t_f= 1 µs, PWM mode,

BUCK1, BUCK2, BUCK3, BUCK4

1.2%

1.5 V ≤ V_{VOUT_Bn}≤ 1.9 V, I_{OUT_Bn}= 1 mA to 1

A / phase, t_r= t_f= 1 µs, PWM mode, BUCK5

4.37cb

4.38

1.0%

±5

V_{PVIN_Bn}stepping from 3 V to 3.5 V, t_r= t_f= 10

µs, I_{OUT_Bn}= I_OUT(max)

T_LNSR

Transient line response

Ripple voltage⁽⁷⁾

-20

20

mV

4.39a

4.39b

PWM mode, 1-phase

PFM mode

3

mV_PP

V_{OUT_Ripple}

15

25 mV_PP

Threshold voltage for Short Circuit

and Residual Voltage Detection

4.40

V_{TH_SC_RV(Bn)}

I_PWM-PFM

Bn_EN = 0 and BUCKn_RV_SEL = 1

140

150

400

500

100

160

mV

mA

PWM to PFM switch current

threshold⁽⁶⁾

4.102

4.101

4.103

Auto mode, V_{PVIN_Bn}= 3.3 V, V_{VOUT_Bn}= 1.0 V

PFM to PWM switch current

threshold⁽⁶⁾

I_PFM-PWM

PWM to PFM switch current

hysteresis

I_{PWM-PFM_HYST}

Electrical Characteristics - DDR VTT Termination, 2.2 MHz Single Phase Only

4.41

V_{PVIN_Bn}

I_{OUT_Bn_SINK}

V_{VOUT_Bn}

C_{IN_Bn}

Input voltage range

2.8

–1

0.5

3

3.3

5.5

0.7

V

A

4.42

Current sink

4.43

Output voltage programmable range

Input filtering capacitance⁽¹⁾

V

4.44a

4.44b

22

µF

C_{OUT-TOTAL_Bn}Output capacitance, local⁽²⁾

10

Output capacitance, total (local and

4.44c

C_{OUT-TOTAL_Bn}

35

65

µF

POL)⁽²⁾

4.45a

4.45b

4.46a

4.161a

Inductance

DCR

329

470

10

611

nH

mΩ

mA

mV

L_Bn

Power inductor

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bn}= 0 mA

19

DC output voltage accuracy, includes V_{VOUT_Bx}< 1 V, PWM mode

voltage reference, DC load and line

V_{VOUT_Bx}≥ 1 V, PWM mode

regulations and temperature

–10

10

V_{OUT_DC_Bx}

4.161b

4.48

–1%

1%

0.5 V ≤ V_{VOUT_Bn}≤ 0.7 V, I_{OUT_Bn}= -1 mA to

-1000 mA, t_r= t_f= 1 µs, PWM mode

T_{LDSR_MP}

Transient load step response⁽⁷⁾

15

mV

V_{PVIN_Bn}stepping from 3 V to 3.5 V, t_r= t_f= 10

µs, I_{OUT_Bn}= I_{OUT_Bn(max)}

4.49

4.50

T_LNSR

Transient line response

Ripple voltage⁽⁷⁾

-20

±5

3

20

5

mV

V_{OUT_Ripple}

PWM mode

mV_PP

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8.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad

of the device except for V_{OUT_Bn}in multiphase configurations, in which case, the voltage level is referenced to the negative

FB_Bn pin of the differential pair.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics - 4.4 MHz V_OUTLess than 1.9 V, Low C_OUT, Single Phase Only

4.51

V_{PVIN_Bn}

V_{VOUT_Bn}

C_{IN_Bn}

Input voltage range

3.0

0.3

3

3.3

5.5

1.9

V

4.52

Output voltage configurable range

Input filtering capacitance⁽¹⁾

4.53a

4.53b

22

µF

C_{OUT-Local_Bn}Output capacitance, local⁽²⁾

10

Output capacitance, total (local and

4.53c

C_{OUT-TOTAL_Bn}

25

100

286

µF

POL)⁽²⁾

4.54a

4.54b

Inductance

DCR

154

220

10

nH

L_Bn

Power inductor

mΩ

I_{OUT_Bn}= 0 mA, BUCK1, BUCK2, BUCK3,

BUCK4

4.55a

19

mA

I_{Q_PWM}

PWM mode Quiescent current

4.55b

I_{OUT_Bn}= 0 mA, BUCK5

mA

mV

4.162a

4.162b

4.162c

V_{VOUT_Bx}< 1 V, PWM mode

V_{VOUT_Bx}≥ 1 V, PWM mode

V_{VOUT_Bx}< 1 V, PFM mode

–10

–1%

–20

10

1%

35

DC output voltage accuracy, includes

voltage reference, DC load and line

regulations and temperature

V_{OUT_DC_Bx}

mV

-1% - 10

mV

1% + 25

mV

4.162d

4.57a

4.57b

4.57c

4.58

V_{VOUT_Bx}≥ 1 V, PFM mode

0.3 V ≤ V_{VOUT_Bn}< 0.6 V, I_{OUT_Bn}= 1 mA to 200

mA / phase, t_r= t_f= 1 µs, PWM mode

15

mV

0.6 V ≤ V_{VOUT_Bn}< 1.5 V, I_{OUT_Bn}= 1 mA to 1

A / phase, t_r= t_f= 1 µs, PWM mode

T_{LDSR_MP}

Transient load step response⁽⁷⁾

1.5 V ≤ V_{VOUT_Bn}≤ 1.9 V, I_{OUT_Bn}= 1 mA to 1

A / phase, t_r= t_f= 1 µs, PWM mode

1.5%

±5

V_{PVIN_Bn}stepping from 3 V to 3.5 V, t_r= t_f= 10

µs, I_{OUT_Bn}= I_{OUT_Bn(max)}

T_LNSR

Transient line response

Ripple voltage⁽⁷⁾

-20

20

8

mV

4.59a

4.59b

PWM mode

PFM mode

5

mV_PP

V_{OUT_Ripple}

15

50 mV_PP

mA

PFM to PWM switch current

threshold⁽⁶⁾

4.111

4.112

4.113

I_PFM-PWM

Auto mode, V_{PVIN_Bn}= 3.3 V, V_{VOUT_Bn}= 1.0 V

500

300

200

PWM to PFM switch current

threshold⁽⁶⁾

I_PWM-PFM

mA

PWM to PFM switch current

hysteresis

I_{PWM-PFM_HYST}

Electrical Characteristics - 4.4 MHz V_OUTGreater than 1.7 V, Single Phase Only

4.61

4.62

V_{PVIN_Bn}

Input voltage range

Output current

4.5

5

5.5

2.5

V

A

I_{OUT_Bn_4.4_HV}

OUT

4.63

V_{VOUT_Bn}

C_{IN_Bn}

Output voltage configurable range

Input filtering capacitance⁽¹⁾

1.7

3

3.34

V

4.64a

4.64b

22

µF

C_{OUT-Local_Bn}Output capacitance, local⁽²⁾

10

Output capacitance, total (local and

4.64c

C_{OUT-TOTAL_Bn}

50

150

611

µF

POL)⁽²⁾

4.65a

Inductance

329

470

10

nH

mΩ

mA

mV

L_Bn

Power inductor

4.65b

DCR

4.66a

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bn}= 0 mA

19

4.163a

4.163b

4.163c

V_{VOUT_Bx}< 1 V, PWM mode

V_{VOUT_Bx}≥ 1 V, PWM mode

V_{VOUT_Bx}< 1 V, PFM mode

–10

–1%

–20

10

1%

25

DC output voltage accuracy, includes

voltage reference, DC load and line

regulations and temperature

V_{OUT_DC_Bx}

mV

-1% - 10

mV

1% + 15

mV

4.163d

4.68

V_{VOUT_Bx}≥ 1 V, PFM mode

1.7 V ≤ V_{VOUT_Bn}≤ 3.34 V, I_{OUT_Bn}= 1 mA to 1

A/phase, t_r= t_f= 1 µs, PWM mode

T_{LDSR_SP}

Transient load step response⁽⁷⁾

1.5%

26

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8.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad

of the device except for V_{OUT_Bn}in multiphase configurations, in which case, the voltage level is referenced to the negative

FB_Bn pin of the differential pair.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

V_{PVIN_Bn}stepping from 4.7 V to 5.2 V, t_r= t_f= 10

µs, I_{OUT_Bn}= I_{OUT_Bn(max)}

4.69

T_LNSR

Transient line response

-20

±5

20

7

mV

4.70a

4.70b

PWM mode

PFM mode

3

mV_PP

V_{OUT_Ripple}

Ripple voltage⁽⁷⁾

15

25 mV_PP

mA

PFM to PWM switch current

threshold⁽⁶⁾

4.121

4.122

4.123

I_PFM-PWM

Auto mode, V_{PVIN_Bn}= 5 V, V_{VOUT_Bn}= 1.8 V

400

250

150

PWM to PFM switch current

threshold⁽⁶⁾

I_PWM-PFM

mA

PWM to PFM switch current

hysteresis

I_{PWM-PFM_HYST}

Electrical Characteristics - 2.2 MHz Full V_OUTRange and V_INGreater than 4.5 V, Single Phase Only

4.71

V_{PVIN_Bn}

V_{VOUT_Bn}

C_{IN_Bn}

Input voltage range

4.5

0.3

3

5

5.5

V

4.72

Output voltage configurable range

Input filtering capacitance⁽¹⁾

3.34

4.73a

4.73b

22

µF

C_{OUT-Local_Bn}Output capacitance, local⁽²⁾

10

Output capacitance, total (local and

4.73c

C_{OUT-TOTAL_Bn}

100

700

1000

1300

µF

POL)⁽²⁾

4.74a

4.74b

4.75

Inductance

1000

10

nH

mΩ

mA

mV

L_Bn

Power inductor

DCR

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bn}= 0 mA

13

4.164a

4.164b

4.164c

V_{VOUT_Bx}< 1 V, PWM mode

V_{VOUT_Bx}≥ 1 V, PWM mode

V_{VOUT_Bx}< 1 V, PFM mode

–10

–1%

–20

10

1%

25

DC output voltage accuracy, includes

voltage reference, DC load and line

regulations and temperature

V_{OUT_DC_Bx}

mV

-1% - 10

mV

1% + 15

mV

4.164d

4.77a

4.77b

4.77c

4.78

V_{VOUT_Bx}≥ 1 V, PFM mode

0.3 V ≤ V_{VOUT_Bn}< 0.6 V, I_{OUT_Bn}= 1 mA to 400

mA / phase, t_r= t_f= 1 µs, PWM mode

15

mV

0.6 V ≤ V_{VOUT_Bn}< 1.5 V, I_{OUT_Bn}= 1 mA to 2

A / phase, t_r= t_f= 1 µs, PWM mode

T_{LDSR_MP}

Transient load step response⁽⁷⁾

1.5 V ≤ V_{VOUT_Bn}≤ 3.34 V, I_{OUT_Bn}= 1 mA to 2

A / phase, t_r= t_f= 1 µs, PWM mode

1.5%

±5

V_{PVIN_Bn}stepping from 4.7 V to 5.2 V, t_r= t_f= 10

µs, I_{OUT_Bn}= I_{OUT_Bn(max)}

T_LNSR

Transient line response

Ripple voltage⁽⁷⁾

-20

20

5

mV

4.79a

4.79b

PWM mode

PFM mode

3

mV_PP

V_{OUT_Ripple}

15

25 mV_PP

mA

PFM to PWM switch current

threshold⁽⁶⁾

4.131

4.132

4.133

I_PFM-PWM

Auto mode, V_{PVIN_Bn}= 5 V, V_{VOUT_Bn}= 1.0V

400

170

230

PWM to PFM switch current

threshold⁽⁶⁾

I_PWM-PFM

mA

PWM to PFM switch current

hysteresis

I_{PWM-PFM_HYST}

Electrical Characteristics - 2.2 MHz V_OUTLess than 1.9 V Multiphase or Single Phase

4.81

V_{PVIN_Bn}

V_{VOUT_Bn}

C_{IN_Bn}

Input voltage range

3.0

0.3

3

3.3

5.5

1.9

V

4.82

Output voltage configurable range

Input filtering capacitance⁽¹⁾

4.83a

4.83b

22

µF

C_{OUT-Local_Bn}Output capacitance, local⁽²⁾

Per phase

10

Output capacitance, total (local and

4.83c

C_{OUT-TOTAL_Bn}

100

329

1000

611

µF

POL)⁽²⁾

4.84a

4.84b

4.85

Inductance

DCR

470

10

nH

mΩ

mA

L_Bn

Power inductor

I_{Q_PWM}

PWM mode Quiescent current

I_{OUT_Bn}= 0 mA

13

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8.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad

of the device except for V_{OUT_Bn}in multiphase configurations, in which case, the voltage level is referenced to the negative

FB_Bn pin of the differential pair.

POS

PARAMETER

TEST CONDITIONS

MIN

–10

–1%

–20

TYP

MAX UNIT

4.165a

V_{VOUT_Bx}< 1 V, PWM mode

10

1%

25

mV

4.165b

4.165c

V_{VOUT_Bx}≥ 1 V, PWM mode

V_{VOUT_Bx}< 1 V, PFM mode

DC output voltage accuracy, includes

voltage reference, DC load and line

regulations and temperature

V_{OUT_DC_Bx}

mV

-1% - 10

mV

1% + 15

mV

4.165d

4.87a

4.87b

4.87c

4.88

V_{VOUT_Bx}≥ 1 V, PFM mode

0.3 V ≤ V_{VOUT_Bn}< 0.6 V, I_{OUT_Bn}= 1 mA to 400

mA / phase, t_r= t_f= 1 µs, PWM mode

5

15

mV

0.6 V ≤ V_{VOUT_Bn}< 1.5 V, I_{OUT_Bn}= 1 mA to 2

A / phase, t_r= t_f= 1 µs, PWM mode

T_{LDSR_MP}

Transient load step response⁽⁷⁾

1.5 V ≤ V_{VOUT_Bn}≤ 1.9 V, I_{OUT_Bn}= 1 mA to 2

A / phase, t_r= t_f= 1 µs, PWM mode

1.0%

±5

V_{PVIN_Bn}stepping from 4.7 V to 5.2 V, t_r= t_f= 10

µs, I_{OUT_Bn}= I_{OUT_Bn(max)}

T_LNSR

Transient line response

Ripple voltage⁽⁷⁾

-20

20

5

mV

4.89a

4.89b

PWM mode, 1-phase

PFM mode

3

mV_PP

V_{OUT_Ripple}

15

25 mV_PP

mA

PFM to PWM switch current

threshold⁽⁶⁾

4.141

4.142

4.143

I_PFM-PWM

Auto mode, V_{PVIN_Bn}= 3.3 V, V_{VOUT_Bn}= 1.0V

500

400

100

PWM to PFM switch current

threshold⁽⁶⁾

I_PWM-PFM

mA

PWM to PFM switch current

hysteresis

I_{PWM-PFM_HYST}

Electrical Characteristics - 2.2 MHz Full V_OUTand Full V_INRange, Single Phase Only

4.91

V_{PVIN_Bn}

V_{VOUT_Bn}

C_{IN_Bn}

Input voltage range

2.8

0.3

3

3.3

5.5

V

4.92

Output voltage configurable range

Input filtering capacitance⁽¹⁾

3.34

4.93a

4.93b

22

µF

C_{OUT-Local_Bn}Output capacitance, local⁽²⁾

10

Output capacitance, total (local and

4.93c

C_{OUT-TOTAL_Bn}

100

700

500

µF

POL)⁽²⁾

4.94a

4.94b

Inductance

DCR

1000

10

1300

nH

L_Bn

Power inductor

mΩ

I_{OUT_Bn}= 0 mA, BUCK1, BUCK2, BUCK3,

BUCK4

4.95

I_{Q_PWM}

PWM mode Quiescent current

13

mA

mV

4.166a

4.166b

V_{VOUT_Bx}< 1 V, PWM mode

V_{VOUT_Bx}≥ 1 V, PWM mode

–10

10

–1%

1%

DC output voltage accuracy, includes

voltage reference, DC load and line

regulations and temperature

V_{OUT_DC_Bx}

-1% - 10

mV

1% + 15

mV

4.166d

4.166c

4.97a

V_{VOUT_Bx}≥ 1 V, PFM mode

V_{VOUT_Bx}< 1 V, PFM mode

–20

25

mV

0.3 V ≤ V_{VOUT_Bn}< 0.6 V, I_{OUT_Bn}= 1 mA to 400

mA / phase, t_r= t_f= 1 µs, PWM mode

35

17

0.6 V ≤ V_{VOUT_Bn}< 1.0 V, I_{OUT_Bn}= 1 mA to 2

A / phase, t_r= t_f= 1 µs, PWM mode

4.97b

4.97c

4.98

T_{LDSR_SP}

Transient load step response⁽⁷⁾

mV

1.0 V ≤ V_{VOUT_Bn}≤ 3.34 V, I_{OUT_Bn}= 1 mA to 2

A / phase, t_r= t_f= 1 µs, PWM mode

3.5%

±5

V_{PVIN_Bn}stepping from 3 V to 3.5 V, t_r= t_f= 10

µs, I_{OUT_Bn}= I_{OUT_Bn(max)}

T_LNSR

Transient line response

Ripple voltage⁽⁷⁾

-20

20

5

mV

4.99a

4.99b

PWM mode

PFM mode

3

mV_PP

V_{OUT_Ripple}

15

25 mV_PP

mA

PFM to PWM switch current

threshold⁽⁶⁾

4.151

4.152

4.153

I_PFM-PWM

Auto mode, V_{PVIN_Bn}= 3.3 V, V_{VOUT_Bn}= 1.0V

335

150

185

PWM to PFM switch current

threshold⁽⁶⁾

I_PWM-PFM

mA

PWM to PFM switch current

hysteresis

I_{PWM-PFM_HYST}

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8.8 BUCK1, BUCK2, BUCK3, BUCK4 and BUCK5 Regulators (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level are referenced to the thermal/ground pad

of the device except for V_{OUT_Bn}in multiphase configurations, in which case, the voltage level is referenced to the negative

FB_Bn pin of the differential pair.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Switching Characteristics

20.1a

20.1b

2.2 MHz setting, internal clock

2

4

2.2

4.4

2.2

4.4

2.2

4.4

2.2

2.4 MHz

4.8 MHz

2.64 MHz

5.3 MHz

2.64 MHz

5.3 MHz

MHz

4.4 MHz setting, internal clock

20.1d

2.2 MHz setting, internal clock, spread spectrum

4.4 MHz setting, internal clock, spread spectrum

2.2 MHz setting, synchronized to external clock

4.4 MHz setting, synchronized to external clock

0.6 V ≤ V_{VOUT_Bn}

1.76

3.5

1.76

3.5

Steady state switching frequency in

PWM mode (NVM configurable)

f_SW

20.1e

20.1f

20.1g

20.2a

Automatic maximum switching

frequency scaling in PWM mode

f_{SW_max}

20.2b

0.3 V ≤ V_{VOUT_Bn}< 0.6 V

MHz

Timing Requirements

From end of voltage ramp to within 15mV from

target V_{OUT_DC_Bx}

20.3

20.4

20.5a

t_{settle_Bn}

t_{startup_Bn}

t_{delay_OC}

Settling time after voltage scaling

Start-up delay

105

218

7

µs

From enable to start of output voltage rise

100

19

150

Peak current limit triggering during every

switching cycle

Over-current detection delay

Digital deglitch time for detected signal.

Time duration to filter out short positive

and negative pulses

Over-current detection signal deglitch

time

20.5b

20.6

t_{deglitch_OC}

23

30

µs

Over-current signal latency time from Total delay from over-current detection to

detection interrupt or PFSM trigger

t_{latency_OC}

(1) Input capacitors must be placed as close as possible to the device pins.

(2) When DC voltage is applied to a ceramic capacitor, the effective capacitance is reduced due to DC bias effect. The table above

therefore lists the minimum value as CAPACITANCE. In order to meet the minimum capacitance requirement, the nominal value of

the capacitor may have to be scaled accordingly to take the drop of capacitance into account for a given DC voltage at the outputs of

regulators.

(3) The maximum output current can be limited by the forward current limit. The maximum output current is also limited by the junction

temperature and maximum average current over lifetime. The power dissipation inside the die increases the junction temperature and

limits the maximum current depending on the length of the current pulse, efficiency, board and ambient temperature.

(4) Additional cooling strategies may be necessary to keep the device junction temperature at recommended limits with large output

current.

(5) SLEW_RATEx[2:0] register default comes from NVM memory, and can be re-configured by the MCU. Output capacitance, forward and

negative current limits and load current may limit the maximum and minimum slew rates.

(6) The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage, and

the inductor current level.

(7) Please refer to the applications section of the datasheet regarding the power delivery network (PDN) used for the transient load step

and output ripple test conditions. All ripple specs are defined across POL capacitor in the described PDN.

(8) The 33.3 mV/µs slew-rate setting is not recommended for L_Bx≥ 1 µH, as this may may trigger OV detection due to larger overshoot at

the buck output.

8.9 Reference Generator (BandGap)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

Capacitance between AMUXOUT pin and thernal/

ground pad

5.1

Max capacitance at AMUX pin

Output voltage

100

pF

V

5.2

Measured at the AMUXOUT pin

1.17

1.2

1.23

Timing Requirements

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8.9 Reference Generator (BandGap) (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

From AMUXOUT_EN=1 to the time bandgap voltage

settles

21.1

t_{SU_REF}

Start-up time

30

µs

8.10 Monitoring Functions

Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/

ground pad of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics: BUCK REGULATORS OUTPUT

7.1a

7.1b

7.1c

BUCKn_OV_THR = 0x0

2%

2.5%

3%

4%

5%

6%

7%

9%

20

3%

3.5%

4%

5%

6%

7%

8%

10%

30

4%

4.5%

5%

6%

7%

8%

9%

11%

40

BUCKn_OV_THR = 0x1

BUCKn_OV_THR = 0x2

BUCKn_OV_THR = 0x3

BUCKn_OV_THR = 0x4

BUCKn_OV_THR = 0x5

BUCKn_OV_THR = 0x6

BUCKn_OV_THR = 0x7

BUCKn_OV_THR = 0x0

BUCKn_OV_THR = 0x1

BUCKn_OV_THR = 0x2

BUCKn_OV_THR = 0x3

BUCKn_OV_THR = 0x4

BUCKn_OV_THR = 0x5

BUCKn_OV_THR = 0x6

BUCKn_OV_THR = 0x7

BUCKn_UV_THR = 0x0

BUCKn_UV_THR = 0x1

BUCKn_UV_THR = 0x2

BUCKn_UV_THR = 0x3

BUCKn_UV_THR = 0x4

BUCKn_UV_THR = 0x5

BUCKn_UV_THR = 0x6

BUCKn_UV_THR = 0x7

BUCKn_UV_THR = 0x0

BUCKn_UV_THR = 0x1

BUCKn_UV_THR = 0x2

BUCKn_UV_THR = 0x3

BUCKn_UV_THR = 0x4

BUCKn_UV_THR = 0x5

BUCKn_UV_THR = 0x6

BUCKn_UV_THR = 0x7

Overvoltage monitoring for buck

7.1d

V_{BUCK_OV_TH}

output, threshold accuracy,

V_{OUT_Bn}≥ 1 V⁽¹⁾

7.1e

7.1f

7.1g

7.1h

7.2a

7.2b

7.2c

7.2d

7.2e

7.2f

25

35

45

30

40

50

Overvoltage monitoring for buck

40

50

60

mV

70

V_{BUCK_OV_TH_mv}output, threshold accuracy,

V_{OUT_Bn}< 1 V⁽¹⁾

50

60

70

80

90

7.2g

7.2h

7.3a

7.3b

7.3c

7.3d

7.3e

7.3f

70

80

90

100

–3%

110

–2%

–4%

–4.5% –3.5% –2.5%

–5%

–6%

–7%

–8%

–9%

–4%

–5%

–6%

–7%

–8%

–3%

–4%

–5%

–6%

–7%

–9%

–20

–25

–30

–40

–50

–60

–70

–90

Undervoltage monitoring for

V_{BUCK_UV_TH}

buck output, threshold accuracy,

V_{OUT_Bn}≥ 1 V⁽¹⁾

7.3g

7.3h

7.4a

7.4b

7.4c

7.4d

7.4e

7.4f

–11% –10%

–40

–45

–50

–60

–70

–80

–90

–110

–30

–35

–40

–50

–60

–70

–80

–100

Undervoltage monitoring for

V_{BUCK_UV_TH_mv}buck output, threshold accuracy,

mV

V_{OUT_Bn}< 1 V⁽¹⁾

7.4g

7.4h

Electrical Characteristics: LDO REGULATOR OUTPUTS

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8.10 Monitoring Functions (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/

ground pad of the device.

POS

PARAMETER

TEST CONDITIONS

MIN

2%

2.5%

3%

4%

5%

6%

7%

9%

20

TYP

3%

3.5%

4%

5%

6%

7%

8%

10%

30

MAX UNIT

7.5a

LDOn_OV_THR = 0x0

4%

4.5%

5%

6%

7%

8%

9%

11%

40

7.5b

7.5c

7.5d

7.5e

7.5f

LDOn_OV_THR = 0x1

LDOn_OV_THR = 0x2

LDOn_OV_THR = 0x3

LDOn_OV_THR = 0x4

LDOn_OV_THR = 0x5

LDOn_OV_THR = 0x6

LDOn_OV_THR = 0x7

LDOn_OV_THR = 0x0

LDOn_OV_THR = 0x1

LDOn_OV_THR = 0x2

LDOn_OV_THR = 0x3

LDOn_OV_THR = 0x4

LDOn_OV_THR = 0x5

LDOn_OV_THR = 0x6

LDOn_OV_THR = 0x7

LDOn_UV_THR = 0x0

LDOn_UV_THR = 0x1

LDOn_UV_THR = 0x2

LDOn_UV_THR = 0x3

LDOn_UV_THR = 0x4

LDOn_UV_THR = 0x5

LDOn_UV_THR = 0x6

LDOn_UV_THR = 0x7

LDOn_UV_THR = 0x0

LDOn_UV_THR = 0x1

LDOn_UV_THR = 0x2

LDOn_UV_THR = 0x3

LDOn_UV_THR = 0x4

LDOn_UV_THR = 0x5

LDOn_UV_THR = 0x6

LDOn_UV_THR = 0x7

Overvoltage monitoring for LDO

output, threshold accuracy,

V_{OUT_LDOn}≥ 1 V⁽²⁾

V_{LDO_OV_TH}

7.5g

7.5h

7.6a

7.6b

7.6c

7.6d

7.6e

7.6f

25

35

45

30

40

50

Overvoltage monitoring for LDO

40

50

60

mV

70

V_{LDO_OV_TH_mv}output, threshold accuracy,

V_{OUT_LDOn}< 1 V⁽²⁾

50

60

70

80

90

7.6g

7.6h

7.7a

7.7b

7.7c

7.7d

7.7e

7.7f

70

80

90

100

–3%

110

–2%

–4%

–4.5% –3.5% –2.5%

–5%

–6%

–7%

–8%

–9%

–4%

–5%

–6%

–7%

–8%

–3%

–4%

–5%

–6%

–7%

–9%

–20

–25

–30

–40

–50

–60

–70

–90

Undervoltage monitoring for

V_{LDO_UV_TH}

LDO output, threshold accuracy,

V_{OUT_LDOn}≥ 1 V⁽²⁾

7.7g

7.7h

7.8a

7.8b

7.8c

7.8d

7.8e

7.8f

–11% –10%

–40

–45

–50

–60

–70

–80

–90

–110

–30

–35

–40

–50

–60

–70

–80

–100

Undervoltage monitoring for

V_{LDO_UV_TH_mv}LDO output, threshold accuracy,

mV

V_{OUT_LDOn}< 1 V⁽²⁾

7.8g

7.8h

Electrical Characteristics: VCCA INPUT

7.9a

7.9b

7.9c

7.9d

VCCA_OV_THR = 0x0

VCCA_OV_THR = 0x1

VCCA_OV_THR = 0x2

VCCA_OV_THR = 0x3

VCCA_OV_THR = 0x4

VCCA_OV_THR = 0x5

VCCA_OV_THR = 0x6

VCCA_OV_THR = 0x7

2%

2.5%

3%

3.5%

4%

4.5%

5%

4%

5%

6%

Overvoltage monitoring for VCCA

input, threshold accuracy⁽³⁾

VCCA_{OV_TH}

7.9e

7.9f

5%

6%

7%

6%

7%

8%

7.9g

7.9h

7%

8%

9%

10%

11%

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8.10 Monitoring Functions (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is measured with reference to the thermal/

ground pad of the device.

POS

7.10a

7.10b

7.10c

7.10d

7.10e

7.10f

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

VCCA_UV_THR = 0x0

-4%

-3%

-2%

VCCA_UV_THR = 0x1

VCCA_UV_THR = 0x2

VCCA_UV_THR = 0x3

VCCA_UV_THR = 0x4

VCCA_UV_THR = 0x5

VCCA_UV_THR = 0x6

VCCA_UV_THR = 0x7

-4.5% -3.5% -2.5%

-5%

-6%

-7%

-8%

-9%

-11%

-4%

-5%

-3%

-4%

-5%

-6%

-7%

-9%

Undervoltage monitoring for

VCCA_{UV_TH}

VCCA input, threshold accuracy⁽³⁾

-6%

-7%

7.10g

7.10h

-8%

-10%

Timing Requirements

26.30a t_{delay_OV_UV}

26.30b t_{delay_OV_UV}

26.31a t_{deglitch1_OV_UV}

BUCK and LDO OV/UV detection Detection delay with 5 mV (V_in< 1 V) or 0.5% (V_in≥ 1 V)

8

12

µs

delay

over/underdrive

VCCA OV/UV detection delay

Detection delay with 30 mV over/underdrive

VMON_DEGLITCH_SEL = 0: Digital deglitch time for

detected signal

3.4

18

3.8

20

4.2

VCCA, BUCK, and LDO OV/UV

signal deglitch time

VMON_DEGLITCH_SEL = 1: Digital deglitch time for

detected signal

26.31b t_{deglitch2_OV_UV}

22

13

µs

VMON_DEGLITCH_SEL = 0: Total delay from 5mV (V_in< 1

V) or 0.5% (V_in≥ 1 V) over/underdrive to interrupt or PFSM

trigger

26.32a t_{latency1_OV_UV}

BUCK and LDO OV/UV signal

latency time

VMON_DEGLITCH_SEL = 1: Total delay from 5mV (V_in< 1

V) or 0.5% (V_in≥ 1 V) over/underdrive to interrupt or PFSM

trigger

26.32b t_{latency2_OV_UV}

30

µs

t_{latency1_VCCA_OV}

VMON_DEGLITCH_SEL = 0: Total delay from 30 mV over/

underdrive to interrupt or PFSM trigger

26.32b

13

30

µs

_UV

VCCA OV/UV signal latency time

PGOOD signal degltich time

t_{latency2_VCCA_OV}

VMON_DEGLITCH_SEL = 1: Total delay from 30 mV over/

underdrive to interrupt or PFSM trigger

26.32b

_UV

t_{deglitch_PGOOD_ris}

26.33a

Internal logic signal transitions from invalid to valid⁽⁴⁾

Internal logic signal transitions from valid to invalid⁽⁴⁾

9.5

10.5

e

t_{deglitch_PGOOD_fal}

26.33b

0

l

(1) The default values of BUCKn_OV_THR & BUCKn_UV_THR registers come from the NVM memory, and can be re-configured by

software.

(2) The default values of LDOn_OV_THR & LDOn_UV_THR registers come from the NVM memory, and can be re-configured by software.

(3) The default values of VCCA_OV_THR & VCCA_UV_THR registers come from the NVM memory, and can be re-configured by

software.

(4) Interrupt status signal is input signal for PGOOD deglitch logic.

8.11 Clocks, Oscillators, and PLL

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics: CRYSTAL

6.1

6.2

6.4

Crystal frequency

32768

Hz

Crystal frequency tolerance

Crystal series resistance

Parameter of crystal, T_J= 25°C

–20

20 ppm

At fundamental frequency

90

kΩ

The power dissipated in the crystal during oscillator

operation

6.5

Oscillator drive power

0.1

1.4

0.5

μW

Corresponding to crystal frequency, including parasitic

capacitances

6.6

6.7

Crystal Load capacitance⁽¹⁾

Crystal shunt capacitance

6

12.5

2.6

pF

Parameter of crystal

ELectrical Characteristics: 32-kHz CRYSTAL OSCILLATOR EXTERNAL COMPONENTS

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8.11 Clocks, Oscillators, and PLL (continued)

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

6.7a

Load capacitance on

External Capacitors

0

13

pF

OSC32KIN and OSC32KOUT

(parallel mode, including

parasitic of PCB for external

capacitor)⁽²⁾

6.7b

Internal Capacitors

9.5

12

14.5

pF

Switching Characteristics: 32-kHz CRYSTAL OSCILLATOR CLOCK

Crystal Oscillator output

frequency

23.1

23.2

23.3

23.4

Typical with specified load capacitors

32768

50%

10

Hz

Crystal Oscillator Output duty

cycle

Parameter of crystal, T_J= 25°C

40%

60%

20

Crystal Oscillator rise and fall

time

10% to 90%, with 10 pF load capacitance

ns

From Oscillator enable to reaching ±1% of final output

frequency

Crystal Oscillator Settling time

200

ms

Switching Characteristics: 20-MHz and 128-kHz RC OSCILLATOR CLOCK

20 MHz RC Oscillator output

frequency

23.10

19

20

21 MHz

135 kHz

128 kHz RC Oscillator output

frequency

23.12

121

128

Switching Characteristics: DPLL, SYNCCLKIN, and SYNCCLKOUT

22.1a

22.1b

22.1c

22.2a

22.2b

22.2c

EXT_CLK_FREQ = 0x0

EXT_CLK_FREQ = 0x1

EXT_CLK_FREQ = 0x2

SS_DEPTH = 0x0

1.1

2.2

4.4

External input clock nominal

frequency

MHz

–18%

–12%

–10%

18%

12%

10%

External input clock required

accuracy from nominal

frequency

SS_DEPTH = 0x1

SS_DEPTH = 0x2

22.13

a

Logic low time for SYNCCLKIN

clock

40

ns

22.13

b

Logic high time for

SYNCCLKIN clock

External clock detection delay

for missing clock detection

22.3

22.4

22.5

1.8

20

µs

External clock input debounce

time for clock detection

Clock change delay (internal to

external)

From valid clock detection to use of external clock

600

22.7a

22.7b

22.7c

22.8

SYNCCLKOUT_FREQ_SEL = 0x1

SYNCCLKOUT_FREQ_SEL = 0x2

SYNCCLKOUT_FREQ_SEL = 0x3

Cycle-to-cycle

1.1

2.2

MHz

SYNCCLKOUT clock nominal

frequency

4.4

SYNCCLKOUT duty-cycle

40%

5

50%

60%

50

SYNCCLKOUT output buffer

external load

22.9

35

pF

22.11a

22.11b

Spread spectrum variation

for nominal switching

frequency

SS_DEPTH = 0x1

SS_DEPTH = 0x2

6.3%

8.4%

Timing Requirements: Clock Monitors

26.7a

Failure on 20MHz system clock

10

40

µs

Clock Monitor Failure signal

latency from occurance of error

t_{latency_CLKfail}

26.7b

26.8

26.9

Failure on 128KHz monitoring clock

Clock Monitor Drift signal

latency from detection

t_{latency_CLKdrift}

f_sysclk

115

µs

Internal system clock

19

20

21 MHz

20%

Threshold for internal system

clock frequency drift detection

26.10 CLKdrift_TH

-20%

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8.11 Clocks, Oscillators, and PLL (continued)

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Threshold for internal system

clock stuck at high or stuck at

low detection

26.11 CLKfail_TH

10 MHz

(1) Customer must use the XTAL_SEL bit to select the corresponding crystal based on its load capacitance.

(2) External capacitors must be used if cyrstal load capacitance > 6 pF.

8.12 Thermal Monitoring and Shutdown

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

8.1a

8.1b

8.2a

8.2b

T_{WARN_0}

TWARN_LEVEL = 0

120

130

135

130

140

145

140

150

155

°C

TWARN_INT thermal warning

threshold (no hysteresis)

T_{WARN_1}

TWARN_LEVEL = 1

TSD_ORD_LEVEL = 0

TSD_ORD_LEVEL = 1

T_{SD_orderly_0}

T_{SD_orderly_1}

TSD_ORD_INT thermal

shutdown rising threshold

T_{SD_orderly_hys_}

8.2c

8.2d

8.3a

8.3b

TSD_ORD_LEVEL = 0

TSD_ORD_LEVEL = 1

10

5

°C

0

TSD_ORD_INT thermal

shutdown hysteresis

T_{SD_orderly_hys_}

1

TSD_IMM_INT thermal

shutdown rising threshold

T_{SD_imm}

140

150

5

160

425

TSD_IMM_INT

thernal shutdown hysteresis

T_{SD_imm_hys}

Timing Requirements

TSD signal latency from

detection

26.6

t_{latancy_TSD}

µs

8.13 System Control Thresholds

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

VCCA UVLO/POR falling

threshold

9.1

9.2

V_{POR_Falling}

Measured on VCCA pin

2.7

2.75

2.8

3

V

VCCA UVLO/POR rising

threshold

V_{POR_Rising}

V_{POR_Hyst}

Measured on VCCA pin

9.3

VCCA UVLO/POR hysteresis

100

4.0

5.7

mV

V

9.5aa

9.5ab

Measured on VCCA pin. VCCA_PG_SET = 0b

Measured on VCCA pin. VCCA_PG_SET = 1b

3.9

5.6

4.1

5.8

V_{VCCA_OVP_Risi}

VCCA OVP rising threshold

ng

V

V_{VCCA_OVP_Hys}

9.5b

9.7

VCCA OVP hysteresis

50

5.9

mV

V

t

V_{VSYS_OVP_Risi}

VSYS OVP rising threshold

Measured on VSYS_SENSE pin, untrimmed

Measured on VSYS_SENSE pin, trimmed

5.6

5.8

6.2

6

ng

V_{VSYS_OVP_Risi}VSYS OVP rising threshold,

9.8

V

trimmed

ng_Trim

Output voltage at OVPGDRV

V_{OVPGDRV_OFF}pin when external FET is

switched off

Measured after OVPGDRV pin has reached steady

state voltage

9.9

0.4

V

Output voltage at OVPGDRV

V_{OVPGDRV_On}pin when external FET is

switched on

Measured after OVPGDRV pin has reached steady

state voltage

9.10

9.11

12

4

V

Gate capacitance of external

C_{iss_extFET}

External NMOS FET: V_DS= 12V, V_GS= 0V

nF

NMOS FET

34

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8.13 System Control Thresholds (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Over-voltage threshold level at

OVPGDRV pin when external

FET is switched on

V_{OVPGDRV_OV_}

9.12

12.5

140

V

TH

Active pull down resistance

R_{VCCA_OVP_PD}between VCCA and GND in

case of VSYS OVP detection

9.13

50

100

Ω

Measured at VSYS_SENSE pin as voltage rises from

0V to V_{POR_Rising}

9.14

9.15

9.16

V_{VSYS_SR}

Input slew rate of VSYS supply

30 mV/µs

60 mV/µs

Input slew rate of VCCA and

PVIN_x supplies

Measured at VCCA and PVIN_x pins as voltage rises

from 0V to V_{POR_Rising}

V_{VCCA_PVIN_SR}

V_{VIO_SR}

V_{VBACKUP_SR}

V_{VSYS_RC_TH}

Measured at VIO pin as voltage rises from 0V

to V_{POR_Rising}

Input slew rate of VIO supply

Input slew rate of VBACKUP

supply

9.17

9.18

9.19

Measured at VBACKUP pin

VSYS reset recovery threshold Measured on VSYS_SENSE pin

50

mV

V

V_{VSYS_UVLO}

VSYS UVLO recovery

Measured on VSYS_SENSE pin

threshold

2.4

0.3

30

2.7

Rising_TH

V_{OVP_FET_Short}VSYS OVP FET-fail short test

9.20

9.21

Measured on VCCA pin

0.42

60

V

threshold

_TH

V_{OVP_FET_Short}VSYS OVP FET fail-short test

mV

hysteresis

_Hyst

Timing Requirements

26.1 t_{VSYS_RC_TH}

Minimum time VSYS_SENSE stays below V_{VSYS_RC_TH}

before device recovers from VSYS power cycle

VSYS reset recovery time

5

ms

Total startup time for OVPDGRV to rise from 0V

to V_{VSYS_SENSE}, including OVP circuit startup, FET

fault detection, and OVPGDRV ramp time. 200 µF

capacitance at VCCA

Startup time for OVPGDRV

output

26.20 t_{VSYSOVP_INIT}

6

20

15

10

Voltage at VSYS_SENSE pin rises from 6 V to 8 V in

7 µs. Measured from the time VSYS_SENSE = 6 V to

the time OVPGDRV = VCCA

t_{latency_VSYSOV}OVPGDRV latency from VSYS

26.2

µs

OVP detection

P

VCCA_PG_SEL = 0b, Voltage at VSYS_SENSE pin

rises from 4 V to 8 V in 7 µs. Measured from the

time VCCA = V_{VCCA_OVP_Rising}to the time OVPGDRV

= VCCA

26.3a

t_{latency_VCCAOV}OVPGDRV latency from VCCA

OVP detection

P

VCCA_PG_SEL = 1b, Voltage at VSYS_SENSE pin

rises from 6 V to 8 V in 7 µs. Measured from the

time VCCA = V_{VCCA_OVP_Rising}to the time OVPGDRV =

VCCA

26.3b

10

µs

Measured time between V_VCCAfalling from 3.3 V to

2.7 V with ≤ 100mv/µs slope, to the detection of

VCCA_UVLO signal

t_{latency_VCCAUVL}VCCA_UVLO signal latency

26.4

26.5

10

12

µs

from detection

O

LDOVINT OVP and UVLO

t_{latency_VINT}

With 25-mV overdrive

signal latency from detection

26.14 t_ABISTrun

26.15 t_LBISTrun

Run time for ABIST

0.25

1.8

ms

Run time for LBIST

Device initialization time to

t_{INIT_NVM_ANAL}load default values for NVM

26.16

26.17

2

1

ms

registers, and start up analog

OG

circuits

Device initialization time for

t_{INIT_REF_CLK_L}

reference bandgaps, system

clock, and internal LDOs

DO

8.14 Current Consumption

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

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8.14 Current Consumption (continued)

Over operating free-air temperature range (unless otherwise noted).

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

From VBACKUP pin. PWRON/ENABLE deactivated.

Device powered by the backup battery source.

VSYS_SENSE = VCCA = 0V. VIO = 0V. VBACKUP

= 3.3V. Only 32-kHz crystal oscillator and RTC

counters are functioning. T_J= 25℃. VSYS_OVP

function deactivated.

Backup current consumption,

regulators disabled

10.2

I_{BACKUP_RTC}

7

10

24

µA

Combined current from VCCA and PVIN_x pins.

VSYS_SENSE is grounded. VCCA = PVIN_Bx

= PVIN_LDOx = 3.3 V. VIO = 0V. 32-kHz crystal

oscillator and RTC digital is functioning. GPI pins in

LDOVRTC domain are active. All monitors are off. T_J=

25℃. VSYS OVP function deactivated

Low Power Standby current

consumption, regulators

disabled

10.3a I_{LP_STANDBY}

11

26

Combined current from VSYS_SENSE, VCCA and

PVIN_x pins, with protection FET in place connecting

the VSYS_SENSE pin with VCCA pin. VSYS_SENSE

= VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V.

32-kHz crystal oscillator and RTC digital is functioning.

GPI pins in LDOVRTC domain are active. All Monitors

are off. T_J= 25℃. VSYS_OVP function activated

I_{LP_STANDBY_OV}Low Power Standby current

10.3b

34

µA

consumption, OVP activated

P

Combined current from VCCA, and PVIN_x.

VSYS_SENSE is grounded. VCCA = PVIN_Bx =

PVIN_LDOx = 3.3 V. VIO = 0V. T_J= 25℃.

10.5a I_STANDBY

Standby current consumption

50

66

62

83

µA

VCCA_VMON_EN=0. VSYS_OVP function deactivated

Combined current from VSYS_SENSE, VCCA and

PVIN_x pins, with protection FET in place connecting

Standby current consumption, the VSYS_SENSE pin with VCCA pin. VSYS_SENSE

10.5b I_{STANDBY_OVP}

OVP activated

= VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V.

T_J= 25℃. VCCA_VMON_EN=0. VSYS_OVP function

activated

Combined current from VSYS_SENSE, VCCA and

PVIN_x pins, with protection FET in place connecting

the VSYS_SENSE pin with VCCA pin. VSYS_SENSE

= VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V.

T_J= 25℃. VCCA_VMON_EN=1. VSYS_OVP function

activated

I_{STANDBY_OVP_}

10.5c

Standby current consumption

250

290

315

363

µA

VCCAmon

Combined current from VSYS_SENSE, VCCA and

PVIN_x pins, with protection FET in place connecting

the VSYS_SENSE pin with VCCA pin. VSYS_SENSE

= VCCA = PVIN_Bx = PVIN_LDOx = 3.3 V. VIO = 0V.

T_J= 25℃. One buck regulator enabled in PFS/PWM

mode, no load. Buck and VCCA OV/UV monitoring

enabled. VSYS_OVP function activated

10.6a I_{SLEEP_3V3}

Sleep current consumption

Combined current from VSYS_SENSE, VCCA and

PVIN_x pins, with protection FET in place connecting

the VSYS_SENSE pin with VCCA pin. VSYS_SENSE =

VCCA = PVIN_Bx = PVIN_LDOx = 5 V. VIO = 0V. T_J=

25℃. One buck regulator enabled in PFS/PWM mode,

no load. Buck and VCCA OV/UV monitoring enabled.

VSYS_OVP function activated

10.6b I_{SLEEP_5V}

300

375

µA

8.15 Backup Battery Charger

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

27.1a

VBACKUP = 1 V, BB_ICHR = 0x0

VBACKUP = 1 V, BB_ICHR = 0x1

BB_VEOC = 0x0

100

500

2.5

2.8

3

I_charge

Charging current

µA

27.1b

27.2a

27.2b

27.2c

27.2d

2.4

2.7

2.9

3.2

2.6

BB_VEOC = 0x1

2.9

V

V_EOC

End of charge voltage⁽¹⁾

BB_VEOC = 0x2

3.1

BB_VEOC = 0x3

3.3

3.4

36

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8.15 Backup Battery Charger (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

End of charge, charger

27.3

I_{q_CHGR}Quiescent current of backup battery charger

enabled, VCCA - VBACKUP > 200

mV. Measured from VCCA pin

5

9

µA

VCCA - VBACKUP > 200 mV. Charger

disabled. Device not in BACKUP state.

Tj < 125°C

27.4a

10

100

I_{q_CHGR_}

Off current of backup battery charger

nA

OFF

VCCA - VBACKUP > 200 mV. Charger

disabled. Device not in BACKUP state.

125°C < Tj < 150°C

27.4b

27.5

250

4

Additional capacitor added when

backup battery ESR > 20 Ω

C_BKUP

Backup battery capacitance with additional capacitor

Backup battery sereies resistance

1

2.2

µF

Ω

27.6a

27.6b

Without additional capacitor in parallel

With additional capacitor in parallel

20

R_{BKUP_E}

SR

1000

(1) End Of Charge Voltage measured when VCCA-VBACKUP > 200mV. When VCCA-VBACKUP is ≤ 200mV, the charger will remain fully

functional, although the EOC voltage measurement will not be based on final voltage, but on charger dropout.

8.16 Digital Input Signal Parameters

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics: nPWRON/ENABLE

11.1

11.2

11.3

V_IL(VCCA)

V_IH(VCCA)

Low-level input voltage

High-level input voltage

Hysteresis

-0.3

1.26

150

0

0.54

V

mV

Electrical Characteristics: I2C/SPI Pins and Input Signals through all GPIO pins

11.4

11.5

11.6

V_IL(DIG)

V_IH(DIG)

Low-level input voltage

High-level input voltage

Hysteresis

-0.3

1.26

150

0

0.54

V

mV

Timing Requirements: nPWRON/ENABLE

24.1a t_{LPK_TIME}

nPWRON Long Press Key time

nPWRON button deglitch time ENABLE_DEGLITCH_EN = 1

8

s

24.1b t_{degl_PWRON}

48

6

50

52

10

ms

ENABLE_EGLITCH_EN = 1, exclude when activated

24.2

t_{degl_ENABLE}

ENABLE signal deglitch time⁽¹⁾under LP_STANDBY state while the system clock is not

available

8

µs

Timing Requirements: GPIx, nSLEEPx, nERRx, and other digital input signals

24.3a

Time from valid GPIx assertion FAST_BOOT_BIST=0

until device wakes up from

10

5

ms

t_{WKUP_LP}

LP_STANDBY state to ACTIVE

24.3b

FAST_BOOT_BIST=1

or MCU ONLY states

GPIx and nSLEEPx signal

GPIOn_DEGLITCH_EN = 1

deglitch time

25.1a t_{degl_GPIx}

25.1b t_{degl_ESMx}

6

8

10

18

µs

nERRn signal deglitch time

GPIOn_DEGLITCH_EN = 1

12

15

Time from receiving nPWRON/

ENABLE trigger in STANDBY

state to nRSTOUT assertion

25.2a

5

ms

t_STARTUP

Time from a valid GPIx

assertion until device starts

power-up seqeunce from a low

power state

25.2b

LDOVINT = 1.8V

1.5

Time from nSLEEPx assertion

until device starts power-down

sequence to enter a low power

state

25.3

t_SLEEP

1.5

ms

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8.16 Digital Input Signal Parameters (continued)

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

input through LP_WKUP1 and LP_WKUP2 (GPIO3 or

GPIO4) pins while the device is in LP_STANDBY state

25.4a

40

ns

Minimum valid input pulse

width for the WKUP input

signals

t_{WK_PW_MIN}

input through WKUP1, WKUP2, LP_WKUP1 and

LP_WKUP2 pins while the device is in mission states

25.4b

200

24

ns

DISABLE_WDOG input signal

deglitch time

25.5a t_{WD_DIS}

25.5b t_{WD_pulse}

30

36

µs

TRIG_WDOG input signal

deglitch time

24

(1) ENABLE signal deglitch is not available when device is activated from the LP_STANDBY state while the deglitching clock is not

available.

8.17 Digital Output Signal Parameters

Over operating free-air temperature range (unless otherwise noted). Voltage level is in reference to the thermal/ground pad of

the device. VIO refers to the VIO_IN pin, VCCA refers to the VCCA pin.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics: SDA_I2C1, and Output Signals through GPO1 and GPO2 pins

Low-level output voltage, push-

pull and open-drain

12.11 V_{OL(VIO)_20mA}

12.12 V_OH(VIO)

I_OL= 20 mA

I_OH= 3 mA

0.4

V

High-level output voltage,

push-pull

VIO – 0.4

Electrical Characteristics: Output Signals through GPO3 and GPO4 pins

Low-level output voltage, push-

pull

12.13 V_OL(DIG)

12.14 V_OH(DIG)

I_OL= 3 mA

I_OH= 3 mA

V

High-level output voltage,

push-pull

1.4

Electrical Characteristics: Output Signals through GPO5 and GPO6 pins

Low-level output voltage, push-

pull

12.4

12.5

V_{OL(DIG)_20mA}

V_OH(DIG)

I_OL= 20 mA

I_OH= 3 mA

V

High-level output voltage,

push-pull

Electrical Characteristics: Output Signals through GPO7, GPO8, GPO9, GPO10, and GPO11 pins

Low-level output voltage, push-

pull and open-drain

12.1

12.2

12.3

V_OL(VIO)

V_OH(VIO)

I_OL= 3 mA

I_OH= 3 mA

0.4

V

High-level output voltage,

push-pull

VIO – 0.4

Supply for external pullup

resistor, open drain

VIO

Electrical Characteristics: EN_DRV, nINT, nRSTOUT

Low-level output voltage for

EN_DRV pin

12.6

12.7

V_{OL(EN_DRV)}

V_OL(nINT)

I_OL=20 mA

I_OL= 20 mA

0.4

V

Low-level output voltage for

nINT pin

Low-level output voltage

for nRSTOUT and

nRSTOUT_SoC pin

12.8

V_OL(nRSTOUT)

I_OL= 20 mA

0.4

9.6

V

Timing Requirements

Gating time for readback

monitor

12.10 t_{gate_readback}

Signal level change or GPIO selection (GPIOn_SEL)

8.8

µs

38

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8.18 I/O Pullup and Pulldown Resistance

Over operating free-air temperature range, VIO refers to the VIO_IN pin, VCCA refers the VCCA pin.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

Electrical Characteristics

13.1a nPWRON pullup resistance

nPWRON IO buffer internal pull up to VCCA supply

280

400

520

kΩ

ENABLE IO buffer internal pull up to VCCA supply and

pull down to ground

13.1b ENABLE pullup and pulldown resistance

13.2

13.3

IO signals pullup resistance

GPIO1 -11 pins configured as input with internal pullup

GPIO1 - 11 pins configured as inputs with internal

pulldown

IO signals pulldown resistance

nRSTOUT and nRSTOUT_SoC pullup

resistance

13.4

13.5

Internal pullup to VIO supply when output driven high

Internal pullup to VCCA supply when output driven high

8

10

12

kΩ

EN_DRV pullup resistance

8.19 I²C Interface

Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode

(400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V.

POS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Electrical Characteristics

Capacitive load for SDA

and SCL

14.1

C_B

400

pF

Timing Requirements

16.1a

16.1b

Standard mode

100

400

1

kHz

Fast mode

16.1c ƒ_SCL

16.1d

Serial clock frequency

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

3.4

1.7

MHz

16.1e

16.2a

4.7

1.3

0.5

160

320

4

16.2b

Fast mode

µs

ns

µs

ns

16.2c t_LOW

16.2d

SCL low time

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

16.2e

16.3a

16.3b

Fast mode

0.6

0.26

60

16.3c t_HIGH

16.3d

SCL high time

Data setup time

Data hold time

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

16.3e

120

250

100

50

16.4a

16.4b

Fast mode

t_SU;DAT

ns

16.4c

Fast mode+

16.4d

High-speed mode

Standard mode

10

16.5a

10

3450

900

16.5b

Fast mode

10

ns

16.5c t_HD;DAT

16.5d

Fast mode+

10

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

10

70

16.5e

10

150

16.6a

4.7

0.6

0.26

160

Setup time for a start

or a REPEATED START

condition

16.6b

t_SU;STA

16.6c

Fast mode

µs

ns

Fast mode+

16.6d

High-speed mode

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8.19 I²C Interface (continued)

Over operating free-air temperature range (unless otherwise noted). Device supports standard mode (100 kHz), fast mode

(400 kHz), and fast mode+ (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode (3.4 MHz) only when VIO is 1.8 V.

POS

16.7a

16.7b

16.7c

16.7d

16.8a

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Standard mode

4

Hold time for a start or

a REPEATED START

condition

Fast mode

0.6

0.26

160

4.7

1.3

0.5

4

µs

t_HD;STA

Fast mode+

High-speed mode

Standard mode

Fast mode

ns

Bus free time between

a STOP and START

condition

16.8b t_BUF

16.8c

µs

Fast mode+

16.9a

Standard mode

Fast mode

16.9b

0.6

0.26

160

µs

ns

Setup time for a STOP

condition

t_SU;STO

16.9c

Fast mode+

16.9d

High-speed mode

Standard mode

Fast mode

16.10a

16.10b

16.10c t_rDA

16.10d

16.10e

16.11a

1000

300

120

80

20

Rise time of SDA signal Fast mode+

High-speed mode, C_b= 100 pF

ns

10

20

High-speed mode, C_b= 400 pF

Standard mode

160

300

120

80

16.11b

Fast mode

6.5

10

16.11c t_fDA

16.11d

Fall time of SDA signal Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

Standard mode

16.11e

13

160

1000

300

120

40

16.12a

16.12b

16.12c t_rCL

16.12d

16.12e

16.13a

Fast mode

20

Rise time of SCL signal Fast mode+

ns

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

10

20

10

80

Rise time of SCL signal High-speed mode, C_b= 100 pF

after a repeated start

condition and after an

acknowledge bit

Standard mode

Fast mode

80

t_rCL1

16.13b

High-speed mode, C_b= 400 pF

20

160

16.14a

300

120

40

16.14b

6.5

10

16.14c t_fCL

16.14d

Fall time of SCL signal

Fast mode+

High-speed mode, C_b= 100 pF

High-speed mode, C_b= 400 pF

16.14e

20

80

Pulse width of spike

suppressed (SCL and

SDA spikes that are less

than the indicated width

are suppressed)

Standard mode, fast mode, and fast

mode+

16.15a

50

10

t_SP

ns

16.15b

High-speed mode

8.20 Serial Peripheral Interface (SPI)

These specifications are ensured by design, VIO = 1.8 V(unless otherwise noted).

POS

PARAMETERS

TEST CONDITIONS

MIN

NOM

MAX UNIT

Electrical Characteristics

15.1

Capacitive load on pin SDO

30

pF

Timing Requirements

17.1

17.2

17.3

1

2

3

Cycle time

200

150

ns

Enable lead time

Enable lag time

40

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These specifications are ensured by design, VIO = 1.8 V(unless otherwise noted).

POS

17.4

17.5

17.6

17.7

17.8

17.9

PARAMETERS

TEST CONDITIONS

MIN

60

15

4

NOM

MAX UNIT

4

5

6

7

8

9

Clock low time

ns

Clock high time

Data setup time

Data hold time

Output data valid after SCLK falling

New output data valid after SCLK falling

60

30

ns

17.1

0

10

11

Disable time

17.1

1

CS inactive time

100

ns

9 Typical Characteristics

65

60

55

260

VCCA_PG_SET = 3.3 V

VCCA_PG_SET = 5 V

255

250

245

240

235

230

225

50

45

40

35

30

25

20

15

10

5

LP STANDBY, no OVP

LP STANDBY

STANDBY

3

3.25 3.5 3.75

4

4.25 4.5 4.75

VCCA (V)

5

5.25 5.5

3

3.25 3.5 3.75

4

4.25 4.5 4.75

VCCA (V)

5

5.25 5.5

TA = 25°C

Figure 9-1. Quiescent Current vs Input Voltage

Figure 9-2. Standby Current with VCCA Monitor

1.5

4

1.3

3

2

1.1

SR = 33.3 V/ms

SR = 20 V/ms

0.9

SR = 10 V/ms

SR = 5 V/ms

SR = 2.5 V/ms

1

0

2.2 MHz, Adding

2.2 MHz, Shedding

4.4 MHz, Adding

4.4 MHz, Shedding

0.7

SR = 1.25 V/ms

SR = 0.625 V/ms

SR = 0.3125 V/ms

0.5

1

1.5

2

2.5

3

3.5 4

0

1

2

3

4

5

6

Time (ms)

I_{OUT_Bn}(A)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 0.6 V

to 1.4 V

TA = 25°C

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1.0 V

TA = 25°C

Figure 9-3. Buck Phase Adding and Shedding

Figure 9-4. Buck Ramp Up Slew Rate

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9 Typical Characteristics (continued)

1.5

1.2

1

SR = 33.3 V/ms

SR = 20 V/ms

SR = 10 V/ms

1.3

SR = 5 V/ms

0.8

0.6

0.4

0.2

0

SR = 2.5 V/ms

SR = 1.25 V/ms

SR = 0.625 V/ms

SR = 0.3125 V/ms

1.1

0.9

0.7

0.5

2.2MHz, 1-phase

2.2MHz, 2-phase

2.2MHz, 3-phase

2.2MHz, 4-phase

4.4MHz, 1-phase

4.4MHz, 2-phase

4.4MHz, 3-phase

4.4MHz, 4-phase

-0.2

0.5

1

1.5

2

2.5

3

3.5

4

0

0.05

0.1

0.15

0.2

Time (ms)

0.25

0.3

0.35

0.4

Time (ms)

V_{PVIN_Bn}= 3.3 Buck VSET = 1.4 V to

0.6 V

TA = 25°C

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V Slew Rate = 5 V/ms

V

Figure 9-6. Buck Start Up with no Load, Auto Mode

Figure 9-5. Buck Ramp Down Slew Rate

1.2

1

1.2

1

0.8

0.6

0.4

0.2

0

0.8

0.6

2.2MHz, 1-phase

0.4

0.2

0

2.2MHz, 2-phase

2.2MHz, 3-phase

2.2MHz, 4-phase

4.4MHz, 1-phase

4.4MHz, 2-phase

4.4MHz, 3-phase

4.4MHz, 4-phase

2.2MHz, 2-phase

2.2MHz, 3-phase

2.2MHz, 4-phase

4.4MHz, 1-phase

4.4MHz, 2-phase

4.4MHz, 3-phase

4.4MHz, 4-phase

-0.2

0

0.05

0.1

0.15

0.2

Time (ms)

0.25

0.3

0.35

0.4

0

0.05

0.1

0.15

0.2

Time (ms)

0.25

0.3

0.35

0.4

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V Slew Rate = 5 V/ms

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V Slew Rate = 5 V/ms

Figure 9-7. Buck Start Up with 1A Load, Auto Mode

Figure 9-8. Buck Shutdown with no Load, Auto Mode

1.2

1.6

1

1.4

1.2

1

0.8

0.6

2.2MHz, 1-phase

0.4

0.2

0

2.2MHz, 2-phase

2.2MHz, 3-phase

2.2MHz, 4-phase

4.4MHz, 1-phase

4.4MHz, 2-phase

4.4MHz, 3-phase

4.4MHz, 4-phase

0.8

No Load

with 1A load

-0.2

0.6

0

0.05

0.1

0.15

0.2

Time (ms)

0.25

0.3

0.35

0.4

0

5

10

15

20

25

30 35

Time (us)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V Slew Rate = 5 V/ms

V_{PVIN_Bn}= 3.3 V

Buck VSET = 0.6 V

to 1.4 V

Slew Rate = 33.3

V/ms

Figure 9-9. Buck Shutdown with 1A Load, Auto Mode

Figure 9-10. Buck Ramp Up with and without Load

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9 Typical Characteristics (continued)

1.5

3.5

3

No Load

with 1A load

3.3 V to 0.8 V

3.3 V to 1.8 V

5 V to 0.8 V

5 V to 1.8 V

5 V to 3.3 V

Bypass Mode

1.4

1.3

1.2

1.1

1

2.5

2

1.5

1

0.9

0.8

0.7

0.6

0.5

0

-0.5

0

10

20

30

40

50

60

70

80

90

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

Time (us)

Time (ms)

V_{PVIN_Bn}= 3.3 Buck VSET = 1.4 V to

0.6 V

Slew Rate = 33.3

V/ms

V_IN(LDOn)= 3.3 V or 5 V

TA = 25°C

V

Figure 9-12. GPLDO Start Up with LDOn_SLOW_RAMP = 0

Figure 9-11. Buck Ramp Down with and without Load

3.5

3.3 V to 0.8 V

3.3 V to 1.8 V

5 V to 0.8 V

5 V to 1.8 V

5 V to 3.3 V

Bypass Mode

3.3 V to 1.8 V

5 V to 0.8 V

5 V to 1.8 V

5 V to 3.3 V

3

2.5

2

3

2.5

2

Bypass Mode

1.5

1

1.5

1

0.5

0

0.5

0

-0.5

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

0

2

4

6

8

10

12

14

16

18

20

Time (ms)

V_IN(LDOn)= 3.3 V or 5 V

TA = 25°C

V_IN(LDOn)= 3.3 V or LDOn_PLDN = 500

5 V

TA = 25°C

Ω

Figure 9-13. GPLDO Start Up with LDOn_SLOW_RAMP = 1

Figure 9-14. GPLDO Shut Down

3.5

3

3.3 V to 0.8 V

3.3 V to 1.8 V

5 V to 0.8 V

5 V to 1.8 V

5 V to 3.3 V

3.3 V to 1.8 V

5 V to 0.8 V

5 V to 1.8 V

5 V to 3.3 V

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

-0.5

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

0

0.4 0.8 1.2 1.6

2

2.4 2.8 3.2 3.6

4

Time (ms)

V_IN(LDOn)= 3.3 V or 5 V

TA = 25°C

V_IN(LDOn)= 3.3 V or 5 V

TA = 25°C

Figure 9-15. LNLDO Start Up with LDOn_SLOW_RAMP = 0

Figure 9-16. LNLDO Start Up with LDOn_SLOW_RAMP = 1

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9 Typical Characteristics (continued)

3.5

3.3 V to 0.8 V

3.3 V to 1.8 V

5 V to 0.8 V

5 V to 1.8 V

5 V to 3.3 V

3

2.5

2

1.5

1

0.5

0

2

4

6

8

10

12

14

16

18

20

Time (ms)

V_IN(LDOn)= 3.3 V or 5 V

LDOn_PLDN = 500 Ω

TA = 25°C

Figure 9-17. LNLDO Shut Down

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10 Detailed Description

10.1 Overview

The TPS6594-Q1 device is a power-management integrated circuit (PMIC), available in a 56-pin, 0.5-mm pitch,

8-mm × 8-mm QFN package. It is designed for powering embedded systems or system on chip (SoC) in

automotive or industrial applications. It provides five configurable buck converter rails, with four of the rails

having the ability to combine outputs in multi-phase mode. BUCK4 has the ability to supply up to 4 A in

single-phase mode, while BUCK1, BUCK2, and BUCK3 have the ability to supply up to 3.5 A in single-phase

mode. When working in multi-phase mode, each BUCK1, BUCK2, BUCK3, and BUCK4 can supply up to 3.5 A

per phase, adding up to 14 A in four-phase configuration. BUCK5 is a single-phase only buck converter, which

supports up to 2 A current load. All five of the BUCK converters have the capability to sink up to 1 A, and support

dynamic voltage scaling. Double buffered voltage scaling registers enable each BUCK to transition to a different

voltage during operation by SPI or I²C. A DPLL enables the BUCK converters to synchronize to an external

clock input, with phase delays between the outputs rails.

The TPS6594-Q1 device also provides three LDO rails, which can supply up to 500 mA per rail and can be

configured in bypass mode and used as a load switch. One additional low-noise LDO rail can supply up to 300

mA. The 500 mA LDOs support 0.6 V to 3.3 V output with 50 mV step. The 300 mA low-noise LDO supports 1.2

V to 3.3 V output with 25 mV step. The output voltages of the LDOs can be pre-configured through the SPI or

I²C interfaces, which are used to configure the power rails and the power states of the TPS6594-Q1 device.

I²C channel 1 (I2C1) is the main channel with access to the registers, which control the configurable power

sequencer, the states and the outputs of power rails, the device operating states, and the RTC registers. I²C

channel 2 (I2C2), which is available through the GPIO1 and GPIO2 pins, is dedicated for accessing the Q&A

Watchdog communication registers. If GPIO1 and GPIO2 are not configured as I2C2 pins, I2C1 can access all

of the registers, including the Q&A Watchdog registers. If I2C_SPI_SEL = 1, SPI is the selected interface for the

device and can be used to access all registers as well.

The TPS6594-Q1 device includes an internal RC oscillator to sequence all resources during power up and

power down. Two internal LDOs (LDOVINT and LDOVRTC) generate the supply for the entire digital circuitry of

the device as soon as the external input supply is available through the VCCA input. A backup battery supply

input can also be used to power the RTC block and a 32 kHz Crystal Oscillator clock generator in the event of

main supply power loss.

TPS6594-Q1 device has eleven GPIOs each with multiple functions and configurable features. All of the GPIOs,

when configured as general purpose output pins, can be included in the power-up and power-down sequence

and used as enable signals for external resources. In addition, each GPIO can be configured as a wake-up input

or a sleep mode trigger. The default configuration of the GPIO port comes from the NVM memory, and can be

re-programmed by system software if the external connection permits.

The TPS6594-Q1 device includes a watchdog with trigger or Q&A modes to monitor software lockup, and two

system error monitoring inputs with fault injection options to monitor the lock-step signal of the attached SoC

or MCU. TPS6594-Q1 includes protection and diagnostic mechanisms such as short-circuit protection, thermal

monitoring, and thermal shutdown. The PMIC device can notify the processor of these events through the

interrupt signal open-drain output, allowing the processor to take action in response.

An SPMI interface is included in the TPS6594-Q1 device to distribute power state information to at most 5

satellite PMICs on the same network, thus enabling synchronous power state transition across multiple PMICs in

the application system. This feature allows the consolidation of IO control signals from up to 6 PMICs powering

the system into a primary TPS6594-Q1 device.

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10.2 Functional Block Diagram

VSYS

VIO

nPWRON/ENABLE

Control

Interface

VSYS OVP

EN_DRV

Windowed

Power-Good

Monitor

Grounds

PGOOD

SCL_I2C1/CLK_SPI

LDOVINT

VINT

BSM

LDOVRTC

VRTC

SDA_I2C1/SDI_SPI

I2C2_SCL_CS

I²C CNTRL,

or SPI

SYNCCLKOUT

Single or

Multi-Phase

I2C2_SDA_SDO

V_CCinternal

supply

nRSTOUT

nINT

PVIN_B1

SW_B1

FB_B1

VCCA

Internal

Interrupt

events

EN

VSEL

RAMP

CLK1

BUCK1

3.5 A

RC

Oscillator

DPLL

(Phase

synchronization

and dither)

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

OSC32KIN

(AVS)

<GND_B1>

SYNCCLKIN

PVIN_B2

SW_B2

FB_B2

EN

VSEL

RAMP

CLK2

BUCK2

3.5 A

DFT

NVM Controller

NVM Memory

(AVS)

<GND_B2>

Registers

VCCA

Pre-Configurable

Power Sequencer

Controller

PVIN_B3

SW_B3

FB_B3

EN

VSEL

RAMP

CLK3

BUCK3

3.5 A

VCCA_UVLO

VCCA

VCCA_OVP

(AVS)

ECO

PWM

DVS

<GND_B3>

WAKEn

NSLEEPn

Default NVM Settings

PVIN_B4

SW_B4

FB_B4

VCCA

EN

VSEL

RAMP

CLK4

BUCK4

4 A (1N)

3.5A (multiN)

Thermal

Monitoring and

Shutdown

(AVS)

<GND_B4>

Hot die detection

I2C2

SPI

PVIN_B5

SW_B5

FB_B5

Q&A WDT

EN

VSEL

RAMP

CLK5

BUCK5

2 A

NERRORn

Error Monitor

Single-Phase

32-kHz Crystal

Oscillator

<GND_B5>

RTC

OSC32KOUT

OSC32KCAP

100Ω

VRTC

Internal supply

REFGND1

Bypass

LDO1

500 mA

Bypass

LDO2

500 mA

Bypass

LDO3

500 mA

LDO4

300 mA

Low Noise

Quiet Ground

AMUX_OUT

Reference

and Bias

REFGND2

VCCA

* These red squares are internal pads for down-bonds to the package thermal/ground pad.

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10.3 Feature Description

10.3.1 System Supply Voltage Monitor and Over-Voltage Protection

The TPS6594-Q1 device includes an over-voltage protection mechanism through a 12 V compliant input monitor

at the VSYS_SENSE pin. When an over-voltage is detected at the VSYS_SENSE pin, OVPGDRV pin is pulled

low to disable the external high voltage load switch, which connects the VSYS supply to the VCCA pin. After

the over-voltage condition is cleared, the voltage at the OVPGDRV pin will recover after the voltage at the

VSYS_SENSE pin stays below V_{VSYS_RC_TH}for at least _{VSYS_RC_TH}

.

TI recommends connecting a 10 V zener diode to ground at the VSYS_SENSE pin and one or more series

resistors between the VSYS_SENSE pin and the pre-regulator output to limit the current surge and protect the

VSYS_SENSE pin from an over-voltage condition due to possible short at the pre-regulator output. The voltage

slew rate at the VSYS_SENSE pin must be limited to ≤ V_{VSYS_SR}to prevent possible damage to the device.

In case the TPS6594-Q1 device detects a VCCA over voltage condition, then the VCCA domain will be

unpowered and will not signal the over voltage condition to the VSYS over-voltage protection module. Therefore,

a dead-lock mechanism is implemented in the VSYS domain by setting a latch to keep the external high voltage

load switch (between VSYS and VCCA) open once the TPS6594-Q1 device has detected a VCCA over voltage

condition.

The TPS6594-Q1 will first check for possible fail-short condition of the external FET at initial power up. The

diagnostic mechanism will pull OVPDGRV pin low when VCCA reaches V_{OVP_FET_Short_TH}, and wait to make

sure VCCA decreases by V_{OVP_FET_Short_Hyst}before pulling the OVPGDRV pin high again. This mechanism will

effectively disconnect the VCCA pin from VSYS in case of a FET fail-short condition; with the addition of the

diagnostic comparator, however, it will also cause a non-monotonic power up behavior with an RC delay at the

VCCA pin. The RC delay is associated with the input capacitance at the VCCA pin and the internal pull-down

resistor value R_{VCCA_OVP_PD}

.

The comparator module in TPS6594-Q1, which monitors the voltage on the VCCA pins, controls the power state

machine of the device. VCCA voltage detection outputs determine the power states of the device as following:

VCCA_UVLO When the supply at the VCCA pin falls below the VCCA_UVLO threshold, TPS6594-Q1 returns

to the BACKUP state. LDOVRTC is powered by the output of the Backup Supply Management

(BSM) module during the BACKUP state. The device returns to the NO SUPPLY state and is

completely shutdown when the input supply of the LDOVRTC falls below the operating range.

The device will not return to the BACKUP state from the NO SUPPLY state.

VCCA_UV

TPS6594-Q1 transitions from the NO SUPPLY state to the INIT state when the voltage on the

VCCA pin rises above VCCA_UV during initial power up.

VCCA_OVP If the voltage on VCCA pin rises above the VCCA_OVP threshold while TPS6594-Q1 is in

operation ,despite the OVPGDRV mechanism, then the device will clear the ENABLE_DRV bit

and start the immediate shutdown sequence to protect itself from an over-voltage input condition.

A separate voltage comparator can be enabled to monitor whether or not the VCCA voltage is within the

expected PGOOD range when VCCA is expected to be 5 V or 3.3 V. Refer to Section 10.3.4 for additional detail

on the operation of the PGOOD monitor function.

LDOVINT, which is the internal supply to the digital core of the device, may attempt to restart the device when

the input voltage at VCCA pin falls or stays between VCCA_UVLO and VCCA_UV voltage levels; the voltage at

the VCCA pin, however, must be above the VCCA_UV voltage level for the device to power up properly.

The Figure 10-1 shows a block diagram of the system input monitoring and over-voltage protection mechanism,

and the generation of the VCCA_UVLO and VCCA_OVP power state control signals.

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VCCA

VSYS

Preregulator

High-Voltage

Load Switch

500Ω

Zener 1

(10 V)

VSYS Clamp

Regulator

VCCA_SENSE

Error

Amplifier

Safety

Bandgap

POWER_UP

Bandgap

Charge Pump

(×3)

EN

-

+

VCCA_UVLO

OVPGDRV

Monitor

œ

VCCA_OVP

VSYS_SENSE_OVP

Q

+

1

D

1

VSYS OVP

Monitor

VCCA OV and UVLO

Monitor

Figure 10-1. VSYS Monitor and OVPGDRV Output Generation

10.3.2 Power Resources (Bucks and LDOs)

The power resources provided by the TPS6594-Q1 device includes synchronous, current mode control bucks

and linear LDOs. These supply resources provide power to the external processors, components, and modules

inside the TPS6594-Q1 device. The supply of the bucks, the PVIN_Bx pins, must connect to the VCCA pin

externally. The supply of the LDOs, the PVIN_LDOx pins, may connect to the VCCA pin or a buck output which

is at a lower voltage level than the VCCA.

The voltage output of each power resource is continuously monitored by a dedicated analog monitor on an

independent reference voltage domain. An unused regulator can also be used as a voltage monitor for an

external rail by connecting the external rail to the FB_Bn the VOUT_LDOn pin. A residual voltage checking

option is also available for each power resource to ensure the output voltage has dropped below 150 mV before

it can be powered up again.

Table 10-1 lists the power resources provided by the TPS6594-Q1 device.

Table 10-1. Power Resources

RESOURCE

TYPE

VOLTAGE

CURRENT CAPABILITY

COMMENTS

0.3 to 0.6 V, 20-mV steps

0.6 to 1.1 V, 5-mV steps

1.1 to 1.66 V, 10-mV steps

1.66 to 3.34 V, 20-mV steps

BUCK1, BUCK2,

BUCK3

Can be configured in multi-phase mode

or stand-alone in single-phase mode

BUCK

3.5 A

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Table 10-1. Power Resources (continued)

RESOURCE

TYPE

VOLTAGE

CURRENT CAPABILITY

COMMENTS

0.3 to 0.6 V, 20-mV steps

0.6 to 1.1 V, 5-mV steps

1.1 to 1.66 V, 10-mV steps

1.66 to 3.34 V, 20-mV steps

4 A in single-phase mode Can be configured in multi-phase mode

3.5 A in multi-phase mode or stand-alone in single-phase mode

BUCK4

BUCK5

BUCK

0.3 to 0.6 V, 20-mV steps

0.6 to 1.1 V, 5-mV steps

1.1 to 1.66 V, 10-mV steps

1.66 to 3.34 V , 20-mV steps

BUCK

2 A

Only in single-phase mode

LDO1, LDO2,

LDO3

LDO

0.6 V to 3.3 V, 50-mV steps

1.2 V to 3.3 V, 25-mV steps

500 mA

300 mA

Bypass mode configurable

Low-noise

LDO4

10.3.2.1 Buck Regulators

10.3.2.1.1 Overview

The TPS6594-Q1 includes five synchronous buck converters, four of which can be combined in multi-phase

configuration. All of the buck converters support the following features:

•

Automatic mode control based on the loading (PFM or PWM mode) or Forced-PWM mode operation

External clock synchronization option to minimize crosstalk

Optional spread spectrum technique to reduce EMI

Soft start

AVS support with configurable slew-rate

Windowed undervoltage and overvoltage monitors with configurable threshold

Windowed voltage monitor for external supply when the buck converter is disabled

When the converters' outputs are combined in multi-phase configuration, it also supports the following features:

•

Current balancing between the phases of the converter

Differential voltage sensing from point of the load

Phase shifted outputs for EMI reduction

Optional dynamic phase shedding or adding

There are two modes of operation for the converter, depending on the output current required: pulse-width

modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load

currents of approximately 600 mA or higher. Lighter output current loads cause the converter to automatically

switch into PFM mode for reduced current consumption. The device avoids pulse skipping and allows easy

filtering of the switch noise by external filter components when forced-PWM mode is selected (BUCKn_FPWM

= 1). This is the recommended mode of operation for the buck converter to achieve better ripple and transient

performance. The drawback of this mode is the higher quiescent current at low output current levels.

When operating in PWM mode the phases of a multi-phase regulator are automatically added or shed based on

the load current level. The forced multi-phase mode can be enabled for lower ripple at the output.

A multi-phase synchronous BUCK converter offers several advantages over a single power stage converter.

Lower ripple on the input and output currents and faster transient response to load steps are the most significant

advantages for application processor power delivery. The heat generated is greatly reduced for each channel

due to the fact that power loss is proportional to the square of current with the even distribution of the load

current in a multi-phase output configuration. The physical size of the output inductor shrinks significantly due to

this heat reduction.

Figure 10-2 shows a block diagram of a single core.

Figure 10-3 shows the interleaving switching action of the multi-phase converters.

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PVIN

High-Side

Current Limit

Loop

Comparator

FBP

Feedback Network

FBN

PDN

Gate

Driver

PWM

Generator

œ

Low-Side

Current Limit

DAC

+

Error

Amplifier

CLK

Figure 10-2. Buck Core Block Diagram

I_{L_TOT_4PH}

I_L1

I_L2

I_L4

I_L3

0

90

180

270

360

450

540

630

720

PWM₁

PWM₂

PWM₄

PWM₃

Switching Cycle 360º

0

90

180

270

360

450

540

630

720

Phase (Degrees)

Figure 10-3. Example of PWM Timings, Inductor Current Waveforms, and Total Output Current in 4-Phase

Configuration. ¹

10.3.2.1.2 Multi-Phase Operation and Phase-Adding or Shedding

The 4-phase converters (Buck1, Buck2, Buck3, and Buck4) switches each channel 90° apart under heavy load

conditions. As a result, the 4-phase converter has an effective ripple frequency four times greater than the

switching frequency of any one phase. In the same way, 3-phase converter has an effective ripple frequency

three times greater and 2-phase converter has an effective ripple frequency two times greater than the switching

frequency of any one phase; the parallel operation, however, decreases the efficiency at light load conditions.

The TPS6594-Q1 can change the number of active phases to optimize efficiency for the variations of the load in

order to overcome this operational inefficiency. This is called phase adding or shedding. The concept is shown in

Figure 10-4.

The converter can be forced to multi-phase operation by the BUCKn_FPWM_MP bit in BUCKn_CTRL1 register.

If the regulator operates in forced multi-phase mode (two phases in the dual-phase configuration, three phases

1

Graph is not in scale and is for illustrative purposes only.

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in three-phase configuration, and four phases in a four-phase configuration) the forced-PWM operation is

automatically used. If the multi-phase operation is not forced, the number of phases are added and shed

automatically to follow the required output current.

Best efficiency obtained with

N=1

N=2

N=3

N=4

Load Current

Figure 10-4. Multiphase Buck Converter Efficiency vs Number of Phases (Converters in PWM Mode) ²

10.3.2.1.3 Transition Between PWM and PFM Modes

Force PWM mode operation with phase-adding or shedding optimizes efficiency at mid-to-full load. The

TPS6594-Q1 converter operates in PWM mode at load current of about 600 mA or higher. The device

automatically switches into PFM mode for reduced current consumption when forced-PWM mode is disabled

(BUCKn_FPWM = 0) at lighter load-current levels. A high efficiency is achieved over a wide output-load-current

range by combining the PFM and the PWM modes.

10.3.2.1.4 Multi-Phase Buck Regulator Configurations

The control of the multi-phase regulator settings is done using the control registers of the master buck in the

multi-phase configuration. The following slave registers are ignored:

•

BUCKn_CTRL register, except BUCKn_VMON_EN and BUCKn_RV_SEL

BUCKn_CONF register

BUCKn_VOUT_1 and BUCKn_VOUT_2 registers

BUCKn_PG_WINDOW register

Interrupt bits related to the slave buck, except BUCKn_ILIM_INT, BUCKn_ILIM_MASK and

BUCKn_ILIM_STAT

Table 10-2 shows the supported Multi-Phase buck regulator configurations and the assigned master buck in

each configuration.

Table 10-2. Master Buck Assignment for Supported Multi-phase Configuration

Supported Multi-Phase Buck Regulator Configuration

Master Buck Assignment

4-Phase: BUCK1 + BUCK2 + BUCK3 + BUCK4

BUCK1

3-Phase: BUCK1 + BUCK2 + BUCK3

2-Phase: BUCK1 + BUCK2

2

Graph is not in scale and is for illustrative purposes only.

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Table 10-2. Master Buck Assignment for Supported Multi-phase Configuration (continued)

Supported Multi-Phase Buck Regulator Configuration

Master Buck Assignment

2-Phase: BUCK3 + BUCK4

BUCK3

When the bucks are configured in 3-phase or 4-phase configurations, there are exceptions to the above list

of slave registers which are ignored. The configuration registers are user configurable for the voltage monitor

function on Buck3 and Buck4 in a 4-phase configuration and Buck3 in a 3-phase configuration. This is because

the FB_Bn pins of these bucks can be used as voltage monitor pins for external supplies. The following list of

registers and register bits for Buck3 and Buck4 can be used to enable and set the target voltage for the external

voltage monitoring function under such configuration:

•

BUCKn_VMON_EN bit

BUCKn_RV_SEL bit

BUCKn_VSEL bit

BUCKn_SLEW_RATE

BUCKn_VOUT_1 and BUCKn_VOUT_2 registers

BUCKn_PG_WINDOW register

Customers are responsible for the values set in these registers when using Buck3 or Buck4 to monitor an

external supply under the 3-phase or 4-phase configuration. If the voltage monitor function is not used under

such a scenario, the FB_Bn pins must be connected to the reference ground, and the BUCKn_VMON_EN and

BUCKn_RV_SEL bits must be set to '0'.

10.3.2.1.5 Spread-Spectrum Mode

The TPS6594-Q1 device supports spread-spectrum modulation of the buck regulators' switching clocks. Three

factory-selectable modulation modes are available: the first mode is modulation from external input clock at the

SYNCCLKIN pin; the second mode is modulating the input clock at the SYNCCLKIN pin using the DPLL; the

third mode is modulating the internal 20 MHz RC Oscillator clock using the DPLL.

This is a fixed NVM option and changing modulation setting during operation is not supported.

The modulation frequency range is limited by the DPLL bandwidth. The max frequency spread for the input clock

to the DPLL is ±18% to secure parametric compliance of the buck output performance.

The internal modulation is disabled by default and can be enabled and configured after power up. Internal

modulation is activated by setting the SS_EN control bit. The internal modulation must be disabled (SS_EN = 0)

when changing the following parameter:

•

SS_DEPTH[1:0] – Spread Spectrum modulation depth

When internal modulation is enabled and configured, it can be disabled by the system MCU during operation.

The device transition to different mission states does not impact internal modulation when it is enabled and

configured.

10.3.2.1.6 Adaptive Voltage Scaling (AVS) and Dynamic Voltage Scaling (DVS) Support

An AVS or a DVS voltage value can be configured by the attached MCU after the buck regulator is powered up

to the default output voltage selected in register BUCKn_VSET1, which loads its default value from NVM. The

purpose of the AVS/DVS voltage is to set the buck output voltage to enable optimal efficiency and performance

of the attached SoC.

All of bucks on the TPS6594-Q1 device support AVS and DVS voltage scaling changes. Once the

AVS/DVS voltage value is written into the BUCKn_VSET1 or BUCKn_VSET2 register, and the MCU sets the

BUCKn_VSEL register to select the AVS/DVS voltage, the output of the buck will maintain at the AVS/DVS

voltage level instead of the default voltage from NVM until any one of the following event occurs:

•

Error that causes the device to re-initialize itself through a power cycle after reaching the SAFE RECOVERY

state

•

Error that causes the device to execute warm reset

MCU configures the device to enter the LP STANDBY state

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Figure 10-5 shows the arbitration scheme for loading the buck output level from the AVS register using the

BUCKn_VSET control registers.

I2C/SPI

REGULATOR ENABLE

I2C/SPI

AVS/DVS ENABLE REG

BUCKn_EN

BUCKn_VSEL

I2C/SPI

BUCKn_VSET1

BUCKn_VSET2

DCDC

Regulator

MUX

Figure 10-5. AVS/DVS Configuration Register Arbitration Diagram

The OV and UV threshold of the buck output voltage monitor will be updated automatically by the digital control

block during the AVS or DVS voltage change. When the output voltage is increased, the OV threshold is updated

at the same time the BUCKn_VSETx is updated to the AVS voltage level, while the UV threshold is updated after

a delay calculated by Equation 1.

When the output voltage is decreased, the UV threshold is updated at the same time the BUCKn_VSETx is

updated to the AVS voltage level, while the OV threshold is updated after a delay calculated by Equation 1.

t_{PG_OV_UV_DELAY}= (dV / BUCKn_SLEW_RATE) + t_{settle_Bx}

(1)

In order to prevent erroneous voltage monitoring, the digital block also temporarily masks the results of the

OV and UV monitor from the regulator output when the buck is enabled and the voltage is rising to the

BUCKn_VSETx level. The duration of the mask starts from the time the buck is enabled. The buck OV monitor

output is masked for a fixed delay time of t_{PG_OV_GATE}, which is approximately 115 µs – 128 µs. The UV monitor

output is masked for the time duration calculated by Equation 2. The 370 µs additional delay time in the formula

includes the start-up delay of the buck, the fixed delay after the ramp, and the time for the BIST operation of the

OV and UV monitors.

t_{PG_UV_GATE}= (BUCKn_VSEL / BUCKn_SLEW_RATE) + 370 µs

(2)

Note

Because output capacitance, forward and negative current limits and load current of the buck may

affect the slew rate of the buck output, the delay time of t_{PG_UV_GATE}may not be sufficient long for the

slower slew rate setting when the target buck output voltage is higher. Please refer to the PMIC User's

Guide for detail information about the supported voltage level and slew rate setting combinations of a

particular orderable part number.

Figure 10-6 and Figure 10-7 are timing diagrams illustrating the voltage change for AVS and DVS enabled bucks

and the corresponding OV and UV monitor threshold changes.

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Initial voltage

AVS_VNOM

OV limit

UV limit

Default from NVM

BUCKn VOUT

I2C/SPI write

State control (or I2C/SPI write)

0x00

0

0x5F

0x5A

BUCKn_VSET1

BUCKn_VSET2

BUCKn_EN

Automatic control

by digital

0x5F

1

0

1

0 us

Register bits

0x00

0

0x5F

0x5A

BUCKn_OV_SET

BUCKn_UV_SET

BUCKn_VSEL

t_{PG_OV_UV_DELAY}

0x5A

0

1

0

1

BUCKn_OV_UV_EN

Automatic control

by digital

Automatic control

by digital

0 us

Automatic control

by digital

BUCKn_OV Monitor Output

BUCKn_OV Gating

t_{PG_OV_GATE}

Automatic control

by digital

0 us

BUCKn_UV Monitor Output

BUCKn_UV Gating

t_{PG_UV_GATE}

Figure 10-6. AVS Voltage and OV UV Threshold Level Change Timing Diagram

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OPP_OD

(or OPP_TURBO)

OPP_OD

(or OPP_TURBO)

OV limit

OPP_NOM

OV limit

UV limit

BUCKn VOUT

I2C/SPI write (DVFS control)

State control (or I2C/SPI write)

0x5F

1

0x73

BUCKn_VSET1

BUCKn_VSET2

Automatic control

by digital

0

1

BUCKn_EN

0 us

0x5F

0x73

Register bits

BUCKn_OV_SET

BUCKn_UV_SET

BUCKn_VSEL

t_{PG_OV_UV_DELAY}

0x5F

0x73

0

1

0

1

BUCK1n_OV_UV_EN

0 us

Automatic control

by digital

Automatic control

by digital

BUCKn_OV Monitor Output

BUCKn_OV Gating

t_{PG_OV_GATE}

0 us

BUCKn_UV Monitor Output

BUCKn_UV Gating

t_{PG_UV_GATE}

Figure 10-7. DVS Voltage and OV UV Threshold Level Change Timing Diagram

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10.3.2.2 Sync Clock Functionality

The TPS6594-Q1 device contains a SYNCCLKIN (GPIO10) input to synchronize switching clock of the buck

regulator with the external clock. The block diagram of the clocking and PLL module is shown in Figure 10-8.

The external clock is selected when the external clock is available, and SEL_EXT_CLK = '1'. The nominal

frequency of the external input clock is set by EXT_CLK_FREQ[1:0] bits in the NVM and it can be 1.1 MHz, 2.2

MHz, or 4.4 MHz. The external SYNCCLKIN clock must be inside accuracy limits (–18%/+18%) of the typical

input frequency for valid clock detection.

The EXT_CLK_INT interrupt is generated in case the external clock is expected (SEL_EXT_CLK = 1), but it is

not available or the clock frequency is not within the valid range.

The TPS6594-Q1 device can also generate

a clock signal, SYNCCLKOUT, for external device

use. The SYNCCLKOUT_FREQ_SEL[1:0] selects the frequency of the SYNCCLKOUT. Note:

SYNCCLKOUT_FREQ_SEL[1:0] must stay static while SYNCCLKOUT is used, as changing the output

frequency selection may cause glitches on the clock output. The SYNCCLKOUT is available through GPIO8,

GPIO9, or GPIO10.

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10.3.2.3 Low Dropout Regulators (LDOs)

All of the LDO regulators in the TPS6594-Q1 device can be supplied by the system supply or another pre-

regulated voltage source which are within the specified VIN range. The PVIN_LDOn voltage level must be equal

or less than the VCCA voltage level to ensure proper operation of the LDOs. The default output voltages of all

LDOs are loaded from the NVM memory and can be configured by the LDOn_VSET[7:0]. There is no hardware

protection to prevent software from selecting an improper output voltage if the minimum level of PVIN_LDOn is

lower than the dropout voltage of the LDO regulator in addition to the configured LDO output voltage. In such

conditions, the output voltage will droop to near the PVIN_LDOn level.

Note

Writing a RESERVED value to the LDOn_VSET[7:0] register bits will trigger a LDOn_OV_INT or

LDOn_UV_INT interrupt.

LDO regulators do not have slew rate control for voltage ramp; by setting the LDOn_SLOW_RAMP bit to '1',

however, will slow down the ramp up speed of the regulator output voltage to < 3 V/ms.

If an LDO is not needed, it can be used as a voltage monitor for an external rail by connecting the external rail

to the VOUT_LDOn pin. The voltage output level to be monitored must be within the PGOOD monitor range of

the LDOn_VSET[7:0] of the LDO. If an external resistor divider is necessary in this case, the user must take into

account the input impedance at the VOUT_LDOn pin (as shown in Figure 10-9), and adjust the resistor values to

compensate for the voltage shift.

External Supply

Output

PVIN_LDOn

VOUT_LDOn

LDO

50 kΩ

Pull-Down resistor

512 kΩ

when LDOs are

Disabled

LDOn_UV_THR

+

UV

œ

DAC

œ

OV

+

LDOnOV_THR

Figure 10-9. Impedance at the VOUT_LDOn Pins

10.3.2.3.1 LDOVINT

The LDOVINT voltage regulator is dedicated to supply the digital and analog functions of the TPS6594-Q1

device, which are not required to be always-on and can be turned-off when the device is in low power states.

The LDOVINT regulator is automatically enabled and disabled as needed if LP_STANDBY_SEL = '1'. The

automatic control optimizes the overall current consumption when the device is in low power LP_STANDBY

state.

The TPS6594-Q1 device's LDOVINT is dedicated for internal use only, and cannot be used to support external

loads. The VOUT_LDOVINT pin should only be connected to the output filtering capacitor for the regulator and

nothing else.

10.3.2.3.2 LDOVRTC

The LDOVRTC regulator supplies always-on functions, such as wake-up functions. This power resource is active

as soon as a valid VCCA is present. The TPS6594-Q1 device's LDOVRTC is dedicated for internal use only,

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and cannot be used to support external loads. The VOUT_LDOVRTC pin should only be connected to the output

filtering capacitor for the regulator and nothing else.

This resource runs in normal mode or backup mode. The LDOVRTC regulator functions in normal mode when

supplied from the main system power rail and is able to supply the input buffers of GPIO3 and GPIO4, the digital

components, the crystal, and the RTC calendar module of the TPS6594-Q1 device. The LDOVRTC regulator

remains on in BACKUP state when VCCA is below the VCCA_UVLO level, and the backup power source is

above the LDOVRTC_UVLO level.

Only the 32 kHz crystal and the RTC counter are activated in the BACKUP state. The RTC calendar function

will remain active in the LP STANDBY state, but the interrupt functions are reduced to maintaining the wake up

functions only. The RTC calendar and interrupt functions are fully activated in the mission states.

The customer has the option to enable the shelf mode by setting the LDORTC_DIS bit to 1 while the device is in

the MISSION state and the I2C bus is in operation and ramp down VCCA to 0 V immediately after the I2C write

has completed. This bit will force the device to skip the BACKUP state and enters the NO SUPPLY state under

VCCA_UVLO condition. This mode is useful to prevent the continual draining of the back up power source when

the 32 KHz crystal and RTC counter functions are no longer needed.

10.3.2.3.3 LDO1, LDO2, and LDO3

The LDO1, LDO2 and LDO3 regulators can deliver up to 500 mA of current, with a configurable output range

of 0.6 V to 3.3 V in 50 mV steps. These 3 LDO regulators also support bypass mode, which allows an input

voltage at the PVIN_LDOn to show up at the VOUT_LDOn pin. This feature allows the LDOs to be configured as

load switches with power sequencing control. Similar to the buck regulatros mentioned in Section 10.3.2.1.4, an

un-used regulator can also be used as a voltage monitor for an external rail by connected the external rail to the

VOUT_LDOn pin.

The bypass capability to connect the input voltage to the output in bypass mode is supported when the input

voltage is within the 1.7 V to 3.5 V range. This bypass capability also allows the LDO to switch from 3.3 V in

bypass mode to 1.8 V in LDO mode or from 1.8 V in LDO mode to 3.3 V in bypass mode for an SD card I/O

supply.

It is important to wait until the LDO has settled on the target voltage from the previous change when changing

the LDO output voltage setting. The worst case voltage scaling time for LDO1, LDO2, and LDO3 is 63 µs x (7 +

the number of 50 mV steps to the new target voltage).

Table 10-4 shows the coding used to select the output voltage for LDO1, LDO2, and LDO3.

Table 10-4. Output Voltage Selection for LDO1, LDO2, and LDO3

Output Voltage

[V]

Output Voltage

[V]

Output Voltage

[V]

Output Voltage

[V]

LDOx_VSET

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

Reserved

0.60

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

1.20

1.25

1.30

1.35

1.40

1.45

1.50

1.55

1.60

1.65

1.70

1.75

1.80

1.85

1.90

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

2.00

2.05

2.10

2.15

2.20

2.25

2.30

2.35

2.40

2.45

2.50

2.55

2.60

2.65

2.70

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

2.80

2.85

2.90

2.95

3.00

0.65

3.05

0.70

3.10

0.75

3.15

0.80

3.20

0.85

3.25

0.90

3.30

0.95

Reserved

1.00

1.05

1.10

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Table 10-4. Output Voltage Selection for LDO1, LDO2, and LDO3 (continued)

Output Voltage

[V]

Output Voltage

[V]

Output Voltage

[V]

Output Voltage

[V]

LDOx_VSET

0x0F

1.15

0x1F

1.95

0x2F

2.75

0x3F

Reserved

10.3.2.3.4 Low-Noise LDO (LDO4)

The LDO4 regulator can deliver up to 300 mA of current, with a configurable output range of 1.2 V to 3.3 V in 25

mV steps. This LDO is specifically designed to supply noise sensitive circuits. This supply can be used to power

circuits such as PLLs, oscillators, or other analog modules that require low noise on the supply. LDO4 does not

support bypass mode. However it can also be used as a external voltage monitor if its regulator function is not

needed.

Table 10-5 shows the coding used to select the output voltage for LDO4.

Table 10-5. Output Voltage Selection for LDO4

Output Voltage

[V]

Output Voltage

[V]

Output Voltage

[V]

Output Voltage

[V]

LDO4_VSET

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

Reserved

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

1.200

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

1.475

1.500

1.525

1.550

1.575

1.600

1.625

1.650

1.675

1.700

1.725

1.750

1.775

1.800

1.825

1.850

1.875

1.900

1.925

1.950

1.975

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

0x5E

0x5F

2.000

2.025

2.050

2.075

2.100

2.125

2.150

2.175

2.200

2.225

2.250

2.275

2.300

2.325

2.350

2.375

2.400

2.425

2.450

2.475

2.500

2.525

2.550

2.575

2.600

2.625

2.650

2.675

2.700

2.725

2.750

2.775

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

2.800

2.825

2.850

2.875

2.900

2.925

2.950

2.975

3.000

3.025

3.050

3.075

3.100

3.125

3.150

3.175

3.200

3.225

3.250

3.275

3.300

Reserved

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10.3.3 Residual Voltage Checking

The residual voltage (RV) checking feature ensures the voltage level at the buck or LDO regulators is below

V_{TH_SC_RV}before it can be ramped up to the target output voltage. If BUCKn/LDOn_RV_SEL=1 by default, then

the residual voltage is also checked before the device enters the BOOT_BIST state. If the residual voltage at

the output of the regulators is greater than V_{TH_SC_RV}, then the device waits until voltage goes below V_{TH_SC_RV}

before starting BOOT_BIST or the voltage ramp up.

This feature is enabled by the BUCKn_VMON_EN and BUCKn_RV_SEL bits for each buck regulator, and by the

LDOn_VMON_EN and LDOn_RV_SEL bits for each LDO regulator. The VMON of the corresponding regulator

will remain on after the regulator is disabled and for the RV_TIMEOUT period when the RV checking feature

is enabled. After the RV_TIMEOUT period elapses, the output voltage of the regulator will be compared to

the short circuit (SC) threshold of V_{TH_SC_RV}and assert the corresponding BUCKn_SC_INT or LDOn_SC_INT

interrupt bits, if the residual voltage is still higher than the threshold voltage. The RV_TIMEOUT period for the

BUCK regulators is automatically calculated by the digital controller inside the device by Equation 3. The RV

timeout period of the LDO regulator is configured by the LDOn_RV_TIMEOUT[3:0].

t_{BUCK_RV_TIMEOUT}= BUCKn_VSET / BUCKn_SLEW_RATE + 100 µs

(3)

The residual voltage check can also be performed on external rails when they are connected to unused LDO

regulator outputs.

Figure 10-10 shows the timing diagram of the residual voltage checking operation which results in pass or fail

results.

RV Check Passing Case:

RV Check Failing Case:

OV limit

Buck ramp time:

Vout/SR

Ramp time slower than expected

UV limit

BUCK/LDO VOUT

SC Threshold

BUCKn/LDOn_sc_out

(internal signal)

BUCKn/LDOn_EN

BUCKn/LDOn_VMON_EN

BUCKn/LDOn_RV_SEL

RV Timeout

BUCKn/LDOn_vmon_en

(internal signal)

Disabled by digital after

RV Timeout

Disabled by digital after

RV Timeout

BUCKn/LDOn_SC_INT

Interrupt set if buckx/ldox_sc_out = 0

Figure 10-10. Residual Voltage Check Timing Diagram

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10.3.4 Output Voltage Monitor and PGOOD Generation

The TPS6594-Q1 device monitors the under-voltage (UV) and over-voltage (OV) conditions of the bucks' and

LDOs', output voltage and VCCA (when it is expected to be 5 V or 3.3 V), and has the option to indicate the

result with a PGOOD signal. Thermal warning can also be included in the result of the PGOOD monitor if it is not

masked. Either voltage and current monitoring or only voltage monitoring can be selected for PGOOD indication.

This selection is set by the PGOOD_SEL_BUCKn register bits for each buck regulator (select master phase

for multi-phase regulator), and is set by the PGOOD_SEL_LDOn register bits for each LDO regulator. When

voltage and current are monitored, an active PGOOD signal active indicates that the regulator output is inside

the Power-Good voltage window and that load current is below the current limit. If only voltage is monitored, then

the current monitoring is ignored for the PGOOD signal.

The BUCKn_VMON_EN bit enables the OV and UV, Short-circuit and current limit comparators. For LDO

regulators, the LDOn_VMON_EN bit enables the OV and UV, Short-circuit and current limit comparators. When

a buck or an LDO is not needed as a regulated output, it can be used as a voltage monitor for an external rail.

For buck converters, if the BUCKn_VMON_EN bit remains '1' while the BUCKn_EN bit is '0', it can be used as

a voltage monitor for an external rail which is connected to the buck converter's FB_Bn pin. For LDO regulators,

if the LDOn_VMON_EN bit remains '1' while the LDOn_EN bit is '0', it can be used as a voltage monitor for an

external rail which is connected to the VOUT_LDOn pin.

When the monitor for a buck or LDO regulator is disabled, the output of the corresponding monitor is

automatically masked to prevent it from forcing PGOOD inactive. This allows PGOOD to be connected to other

open-drain power good signals in the system.

The VCCA_VMON_EN bit enables the monitoring of the VCCA input voltage. It can be enabled as an NVM

default setting, which will start the monitoring of the VCCA voltage after the voltage monitor passes ABIST

during the BOOT BIST state. The reference voltage for the VCCA monitor can be set by the VCCA_PG_SET

bit to either 3.3 V or 5 V. The PGOOD_SEL_VCCA register bit selects whether or not the result of the VCCA

monitor will be included in the PGOOD monitor output signal.

An NVM option is available to gate the PGOOD output with the nRSTOUT and the nRSTOUT_SoC signals, the

intended reset signals for the safety MCU and the SoC respectively. When PGOOD_SEL_NRSTOUT = '1', the

PGOOD pin is gated by the nRSTOUT signal. When PGOOD_SEL_NRSTOUT_SOC = '1', the PGOOD pin is

gated by the nRSTOUT_SoC signal. This option allows the PGOOD output to be used as an enable signal for

external peripherals.

The monitoring from all the output rails are combined, and PGOOD is active only if all the sources shows active

status.

The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW bit. If the bit is 0, only

undervoltage is monitored; if the bit is 1, then undervoltage and over-voltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by PGOOD_POL and GPIO9_OD bits.

Figure 10-11 shows the Power-Good generation block diagram, and Figure 10-12 shows the Power-Good

waveforms.

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Die

Temperature

Monitor

T_J< T_WARN

TWARN_LEVEL

PGOOD_SEL_TDIE_WARN

VMON

BUCKn

VMON

PGOOD_BUCKn

BUCKn

PGOOD_WINDOW

BUCKn

Monitor

BUCKn_ILIM

BUCKn_VSETn

BUCKn_UV_THR

BUCKn_OV_THR

BUCKn_VMON_EN

PGOOD_SEL_BUCKn

VMON

BUCKn

VMON

BUCKn

Monitor

PGOOD_LDOn

BUCKn

LDOn

PGOOD_WINDOW

PGOOD (GPIO9)

LDOn_VSET

LDOn_UV_THR

LDOn_OV_THR

PGOOD_POL

LDOn_VMON_EN

PGOOD_SEL_LDOn

PGOOD_VCCA

VCCA

Monitor

PGOOD_WINDOW

VCCA_PG_SET

VCCA_UV_THR

VCCA_OV_THR

VCCA_VMON_EN

PGOOD_SEL_VCCA

NRSTOUT

PGOOD_SEL_NRSTOUT

NRSTOUT_SoC

PGOOD_SEL_NRSTOUT_SOC

Figure 10-11. PGOOD Block Diagram

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Voltage

Powergood window

BUCKn_VSETn or

LDOn_VSET (1)

Power-good

window

BUCKn_VSETn or

LDOn_VSET (2)

Time

On Request

VIO

BUCKn_VMON_EN

or LDOn_VMON_EN

NRSTOUT

or NRSTOUT_SoC

t_latency

_PGOOD

PGOOD

(PGOOD_SEL_NRSTOUT =1

or PGOOD_SEL_NRSTOUT_SOC = 1)

t_latency

_PGOOD

PGOOD

(PGOOD_SEL_NRSTOUT = 0

and PGOOD_SEL_NRSTOUT_SOC = 0)

BUCKn_VSETn or LDOn_VSET (1)

BUCKn_VSETn or LDOn_VSET (2)

Regulator VSET

Figure 10-12. PGOOD Waveforms

The OV and UV threshold of the buck and LDO output voltage monitor are updated automatically by the digital

control block when the output voltage setting changes. When the output voltage is increased, the OV threshold

is updated at the same time the VSET of the regulator is changed. The UV threshold is updated after a delay

calculated by the delta voltage change and the slew rate setting. When the output voltage is decreased, the UV

threshold is updated at the same time the VSET of the regulator is changed. The OV threshold is updated after

a delay calculated by the delta voltage change and the slew rate setting. The OV and UV threshold of the buck

and LDO output voltage monitors are calculated based on the target output voltage set by the corresponding

BUCKn_VSET1, BUCKn_VSET2, or LDOn_VSET registers, and the deviation from the target output voltage set

by the corresponding BUCKn_UV_THR, BUCKn_OV_THR, LDOn_UV_THR, and the LDOn_OV_THR registers.

For the OV and UV threshold of buck and LDO output monitors to update with the correct timing, the following

operating procedures must be followed when updating the VSET values of the regulators to avoid detection of

OV/UV fault:

•

Buck and LDO regulators must be enabled at the same time as or earlier than as their VMON so that the

voltage will reach target value before OV/UV self test (BIST) is done

•

New voltage level must not be set before the startup has finished and OV/UV self test (BIST) is completed

New voltage level must not be set before the previous voltage change (ramp plus settling time) has

completed

It is important to note: when a regulator is enabled, a voltage monitor self test is performed to ensure proper

operation. The monitoring function is disabled and gated during this time. Figure 10-13 shows the timing diagram

of the buck regulator UV/OV self test. Figure 10-14 shows the timing diagram of the LDO UV/OV self test. The

monitoring function will become effective after the gating period.

The self test for VCCA, Buck and LDO voltage monitors is done every time when the monitoring function is

enabled and VMON_ABIST_EN=1. The self test checks that OV and UV comparators are changing their output

when the input thresholds are swapped. The self test assumes that the input voltage is inside OV/UV threshold

limits. If the voltage is outside the limits, the self test will fail and BIST_FAIL_INT interrupt is set. In addition, a

failed self test for over-voltage comparator will set the over-voltage interrupt.

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OV/UV test 1 & 2:

25µs + 25µs

OV limit

UV limit

Settling time

BUCKx VOUT

Ramp time

Vout/SR

Start-up delay

BUCKx_VMON_EN

BUCKx_EN

buckx_ov_gating

buckx_uv_gating

50µs

t_{PG_OV_GATE}

Total time: t_{PG_UV_GATE}

Figure 10-13. Timing of Buck Regulator UV/OV Self Test

OV/UV test 1 & 2:

25µs + 25µs

OV limit

UV limit

LDOx VOUT

LDOx_VMON_EN

LDOx_EN

ldox_ov_gating

ldox_uv_gating

Typ 102 ~ 109µs

50µs

Total time:

Typ 601 ~ 608µs

Figure 10-14. Timing of LDO Regulator UV/OV Self Test

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10.3.5 Thermal Monitoring

The TPS6594-Q1 device includes several thermal monitoring functions for internal thermal protection of the

PMIC.

The TPS6594-Q1 device integrates thermal detection modules to monitor the temperature of the die. These

modules are placed on opposite sides of the device and close to the LDO and BUCK modules. An over-

temperature condition at either module first generates a warning to the system, and if the temperature continues

to rise, then a switch-off of the PMIC device can occur before damage to the die.

Three thermal protection levels are available. One of these protections is a thermal warning function described

in Section 10.3.5.1, which sends an interrupt to software. Software is expected to close any noncritical running

tasks to reduce power. The second and third protections are the thermal shutdown (TS) function described in

Section 10.3.5.2, which begins device shutdown orderly or immediately.

Thermal monitoring is automatically enabled when any one of the buck or LDO outputs is enabled within the

mission states. It is disabled in low power states, including the LP_STANDBY state, when only the internal

regulators are enabled, to minimize the device power consumption. Indication of a thermal warning event is

written to the TWARN_INT register.

The current consumption of the thermal monitoring can be decreased in the mission states when the low power

dissipation is important. If LPM_EN bit is set and the temperature is below thermal warning level in all thermal

detection modules, only one thermal detection module is monitored. If the temperature rises in this module,

monitoring in all thermal detection modules is started.

If the die temperature of the TPS6594-Q1 device continues to rise while the device is in mission state, an

TSD_ORD_INT or TSD_IMM_INT interrupt is generated, causing a SEVERE or MODERATE error trigger

(respectively) in the state machine. While the sequencing and error handling is NVM memory dependent,

TI recommends a sequenced shutdown for MODERATE errors, and an immediate shutdown, using resistive

discharging, for SEVERE errors to prevent damage to the device. The system cannot restart until the

temperature falls below the thermal warning threshold.

10.3.5.1 Thermal Warning Function

The thermal monitor provides a warning to the host processor through the interrupt system when the

temperature reaches within a cautionary range. The threshold value must be set to less than the thermal

shutdown threshold.

The integrated thermal warning function provides the MCU an early warning of over-temperature condition. This

monitoring system is connected to the interrupt controller and can send an TWARN_INT interrupt when the

temperature is higher than the preset threshold. The TPS6594-Q1 device uses the TWARN_LEVEL register

bit to set the thermal warning threshold temperature at 130°C or 140°C. There is no hysterisis for the thermal

warning level.

When the power-management software triggers an interrupt, immediate action must be taken to reduce the

amount of power drawn from the PMIC device (for example, noncritical applications must be closed).

10.3.5.2 Thermal Shutdown

The thermal shutdown detector monitors the temperature on the die. If the junction reaches a temperature at

which damage can occur, a switch-off transition is initiated and a thermal shutdown event is written into a status

register. There are two levels of thermal shutdown threshold. When the die temperature reaches the T_{SD_orderly}

level, an orderly shutdown of the TPS6594-Q1 device will take place. If the die temperature raises rapidly and

reaches the T_{SD_imm}level before the orderly shutdown process completes, an immediate shutdown of the device

will take place to turn off all of the power resources as rapidly as possible. After the thermal shutdown takes

place, the system cannot restart until the die temperature falls below the thermal warning threshold.

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10.3.6 Backup Supply Power-Path

LDOVRTC is supplied from either the VBACKUP (backup supply from either coin-cell or super-cap) input or

VCCA. The power-path is designed to prioritize VCCA to maximize the life of the backup supply.

When VCCA drops below the VCCA_UVLO threshold, the device shuts down all rails except LDOVRTC and

enters BACKUP mode. At this point, the Backup Supply Power-Path switches to the VBACKUP as the input of

LDOVRTC. When the voltage of VCCA returns to level above the VCCA_UVLO threshold level, the power-path

switches the input of LDOVRTC back to VCCA.

When both the VCCA voltage drop below the VCCA_UVLO threshold, and the VBACKUP voltage drops below

the RTC_LDO_UVLO threshold, LDOVRTC is turned OFF and the digital core is reset, forcing the device into

NO SUPPLY state.

Note: backup supply is not required for the device to operate. The device will skip BACKUP state if the

VBACKUP pin is grounded.

10.3.7 General-Purpose I/Os (GPIO Pins)

The TPS6594-Q1 device integrates eleven configurable general-purpose I/Os that are multiplexed with

alternative features as listed in Section 7

For GPIOs characteristics, refer to Electrical Characteristics tables for Digital Input Signal Parameters and Digital

Output Signal Parameters.

When configured as primary functions, all GPIOs are controlled through the following set of registers bits under

the individual GPIOn_CONF register.

•

GPIOn_DEGLITCH_EN: Enables the 8 µs deglitch time for each GPIO pin (input)

GPIOn_PU_PD_EN: Enables the internal pull up or pull down resistor connected to each GPIO pin

GPIOn_PU_SEL: Selects the pull up or the pull down resistor to be connected when GPIOn_PU_PD_EN =

'1'. '1' = pull-up resistor selected, '0' = pull-down resistor selected

•

GPIOn_OD: Configures the GPIO pin (output) as: '1' = open drain, '0' = push-pull

GPIOn_DIR: Configures the input or output direction of each GPIO pin

Each GPIO event can generate an interrupt on a rising edge, falling edge, or both, configured through the

GPIOn_FALL_MASK and the GPIOn_RISE_MASK register bits. A GPIO-interrupt applies when the primary

function (general-purpose I/O) has been selected and also for the following alternative functions:

•

nRSTOUT_SOC

PGOOD

nERR_MCU

nERR_SoC

TRIG_WDOG

DISABLE_WDOG

NSLEEP1, NSLEEP2

WKUP1, WKUP2

LP_WKUP1, LP_WKUP2

The GPIOn_SEL[2:0] register bits under the GPIOn_CONF registers control the selection between a primary and

an alternative function. When a pre-defined function is selected, some predetermined IO characteristics (such as

pullup, pulldown, push-pull or open drain) for the pin will be enforced regardless of the settings of the associated

GPIO configuration register. Please note that if the GPIOn_SEL[2:0] is changed during device operation, a signal

glitch may occur which may cause digital malfunction, especially if it involves a clock signal such as SCL_I2C2,

CLK32KOUT, SCL_SPMI, SYNCCLKIN, or SYNCCLKOUT. Please refer to Section 7.1 for more detail on the

predetermined IO characteristics for each pre-defined digital interface function.

All GPIOs can be configured as a wake-up input when it is configured as a WKUP1 or a WKUP2 signal. Only

GPIO3 and GPIO4 can be configured as LP_WKUP1 or LP_WKUP2 signal so that they can be used to wake

up the device from LP_STANDBY state. All GPIOs can also be configured as a NSLEEP1 or a NSLEEP2 input.

For more information regarding the usage of the NSLEEPx pins and the WKUPx pins, please refer to Section

10.4.1.2.4.3 and Section 10.4.1.2.4.4.

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Any of the GPIO pin can also be configured as part of the power-up sequence to enable external devices such

as external BUCKs when it is configured as a general-purpose output port.

The nINT , EN_DRV, nRSTOUT pins and nRSTOUT_SOC signals have readback monitoring to detect errors on

the signals. The monitoring of the EN_DRV signal checks for mismatch in both low and high levels. For nINT,

nRSTOUT and nRSTOUT_SOC signals, the readback monitoring checks for mismatches only in the low level,

therefore allow the signals to be combined with other signals externally. The readback mismatch is continuously

monitored without deglitch circuitry during operation, and the monitoring is gated for t_{gate_readback}period when the

signal state is changed or when a new function is selected for the GPIO pin with the GPIOn_SEL bits.

Note

All GPIOs defaults to generic input pins before NVM memory is loaded during device power up.

Therefore if any GPIOs has external pull-up resistros connecting to a voltage domin which is

energized before the NVM memory is loaded, the GPIO pin will be pulled high before the configuration

for the pin is loaded from the NVM.

Note

For GPIO pins with internal pull down enabled, pulling the voltage at the pin higher than the voltage

level of its output power domain, will result in additional leackage. If the internal pull down must

be enabled, please use resistor divder to divide down the input voltage, or use a series resistor to

connect to the input source and ensure the voltage level at the GPIO pin is below the voltage level of

its output power domain.

10.3.8 nINT, EN_DRV, and nRSTOUT Pins

The nINT, EN_DRV, nRSTOUT, and nRSTOUT_SoC pins are IO pins with dedicated functions.

The nINT pin is the open drain interrupt output pin. More description regarding the function of this pin can be

found under Section 1.

The nRSTOUT pin, together with the nRSTOUT_SoC configured IO pin, are the system reset pins which can be

configured as open-drain or push-pull outputs. They stay in the default low state until they are pulled up by the

PFSM of the device, typically after the end of a power up sequence, and are the first to be pulled low during a

power down sequence.

The purpose of the EN_DRV pin is to indicate when the device enters safe state. It has an internal 10kΩ

high-side pull up to the VCCA supply. The TPS6594-Q1 pulls this pin to the default low state, and releases the

pull down when the device arrives at a safe operating state. The MCU can pull this output pin high by setting the

ENABLE_DRV bit to '1' when TPS6594-Q1 releases the pull down.

The nINT, EN_DRV, nRSTOUT and nRSTOUT_SOC pins have readback monitoring to detect errors on the

signals. The monitoring of the EN_DRV signal checks for mismatch in both low and high levels. For nINT,

nRSTOUT and nRSTOUT_SOC signals, the readback monitoring checks for mismatches only in the low

level, therefore allow the signals to be combined with other signals externally. The readback mismatch is

continuously monitored without deglitch circuitry during operation, and the monitoring is gated for t_{gate_readback}

period when the signal state is changed or when a new function is selected for the GPIO pin with

the GPIOn_SEL bits. NINT_READBACK_INT, EN_DRV_READBACK_INT, NRSTOUT_READBACK_INT, and

NRSTOUT_SOC_READBACK_INT are the interrupt bits which will be asserted in an event of a readback

mismatch for these pins, respectively.

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10.3.9 Interrupts

The interrupt registers in the device are organized in hierarchical fashion. The interrupts are grouped into the

following categories:

BUCK ERROR

These interrupts indicate over-voltage (OV), under-voltage (UV), short-circuit (SC),

residual voltage (SC) and over-current (ILIM) error conditions found on the Buck

regulators.

LDO ERROR

These interrupts indicate OV, UV, and SC error conditions found on the LDO

regulators, as well as OV and UV error conditions found on the VCCA supply.

SEVERE ERROR

These errors indicate severe device error conditions, such as thermal shutdown,

PFSM sequencing and execution error and pre-regulator over-voltage failure, which

causes the device to trigger the PFSM to execute immediate shutdown of all digital

outputs, external voltage rails and monitors, and proceed to the Safe Recovery State.

MODERATE ERROR

These interrupts provide warnings to the system to indicate detection of multiple

WDOG Errors or ESM errors exceeding the allowed recovery count, detection of long

press nPWRON button, SPMI communication error, register CRC error, BIST failure,

or thermal reaching orderly shutdown level. These warning causes the device to

trigger the PFSM to execute orderly shutdown of all digital outputs, external voltage

rails and monitors, and proceed to the Safe Recovery State.³

MISCELLANEOUS

WARNING

These interrupts provide information to the system to indicate detection of WDOG or

ESM errors, die temperature crossing thermal warning threshold, device passing BIST

test, or external sync clock availability.

STARTUP SOURCE

GPIO DETECTION

These interrupts provides information to the system on the mechanism which caused

the device to start up, which includes FSD, RTC alarm or timer interrupts, the

activation of the ENABLE pin or the nPRWON pin button detection.

These interrupts indicate the High/Rising-Edge or the Low/Falling-Edge detection at

the GPIO1 through GPIO11 pins.

FSM ERROR

INTERRUPT

These interrupts indicate the detection of an error which causes the device mission

state changes.

All interrupts are logically combined on a single output pin, nINT (active low). The host processor can read

the INT_TOP register to find the interrupt registers to find out the source of the interrupt, and write '1' to the

corresponding interrupt register bit to clear the interrupt. This mechanism ensures when a new interrupt occurs

while the nINT pin is still active, all of the corresponding interrupt register bit will retain the interrupt source

information until it is cleared by the host.

Some of the interrupts and EN_DRV status are also sent to host during SPI communication. See Section 10.5.3

for more information on SPI status signals.

Any interrupt source can be masked by setting the corresponding mask register to '1'. When an interrupt is

masked, the interrupt bit is not updated when the associated event occurs, the nINT line will not be affected, and

the event is not recorded. If an interrupt is masked after the event occurred, the interrupt register bit will reflect

the event until the bit is cleared. While the event is masked, the interrupt register bit will not be over-written when

a new event occurs.

Figure 10-15 shows the hierarchical structure of the interrupt registers according to the categories described

above. The purpose of this register structure is to reduce the number of interrupt register read cycles the host

has to perform in order to identify the source of the interrupt. Table 10-6 summarizes the trigger and the clearing

mechanism for all of the interrupt signals. More detail descriptions of each interrupt registers can be found in

Section 10.7.

3

The SEVERE ERROR and the MODERATE ERROR are handled in NVM memory but TI requires that the NVM pre-configurable finite

state machine (PFSM) settings always follow this described error handling to meet device specifications.

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INT_FSM_ERR[7:0]

READBACK

_ERR_INT

SOC_PWR

_ERR_INT

MCU_PWR

_ERR_INT

ORD_

SHUTDOWN_INT

IMM_

SHUTDOWN_INT

WD_INT

ESM_INT

COMM_ERR_INT

INT_COMM_ERR[7:0]

I2C2_ADR

_ERR_INT

I2C2_CRC

_ERR_INT

COMM_ADR

_ERR_INT

COMM_CRC

_ERR_INT

COMM_FRM

_ERR_INT

INT_READBACK_ERR[7:0]

INT_ESM[7:0]

NRSTOUT_SOC

_READBACK_INT

EN_DRV

_READBACK_INT

ESM_MCU

_RST_INT

ESM_MCU

_FAIL_INT

ESM_MCU

_PIN_INT

ESM_SOC

_RST_INT

ESM_SOC

_FAIL_INT

ESM_SOC

_PIN_INT

INT_SEVERE_ERR[7:0]

VCCA_OVP_INT

BIST_FAIL

TSD_IMM_INT

TSD_ORD_INT

BIST_PASS_INT

PFSM_ERR_INT

INT_MODERATE_ERR[7:0]

NRSTOUT

_READBACK_INT

NINT_READBACK

_INT

NPWRON_LONG

_INT

SPMI_ERR_INT

RECOV_CNT_INT

TWARN_INT

REG_CRC_ERR_INT

INT_MISC[7:0]

EXT_CLK_INT

ENABLE_INT

INT_STARTUP[7:0]

NPWRON

_START_INT

FSD_INT

RTC_INT

INT_GPIO[7:0]

GPIO1_8_INT

GPIO4_INT

GPIO11_INT

GPIO3_INT

GPIO10_INT

GPIO2_INT

GPIO9_INT

GPIO1_INT

INT_GPIO1_8[7:0]

GPIO8_INT

GPIO7_INT

GPIO6_INT

GPIO5_INT

INT_LDO_VMON[7:0]

INT_VMON[7:0]

VCCA_INT

LDO3_4_INT

LDO1_2_INT

VCCA_UV_INT

LDO3_UV_INT

LDO1_UV_INT

VCCA_OV_INT

LDO3_OV_INT

LDO1_OV_INT

INT_LDO3_4[7:0]

LDO4_ILIM_INT

LDO4_SC_INT

LDO2_SC_INT

LDO4_UV_INT

LDO2_UV_INT

LDO4_OV_INT

LDO2_OV_INT

LDO3_ILIM_INT

LDO1_ILIM_INT

LDO3_SC_INT

LDO1_SC_INT

INT_LDO1_2[7:0]

LDO2_ILIM_INT

INT_BUCK[7:0]

INT_BUCK5[7:0]

BUCK5_INT

BUCK3_4_INT

BUCK1_2_INT

BUCK5_ILIM_INT

BUCK3_ILIM_INT

BUCK1_ILIM_INT

BUCK5_SC_INT

BUCK3_SC_INT

BUCK1_SC_INT

BUCK5_UV_INT

BUCK3_UV_INT

BUCK1_UV_INT

BUCK5_OV_INT

BUCK3_OV_INT

BUCK1_OV_INT

INT_BUCK3_4[7:0]

BUCK4_ILIM_INT

BUCK4_SC_INT

BUCK2_SC_INT

BUCK4_UV_INT

BUCK2_UV_INT

BUCK4_OV_INT

BUCK2_OV_INT

INT_BUCK1_2[7:0]

BUCK2_ILIM_INT

Figure 10-15. Hierarchical Structure of Interrupt Registers

72

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Table 10-6. Summary of Interrupt Signals

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

EN_ILIM_FSM_CTR

L=1:

According to

BUCKn_GRP_SEL

and x_RAIL_TRIG

bits

EN_ILIM_FSM_CTR

L=0:

N/A

EN_ILIM_FSM_CT

RL=1:

Transition according Depends on FSM

to FSM trigger and configuration, see

interrupt

EN_ILIM_FSM_CT diagram

RL=0:

Write 1 to

BUCKn_ILIM_INT

bit

Buck regulator forward

current limit triggered

BUCKn_ILIM_INT =

1

BUCKn_ILIM_MASK

BUCKn_ILIM_STAT Interrupt is not

cleared if current

FSM transition

limit violation is

active

Interrupt only

EN_ILIM_FSM_CTR

L=1:

According to

LDOn_GRP_SEL

and x_RAIL_TRIG

bits

EN_ILIM_FSM_CTR

L=0:

N/A

EN_ILIM_FSM_CT

RL=1:

Transition according Depends on FSM

to FSM trigger and configuration, see

interrupt

EN_ILIM_FSM_CT diagram

RL=0:

Interrupt only

Write 1 to

LDOn_ILIM_INT bit

Interrupt is not

cleared if current

limit violation is

active

LDO regulator current

limit triggered

LDOn_ILIM_INT = 1 LDOn_ILIM_MASK

LDOn_ILIM_STAT

FSM transition

According to

Buck output or switch BUCKn_GRP_SEL

Regulator disable

and transition

according to FSM

Depends on FSM

configuration, see

FSM transition

Write 1 to

N/A

BUCKn_SC_INT = 1 N/A

short circuit detected

and x_RAIL_TRIG

bits

BUCKn_SC_INT bit

trigger and interrupt diagram

According to

LDOn_GRP_SEL

and x_RAIL_TRIG

bits

Regulator disable

and transition

according to FSM

Depends on FSM

configuration, see

FSM transition

LDO output short

circuit detected

Write 1 to

N/A

LDOn_SC_INT = 1

N/A

LDOn_SC_INT bit

trigger and interrupt diagram

BUCKn_RV_SEL =

1

BUCKn_RV_SEL =

1

According to

BUCKn_GRP_SEL

and x_RAIL_TRIG

bits

BUCKn_RV_SEL =

0

Regulator disable

Depends on FSM

and transition

according to FSM

trigger and interrupt

BUCKn_RV_SEL =

0

Buck output residual

voltage violation

configuration, see

FSM transition

diagram

Write 1 to

N/A

BUCKn_SC_INT = 1 N/A

BUCKn_SC_INT bit

N/A

LDOn_RV_SEL = 1 LDOn_RV_SEL = 1

According to

LDOn_GRP_SEL

and x_RAIL_TRIG

bits

Regulator disable

and transition

according to FSM

trigger and interrupt

Depends on FSM

configuration, see

FSM transition

diagram

LDO output residual

voltage violation

Write 1 to

N/A

LDOn_SC_INT = 1

N/A

LDOn_SC_INT bit

LDOn_RV_SEL = 0 LDOn_RV_SEL = 0

N/A

According to

BUCKn_GRP_SEL

and x_RAIL_TRIG

bits

Depends on FSM

configuration, see

FSM transition

diagram

Write 1 to

BUCKn_OV_INT bit

Interrupt is not

cleared if it is active

Transition according

to FSM trigger and

interrupt

Buck regulator

overvoltage

BUCKn_OV_INT = 1 BUCKn_OV_MASK

BUCKn_UV_INT = 1 BUCKn_UV_MASK

LDOn_OV_INT = 1 LDOn_OV_MASK

BUCKn_OV_STAT

According to

BUCKn_GRP_SEL

and x_RAIL_TRIG

bits

Depends on FSM

configuration, see

FSM transition

diagram

Write 1 to

Transition according

to FSM trigger and

interrupt

Buck regulator

undervoltage

BUCKn_UV_INT bit

BUCKn_UV_STAT

Interrupt is not

cleared if it is active

According to

LDOn_GRP_SEL

and x_RAIL_TRIG

bits

Depends on FSM

configuration, see

FSM transition

diagram

Write 1 to

Transition according

to FSM trigger and

interrupt

LDO regulator

overvoltage

LDOn_OV_INT bit

LDOn_OV_STAT

Interrupt is not

cleared if it is active

According to

LDOn_GRP_SEL

and x_RAIL_TRIG

bits

Depends on FSM

configuration, see

FSM transition

diagram

Write 1 to

Transition according

to FSM trigger and

interrupt

LDO regulator

undervoltage

LDOn_UV_INT bit

LDOn_UV_STAT

LDOn_UV_INT = 1

LDOn_UV_MASK

Interrupt is not

cleared if it is active

According to

VCCA_GRP_SEL

and x_RAIL_TRIG

bits

Depends on FSM

configuration, see

FSM transition

diagram

Write 1 to

VCCA input

overvoltage

monitoring

Transition according

to FSM trigger and

interrupt

VCCA_OV_INT bit

VCCA_OV_STAT

VCCA_OV_INT = 1 VCCA_OV_MASK

VCCA_UV_INT = 1 VCCA_UV_MASK

Interrupt is not

cleared if it is active

According to

VCCA_GRP_SEL

and x_RAIL_TRIG

bits

Depends on FSM

configuration, see

FSM transition

diagram

Write 1 to

VCCA input

undervoltage

monitoring

Transition according

to FSM trigger and

interrupt

VCCA_UV_INT bit

VCCA_UV_STAT

Interrupt is not

cleared if it is active

Write 1 to

TWARN_INT bit

Interrupt is

Thermal warning

N/A

Interrupt only

Not valid

TWARN_INT = 1

TWARN_MASK

TWARN_STAT

not cleared if

temperature is

above thermal

warning level

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Table 10-6. Summary of Interrupt Signals (continued)

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

Write 1 to

All regulators

disabled and Output STARTUP_DEST[1:0]

GPIOx set to low

in a sequence and

interrupt⁽¹⁾

Automatic startup to

TSD_ORD_INT bit

Interrupt is

not cleared if

temperature is

above thermal

shutdown level

ORDERLY_SHUTDO

WN

(MODERATE_ERR_I

NT)

Thermal shutdown,

orderly sequenced

state after

temperature is below

TWARN level

TSD_ORD_INT = 1 N/A

TSD_ORD_STAT

Write 1 to

TSD_IMM_INT bit

Interrupt is

not cleared if

temperature is

above thermal

shutdown level

All regulators

Automatic startup to

STARTUP_DEST[1:0]

state after

temperature is below

TWARN level

disabled with pull-

down resistors and

Output GPIOx set

to low immediately

and interrupt⁽¹⁾

IMMEDIATE_SHUTD

OWN

(SEVERE_ERR_INT)

Thermal shutdown,

immediate

TSD_IMM_INT = 1

N/A

TSD_IMM_STAT

All regulators

disabled and Output Automatic startup to

GPIOx set to low

immediately and

interrupt⁽¹⁾

ORDERLY_SHUTDO

WN

(MODERATE_ERR_I

NT)

Write 1 to

BIST_FAIL_INT bit

BIST error

STARTUP_DEST[1:0] BIST_FAIL_INT = 1 BIST_FAIL_MASK

state

N/A

All regulators

disabled and Output Automatic startup to

GPIOx set to low

immediately and

interrupt⁽¹⁾

ORDERLY_SHUTDO

WN

(MODERATE_ERR_I

NT)

Write 1 to

REG_CRC_ERR_IN

T bit

REG_CRC_ERR_IN

T = 1

Register CRC error

STARTUP_DEST[1:0]

state

REG_CRC_ERR_MASK N/A

All regulators

disabled and Output Automatic startup to

GPIOx set to low

immediately and

interrupt⁽¹⁾

ORDERLY_SHUTDO

SPMI communication WN

Write 1 to

SPMI_ERR_INT bit

STARTUP_DEST[1:0] SPMI_ERR_INT = 1 SPMI_ERR_MASK

state

N/A

error

(MODERATE_ERR_I

NT)

Write 1 to

COMM_FRM_ERR_

INT bit

COMM_FRM_ERR_ COMM_FRM_ERR_MA

Not valid

SPI frame error

N/A

Interrupt only

N/A

INT = 1⁽⁴⁾

SK

Write 1 to

COMM_CRC_ERR_

INT bit

COMM_CRC_ERR_ COMM_CRC_ERR_MA

INT = 1 SK

I2C1 or SPI CRC error N/A

Not valid

Write 1 to

COMM_ADR_ERR_

INT bit

I2C1 or SPI address

COMM_ADR_ERR_ COMM_ADR_ERR_MA

N/A

error⁽⁵⁾

INT = 1

SK

Write 1 to

I2C2_CRC_ERR_IN

T bit

I2C2_CRC_ERR_IN

T = 1

I2C2 CRC error

N/A

I2C2_CRC_ERR_MASK N/A

I2C2_ADR_ERR_MASK N/A

Write 1 to

I2C2_ADR_ERR_IN

T bit

I2C2_ADR_ERR_IN

T = 1

I2C2 address error⁽⁵⁾

Automatic startup to

STARTUP_DEST[1:0]

state. If previous

PFSM_ERR_INT is

pending, VCCA power

cycle needed for

recovery.

All regulators

disabled with pull-

down resistors and

Output GPIOx set

to low immediately

and interrupt⁽¹⁾

IMMEDIATE_SHUTD

OWN

(SEVERE_ERR_INT)

PFSM_ERR_INT =

1

Write 1 to

PFSM_ERR_INT bit

PFSM error

N/A

Write 1 to

EN_DRV pin readback

error (monitoring high N/A

and low states)

EN_DRV_READBA

CK_INT bit

Interrupt is not

cleared if it is active

Interrupt and

EN_DRV = 0

EN_DRV_READBA EN_DRV_READBACK_ EN_DRV_READBA

CK_INT = 1 MASK CK_STAT

Not valid

All regulators

Write 1 to

NINT_READBACK_I

NT bit

Interrupt is not

cleared if it is active

ORDERLY_SHUTDO disabled with pull-

WN down resistors and

(MODERATE_ERR_I Output GPIOx set

NINT pin readback

error (monitoring low

state)

Automatic startup to

STARTUP_DEST[1:0]

state

NINT_READBACK_I NINT_READBACK_MA NINT_READBACK

NT = 1 SK _STAT

NT)

to low immediately

and interrupt⁽¹⁾

All regulators

Write 1 to

NRSTOUT_READB

ACK_INT bit

Interrupt is not

cleared if it is active

ORDERLY_SHUTDO disabled with pull-

WN down resistors and

(MODERATE_ERR_I Output GPIOx set

NRSTOUT pin

readback error

(monitoring low state)

Automatic startup to

STARTUP_DEST[1:0]

state

NRSTOUT_READB NRSTOUT_READBACK NRSTOUT_READB

ACK_INT = 1 _MASK ACK_STAT

NT)

to low immediately

and interrupt⁽¹⁾

Write 1 to

NRSTOUT_SOC pin

readback error

(monitoring low state)

NRSTOUT_SOC_R

EADBACK_INT bit

Interrupt is not

NRSTOUT_SOC_R NRSTOUT_SOC_READ NRSTOUT_SOC_R

EADBACK_INT = 1 BACK_MASK EADBACK_STAT

N/A

Interrupt only

Not valid

cleared if it is active

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Table 10-6. Summary of Interrupt Signals (continued)

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

Fault detected by

SOC ESM (level

mode: low level

detected, PWM mode:

PWM signal timing

violation)

Write 1 to

ESM_SOC_PIN_IN

T bit

ESM_SOC_PIN_IN

T = 1

N/A

Interrupt only

Not valid

ESM_SOC_PIN_MASK N/A

ESM_SOC_FAIL_MASK N/A

Fault detected by

SOC ESM (level

mode: low level

longer than DELAY1

time, PWM mode:

ESM error counter >

FAIL_THR longer than

DELAY1time)

Interrupt and

EN_DRV = 0

(configurable)

Write 1 to

ESM_SOC_FAIL_IN

T bit

ESM_SOC_FAIL_IN

T = 1

N/A

Not valid

Fault detected

by SOC ESM

(level mode: low

level longer than

DELAY1+DELAY2

time, PWM mode:

ESM error counter >

FAIL_THR longer than

DELAY1+DELAY2

time)

Automatically returns

to the current

operating state after

the completion of SoC

warm reset

Interrupt, and

NRSTOUT_SOC

toggle⁽¹⁾

Write 1 to

ESM_SOC_RST_IN

T bit

ESM_SOC_RST_IN

T = 1

ESM_SOC_RST

ESM_SOC_RST_MASK N/A

Fault detected by

MCU ESM (level

mode: low level

detected, PWM mode:

PWM signal timing

violation

Write 1 to

ESM_MCU_PIN_IN

T bit

ESM_MCU_PIN_IN

T = 1

N/A

Interrupt only

Not valid

ESM_MCU_PIN_MASK N/A

ESM_MCU_FAIL_MASK N/A

Fault detected by

MCU ESM (level

mode: low level

longer than DELAY1

time, PWM mode:

ESM error counter >

FAIL_THR longer than

DELAY1 time)

Interrupt and

EN_DRV = 0

(configurable)

Write 1 to

ESM_MCU_FAIL_IN

T bit

ESM_MCU_FAIL_IN

T = 1

Fault detected

by MCU ESM

(level mode: low

level longer than

DELAY1+DELAY2

time, PWM mode:

ESM error counter >

FAIL_THR longer than

DELAY1+DELAY2

time)

Interrupt and Warm Automatically returns

Reset (EN_DRV = 0 to the current

and NRSTOUT and operating state after

Write 1 to

ESM_MCU_RST_IN

T bit

ESM_MCU_RST_IN

T = 1

ESM_MCU_RST

ESM_MCU_RST_MASK N/A

NRSTOUT_SOC

the completion of

warm reset

toggle)⁽¹⁾

External clock is

expected, but it is

not available or the

frequency is not in the

valid range

Write 1 to

EXT_CLK_INT bit

N/A

Interrupt only

Not valid

EXT_CLK_INT = 1⁽²⁾EXT_CLK_MASK

EXT_CLK_STAT

BIST completed

successfully

BIST_PASS_INT =

BIST_PASS_MASK

1

Write 1 to

BIST_PASS_INT bit

N/A

Clear interrupt and

WD_FAIL_CNT <

WD_FAIL_TH

Watchdog fail counter

above fail threshold

Interrrupt and

EN_DRV = 0

Write 1 to

WD_FAIL_INT bit

WD_FAIL_INT = 1

N/A

Interrupt and

Warm Reset if

WD_RST_EN = 1

(EN_DRV = 0

Automatically returns

to the current

operating state after

Watchdog fail counter WD_RST (if

above reset threshold WD_RST_EN = 1)

Write 1 to

WD_RST_INT bit

WD_RST_INT = 1

N/A

and NRSTOUT and the completion of

NRSTOUT_SOC

warm reset

toggle)⁽¹⁾

Interrupt and Warm Automatically returns

Reset (EN_DRV = 0 to the current

and NRSTOUT and operating state after

Write 1 to

WD_LONGWIN_TI

MEOUT_INT bit

Watchdog long

WD_RST

WD_LONGWIN_TI

MEOUT_INT = 1

N/A

window timeout

NRSTOUT_SOC

the completion of

warm reset

toggle)⁽¹⁾

Startup to

STARTUP_DEST[1:

0] state and

Write 1 to ALARM

bit

RTC alarm wake-up

RTC timer wake-up

TRIGGER_SU_x

Not valid

ALARM = 1

TIMER = 1

IT_ALARM = 0

IT_TIMER = 0

N/A

interrupt⁽¹⁾

Startup to

STARTUP_DEST[1:

0] state and

Write 1 to TIMER bit

interrupt⁽¹⁾

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Table 10-6. Summary of Interrupt Signals (continued)

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

Startup to

Write 1 to

NPWRON_START_I

NT bit

Low state in

NPWRON pin

STARTUP_DEST[1:

0] state and

NPWRON_START_I NPWRON_START_MAS

TRIGGER_SU_x

Not valid

NPWRON_IN

NT = 1

K

interrupt⁽¹⁾

All regulators

disabled and Output

GPIOx set to low

in a sequence and

interrupt⁽¹⁾

Write 1 to

NPWRON_LONG_I

NT bit

Long low state in

NPWRON pin

ORDERLY_SHUTDO

WN

Valid power-on

request

NPWRON_LONG_I NPWRON_LONG_MAS

NPWRON_IN

NT = 1

K

Transition to

TRIGGER_FORCE_ STANDBY or

Low state in ENABLE STANDBY/ LP_STANDBY

TRIGGER_FORCE_ depending on the

ENABLE pin rise

Not valid

N/A

LP_STANDBY

LP_STANDBY_SEL

bit setting⁽¹⁾

(1)

Write 1 to

ENABLE_INT bit

ENABLE pin rise

TRIGGER_SU_x

ENABLE_INT = 1

ENABLE_MASK

ENABLE_STAT

N/A

All regulators

disabled and Output Automatic startup to

Write 1 to

ORD_SHUTDOWN_

INT

Fault causing orderly

shutdown

ORDERLY_SHUTDO

WN

ORD_SHUTDOWN_ ORD_SHUTDOWN_MA

INT SK

GPIOx set to low

in a sequence and

interrupt⁽¹⁾

STARTUP_DEST[1:0]

state

All regulators

disabled with pull-

IMMEDIATE_SHUTD down resistors and

Automatic startup to

STARTUP_DEST[1:0]

state

Write 1 to

IMM_SHUTDOWN_I

NT

Fault causing

immediate shutdown

IMM_SHUTDOWN_I IMM_SHUTDOWN_MA

NT SK

N/A

OWN

Output GPIOx set

to low immediately

and interrupt⁽¹⁾

Depends on FSM

configuration, see

FSM transition

diagram

Transition according

to FSM trigger and

interrupt

Write 1 to

MCU_PWR_ERR_I

NT

Power supply error for MCU_POWER_ERR

MCU OR

MCU_PWR_ERR_I MCU_PWR_ERR_MAS

NT

N/A

K

Depends on FSM

configuration, see

FSM transition

diagram

Transition according

to FSM trigger and

interrupt

Write 1 to

SOC_PWR_ERR_I

NT

Power supply error for SOC_POWER_ERR

SOC_PWR_ERR_I SOC_PWR_ERR_MAS

SOC

OR

NT

K

All regulators

Write 1 to INT_OVP

_INT bit

Interrupt is not

cleared if VCCA

voltage is above

VCCA_OVPlevel

Automatic startup to

STARTUP_DEST[1:0]

state after VCCA

voltage is below

VCCA_OVP

disabled with pull-

down resistors and

Output GPIOx set

to low immediately

and interrupt⁽¹⁾

IMMEDIATE_SHUTD

OWN

(SEVERE_ERR_INT)

VCCA over-voltage

VCCA_OVP_INT =

1

N/A

VCCA_OVP_STAT

GPIOx_IN

(VCCA_OVP

)

According to

GPIOx_FSM_MASK Transition according

GPIOx_RISE_MASK

GPIOx_FALL_MASK

Write 1 to

GPIOx_INT bit

GPIO interrupt

and

to FSM trigger and Not valid

GPIOx_FSM_MASK_ interrupt

POL bits

GPIOx_INT = 1

Transition to

WKUP1 and

LP_WKUP1 signals

GPIOx_RISE_MASK

GPIOx_FALL_MASK

Write 1 to

GPIOx_INT bit

WKUP1

WKUP2

ACTIVE state and

Not valid

N/A

GPIOx_IN

interrupt⁽¹⁾

Transition to MCU

ONLY state and

interrupt⁽¹⁾

WKUP2 and

LP_WKUP2 signals

GPIOx_RISE_MASK

GPIOx_FALL_MASK

Write 1 to

GPIOx_INT bit

According to

NSLEEP1 and

NSLEEP2

State transition

based on NSLEEP1 Not valid

and NSLEEP2

NSLEEP1 signal,

NSLEEP1B bit

NSLEEP1_MASK

NSLEEP2_MASK

N/A

According to

NSLEEP1 and

NSLEEP2

State transition

based on NSLEEP1 Not valid

and NSLEEP2

NSLEEP2 signal,

NSLEEP2B bit

All regulators

disabled with pull-

LDOVINT over- or

undervoltage

IMMEDIATE_SHUTD

OWN

Valid LDOVINT

voltage

down resistors and

Output GPIOx set to

low immediately⁽¹⁾

N/A

All regulators

disabled with pull-

Main clock outside

valid frequency

IMMEDIATE_SHUTD

OWN

down resistors and VCCA power cycle

Output GPIOx set to

low immediately⁽¹⁾

All regulators

Recovery counter limit ORDERLY_SHUTDO disabled and Output

VCCA power cycle

VCCA voltage rising

N/A

exceeded⁽³⁾

WN

GPIOx set to low in

a sequence⁽¹⁾

VCCA supply falling

below VCCA_UVLO

IMMEDIATE_SHUTD Immediate

OWN

shutdown⁽¹⁾

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Table 10-6. Summary of Interrupt Signals (continued)

MASK FOR

INTERRUPT

CLEAR

EVENT

TRIGGER FOR FSM

RESULT ⁽¹⁾

RECOVERY

INTERRUPT BIT

LIVE STATUS BIT

Startup to

First supply detection,

VCCA supply rising

above VCCA_UVLO

STARTUP_DEST[1:

0] state and

Write 1 to FSD_INT

bit

TRIGGER_SU_x

Not valid

FSD_INT = 1

FSD_MASK

N/A

interrupt⁽¹⁾

(1) The results shown in this column are selected to meet functional safety assumptions and device specifications. The actual results

can be configured differently in NVM memory. TI recommends reviewing of the system and device funcational safety goal and

documentation before deviating from these recommendations.

(2) Interrupt is generated during clock detector operation and in case clock is not available when clock detector is enabled.

(3) This event will not occur if RECOV_CNT_THR = 0, even though RECOV_CNT will continue to accumulate and increase, and will

eventually saturate when it reaches the maximum count of 15.

(4) Due to a digital logic errata in the device, a write or read SPI command which coincide with the rising edge of the CS signal may not

cause the COMM_FRM_ERR_INT interrupt.

(5) I2C1, I2C2, or SPI address error will only occur in safety applications if the interface CRC feature is enabled, when both

I2C1_SPI_CRC_EN and I2C2_CRC_EN are set to '1'.

10.3.10 RTC

10.3.10.1 General Description

The RTC is driven by the 32-kHz oscillator and it provides the alarm and time-keeping functions.

The main functions of the RTC block are:

•

Time information (seconds, minutes, and hours) in binary-coded decimal (BCD) code

Calendar information (day, month, year, and day of the week) in BCD code up to year 2099

Configurable interrupts generation; the RTC can generate two types interrupts which can be enabled and

masked individually:

– Timer interrupts periodically (1-second, 1-minute, 1-hour, or 1-day periods)

– Alarm interrupt at a precise time of the day (alarm function)

•

Oscillator frequency calibration and time correction with 1/32768 resolution

Figure 10-16 shows the RTC block diagram.

32-kHz

clock input

32-kHz

counter

Frequency

compensation

Week days

Control

Seconds

Minutes

Hours

Days

Months

Years

Interrupt

Alarm

INT_ALARM

INT_TIMER

Figure 10-16. RTC Block Diagram

10.3.10.2 Time Calendar Registers

All the time and calendar information is available in the time calendar (TC) dedicated registers:

SECONDS_REG, MINUTES_REG, HOURS_REG, DAYS_REG, WEEKS_REG, MONTHS_REG, and

YEARS_REG. The TC register values are written in BCD code.

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•

Year data ranges from 00 to 99.

– Leap Year = Year divisible by four (2000, 2004, 2008, 2012, and so on)

– Common Year = Other years

•

Month data ranges from 01 to 12.

Day value ranges:

– 1 to 31 when months are 1, 3, 5, 7, 8, 10, 12

– 1 to 30 when months are 4, 6, 9, 11

– 1 to 29 when month is 2 and year is a leap year

– 1 to 28 when month is 2 and year is a common year

Weekday value ranges from 0 to 6.

Hour value ranges from 0 to 23 in 24-hour mode and ranges from 1 to 12 in AM or PM mode.

Minutes value ranges from 0 to 59.

•

Seconds value ranges from 0 to 59.

Example: Time is 10H54M36S PM (PM_AM mode set), 2008 September 5; previous registers values are listed

in Table 10-7:

Table 10-7. RTC Time Calendar Registers Example

REGISTER

CONTENT

RTC_SECONDS

RTC_MINTURES

RTC_HOURS

RTC_DAYS

0x36

0x54

0x10

0x05

RTC_MONTHS

RTC_YEARS

RTC_WEEKS

0x09

0x08

0x06

The user can round to the closest minute, by setting the ROUND_30S register bit in the RTC_CTRL_REG

register. TC values are set to the closest minute value at the next second. The ROUND_30S bit is automatically

cleared when the rounding time is performed.

Example:

•

If current time is 10H59M45S, round operation changes time to 11H00M00S

If current time is 10H59M29S, round operation changes time to 10H59M00S

10.3.10.2.1 TC Registers Read Access

TC register read access can be done in two ways:

•

A direct read to the TC registers. In this case, there can be a discrepancy between the final time read and

the real time because the RTC keeps running because some of the registers can toggle in between register

accesses. Software must manage the register change during the reading.

•

Read access to shadowed TC registers. These registers are at the same addresses as the normal TC

registers. They are selected by setting the GET_TIME bit in the RTC_CTRL_REG register. When this bit

is set, the content of all TC registers is transferred into shadow registers so they represent a coherent

timestamp, avoiding any possible discrepancy between them. When processing the read accesses to the

TC registers, the value of the shadowed TC registers is returned so it is completely transparent in terms of

register access.

10.3.10.2.2 TC Registers Write Access

TC registers write accesses can be done while RTC is stopped. MCU can stop the RTC by the clearing the

STOP_RTC bit of the control register and checking the RUN bit of the status to be sure that RTC is frozen. MCU

then updates the TC values and restarts the RTC by setting the STOP_RTC bit, which ensures that the final

written values are aligned with the targeted values.

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10.3.10.3 RTC Alarm

RTC alarm registers (ALARM_SECONDS_REG, ALARM_MINUTES_REG, ALARM_HOURS_REG,

ALARM_DAYS_REG, ALARM_MONTHS_REG, and ALARM_YEARS_REG) are used to set the alarm time or

date to the corresponding generated ALARM interrupts. See Section 10.3.10.2 for how these register values are

written in BCD code, with the same data range as described for the TC registers.

10.3.10.4 RTC Interrupts

The RTC supports two types of interrupts:

•

ALARM interrupt. This interrupt is generated when the configured date or time in the corresponding ALARM

registers is reached. This interrupt is enabled and disabled by setting the IT_ALARM bit. It is important to

set the IT_ALARM = 0 to disable the alarm interrupt prior to configuring the ALARM registers to prevent the

interrupt from mis-firing.

•

TIMER interrupt. This interrupt is generated when the periodic time (day, hour, minute, second) set in the

EVERY bits of the RTC_INTERRUPTS register is reached. The first of the periodic interrupt will occur when

the RTC counter reaches the next day, hour, minute, or second counter value. For example, if a timer

interrupt is set for every hour at 2:59 AM, the first interrupt will occur at 3:00 AM instead of 3:59 AM. This

interrupt is enabled and disabled by setting the IT_TIMER bit. It is important to set the IT_TIMER = 0 to

disable the timer interrupt prior to configuring the periodic time value to prevent the interrupt from mis-firing.

Both types of the RTC interrupts can be used to wake up the device from the STANDBY state or the

LP_STANDBY state when they are not masked.

10.3.10.5 RTC 32-kHz Oscillator Drift Compensation

The RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers are used to compensate for any inaccuracy

of the 32-kHz clock output from the 32-kHz crystal oscillator. To compensate for any inaccuracy, MCU must

perform an external calibration of the oscillator frequency, calculate the drift compensation needed versus one

time hour period, and load the compensation registers with the drift compensation value.

The compensation mechanism is enabled by the AUTO_COMP_EN bit in the RTC_CTRL_REG register. The

process happens after the first second of each hour. The time between second 1 to second 2 (T_ADJ) is

adjusted based on the settings of the two RTC_COMP_MSB_REG and RTC_COMP_LSB_REG registers.

These two registers form a 16-bit, 2 s complement value COMP_REG (from –32767 to 32767) that is subtracted

from the 32-kHz counter as per the following formula to adjust the length of T_ADJ: (32768 - COMP_REG) /

32768. It is therefore possible to adjust the compensation with a 1/32768-second time unit accuracy per hour

and up to 1 second per hour.

Software must ensure that these registers are updated before each compensation process (there is no hardware

protection). For example, software can load the compensation value into these registers after each hour event,

during second 0 to second 1, just before the compensation period, happening from second 1 to second 2.

It is also possible to preload the internal 32-kHz counter with the content of the RTC_COMP_MSB_REG and

RTC_COMP_LSB_REG registers when setting the SET_32_COUNTER bit in the RTC_CTRL_REG register.

This must be done when the RTC is stopped.

Figure 10-17 shows the RTC compensation scheduling.

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HOURS_REG

3

4

5

6

0

1

...

58

59

0

1

...

58

59

0

1

...

58

59

0

1

...

58

59

SECONDS_REG

HOURS_REG

SECONDS_REG

3

4

59

0

58

2

3

Compensation Value Frozen

New Compensation Value

RTC_COMP_xxx_REG

Register

Update

Compensation

Event

Figure 10-17. RTC Compensation Scheduling

10.3.11 Watchdog (WD)

The watchdog monitors the correct operation of the MCU. This watchdog requires specific messages from the

MCU in specific time intervals to detect correct operation of the MCU. The MCU can control the logic-level of the

EN_DRV pin when the watchdog detects correct operation of the MCU. When the watchdog detects an incorrect

operation of the MCU, the TPS6594-Q1 device pulls the EN_DRV pin low . This EN_DRV pin can be used in

the application as a control-signal to deactivate the power output stages, for example a motor driver, in case of

incorrect operation of the MCU.

The watchdog has two different modes which are defined as follows:

Trigger mode

In trigger mode, the MCU applies a pulse signal with a minimum pulse width of t_{WD_pulse}on

the pre-assigned GPIO input pin to send the required watchdog trigger. To select this mode,

the MCU must clear bit WD_MODE_SELECT. Section 10.3.11.6 provides more details.

Q&A (question In Q&A mode, the MCU sends watchdog answers through the I2C bus or SPI bus. To select

and

answer) this mode, the MCU must set bit WD_MODE_SELECT. Section 10.3.11.8.1 provides more

mode

details.

10.3.11.1 Watchdog Fail Counter and Status

The watchdog includes a watchdog fail counter WD_FAIL_CNT[3:0] that increments because of bad events or

decrements because of good events. Furthermore, the watchdog includes two configurable thresholds:

1. Fail-threshold (configurable through bits WD_FAIL_TH[2:0])

2. Reset-threshold (configurable through bits WD_RST_TH[2:0])

When the WD_FAIL_CNT[3:0] counter value is less than or equal to the configured Watchdog-Fail threshold

(WD_FAIL_TH[2:0]) and bit WD_FIRST_OK=1, the MCU can set the ENABLE_DRV bit when no other error-

flags are set.

When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail threshold

(WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0]), the device clears the ENABLE_DRV bit, sets the error-flag

WD_FAIL_INT, and pulls the nINT pin low.

When the WD_FAIL_CNT[3:0] counter value is greater than the configured Watchdog-Fail plus Watchdog-Reset

threshold (WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])) and the watchdog-reset function is

enabled (configuration bit WD_RST_EN=1), the device generates a WD_ERROR trigger in the state machine

and sets the error-flag WD_RST_INT, and pulls the nINT pin low.

The device clears the WD_FAIL_CNT[3:0] each time the watchdog enters the Long Window. The status bits

WD_FAIL_INT and WD_RST_INT are latched until the MCU writes a ‘1’ to these bits.

Table 10-8 gives an overview of the Watchdog Fail Counter value ranges and the corresponding device status.

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Table 10-8. Overview of Watchdog Fail Counter value ranges and corresponding device status

Watchdog Fail Counter value

Device Status

WD_FAIL_CNT[3:0]

MCU can set the ENABLE_DRV bit if WD_FIRST_OK=1 and no

WD_FAIL_CNT[3:0] ≤ WD_FAIL_TH[2:0]

other error-flags are set

WD_FAIL_TH[2:0] < WD_FAIL_CNT[3:0] ≤ (WD_FAIL_TH[2:0] +

WD_RST_TH[2:0])

The device clears the ENABLE_DRV bit, sets error-flag

WD_FAIL_INT and pulls the nINT pin low

If configuration bit WD_RST_EN=1, device generates WD_ERROR

trigger in the state machine and reacts as defined in the PFSM, sets

the error-flag WD_RST_INT, and pulls the nINT pin low. See Table

1-1 for the interrupt handling of WD_RTS.

WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] + WD_RST_TH[2:0])

The WD_FAIL_CNT[3:0] counter responds as follows:

•

When the Watchdog is in the Long-Window, the WD_FAIL_CNT[3:0] is cleared to 4’b0000

A good event decrements the WD_FAIL_CNT[3:0] by one before the start of the next Window-1

A bad event increments the WD_FAIL_CNT[3:0] by one before the start of the next Window-1

Refer to Section 10.3.11.6 and Section 10.3.11.8.1 respectively for definitions of good events and bad events.

10.3.11.2 Watchdog Start-Up and Configuration

When the device releases the nRSTOUT pin, the watchdog starts with the Long Window. This Long Window has

a time interval (t_{LONG_WINDOW}) with a default value set in bits WD_LONGWIN[7:0].

As long as the watchdog is in the Long Window, the MCU can configure the watchdog through the following

register bits:

•

WD_EN to enable or disable the watchdog

WD_LONGWIN[7:0] to increase the duration of the Long-Window time-interval

WD_MODE_SELECT to select the Watchdog mode (Trigger mode or Q&A Mode)

WD_PWRHOLD to activate the Watchdog Disable function (more detail in Section 10.3.11.4)

WD_RETURN_LONGWIN to configure wheter to return to Long-Window or continue to the next seqeunce

after the completion of the current watchdog sequence (more detail in Section 10.3.11.4)

WD_WIN1[6:0] to configure the duration of the Window-1 time-interval

WD_WIN2[6:0] to configure the duration of the Window-2 time-interval

WD_RST_EN to enable or disable the watchdog-reset function

WD_FAIL_TH[2:0] to configure the Watchdog-Fail threshold

WD_RST_TH[2:0] to configure the Watchdog-Reset threshold

WD_QA_FDBK[1:0] to configure the settings for the reference answer-generation

WD_QA_LFSR[1:0] to configure the settings for the question-generation

WD_QUESTION_SEED[3:0] to configure the starting-point for the 1st question-generation

WD_QA_CFG for watchdog in Q&A Mode

•

The device will keep the above register bit values configured by the MCU as long as the device is powered.

The MCU can configure the time interval of the Long Window (t_{LONG_WINDOW}) with the WD_LONGWIN[7:0] bits.

The WD_LONGWIN[7:0] bits are defined as:

•

0x00: 80 ms

0x01 - 0x40: 125 ms to 8 sec, in 125 ms steps

0x41 - 0xFF: 12 sec to 772 sec, in 4 sec steps

Use Equation 4 and Equation 5 to calculate the minimum and maximum values for the Long Window

(t_{LONG_WINDOW}) time interval when WD_LONGWIN[7:0] > 0x00:

t_{LONG_WINDOW_MIN}= WD_LONGWIN[7:0] × 0.95

t_{LONG_WINDOW_MAX}= WD_LONGWIN[7:0] × 1.05

(4)

(5)

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Note

If the MCU software changes the duration of the Long-Window to an interval shorter than the time in

which the watchdog has been in the Long-Window, the time-out function of the Long-Window will no

longer operate.

When the MCU clears bit WD_EN, the watchdog goes out of the Long Window and disables the watchdog.

When the watchdog is disabled in this way, the MCU can set bit WD_EN back to ‘1’ to enable the watchdog

again, and the MCU can control the ENABLE_DRV bit when no other error-flags are set. The MCU must clear bit

WD_PWRHOLD before setting bit WD_EN back to ‘1’ to start the watchdog in Long Window.

The watchdog locks the following configuration register bits when it goes out of the Long Window and starts the

first watchdog sequence:

•

WD_WIN1[6:0]

WD_WIN2[6:0]

WD_LONGWIN[7:0]

WD_MODE_SELECT

WD_QA_FDBK[1:0], WD_QA_LFSR[1:0] and WD_QUESTION_SEED[3:0]

WD_RST_EN, WD_EN, WD_FAIL_TH[2:0] and WD_RST_TH[2:0]

10.3.11.3 MCU to Watchdog Synchronization

In order to go out of the Long Window and start the first watchdog sequence, the MCU must do the following:

•

Clear bits WD_PWRHOLD (more detail in Section 10.3.11.4)

Apply a pulse signal with a minimum pulse-width t_{WD_pulse}on the pre-assigned GPIO pin in the case the

watchdog is configured for Trigger mode, or

•

Write four times to WD_ANSWER[7:0] in the case the watchdog is configured for Q&A mode

When the MCU fails to get the watchdog out of the Long Window before the configured Long

Window time interval (t_{LONG_WINDOW}) elapses, the device goes through a warm reset, and sets the

WD_LONGWIN_TIMEOUT_INT. This bit latched until the MCU writes a ‘0’ to it ‘1’ to clear it.

10.3.11.4 Watchdog Disable Function

The watchdog in the TPS6594-Q1 device has a Watchdog Disable function to prevent an unwanted MCU

reset in case the MCU is un-programmed or needs to be reprogrammed. In order to activate this Watchdog

Disable function for an un-programmed MCU, DISABLE_WDOG pin must be asserted to a logic-high level for

a time-interval longer than t_{WD_DIS}prior to the moment the device releases the nRSTOUT pin. If the Watchdog

Disable function is activated in this way, the device sets bit WD_PWRHOLD to keep the watchdog in the Long

Window. The watchdog stays in the Long Window until the MCU clears the WD_PWRHOLD bit.

In case the MCU needs to be reprogrammed while the watchdog monitors the correct operation of the MCU,

the MCU can set bit WD_RETURN_LONGWIN to put the watchdog back in the Long Window. When the MCU

set this bit, the watchdog returns to the Long Window after the current Watchdog Sequence completes. In order

to make the watchdog stay in the Long Window as long as needed the MCU can either re-configure the Long

Window (t_{LONG_WINDOW}) time interval, or set the WD_PWRHOLD bit. Once the MCU starts the first watchdog

sequence (as described in Section 10.3.11.3), the MCU must clear bit WD_RETURN_LONGWIN before the end

of the first watchdog sequence in order to continue the watchdog sequnece operation.

10.3.11.5 Watchdog Sequence

Once the watchdog is out of the Long Window, each watchdog sequence starts with a Window-1 followed by a

Window-2. The watchdog ends the current sequence and starts a next sequence when one of the events below

occurs:

•

The configured Window-2 time period elapses

The watchdog detects a pulse signal with a minimum pulse-width t_{WD_pulse}on the pre-assigned GPIO pin if

the watchdog is used in Trigger mode

•

The watchdog detects four times a write access to WD_ANSWER[7:0] in case the watchdog is used in Q&A

mode

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The MCU can configure the time periods of the Window-1 (t_WINDOW1) and Window-2 (t_WINDOW2) with the bits

WD_WIN1[6:0] and WD_WIN2[6:0] respectively, before starting the sequence.

Use Equation 6 and Equation 7 to calculate the minimum and maximum values for the t_WINDOW1time interval.

t_{WINDOW1_MIN}= (WD_WIN1[6:0] + 1) × 0.55 × 0.95 ms

t_{WINDOW1_MAX}= (WD_WIN1[6:0] + 1) × 0.55 × 1.05 ms

(6)

(7)

Use Equation 8 and Equation 9 to calculate the minimum and maximum values for the t_WINDOW-2time interval.

t_{WINDOW2_MIN}= (WD_WIN2[6:0] + 1) × 0.55 × 0.95 ms

t_{WINDOW2_MAX}= (WD_WIN2[6:0] + 1) × 0.55 × 1.05 ms

10.3.11.6 Watchdog Trigger Mode

(8)

(9)

When the TPS6594-Q1 device is configured to use the Watchdog Trigger Mode, the watchdog receives the

watchdog-triggers from the MCU on the pre-assigned GPIO pin. A rising edge on this GPIO pin, followed by a

stable logic-high level on that pin for more than the maximum pulse time, t_{WD_pulse(max)}, is a watchdog-trigger.

The watchdog uses a deglitch filter with a t_{WD_pulse}filter time and an internal system clock to create the

internally-generated trigger pulse from the watchdog-trigger on the pre-assigned GPIO pin.

The watchdog detects a good event when the watchdog-trigger comes in Window-2. The rising edge of the

watchdog-trigger on the pre-assigned GPIO pin must occur for at least the t_{WD_pulse}time before the end of

Window-2 to generate such a good event.

The watchdog detects a bad event when one of the following events occurs:

•

The watchdog-trigger comes in Window-1. The rising edge of the watchdog-trigger on the pre-assigned GPIO

pin must occur for at least the t_{WD_pulse}time before the end of Window-1 to generate such a bad event. In

case of this bad event, the device sets bits WD_TRIG_EARLY and WD_BAD_EVENT.

No watchdog-trigger comes in Window-2. In case of this bad event (also referred to as time-out event), the

device sets bits WD_TIMEOUT and WD_BAD_EVENT.

•

Please consider that the minimum WD-pulse duration needs to meet the maximum deglitch time t_{WD_pulse (max)}

.

The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of

the watchdog-sequence.

Figure 10-18 shows the flow-chart of the watchdog in Trigger mode.

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10.3.11.7 WatchDog Flow Chart and Timing Diagrams in Trigger Mode

NO SUPPLY

Device sets WD_RST_EN=1 per default

Device sets WD_EN=1 per default.

Wake-up

NO

request?

YES

Device sets

WD_PWRHOLD bit

DISABLE_WDOG

hardware condition

applied?

YES

NO

RESTART

from all

states except

NO SUPPLY

Reset-Extension

time-interval

elapsed?

NO

YES

WD_RETURN_

LONGWIN=1?

YES

WATCHDOG LONG WINDOW

NO

- MCU reset inactive

- Device forces ENABLE_DRV= 0

- MCU clears error-flags

- Device releases nINT pin if no other error-flags are set

- Device unlocks Watchdog-Configuration registers

- Device sets WD_FAIL_CNT[3:0]=4'b0000 and sets WD_FIRST_OK=0

MCU either clears WD_EN, or:

WINDOW-1

1) MCU configures watchdog in Trigger mode

2) MCU configures Window-1 and Window-2 time-intervals

3) MCU configures WD_FAIL_TH, WD_RST_TH and WD_RST_EN

4) MCU sends trigger pulse

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not change

ENABLE_DRV bit

- Device waits until WINDOW-1 time elapses

NO

- Device sets

WD_TRG_EARLY

error-flag

- Device sets

WD_BAD_EVENT

error-flag

Device has

Received trigger-

NO

WD_PWRHOLD=0?

YES

WINDOW-1

NO

YES

time-interval

elapsed?

pulse

?

YES

WD_EN=0?

YES

NO

WINDOW-2

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

YES

- MCU sends trigger-pulse

NO

NORMAL t NO Watchdog

- MCU reset inactive

- MCU can set

ENABLE_DRV=1 if no other

error-flags are set

NO

WD_EN=0?

Device sets

WD_TIMEOUT error-

flag

Device has

Received trigger-

WINDOW-2

time-interval

elapsed?

YES

NO

Device clears

WD_BAD_EVENT

error-flag

- Device sets

WD_BAD_EVENT

error-flag

pulse

?

- Interrupt inactive if no

other error-flag set

YES

- Device decrements WD_FAIL_CNT

- Device sets WD_FIRST_OK=1

- MCU can set ENABLE_DRV=1 if no other error-flags are set

Device locks all Watchdog

configuration registers and bits,

except WD_RETURN_LONGWIN bit

Device has

received trigger

pulse?

YES

NO

Device Increments WD_FAIL_CNT[3:0]

MCU configred LONG-WINDOW

time-interval shorter than time in which

Wathcdog has been in the

YES

Long-Window?

NO

WD_FAIL_CNT[3:0] >

WD_FAIL_TH

[2:0]

NO

LONG-WINDOW

time-interval

elapsed?

NO

YES

- Device forces ENABLE_DRV=0

- Device sets WD_FAIL_INT

error-flag

YES

- Interrupt active

Device sets

WD_LONGWIN_TIMEOUT

error-flag

- Device sets WD_RST_INT

error-flag

- Interrupt active

- Device clears

WD_BAD_EVENT error-flag

WD_FAIL_CNT[3:0] >

(WD_FAIL_TH[2:0] +

WD_RST_TH[2:0])

&

WATCHDOG-RESET

-WD_RST trigger to FSM

YES

NO

WD_RST_EN=1

Figure 10-18. Flow Chart for WatchDog Monitor in Trigger Mode

Figure 10-19, Figure 10-20, Figure 10-21, Figure 10-22, and Figure 10-23 give examples of watchdog is trigger

mode with good and bad events after device startup.

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RESET Extension Time

nRSTOUT

(Reset to MCU, controlled by

internal RSTOUT-control signal

t > t_{WD_pulse}

Watchdog-Trigger

onGPIOpin

t_{WD_pulse}

InternallyGenerated

TriggerPulse

tt <

t_WINDOW-2

tt < t_{LONG_WINDOW}

t

tt = t_WINDOW-1

t

tt < t_WINDOW-2

t

tt = t_WINDOW-1

t

Window-1

Watchdog Windows

WD_FAIL_CNT[3:0]

LongWindow

Window-1

Window-2

Window-1

Window-2

xxxx

0000

x

0

1

WD_FIRST_OK

MCU clears watchdog error-flags

WD_FAIL_INT

WD_RST_INT

x

0

x

WD_LONGWIN_TIMEOUT

_INT

WD_TRIG_EARLY

WD_TIMEOUT

0

x

MCU sets ENABLE_DRV (only possible when

FIRST_WD_OK=1)

1

x

0

ENABLE_DRV

Device State

ACTIVE or MCU_ONLY

x

000

RECOV_CNT[2:0]

Figure 10-19. Watchdog in Trigger mode – Normal MCU Startup with Correct Watchdog-Triggers

RESET Extension Time

nRSTOUT

(Reset to MCU)

Watchdog-Triggeron

GPIOpin

InternallyGenerated

TriggerPulse

tt = t_{LONG_WINDOW}

t

tt = t_{LONG_WINDOW}

t

Watchdog Windows

WD_FAIL_CNT[3:0]

LongWindow

0000

xxxx

x

0000

0

0000

0

WD_FIRST_OK

MCU clears watchdog error-flags

x

0

WD_FAIL_INT

WD_RST_INT

x

WD_LONGWIN_

TIMEOUT_INT

0

1

WD_TRG_EARLY

WD_TIMEOUT

x

0

x

ENABLE_DRV

0

ACTIVE or MCU_ONLY

(same state as previously)

ACTIVE or MCU_ONLY

(same state as previously)

x

ACTIVE or MCU_ONLY

Warm Reset

SHUTDOWN

Device State

RECOV_CNT[2:0]

000

001

010

…

110

111

000

Figure 10-20. Watchdog in Trigger Mode – MCU Does Not Send Watchdog-Triggers After Startup

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RESET Extension

Time

RESET Extension Time

nRSTOUT

(Reset to MCU)

t > t_{WD_pulse}

Watchdog-Trigger

onGPIOpin

t_{WD_pulse}

InternallyGenerated

TriggerPulse

tt < t_{LONG_WINDOW}

t

tt < t_WINDOW-1

t

tt = t_WINDOW-1

t

tt < t_WINDOW-2

t

tt < t_WINDOW-1

t

Watchdog

Windows

Long

Window

LongWindow

Window-1

Window-2

Window-1

WD_FAIL_CNT[3:0]

xxxx

0000

0001

0010

0000

WD_FAIL_TH[2:0]=000

WD_RST_TH[2:0]=001

WD_FAIL_CNT

> WD_FAIL_TH

WD_FAIL_CNT >

WD_FAIL_TH + WD_RST_TH

x

0

1

0

WD_FIRST_OK

WD_FAIL_INT

WD_RST_INT

MCU clears watchdog error-flags

1

x

0

1

0

WD_LONGWIN

_TIMEOUT_INT

x

1

WD_TRG_EARLY

WD_TIMEOUT

0

MCU sets ENABLE_DRV (only possible when

FIRST_WD_OK=1)

x

1

0

ENABLE_DRV

Device State

0

Warm

Reset

ACTIVE or MCU_ONLY

(same state as previously)

x

ACTIVE or MCU_ONLY

001

RECOV_CNT[2:0]

000

Figure 10-21. Watchdog in Trigger Mode – Bad Event (Watchdog-Triggers in Window-1) After Startup

RESET

Extension Time

RESET Extension Time

nRSTOUT

(Reset to MCU)

t > t_{WD_pulse}

t < t_{WD_pulse}

Watchdog-Trigger

onGPIOpin

t_{WD_pulse}

InternallyGenerated

TriggerPulse

tt < t_{LONG_WINDOW}

t

tt = t_WINDOW-1

t

tt < t_WINDOW-2

t

tt = t_WINDOW-1

t

tt = t_WINDOW-2

t

tt = t_WINDOW-1

t

tt = t_WINDOW-2

t

LongWindow

Window-1

Window-2

Window-1

Window-2

Window-1

Window-2

Watchdog Windows

WD_FAIL_CNT[3:0]

LongWindow

0000

xxxx

0000

0001

WD_FAIL_CNT > WD_FAIL_TH

0010

WD_FAIL_TH[2:0]=000

WD_RST_TH[2:0]=001

WD_FAIL_CNT >

WD_FAIL_TH + WD_RST_TH

x

0

1

0

FIRST_WD_OK

MCU clears watchdog error-flags

WD_FAIL_INT

WD_RST_INT

1

x

0

1

WD_LONGWIN_

TIMEOUT_INT

x

0

x

WD_TRIG_EARLY

WD_TIMEOUT

0

1

MCU sets ENABLE_DRV (only possible when FIRST_WD_OK=1)

x

1

0

ENABLE_DRV

Device State

0

Warm

ACTIVE or MCU_ONLY

(same state as previously)

ACTIVE or MCU_ONLY

Reset

001

RECOV_CNT[2:0]

000

Figure 10-22. Watchdog in Trigger Mode – Bad Events (Too Short or no Trigger in Window-2) After

Startup

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RESET Extension Time

nRSTOUT

(Reset to MCU)

t > t_{WD_pulse}

t < t_{WD_pulse}

t > t_{WD_pulse}

Watchdog-Trigger

onGPIOpin

t_{WD_pulse}

InternallyGenerated

TriggerPulse

tt <

t_{LONG_WINDOW}

t

tt <

t_WINDOW-2

tt <

t_WINDOW-2

tt <

t_WINDOW-2

tt = t_WINDOW-1

t

tt = t_WINDOW-1

t

tt = t_WINDOW-2

t

tt = t_WINDOW-1

t

tt = t_WINDOW-1

t

LongWindow

Window-1

Window-2

Window-1

Window-2

Window-1

Window-2

Window-1

Window-2

Watchdog Windows

WD_FAIL_CNT[3:0]

WD_FAIL_TH[2:0]=000

WD_RST_TH[2:0]=001

00

xxxx

0000

0001

0000

WD_FAIL_CNT > WD_FAIL_TH

x

0

1

FIRST_WD_OK

MCU clears WD_FAIL_TH error-flag (only

possible when WD_FAIL_CNT =< WD_FAIL_TH)

MCU clears watchdog error-flags

WD_FAIL_INT

WD_RST_INT

x

1

0

WD_LONGWIN_

TIMEOUT_INT

x

0

x

WD_TRIG_EARLY

WD_TIMEOUT

0

MCU sets ENABLE_DRV (only possible when

FIRST_WD_OK=1)

MCU sets ENABLE_DRV (only possible when

FIRST_WD_OK=1)

x

1

ENABLE_DRV

0

ACTIVE or MCU_ONLY

x

Device State

000

RECOV_CNT[2:0]

Figure 10-23. Watchdog in Trigger Mode – Good Events (Correct Watchdog-Triggers) After Startup,

Followed by a Bad-Event (No Watchdog-Trigger in Window-2) and After That Followed by a Good Event.

10.3.11.8 Watchdog Question-Answer Mode

When the TPS6594-Q1 device is configured to use the Watchdog Question Answer mode, the watchdog

requires specific messages from the MCU in specific time intervals to detect correct operation of the MCU.

The device provides a question for the MCU in WD_QUESTION[3:0] during operation. The MCU performs a

fixed series of arithmetic operations on this question to calculate the required 32-bit answer. This answer is split

into four answer bytes: Answer-3, Answer-2, Answer-1, and Answer-0. The MCU writes these answer bytes

one byte at a time into WD_ANSWER[7:0] from the SPI or the dedicated I²C2 interface, mapped to GPIO1 and

GPIO2 pins.

A good event occurs when the MCU sends the correct answer-bytes calculated for the current question in the

correct watchdog window and in the correct sequence.

A bad event occurs when one of the events that follows occur:

•

The MCU sends the correct answer-bytes, but not in the correct watchdog window.

The MCU sends incorrect answer-bytes.

The MCU returns correct answer-bytes, but in the incorrect sequence.

If the MCU stops providing answer-bytes for the duration of the watchdog time-period, the watchdog detects

a time-out event. This time-out event sets the WD_TIMEOUT status bit, increments the WD_FAIL_CNT[3:0]

counter, and starts a new watchdog sequence.

10.3.11.8.1 Watchdog Q&A Related Definitions

A question and answer are defined as follows:

Question A question is a 4-bit word (see Section 10.3.11.8.2).

The watchdog provides the question to the MCU when the MCU reads the WD_QUESTION[3:0] bits.

The MCU can request each new question at the start of the watchdog sequence, but this is

not required to calculate the answer. The MCU can also have a software implementation, which

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generates the question according the circuit shown in Figure 10-26. Nevertheless, the answer and

therefore the answer-bytes are always based on the question generated inside the watchdog of the

device. So, if the MCU generates an incorrect question and gives answer-bytes calculated from this

incorrect question, the watchdog detects a bad event

Answer An answer is a 32-bit word that is split into four answer bytes: Answer-3, Answer-2, Answer-1, and

Answer-0.

The watchdog receives an answer-byte when the MCU writes to the WD_ANSWER[7:0] bits. For

each question, the watchdog requires four correct answer-bytes from the MCU in the correct timing

and order (Answer-3, Answer-2, and Answer-1 in Window 1 in the correct sequence, and Answer-0

in Window 2) to detect a good event.

The watchdog sequence in Q&A mode ends after the MCU writes the fourth answer byte (Answer-0), or after a

time-out event when the Window-2 time-interval elapses.

Window-1

t = t_WINDOW-1

Window-2

t = t_WINDOW-2

Three correct answer-bytes must be provided in Window-1 and

in the correct order:

The fourth answer-byte, Answer-0, must be provided

in Window-2.

ñ

Answer-3

Answer-2

Answer-1

After the MCU writes the fourth Answer-0 to

WD_ANSWER[7:0], the Watchdog generates the

next question within 1 Internal System Clock Cycle,

after which the next Watchdog Sequence

(Q&A [n + 1]) begins

After the Window-1 time elapses, Window 2 begins.

The MCU needs to write the answer-bytes to the WD_ANSWER[7:0] bits.

Question

Answer

MCU reads question⁽¹⁾

MCU provides answer⁽²⁾

Write to

WD_ANSWER[7:0]

-> Answer-1

Read bits WD_

QUESTION[3:0]

Write to

WD_ANSWER[7:0]

-> Answer-0

WD_ANSWER[7:0] WD_ANSWER[7:0]

-> Answer-3

I2C2/SPI

Commands

-> Answer-2

NCS Pin (for

SPI only)

1 Internal System Clock Cycle

to Generate a new question for the next watchdog

sequence Q&A [n + 1]

Q&A [n]

Q&A [n + 1]

Watchdog Sequence

(1) The MCU is not required to read the question. The MCU can give correct answer-bytes Answer-3, Answer-2, Answer-1 as soon as

Window-1 starts. The next watchdog sequence always starts in 1 system clock cycle after the watchdog receives the final Answer-0.

(2) The MCU can put other I²C or SPI commands in-between the write-commands to WD_ANSWER[7:0] (even re-requesting the

question). This has no influence on the detection of a good event, as long as the three correct answer-bytes in Window-1 are in the

correct sequence, and the fourth correct answer-byte is provided before the configured Window-2 time-interval elapses.

Figure 10-24. Watchdog Sequence in Q&A Mode

10.3.11.8.2 Question Generation

The watchdog uses a 4-bit question counter (QST_CNT[3:0] bits in Figure 10-25), and a 4-bit Markov chain

to generate a 4-bit question. The MCU can read this question in the WD_QUESTION[3:0] bits. The watchdog

generates a new question when the question counter increments, which only occurs when the watchdog detects

a good event. The watchdog does not generate a new question when it detects a bad event or a time-out event.

The question-counter provides a clock pulse to the Markov chain when it transitions from 4’b1111 to 4’b0000.

The question counter and the Markov chain are set to the default value of 4’b0000 when the watchdog goes out

of the Long Window.

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Note

The Question-Generator is only re-initialized (starting with question 0000) at device power-up. In

following situations, the MCU software needs to read the current question in order to synchronize with

the Question-Generator:

•

After MCU re-boot from a warm-reset

After MCU software sets bit WD_RETURN_LONGWIN=1 to put the Watchdog back into Long

Window

•

After MCU wrote WD_EN=0, then reenable Watchdog again with WD_EN=1

Figure 10-25 shows the logic combination for the WD_QUESTION[3:0] generation.

Figure 10-26 shows how the logic combination of the question-counter with the WD_ANSW_CNT[1:0] status bits

generates the reference answer-bytes.

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4-Bit LFSR Polynomial Equation⁽¹⁾

WD_QA_LFSR[1:0] = 0x00:

WD_QA_LFSR[1:0] = 0x01:

WD_QA_LFSR[1:0] = 0x10:

WD_QA_LFSR[1:0] = 0x11:

y = x4 + x3 + 1 (Default Value)

y = x4 + x2 + 1

y = x3 + x2 + 1

y = x4 + x3 + x2 +1

x3

x1

x2

x4

Bit 0

Bit 3

Bit 1

Bit 2

4-bit SEED Value Loaded when the device goes to the RESET state

(Configurable Through WD_QUESTION_SEED[3:0])

(Default Value 4'b1010)

x1

1

0

1

0

1

0

1

0

1

x2

0

1

0

1

0

1

0

1

0

x3

1

0

1

0

1

0

1

0

1

x4

0

1

0

1

0

1

0

1

0

x2

x1

x4

x3

00

01

10

11

WD_QUESTION[0]

SEED

1

QST_CNT[1]

QST_CNT[0]

QST_CNT[3]

QST_CNT[2]

00

01

10

11

2

3

4

x4

x3

x2

x1

00

01

10

11

5

WD_QUESTION[1]

6

7

QST_CNT[3]

QST_CNT[2]

QST_CNT[1]

QST_CNT[0]

00

01

10

11

8

9

10

11

12

13

14

15

00

01

10

11

x1

x4

x3

x2

WD_QUESTION[2]

00

01

10

11

QST_CNT[0]

QST_CNT[3]

QST_CNT[2]

QST_CNT[1]

The default question-sequence order with the default

WD_QUESTION_SEED[3:0] and WD_QA_LFSR[1:0] values

x3

x2

x1

x4

00

01

10

11

WD_QUESTION[3]

”Question‘ Counter

CNT [0]

QST_CNT[0]

QST_CNT[1]

QST_CNT[2]

QST_CNT[3]

QST_CNT[2]

QST_CNT[1]

QST_CNT[0]

QST_CNT[3]

00

01

10

11

CNT [1]

—good event“

INCR + 1

trigger

CNT [2]

CNT [3]

Feedback settings are controllable through the bits

WD_QA_FDBK[1:0]

(Default value is 2'b00; the selected signals are in red)

(1) If current, the y value is 0000, the next y value will be 0001, and any further question generation begins from this value.

Figure 10-25. Watchdog Question Generation

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WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[0]

X = 3, 2,1, 0

WD_ANSW_CNT[1]

WD_QUESTION[3]

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

00

01

10

11

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[1]

X = 3, 2,1, 0

WD_QUESTION[2]

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[3]

00

01

10

11

WD_QUESTION[1]

WD_ANSW_CNT[1]

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[2]

X = 3, 2,1, 0

WD_QUESTION[3]

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

00

01

10

11

WD_QUESTION[1]

WD_ANSW_CNT[1]

WD_QUESTION[2]

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[3]

X = 3, 2,1, 0

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

WD_QUESTION[3]

WD_ANSW_CNT[1]

WD_QUESTION[1]

WD_QUESTION[0]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[4]

X = 3, 2,1, 0

WD_ANSW_CNT[0]

WD_QUESTION[3]

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

00

01

10

11

Reference-Answer-X[5]

X = 3, 2,1, 0

WD_ANSW_CNT[0]

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

WD_QUESTION[3]

00

01

10

11

Reference-Answer-X[6]

X = 3, 2,1, 0

WD_ANSW_CNT[0]

WD_QUESTION[2]

WD_QUESTION[0]

WD_QUESTION[1]

WD_QUESTION[2]

00

01

10

11

Reference-Answer-X[7]

X = 3, 2,1, 0

WD_ANSW_CNT[0]

Feedback settings are controllable through the bits WD_QA_FDBK[1:0]

(Default value is 2'b00; the selected signals are in red)

Calculated Reference-Answer-X byte

Figure 10-26. Watchdog Reference Answer Calculation

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10.3.11.8.3 Answer Comparison

The 2-bit, watchdog-answer counter, WD_ANSW_CNT[1:0], counts the number of received answer-bytes and

controls the generation of the reference answer-byte as shown in Figure 10-26. At the start of each watchdog

sequence, the default value of the WD_ANSW_CNT[1:0] counter is 2’b11 to indicate that the watchdog expects

the MCU to write the correct Answer-3 in WD_ANSWER[7:0].

The device sets the WD_ANSW_ERR status bit as soon as one answer byte is not correct. The device clears

this status bit only if the MCU writes a ‘1’ to this bit.

10.3.11.8.3.1 Sequence of the 2-bit Watchdog Answer Counter

The sequence of the 2-bit, watchdog answer-counter is as follows for each counter value:

•

WD_ANSW_CNT[1:0] = 2‘b11:

1. The watchdog calculates the reference Answer-3.

2. A write access occurs. The MCU writes the Answer-3 byte in WD_ANSWER[7:0].

3. The watchdog compares the reference Answer-3 with the Answer-3 byte in WD_ANSWER[7:0].

4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘10 and sets the WD_ANSW_ERR status

bit to 1 if the Answer-3 byte was incorrect.

WD_ANSW_CNT[1:0] = 2b‘10:

1. The watchdog calculates the reference Answer-2.

2. A write access occurs. The MCU writes the Answer-2 byte in WD_ANSWER[7:0].

3. The watchdog compares the reference Answer-2 with the Answer-2 byte in WD_ANSWER[7:0]..

4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘01 and sets the WD_ANSW_ERR status

bit to 1 if the Answer-2 byte was incorrect.

WD_ANSW_CNT[1:0] = 2b‘01:

1. The watchdog calculates the reference Answer-1.

2. A write access occurs. The MCU writes the Answer-1 byte in WD_ANSWER[7:0].

3. The watchdog compares the reference Answer-1 with the Answer-1 byte in WD_ANSWER[7:0]..

4. The watchdog decrements the WD_ANSW_CNT[1:0] bits to 2b‘00 and sets the WD_ANSW_ERR status

bit to 1 if the Answer-1 byte was incorrect.

WD_ANSW_CNT[1:0] = 2b‘00:

1. The watchdog calculates the reference Answer-0.

2. A write access occurs. The MCU writes the Answer-0 byte in WD_ANSWER[7:0].

3. The watchdog compares the reference Answer-0 with the Answer-0 byte in WD_ANSWER[7:0].

4. The watchdog sets the WD_ANSW_ERR status bit to 1 if the Answer-0 byte was incorrect.

5. The watchdog starts a new watchdog sequence and sets the WD_ANSW_CNT[1:0] to 2‘b11’.

The MCU needs to clear the bit by writing a '1' to the WD_ANSW_ERR bit.

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Table 10-9. Set of Questions and Corresponding Answer-Bytes Using the Default Setting of WD_QA_CFG

Register

ANSWER-BYTES (EACH BYTE TO BE WRITTEN INTO WD_ANSWER[7:0])

WD QUESTION

ANSWER-3

ANSWER-2

ANSWER-1

ANSWER-0

WD_ANSW_CNT [1:0] =

2’b11

WD_ANSW_CNT [1:0] =

2’b10

WD_ANSW_CNT [1:0] =

2’b01

WD_ANSW_CNT [1:0] =

2’b00

WD_QUESTION[3:0]

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

0x8

0x9

0xA

0xB

0xC

0xD

0xE

0xF

FF

B0

E9

A6

75

3A

63

2C

D2

9D

C4

8B

58

17

4E

01

0F

40

19

56

85

CA

93

DC

22

6D

34

7B

A8

E7

BE

F1

F0

BF

E6

A9

7A

35

6C

23

DD

92

CB

84

57

18

41

0E

00

4F

16

59

8A

C5

9C

D3

2D

62

3B

74

A7

E8

B1

FE

10.3.11.8.3.2 Watchdog Sequence Events and Status Updates

The watchdog sequence events are as follows for the different scenarios listed:

•

A good event occurs when all answer bytes are correct in value and timing. After such a good event,

following events will occur:

1. The WD_FAIL_CNT[2:0] counter decrements by one at the end of the watchdog-sequence.

2. The question-counter increments by one and the watchdog generates a new question.

A bad event occurs when all answer-bytes are correct in value but not in correct timing. After such a bad

event, following events will occur:

•

1. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before

watchdog has received Answer-3, Answer-2 and Answer-1.

2. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answers

in Window-1.

3. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.

4. The question-counter does not change, and hence the watchdog does not generate a new question.

A bad event occurs when one or more of the answer-bytes are not correct in value but in correct timing. After

such a bad event, following events will occur:

1. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an

incorrect answer-byte.

2. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.

3. The question-counter does not change, and hence the watchdog does not generate a new question.

A bad event occurs when one or more of the answer-bytes are not correct in value and not in correct timing.

After such a bad event, following events will occur:

•

1. The WD_ANSW_ERR and WD_BAD_EVENT status bits are set as soon as the watchdog detects an

incorrect answer-byte.

2. The WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before

watchdog has received Answer-3, Answer-2 and Answer-1.

3. The WD_ANSW_EARLY and WD_BAD_EVENT status bits are set if watchdog receives all four answer-

bytes in Window-1.

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4. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.

5. The question-counter does not change, and hence the watchdog does not generate a new question.

A time-out event occurs when the device receives less than 4 answer-bytes before Window-2 time-interval

elapses. After a time-out event occurs, following events will occur:

•

1. WD_SEQ_ERR and WD_BAD_EVENT status bits are set if Window-1 time-interval elapses before

watchdog has received Answer-3, Answer-2 and Answer-1.

2. The WD_TIMEOUT and WD_BAD_EVENT status bits are set at the end of the watchdog-sequence.

3. The WD_FAIL_CNT[2:0] counter increments by one at the end of the watchdog-sequence.

4. The question-counter does not change, and hence the watchdog does not generate a new question.

The status bit WD_BAD_EVENT is read-only. The watchdog clears the WD_BAD_EVENT status bit at the end of

the watchdog-sequence.

The status bits WD_SEQ_ERR, WD_ANSW_EARLY, and WD_TIMEOUT are latched until the MCU writes a ‘1’

to these bits. If one or more of these status bits are set, the watchdog can still detect a good event in the next

watchdog-sequence. These status bits are read-only. The watchdog clears the WD_BAD_EVENT status bit at

the end of the watchdog-sequence.

Note

The WD_FIRST_OK bit is set after receiving 4 answers in the correct time frames, regardless of the

correctness of the answers. In order to not clear the bit in case of incorrect answers, the following

procedure is recommended:

•

When WD_FIRST_OK bit is set, the MCU shall read the WD_FAIL_CNT (address 0x40).

If WD_FAIL_CNT is zero, the MCU shall clear the WD_FIRST_OK bit.

If WD_FAIL_CNT is not zero, the MCU shall continue sending frames until WD_FAIL_CNT

decrements before clearing WD_FIRST_OK.

Figure 10-27 shows the flow-chart of the watchdog in Q&A mode.

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NO SUPPLY

WD_RETURN_

LONGWIN=1?

YES

Device sets WD_RST_EN=1 per default

Device sets WD_EN=1 per default.

Wake-up

request?

NO

ANSWER-3

YES

- Device sets WD_ANSW_CNT[2:0]=2'b11

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

Device sets

WD_PWRHOLD bit

DISABLE_WDOG

hardware condition

applied?

NO

YES

- MCU sends ANSWER-3

- Device sets

WD_SEQ_ERR

error-flag

NO

Device has

WINDOW-1

- Device sets

WD_BAD

_EVENT

WINDOW-2

time-interval

elapsed?

YES

NO

received

time-interval

elapsed?

ANSWER-3 ?

error-flag

RESTART

from all

states except

NO SUPPLY

YES

Reset-Extension

time-interval

elapsed?

NO

YES

- Device sets

WD_ANSW_ERR error-flag

- Device sets

ANSWER-3

correct?

NO

YES

WD_BAD_EVENT error-flag

YES

ANSWER-2

WATCHDOG LONG WINDOW

- Device sets WD_ANSW_CNT[2:0]=2'b10

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

- Device releases MCU reset pin

- Device forces ENABLE_DRV= 0

- MCU clears error-flags

NO

- Device releases nINT pin if no other error-flags are set

- Device unlocks Watchdog-Configuration registers

- Device sets WD_ANSW_CNT[2:0]=2'b11

- Device sets WD_FAIL_CNT[3:0]=4'b0000 and sets WD_FIRST_OK=0

MCU either clears WD_EN, or:

1) MCU configures watchdog in Q&A mode

2) MCU configures Window-1 and Window-2 time-intervals

3) MCU configures WD_FAIL_TH, WD_RST_TH and WD_RST_EN

4) MCU sends 4 answers

NO

- MCU sends ANSWER-2

- Device sets

WD_SEQ_ERR

error-flag

- Device sets

WD_BAD

_EVENT

Device has

received

WINDOW-2

time-interval

elapsed?

WINDOW-1

time-interval

elapsed?

NO

YES

ANSWER-2?

YES

error-flag

YES

- Device sets

ANSWER-2

correct?

WD_ANSW_ERR error-flag

- Device sets

WD_BAD_EVENT error-flag

NO

WD_PWRHOLD=0?

YES

ANSWER-1

- Device sets WD_ANSW_CNT[2:0]=2'b01

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

WD_EN=0?

YES

NO

- MCU sends ANSWER-1

- Device sets

WD_SEQ_ERR

error-flag

- Device sets

WD_BAD

_EVENT

YES

Device has

WINDOW-2

time-interval

elapsed?

WINDOW-1

time-interval

elapsed?

NORMAL t NO Watchdog

- MCU reset inactive

- MCU can set

ENABLE_DRV=1 if no other

error-flags are set

YES

NO

received

NO

WD_EN=0?

ANSWER-1?

error-flag

YES

- Device released nINT pin if

no other error-flag set

YES

- Device sets

WD_ANSW_ERR error-flag

- -Device sets

NO

ANSWER-1

correct?

WD_BAD_EVENT error-flag

YES

Device generates 1^st

QUESTION

Device has

received 4

answers ?

YES

ANSWER-0

- Device locks all Watchdog

configuration registers and

bits, except

- Device sets WD_ANSW_CNT[2:0]=2'b00

- If FIRST_WD_OK=0, device forces

ENABLE_DRV=0, else device does not

change ENABLE_DRV bit

WD_RETURN_LONGWIN bit

NO

- MCU sends ANSWER-0

Device sets

WD_TIMEOUT

error-flag

- Device sets

WD_BAD_EVENT

error-flag

MCU configred

LONG-WINDOW

time-interval shorter than

time in which Wathcdog has

been in the

Device has

received

ANSWER-0?

WINDOW-2

time-interval

elapsed?

YES

NO

Device

Increments

WD_FAIL_CNT

[3:0]

YES

Long-Window?

Device sets

WD_ANSW_EARLY error-flag

- Device sets

WINDOW-1

time-interval

not elapsed?

NO

YES

WD_FAIL_CNT[3:0] >

WD_FAIL_TH

[2:0]

NO

WD_BAD_EVENT error-flag

LONG-WINDOW

time-interval

elapsed?

NO

YES

- Device sets

Device clears

WD_BAD_EVENT

error-flag

WD_ANSW_ERR error-flag

- Device sets

WD_BAD_EVENT error-flag

NO

ANSWER-0

correct?

YES

- Device forces ENABLE_DRV=0

- Device sets WD_FAIL_INT

error-flag

Device sets

YES

- Interrupt active

WD_LONGWIN_TIMEOUT

error-flag

YES

WD_BAD_EVENT

=1?

WATCHDOG-RESET

-WD_RST trigger to FSM

NO

WD_FAIL_CNT[3:0] >

(WD_FAIL_TH[2:0] +

WD_RST_TH[2:0])

&

- Device sets WD_RST_INT

error-flag

- Interrupt active

- Device clears

WD_BAD_EVENT error-flag

- Device decrements WD_FAIL_CNT

- Device generates next QUESTION

- Device sets WD_FIRST_OK=1

YES

NO

- MCU can set ENABLE_DRV=1 if no other error-flags are set

WD_RST_EN=1

Figure 10-27. Flow Chart for WatchDog in Q&A Mode

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10.3.11.8.3.3 Watchdog Q&A Sequence Scenarios

Table 10-10. Correct and Incorrect WD Q&A Sequence Run Scenarios

NUMBER OF WD ANSWERS

WD STATUS BITS IN WDT_STATUS REGISTER

ACTION

COMMENTS

RESPONSE

WINDOW 1

RESPONSE

WINDOW 2

ANSW_ERR ANSW_EARLY

SEQ_ERR

TIME_OUT

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

0 answers

0b

1b

0b

1b

0b

No answers

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

4 INCORRECT

answers

1b

WD_ANSW_CNT[1:0] = 3

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

4 CORRECT

answers

0 answers

1 CORRECT answer

Less than 3 CORRECT

ANSWER in RESPONSE

WINDOW 1 and 1

CORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] < 3)

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 CORRECT answer 1 CORRECT answer

0b

1b

0b

1b

2 CORRECT answer 1 CORRECT answer

1 INCORRECT

0 answers

answer

Less than 3 CORRECT

ANSWER in RESPONSE

WINDOW 1 and 1

INCORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] < 3)

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 INCORRECT

1 CORRECT answer

answer

2 CORRECT

answers

1 INCORRECT

answer

4 CORRECT

answers

0 answers

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

Less than 3 CORRECT

ANSWER in WIN1 and more

than 1 CORRECT ANSWER

in RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] = 3)

3 CORRECT

answers

1 CORRECT answer

0b

1b

0b

1b

0b

2 CORRECT

answers

2 CORRECT

answers

4 INCORRECT

answers

0 answers

Less than 3 CORRECT

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

ANSWER in RESPONSE

WINDOW 1 and more than

1 INCORRECT ANSWER

in RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] = 3)

3 INCORRECT

answers

1 CORRECT answer

2 CORRECT

answers

2 INCORRECT

answers

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

3 CORRECT

answers

0 answers

0b

1b

0b

1b

Less than 3 INCORRECT

ANSWER in RESPONSE

WINDOW 1 and more than

1 CORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] < 3)

1 INCORRECT

answer

2 CORRECT

answers

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

2 INCORRECT

answers

1 CORRECT answer

3 INCORRECT

answers

0 answers

Less than 3 INCORRECT

ANSWER in RESPONSE

WINDOW 1 and more than

1 INCORRECT ANSWER

in RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] < 3)

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 INCORRECT

answer

2 INCORRECT

answer

1b

0b

1b

2 INCORRECT

answer

1 INCORRECT

answer

4 CORRECT

answers

0 answers

0b

1b

0b

1b

0b

Less than 3 INCORRECT

ANSWER in RESPONSE

WINDOW 1 and more than

1 CORRECT ANSWER in

RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] = 3)

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 INCORRECT

answer

3 CORRECT

answers

2 INCORRECT

answers

2 CORRECT

answers

4 INCORRECT

answers

0 answers

Less than 3 INCORRECT

ANSWER in RESPONSE

WINDOW 1 and more than

1 INCORRECT ANSWER

in RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] = 3)

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

1 INCORRECT

answer

3 INCORRECT

answers

1b

0b

1b

0b

2 INCORRECT

answers

2 INCORRECT

answers

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Table 10-10. Correct and Incorrect WD Q&A Sequence Run Scenarios (continued)

NUMBER OF WD ANSWERS

WD STATUS BITS IN WDT_STATUS REGISTER

ACTION

COMMENTS

RESPONSE

WINDOW 1

RESPONSE

WINDOW 2

ANSW_ERR ANSW_EARLY

SEQ_ERR

TIME_OUT

3 CORRECT

answers

0 answers

0b

1b

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD Question

Less than 4 CORRECT ANSW

in RESPONSE WINDOW 1

and more than 0 ANSWER

in RESPONSE WINDOW 2

(WD_ANSW_CNT[1:0] < 3)

2 CORRECT

answers

1b

0b

1 CORRECT

answers

-New WD cycle starts after the

4th WD answer

3 CORRECT

answers

1 CORRECT answer -Decrement WD failure counter

-New WD cycle starts with a new

WD question

0b

1b

0b

1b

0b

1b

0b

CORRECT SEQUENCE

WD_ANSW_CNT[1:0] = 3

WD_ANSW_CNT[1:0] < 3

WD_ANSW_CNT[1:0] = 3

-New WD cycle starts after the

4th WD answer

3 CORRECT

answers

1 INCORRECT

-Increment WD failure counter

answers

0b

-New WD cycle starts with the

same WD question

-New WD cycle starts after the

end of RESPONSE WINDOW 2

-Increment WD failure counter

-New WD cycle starts with the

same WD question

3 INCORRECT

answers

0 answers

-New WD cycle starts after the

4th WD answer

3 INCORRECT

answers

1 CORRECT answer -Increment WD failure counter

-New WD cycle starts with the

same WD question

-New WD cycle starts after the

4th WD answer

3 INCORRECT

answers

1 INCORRECT

-Increment WD failure counter

answer

-New WD cycle starts with the

same WD question

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

4 CORRECT

answers

Not applicable

3 CORRECT

answers + 1

INCORRECT answer

Not applicable

4 CORRECT or INCORRECT

ANSWER in RESPONSE

WINDOW 1

-New WD cycle starts after the

4th WD answer

-Increment WD failure counter

-New WD cycle starts with the

same WD question

2 CORRECT

answers +

2 INCORRECT

answers

1b

0b

1 CORRECT answer

+ 3 INCORRECT

answers

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10.3.12 Error Signal Monitor (ESM)

The TPS6594-Q1 device has two Error Signal Monitor (ESMs): one ESM_MCU to monitor the MCU error output

signal at the nERR_MCU input pin, and one ESM_SoC to monitor the SoC error output signal at the nERR_SoC

input pin.

At device start-up, the ESM_MCU and ESM_SoC can be enabled or disabled through configuration bits

ESM_MCU_EN and ESM_SOC_EN. The values for these configuration bits are stored in the device EEPROM.

To start the enabled ESM, the MCU sets the start bits ESM_MCU_START or ESM_SOC_START for the

respective ESM through software after the system is powered up and the initial software configuration is

completed. If the MCU clears a start bit, the ESM stops monitoring its input pin. The MCU can set the

ENABLE_DRV bit only when the MCU has either started or disabled the ESM. When the prospective ESM

is started, the following configuration registers are write protected and can only be read:

Configuration registers write-protected by the ESM_MCU_START register bit:

•

ESM_MCU_DELAY1_REG

ESM_MCU_DELAY2_REG

ESM_MCU_MODE_CFG

ESM_MCU_HMAX_REG

ESM_MCU_HMIN_REG

ESM_MCU_LMAX_REG

ESM_MCU_LMIN_REG

Configuration registers write-protected by the ESM_SOC_START register bit:

•

ESM_SOC_DELAY1_REG

ESM_SOC_DELAY2_REG

ESM_SOC_MODE_CFG

ESM_SOC_HMAX_REG

ESM_SOC_HMIN_REG

ESM_SOC_LMAX_REG

ESM_SOC_LMIN_REG

ESM uses a deglitch-filter with deglitch-time t_{degl_ESMx}to monitor its related input pin.

The MCU can configure the ESM in two different modes which are defined as follows:

Level the ESM detects an ESM-error when the input pin remains low for a time equal to or longer than the

Mode deglitch-time t_{degl_ESMx}

.

To select this mode for the ESM_MCU, the MCU must clear bit ESM_MCU_MODE. To select this

mode for the ESM_SoC, the MCU must clear bit ESM_SOC_MODE. See Section 10.3.12.1.1 for

further detail

PWM the ESM monitors a PWM signal at its input pin. The ESM detects a bad-event when the frequency or

Mode duty cycle of the PWM input signal deviates from the expected signal. The ESM detects a good-event

when the frequency and duty cycle of the PWM signal match with the expected signal for one signal

period.

The ESM has an error-counter (ESM_MCU_ERR_CNT[4:0] or ESM_SOC_ERR_CNT[4:0]), which

increments with +2 after each bad-event, and decrements with -1 after each good-event. The ESM

detects an ESM-error when the error-counter value is more than its related threshold value.

To select this mode for the ESM_MCU, the MCU must set bit ESM_MCU_MODE. To select this

mode for the ESM_SoC, the MCU must set bit ESM_SOC_MODE. See Section 10.3.12.1.2 for further

details.

The MCU can configure each ESM as long as its related start bit is cleared to 0 (bit ESM_MCU_START or

ESM_SOC_START). As soon as the MCU sets a start bit, the device sets a write-protection on the configuration

registers of the related ESM except the related start bits ESM_MCU_START and ESM_SOC_START.

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10.3.12.1 ESM Error-Handling Procedure

Each ESM has two of its own configurable delay-timers, which are reset when the device clears the respective

ESM_x_START bit. Below steps describe the procedure through which ESM goes in case it detects an ESM-

error:

1. If the respective mask bit ESM_x_PIN_MASK=0, the device sets interrupt bit ESM_MCU_PIN_INT or

ESM_SOC_PIN_INT, and pulls the nINT pin low.

2. The ESM starts the delay-1 timer (configurable through related ESM_MCU_DELAY1[7:0] or

ESM_SOC_DELAY1[7:0] bits).

3. If the ESM-error is no longer present and MCU has cleared the related interrupt bit ESM_MCU_PIN_INT

or ESM_SOC_PIN_INT before the delay-1 timer elapses, the device will release the nINTpin, the ESM will

reset the delay-1 and delay-2 timers and continues to monitor its input pin.

4. If the ESM-error is still present and the delay-1 timer elapses, then the ESM clears the ENABLE_DRV bit if

bit ESM_MCU_ENDRV=1 or if bit ESM_SOC_ENDRV=1.

5. If the delay-2 timer (configurable through related ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits)

is set to 0, then the ESM skips steps 6 of this list, and performs step 7.

6. If the delay-2 timer is not set to 0, then:

a. ESM starts the delay-2 timer,

b. If EMS_MCU_FAIL_MASK = 0, the device sets interrupt bit ESM_MCU_FAIL_INT and pulls the nINT pin

low and starts the delay-2 timer.

c. If EMS_SOC_FAIL_MASK = 0, the device sets interrupt bit ESM_SOC_FAIL_INT, pulls the nINT pin low

and starts the delay-2 timer.

7. If the ESM-error is no longer present and the MCU has cleared the related interrupt bits listed below before

the delay-2 timer elapses, the device will release the nINTpin, the ESM will reset the delay-1 and delay-2

timers and continues to monitor its input pin:

•

ESM_MCU_PIN_INT (and ESM_MCU_FAIL_INT if set in step 6), or

ESM_SOC_PIN_INT (and ESM_SOC_FAIL_INT if set in step 6)

8. If the ESM-error is still present and the delay-2 timer elapses, then:

a. For ESM_MCU, the device:

i. clears the ESM_MCU_START BIT

ii. sets interrupt bit ESM_MCU_RST_INT, which the device handles as an ESM_MCU_RST trigger for

FSM, described in Table 1-1

iii. After this trigger handling completes, the device re-initializes the ESM_MCU

b. For ESM_SoC, the device:

i. clears the ESM_SOC_START bit

ii. sets interrupt bit ESM_SOC_RST_INT, which the device handles as an ESM_SOC_RST trigger for

FSM, described in Table 1-1

iii. After this trigger handling completes, the device re-initializes the ESM_SoC

ESM_MCU_DELAY1[7:0] and ESM_SOC_DELAY1[7:0] set the delay-1 time-interval (t_DELAY-1) for the related

ESM_MCU or ESM_SoC. Use Equation 10 and Equation 11 to calculate the worst-case values for the t_DELAY-1

:

Min. t_DELAY-1= (ESM_x_DELAY1[7:0] × 2.048 ms) × 0.95

Max. t_DELAY-1= (ESM _x_DELAY1[7:0] × 2.048 ms) × 1.05

(10)

(11)

In which x stands for either MCU or SoC.

ESM_MCU_DELAY2[7:0] or ESM_SOC_DELAY2[7:0] bits set the delay-2 time-interval (t_DELAY-2) for the related

ESM_MCU or ESM_SoC. Use Equation 12 and Equation 13 to calculate the worst-case values for the t_DELAY-2

:

Min. t_DELAY-2= (ESM_x_DELAY2[7:0] × 2.048 ms) × 0.95

Max. t_DELAY-2= (ESM _x_DELAY2[7:0] × 2.048 ms) × 1.05

(12)

(13)

In which x stands for either MCU or SoC.

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10.3.12.1.1 Level Mode

In Level Mode, after MCU has set the start bit (bit ESM_MCU_START or bit ESM_SOC_START), the ESM

monitors its nERR_MCU or nERR_SoC input pin. Each ESM detects an ESM-error when the voltage level on

its input pin remains low for a time equal or longer than the deglitch-time t_{degl_ESMx}. When an ESM detects

an ESM-error, it starts the ESM Error-Handling procedure as described in Section 10.3.12.1. Section 10.3.12.1

describes how if the voltage level on its input pin remains high for a time equal or longer than the deglitch-time

t_{degl_ESMx}, before the elapse of the configured delay-1 or delay-2 time-intervals, and the MCU software clears

all ESM related interrupt bits, then the ESM-error is no longer present and the ESM stops the Error-Handling

Procedure. If the ESM-error persists such that the configured delay-1 and delay-2 times elapse, the ESM

sends a ESM_x_RST trigger to the FSM and the device clear the ESM_x_START bit. After FSM completes the

handling of the ESM_x_RST trigger, the device re-initializes the ESM.

For a complete overview on how the ESM works in Level Mode, please refer to the flow-chart in Figure 10-28.

Figure 10-29, Figure 10-30, Figure 10-31, and Figure 10-32 show example wave forms for several error-cases

for the ESM in Level Mode. In these examples, only the ESM_MCU is shown.

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Global Reset Conditions:

START

ESM_x Level Mode

Procedure

- Warm-Reset from Watchdog or ESM_x

- Immediate or Orderly Shutdown

ESM_x in Level-Mode

- Device releases MCU/SoC reset pin

- MCU can set ENABLE_DRV bit

- Device releases nINT pin

- Device Power-On-Reset

NO

ESM_x_EN=1

?

- no ESM_x interrupt bit set

YES

ESM_x pin

NO

level

= 0?

- Device clears ESM_x_START=0

- Device resets the ESM_x_DELAY1

and ESM_x_DELAY2 timers

YES

ESM_x-INTERRUPT

- If ESM_x_PIN_MASK=0, device sets

ESM_x_PIN_INT interrupt bit And pulls nINT

pin low

- Device starts ESM_x_DELAY1 timer, or

continues to run this timer if already started

- Device does not change ENABLE_DRV bit

- Device does not change the level of the

MCU/SoC reset pins

Note: the procedures ^Check

ESM_x_START=1" and ^ESM_x Level

a}ꢀꢁ tŒ}ꢂꢁꢀµŒꢁ^ Œµv ]v ‰ꢃŒꢃooꢁo.

If ESM_x_START=0, the device stops

the ^ESM_x Level Mode

- Device releases

nINT pin if all

interrupt bits are

cleared

- ESM resets

ESM_x_DELAY1 and

ESM_x_DELAY2

timers

Reset-Extension

time-interval

elapsed?

NO

tŒ}ꢂꢁꢀµŒꢁ^

Check ESM_x_START=1

YES

- Device stops ESM_x

Level Mode Procedure

- Device resets the

ESM_x_DELAY1 and

ESM_x_DELAY2 timers

ESM_x pin

level =1 &

ESM_x_PIN_INT=0

?

NO

YES

ESM_x_START

=1?

YES

NO

ESM_x-CONFIGURE

- Device releases MCU/SoC reset pin

- For ESM_MCU: Device forces ENABLE_DRV = 0

- For ESM_SoC: Device forces ENABLE_DRV = 0 if ESM_SoC_ENDRV = 1

- MCU clears all interrupt bits

ESM_x_DELAY1

NO

time-interval

elapsed?

- Device releases nINT pin if no other interrupt bits are set

YES

-

ESM_x configuration registers unlocked

- MCU either clears ESM_x_EN, or

1) MCU configures ESM_x in Level-Mode (bit ESM_x_MODE)

2) MCU configures ESM_x_DELAY1, ESM_x_DELAY2 and ESM_x_ENDRV

3) MCU sets ESM_x_START

Configuration bit

ESM_x_ENDRV =1?

Device forces

ENABLE_DRV= 0

YES

Device locks all

ESM_x

NO

ESM_x_START

=1?

YES

configuration

registers

NO

ESM_x_DELAY2

set to 0?

YES

NO

ESM_x_EN

=0?

NO

- If ESM_x_FAIL_MASK=0, device sets

ESM_x_FAIL_INT interrupt bit And pulls

nINT pin low

YES

- Device starts ESM_x_DELAY2 timer, or

continues to run this timer if already started

NO ESM_x

- MCU/SoC reset inactive

- MCU can set ENABLE_DRV bit (if

no other interrupt bits are set)

- nINT pin released

(if no other interrupt bits are set)

- no ESM_x interrupt bit set

YES

ESM_x pin level =1

& ESM_x_PIN_INT=0 &

ESM_x_FAIL_INT=0

?

ESM_x Level-Mode

Error-Handling

Procedure

NO

ESM_x_EN

=0?

YES

ESM_x_DELAY2

time-interval

elapsed?

NO

YES

-

If ESM_x_FAIL_MASK=0, device sets

ESM_x_FAIL_INT interrupt bIt and pulls nINT

pin low

ESM_x-RESET

- ESM_x_RST trigger send to to FSM

- If ESM_x_RST_MASK=0, device sets

ESM_x_RST_INT interrupt bit and

pulls nINT pin low

Figure 10-28. Flow Chart for Error Detection in Level Mode

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MCU Reset-Extension Time

nRSTOUT Pin

MCU sets

ESM_MCU_START

x

0

1

t_{degl_ESMx}15 ꢀs

t_{LOW_ERROR}<

ESM_MCU_DELAY1

ESM_MCU Input

t_{degl_ESMx}15 ꢀs

Deglitched ESM_MCU

Input Signal

t_{degl_ESMx}15 ꢀs

ESM_MCU_DELAY1 timer reset after

MCU clears ESM_MCU_PIN_INT

ESM_MCU_DELAY1

MCU clears

ESM_MCU_PIN_INT

&

Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT

(ESM_MCU_PIN_MASK=0)

0

1

0

nINT goes immediately low,

MCU needs to check

whether it initiated the

fault-injection or not

nINT goes high after MCU clears

ESM_MCU_PIN_INT

nINT Pin

ESM_MCU_FAIL_INT

(ESM_MCU_FAIL_MASK=0)

0

ESM_MCU_RST_INT

(ESM_MCU_RST_MASK=0)

0

x

0

1

ENABLE_DRV

MCU sets ENABLE_DRV (only

possible when

ESM_MCU_START=1)

Device State

x

ACTIVE or MCU_ONLY

t

0

Case Number 1:

MCU initiated a fault-injection, and MCU clears the ESM_MCU_PIN_INT interrupt bit before elapse of ESM_MCU_DELAY1 time-interval

Figure 10-29. Example Waveform for ESMx in Level Mode - Case Number 1: ESM_MCU Signal Recovers

Before Elapse of Delay-1 time-interval

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MCU Reset-Extension Time

MCU sets

nRSTOUT Pin

ESM_MCU_START

x

0

1

ESM_MCU_START

t_{ESM_DEGLITCH}15 ꢀs

t_{LOW_ERROR}< (ESM_MCU_DELAY1 +

ESM_MCU_DELAY2)

ESM_MCU Input Pin

t_{degl_ESMx}15 ꢀs

Deglitched ESM_MCU

Input Signal

t_{degl_ESMx}15 ꢀs

ESM_MCU_DELAY1 and

ESM_MCU_DELAY2 timers reset after

MCU clears ESM_MCU_PIN_INT and

ESM_MCU_FAIL_INT

ESM_MCU_DELAY1

ESM_MCU_DELAY2

MCU clears

ESM_MCU_PIN_INT

&

Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT

(ESM_MCU_PIN_MASK=0)

0

1

0

nINT goes immediately low,

MCU needs to check

whether it initiated the

fault-injection or not

nINT goes high after MCU clears

ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT

&

nINT Pin

MCU clears

ESM_MCU_FAIL_INT

(ESM_MCU_FAIL_MASK=0)

0

1

0

ESM_MCU_RST_INT

(ESM_MCU_RST_MASK=0)

0

x

0

1

ENABLE_DRV

1

MCU sets ENABLE_DRV (only

possible when

ESM_MCU_START=1)

MCU sets ENABLE_DRV

x

ACTIVE or MCU_ONLY

Device State

t

0

Case Number 2: ESM_MCU_DELAY2 > 0

An error event occurred in the MCU, but the MCU recovers and clears the interrupt bits before elapse of the ESM_MCU_DELAY2 time-interval

Figure 10-30. Example Waveform for ESM in Level Mode – Case Number 2: Delay-2 Not Set To 0 and

ESM_MCU_ENDRV=1, ESM_MCU Signal Recovers Elapse of Delay-2 Time-Interval

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MCU Reset-Extension Time

nRSTOUT Pin

MCU sets

ESM_MCU_START after all

interrupt bits are cleared

MCU sets

ESM_MCU_START

0

x

0

1

t_{degl_ESMx}15 ꢀs

t_{LOW_ERROR}

ESM_MCU Input

t_{degl_ESMx}15 ꢀs

Deglitched ESM_MCU

Input Signal

t_{degl_ESMx}15 ꢀs

ESM_MCU_DELAY1 timer

reset when ESM resets the

MCU

ESM_MCU_DELAY1

MCU clears

ESM_MCU_PIN_INT

&

Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT

(ESM_MCU_PIN_MASK=0)

0

1

0

nINT goes immediately low,

MCU needs to check

whether it initiated the

fault-injection or not

nINT goes high after MCU clears

ESM_MCU_PIN_INT and ESM_MCU_RST_INT

nINT Pin

&

ESM_MCU_FAIL_INT

(ESM_MCU_FAIL_MASK=0)

0

MCU clears

ESM_MCU_RST_INT

(ESM_MCU_RST_MASK=0)

0

1

0

x

0

1

ENABLE_DRV

Device State

MCU sets ENABLE_DRV (only

possible when

ESM_MCU_START=1)

MCU sets ENABLE_DRV (only

possible when

ESM_MCU_START=1)

Warm

Reset

x

ACTIVE or MCU_ONLY

ACTIVE or MCU_ONLY (same as previous)

t

0

Case Number 3a: ESM_MCU_DELAY2 = 0

An error event occurred in the MCU, and the MCU is unable to correct the error before elapse of the ESM_MCU_DELAY1 time-interval. Hence the PMIC resets the MCU

Figure 10-31. Example Waveform for ESM in Level Mode – Case Number 3a: Delay-2 Set To 0 and

ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs

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MCU Reset-Extension Time

MCU sets

MCU Reset-Extension Time

nRSTOUT Pin

MCU sets ESM_MCU_START

after all interrupt bits are cleared

ESM_MCU_START

0

x

0

1

t_{degl_ESMx}15 ꢀs

t_{LOW_ERROR}

ESM_MCU Input Pin

t_{degl_ESMx}15 ꢀs

Internally Deglitched

ESM_MCU Input Signal

t_{degl_ESMx}15 ꢀs

ESM_MCU_DELAY1 and

ESM_MCU_DELAY2

timers reset when ESM

resets the MCU

MCU clears

ESM_MCU_PIN_INT

ESM_MCU_DELAY1

ESM_MCU_DELAY2

&

Deglitched ESM_MCU Input Signal = high

ESM_MCU_PIN_INT

(ESM_MCU_PIN__MASK=0)

0

1

0

nINT goes immediately low,

MCU needs to check

whether it initiated the

fault-injection or not

nINT goes high after MCU clears

ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT

and ESM_MCU_RST_INT

&

nINT Pin

MCU clears

ESM_MCU_FAIL_INT

(ESM_MCU_FAIL_MASK=0)

0

1

0

MCU clears

ESM_MCU_RST_INT

(ESM_MCU_RST_MASK=0)

0

1

0

x

0

1

ENABLE_DRV

Device State

MCU sets ENABLE_DRV (only

possible when

ESM_MCU_START=1)

MCU sets ENABLE_DRV (only

possible when

ESM_MCU_START=1)

Warm

Reset

x

ACTIVE or MCU_ONLY

ACTIVE or MCU_ONLY (same as previous)

t

0

Case Number 3b: ESM_MCU_DELAY2 > 0

An error event occurred in the MCU, and the MCU is unable to correct the error before elapse of the ESM_MCU_DELAY1 and ESM_MCU_DELAY2 time-intervals. Hence the PMIC resets the MCU

Figure 10-32. Example Waveform for ESM in Level Mode – Case Number 3b: Delay-2 Not Set to 0 and

ESM_MCU_ENDRV=1, ESM_MCU Input Signal Recovers Too Late and MCU-Reset Occurs

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MCU Reset-Extension Time

nRSTOUT Pin

MCU sets

ESM_MCU_START

MCU sets ESM_MCU_START

after all interrupt bits are cleared

ESM_MCU_START

0

x

0

1

t_{degl_ESMx}15 ꢀs

t_{LOW_ERROR}

ESM_MCU Input Pin

t_{degl_ESMx}15 ꢀs

Internally Deglitched

ESM_MCU Input Signal

t_{degl_ESMx}15 ꢀs

ESM_MCU_DELAY1 and

ESM_MCU_DELAY2

timers reset when ESM

resets the MCU

MCU clears

ESM_MCU_PIN_INT

Deglitched ESM_MCU Input Signal = high

ESM_MCU_DELAY1

ESM_MCU_DELAY2

&

ESM_MCU_PIN_INT

(ESM_MCU_PIN__MASK=0)

0

1

0

nINT goes immediately low,

MCU needs to check

whether it initiated the

fault-injection or not

nINT goes high after MCU clears

ESM_MCU_PIN_INT and ESM_MCU_FAIL_INT

and ESM_MCU_RST_INT

&

nINT Pin

MCU clears

ESM_MCU_FAIL_INT

MCU clears

ESM_MCU_FAIL_INT

(ESM_MCU_FAIL_MASK=0)

0

1

0

1

0

MCU clears

ESM_MCU_RST_INT

(ESM_MCU_RST_MASK=0)

0

1

0

x

0

1

ENABLE_DRV

Device State

MCU sets ENABLE_DRV (only

possible when

ESM_MCU_START=1)

MCU sets ENABLE_DRV (only

possible when

ESM_MCU_START=1)

Warm

Reset

x

ACTIVE or MCU_ONLY

ACTIVE or MCU_ONLY (same as previous)

t

0

Case Number 3c: ESM_MCU_DELAY2 > 0

An error event occurred in the MCU, the MCU recovers and clears ESM_MCU_FAIL_INT, but fails to clear ESM_MCU_PIN_INT before elapse of the ESM_MCU_DELAY2 time-interval.

Hence the PMIC resets the MCU and sets ESM_FAIL_INT (if ESM_MCU_FAIL_MASK=0).

Figure 10-33. Example Waveform for ESM in Level Mode – Case Number 3c: Delay-2 Not Set to 0 and

ESM_MCU_ENDRV=1, MCU Fails to Clear ESM_MCU_PIN_INT Before Elapse of the ESM_MCU_DELAY2

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10.3.12.1.2 PWM Mode

10.3.12.1.2.1 Good-Events and Bad-Events

In PWM mode, each ESM monitors the high-pulse and low-pulse duration times its PWM inputs signal as

follows:

•

After a falling edge, the ESM starts monitoring the low-pulse time-duration. If the input signal remains low

after exceeding the maximum low-pulse time-threshold (t_{LOW_MAX_TH}), the ESM detects a bad event and

the low-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold,

the ESM detects a bad event. On the next rising edge on the input signal, the ESM starts the high-pulse

time-duration monitoring

•

After a rising edge, the ESM starts monitoring the high-pulse time-duration. If the input signal remains high

after exceeding the maximum high-pulse time-threshold (t_{HIGH_MAX_TH}), the ESM detects a bad event and

the high-pulse duration counter reinitializes. Each time the signal further exceeds the maximum threshold,

the ESM detects a bad event. On the next falling edge on the input signal, the ESM starts the low-pulse

time-duration monitoring.

In addition, each ESM detects a bad-event in PWM mode if one of the events that follow occurs on the

deglitched signal of the related input pin nERR_MCU or nERR_SoC:

•

A high-pulse time-duration which is longer than the maximum high-pulse time-threshold (t_{HIGH_MAX_TH}) that is

configured in corresponding ESM_MCU_HMAX[7:0] or ESM_SOC_HMAX[7:0].

A high-pulse time-duration which is shorter than the minimum high-pulse time-threshold (t_{HIGH_MIN_TH}) that is

configured in corresponding ESM_MCU_HMIN[7:0] or ESM_SOC_HMIN[7:0].

A low-pulse time-duration which is longer than the maximum low-pulse time-threshold (t_{LOW_MAX_TH}) that is

configured in corresponding ESM_MCU_LMAX[7:0] or ESM_SOC_LMAX[7:0].

A low-pulse time-duration which is less than the minimum low-pulse time-threshold (t_{LOW_MIN_TH}) that is

configured in corresponding ESM_MCU_LMIN[7:0] or ESM_SOC_LMIN[7:0].

The ESM detects a good-event in PWM mode if one of the events that follow occurs on the deglitched signal of

the related input pin nERR_MCU or nERR_SoC:

•

A low-pulse time-duration within the minimum and maximum low-pulse time-thresholds is followed by a

high-pulse time-duration within the minimum and maximum high-pulse time-thresholds, or

A high-pulse duration within the minimum and maximum high-pulse time-thresholds is followed by a low-

pulse duration within the minimum and maximum low-pulse time-thresholds

•

ESM_MCU_HMAX[7:0] and ESM_SOC_HMAX[7:0] set the maximum high-pulse time-threshold (t_{HIGH_MAX_TH}

)

for the related ESM. Use Equation 14 and Equation 15 to calculate the worst-case values for the t_{HIGH_MAX_TH}

:

Min. t_{HIGH_MAX_TH}= (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 0.95

Max. t_{HIGH_MAX_TH}= (15 µs +ESM_x_HMAX[7:0] × 15 µs) × 1.05

(14)

(15)

In which x stands for either MCU or SoC.

ESM_MCU_HMIN[7:0] and ESM_SOC_HMIN[7:0] set the minimum high-pulse time-threshold (t_{HIGH_MIN_TH}) for

the related ESM. Use Equation 16 and Equation 17 to calculate the worst-case values for the t_{HIGH_MIN_TH}

:

Min. t_{HIGH_MIN_TH}= (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 0.95

Max. t_{HIGH_MIN_TH}= (15 µs +ESM_x_HMIN[7:0] × 15 µs) × 1.05

(16)

(17)

In which x stands for either MCU or SoC.

ESM_MCU_LMAX[7:0] and ESM_SOC_LMAX[7:0] set the maximum low-pulse time-threshold (t_{LOW_MAX_TH}) for

the related ESM. Use Equation 18 and Equation 19 to calculate the worst-case values for the t_{LOW_MAX_TH}

:

Min. t_{LOW_MAX_TH}= (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 0.95

Max. t_{LOW_MAX_TH}= (15 µs +ESM_x_LMAX[7:0] × 15 µs) × 1.05

(18)

(19)

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In which x stands for either MCUor SoC.

ESM_MCU_LMIN[7:0] and ESM_SOC_LMIN[7:0] set the minimum low-pulse time-threshold (t_{LOW_MIN_TH}) for

the related ESM. Use Equation 20 and Equation 21 to calculate the worst-case values for the t_{LOW_MIN_TH}

:

Min. t_{LOW_MIN_TH}= (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 0.95

Max. t_{LOW_MIN_TH}= (15 µs +ESM_x_LMIN[7:0] × 15 µs) × 1.05

(20)

(21)

In which x stands for either MCU or SoC.

Please note that when setting up the minimum and the maximum low/high-pulse time-thresholds need to be

configured such that clock tolerances from the TPS6594-Q1 and from the processor are incorporated. Equation

22, Equation 23, Equation 24, and Equation 25 are a guideline on how to incorporate these clock-tolerances:

ESM_x_HMIN[7:0] < 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance)

ESM_x_HMAX[7:0] > 0.5 × (ESM_x_HMAX[7:0] + ESM_x_HMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance)

ESM_x_LMIN[7:0] < 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 0.95 × (1 - MCU/SoC clock tolerance)

(22)

(23)

(24)

(25)

ESM_x_LMAX[7:0] > 0.5 × (ESM_x_LMAX[7:0] + ESM_x_LMIN[7:0]) × 1.05 × (1 + MCU/SoC clock tolerance)

10.3.12.1.2.2 ESM Error-Counter

If an ESM detects a bad-event, it increments its related error-counter (bits ESM_MCU_ERR_CNT[4:0] or bits

ESM_SOC_ERR_CNT[4:0]) by 2. If an ESM detects a good-event, it decrements its related error-counter (bits

ESM_MCU_ERR_CNT[4:0] or bits ESM_SOC_ERR_CNT[4:0]) by 1.

The device clears each error counter when ESM_x_START=0. Furthermore, the device clears the error-counter

ESM_SOC_ERR[4:0] when it resets the SoC.

Each

error-counter

has

a

(bits

ESM_MCU_ERR_CNT_TH[3:0]

or

bits

ESM_SOC_ERR_CNT_TH[3:0]) which the MCU can configure if the related ESM start-bit is 0. If the error-

counter value is above its configured threshold, the related ESM has detected a so-called ESM-error and

starts the Error-Handling Procedure as described in Section 10.3.12.1. If the error-counter reached a value

equal or less its configured threshold before the elapse of the configured delay-1 or delay-2 intervals and the

MCU software clears all ESM related interrupt bits, the ESM-error is no longer present and the ESM stops the

Error-Handling Procedure as described in Section 10.3.12.1. If the ESM-error persists such that the configured

delay-1 and delay-2 times elapse, the ESM sends a ESM_x_RST trigger to the FSM and the device clear the

ESM_x_START bit. After FSM completes the handling of the ESM_x_RST trigger, the device re-initializes the

ESM.

10.3.12.1.2.3 ESM Start-Up in PWM Mode

After MCU has set the start bit of an ESM (bit ESM_MCU_START or bit ESM_SOC_START), there are two

possible scenarios:

1. The deglitched signal of the monitored input pin has a low level at the moment the MCU sets the start bit. In

this scenario, the related ESM starts the following procedure:

a. Start a timer with a time-length according the value configured in correspondig ESM_MCU_LMAX[7:0] or

ESM_SOC_LMAX[7:0].

b. Wait for a first rising edge on its deglitched input signal.

c. If the rising edge comes before the configured time-length elapses, the ESM skips the next step and

starts to monitor the high-pulse duration time. Hereafter, the ESM detects good-events or bad-events as

described in Section 10.3.12.1.2.1. Figure 10-35 shows an example this scenario as Case Number 1.

d. If the configured time-length (configured in corresponding ESM_MCU_LMAX[7:0] or

ESM_SOC_LMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter

with +2. Hereafter, the ESM detects good-events or bad-events as described in Section 10.3.12.1.2.1.

Figure 10-37 shows an example this scenario as Case Number 3.

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e. If the error-counter value is above its configured threshold, the related ESM has detected a so-called

ESM-error and starts the Error-Handling Procedure as described in Section 10.3.12.1.2.1.

f. During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates

the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling

Procedure reaches the step in which the device causes an ESM ERROR trigger in the state machine,

which may reset the MCU or SoC according to the PFSM definition. Figure 10-38 shows a scenario in

which the device resets the MCU or SoC as Case Number 4.

g. If the error-counter reaches a value equal or less its configured threshold before the elapse of the

configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits,

the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in

Section 10.3.12.1.2.1.

2. The deglitched signal monitored input pin has a high level at the moment the MCU sets the start bit. In this

scenario, the related ESM starts the following procedure:

a. Start a timer with a time-length according the value configured in corresponding ESM_MCU_HMAX[7:0]

or ESM_SOC_HMAX[7:0].

b. Wait for a first falling edge on its deglitched input signal.

c. If the falling edge comes before the configured time-length elapses, the ESM skips the next step and

starts to monitor the low-pulse duration time. Hereafter, the ESM detects good-events or bad-events as

described in Section 10.3.12.1.2.1. Figure 10-36 shows an example this scenario as Case Number 2.

d. If the configured time-length (configured in corresponding ESM_MCU_HMAX[7:0] or

ESM_SOC_HMAX[7:0]) elapses, the ESM detects a bad-event and increments the related error-counter

with +2. Hereafter, the ESM detects good-events or bad-events as described in Section 10.3.12.1.2.1.

e. If the error-counter value is above its configured threshold, the related ESM has detected a so-called

ESM-error and starts the Error-Handling Procedure as described in Section 10.3.12.1.2.1.

f. During this Error-Handling Procedure, the ESM continues to monitor its related input pin, and updates

the error-counter accordingly when it detects good-events or bad-events, until the Error-Handling

Procedure reaches the step in which the device causes an ESM ERROR trigger in the state machine,

which may reset the MCU or SoC according to the PFSM definition, as Case Number 4.

g. If the error-counter reaches a value equal or less its configured threshold before the elapse of the

configured delay-1 or delay-2 time-intervals and the MCU software clears all ESM related interrupt bits,

the ESM-error is no longer present and the ESM stops the Error-Handling Procedure as described in

Section 10.3.12.1.2.1.

10.3.12.1.2.4 ESM Flow Chart and Timing Diagrams in PWM Mode

For a complete overview on how the ESM works in PWM Mode, please refer to the flow-chart in Figure 10-34.

Figure 10-35, Figure 10-36, Figure 10-37, and Figure 10-38 show example waveforms for several error-cases for

the ESM in PWM Mode.

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Global Reset Conditions:

- Warm-Reset from Watchdog or ESM_x

- Immediate or Orderly Shutdown

NO

ESM_x-CONFIGURE

- Device releases MCU/SoC reset pins

- Device forces ENABLE_DRV= 0

- MCU clears all interrupt bits

- Device releases nINT pin if no other interrupt bits are set

NO ESM_x

NO

- MCU/SoC reset inactive

- MCU can set ENABLE_DRV bit -

nINT pin released

(if no other interrupt bits are set)

- no ESM_x interrupt bit set

YES

ESM_x_EN

=0?

- Device Power-On-Reset

ESM_x_START

=1?

NO

ESM_x_EN

=0?

-

ESM_x configuration registers unlocked

YES

START

- MCU either clears ESM_x_EN, or

1) MCU configures ESM in PWM-Mode +

ESM_x_H/L_MAX/MIN times

2) MCU configures ESM_x_DELAY1, ESM_x_DELAY2 and

ESM_x_ENDRV

YES

Device locks all

ESM_x

- Device stops

YES

configuration

registers

ESM_x_PWM Mode

Procedure and ESM_x

PWM Error-Handling

Procedure

- Device resets the

ESM_x_DELAY1 and

ESM_x_DELAY2 timers

NO

ESM_x_EN=1

?

3) MCU sets ESM_x_START

ESM_x_

START=1?

NO

YES

Note: šZꢀ ‰Œ}ꢁꢀꢂµŒꢀ• c/Zꢀꢁl 9{a_x_START=1", c9{a_Æ tía a}ꢂꢀ tŒ}ꢁꢀꢂµŒꢀ^ ꢃvꢂ c9{a_x

PWM Error-Iꢃvꢂo]vP tŒ}ꢁꢀꢂµŒꢀ^ Œµv ]v ‰ꢃŒꢃooꢀo. If ESM_x_START=0, the device stops the

c9{a_Æ tía a}ꢂꢀ tŒ}ꢁꢀꢂµŒꢀ^ ꢃvꢂ šZꢀ c9{a_x PWM Error-Iꢃvꢂo]vP tŒ}ꢁꢀꢂµŒꢀ^

Check

ESM_x_START=1

- Device clears

ESM_x_START=0

- Device resets the

ESM_x_DELAY1

and ESM_x_DELAY2

timers

ESM_x_ PWM Mode Procedure

NO

YES

NO

ESM_x

detects

Falling Edge

?

ESM_x_

LMAX time

elapsed?

ESM_x_

HMAX time

elapsed?

ESM_x pin

level

= 0?

detects

Rising Edge

?

YES

NO

YES

- MCU/SoC reset inactive

Reset-Extension

time-interval

elapsed?

YES

ESM_x

PWM Error-

Handling

- MCU can set ENABLE_DRV bit

- nINT pin released

(if no other interrupt bits are set)

- no ESM_x interrupt bit set

ESM_x

PWM Error-

Handling

Device increase

ESM_x

Error-Counter

with +2

Device increase

ESM_x

Error-Counter

with +2

Procedure

NO

ESM_x

detects

Falling Edge

?

ESM_x

detects

Rising Edge

?

ESM_x_

HMAX time

elapsed?

ESM_x_

LMAX time

elapsed?

YES

NO

YES

Device increase

ESM_x

Error-Counter

with +2

Device increase

ESM_x_

HMIN time

elapsed?

ESM_x_

LMIN time

elapsed?

ESM_x

Error-Counter

with +2

NO

YES

ESM_x PWM Error-

Handling Procedure

ESM_x PWM Error-

Handling Procedure

Device decrease

ESM_x

Error-Counter

with -1

NO

ESM_x

detects

Rising Edge

?

ESM_x

detects

Falling Edge

?

ESM_x_

LMAX time

elapsed?

ESM_x_

HMAX time

elapsed?

NO

Device decrease

ESM_x

YES

Error-Counter

with -1

Device increase ESM_x

Error-Counter with +2

Device increase ESM_x

Error-Counter with +2

YES

ESM_x PWM Error-

Handling Procedure

ESM_x PWM Error-

Handling Procedure

ESM_x_

LMIN time

elapsed?

ESM_x_

HMIN time

elapsed?

Device increase ESM_x

Error-Counter with +2

Device increase ESM_x

Error-Counter with +2

NO

YES

ESM_x PWM Error-

Handling Procedure

ESM_x PWM Error-

Handling Procedure

ESM_x PWM Error-Handling Procedure

Note: until step ESM_x-RESET, the

ESM_x_PWM Mode Procedure runs

NO

ESM_x

Error-Counter

≤ Threshold &

ESM_x_PIN_INT=

ESM_x-INTERRUPT

in parallel

Configuration

- If ESM_x_PIN_MASK=0, device sets

ESM_x_PIN_INT interrupt bit and pulls nINT

pin low

- Device starts ESM_x_DELAY1 timer, or

continues to run this timer if already started

- Device does not change ENABLE_DRV bit

- Device does not change the level of the

MCU/SoC reset pins

ESM_x_DELAY1

time-interval

elapsed?

NO

YES

bit

ESM_x_ENDRV

=1?

YES

ESM_x

Error-Counter

>Threshold

0?

YES

START

END

Device forces

ENABLE_DRV= 0

NO

YES

NO

- Device releases nINT pin if

all interrupt bits are cleared

- ESM resets ESM_x_DELAY1

and ESM_x_DELAY2 timers

ESM_x_DELAY2

set to 0?

YES

NO

ESM_x-RESET

ESM_x

Error-Counter

< Threshold &

ESM_x_PIN_INT=0 &

ESM_x_FAIL_INT

=0?

- ESM_x_RST trigger send

to to FSM

- If ESM_x_RST_MASK=0,

device sets ESM_x_RST_INT

interrupt bit and pulls nINT

pin low

-

If ESM_x_FAIL_MASK=0,

- If ESM_x_FAIL_MASK=0, device sets

ESM_x_FAIL_INT interrupt bit and pulls nINT pin

low

- Device starts ESM_x_DELAY2 timer, or continues

to run this timer if already started

ESM_x_DELAY2

time-interval

elapsed?

device sets ESM_x_FAIL_INT

interrupt bit and pulls nINT

pin low

YES

NO

Figure 10-34. Flow-Chart for ESM_MCU and ESM_SoC in PWM Mode

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Reset-Extension Time

nRSTOUT /

nRSTOUT_SoC Pin

MCU sets ESM_x_START

x

0

1

ESM_x_START

t_{degl_ESMx}15 ꢀs

t_{HIGH_MAX_TH}

=

t_{HIGH_MAX_TH}

=

(ESM_x_HMAX [7:0] + 1) × 15 ꢀs

t_{HIGH_MIN_TH}=

(ESM_x_HMIN [7:0] + 1)

t_{HIGH_MIN_TH}=

(ESM_x_HMIN [7:0] + 1)

× 15 ꢀs

t_{LOW_MAX_TH}

=

t_{LOW_MAX_TH}

=

t_{LOW_MAX_TH}

=

(ESM_x_LMAX[7:0] + 1) × 15 ꢀs

t_{LOW_MIN_TH}

=

t_{LOW_MIN_TH}=

(ESM_x_LMIN[7:0] + 1) × 15 ꢀs

High-Pulse Timer

Stopped,

Low-Pulse Timer

Reset and Started

High-Pulse Timer

Stopped,

Low-Pulse Timer

Reset and Started

Low-Pulse Timer

Reset and

Started

Deglitched ESM_x

Input Signal

Low-Pulse Timer

Stopped,

Low-Pulse Timer

Stopped,

Low-Pulse Timer

Stopped,

High-Pulse Timer

Reset and Started

High-Pulse Timer

Reset and Started

High-Pulse Timer

Reset and Started

no bad event trigger as

long as rising edge on

ESM_x signal comes

before elapse of

t_{PWM_LOW}

t_{PWM_HIGH}

1 ESM_x good-event

t_{LOW_MAX_TH}

InternalESM_x

badeventTrigger

InternalESM_x

goodeventTrigger

ESM_x_ERR_CNT[4:0]

x

00000

ESM_x_PIN_INT

(ESM_x_PIN_MASK=0)

0

nINT Pin

ESM_x_FAIL_INT

(ESM_x_FAIL_MASK=0)

0

ESM_x_RST_INT

(ESM_x_RST_MASK=0)

0

ENABLE_DRV

x

1

MCU sets ENABLE_DRV (ESM_MCU, only possible if

ESM_MCU_START=1. ESM_SOC possible if ESM_SOC_ENDRV=0

or if ESM_SOC_ENDRV=1 and ESM_SOC_START=1)

Case Number 1:

PWM signal has a low level at the moment the MCU sets bit ESM_x_start, and the PMIC receives a PWM Error Signal with Correct Timing afterwards

Figure 10-35. Example Waveform for ESM in PWM Mode – Case Number 1: ESM Starts with Low-Level at

Deglitched Input signal, and Receives Correct PWM Signal Afterwards

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Reset-Extension Time

nRSTOUT /

nRSTOUT_SoC Pin

ESM_x_START

MCU sets ESM_x_START

x

0

1

t_{degl_ESMx}15 ꢀs

t_{HIGH_MAX_TH}

=

t_{HIGH_MAX_TH}

=

t_{HIGH_MAX_TH}

=

(ESM_x_HMAX [7:0] + 1) × 15 ꢀs

t_{HIGH_MIN_TH}=

(ESM_x_HMIN [7:0] + 1)

t_{HIGH_MIN_TH}=

(ESM_x_HMIN [7:0] + 1)

× 15 ꢀs

t_{LOW_MAX_TH}

=

t_{LOW_MAX_TH}

=

(ESM_x_LMAX[7:0] + 1) × 15 ꢀs

t_{LOW_MIN_TH}

(ESM_x_LMIN[7:0] + 1) × 15 ꢀs

=

t_{LOW_MIN_TH}

(ESM_x_LMIN[7:0] + 1) × 15 ꢀs

=

High-Pulse Timer

Reset and Started

High-Pulse Timer

Stopped,

High-Pulse Timer

Stopped,

High-Pulse Timer

Stopped,

Deglitched ESM_x

Input Signal

Low-Pulse Timer

Reset and Started

Low-Pulse Timer

Reset and Started

Low-Pulse Timer

Reset and Started

Low-Pulse Timer

Stopped,

Low-Pulse Timer

Stopped,

High-Pulse Timer

Reset and Started

High-Pulse Timer

Reset and Started

no bad event trigger as

long as falling edge on

ESM_x signal comes

before elapse of

t_{PWM_HIGH}

t_{PWM_LOW}

1 ESM_x good-event

t_{HIGH_MAX_TH}

InternalESM_x

badeventTrigger

InternalESM_x

goodeventTrigger

x

00000

ESM_x_ERR_CNT[4:0]

ESM_x_PIN_INT

(ESM_x_PIN_MASK=0)

0

nINT Pin

ESM_x_FAIL_INT

(ESM_x_FAIL_MASK=0)

0

ESM_x_RST_INT

(ESM_x_RST_MASK=0)

0

ENABLE_DRV

x

1

MCU sets ENABLE_DRV (ESM_MCU, only possible if

ESM_MCU_START=1. ESM_SOC possible if ESM_SOC_ENDRV=0

or if ESM_SOC_ENDRV=1 and ESM_SOC_START=1)

Case Number 2:

PWM signal has a high level at the moment the MCU sets bit ESM_x_start, and the PMIC receives a PWM Error Signal with Correct Timing afterwards

Figure 10-36. Example Waveform for ESM in PWM Mode – Case Number 2: ESM Starts with High-Level at

Deglitched Input Signal, and Receives Correct PWM Signal Afterwards

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Reset-Extension Time

nRSTOUT /

nRSTOUT_SoC Pin

MCU sets ESM_x_START

x

0

1

ESM_x_START

t_{degl_ESMx}15 ꢀs

t_{HIGH_MAX_TH}=

(ESM_x_HMAX [7:0] + 1) ×

t_{HIGH_MAX_TH}=

(ESM_x_HMAX [7:0] + 1) ×

t_{HIGH_MAX_TH}=

(ESM_x_HMAX [7:0] + 1) ×

15 ꢀs

t_{HIGH_MIN_TH}=

(ESM_x_HMIN

t_{HIGH_MIN_TH}=

(ESM_x_HMIN

t_{HIGH_MIN_TH}=

(ESM_x_HMIN

[7:0] + 1) × 15 ꢀs

t_{LOW_MAX_TH}=

(ESM_x_LMAX[7:0] + 1)

t_{LOW_MAX_TH}

=

(ESM_x_LMAX[7:0] + 1)

× 15 ꢀs

t_{LOW_MAX_TH}=

(ESM_x_LMAX[7:0] + 1)

t_{LOW_MAX_TH}

(ESM_x_LMAX[7:0] + 1)

=

t_{LOW_MAX_TH}=

(ESM_x_LMAX[7:0] + 1)

× 15 ꢀs

t_{LOW_MIN_TH}

(ESM_x_LMIN[7:0]

=

t_{LOW_MIN_TH}=

(ESM_x_LMIN[7:0]

t_{LOW_MIN_TH}=

(ESM_x_LMIN[7:0]

+ 1) × 15 ꢀs

Deglitched ESM_x

Input Signal

t_{PWM_LOW}

t_{PWM_HIGH}

1 ESM_x good event

InternalESM_xbad

eventTrigger

InternalESM_xgood

eventTrigger

ESM_x_ERR_CNT[4:0]

00010

00001

00000

ESM_x_DELAY2

00000

ESM_x_DELAY1 and

x

00000

ESM_x_ERR_CNT_

TH[3:0] = 0001

ESM_x_DELAY1

ESM_x_DELAY2 timers reset after

MCU clears ESM_x_PIN_INT and

ESM_x_FAIL_INT

MCU clears ESM_x_PIN_INT

ESM_x_ERR_CNT[4:0] ≤

ESM_x_ERR_CNT_TH[3:0]

&

ESM_x_PIN_INT

0

1

0

&

nINT Pin

MCU clears

ESM_x_FAIL_INT

1

0

ESM_x_FAIL_INT

0

ESM_x_RST_INT

ENABLE_DRV

x

1

0

1

MCU sets ENABLE_DRV (ESM_MCU,

only possible if ESM_MCU_START=1.

ESM_SOC possible if

MCU sets ENABLE_DRV (ESM_MCU, only possible if

ESM_MCU_START=1. ESM_SOC possible if ESM_SOC_ENDRV=0

or if ESM_SOC_ENDRV=1 and ESM_SOC_START=1)

Note: PMIC clears ENABLE_DRV

only when configuration bit

ESM_x_ENDRV=1

ESM_SOC_ENDRV=0 or if

ESM_SOC_ENDRV=1 and

ESM_SOC_START=1)

Case Number 3: ESM_DELAY2 > 0

PWM signal has a low level at the moment the MCU sets bit ESM_x_start, but the PMIC receives the PWM Error Signal too late. Afterwards PWM Error Signal recovers with Correct Timing and

ESM_x_ERR_CNT[4:0] reaches a value less than the configured ESM_x_ERR_CNT_TH[3:0] before elapse of the ESM_x_DELAY2 time-interval

Figure 10-37. Example Waveform for ESM in PWM Mode – Case Number 3: ESM Starts with Low-Level at

Deglitched Input Signal, but Receives Too Late a Correct PWM Signal Afterwards

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Reset-Extension

Time

Reset-Extension Time

nRSTOUT /

nRSTOUT_SoC Pin

ESM_x_START

MCU sets

ESM_x_START after all

interrupt bits are cleared

MCU sets ESM_x_START

x

0

1

t_{degl_ESMx}15 ꢀs

t_{HIGH_MAX_TH}=

(ESM_x_HMAX

t_{HIGH_MAX_TH}

(ESM_x_HMAX

=

t_{HIGH_MAX_TH}

(ESM_x_HMAX (ESM_x_HMAX

=

t_{HIGH_MAX_TH}=

[7:0] + 1) × 15 ꢀs

[7:0] + 1) × 15 ꢀs[7:0] + 1) × 15 ꢀs

t_{HIGH_MIN_TH}

(ESM_x_

HMIN [7:0] +

=

t_{HIGH_MIN_TH}

(ESM_x_

HMIN [7:0] +

=

t_{HIGH_MIN_TH}

(ESM_x_

HMIN [7:0] +

=

t_{HIGH_MIN_TH}

(ESM_x_

HMIN [7:0] +

=

1) × 15 ꢀs

1) x 15 ꢀs

t_{LOW_MAX_TH}

=

(ESM_x_LMAX[7:0] + 1)

× 15 ꢀs

t_{LOW_MAX_TH}=

(ESM_x_LMAX[7:0] + 1)

t_{LOW_MAX_TH}

=

(ESM_x_LMAX[7:0] + 1)

× 15 ꢀs

t_{LOW_MAX_TH}

(ESM_x_LMAX[7:0] + 1)

=

t_{LOW_MAX_TH}=

(ESM_x_LMAX[7:0] + 1)

t_{LOW_MAX_TH}=

(ESM_x_LMAX[7:0]

+ 1) × 15 ꢀs

× 15 ꢀs

t_{LOW_MIN_TH}

(ESM_x_LMIN[7:

0] + 1) × 15 ꢀs

=

t_{LOW_MIN_TH}

(ESM_x_LMIN[7:

0] + 1) × 15 ꢀs

=

t_{LOW_MIN_TH}

(ESM_x_LMIN[7:

0] + 1) × 15 ꢀs

=

t_{LOW_MIN_TH}=

(ESM_x_LMIN[7:

0] + 1) × 15 ꢀs

Deglitched ESM_x

Input Signal

t

t_{PWM_HIGH}

t_{PWM_LOW}

t_{PWM_HIGH}

t_{PWM_LOW}

t_{PWM_HIGH}

t_{PWM_LOW}

P

W

M

_

H

I

G

H

P

W

M

_

L

O

W

1 ESM_x good event

InternalESM_xbad

eventTrigger

InternalESM_xgood

eventTrigger

ESM_x_ERR_

CNT[4:0]

00100

00101

00000

x

00000

00110

00010

ESM_x_ERR_CNT_

TH[3:0] = 0011

ESM_x_DELAY1 and ESM_x_DELAY2 timers

reset when ESM_x resets the MCU or SoC

ESM_x_DELAY1

ESM_x_DELAY2

MCU clears ESM_x_PIN_INT

ESM_x_ERR_CNT[4:0] ≤

ESM_x_ERR_CNT_TH[3:0]

&

ESM_x_PIN_INT

(ESM_x_PIN_MASK

=0)

0

1

0

&

nINT Pin

MCU clears

ESM_x_FAIL_INT

(ESM_x_FAIL_MASK

=0)

1

0

MCU clears

ESM_x_RST_INT

(ESM_x_RST_MASK

=0)

0

1

ENABLE_DRV

x

1

0

1

MCU sets ENABLE_DRV (ESM_MCU, only possible if

ESM_MCU_START=1. ESM_SOC possible if

ESM_SOC_ENDRV=0 or if ESM_SOC_ENDRV=1 and

ESM_SOC_START=1)

Note: PMIC clears ENABLE_DRV

only when configuration bit

ESM_x_ENDRV=1

MCU sets ENABLE_DRV (ESM_MCU, only

possible if ESM_MCU_START=1. ESM_SOC

possible if ESM_SOC_ENDRV=0 or if

ESM_SOC_ENDRV=1 and ESM_SOC_START=1)

Case Number 4: _DELAY2 > 0

PWM signal has an error after start-up, and the ESM_x_ERR_CNT[4:0] > ESM_x_ERR_CNT_TH[3:0] during the elapse of ESM_x_DELAY1 and ESM_x_DELAY2. Hence the PMIC

pulls the nRSTOUT / nRSOUT_SoC pin low, and releases this pin after the reset-extension time. After this, MCU clears all errors and restarts the ESM_x

Figure 10-38. Example Waveform for ESM in PWM Mode – Case Number 4: ESM Starts with Low-Level

at Deglitched Input Signal and Receives a Correct PWM Signal. Afterwards the ESM Detects Bad Events,

and the PWM Signal Recovers Too Late which Leads to an ESM ERROR Trigger in the State Machine

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10.4 Device Functional Modes

10.4.1 Device State Machine

The TPS6594-Q1 device integrates a finite state machine (FSM) engine, which manages the state of the device

during operating state transitions. It supports EEPROM configurable mission states with configurable input

triggers for transitions between states. Any resources, including the 5 bucks, 4 LDOs, and all of the digital IO

pins including the 11 GPIO pins on the device, can be controlled during power sequencing. When a resource is

not controlled or configured through a power sequence, the resource is left in the default state as pre-configured

by the NVM.

Each resource can be pre-configured through the NVM configuration, or re-configured through register bits.

Therefore, the user can statically control the resource through the control interfaces (I²C or SPI), or the FSM can

automatically control the resource during state sequences.

The FSM is powered by an internal LDO which is automatically enabled when VCCA supply is available to the

device. Ensuring that the VCCA supply is the first supply available to the device is important to ensure proper

operation of all the power resources as well as the control interface and device IOs.

There are 3 parts of the FSM which control the operational modes of the TPS6594-Q1 device:

•

Fixed Device Power Finite State Machine (FFSM)

Pre-Configurable Mission Finite State Machine (PFSM)

Error Handling Operations

The PFSM works in complimentry to the traditional FFSM in order to draw from the strengths of both designs

and to reduce the high cost of a completely configurable FSM. The PFSM provides configurable rail sequencing

utilizing instructions in configuration memory. This flexibility enables customers to alter power-up sequences on a

platform basis. The FFSM handles the majority of fixed functionality that is internally mandated and common to

all platforms.

10.4.1.1 Fixed Device Power FSM

The Fixed Device Power portion of the FSM engine manages the power up of the device before the power rails

are fully enabled and ready to power external loadings, and the power down of the device when in the event of

insufficient power supply or device or system error conditions. While the device is in one of the Hardware Device

Powers states, the ENABLE_DRV bit remains low.

The definitions and transition triggers of the Device Power States are fixed and cannot be reconfigured.

Following are the definitions of the Device Power states:

NO SUPPLY

The device is not powered by a valid energy source on the system power rail. The device is

completely powered off.

BACKUP (RTC The device is not powered by a valid supply on the system power rail (VCCA < VCCA_UVLO);

backup

battery)

a backup power source, however, is present and is within the operating range of the

LDOVRTC. The RTC clock counter remains active in this state if it has been previously

activated by appropriate register enable bit. The calendar function of the RTC block is

activated, but not accessible in this state. Customer has the option to enable the shelf mode

by disconnecting the VCCA supply completely, even while the backup battery is connected

to the VBACKUP pin. This will force the device to skip the BACKUP state and enters the

NO SUPPLY state under VCCA_UVLO condition to reduce current draining from the backup

battery.

LP_STANDBY The device can enter this state from a mission state after receiving a valid OFF request or

an I2C trigger, and the LP_STANDBY_SEL= 1. When the device is in this state, the RTC

clock counter and the RTC Alarm or Timer Wake up functions are active if they have been

previously activated by appropriate register enable bit. Low Power Wake-up input monitor in

the LDOVRTC domain (LP_WKUP secondary function through GPIO3 or GPIO4) and the on

request monitors are also enabled in this state. When a logic level transition from high-to-low

or low-to-high with a minimum pulse length of t_{LP_WKUP}is detected on the assigned LP_WKUP

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pin, or if the device detects a valid on-request or a wake up signal from the RTC block, the

device will proceed to power up the device and reach the default mission state. More details

regarding the LP_WAKE function can be found in Section 10.4.1.2.4.5.

INIT

The device is powered by a valid supply on the system power rail (VCCA ≥ VCCA_UV). If

the device was previously in LP_STANDBY state, it has received an external wake-up signal

at the LP_WKUP1/2 pins, the RTC alarm or timer wake-up signal, or an On Request from

the nPWRON/ENABLE pin. Device digital and monitor circuits are powered up. The PMIC

reads its internal NVM memory in this state and configures default values to registers, IO

configuration and FSM accordingly.

BOOT BIST

The device is running the built-in self test routine which includes both the LBIST and the

ABIST/CRC. An option is available to shorten the device power up time from the NO_SUPPLY

state by setting the NVM bit FAST_BOOT_BIST = '1' to skip the LBIST. Software can also

set the FAST_BIST = '1' to skip LBIST after the device wakes up from the LP STANDBY

state. When the device arrives at this state from the SAFE_RECOVERY state, LBIST is

automatically skipped if it has not previously failed. If LBIST failed, but passed after multiple

re-tries before exceeding the recovery counter limit, the device will be powered up normally.

The following NVM bits are additional options which can be set to disable parts of the

ABIST/CRC tests if further sequence time reduction is required. Note: the BIST tests are

executed as parallel processes, and the longest process determines the total BIST duration.

Therefore, the following options does not guarantee a certain amount of time saving from the

total BIST duration:

•

REG_CRC_EN = '0': disables the register map and SRAM CRC check

VMON_ABIST_EN = '0': disables the ABIST for the VMON OV/UV function

RUNTIME BIST A request was received from the MCU to exercise runtime BIST on the device. No rails

are modified and all external signals, including all I²C or SPI interface communications, are

ignored during BIST. If the device passed BIST, it will resume the previous operation. if the

device failed BIST, it will shut down all of the regulator outputs and proceed to the SAFE

RECOVERY state. In order to avoid a register CRC error, all register writes must be avoided

after the request for the BIST operation until an interrupt is asserted to indicate the completion

of BIST. The results of the BIST are indicated by the BIST_PASS_INT or the BIST_FAIL_INT

bits.

SAFE

RECOVERY

The device meets the qualified error condition for immediate or ordered shutdown request.

If the error is recovered within the recovery time interval or meets the restart condition, the

device will increment the recovery count, and return to INIT state if the recovery count does

not exceeded the threshold of the counter. If the recovery count exceeded the threshold or if

the error cannot be recovered, such as the die temperature cannot be reduced to < T_WARN

,

or if VCCA stays above OVP threshold, the device will stay in SAFE RECOVERY state until

supply power cycle occurs.

When multiple system conditions occur simultaneously which demands power state arbitration, the device will go

to the higher priority state according to the following priority order:

1. NO SUPPLY

2. BACKUP

3. SAFE_RECOVERY

4. LP_STANDBY

5. MISSION STATES

Figure 10-39 shows the power transition states of the FSM engine.

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NO

SUPPLY

LDOVRTC UVLO Condition or

Shelf Mode enabled

VCCA < VCCA_UVLO

BACKUP

All States

Except NO SUPPLY

VCCA > VCCA_UV

LP STANDBY

VCCA > VCCA_UV

LP_STANDBY_SEL = 1 and

no valid WAKE request¹

Valid WAKE Request¹

INIT

INIT done and

no error detected and

no residual voltage detected

Error recovered or

meets restart condition

Off request and

LP_STANDBY_SEL = 1

All States

Recovery

counter exceeded

Thermal Shutdown or

VCCA OVP

Error Conditions

(recovery cnt +1)

SAFE

RECOVERY

BOOT

BIST

BOOT BIST error

(recovery cnt +1)

Orderly shutdown

Condition

(recovery cnt +1)

BOOT BIST success

Severe or Moderate

PFSM Errors

(recovery cnt +1)

Mission States

RUNTIME BIST request

RUNTIME BIST complete

RUNTIME

BIST

¹A valid WAKE request consist of:

ñ nPWRON/ENABLE on request detection if the device arrived the LP_STANDBY state through

the long key-press of the nPWRON pin or by disabling the ENABLE pin, or

ñ RTC Alarm, RTC Timer, LP_WKUP1 or LP_WKUP2 detection if the device arrived the

LP_STANDBY state through writing to a TRIGGER_I2C_0 bit.

Figure 10-39. State Diagram for Device Power States

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10.4.1.1.1 Register Resets and EEPROM read at INIT state

When the device transitions from the LP_STANDBY or the SAFE_RECOVERY to the INIT state, the registers

are reset and EEPROM is read based on FIRST_STARTUP_DONE bit. When the FIRST_STARTUP_DONE is

'0', registers which are not in the RTC domain are reset, and all of the EEPROM registers, including the ones in

the RTC domains, will be loaded from the EEPROM. Once the FIRST_STARTUP_DONE bit is set to '1', typically

after the initial power up from a supply power cycle, the registers in the RTC domain will not be reset, and the

EEPROM registers in the RTC comain will no longer be loaded from the EEPROM. This prevents the control and

status bits stored in the RTC domain registers from being over written.

Table 10-11. Register resets and EEPROM read at INIT state

FIRST

_STARTUP_DONE

EEPROM Registers in

RTC Domain

Non-EEPROM Registers in

RTC Domain

Other Non-EEPROM

Registers

Other EEPROM Registers

Defaults read from

EEPROM

Reset and defaults read

from EEPROM

0

1

No changes

Reset

Reset and defaults read

from EEPROM

No changes

Below are the EEPROM register bits in the RTC domain:

•

GPIO3_CONF and GPIO4_CONF registers, except the GPIOn_DEGLITCH_EN bits

GPIO3_RISE_MASK, GPIO3_FALL_MASK, GPIO4_RISE_MASK, and GPIO4_FALL_MASK bits

NPWRON_CONF register except ENALBE_DEGLITCH_EN and NRSTOUT_OD bits

FSD_MASK, ENABLE_MASK, NPWRON, START_MASK, and NPWRON_LONG_MASK bits

STARTUP_DEST, FAST_BIST, LP_STANDBY_SEL, XTAL_SEL, and XTAL_EN bits

PFSM_DELAYn, and RTC_SPARE_n bits

Below are the non-EEPROM register bits in the RTC domain:

•

FIRST_STARTUP_DONE bit

SCRATCH_PAD_n bits

All of RTC control and configuration registers

10.4.1.2 Pre-Configurable Mission States

When the device arrives at a mission state, all rail sequencing is controlled by the pre-configurable FSM engine

(PFSM) through the configuration memory. The configuration memory allows configurations of the triggers and

the operation states which together form the configurable sub state machine within the scope of mission states.

This sub state machine could be used to control and sequence the different voltage outputs as well as any

GPIO outputs that can be used as enable for external rails. When the device is in a mission state, it has the

capacity to supply the processor and other platform modules depending on the power rail configuration. The

definitions and transition triggers of the mission states are configurable through the NVM configuration. Unlike

the user registers, the PFSM defintion stored in the NVM cannot be modified during normal operation. When the

PMIC determines that a transition to another operation state is necessary, it will read the configuration memory

to determine what sequencing is needed for the state transition.

Table 10-15 shows how the trigger signals for each state transition can come from a variety of interface or GPIO

inputs, or potential error sources. Figure 10-40 shows how the device processes all of the possible error sources

inside the PFSM engine, a hierarchical mask system is applied to filter out the common errors which can be

handled by interrupt only, and categorize the other error sources as Severe Global Error, Moderate Global Error,

and so forth. The filtered and categorized triggers are sent into the PFSM engine, which then determines the

entry and exit condition for each configured mission state.

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All Potential Error (Interrupt) Sources

INTERRUPT

is given

First level mask to filter out non-error interrupts vs. interrupts which require error handling

External Voltage Monitors

(for pre-regulator or external

power rails)

VCCA BUCK1 BUCK2 BUCK3 BUCK4 BUCK5 LDO1

LDO2

LDO3

LDO4

Recovery Counter Limit to FSM

OR

function

WD error N or Long Window to FSM

Severe Global

Error

MCU Rail Group

SoC Rail Group

Other Rail Group

WD error M (M>N) to FSM

SoC Error Monitor to FSM

MCU Error Monitor to FSM

Mask

Moderate Global

Error

IMMEDIATE

SHUTDOWN trigger

input to FSM

Immediate Shutdown Trigger Mask

Orderly Shutdown Trigger Mask

MCU Power Error Trigger Mask

SoC Power Error Trigger Mask

ORDERLY

SHUTDOWN trigger

input to FSM

MCU Power

Error Signal

SoC Power

Error Signal

Figure 10-40. Error Source Hierarchical Mask System

Figure 10-42 shows an example of how the PFSM engine utilizes instructions to execute the configured device

state and sequence transitions of the mission state-machine. Table 10-12 provides the instruction set and usage

description of each instruction in the following sections. Section 10.4.1.2.2 describes how the instructions are

stored in the NVM memory.

Table 10-12. Configurable FSM Instruction set

Command Opcode

"0000"

Command

REG_WRITE_MASK_PAGE0_IMM

REG_WRITE_IMM

Command Description

Write the specified data, except the masked bits, to the specified

page 0 register address.

"0001"

Write the specified data to the specified register address.

Write the specified data, except the masked bits, to the specified

register address.

"0010"

REG_WRITE_MASK_IMM

Write the target voltage of a specified regulator after a specified

delay.

"0011"

"0100"

"0101"

"0110"

REG_WRITE_VOUT_IMM

REG_WRITE_VCTRL_IMM

REG_WRITE_MASK_SREG

SREG_READ_REG

Write the operation mode of a specified regulator after a specified

delay.

Write the data from a scratch register, except the masked bits, to

the specified register address.

Write scratch register (REG0-3) with data from a specified

address.

Execution is paused until the specified type of the condition is met

or timed out.

"0111"

"1000"

"1001"

WAIT

DELAY_IMM

DELAY_SREG

Delay the execution by a specified time.

Delay the execution by a time value stored in the specified scratch

register.

Set a trigger destination address for a given input signal or

condition.

"1010"

TRIG_SET

"1011"

"1100"

TRIG_MASK

END

Sets a trigger mask that determines which triggers are active.

Mark the final instruction in a sequential task.

Write the specified data to the BIT_SEL location of the specified

page 0 register address.

"1101"

"1110"

REG_WRITE_BIT_PAGE0_IMM

REG_WRITE_WIN_PAGE0_IMM

Write the specified data to the SHIFT location of the specified

page 0 register address.

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Table 10-12. Configurable FSM Instruction set (continued)

Command Opcode

Command

Command Description

"1111"

SREG_WRITE_IMM

Write the specified data to the scratch register (REG0-3).

10.4.1.2.1 PFSM Commands

Following section describes each PFSM command in detail and provides example usage codes. More

information on example NVM configuration, available device options and documentations can be found at Fully

Customizable Integrated Power.

10.4.1.2.1.1 REG_WRITE_IMM Command

Description: Write the specified data to the specified register address

Assembly command: REG_WRITE_IMM [ADDR=]<Address> [DATA=]<Data>

Address and Data can be in any literal integer format (decimal, hex, and so forth).

'ADDR=' and 'DATA=' are optional. When included, the parameters can be in any order.

Examples:

•

REG_WRITE_IMM 0x1D 0x55 — Write value 0x55 to address 0x1D

REG_WRITE_IMM ADDR=0x10 DATA=0xFF — Write value 0xFF to address 0x10

REG_WRITE_IMM DATA=0xFF ADDR=0x10 — Write value 0xFF to address 0x10

10.4.1.2.1.2 REG_WRITE_MASK_IMM Command

Description: Write the specified data, except the masked bits, to the specified register address

Assembly command: REG_WRITE_MASK_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask>

Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth).

'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order.

Examples:

•

REG_WRITE_MASK_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at address

0x1D

REG_WRITE_MASK_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4 bits of the

register at address 0x10

REG_WRITE_MASK_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4 bits of the

register at address 0x10

10.4.1.2.1.3 REG_WRITE_MASK_PAGE0_IMM Command

Description: Write the specified data, except the masked bits, to the specified page 0 register address

Assembly

command:

REG_WRITE_MASK_PAGE0_IMM

[ADDR=]<Address>

[DATA=]<Data>

[MASK=]<Mask>

Address, Data, and Mask can be in any literal integer format (decimal, hex, and so forth).

'ADDR=', 'DATA=', and 'MASK=' are optional. When included, the parameters can be in any order.

Examples:

•

REG_WRITE_MASK_PAGE0_IMM 0x1D 0x80 0xF0 — Write 0b1000 to the upper 4 bits of the register at

address 0x1D

REG_WRITE_MASK_PAGE0_IMM ADDR=0x10 DATA=0x0F MASK=0xF0 — Write 0b1111 to the lower 4

bits of the register at address 0x10

REG_WRITE_MASK_PAGE0_IMM DATA=0x0F MASK=0xF0 ADDR=0x10 — Write 0b1111 to the lower 4

bits of the register at address 0x10

10.4.1.2.1.4 REG_WRITE_BIT_PAGE0_IMM Command

Description: Write the specified data to the BIT_SEL location of the specified page 0 register address

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Assembly command: REG_WRITE_BIT_PAGE0_IMM [ADDR=]<Address> [BIT=]<Bit> [DATA=]<Data>

Address, Bit, and Data can be in any literal integer format (decimal, hex, and so forth).

'ADDR=', 'BIT=', and 'DATA=' are optional. When included, the parameters can be in any order.

Examples:

•

REG_WRITE_BIT_PAGE0_IMM 0x1D 7 0 — Write '0' to bit 7 of the register at address 0x1D

REG_WRITE_BIT_PAGE0_IMM ADDR=0x10 BIT=3 DATA=1 — Write 0b1 to bit 3 of the register at address

0x10

10.4.1.2.1.5 REG_WRITE_WIN_PAGE0_IMM Command

Description: Write the specified data to the SHIFT location of the specified page 0 register address

Assembly command: REG_WRITE_WIN_PAGE0_IMM [ADDR=]<Address> [DATA=]<Data> [MASK=]<Mask>

[SHIFT=]<Shift>

Address, Data, Mask, and Shift can be in any literal integer format (decimal, hex, and so forth).

'ADDR=', 'DATA=', 'MASK=', and 'SHIFT=' are optional. When included, the parameters can be in any order.

Examples:

•

REG_WRITE_WIN_PAGE0_IMM ADDR=0x1D DATA=0x8 MASK=0x13 SHIFT=2 — Write bits 5:4 to 0b10

to the register at address 0x1D. Data and mask give 5-bit value 0bx10xx. This is then left shifted 2 bits to give

full byte value of 0bxx10xxxx, hence sets bits 5:4 to 0b10.

10.4.1.2.1.6 REG_WRITE_VOUT_IMM Command

Description: Write the target voltage of a specified regulator after a specified delay. This is a spin-off of the

REG_WRITE_IMM command with the intention to save instruction bits.

Assembly

command:

REG_WRITE_VOUT_IMM

[REGULATOR=]<Regulator

ID>

[SEL=]<VSEL>

[VOUT=]<Vout> [DELAY=]<Delay>

'REGULATOR=', ''SEL=', 'VOUT=', and 'DELAY=' are options. When included, the parameters can be in any

order.

Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4.

VSEL selects the BUCKn_VSET1 or BUCKn_VSET2 bits which the command will write to if Regulator ID is

BUCK1-5. It is defined as: '0': BUCKn_VSET1, '1': BUCKn_VSET2, '2': Currently Active BUCKn_VSET, '3':

Currently Inactive BUCKn_VSET. If Regulator ID is LDO1-4, VSEL value is ignored.

VOUT = output voltage in mV or V. Unit must be listed.

DELAY = delay time in ns, µs, ms, or s. If there are no units, it must be an integer value between 0-63, which will

become the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP.

Delay value will be rounded to the nearest achievable delay time based on the current step size. Current step

size will default to the NVM setting or a SET_DELAY value from a previous command in the same sequence.

Assembler will report an error if the step size is too large or too small to meet the delay.

Examples:

•

REG_WRITE_VOUT_IMM BUCK3 2 1.05 V 100 µs — Sets BUCK3 to 1.05 V by updating the active

BUCK3_VSET register after 100 µs

•

REG_WRITE_VOUT_IMM REGULATOR=LDO1 SEL=0 VOUT=700 mV DELAY=6 ms — Sets LDO1 to 700

mV after 6 ms.

10.4.1.2.1.7 REG_WRITE_VCTRL_IMM Command

Description: Write the operation mode of a specified regulator after a specified delay. This is a spin-off of the

REG_WRITE_IMM command with the intention to save instruction bits.

Assembly command: REG_WRITE_VCTRL_IMM [REGULATOR=]<Regulator ID> [VCTRL=]<VCTRL>

[MASK=]<Mask> [DELAY=]<Delay> [DELAY_MODE=]<Delay Mode>

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'REGULATOR=', 'VCTRL=', 'MASK=', and 'DELAY=' are options. When included, the parameters can be in any

order.

Regulator ID = BUCK1, BUCK2, BUCK3, BUCK4, BUCK5, LDO1, LDO2, LDO3, or LDO4.

VCTRL = 0-15, in hex, decimal, or binary format. Data to write to the following regulator control fields: BUCKs:

BUCKn_PLDN, BUCKn_VMON_EN, BUCKn_VSEL, BUCKn_FPWM_MP, BUCKn_FPWM, and BUCKn_EN.

LDOs: LDOn_PLDN, LDOn_VMON_EN, 0, 0, LDOn_EN.

DELAY = delay time in ns, µs, ms, or s. If there is no units, it must be an integer value between 0-63, which will

become the threshold count for the counter running a step size specified in the register PFSM_DELAY_STEP.

Delay value will be rounded to the nearest achievable delay time based on the current step size. Current step

size will default to the NVM setting or a SET_DELAY value from a previous command in the same sequence.

Assembler will report an error if the step size is too large or too small to meet the delay.

Delay Mode must be one of the below options: MATCH_EN = 0 (Delay if VCTRL enable bit mismatches)

MATCH_ALL = 1 (Delay if any VCTRL bits mismatch) ALWAYS = 2 (Delay always)

Examples:

•

REG_WRITE_VCTRL_IMM BUCK3 0x00 0xE0 100 µs — Sets BUCK3 to OFF (VCTRL bits = 0b00000)

after 100 µs

•

REG_WRITE_VCTRL_IMM REGULATOR=LDO1 VCTRL=0x09 MASK=0x36 DELAY=10 ms — Set

LDO1_VMON and LDO1_EN to '1' after 10 ms

10.4.1.2.1.8 REG_WRITE_MASK_SREG Command

Description: Write the data from a scratch register, except the masked bits, to the specified register address

Assembly command: REG_WRITE_MASK_SREG [REG=]<Scratch Register> [ADDR=]<Address>

[MASK=]<Mask>

'REG=', 'ADDR=', and 'MASK=' are options. When included, the parameters can be in any order.

Scratch Register can be R0, R1, R2, or R3.

Address and Mask can be in any literal integer format (decimal, hex, and so forth).

Examples:

•

REG_WRITE_MASK_SREG R2 0x22 0x00 — Write the content of scratch register 2 to address 0x22

REG_WRITE_MASK_SREG REG=R0 ADDR=0x054 MASK=0xF0 — Write the lower 4 bits of scratch

register 0 to address 0x54

10.4.1.2.1.9 SREG_READ_REG Command

Description: Write scratch register (REG0-3) with data from a specified address

Assembly command: SREG_READ_REG [REG=]<Scratch Register> [ADDR=]<Address>

'REG=' and 'ADDR=' are options. When included, the parameters can be in any order.

Scratch Register can be R0, R1, R2, or R3.

Address can be in any literal integer format (decimal, hex, and so forth).

Examples:

•

SREG_READ_REG R2 0x15 — Read the content of address 0x15 and write the data to scratch register 2

SREG_READ_REG ADDR=0x077 REG=R3 — Read the content of address 0x77 and write the data to

scratch register 3

10.4.1.2.1.10 SREG_WRITE_IMM Command

Description: Write the specified data to the scratch register (REG0-3)

Assembly command: SREG_WRITE_IMM [REG=]<Register> [DATA=]<Data>

Data can be in any literal integer format (decimal, hex, and so forth).

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Register can be R0, R1, R2, or R3.

'REG=' and 'DATA=' are options. When included, the parameters can be in any order.

Examples:

•

SREG_WRITE_IMM R2 0x15 — Write 0x15 to scratch register 2

SREG_WRITE_IMM ADDR=0x077 REG=R3 — Read 0x77 to scratch register 3

10.4.1.2.1.11 WAIT Command

Description: Wait upon a condition of a given type. Execution is paused until the specified type of the condition is

met or timed out

Assembly

command:

WAIT

[COND=]<Condition>

[TYPE=]<Type>

[TIMEOUT=]<Timeout>

[DEST=]<Destination>

Alternative assembly command: JUMP [DEST=]<Destination>

'COND=', 'TYPE=', 'TIMEOUT=', and 'DEST=' are options. When included, the parameters can be in any order.

Condition are listed in Table 10-13. Examples: GPIO1, BUCK1_PG, I2C_1

Type = LOW, HIGH, RISE, or FALL

Timeout = timeout value in ns, µs, ms, or s. If there is no units, it must be an integer value between 0-63.

Timeout value will be rounded to the nearest achievable time based on the current step size. Current step

size will default to the NVM setting or a SET_DELAY value from a previous command in the same sequence.

Assembler will report an error if the step size is too large or too small to meet the delay.

Destination = Label to jump to if when timeout occurs. Destination must be after the WAIT statement in memory.

Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1'

indicates the destination address is external and represents a FSM state ID.

When using the jump command, this will be an unconditional jump. The command will be compiled as "WAIT

COND=63 TYPE=LOW TIMEOUT=0 DEST=<Destination>". Condition 63 is a hardcoded 1, so the condition is

never satisfied and will always timeout. Therefore the command will always jump to the destination.

Examples:

•

WAIT GPIO4 RISE 1 s <Destination> 0 — Wait to execute the command at the specified SRAM address

when a rise edge is detected at GPIO4, or after 1 second

•

WAIT COND=BUCK1_PG TYPE=HIGH TIMEOUT=500 µs DEST=<mcu2act_seq> — Wait to execute the

commands at <mcu2act_seq> address as soon as BUCK1 output is within power_good range, or after 500

µs

Table 10-13. WAIT Command Conditions

COND_ Condition Name

SEL

COND_ Condition Name

SEL

COND_ Condition Name

SEL

COND_ Condition Name

SEL

0

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

BUCK1_PG

16

17

18

19

20

21

22

23

24

25

26

27

LDO1_PG

LDO2_PG

LDO3_PG

LDO4_PG

PGOOD

TWARN_EVENT

INTERRUPT_PIN

N/A

32

33

34

35

36

37

38

39

40

41

42

43

I2C_0

48

49

50

51

52

53

54

55

56

57

58

59

LP_STANDBY_SEL

1

I2C_1

N/A

2

I2C_2

3

I2C_3

4

I2C_4

5

I2C_5

6

I2C_6

7

I2C_7

8

N/A

SREG0_0

SREG0_1

SREG0_2

SREG0_3

9

N/A

10

11

N/A

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Table 10-13. WAIT Command Conditions (continued)

COND_ Condition Name

SEL

COND_ Condition Name

SEL

COND_ Condition Name

SEL

COND_ Condition Name

SEL

12

13

14

15

BUCK2_PG

BUCK3_PG

BUCK4_PG

BUCK5_PG

28

29

30

31

N/A

44

45

46

47

SREG0_4

SREG0_5

SREG0_6

SREG0_7

60

N/A

0

61

62

63

1

10.4.1.2.1.12 DELAY_IMM Command

Description: Delay the execution by a specified time

Assembly command: DELAY_IMM <Delay>

Delay = delay time in ns, µs, ms, or s. If there is no units, it must be an integer value between 0-63. Delay value

will be rounded to the nearest achievable time based on the current step size. Current step size will default to the

NVM setting or a SET_DELAY value from a previous command in the same sequence. Assembler will report an

error if the step size is too large or too small to meet the delay.

Examples:

•

DELAY_IMM 100 µs — Delay execution by 100 µs

DELAY_IMM 10 ms — Delay execution by 10 ms

DELAY_IMM 8 — Delay execution by 8 ticks of the current PFSM time step

10.4.1.2.1.13 DELAY_SREG Command

Description: Delay the execution by a time value stored in the specified scratch register.

Assembly command: DELAY_SREG <Register>

Register can be R0, R1, R2, or R3.

Examples:

•

DELAY_SREG R0 — Delay execution by the time value stored in scratch register0

10.4.1.2.1.14 TRIG_SET Command

Description: Set a trigger destination address for a given input signal or condition. These commands must be

defined at the beginning of PFSM configuration memory.

Assembly

command:

TRIG_SET

[DEST=]<Destination>

[ID=]<Trig_ID>

[SEL=]<Trig_sel>

[TYPE=]<Trig_type> [IMM=]<IMM> [EXT=]<Memory space>

'DEST=', 'ID=', 'SEL='. 'TYPE=', 'IMM=', and 'EXT=' are options. When included, the parameters can be in any

order.

Destination is the label where this trigger should start executing.

Trig_ID is the ID of the hardware trigger module to be configured (value range 0-27). They must be defined in

numeric order based on the priority of the trigger.

Trig_Sel is the 'Trigger Name' from the Table 10-15. This is the trigger signal to be associated with the specified

TRIG_ID.

Trig_type = LOW, HIGH, RISE, or FALL.

IMM can be either '0' or '1'. = '0' if the trigger is not activated until the END command of a given task; '1' if the

trigger is activated immediately and can abort a sequence.

REENTRANT can be either '0' or '1'. '1' permits a trigger to return to the current state, which allows a self-

branching trigger to execute the current sequence again.

Memory space can be either '0' or '1'. '0' indicates the destination address is in the PFSM memory space. '1'

indicates the destination address is external and represents a FSM state ID.

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Examples:

•

TRIG_SET seq1 20 GPIO_1 LOW 0 0 — Set trigger 20 to be GPIO_1=Low, not immediate. When triggered,

start executing at ‘seq1’ label.

•

TRIG_SET DEST=seq2 ID=15 SEL=WD_ERROR TYPE=RISE IMM=0 EXT=0 — Set trigger 15 to be rising

WD_ERROR trigger, not immediate. When triggered, start executing at ‘seq2’ label.

10.4.1.2.1.15 TRIG_MASK Command

Description: Sets a trigger mask that determines which triggers are active. Setting a ‘0’ enables the trigger,

setting a ‘1’ disables (masks) the trigger.

Assembly command: TRIG_MASK <Mask value>

Mask Value = 28-bit mask in any literal integer format (decimal, hex, and so forth).

Examples:

•

TRIG_MASK 0x5FF82F0 — Set the trigger mask to 0x5FF82F0

10.4.1.2.1.16 END Command

Table 10-14 shows the format of the END commands.

Table 10-14. END Command Format

Bit[3:0]

CMD

4 bits

Description: Marks the final instruction in a sequential task

Fields:

•

CMD: Command opcode (0xC)

Assembly command: END

10.4.1.2.2 Configuration Memory Organization and Sequence Execution

The configuration memory is loaded from EEPROM into an SRAM. Figure 10-41 shows an example

configuration memory with only two configured sequences.

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pfsm_start:

TRIG_SET DEST=sequence_name1 ID=0 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

TRIG_SET DEST=sequence_name2 ID=1 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

TRIG_SET DEST=sequence_name3 ID=2 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

TRIG_SET DEST=sequence_name4 ID=4 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

TRIG_SET DEST=sequence_name5 ID=4 SEL=trigger_name TYPE=high/low/rise/fall IMM=0/1 EXT=0/1

……

TRIG_MASK 0xFFFFFF0

END

sequence_name1

These TRIG_SET instructions are used to

define the trigger types which initiates each

power state sequence. There are a total of

28 TRIG_SET available for each PMIC. TYPE

parameter defines the type of trigger as:

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

DELAY_IMM delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

TRIG_MASK 0xFC00EDF

END

……

sequence_name4

High: active high (level sensitive)

Low: active low (level sensitive)

Rise: active high (edge sensitive)

Fall: active low (edge sensitive)

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

DELAY_IMM delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

DELAY_IMM delay_time

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

REG_WRITE_VCTRL_IMM REGULATOR=regulator VCTRL=ctrl_setting MASK=mask_setting DELAY=delay_time

REG_WRITE_MASK_IMM ADDR=register_addr DATA=data MASK=mask_setting

TRIG_MASK 0xFEF6EDC

END

Figure 10-41. Configuration Memory Script Example

As soon as the PMIC state reaches the mission states, it will start reading from the configuration memory until

it hits the first END command. Setting up the triggers (1-28) should be the first section of the configuration

memory, as well as the first set of trigger configurations. The trigger configurations are read and mapped to

an internal lookup table, which contains the starting address associated with each trigger in the configuration

memory. If the trigger destination is an FFSM state then the address contains the fixed state value. After the

trigger configurations are read and mapped into the SRAM, these triggers control the execution flow of the state

transitions. The signal source of each trigger is listed under Table 10-15.

When a trigger or multiple triggers are activated, the PFSM execution engine looks up the starting address

associated with the highest priority trigger which is unmasked, and starts executing commands until it hits an

END command. The last commands before END statement will generally be the TRIG_MASK command, which

directs the PFSM to a new set of unmasked trigger configurations, and the trigger with the highest priority in the

new set will be serviced next. Trigger priority is determined by the Trigger ID associated with each trigger. The

priority of the trigger decreases as the associated trigger ID increases. As a result the critical error triggers are

usually located at the lowest trigger IDs.

The TRIG_SET commands specify if a trigger is immediate or non-immediate. Immediate triggers are serviced

immediately, which involves branching from the current sequence of commands to reach a new target

destination. The non-immediate triggers are accumulated and serviced in the order of priority through the

execution of each given sequence until the END command in reached. Therefore the trigger ID assignment for

each trigger can be arranged to produce the desired PFSM behavior.

The TRIG_MASK command determines which triggers are active at the end of each sequence, and is usually

placed just before the END instruction. The TRIG_MASK takes a 28 bit input to allow any combination of

triggers to be enabled with a single command. Through the definition of the active triggers after each seqeunce

execution the TRIG_MASK command can be conceptualized as establishing a power state.

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The above sequence of waiting for triggers and executing the sequence associated with an activated trigger

is the normal operating condition of the PFSM execution engine when the PMIC is in the MISSION state. The

FFSM state machine will take over control from the execution engine any time an event occurs that requires a

transition from the MISSION state of the PMIC to a fixed device state.

Table 10-15. PFSM Trigger Selections

Trigger Name

Trigger Source

An error event causes one of the triggers defined in the FSM_TRIG_SEL_1/2 register to activate, and

the inteded action for the activated trigger is to immediate shutdown the device

IMMEDIATE_SHUTDOWN

MCU_POWER_ERROR

ORDERLY_SHUTDOWN

Output failure detection from a regulator which is assigned to the MCU rail group (x_GRP_SEL = '01')

An event which causes MODERATE_ERR_INT = '1'

nPWRON long-press event when NPOWRON_SEL = '01', or ENABLE = '0' when NPOWERON_SEL =

'00'

FORCE_STANDBY

SPMI_WD_BIST_DONE

ESM_MCU_ERROR

WD_ERROR

Completion of SPMI WatchDog BIST

An event which causes ESM_MCU_FAIL_INT

An event which causes WD_INT

SOC_POWER_ERROR

ESM_SOC_ERROR

Output failure detection from a regulator which is assigned to the SOC rail group (x_GRP_SEL = '10')

An event which causes ESM_SOC_FAIL_INT

NSLEEP2 and NSLEEP1 = '11'. More information regarding the NSLEEP1 and NSLEEP2 functions

can be found under Section 10.4.1.2.4.3

A

WKUP1

A rising or falling edge detection on a GPIO pin which is configured as WKUP1 or LP_WKUP1

A valid On-Request detection when STARTUP_DEST = '11'

SU_ACTIVE

NSLEEP2 and NSLEEP1 = '10'. More information regarding the NSLEEP1 and NSLEEP2 functions

can be found under Section 10.4.1.2.4.3

B

WKUP2

A rising or falling edge detection on a GPIO pin which is configured as WKUP2 or LP_WKUP2

A valid On-Request detection when STARTUP_DEST = '10'

SU_MCU_ONLY

NSLEEP2 and NSLEEP1 = '01', More information regarding the NSLEEP1 and NSLEEP2 functions

can be found under Section 10.4.1.2.4.3

C

D

NSLEEP2 and NSLEEP1 = '00'. More information regarding the NSLEEP1 and NSLEEP2 functions

can be found under Section 10.4.1.2.4.3

SU_STANDBY

SU_X

A valid On-Request detection when STARTUP_DEST = '00'

A valid On-Request detection when STARTUP_DEST = '01'

PFSM WAIT command condition timed out. More information regarding the WAIT command can be

found under Section 10.4.1.2.1.11

WAIT_TIMEOUT

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

I2C_0

Input detection at GPIO1 pin

Input detection at GPIO2 pin

Input detection at GPIO3 pin

Input detection at GPIO4 pin

Input detection at GPIO5 pin

Input detection at GPIO6 pin

Input detection at GPIO7 pin

Input detection at GPIO8 pin

Input detection at GPIO9 pin

Input detection at GPIO10 pin

Input detection at GPIO11 pin

Input detection of TRIGGER_I2C_0 bit

Input detection of TRIGGER_I2C_1 bit

Input detection of TRIGGER_I2C_2 bit

Input detection of TRIGGER_I2C_3 bit

Input detection of TRIGGER_I2C_4 bit

Input detection of TRIGGER_I2C_5 bit

I2C_1

I2C_2

I2C_3

I2C_4

I2C_5

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Table 10-15. PFSM Trigger Selections (continued)

Trigger Name

Trigger Source

I2C_6

Input detection of TRIGGER_I2C_6 bit

Input detection of TRIGGER_I2C_7 bit

I2C_7

SREG0_0

SREG0_1

SREG0_2

SREG0_3

SREG0_4

SREG0_5

SREG0_6

SREG0_7

0

Input detection of SCRATCH_PAD_REG_0 bit 0

Input detection of SCRATCH_PAD_REG_0 bit 1

Input detection of SCRATCH_PAD_REG_0 bit 2

Input detection of SCRATCH_PAD_REG_0 bit 3

Input detection of SCRATCH_PAD_REG_0 bit 4

Input detection of SCRATCH_PAD_REG_0 bit 5

Input detection of SCRATCH_PAD_REG_0 bit 6

Input detection of SCRATCH_PAD_REG_0 bit 7

Always '0'

1

Always '1'

10.4.1.2.3 Mission State Configuration

The Mission States portion of the FSM engine manages the sequencing of power rails and external outputs in

the user defined states. The rest of Section 10.4.1 will use Figure 10-42 as an example state machine which is

defined through the configuration memory using the configuration FSM instructions.

To LP_STANDBY

To Safe Recovery

State

Severe or

Moderate PFSM

Errors

From any

Operation States

LP_STAND

=1

BY_SEL

Immediate or Orderly

Shutdown Condition

Detected

Valid On Request and

STANDBY

STARTUP_DEST[1:0] = 0x00

Valid On Request and

OFF request

STARTUP_DEST[1:0] = 0x03

Warm Reset triggered by

ESM or WDOG error

Valid On Request and

STARTUP_DEST[1:0] = 0x02

OFF request

ACTIVE

OFF request

WKUP1 0W1 or

NSLEEP1

NSLEEP2&NSLEEP1

11W10

0W1

NSLEEP2

1:0

WKUP1 0W 1 or

NSLEEP2&NSLEEP1

00W11

MCU ONLY

WKUP2 0W 1 or

NSLEEP2&NSLEEP1

00W10

NSLEEP2

1:0

Warm Reset triggered by

ESM or WDOG error

DEEP SLEEP

/S2R

Figure 10-42. Example of a Mission State-Machine

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Each power state (light blue bubbles in Figure 10-42) defines the ON or OFF state and the sequencing timing

of the external regulators and GPIO outputs. This example defines 4 power states: STANDBY, ACTIVE, MCU

ONLY, and DEEP_SLEEP/S2R states. The priority order of these states will be the following:

1. ACTIVE

2. MCU ONLY

3. DEEP SLEEP/S2R

4. STANDBY

The transitions between each power state is determined by the trigger signals source pre-selected from Table

10-15. These triggers are then placed in the order of priority through the trigger ID assignment of each trigger

source. The critical error triggers are placed first, some specified as immediate triggers that can interrupt an

on-going sequence. The non-error triggers, which are used to enable state transtions during normal device

operation, are then placed according to the priority order of the state the device is transitioning to. Table 10-16

list the trigger signal sources, in the order of priority, used to define the power states and transitions of the

example mission state machine shown in Figure 10-42. This table also helps to determine which triggers should

be masked by the TRIG_MASK command upon arriving a pre-defined power state to produce the desired PFSM

behavior.

Table 10-16. List of Trigger Used in Example Mission State Machine

Trigger ID

Trigger Masked In Each User Defined Power State

Trigger Signal

State Transitions

DEEP

SLEEP / S2R

STANDBY

ACTIVE

MCU ONLY

0

1

2

3

IMMEDIATE_SHUTDOWN ⁽¹⁾

MCU_POWER_ERROR ⁽¹⁾

ORDERLY_SHUTDOWN ⁽¹⁾

TRIGGER_FORCE_STANDBY

From any state to SAFE

RECOVERY

From any state to SAFE

RECOVERY

From any state to SAFE

RECOVERY

From any state

to STANDBY or

LP_STANDBY

Masked

4

5

6

WD_ERROR

Perform warm reset of all

power rails and return to

ACTIVE

Masked

ESM_MCU_ERROR

ESM_SOC_ERROR

Perform warm reset of all

power rails and return to

ACTIVE

Perform warm reset of

power rails in SOC

domain and return to

ACTIVE

Masked

7

8

WD_ERROR

Perform warm reset of all

power rails and return to

MCU ONLY

Masked

ESM_MCU_ERROR

Perform warm reset of all

power rails and return to

MCU ONLY

9

SOC_POWER_ERROR

ACTIVE to MCU ONLY

Start RUNTIME_BIST

Masked

10

11

TRIGGER _I2C_1 (self-cleared)

TRIGGER_I2C_2 (self-cleared)

Enable I2C CRC

Function

Masked

12

13

14

TRIGGER_SU_ACTIVE

TRIGGER_WKUP1

STANDBY to ACTIVE

Any State to ACTIVE

TRIGGER_A (NSLEEP2&NSLEEP1 MCU ONLY or DEEP

= '11')

Masked

SLEEP/S2R to ACTIVE

15

TRIGGER_SU_MCU_ONLY

STANDBY to MCU ONLY

Masked

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Table 10-16. List of Trigger Used in Example Mission State Machine (continued)

Trigger ID

Trigger Masked In Each User Defined Power State

Trigger Signal

State Transitions

DEEP

SLEEP / S2R

STANDBY

ACTIVE

MCU ONLY

16

17

18

TRIGGER_WKUP2

STANDBY or DEEP

SLEEP/S2R to MCU

ONLY

Masked

TRIGGER_B (NSLEEP2&NSLEEP1 ACTIVE or DEEP

= '10')

SLEEP/S2R to MCU

ONLY

Masked

TRIGGER_D or TRIGGER_C

(NSLEEP2 = '0' )

ACTIVE or MCU ONLY

to DEEP SLEEP/S2R

Masked

Mask

Masked

19

20

TRIGGER_I2C_0 (self-cleared)

Always '1' ⁽²⁾

Any state to STANDBY

STANDBY to SAFE

RECOVERY

Masked

21

22

23

24

25

26

27

Not Used

Mask

Masked

0xFF01270

Masked

0xFFC9FF0

Not Used

28-bit TRIG_MASK Value in Hex format: 0xFFE4FF8 0xFF18180

(1) This is an immediate trigger.

(2) When an error occurs, which requires the device to enter directly to the SAFE RECOVERY state, the mask for this trigger must be

removed while all other non-immediate triggers are masked. The device will leave mission states and the FFSM state machine will take

over control of the device power states once this trigger is executed.

10.4.1.2.4 Pre-Configured Hardware Transitions

There are some pre-defined trigger sources, such as on-requests and off-requests, which are constructed with

the combination of hardware input signals and register bits settings. This section provides more detail to these

pre-defined trigger sources and shows how they can be utilized in the PFSM configuration to initiate state to

state transitions.

10.4.1.2.4.1 ON Requests

ON requests are used to switch on the device, which transitions the device from the STANDBY or the

LP_STANDBY to the state specified by STARTUP_DEST[1:0].

After the device arrives at the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the

NSLEEP1 and NSLEEP2 signals accordingly before clearing the STARTUP_INT interrupt. Once the interrupt is

cleared, the device will stay or move to the next state corresponding to the NSLEEP signals state assignment as

specified in Table 10-20.

Table 10-17 lists the available ON requests.

Table 10-17. ON Requests

EVENT

MASKABLE

COMMENT

Edge sensitive

Level sensitive

DEBOUNCE

50 ms

nPWRON (pin)

ENABLE (pin)

Yes

8 µs

VCCA > VCCA_UV and FSD

unmasked

First Supply Detection (FSD)

Yes

N/A

RTC ALARM Interrupt

RTC TIMER Interrupt

Yes

N/A

8 µs

WKUP1 or WKUP2 Detection

Edge sensitive

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Table 10-17. ON Requests (continued)

EVENT

MASKABLE

COMMENT

DEBOUNCE

LP_WKUP1 or LP_WKUP2

Detection

Yes

Edge sensitive

N/A

Recover from system errors

which caused immediate or

orderly shut down of the

device

Recovery from Immediate and

Orderly Shutdown

Yes

N/A

If one of the events listed in Table 10-17 occurs, then the event powers on the device unless one of the gating

conditions listed in Table 10-18 is present.

Table 10-18. ON Requests Gating Conditions

EVENT

MASKABLE

COMMENT

VCCA_SENSE > VCCA_OVP, VSYS_DEAD_LOCK_EN = 1

VCCA < VCCA_UVLO

VCCA_OVP (event)

VCCA_UVLO (event)

VINT_OVP (event)

VINT_UVLO (event)

No

LDOVINT > 1.98 V

LDOVINT < 1.62 V

Device stays in SAFE RECOVERY until temperature decreases

below TWARN level

TSD (event)

No

The NPWRON_SEL NVM register bit determines whether the nPWRON/ENABLE pin should be treated as a

power on press button or a level sensitive enable switch. When this pin is configured as the nPWRON button, a

short button press detection will be latched internally as a device enable signal until the NPWRON_START_INT

is cleared, or a long press key event is detected. The short button press detection occurs when an falling edge is

detected at the nPWRON pin. When the NPWRON_START_MASK bit is set to '1', the device will no longer react

to the changing state of the pin as the nPWRON press button.

The nPWRON/ENABLE pin is a level sensitive pin when it is configured as an ENABLE pin, and an assertion will

enable the device until the pin is released. When the ENABLE_MASK bit is set to '1', the device will no longer

react to the changing state of the pin as the ENALBE switch.

10.4.1.2.4.2 OFF Requests

An OFF request is used to orderly switch off the device. OFF requests initiate transition from any other mission

state to the STANDBY state or the LP_STANDBY state depending on the setting of the LP_STANDBY_SEL bit.

Table 10-19 lists the conditions to generate the OFF requests and the corresponding destination state.

Table 10-19. OFF Requests

LP_STANDBY_SEL BIT

EVENT

DEBOUNCE

DESTINATION STATE

SETTING

LP_STANDBY_SEL = 0

LP_STANDBY_SEL = 1

LP_STANDBY_SEL = 0

LP_STANDBY_SEL = 1

LP_STANDBY_SEL = 0

LP_STANDBY_SEL = 1

STANDBY

LP_STANDBY

STANDBY

nPWRON (pin)

(long press key event)

8 s

ENABLE (pin)

8 µs

NA

LP_STANDBY

STANDBY

I2C_TRIGGER_0

LP_STANDBY

The long press key event occurs when the nPWRON pin stays low for longer than t_{LPK_TIME}while the device is in

a mission state.

When the nPWRON or ENABLE pin is used as the OFF request, the device must wake up from the STANDBY

or the LP_STANDBY state through the ON request initiated by the same pin. The NPWRON_START_MASK or

the ENABLE_MASK must remain low in this case to allow the detection of the ON request initiated by the pin.

If the device should enter the LP_STANDBY state through the OFF request, it is important that the state of the

nPWRON or ENABLE pin must remain the same until the state transition is completed. Failure to do so may

result in unsuccessful wake up from the LP_STANDBY state when the pin re-initiates On request.

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Using the I2C_TRIGGER_0 bit as the OFF request will enable the device to wake up from the STANDBY or

the LP_STANDBY states through the detection of LP_WKUPn/WKUPn pins, as well as RTC alarm or timer

interrupts. To enable this feature, the device must set the I2C_TRIGGER_0 bit to '1' while the NSLEEPn signals

are masked, and the ON request (initialized by the nPWRON or ENABLE pins) must remain active.

10.4.1.2.4.3 NSLEEP1 and NSLEEP2 Functions

The SLEEP requests are activated through the assertion of nSLEEP1 or nSLEEP2 pins, which are the

secondary functions of the 11 GPIO pins and can be selected through GPIO configuration using the GPIOx_SEL

register bits. If the nSLEEP1 or nSLEEP2 pins are not available, the NSLEEP1B and NSLEEP2B register bits

can be configured in place for their functions. The input of nSLEEP1 pin and the state of the NSLEEP1B register

bit are combined to create the NSLEEP1 signal through an OR function. Similarly for the input of the nSLEEP2

pin and the NSLEEP2B register bit as they are combined to create the NSLEEP2 signal.

A 1 → 0 logic level transition of the NSLEEP signal generates a sleep request, while a 0 → 1 logic level

transition reverses the sleep request in the example PFSM from Figure 10-42. When a NSLEEPn signal

transitions from 1 → 0, it generates a sleep request to go from a higher power state to a lower power state.

When the signal transitions from 0 → 1, it reverses the sleep request and returns the device to the higher power

state.

The NSLEEPn_MASK bit can be used to mask the sleep request associated with the corresponding NSLEEPn

signal. When the NSLEEPn_MASK = 1, the corresponding NSLEEPn signal will be ignored. Table 10-20shows

how the combination of the NSLEEPn signals and NSLEEPn_MASK bits creates triggers A/B/C/D to the FSM to

control the power state of the device.

The states of the resources during ACTIVE, SLEEP, and DEEP SLEEP/S2R states are defined in the

LDOn_CTRL and BUCKn_CTRL registers. For each resource, a transition to the MCU ONLY or the DEEP

SLEEP/S2R states is controlled by the FSM when the resource is associated to the SLEEP or DEEP

SLEEP/S2R states.

Table 10-20 shows the corresponding state assignment based on the state of the NSLEEPn and their

corresponding mask signals using the example PFSM from Figure 10-42.

Table 10-20. NSLEEPn Transitions and Mission State Assignments

Current State

NSLEEP1

NSLEEP2

NSLEEP1 MASK NSLEEP2 MASK

Trigger to FSM

TRIGGER B

TRIGGER A

Next State

MCU ONLY

ACTIVE

DEEP SLEEP/S2R

0

0 → 1

0

1

0

1

0 → 1

Don't care

0 → 1

ACTIVE

DEEP SLEEP/S2R

or MCU ONLY

Don't care

TRIGGER A

TRIGGER D

ACTIVE

MCU ONLY

0 → 1

0

1

0

1 → 0

DEEP SLEEP

or S2R

MCU ONLY

Don't care

1 → 0

1

0

DEEP SLEEP

or S2R

TRIGGER D

TRIGGER B

TRIGGER D

ACTIVE

1 → 0

1

0

MCU ONLY

1 → 0

DEEP SLEEP

or S2R

ACTIVE

Don't care

1 → 0

1

0

1

DEEP SLEEP

or S2R

TRIGGER D

TRIGGER B

Don't care

MCU ONLY

10.4.1.2.4.4 WKUP1 and WKUP2 Functions

The WKUP1 and WKUP2 functions are activated through the edge detection on all GPIO pins. Any one of these

GPIO pins when configured as an input pin can be configured to wake up the device by setting GPIOn_SEL

bit to select the WKUP1 or WKUP2 functions. In the example PFSM depicted in Figure 10-42, when a GPIO

pin is configured as a WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable by the

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GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) will wake up the device to the ACTIVE state. Likewise

if a GPIO pin is configured as a WKUP2 pin, a detected edge will wake up the device to the MCU ONLY state.

If multiple edge detections of WKUP signals occur simultaneous, the device will go to the state in the following

priority order:

1. ACTIVE

2. MCU ONLY

When a valid edge is detected at a WKUP pin, an interrupt will be generated by the nINT pin to signal the MCU

of the wake-up event, and the GPIOx_INT interrupt bit will be set. The wake request will remain active until the

GPIOx_INT bit is cleared by the MCU. While the wake request is executing, the device will ignore any sleep

request to go to a lower power state until the corresponding GPIOx_INT interrupt bit is cleared to deactivate the

wake request. After the wake request is deactivated, the device will return to the state indicated by the NSLEEP1

and NSLEEP2 signals as shown in Table 10-20.

10.4.1.2.4.5 LP_WKUP Pins for Waking Up from LP STANDBY

The LP_WKUP functions are activated through the edge detection of LP_WKUP pins, configurable as secondary

functions of GPIO3 and GPIO4. They are specially designed to wake the device up from the LP STANDBY state

when a high speed wake up signal is detected. Similar to the WKUP1 and WKUP2 pins, when GPIO3 or GPIO4

pin is configured as an LP_WKUP1 pin, a rising or falling edge detected at the input of this pin (configurable

by the GPIOn_FALL_MASK and the GPIOn_RISE_MASK bits) will wake up the device to the ACTIVE state.

Likewise, if the pin is configured as an LP_WKUP2 pin, a detected edge will wake up the device to the MCU

ONLY state. If multiple edge detections of LP_WKUP signals occur simultaneously, the device will go to the state

in the following priority order:

1. ACTIVE

2. MCU ONLY

Note

Due to a digital control errata in the device, the ENABLE_MASK/NPWRON_START_MASK bit much

be set to '1' before the device enters LP_STANDBY state in order for the LP_WKUP2 pin to correctly

wake up the device to the MCU_ONLY state.

The TPS6594-Q1 device supports limited CAN wake-up capability through the LP_WKUP1/2 pins. When an

input signal (without deglitch) with logic level transition from high-to-low or low-to-high with a minimum pulse

width of t_{WK_PW_MIN}is detected on the assigned LP_WKUP1/2 pins, the device will wake up asynchronously and

execute the power up sequence. CAN-transceiver RXD- or INH-outputs can be connected to the LP_WKUP pin.

If RXD-output is used, it is assumed that the transceiver RXD-pin IO is powered by the transceiver itself from an

external supply when TPS6594-Q1 is in the LP_STANDBY state. If INH-signal is used it has to be scaled down

to the recommenced GPIO input voltage level specified in the electrical characteristics table.

In this PFSM example, the device can wake up from the LP_STANDBY state through the detection of LP_WKUP

pins only if it enters the LP_STANDBY state through the TRIGGER_I2C_0 OFF request while the NSLEEPn

signals are masked, and the on request initialized by the nPWRON/ENABLE pin remains active. Once a valid

wake-up signal is detected at the LP_WKUP pin, it is handled as a WAKE request. An interrupt will be generated

by the nINT pin to signal the MCU of the wake-up event, and the corresponding GPIOx_INT interrupt bit will be

set. The wake request will remain active until the interrupt bit is cleared by the MCU. Table 10-20 shows how

the device will return to the state indicated by the NSLEEP1 and NSLEEP2 signals after the wake request is

deactivated.

Figure 10-43 illustrates the valid wake-up signal at the LP_WKUP1/2 pins, and the generation and clearing of the

internal wake-up signal.

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> t_{WK_PW_MIN}

High Pulse Input at LP_WKUP pin

(GPIO3 or GPIO4)

(e.g. INH-signal)

Wake Signal Latched

on rising edge

MCU clears the

Wake interrupt

> t_{WK_PW_MIN}

Low Pulse Input at LP_WKUP pin

(GPIO3 or GPIO4)

(e.g. RXD-signal)

Wake Signal Latched

on falling edge

MCU clears the

Wake interrupt

Figure 10-43. CAN Wake-Up Timing Diagram

10.4.1.3 Error Handling Operations

The FSM engine of the TPS6594-Q1 device is designed to handle the following types of errors throughout the

operation:

•

Power Rail Output Error

Boot BIST Error

Runtime BIST Error

Catastrophic Error

Watchdog Error

Error Signal Monitor (ESM) Error

Warnings

10.4.1.3.1 Power Rail Output Error

A power rail output error occurs when an error condition is detected from the output rails of the device, which are

used to power the attached MCU or SoC. These errors include the following:

•

Rails not reaching or maintaining within the power good voltage level threshold.

A short condition that is detected at a regulator output.

The load current that exceedes the forward current limit.

The BUCKn_GRP_SEL, LDOn_GRP_SEL, and VCCA_GRP_SEL registers are used to configure the rail group

for all of the Bucks, LDOs, and the voltage monitors, which are available for external rails. The selectable rail

groups are MCU rail group, SoC rail group, or other rail group. The TPS6594-Q1 device is designed to react

differently when an error is detected from a power resource assigned to the different rail groups.

Figure 10-40 shows how the SOC_RAIL_TRIG[1:0], MCU_RAIL_TRIG[1:0], and OTHER_RAIL_TRIG[1:0]

registers are used as the Immediate Shutdown Trigger Mask, Orderly Shutdown Trigger Mask, MCU Power

Error Trigger Mask, or the SoC Power Error Trigger Mask. The settings of these register bits determine the error

handling sequence which the assigned groups of rails should take in an event of an output error. The PFSM

engine can be configured to execute the appropriate error handling sequence for the following error handling

sequence options: immediate shutdown, orderly shutdown, MCU power error, or SOC power error. For example,

if an immediate shutdown sequence is assigned to the MCU rail group through the MCU_RAIL_TRIG[1:0],

any failure detected in this group of rails will cause the IMMEDIATE_SHUTDOWN trigger to be executed.

This trigger is expected to start the immediate shutdown sequence and cause the device to enter the SAFE

RECOVERY state. The device will immediately reset the attached MCU and SoC by de-asserting the nRSTOUT

and nRSTOUT_SoC (GPO1) pins. All of the power resources assigned to the MCU and SOC will shutdown

immediately without a sequencing order. The nINT pin will signal a MCU_PWR_ERR_INT interrupt event has

occurred and the EN_DRV pin will be forced low. If the error is recoverable within the recovery time interval,

the device will increment the recovery count, return to INIT state, and reattempt the power up sequence (if

the recovery count has not exceeded the counter threshold). If the recovery count has already exceeded the

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threshold, the device will stay in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO

threshold and the device is power cycled.

The power resources assigned to the SoC rail group are typically assigned to the SOC power error handling

sequence. In this PFSM example depicted in Figure 10-42, when a power resource in this group is detected,

the PFSM will typically cause the device to execute the shutdown of all the resources assigned to the SoC

rail group, and the device will enter the MCU ONLY state. The device will immediately reset the attached SoC

by toggling the nRSTOUT_SoC (GPO1) pin. The reset output to the MCU and the resources assigned to the

MCU rail group will remain unchanged. The EN_DRV pin will also remain unchanged, and the nINT pin will

signal that an SOC_PWR_ERR_INT interrupt event has occurred. To recover from the MCU_ONLY state after

a SOC power error, the MCU software must set NSLEEP1 signal to '0' while NSLEEP2 signal remains '1'. This

action signals TPS6594-Q1 that MCU has acknowleged the SOC power error, and is ready to return to normal

operation. MCU can then set the NSLEEP1 signal back to '1' for the device to return to ACTIVE state and

reattempt the SoC power up. Refer to Section 10.4.1.2.4.3 for information regarding the setting of the NSLEEP1

and NSLEEP2 signals.

10.4.1.3.2 Boot BIST Error

Boot BIST error occurs when the device is not able to pass the BOOT BIST during device power up. Every

failure of the BOOT BIST attempt will cause the recovery count to increment as the device enters the SAFE

RECOVERY state. If the count value is smaller than the counter threshold, the device will attempt to enter the

INIT state again and reattempt the BOOT BIST until the recovery count reaches the maximum threshold. When

this occurs the device will stay in the SAFE RECOVERY state until VCCA voltage is below the VCCA_UVLO

threshold and the device is power cycled.

10.4.1.3.3 Runtime BIST Error

Runtime BIST error occurs when the device is not able to pass the Runtime BIST while the device is in an

operation state. This error creates an immediate shutdown condition, which will cause the device to execute the

immediate shutdown sequence and enter the SAFE RECOVERY state. The device will immediately reset the

attached MCU and SoC by de-asserting the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11)) pins. All of the

power resources assigned to the MCU and SOC will be immediately shutdown. The EN_DRV pin will be forced

low, and the nINT pin will be de-asserted to signal an interrupt event has occurred.

10.4.1.3.4 Catastrophic Error

Catastrophic errors are errors that affect multiple power resources such as errors detected in supply voltage,

LDOVINT supply for control logic, clocks monitors, and device temperature passing the thermal shutdown

threshold, or error detected in the SPMI communication network. These errors are grouped as the severe errors.

By setting the SEVERE_ERR_TRIG[1:0] to create an immediate or orderly shutdown condition, the PFSM will

execute the corresponding sequence for the IMMEDIATE_SHUTDOWN trigger or the ORDERLY_SHUTDOWN

trigger and enter the SAFE RECOVERY state. The device will reset the attached MCU and SoC by de-asserting

the nRSTOUT and nRSTOUT_SoC (GPO1 or GPIO11) pins. All of the power resources assigned to the MCU

and SOC will be shutdown. The nINT pin will be de-asserting to signal an interrupt event has occurred, and the

EN_DRV pin will be forced low.

10.4.1.3.5 Watchdog (WDOG) Error

Section 10.3.11 describes details about the Watchdog (WDOG) errors detection mechanisms.

10.4.1.3.6 Error Signal Monitor (ESM) Error

There are two Error Signal Monitors (ESM) available for the TPS6594-Q1 device, one designed to detect and

handle the error signals received from the attached SoC, while the other one for the attached MCU. Section

10.3.12 describes the error detection mechanisms for both monitors in detail.

10.4.1.3.7 Warnings

Warning are non-catastrophic errors. When such an error occurs while the device is in the operating states, the

device detects the error and handles the error through the interrupt handler. These are errors such as thermal

warnings, I2C, or SPI communication errors, or power resource over current limit detection while the output

voltage still maintains within the power good threshold. When these errors occur, the PFSM will pull the nINT pin

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low to signal an interrupt event has occurred. The device will remain in the operation state and no changes will

be applied to the state of the EN_DRV pin, the power resources, nor the reset outputs.

10.4.1.4 Device Startup Timing

Figure 10-44 shows the timing diagram of the TPS6594-Q1 after the first supply detection.

~2V

VSYS_SENSE

t_{VSYSOVP_INIT}

OVPGDRV

VCCA

VCCA_UVLO

t_{INIT_REF_CLK_LDO}

Reference Block &

System Clock Ready

VINT & VRTC

t_{INIT_NVM_ANALOG}

NVM

Initialization

t_{BOOT_BIST}

Boot BIST

Completion

Valid On Request

Power Sequence Time

Power Up Rail

Sequencing

Reset delay

nRSTOUT

NO SUPPLY

INIT

BOOT BIST

STANDBY

ACTIVE

Figure 10-44. Device Startup Timing Diagram

t_{VSYSOVP_INIT}is the time between VSYS detection and when the VSYS Over Voltage Protection Module is in

operation and the external protection FET connects the VSYS_SENSE to VCCA and the PVINx pins.

t_{INIT_REFCLK_LDO}is the start up time for the reference block. t_{INIT_NVM_ANALOG}is the time for the device to load

the default values of the NVM configurable registers from the NVM memory, and the start up time for the analog

circuits in the device. t_{INIT_REFCLK_LDO}and t_{INIT_NVM_ANALOG}are defined in the electrical characteristics table.

t_{BOOT_BIST}is the sum of t_ABISTrunand t_LBISTrun, which are defined in the electrical characterization tables.

The Power Sequence time is the total time for the device to complete the power up sequence. Please refer to

Section 10.4.1.5 for more details.

The reset delay time is a configurable wait time for the nRSTOUT and the nRSTOUT_SoC release after the

power up sequence is completed.

10.4.1.5 Power Sequences

A power sequence is an automatic preconfigured sequence the TPS6594-Q1 device applies to its resources,

which include the states of the BUCKs, LDOs, 32-kHz clock, and the GPIO output signals. For a detailed

description of the GPIOs signals, please refer to Section 10.3.7.

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Figure 10-45 shows an example of a power up transition followed by a power down transition. The power up

sequence is triggered through a valid on request, and the power down sequence is trigger by a valid off request.

The resources controlled (for this example) are: BUCK3, LDO1, BUCK2, LDO2, GPIO1, LDO4, and LDO3. The

time between each resource enable and disable (TinstX) is also part of the preconfigured sequence definition.

When a resource is not assigned to any power sequence, it remains in off mode. The MCU can enable and

configure this resource independently when the power sequence completes.

Power Up Sequence

Power Down Sequence

Valid On

Request

X

Valid Off

Request

X

BUCK3

LDO1

t_(inst16)

t_(inst1)

t_(inst15)

t_(inst14)

t_(inst2)

BUCK2

t_(inst3)

t_(inst4)

t_(inst5)

t_(inst6)

LDO2

REGEN1

LDO4

t_(inst13)

t_(inst12)

t_(inst11)

LDO3

t_(inst7)

t_(inst8)

t_(inst10)

t_(inst9)

GPIO7

nRSTOUT/

nRSTOUT_SoC

Figure 10-45. Power Sequence Example

As the power sequences of the TPS6594-Q1 device are defined according to the processor requirements, the

total time for the completion of the power sequence will vary across various system definitions.

10.4.1.6 First Supply Detection

The TPS6594-Q1 device can be configured to automatically start up from a first supply-detection (FSD)

event detection. This feature is enabled by setting the FSD_MASK register bit to '0', and setting the

NPWRON_SEL[1:0] registers bits to '10' or '11' to mask the functionality of the nPWRON/ENABLE pin. When the

device is powered up from the NO SUPPLY state, the FSD detection is validated after the NVM default for this

feature is loaded into the device memory.

When the FSD feature is enabled, the PMIC immediately powers up from the NO SUPPLY state to an operation

state, configured by the STARTUP_DEST[1:0] bits when VCCA > VCCA_UV, while VCCA_UV gating is

performed, and only when VCCA voltage monitoring is enabled (VCCA_VMON_EN = 1). After the device arrives

the corresponding STARTUP_DEST[1:0] operation state, the MCU must setup the NSLEEP1 and NSLEEP2

signals accordingly before clearing the FSD_INT interrupt. Once the interrupt is cleared, the device will stay or

move to the destination state according to the state of the NSLEEP1/2 signals as specified in Table 10-20.

10.4.1.7 Register Power Domains and Reset Levels

The TPS6594-Q1 registers are defined by the following categories:

•

LDOVINT registers

LDOVRTC registers

LDOVINT The LDOVINT registers are powered by the internal LDOVINT, and retain their values until the

registers

device enters the LP_STANDBY state or the BACKUP state after the device was fully powered

up and in operation. When this occurs, LDOVINT is powered off, and the content of all LDOVINT

registers will be lost (including the VSET registers), which stores the default output voltage levels

for all of the external power rails. As the device re-enters the INIT state from a wake up signal or

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an On-request, the registers powered by the LDOVINT will be re-written with the default values. All

registers in the device, except the LDOVRTC registers, are powered by LDOVINT.

LDOVRTC The LDOVRTC registers retains their values until a Power-On-Reset (POR) occurs. POR occurs

registers

when the device loses supply power and enters the NO SUPPLY state. When this occurs,

LDOVRTC is powered off, and the content of all LDOVRTC registers will be lost.

Following are the LDOVRTC registers:

•

All RTC registers

RTC and Crystal Oscillator bits

Status registers for the following events: TSD and RTC reset

Control registers for PWRON/ENABLE, GPIO3, and GPIO4 pins (for wake signal monitor

during LP_STANDBY state)

Following interrupt registers:

– FSD_INT

•

– RECOV_CNT_INT

– TSD_ORD_INT

– TSD_IMM_INT

– PFSM_ERR_INT

– VCCA_OVP_INT

– ESM_MCU_RST_INT

– ESM_SOC_RST_INT

– WD_RST_INT

– WD_LONGWIN_TIMEOUT_INT

– NPWRON_LONG_INT

10.4.2 Multi-PMIC Synchronization

A multi-PMIC synchronization scheme is implemented in the TPS6594-Q1 device to synchronize the power

state changes with other PMIC devices. This feature consolidates and simplifies the IO control signals required

between the application processor or the microcontroller and multiple PMICs in the system. The control interface

consists of an SPMI protocol which communicates the next power state information from the primary TPS6594-

Q1 device to up to 5 secondary PMICs, and receives feedback signal from the secondary PMICs to indicate any

error condition. Figure 10-46 is the block diagram of the power state synchronization scheme. The TPS6594-Q1

is represented as the primary PMIC in this block diagram, which is responsible for broadcasting the synchronous

system power state data, and processing the error feedback signals from the secondary PMICs. It is the primary

device in the SPMI interface bus.

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Synchronous-System Power-State Data

Error Feedback

Primary PMIC

Secondary PMIC

Sequencing and Power

State Configurations in

Nonvolatile Memory

Sequencing and Power

State Configurations in

Nonvolatile Memory

Sequencing and Power

State Configurations in

Nonvolatile Memory

Power-State

Sequencer

Controller

Power-State

Sequencer

Controller

Power-State

Sequencer Controller

Power supply

configuration

STATE

1

Exit Condition 1

Signal list

Internal condition list

Error Conditions

Timeout on PGOOD

Thermal

Power supply

configuration

Power supply

configuration

Current

Voltage

STATE

1

Exit Condition

Signal list

Internal condition list

1

STATE

1

Exit Condition 1

Signal list

Internal condition list

STATE_1

Error Conditions

Timeout on PGOOD

Thermal

Error Conditions

Timeout on PGOOD

Thermal

...

STATE

2

Exit Condition

Signal list

Internal condition list

1

2

Current

Voltage

Current

Voltage

STATE_1

Effective

...

Effective

power

state

Effective

power

state

OFF

STATE

2

Exit Condition

Signal list

Internal condition list

1

2

STATE

2

Exit Condition

Signal list

Internal condition list

1

2

STATE

2

Exit Condition

Signal list

Internal condition list

STATE_2

OFF

STATE

2

Exit Condition

Signal list

Internal condition list

STATE

2

Exit Condition

Signal list

Internal condition list

STATE_2

power

state

ERROR

(SAFE STATE)

ERROR

(SAFE STATE)

ERROR

(SAFE STATE)

STATE_3

Controller for

Output Power

Supply Rails

STATE_3

Controller for

Output Power

Supply Rails

Controller for

Output Power

Supply Rails

STATE_N

Power

supply

error

Power

supply

error

Power

supply

error

Signal Arbitration

Logic

ENABLE or WAKE

signals from

external hardware

Power-State Control

Signals such as:

ACTIVE, SLEEP, RESET,

ERROR, TRACKING

Scalable Microprocessor and System on Chip

Figure 10-46. Multi-PMIC Power State Synchronization Block Diagram

In this scheme each primary and secondary PMIC runs on its own system clock, and maintains its own I2C

register set. Each PMIC will monitor its own activities and pull down the open-drain output of nINT or PGOOD

pin when errors are detected. The microprocessor will need to read the status bits on each PMIC device to find

out the source of error being reported.

To synchronize the timing when entering and exiting from the LP_STANDBY state, the VOUT_LDOVINT of

the TPS6594-Q1 device must be connected to the ENABLE input of the secondary PMICs, which are the

slave devices in the SPMI interface bus. Figure 10-47 illustrates the pin connections between the primary, the

secondary, and the application processor or the System-on-Chip.

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VIO

Secondary PMIC

I2C_SCL

I2C_SDA

SDATA

SCLK

Interrupt

Handler

Power

Sequencer

nINT

Power Good

Monitor

ENABLE

PGOOD

Secondary PMIC

I2C_SCL

I2C_SDA

SDATA

SCLK

Power

nINT

Sequencer

µProcessor

&

PGOOD

ENABLE

System

on

Primary PMIC

Chip

I2C1_SCL

I2C1_SDA

VOUT_LDOVINT

nPWRON/ENABLE

nINT

nERRORx

nSLEEPx

Power

Sequencer

GPIO

nRSTOUTx

WAKEn

PG

SCLK

SDATA

I2C2_SCL

I2C2_SDA

Q&A

WDOG

Figure 10-47. Multi-PIMC Pin Connections

The power sequencer of the multiple PMICs are synchronized at the beginning of each power up and power

down sequence; a variation in the sequence timing, however, is still possible due to the ±5% clock accuracy of

the independent system clocks on the primary and secondary PMICs. The worst case sequence timing variation

from different PMIC rails is up to ±10% of the target delay time. Figure 10-48 illustrates the creation of this timing

variation between PMICs.

Primary PMIC

System clock

(+/-5% accuracy)

...

Primary PMIC

Rail X

Sequence delay between rails in Primary PMIC

Primary PMIC

Rail Y

Secondary PMIC

System clock

(+/-5% accuracy)

...

Sequence delay between rails in secondary PMIC

Secondary PMIC

Rail Z

Sequencing timing variation between PMIC rails

Figure 10-48. Multi-PMIC Rail Sequencing Timing Variation

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10.4.2.1 SPMI Interface System Setup

An SPMI interface in the TPS6594-Q1 device is utilized to communicate the power state transition across

multiple PMICs in the system. The interface block contains an SPMI master block and an SPMI slave block.

There is only one SPMI master device in any given system. The TPS6594-Q1 device is generally the SPMI

master in the system with master and slave blocks enabled. As the SPMI master it initiates SPMI interface BIST

and executes periodic checking of the SPMI bus health.

The SPMI master ID (MID) of the TPS6594-Q1 device is 1. TPS6594-Q1 will also contain a logical SPMI slave

interface in order to receive SPMI communications from the SPMI slave devices. The TPS6594-Q1 as the SPMI

master device will contain the slave (SID) = 0101.

All of the slave devices on this SPMI network will only have the slave interface enabled. There cannot be more

than 5 slave devices in the system. The SIDs for the five slave devices are:

•

1st slave device: 0011

2nd slave device: 1100

3rd slave device: 1001

4th slave device: 0110

5th slave device: 1010

All devices in the SPMI network will listen to Group Slave ID (GSID): 1111. This address is used to communicate

all power state transition information in broadcast mode to all connected devices in parallel.

10.4.2.2 Transmission Protocol and CRC

The communication between the devices on the network utilizes Extended Register Write command to GSID

address 1111 with byte length of 2. Sequence format complies with MIPI SPMI 2.0 specification. First data frame

carries the data payload of 5 bits and 3 filler bits.

Communication over the SPMI interface may contain information regarding the power state transition or the

unique SID of one or more slave devices. In the case of power state information, the data payload contains 5 bits

of Trigger ID information and 3 trigger state bits. In the case of SID information, all 8 bits contain the SID of the

slave device.

Second data frame carries 8 bits of CRC information. CRC polynomial used is X⁸+ X²+ X + 1. CRC is

calculated over the SPMI command frame, the address frame, and the first data frame (which contains the

payload and excludes the parity bits in these three frames).

Figure 10-49 shows the data format of the SPMI Extended Register Write Command.

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SCLK

SDATA

SA3

SA2

SA1

SA0

0

BC3

BC2

BC1

BC0

P

Extended register-write command frame

SSC

SCLK

SDATA

P

A7

A6

A5

A4

A3

A2

A1

A0

P

Register address (data frame) for first register

SCLK

SDATA

P

D7

D6

D5

D4

D3

D2

D1

D0

P

First data frame

... Intermediate Data Frames ...

SCLK

SDATA

P

D7

D6

D5

D4

D3

D2

D1

D0

P

0

Last data frame

Bus park ACK or Bus park

NAK

Signal driven by BOM or request-capable slave device

(SCLK always driven by BOM only)

Signal not driven; pulldown only.

Response by slave devices

For reference only

Figure 10-49. SPMI Extended Register Write Command

10.4.2.3 SPMI Slave Communication to SPMI Master

An SPMI slave device communicates to the SPMI master device and any other SPMI slave devices, only if

there is an internal error, which is not SPMI related. The slave device initiates the error communication using

Slave Arbitration Request with A-bit as defined in the SPMI 2.0 specification. SPMI 2.0 protocol manages the

situation with multiple slave devices requesting error communication at the same time. This is resolved using the

slave arbitration process as described in SPMI 2.0 specification. Once the SPMI slave device wins the Slave

Arbitration using A-bit protocol, it will perform Extended Register Write command to Group Slave ID address

1111 with using the protocol described earlier in this document for communicating PFSM trigger ID.

10.4.2.3.1 Incomplete Communication from SPMI Slave to SPMI Master

In case the TPS6594-Q1 device as the SPMI master detects Slave Arbitration Request on the SPMI interface,

but the received sequence has an error or is incomplete, it will immediately perform SPMI interface BIST. If

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this fails, SPMI master will execute error handling for the SPMI error. If the SPMI interface BIST is successfully

executed, TPS6594-Q1 will resume normal operation.

10.4.2.4 SPMI BIST Overview

The BIST operation is implemented during BIST state and regularly during runtime operation. Figure 10-50

below illustrates how SPMI BIST operates during device power-up.

PMIC internal sequencing

PWRON/ENABLE causes transition

to active mode

ñ

read NVM

initialization

Etc.

Power sequence

FTTI >> SPMI BIST interval

VIN

PWRON/ENABLE

PMIC State

BOOT BIST

STANDBY

ACTIVE/MISSION

SPMI

SPMI BIST patterns

SPMI BIST pattern as part of BOOT

BIST sequence

SPMI messaging to secondary PMIC

to go to ACTIVE state

Figure 10-50. SPMI BIST Operation

TPS6594-Q1 will initialize itself by reading NVM and performing any actions needed to prepare for operation

after the input power is detected and verified to be at the correct level. TPS6594-Q1 will then enter the BOOT

BIST state, in which the internal logic will sequence a series of tests to verify that TPS6594-Q1 and the system

are OK. As part of this test, the SPMI interface BIST is performed. After it is completed successfully, the device

goes to the standby state and waits for further signals from the system to initiate the power-up sequence of the

processor.

A valid on request initiates the processor power-up sequence. TPS6594-Q1 (as the SPMI master) will

communicate this event through the SPMI to all of the slave devices in the system. Then the power-up sequence

will be executed and TPS6594-Q1 will enter the active state or any mission states.

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10.5 Control Interfaces

The device has two, exclusive selectable (from factory settings) interfaces. The first selection is up to two

high-speed I²C interfaces (I2C_SPI_SEL=0). The second selection is one SPI interface (I2C_SPI_SEL=1). The

SPI and I2C1 interfaces are used to fully control and configure the device, and have access to all of the

configuration registers and Watchdog registers. During normal operating mode, when the I²C configuration is

selected, and GPIO1 and GPIO2 pins can be configured as the SCL_I2C2 and SDA_I2C2 pins, I2C2 interface

will become the dedicated interface for the Q&A Watchdog communication channel, while I2C1 interface will no

longer have access to the Watchdog registers. The I2C2 interface is automatically disabled and will have access

to all of the registers, including the Watchdog registers, when the device enters the EEPROM programing mode.

10.5.1 CRC Calculation for I²C and SPI Interface Protocols

For safety applications, the TPS6594-Q1 device supports read and write protocols with embedded CRC data

fields. The master and slave devices use a standard CRC-8 polynomial to calculate the checksum value: X⁸+ X²

+ X + 1. The CRC algorithm details are as follows:

•

Initial value for the remainder is all 1s

Big-endian bit stream order

Result inversion is enabled

For I²C Interface, the TPS6594-Q1 device uses this polynomial to calculate the checksum value on every bit

except the ACK and NACK bits it receives from the MCU during a write protocol. The device compares this

calculated checksum with the MCRC checksum value which the device receives from the MCU. The device also

uses this polynomial to calculate the SCRC checksum value based on every bit except the ACK and NACK bits,

which the device transmits to the MCU during a read protocol. The master device (MCU) must use this same

polynomial to calculate the checksum value based on the bits, which the MCU receives from the device. The

MCU must compare this calculated checksum with the SCRC checksum value which it receives from the device.

For the SPI interface, the TPS6594-Q1 device uses this polynomial to calculate the checksum value on every bit

it receives from the MCU during a write protocol. The device compares this calculated checksum with the MCRC

checksum value, which the device receives from the master device (MCU). During a read protocol, the device

also uses this polynomial to calculate the SCRC checksum value based on the first 16 bits sent by the master

device, and the next 8 bits the device transmits to the master device. The master device must use this same

polynomial to calculate the checksum value based on the bits which the master device sends to and receives

from the device, and compare it with the SCRC checksum value which it receives from the device.

Figure 10-51 and Figure 10-52 are examples for the 4-bit MCRC and the SCRC calculation from 16-bit databus.

16-bit bus ordering value:

15

0

CMD[7] CMD[6] CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0]

Flip-Flop the Preload Value

(Seed Value)

1

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Flip Flop

MCRC[3]

MCRC[2]

MCRC[1]

MCRC[0]

Figure 10-51. Calculation of 4-Bit Master CRC (MCRC) Output

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16-bit bus ordering value:

15

0

STAT[7] STAT[6] STAT[5] STAT[4] STAT[3] STAT[2] STAT[1] STAT[0]

R[7]

R[6]

R[5]

R[4]

R[3]

R[2]

R[1]

R[0]

Flip-Flop the Preload Value

(Seed Value)

1

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Q

D

Flip Flop

SCRC[3]

SCRC[2]

SCRC[1]

SCRC[0]

Figure 10-52. Calculation of 4-Bit Slave CRC (SCRC) Input

10.5.2 I²C-Compatible Interface

The default I²C1 7-bit slave device address of the TPS6594-Q1 device is set to 0x48 (0b1001000 in binary),

while the two least-significant bits can be changed for alternative page selection listed under Section 10.6.1.

The default 7-bit slave device address for the Q&A WatchDog I²C2 interface is set to 0x12. The I2C1_ID and

I2C2_ID register bits can be used to reconfigure the 7-bit default slave address for the corresponding I²C

interface.

The I²C-compatible synchronous serial interface provides access to the configurable functions and registers

on the device. This protocol uses a two-wire interface for bidirectional communications between the devices

connected to the bus. The two interface lines are the serial data line (SDA), and the serial clock line (SCL).

Every device on the bus is assigned a unique address and acts as either a master or a slave depending on

whether it generates or receives the serial clock SCL. The SCL and SDA lines must each have a pullup resistor

placed somewhere on the line and remain HIGH even when the bus is idle. The device supports standard mode

(100 kHz), fast mode (400 kHz), and fast mode plus (1 MHz) when VIO is 3.3 V or 1.8 V, and high-speed mode

(3.4 MHz) only when VIO is 1.8 V.

10.5.2.1 Data Validity

The data on the SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the

state of the data line can only be changed when clock signal is LOW.

SCL

SDA

data

change

allowed

data

change

allowed

data

change

allowed

data

valid

data

valid

Figure 10-53. Data Validity Diagram

10.5.2.2 Start and Stop Conditions

The device is controlled through an I²C-compatible interface. START and STOP conditions classify the beginning

and end of the I²C session. A START condition is defined as the SDA signal going from HIGH to LOW while the

SCL signal is HIGH. A STOP condition is defined as the SDA signal going from LOW to HIGH while the SCL

signal is HIGH. The I²C master device always generates the START and STOP conditions.

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SDA

SCL

S

P

START

STOP

Condition

Figure 10-54. Start and Stop Sequences

The I²C bus is considered busy after a START condition and free after a STOP condition. The I²C master can

generate repeated START conditions during data transmission. A START and a repeated START condition are

equivalent function-wise. Figure 10-55 shows the SDA and SCL signal timing for the I²C-compatible bus. For

timing values, see the Specification section.

t_BUF

SDA

t_HD;STA

t_rCL

t_fDA

t_rDA

t_SP

t_LOW

t_fCL

SCL

t_HD;STA

t_SU;STA

t_SU;STO

t_HIGH

t_HD;DAT

S

t_SU;DAT

S

RS

P

START

REPEATED

START

STOP

START

Figure 10-55. I²C-Compatible Timing

10.5.2.3 Transferring Data

Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.

Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated

by the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls

down the SDA line during the 9th clock pulse, signifying an acknowledge. The device generates an acknowledge

after each byte has been received.

There is one exception to the acknowledge after every byte rule. When the master is the receiver, it must

indicate to the transmitter an end of data by not-acknowledging (negative acknowledge) the last byte clocked out

of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),

but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by

an eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE and a 1

indicates a READ. The second byte selects the register to which the data will be written. The third byte contains

data to write to the selected register. Figure 10-56 shows an example bit format of device address 110000-Bin =

60Hex.

MSB

LSB

1

Bit 7

1

Bit 6

0

Bit 5

0

Bit 4

0

Bit 3

0

Bit 2

0

Bit 1

R/W

Bit 0

I²C Slave Address (chip address)

Figure 10-56. Example Device Address

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For safety applications, the device supports read and write protocols with embedded CRC data fields. In a write

cycle, the I²C master should provide the 8-bit CRC value after sending the write data bits and receiving the ACK

from the slave. The CRC value should be calculated from every bit included in the write protocol except the ACK

bits from the slave. In a read cycle, the I²C slave should provide the 8-bit CRC value after sending the read data

bits and the ACK bit, and expect to receive the NACK from the master at the end of the protocol. The CRC value

should be calculated from every bit included in the read protocol except the ACK and NACK bits.

The embedded CRC field can be enabled or disabled from the protocol by setting the I2C1_SPI_CRC_EN (for

I2C1) or I2C2_CRC_EN (for I2C2) register bit to '1' - enabled, '0' - disabled. The default of this bit is configurable

through the NVM.

In case the calculated CRC-value does not match the received CRC-check-sum, an I²C-CRC-error is detected,

the COMM_CRC_ERR_INT (for I2C1) or I2C2_CRC_ERR_INT (for I2C2) bit is set, unless it is masked by the

COMM_CRC_ERR_MASK or I2C2_CRC_ERR_MASK bit. The MCU must clear this bit by writing a ‘1’ to the

COMM_CRC_ERR_INT (for I2C1) or I2C2_CRC_ERR_INT (for I2C2) bit.

When the CRC field is enabled, in the case when MCU attempts to write to a read-only register or a register-

address that does not exist, the device sets the COMM_ADR_ERR_INT (for I2C1) or I2C2_ADR_ERR_INT (for

I2C2) bit, unless the COMM_ADR_ERR_MASK or I2C2_ADR_ERR_MASK bit is set. The MCU must clear this

bit by writing a ‘1’ to the COMM_ADR_ERR_INT (for I2C1) or I2C2_ADR_ERR_INT (for I2C2) bit.

START

ACK

ACK STOP

I2C_ID[6:0]

0

ADDR[7:0]

WDATA[7:0]

STOP

SCL

SDA

0x60

0x36

0x16

Figure 10-57. I²C Write Cycle without CRC

START

ACK

ACK STOP

I2C_ID[6:0]

0

ADDR[7:0]

WDATA[7:0]

MCRC[7:0]

STOP

SCL

SDA

0x60

0x36

0x16

0x43

Master provides MCRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, and the WDATA bits (24 bits).

Figure 10-58. I²C Write Cycle with CRC

REPEATED

START

STOP

START

ACK

NCK

I2C_ID[6:0]

0

ADDR[7:0]

I2C_ID[6:0]

1

RDATA[7:0]

STOP

SCL

SDA

0x60

0x36

0x60

0x16

When READ function is to be accomplished, a WRITE function must precede the READ function as shown above.

Figure 10-59. I²C Read Cycle without CRC

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REPEATED

START

STOP

START

ACK

NCK

I2C_ID[6:0]

0

ADDR[7:0]

I2C_ID[6:0]

1

RDATA[7:0]

SCRC[7:0]

STOP

SCL

SDA

0x60

0x36

0x60

0x16

0x7D

Slave provides SCRC[7:0], which is calculated from the I2C_ID, R/W, ADDR, I2C_ID, R/W, and the RDATA bits (32 bits).

Figure 10-60. I²C READ Cycle with CRC

10.5.2.4 Auto-Increment Feature

The auto-increment feature allows writing several consecutive registers within one transmission. Every time an

8-bit word is sent to the device, the internal address index counter is incremented by one and the next register

is written. Table 10-21 lists the writing sequence to two consecutive registers. Note that auto increment feature

does not support CRC protocol.

Table 10-21. Auto-Increment Example

DEVICE

ADDRESS =

0x60

MASTER

ACTION

REGISTER

ADDRESS

START

WRITE

DATA

STOP

PMIC device

ACK

10.5.3 Serial Peripheral Interface (SPI)

The device supports SPI serial-bus interface and it operates as a slave. A single read and write transmission

consists of 24-bit write and read cycles (32-bit if CRC is enabled) in the following order:

•

Bits 1-8: ADDR[7:0], Register address

Bits 9-11: PAGE[2:0], Page address for register

Bit 12: Read/Write definition, 0 = WRITE, 1 = READ.

Bits 13-16: RESERVED[4:0], Reserved, use all zeros.

For Write: Bits 17-24: WDATA[7:0], write data

For Write with CRC enabled: Bits 25-32: MCRC[7:0], CRC error code calculated from bits 1-24, sent by

master

•

For Read: Bits 17-24: RDATA[7:0], read data

For Read with CRC enabled: Bits 25-32: SCRC[7:0], CRC error code calculated from bits 1-16, sent by

master, and bits 17-24, sent by slave

The embedded CRC filed can be enabled or disabled from the protocol by setting the I2C1_SPI_CRC_EN

register bit to '1' - enabled, '0' - disabled. The default of this bit is configurable through the NVM.

The SDO output is in a high-impedance state when the CS pin is high. When the CS pin is low, the SDO output

is always driven low except when the RDATA or SCRC bits are sent. When the RDATA or SCRC bits are sent,

the SDO output is driven accordingly.

The address, page, data, and CRC are transmitted MSB first. The slave-select signal (CS) must be low during

the cycle transmission. The CS signal resets the interface when it is high, and must be taken high between

successive cycles. Data is clocked in on the rising edge of the SCLK clock signal and it is clocked out on the

falling edge of SCLK clock signal.

The SPI Timing diagram shows the timing information for these signals.

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CS_SPI

SCLK_SPI

SDI_SPI

PAGE

[2:0]

Reserved[3:0]

0

WDATA[7:0]

ADDR[7:0]

SDO_SPI Hi-Z

Hi-Z

Figure 10-61. SPI Write Cycle

CS_SPI

SCLK_SPI

SDI_SPI

PAGE

[2:0]

Reserved[3:0]

ADDR[7:0]

0

WDATA[7:0]

MCRC[7:0]

SDO_SPI Hi-Z

Hi-Z

Figure 10-62. SPI Write Cycle with Master CRC

CS_SPI

SCLK_SPI

SDI_SPI

PAGE

[2:0]

Reserved[3:0]

1

ADDR[7:0]

Hi-Z

RDATA[7:0]

Hi-Z

SDO_SPI

Figure 10-63. SPI Read Cycle

CS_SPI

SCLK_SPI

SDI_SPI

PAGE

[2:0]

Reserved[3:0]

1

ADDR[7:0]

SDO_SPI Hi-Z

RDATA[7:0]

SCRC[7:0]

Hi-Z

Figure 10-64. SPI Read Cycle with Slave CRC

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10.6 Configurable Registers

10.6.1 Register Page Partitioning

The registers in the TPS6594-Q1 device are organized into five internal pages. Below is a list of the pages which

the each type of the registers belongs to:

•

Page 0: User Registers

Page 1: NVM Control, Configuration, and Test Registers

Page 2: Trim Registers

Page 3: SRAM for PFSM Registers

Page 4: WatchDog Registers

10.6.2 CRC Protection for Configuration, Control, and Test Registers

A static CRC-16 engine exist to protect all the static registers in the design. Static registers are registers in Page

1, 2, and 3, with values that do not change once loaded from NVM. The CRC-16 engine continuously checks

the control registers on the device. The expected CRC-16 value is stored in the NVM. Anytime a mismatch

between the calculated and expected CRC-16 values is detected, the interrupt bit REG_CRC_ERR_INT is set

and the device will force a orderly shutdown sequence to return to the SAFE RECOVERY state. The device

NVM control, configuration, and test registers in page 1 are protected against read or write access when the

device is in normal functional mode. The CRC-16 protection for the NVM registers is configured and enabled

only when the device is in DFT/DEBUG operating mode.

The CRC-16 engine uses a standard CRC-16 polynomial to calculate the internal known-good checksum-value,

which is X¹⁶+ X¹⁴+ X¹³+ X¹²+ X¹⁰+ X⁸+ X⁶+ X⁴+ X³+ X + 1.

The initial value for the remainder of the polynomial is all 1s and is in big-endian bit-stream order. The inversion

of the calculated result is enabled.

Note

The CRC-16 engine assume the value of '0' for all undefined or reserved bits in all control registers.

Therefore, the software MUST NOT write the value of '1' to any of these undefined or reserved bits. If

the value of '1 is written to any undefined or reserved bit of a writeable register, a mismatch between

the calculated and expected CRC-16 values will be detected, a REG_CRC_ERR interrupt will be set,

and the device will force a orderly shutdown sequence to return to the SAFE RECOVERY state.

10.6.3 CRC Protection for User Registers

A dynamic CRC-8 engine exists to protect registers that have values which can change during operation. These

are registers in Page 1 and 4. When writes occur to these pages, the dynamic CRC-8 is checked, computed,

and updated. Continuously during operation the CRC-8 are evaluated and verified in a round-robin fashion.

The CRC-8 engine utilizes the Polynomial(0xA6) = X⁸+ X⁶+ X³+ X²+ 1, which provides a H4 hamming

distance.

10.6.4 Register Write Protection

For safety application, in order to prevent unintentional writes to the control registers, the TPS6594-Q1 device

implements locking and unlocking mechanisms to many of its configuration/control registers described in the

following subsections.

10.6.4.1 ESM and WDOG Configuration Registers

The configuration registers for the watchdog and the ESM modules are locked when their monitoring functions

are in operation. The timing and the list of the watchdog registers which will locked is described under Section

10.3.11.2. The list of ESM registers locked after the start of each ESM module is described under Section

10.3.12

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10.6.4.2 User Registers

User registers in page 0, except the ESM and the WDOG configuration registers described in Section 10.6.4.1,

and the interrupt registers (x_INT) at address 0x5a through 0x6c in page 0, can be write protected by a

dedicated lock. User must write '0x9B' to the REGISTER_LOCK register to unlock the register. Writing any

value other than '0x9B' will activate the lock again. To check the register lock status, user should read the

REGISTER_LOCK_STATUS bit. When this bit is '0', it indicates the user registers are unlocked. When this bit is

'1', the user registers are locked. During startup sequence such as powering up for the first time, waking up from

LP_STANDBY, or recovering from SAFE_RECOVERY, the user registers will be unlocked automatically.

As an extra measure of protection to prevent the accidental change of the buck frequency while the buck is in

operation, the BUCKn_FREQ_SEL register bits are locked by the REGISTER_LOCK register. User is advised

against changing the buck frequency while the buck is in operation.

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10.7 Register Maps

10.7.1 TPS6594-Q1 Registers

Table 10-22 lists the memory-mapped registers for the TPS6594-Q1 registers. All register offset addresses

not listed in Table 10-22 should be considered as reserved locations and the register contents should not be

modified.

Table 10-22. TPS6594-Q1 Registers

Offset

0x1

Acronym

Register Name

Section

DEV_REV

Section 10.7.1.1

Section 10.7.1.2

Section 10.7.1.3

Section 10.7.1.4

Section 10.7.1.5

Section 10.7.1.6

Section 10.7.1.7

Section 10.7.1.8

Section 10.7.1.9

Section 10.7.1.10

Section 10.7.1.11

Section 10.7.1.12

Section 10.7.1.13

Section 10.7.1.14

Section 10.7.1.15

Section 10.7.1.16

Section 10.7.1.17

Section 10.7.1.18

Section 10.7.1.19

Section 10.7.1.20

Section 10.7.1.21

Section 10.7.1.22

Section 10.7.1.23

Section 10.7.1.24

Section 10.7.1.25

Section 10.7.1.26

Section 10.7.1.27

Section 10.7.1.28

Section 10.7.1.29

Section 10.7.1.30

Section 10.7.1.31

Section 10.7.1.32

Section 10.7.1.33

Section 10.7.1.34

Section 10.7.1.35

Section 10.7.1.36

Section 10.7.1.37

Section 10.7.1.38

Section 10.7.1.39

Section 10.7.1.40

0x2

NVM_CODE_1

NVM_CODE_2

BUCK1_CTRL

0x3

0x4

0x5

BUCK1_CONF

BUCK2_CTRL

0x6

0x7

BUCK2_CONF

BUCK3_CTRL

0x8

0x9

BUCK3_CONF

BUCK4_CTRL

0xA

0xB

BUCK4_CONF

BUCK5_CTRL

0xC

0xD

BUCK5_CONF

BUCK1_VOUT_1

BUCK1_VOUT_2

BUCK2_VOUT_1

BUCK2_VOUT_2

BUCK3_VOUT_1

BUCK3_VOUT_2

BUCK4_VOUT_1

BUCK4_VOUT_2

BUCK5_VOUT_1

BUCK5_VOUT_2

BUCK1_PG_WINDOW

BUCK2_PG_WINDOW

BUCK3_PG_WINDOW

BUCK4_PG_WINDOW

BUCK5_PG_WINDOW

LDO1_CTRL

0xE

0xF

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

LDO2_CTRL

LDO3_CTRL

LDO4_CTRL

LDORTC_CTRL

LDO1_VOUT

LDO2_VOUT

LDO3_VOUT

LDO4_VOUT

LDO1_PG_WINDOW

LDO2_PG_WINDOW

LDO3_PG_WINDOW

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Table 10-22. TPS6594-Q1 Registers (continued)

Offset

0x2A

0x2B

0x2C

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

0x4C

0x4D

0x4E

0x4F

0x50

0x51

0x52

0x53

0x54

0x56

0x57

0x58

0x59

0x5A

0x5B

Acronym

Register Name

Section

LDO4_PG_WINDOW

VCCA_VMON_CTRL

VCCA_PG_WINDOW

GPIO1_CONF

Section 10.7.1.41

Section 10.7.1.42

Section 10.7.1.43

Section 10.7.1.44

Section 10.7.1.45

Section 10.7.1.46

Section 10.7.1.47

Section 10.7.1.48

Section 10.7.1.49

Section 10.7.1.50

Section 10.7.1.51

Section 10.7.1.52

Section 10.7.1.53

Section 10.7.1.54

Section 10.7.1.55

Section 10.7.1.56

Section 10.7.1.57

Section 10.7.1.58

Section 10.7.1.59

Section 10.7.1.60

Section 10.7.1.61

Section 10.7.1.62

Section 10.7.1.63

Section 10.7.1.64

Section 10.7.1.65

Section 10.7.1.66

Section 10.7.1.67

Section 10.7.1.68

Section 10.7.1.69

Section 10.7.1.70

Section 10.7.1.71

Section 10.7.1.72

Section 10.7.1.73

Section 10.7.1.74

Section 10.7.1.75

Section 10.7.1.76

Section 10.7.1.77

Section 10.7.1.78

Section 10.7.1.79

Section 10.7.1.80

Section 10.7.1.81

Section 10.7.1.82

Section 10.7.1.83

Section 10.7.1.84

Section 10.7.1.85

GPIO2_CONF

GPIO3_CONF

GPIO4_CONF

GPIO5_CONF

GPIO6_CONF

GPIO7_CONF

GPIO8_CONF

GPIO9_CONF

GPIO10_CONF

GPIO11_CONF

NPWRON_CONF

GPIO_OUT_1

GPIO_OUT_2

GPIO_IN_1

GPIO_IN_2

RAIL_SEL_1

RAIL_SEL_2

RAIL_SEL_3

FSM_TRIG_SEL_1

FSM_TRIG_SEL_2

FSM_TRIG_MASK_1

FSM_TRIG_MASK_2

FSM_TRIG_MASK_3

MASK_BUCK1_2

MASK_BUCK3_4

MASK_BUCK5

MASK_LDO1_2

MASK_LDO3_4

MASK_VMON

MASK_GPIO1_8_FALL

MASK_GPIO1_8_RISE

MASK_GPIO9_11

MASK_STARTUP

MASK_MISC

MASK_MODERATE_ERR

MASK_FSM_ERR

MASK_COMM_ERR

MASK_READBACK_ERR

MASK_ESM

INT_TOP

INT_BUCK

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Table 10-22. TPS6594-Q1 Registers (continued)

Offset

0x5C

0x5D

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x8A

Acronym

Register Name

Section

INT_BUCK1_2

Section 10.7.1.86

Section 10.7.1.87

Section 10.7.1.88

Section 10.7.1.89

Section 10.7.1.90

Section 10.7.1.91

Section 10.7.1.92

Section 10.7.1.93

Section 10.7.1.94

Section 10.7.1.95

Section 10.7.1.96

Section 10.7.1.97

Section 10.7.1.98

Section 10.7.1.99

Section 10.7.1.100

Section 10.7.1.101

Section 10.7.1.102

Section 10.7.1.103

Section 10.7.1.104

Section 10.7.1.105

Section 10.7.1.106

Section 10.7.1.107

Section 10.7.1.108

Section 10.7.1.109

Section 10.7.1.110

Section 10.7.1.111

Section 10.7.1.112

Section 10.7.1.113

Section 10.7.1.114

Section 10.7.1.115

Section 10.7.1.116

Section 10.7.1.117

Section 10.7.1.118

Section 10.7.1.119

Section 10.7.1.120

Section 10.7.1.121

Section 10.7.1.122

Section 10.7.1.123

Section 10.7.1.124

Section 10.7.1.125

Section 10.7.1.126

Section 10.7.1.127

Section 10.7.1.128

Section 10.7.1.129

Section 10.7.1.130

INT_BUCK3_4

INT_BUCK5

INT_LDO_VMON

INT_LDO1_2

INT_LDO3_4

INT_VMON

INT_GPIO

INT_GPIO1_8

INT_STARTUP

INT_MISC

INT_MODERATE_ERR

INT_SEVERE_ERR

INT_FSM_ERR

INT_COMM_ERR

INT_READBACK_ERR

INT_ESM

STAT_BUCK1_2

STAT_BUCK3_4

STAT_BUCK5

STAT_LDO1_2

STAT_LDO3_4

STAT_VMON

STAT_STARTUP

STAT_MISC

STAT_MODERATE_ERR

STAT_SEVERE_ERR

STAT_READBACK_ERR

PGOOD_SEL_1

PGOOD_SEL_2

PGOOD_SEL_3

PGOOD_SEL_4

PLL_CTRL

CONFIG_1

CONFIG_2

ENABLE_DRV_REG

MISC_CTRL

ENABLE_DRV_STAT

RECOV_CNT_REG_1

RECOV_CNT_REG_2

FSM_I2C_TRIGGERS

FSM_NSLEEP_TRIGGERS

BUCK_RESET_REG

SPREAD_SPECTRUM_1

FREQ_SEL

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Table 10-22. TPS6594-Q1 Registers (continued)

Offset

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

0x99

0x9A

0x9B

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA6

0xA7

0xAB

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

0xC3

0xC4

0xC5

0xC6

0xC7

Acronym

Register Name

Section

FSM_STEP_SIZE

Section 10.7.1.131

Section 10.7.1.132

Section 10.7.1.133

Section 10.7.1.134

Section 10.7.1.135

Section 10.7.1.136

Section 10.7.1.137

Section 10.7.1.138

Section 10.7.1.139

Section 10.7.1.140

Section 10.7.1.141

Section 10.7.1.142

Section 10.7.1.143

Section 10.7.1.144

Section 10.7.1.145

Section 10.7.1.146

Section 10.7.1.147

Section 10.7.1.148

Section 10.7.1.149

Section 10.7.1.150

Section 10.7.1.151

Section 10.7.1.152

Section 10.7.1.153

Section 10.7.1.154

Section 10.7.1.155

Section 10.7.1.156

Section 10.7.1.157

Section 10.7.1.158

Section 10.7.1.159

Section 10.7.1.160

Section 10.7.1.161

Section 10.7.1.162

Section 10.7.1.163

Section 10.7.1.164

Section 10.7.1.165

Section 10.7.1.166

Section 10.7.1.167

Section 10.7.1.168

Section 10.7.1.169

Section 10.7.1.170

Section 10.7.1.171

Section 10.7.1.172

Section 10.7.1.173

Section 10.7.1.174

Section 10.7.1.175

LDO_RV_TIMEOUT_REG_1

LDO_RV_TIMEOUT_REG_2

USER_SPARE_REGS

ESM_MCU_START_REG

ESM_MCU_DELAY1_REG

ESM_MCU_DELAY2_REG

ESM_MCU_MODE_CFG

ESM_MCU_HMAX_REG

ESM_MCU_HMIN_REG

ESM_MCU_LMAX_REG

ESM_MCU_LMIN_REG

ESM_MCU_ERR_CNT_REG

ESM_SOC_START_REG

ESM_SOC_DELAY1_REG

ESM_SOC_DELAY2_REG

ESM_SOC_MODE_CFG

ESM_SOC_HMAX_REG

ESM_SOC_HMIN_REG

ESM_SOC_LMAX_REG

ESM_SOC_LMIN_REG

ESM_SOC_ERR_CNT_REG

REGISTER_LOCK

MANUFACTURING_VER

CUSTOMER_NVM_ID_REG

SOFT_REBOOT_REG

RTC_SECONDS

RTC_MINUTES

RTC_HOURS

RTC_DAYS

RTC_MONTHS

RTC_YEARS

RTC_WEEKS

ALARM_SECONDS

ALARM_MINUTES

ALARM_HOURS

ALARM_DAYS

ALARM_MONTHS

ALARM_YEARS

RTC_CTRL_1

RTC_CTRL_2

RTC_STATUS

RTC_INTERRUPTS

RTC_COMP_LSB

RTC_COMP_MSB

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Table 10-22. TPS6594-Q1 Registers (continued)

Offset

0xC8

Acronym

Register Name

Section

RTC_RESET_STATUS

SCRATCH_PAD_REG_1

SCRATCH_PAD_REG_2

SCRATCH_PAD_REG_3

SCRATCH_PAD_REG_4

PFSM_DELAY_REG_1

PFSM_DELAY_REG_2

PFSM_DELAY_REG_3

PFSM_DELAY_REG_4

WD_ANSWER_REG

WD_QUESTION_ANSW_CNT

WD_WIN1_CFG

Section 10.7.1.176

Section 10.7.1.177

Section 10.7.1.178

Section 10.7.1.179

Section 10.7.1.180

Section 10.7.1.181

Section 10.7.1.182

Section 10.7.1.183

Section 10.7.1.184

Section 10.7.1.185

Section 10.7.1.186

Section 10.7.1.187

Section 10.7.1.188

Section 10.7.1.189

Section 10.7.1.190

Section 10.7.1.191

Section 10.7.1.192

Section 10.7.1.193

Section 10.7.1.194

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0x401

0x402

0x403

0x404

0x405

0x406

0x407

0x408

0x409

0x40A

WD_WIN2_CFG

WD_LONGWIN_CFG

WD_MODE_REG

WD_QA_CFG

WD_ERR_STATUS

WD_THR_CFG

WD_FAIL_CNT_REG

Complex bit access types are encoded to fit into small table cells. Table 10-23 shows the codes that are used for

access types in this section.

Table 10-23. TPS6594-Q1 Access Type Codes

Access Type

Read Type

R

Code

Description

R

Read

Write Type

W

Write

W1C

W

Write

1C

1 to clear

WSelfClrF

W

Write

Reset or Default Value

-n

Value after reset or the default

value

Register Array Variables

i,j,k,l,m,n

When these variables are used in

a register name, an offset, or an

address, they refer to the value of

a register array where the register

is part of a group of repeating

registers. The register groups

form a hierarchical structure and

the array is represented with a

formula.

y

When this variable is used in a

register name, an offset, or an

address it refers to the value of

a register array.

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10.7.1.1 DEV_REV Register (Offset = 0x1) [Reset = 0x0]

DEV_REV is shown in Figure 10-60 and described in Table 10-24.

Return to the Table 10-22.

Figure 10-60. DEV_REV Register

7

6

5

4

3

2

1

0

TI_DEVICE_ID

R/W-0b

Table 10-24. DEV_REV Register Field Descriptions

Bit

7:0

Field

TI_DEVICE_ID

Type

Reset

Description

R/W

0b

TI_DEVICE_ID[7]:

0 - Industrial

1 - Auto

TI_DEVICE_ID[6:2] = Device GPN

TI_DEVICE_ID[1]:

0 - QM

1 - ASIL

TI_DEVICE_ID[0] = Reserved

Note: This register can be programmed only by the manufacturer.

(Default from NVM memory)

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10.7.1.2 NVM_CODE_1 Register (Offset = 0x2) [Reset = 0x0]

NVM_CODE_1 is shown in Figure 10-61 and described in Table 10-25.

Return to the Table 10-22.

Figure 10-61. NVM_CODE_1 Register

7

6

5

4

3

2

1

0

TI_NVM_ID

R/W-0b

Table 10-25. NVM_CODE_1 Register Field Descriptions

Bit

7:0

Field

TI_NVM_ID

Type

Reset

Description

R/W

0b

Note: This register can be programmed only by the manufacturer.

(Default from NVM memory)

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10.7.1.3 NVM_CODE_2 Register (Offset = 0x3) [Reset = 0x0]

NVM_CODE_2 is shown in Figure 10-62 and described in Table 10-26.

Return to the Table 10-22.

Figure 10-62. NVM_CODE_2 Register

7

6

5

4

3

2

1

0

TI_NVM_REV

R/W-0b

Table 10-26. NVM_CODE_2 Register Field Descriptions

Bit

7:0

Field

TI_NVM_REV

Type

Reset

Description

R/W

0b

NVM revision of the IC

Note: This register can be programmed only by the manufacturer.

(Default from NVM memory)

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10.7.1.4 BUCK1_CTRL Register (Offset = 0x4) [Reset = 0x22]

BUCK1_CTRL is shown in Figure 10-63 and described in Table 10-27.

Return to the Table 10-22.

Figure 10-63. BUCK1_CTRL Register

7

6

5

4

3

2

1

0

BUCK1_RV_SE RESERVED

L

BUCK1_PLDN BUCK1_VMON BUCK1_VSEL BUCK1_FPWM BUCK1_FPWM

BUCK1_EN

_EN

_MP

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-27. BUCK1_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK1_RV_SEL

R/W

0b

Select residual voltage checking for BUCK1 feedback pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6

5

RESERVED

R/W

0b

1b

BUCK1_PLDN

Enable output pull-down resistor when BUCK1 is disabled:

(Default from NVM memory)

0b = Pull-down resistor disabled

1b = Pull-down resistor enabled

4

3

2

BUCK1_VMON_EN

BUCK1_VSEL

R/W

0b

Enable BUCK1 OV, UV, SC and ILIM comparators:

(Default from NVM memory)

0b = OV, UV, SC and ILIM comparators are disabled

1b = OV, UV, SC and ILIM comparators are enabled

Select output voltage register for BUCK1:

(Default from NVM memory)

0b = BUCK1_VOUT_1

1b = BUCK1_VOUT_2

BUCK1_FPWM_MP

Forces the BUCK1 regulator to operate always in multi-phase and

forced PWM operation mode:

(Default from NVM memory)

0b = Automatic phase adding and shedding.

1b = Forced to multi-phase operation, all phases in the multi-phase

configuration.

1

0

BUCK1_FPWM

BUCK1_EN

R/W

1b

0b

Forces the BUCK1 regulator to operate in PWM mode:

(Default from NVM memory)

0b = Automatic transitions between PFM and PWM modes (AUTO

mode).

1b = Forced to PWM operation.

Enable BUCK1 regulator:

(Default from NVM memory)

0b = BUCK regulator is disabled

1b = BUCK regulator is enabled

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10.7.1.5 BUCK1_CONF Register (Offset = 0x5) [Reset = 0x22]

BUCK1_CONF is shown in Figure 10-64 and described in Table 10-28.

Return to the Table 10-22.

Figure 10-64. BUCK1_CONF Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK1_ILIM

R/W-100b

BUCK1_SLEW_RATE

R/W-10b

Table 10-28. BUCK1_CONF Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

BUCK1_ILIM

0b

100b

Sets the switch peak current limit of BUCK1. Can be programmed at

any time during operation:

(Default from NVM memory)

0b = Reserved

1b = Reserved

10b = 2.5 A

11b = 3.5 A

100b = 4.5 A

101b = 5.5 A

110b = Reserved

111b = Reserved

2:0

BUCK1_SLEW_RATE

R/W

10b

Sets the output voltage slew rate for BUCK1 regulator (rising and

falling edges):

(Default from NVM memory)

0b = 33 mV/μs

1b = 20 mV/μs

10b = 10 mV/μs

11b = 5.0 mV/μs

100b = 2.5 mV/μs

101b = 1.3 mV/μs

110b = 0.63 mV/μs

111b = 0.31 mV/μs

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10.7.1.6 BUCK2_CTRL Register (Offset = 0x6) [Reset = 0x22]

BUCK2_CTRL is shown in Figure 10-65 and described in Table 10-29.

Return to the Table 10-22.

Figure 10-65. BUCK2_CTRL Register

7

6

5

4

3

2

1

0

BUCK2_RV_SE RESERVED

L

BUCK2_PLDN BUCK2_VMON BUCK2_VSEL

_EN

RESERVED

BUCK2_FPWM

BUCK2_EN

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-29. BUCK2_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK2_RV_SEL

R/W

0b

Select residual voltage checking for BUCK2 feedback pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6

5

RESERVED

R/W

0b

1b

BUCK2_PLDN

Enable output pull-down resistor when BUCK2 is disabled:

(Default from NVM memory)

0b = Pull-down resistor disabled

1b = Pull-down resistor enabled

4

3

BUCK2_VMON_EN

BUCK2_VSEL

R/W

0b

Enable BUCK2 OV, UV, SC and ILIM comparators:

(Default from NVM memory)

0b = OV, UV, SC, and ILIM comparators are disabled

1b = OV, UV, SC and ILIM comparators are enabled

Select output voltage register for BUCK2:

(Default from NVM memory)

0b = BUCK2_VOUT_1

1b = BUCK2_VOUT_2

2

1

RESERVED

R/W

0b

1b

BUCK2_FPWM

Forces the BUCK2 regulator to operate in PWM mode:

(Default from NVM memory)

0b = Automatic transitions between PFM and PWM modes (AUTO

mode).

1b = Forced to PWM operation.

0

BUCK2_EN

R/W

0b

Enable BUCK2 regulator:

(Default from NVM memory)

0b = BUCK regulator is disabled

1b = BUCK regulator is enabled

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10.7.1.7 BUCK2_CONF Register (Offset = 0x7) [Reset = 0x22]

BUCK2_CONF is shown in Figure 10-66 and described in Table 10-30.

Return to the Table 10-22.

Figure 10-66. BUCK2_CONF Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK2_ILIM

R/W-100b

BUCK2_SLEW_RATE

R/W-10b

Table 10-30. BUCK2_CONF Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

BUCK2_ILIM

0b

100b

Sets the switch peak current limit of BUCK2. Can be programmed at

any time during operation:

(Default from NVM memory)

0b = Reserved

1b = Reserved

10b = 2.5 A

11b = 3.5 A

100b = 4.5 A

101b = 5.5 A

110b = Reserved

111b = Reserved

2:0

BUCK2_SLEW_RATE

R/W

10b

Sets the output voltage slew rate for BUCK2 regulator (rising and

falling edges):

(Default from NVM memory)

0b = 33 mV/μs

1b = 20 mV/μs

10b = 10 mV/μs

11b = 5.0 mV/μs

100b = 2.5 mV/μs

101b = 1.3 mV/μs

110b = 0.63 mV/μs

111b = 0.31 mV/μs

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10.7.1.8 BUCK3_CTRL Register (Offset = 0x8) [Reset = 0x22]

BUCK3_CTRL is shown in Figure 10-67 and described in Table 10-31.

Return to the Table 10-22.

Figure 10-67. BUCK3_CTRL Register

7

6

5

4

3

2

1

0

BUCK3_RV_SE RESERVED

L

BUCK3_PLDN BUCK3_VMON BUCK3_VSEL BUCK3_FPWM BUCK3_FPWM

BUCK3_EN

_EN

_MP

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-31. BUCK3_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK3_RV_SEL

R/W

0b

Select residual voltage checking for BUCK3 feedback pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6

5

RESERVED

R/W

0b

1b

BUCK3_PLDN

Enable output pull-down resistor when BUCK3 is disabled:

(Default from NVM memory)

0b = Pull-down resistor disabled

1b = Pull-down resistor enabled

4

3

2

BUCK3_VMON_EN

BUCK3_VSEL

R/W

0b

Enable BUCK3 OV, UV, SC, and ILIM comparators:

(Default from NVM memory)

0b = OV, UV, SC and ILIM comparators are disabled

1b = OV, UV, SC and ILIM comparators are enabled

Select output voltage register for BUCK3:

(Default from NVM memory)

0b = BUCK3_VOUT_1

1b = BUCK3_VOUT_2

BUCK3_FPWM_MP

Forces the BUCK3 regulator to operate always in multi-phase and

forced PWM operation mode:

(Default from NVM memory)

0b = Automatic phase adding and shedding.

1b = Forced to multi-phase operation, all phases in the multi-phase

configuration.

1

0

BUCK3_FPWM

BUCK3_EN

R/W

1b

0b

Forces the BUCK3 regulator to operate in PWM mode:

(Default from NVM memory)

0b = Automatic transitions between PFM and PWM modes (AUTO

mode).

1b = Forced to PWM operation.

Enable BUCK3 regulator:

(Default from NVM memory)

0b = BUCK regulator is disabled

1b = BUCK regulator is enabled

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10.7.1.9 BUCK3_CONF Register (Offset = 0x9) [Reset = 0x22]

BUCK3_CONF is shown in Figure 10-68 and described in Table 10-32.

Return to the Table 10-22.

Figure 10-68. BUCK3_CONF Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK3_ILIM

R/W-100b

BUCK3_SLEW_RATE

R/W-10b

Table 10-32. BUCK3_CONF Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

BUCK3_ILIM

0b

100b

Sets the switch peak current limit of BUCK3. Can be programmed at

any time during operation:

(Default from NVM memory)

0b = Reserved

1b = Reserved

10b = 2.5 A

11b = 3.5 A

100b = 4.5 A

101b = 5.5 A

110b = Reserved

111b = Reserved

2:0

BUCK3_SLEW_RATE

R/W

10b

Sets the output voltage slew rate for BUCK3 regulator (rising and

falling edges):

(Default from NVM memory)

0b = 33 mV/μs

1b = 20 mV/μs

10b = 10 mV/μs

11b = 5.0 mV/μs

100b = 2.5 mV/μs

101b = 1.3 mV/μs

110b = 0.63 mV/μs

111b = 0.31 mV/μs

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10.7.1.10 BUCK4_CTRL Register (Offset = 0xA) [Reset = 0x22]

BUCK4_CTRL is shown in Figure 10-69 and described in Table 10-33.

Return to the Table 10-22.

Figure 10-69. BUCK4_CTRL Register

7

6

5

4

3

2

1

0

BUCK4_RV_SE RESERVED

L

BUCK4_PLDN BUCK4_VMON BUCK4_VSEL

_EN

RESERVED

BUCK4_FPWM

BUCK4_EN

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-33. BUCK4_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK4_RV_SEL

R/W

0b

Select residual voltage checking for BUCK4 feedback pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6

5

RESERVED

R/W

0b

1b

BUCK4_PLDN

Enable output pull-down resistor when BUCK4 is disabled:

(Default from NVM memory)

0b = Pull-down resistor disabled

1b = Pull-down resistor enabled

4

3

BUCK4_VMON_EN

BUCK4_VSEL

R/W

0b

Enable BUCK4 OV, UV, SC and ILIM comparators:

(Default from NVM memory)

0b = OV, UV, SC and ILIM comparators are disabled

1b = OV, UV, SC and ILIM comparators are enabled

Select output voltage register for BUCK4:

(Default from NVM memory)

0b = BUCK4_VOUT_1

1b = BUCK4_VOUT_2

2

1

RESERVED

R/W

0b

1b

BUCK4_FPWM

Forces the BUCK4 regulator to operate in PWM mode:

(Default from NVM memory)

0b = Automatic transitions between PFM and PWM modes (AUTO

mode).

1b = Forced to PWM operation.

0

BUCK4_EN

R/W

0b

Enable BUCK4 regulator:

(Default from NVM memory)

0b = BUCK regulator is disabled

1b = BUCK regulator is enabled

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10.7.1.11 BUCK4_CONF Register (Offset = 0xB) [Reset = 0x22]

BUCK4_CONF is shown in Figure 10-70 and described in Table 10-34.

Return to the Table 10-22.

Figure 10-70. BUCK4_CONF Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK4_ILIM

R/W-100b

BUCK4_SLEW_RATE

R/W-10b

Table 10-34. BUCK4_CONF Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

BUCK4_ILIM

0b

100b

Sets the switch peak current limit of BUCK4. Can be programmed at

any time during operation:

(Default from NVM memory)

0b = Reserved

1b = Reserved

10b = 2.5 A

11b = 3.5 A

100b = 4.5 A

101b = 5.5 A

110b = Reserved

111b = Reserved

2:0

BUCK4_SLEW_RATE

R/W

10b

Sets the output voltage slew rate for BUCK4 regulator (rising and

falling edges):

(Default from NVM memory)

0b = 33 mV/μs

1b = 20 mV/μs

10b = 10 mV/μs

11b = 5.0 mV/μs

100b = 2.5 mV/μs

101b = 1.3 mV/μs

110b = 0.63 mV/μs

111b = 0.31 mV/μs

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10.7.1.12 BUCK5_CTRL Register (Offset = 0xC) [Reset = 0x22]

BUCK5_CTRL is shown in Figure 10-71 and described in Table 10-35.

Return to the Table 10-22.

Figure 10-71. BUCK5_CTRL Register

7

6

5

4

3

2

1

0

BUCK5_RV_SE RESERVED

L

BUCK5_PLDN BUCK5_VMON BUCK5_VSEL

_EN

RESERVED

BUCK5_FPWM

BUCK5_EN

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-35. BUCK5_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK5_RV_SEL

R/W

0b

Select residual voltage checking for BUCK5 feedback pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6

5

RESERVED

R/W

0b

1b

BUCK5_PLDN

Enable output pull-down resistor when BUCK5 is disabled:

(Default from NVM memory)

0b = Pull-down resistor disabled

1b = Pull-down resistor enabled

4

3

BUCK5_VMON_EN

BUCK5_VSEL

R/W

0b

Enable BUCK5 OV, UV, SC and ILIM comparators:

(Default from NVM memory)

0b = OV, UV, SC and ILIM comparators are disabled

1b = OV, UV, SC and ILIM comparators are enabled

Select output voltage register for BUCK5:

(Default from NVM memory)

0b = BUCK5_VOUT_1

1b = BUCK5_VOUT_2

2

1

RESERVED

R/W

0b

1b

BUCK5_FPWM

Forces the BUCK5 regulator to operate in PWM mode:

(Default from NVM memory)

0b = Automatic transitions between PFM and PWM modes (AUTO

mode).

1b = Forced to PWM operation.

0

BUCK5_EN

R/W

0b

Enable BUCK5 regulator:

(Default from NVM memory)

0b = BUCK regulator is disabled

1b = BUCK regulator is enabled

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10.7.1.13 BUCK5_CONF Register (Offset = 0xD) [Reset = 0x22]

BUCK5_CONF is shown in Figure 10-72 and described in Table 10-36.

Return to the Table 10-22.

Figure 10-72. BUCK5_CONF Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK5_ILIM

R/W-100b

BUCK5_SLEW_RATE

R/W-10b

Table 10-36. BUCK5_CONF Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

BUCK5_ILIM

0b

100b

Sets the switch peak current limit of BUCK5. Can be programmed at

any time during operation:

(Default from NVM memory)

0b = Reserved

1b = Reserved

10b = 2.5 A

11b = 3.5 A

100b = Reserved

101b = Reserved

110b = Reserved

111b = Reserved

2:0

BUCK5_SLEW_RATE

R/W

10b

Sets the output voltage slew rate for BUCK5 regulator (rising and

falling edges):

(Default from NVM memory)

0b = 33 mV/μs

1b = 20 mV/μs

10b = 10 mV/μs

11b = 5.0 mV/μs

100b = 2.5 mV/μs

101b = 1.3 mV/μs

110b = 0.63 mV/μs

111b = 0.31 mV/μs

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10.7.1.14 BUCK1_VOUT_1 Register (Offset = 0xE) [Reset = 0x0]

BUCK1_VOUT_1 is shown in Figure 10-73 and described in Table 10-37.

Return to the Table 10-22.

Figure 10-73. BUCK1_VOUT_1 Register

7

6

5

4

3

2

1

0

BUCK1_VSET1

R/W-0b

Table 10-37. BUCK1_VOUT_1 Register Field Descriptions

Bit

7:0

Field

BUCK1_VSET1

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.15 BUCK1_VOUT_2 Register (Offset = 0xF) [Reset = 0x0]

BUCK1_VOUT_2 is shown in Figure 10-74 and described in Table 10-38.

Return to the Table 10-22.

Figure 10-74. BUCK1_VOUT_2 Register

7

6

5

4

3

2

1

0

BUCK1_VSET2

R/W-0b

Table 10-38. BUCK1_VOUT_2 Register Field Descriptions

Bit

7:0

Field

BUCK1_VSET2

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.16 BUCK2_VOUT_1 Register (Offset = 0x10) [Reset = 0x0]

BUCK2_VOUT_1 is shown in Figure 10-75 and described in Table 10-39.

Return to the Table 10-22.

Figure 10-75. BUCK2_VOUT_1 Register

7

6

5

4

3

2

1

0

BUCK2_VSET1

R/W-0b

Table 10-39. BUCK2_VOUT_1 Register Field Descriptions

Bit

7:0

Field

BUCK2_VSET1

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.17 BUCK2_VOUT_2 Register (Offset = 0x11) [Reset = 0x0]

BUCK2_VOUT_2 is shown in Figure 10-76 and described in Table 10-40.

Return to the Table 10-22.

Figure 10-76. BUCK2_VOUT_2 Register

7

6

5

4

3

2

1

0

BUCK2_VSET2

R/W-0b

Table 10-40. BUCK2_VOUT_2 Register Field Descriptions

Bit

7:0

Field

BUCK2_VSET2

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.18 BUCK3_VOUT_1 Register (Offset = 0x12) [Reset = 0x0]

BUCK3_VOUT_1 is shown in Figure 10-77 and described in Table 10-41.

Return to the Table 10-22.

Figure 10-77. BUCK3_VOUT_1 Register

7

6

5

4

3

2

1

0

BUCK3_VSET1

R/W-0b

Table 10-41. BUCK3_VOUT_1 Register Field Descriptions

Bit

7:0

Field

BUCK3_VSET1

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.19 BUCK3_VOUT_2 Register (Offset = 0x13) [Reset = 0x0]

BUCK3_VOUT_2 is shown in Figure 10-78 and described in Table 10-42.

Return to the Table 10-22.

Figure 10-78. BUCK3_VOUT_2 Register

7

6

5

4

3

2

1

0

BUCK3_VSET2

R/W-0b

Table 10-42. BUCK3_VOUT_2 Register Field Descriptions

Bit

7:0

Field

BUCK3_VSET2

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.20 BUCK4_VOUT_1 Register (Offset = 0x14) [Reset = 0x0]

BUCK4_VOUT_1 is shown in Figure 10-79 and described in Table 10-43.

Return to the Table 10-22.

Figure 10-79. BUCK4_VOUT_1 Register

7

6

5

4

3

2

1

0

BUCK4_VSET1

R/W-0b

Table 10-43. BUCK4_VOUT_1 Register Field Descriptions

Bit

7:0

Field

BUCK4_VSET1

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.21 BUCK4_VOUT_2 Register (Offset = 0x15) [Reset = 0x0]

BUCK4_VOUT_2 is shown in Figure 10-80 and described in Table 10-44.

Return to the Table 10-22.

Figure 10-80. BUCK4_VOUT_2 Register

7

6

5

4

3

2

1

0

BUCK4_VSET2

R/W-0b

Table 10-44. BUCK4_VOUT_2 Register Field Descriptions

Bit

7:0

Field

BUCK4_VSET2

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.22 BUCK5_VOUT_1 Register (Offset = 0x16) [Reset = 0x0]

BUCK5_VOUT_1 is shown in Figure 10-81 and described in Table 10-45.

Return to the Table 10-22.

Figure 10-81. BUCK5_VOUT_1 Register

7

6

5

4

3

2

1

0

BUCK5_VSET1

R/W-0b

Table 10-45. BUCK5_VOUT_1 Register Field Descriptions

Bit

7:0

Field

BUCK5_VSET1

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.23 BUCK5_VOUT_2 Register (Offset = 0x17) [Reset = 0x0]

BUCK5_VOUT_2 is shown in Figure 10-82 and described in Table 10-46.

Return to the Table 10-22.

Figure 10-82. BUCK5_VOUT_2 Register

7

6

5

4

3

2

1

0

BUCK5_VSET2

R/W-0b

Table 10-46. BUCK5_VOUT_2 Register Field Descriptions

Bit

7:0

Field

BUCK5_VSET2

Type

Reset

Description

R/W

0b

Voltage selection for buck regulator. See Buck regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.24 BUCK1_PG_WINDOW Register (Offset = 0x18) [Reset = 0x0]

BUCK1_PG_WINDOW is shown in Figure 10-83 and described in Table 10-47.

Return to the Table 10-22.

Figure 10-83. BUCK1_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK1_UV_THR

R/W-0b

BUCK1_OV_THR

R/W-0b

Table 10-47. BUCK1_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

BUCK1_UV_THR

0b

Powergood low threshold level for BUCK1:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

BUCK1_OV_THR

R/W

0b

Powergood high threshold level for BUCK1:

(Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.25 BUCK2_PG_WINDOW Register (Offset = 0x19) [Reset = 0x0]

BUCK2_PG_WINDOW is shown in Figure 10-84 and described in Table 10-48.

Return to the Table 10-22.

Figure 10-84. BUCK2_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK2_UV_THR

R/W-0b

BUCK2_OV_THR

R/W-0b

Table 10-48. BUCK2_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

BUCK2_UV_THR

0b

Powergood low threshold level for BUCK2:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

BUCK2_OV_THR

R/W

0b

Powergood high threshold level for BUCK2:

(Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.26 BUCK3_PG_WINDOW Register (Offset = 0x1A) [Reset = 0x0]

BUCK3_PG_WINDOW is shown in Figure 10-85 and described in Table 10-49.

Return to the Table 10-22.

Figure 10-85. BUCK3_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK3_UV_THR

R/W-0b

BUCK3_OV_THR

R/W-0b

Table 10-49. BUCK3_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

BUCK3_UV_THR

0b

Powergood low threshold level for BUCK3:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

BUCK3_OV_THR

R/W

0b

Powergood high threshold level for BUCK3:

(Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.27 BUCK4_PG_WINDOW Register (Offset = 0x1B) [Reset = 0x0]

BUCK4_PG_WINDOW is shown in Figure 10-86 and described in Table 10-50.

Return to the Table 10-22.

Figure 10-86. BUCK4_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK4_UV_THR

R/W-0b

BUCK4_OV_THR

R/W-0b

Table 10-50. BUCK4_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

BUCK4_UV_THR

0b

Powergood low threshold level for BUCK4:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

BUCK4_OV_THR

R/W

0b

Powergood high threshold level for BUCK4:

(Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.28 BUCK5_PG_WINDOW Register (Offset = 0x1C) [Reset = 0x0]

BUCK5_PG_WINDOW is shown in Figure 10-87 and described in Table 10-51.

Return to the Table 10-22.

Figure 10-87. BUCK5_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK5_UV_THR

R/W-0b

BUCK5_OV_THR

R/W-0b

Table 10-51. BUCK5_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

BUCK5_UV_THR

0b

Powergood low threshold level for BUCK5:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

BUCK5_OV_THR

R/W

0b

Powergood high threshold level for BUCK5:

(Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.29 LDO1_CTRL Register (Offset = 0x1D) [Reset = 0x60]

LDO1_CTRL is shown in Figure 10-88 and described in Table 10-52.

Return to the Table 10-22.

Figure 10-88. LDO1_CTRL Register

7

6

5

4

3

2

1

0

LDO1_RV_SEL

LDO1_PLDN

R/W-11b

LDO1_VMON_

EN

RESERVED

R/W-0b

LDO1_SLOW_

RAMP

LDO1_EN

R/W-0b

Table 10-52. LDO1_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO1_RV_SEL

R/W

0b

Select residual voltage checking for LDO1 output pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6:5

LDO1_PLDN

R/W

11b

0b

Enable output pull-down resistor when LDO1 is disabled:

(Default from NVM memory)

0b = 50 kOhm

1b = 125 Ohm

10b = 250 Ohm

11b = 500 Ohm

4

LDO1_VMON_EN

Enable LDO1 OV and UV comparators:

(Default from NVM memory)

0b = OV and UV comparators are disabled

1b = OV and UV comparators are enabled.

3:2

1

RESERVED

R/W

0b

LDO1_SLOW_RAMP

LDO1 startup slew rate selection

0b = 25 mV/µs maximum ramp up slew rate for LDO output from

0.3V to 90% of LDOn_VSET

1b = 3 mV/µs maximum ramp up slew rate for LDO output from 0.3 V

to 90% of LDOn_VSET

0

LDO1_EN

R/W

0b

Enable LDO1 regulator:

(Default from NVM memory)

0b = LDO1 regulator is disabled

1b = LDO1 regulator is enabled.

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10.7.1.30 LDO2_CTRL Register (Offset = 0x1E) [Reset = 0x60]

LDO2_CTRL is shown in Figure 10-89 and described in Table 10-53.

Return to the Table 10-22.

Figure 10-89. LDO2_CTRL Register

7

6

5

4

3

2

1

0

LDO2_RV_SEL

LDO2_PLDN

R/W-11b

LDO2_VMON_

EN

RESERVED

R/W-0b

LDO2_SLOW_

RAMP

LDO2_EN

R/W-0b

Table 10-53. LDO2_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO2_RV_SEL

R/W

0b

Select residual voltage checking for LDO2 output pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6:5

LDO2_PLDN

R/W

11b

0b

Enable output pull-down resistor when LDO2 is disabled:

(Default from NVM memory)

0b = 50 kOhm

1b = 125 Ohm

10b = 250 Ohm

11b = 500 Ohm

4

LDO2_VMON_EN

Enable LDO2 OV and UV comparators:

(Default from NVM memory)

0b = OV and UV comparators are disabled

1b = OV and UV comparators are enabled.

3:2

1

RESERVED

R/W

0b

LDO2_SLOW_RAMP

LDO2 startup slew rate selection

0b = 25 mV/µs maximum ramp up slew rate for LDO output from

0.3V to 90% of LDOn_VSET

1b = 3 mV/µs maximun ramp up slew rate for LDO output from 0.3 V

to 90% of LDOn_VSET

0

LDO2_EN

R/W

0b

Enable LDO2 regulator:

(Default from NVM memory)

0b = LDO1 regulator is disabled

1b = LDO1 regulator is enabled.

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10.7.1.31 LDO3_CTRL Register (Offset = 0x1F) [Reset = 0x60]

LDO3_CTRL is shown in Figure 10-90 and described in Table 10-54.

Return to the Table 10-22.

Figure 10-90. LDO3_CTRL Register

7

6

5

4

3

2

1

0

LDO3_RV_SEL

LDO3_PLDN

R/W-11b

LDO3_VMON_

EN

RESERVED

R/W-0b

LDO3_SLOW_

RAMP

LDO3_EN

R/W-0b

Table 10-54. LDO3_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO3_RV_SEL

R/W

0b

Select residual voltage checking for LDO3 output pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6:5

LDO3_PLDN

R/W

11b

0b

Enable output pull-down resistor when LDO3 is disabled:

(Default from NVM memory)

0b = 50 kOhm

1b = 125 Ohm

10b = 250 Ohm

11b = 500 Ohm

4

LDO3_VMON_EN

Enable LDO3 OV and UV comparators:

(Default from NVM memory)

0b = OV and UV comparators are disabled

1b = OV and UV comparators are enabled.

3:2

1

RESERVED

R/W

0b

LDO3_SLOW_RAMP

LDO3 startup slew rate selection

0b = 25 mV/µs maximum ramp up slew rate for LDO output from

0.3V to 90% of LDOn_VSET

1b = 3 mV/µs maximum ramp up slew rate for LDO output from 0.3 V

to 90% of LDOn_VSET

0

LDO3_EN

R/W

0b

Enable LDO3 regulator:

(Default from NVM memory)

0b = LDO1 regulator is disabled

1b = LDO1 regulator is enabled.

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10.7.1.32 LDO4_CTRL Register (Offset = 0x20) [Reset = 0x60]

LDO4_CTRL is shown in Figure 10-91 and described in Table 10-55.

Return to the Table 10-22.

Figure 10-91. LDO4_CTRL Register

7

6

5

4

3

2

1

0

LDO4_RV_SEL

LDO4_PLDN

R/W-11b

LDO4_VMON_

EN

RESERVED

R/W-0b

LDO4_SLOW_

RAMP

LDO4_EN

R/W-0b

Table 10-55. LDO4_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO4_RV_SEL

R/W

0b

Select residual voltage checking for LDO4 output pin.

(Default from NVM memory)

0b = Disabled

1b = Enabled

6:5

LDO4_PLDN

R/W

11b

0b

Enable output pull-down resistor when LDO4 is disabled:

(Default from NVM memory)

0b = 50 kOhm

1b = 125 Ohm

10b = 250 Ohm

11b = 500 Ohm

4

LDO4_VMON_EN

Enable LDO4 OV and UV comparators:

(Default from NVM memory)

0b = OV and UV comparators are disabled

1b = OV and UV comparators are enabled.

3:2

1

RESERVED

R/W

0b

LDO4_SLOW_RAMP

LDO4 startup slew rate selection

0b = 25 mV/µs maximum ramp up slew rate for LDO output from 0.3

V to 90% of LDOn_VSET

1b = 3 mV/µs maximum ramp up slew rate for LDO output from 0.3 V

to 90% of LDOn_VSET

0

LDO4_EN

R/W

0b

Enable LDO4 regulator:

(Default from NVM memory)

0b = LDO1 regulator is disabled

1b = LDO1 regulator is enabled.

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10.7.1.33 LDORTC_CTRL Register (Offset = 0x22) [Reset = 0x0]

LDORTC_CTRL is shown in Figure 10-92 and described in Table 10-56.

Return to the Table 10-22.

Figure 10-92. LDORTC_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

LDORTC_DIS

R/W-0b

Table 10-56. LDORTC_CTRL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

0b

LDORTC_DIS

0b

Disable LDORTC regulator:

0b = LDORTC regulator is enabled

1b = LDORTC regulator is disabled

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10.7.1.34 LDO1_VOUT Register (Offset = 0x23) [Reset = 0x0]

LDO1_VOUT is shown in Figure 10-93 and described in Table 10-57.

Return to the Table 10-22.

Figure 10-93. LDO1_VOUT Register

7

6

5

4

3

2

1

0

LDO1_BYPASS

R/W-0b

LDO1_VSET

R/W-0b

RESERVED

R/W-0b

Table 10-57. LDO1_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO1_BYPASS

R/W

0b

Set LDO1 to bypass mode:

(Default from NVM memory)

0b = LDO is set to linear regulator mode.

1b = LDO is set to bypass mode.

6:1

0

LDO1_VSET

RESERVED

R/W

0b

Voltage selection for LDO regulator. See LDO regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.35 LDO2_VOUT Register (Offset = 0x24) [Reset = 0x0]

LDO2_VOUT is shown in Figure 10-94 and described in Table 10-58.

Return to the Table 10-22.

Figure 10-94. LDO2_VOUT Register

7

6

5

4

3

2

1

0

LDO2_BYPASS

R/W-0b

LDO2_VSET

R/W-0b

RESERVED

R/W-0b

Table 10-58. LDO2_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO2_BYPASS

R/W

0b

Set LDO2 to bypass mode:

(Default from NVM memory)

0b = LDO is set to linear regulator mode.

1b = LDO is set to bypass mode.

6:1

0

LDO2_VSET

RESERVED

R/W

0b

Voltage selection for LDO regulator. See LDO regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.36 LDO3_VOUT Register (Offset = 0x25) [Reset = 0x0]

LDO3_VOUT is shown in Figure 10-95 and described in Table 10-59.

Return to the Table 10-22.

Figure 10-95. LDO3_VOUT Register

7

6

5

4

3

2

1

0

LDO3_BYPASS

R/W-0b

LDO3_VSET

R/W-0b

RESERVED

R/W-0b

Table 10-59. LDO3_VOUT Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO3_BYPASS

R/W

0b

Set LDO3 to bypass mode:

(Default from NVM memory)

0b = LDO is set to linear regulator mode.

1b = LDO is set to bypass mode.

6:1

0

LDO3_VSET

RESERVED

R/W

0b

Voltage selection for LDO regulator. See LDO regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.37 LDO4_VOUT Register (Offset = 0x26) [Reset = 0x0]

LDO4_VOUT is shown in Figure 10-96 and described in Table 10-60.

Return to the Table 10-22.

Figure 10-96. LDO4_VOUT Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

LDO4_VSET

R/W-0b

Table 10-60. LDO4_VOUT Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

LDO4_VSET

0b

6:0

0b

Voltage selection for LDO regulator. See LDO regulators chapter for

voltage levels.

(Default from NVM memory)

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10.7.1.38 LDO1_PG_WINDOW Register (Offset = 0x27) [Reset = 0x0]

LDO1_PG_WINDOW is shown in Figure 10-97 and described in Table 10-61.

Return to the Table 10-22.

Figure 10-97. LDO1_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

LDO1_UV_THR

R/W-0b

LDO1_OV_THR

R/W-0b

Table 10-61. LDO1_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

LDO1_UV_THR

0b

Powergood low threshold level for LDO1:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

LDO1_OV_THR

R/W

0b

Powergood high threshold level for LDO1:

(Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.39 LDO2_PG_WINDOW Register (Offset = 0x28) [Reset = 0x0]

LDO2_PG_WINDOW is shown in Figure 10-98 and described in Table 10-62.

Return to the Table 10-22.

Figure 10-98. LDO2_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

LDO2_UV_THR

R/W-0b

LDO2_OV_THR

R/W-0b

Table 10-62. LDO2_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

LDO2_UV_THR

0b

Powergood low threshold level for LDO2:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

LDO2_OV_THR

R/W

0b

Powergood high threshold level for LDO2:

(Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.40 LDO3_PG_WINDOW Register (Offset = 0x29) [Reset = 0x0]

LDO3_PG_WINDOW is shown in Figure 10-99 and described in Table 10-63.

Return to the Table 10-22.

Figure 10-99. LDO3_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

LDO3_UV_THR

R/W-0b

LDO3_OV_THR

R/W-0b

Table 10-63. LDO3_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

LDO3_UV_THR

0b

Powergood low threshold level for LDO3:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

LDO3_OV_THR

R/W

0b

Powergood high threshold level for LDO3:

Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.41 LDO4_PG_WINDOW Register (Offset = 0x2A) [Reset = 0x0]

LDO4_PG_WINDOW is shown in Figure 10-100 and described in Table 10-64.

Return to the Table 10-22.

Figure 10-100. LDO4_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

LDO4_UV_THR

R/W-0b

LDO4_OV_THR

R/W-0b

Table 10-64. LDO4_PG_WINDOW Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:3

RESERVED

0b

LDO4_UV_THR

0b

Powergood low threshold level for LDO4:

(Default from NVM memory)

0b = -3% / -30 mV

1b = -3.5% / -35 mV

10b = -4% / -40 mV

11b = -5% / -50 mV

100b = -6% / -60 mV

101b = -7% / -70 mV

110b = -8% / -80 mV

111b = -10% / -100 mV

2:0

LDO4_OV_THR

R/W

0b

Powergood high threshold level for LDO4:

(Default from NVM memory)

0b = +3% / +30 mV

1b = +3.5% / +35 mV

10b = +4% / +40 mV

11b = +5% / +50 mV

100b = +6% / +60 mV

101b = +7% / +70 mV

110b = +8% / +80 mV

111b = +10% / +100 mV

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10.7.1.42 VCCA_VMON_CTRL Register (Offset = 0x2B) [Reset = 0x0]

VCCA_VMON_CTRL is shown in Figure 10-101 and described in Table 10-65.

Return to the Table 10-22.

Figure 10-101. VCCA_VMON_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

VMON_DEGLIT

CH_SEL

RESERVED

R/W-0b

VCCA_VMON_

EN

R/W-0b

Table 10-65. VCCA_VMON_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5

RESERVED

R/W

0b

VMON_DEGLITCH_SEL R/W

0b

Deglitch time select for BUCKx_VMON, LDOx_VMON and

VCCA_VMON

(Default from NVM memory)

0b = 4 µs

1b = 20 µs

4:1

0

RESERVED

R/W

0b

VCCA_VMON_EN

Enable VCCA OV and UV comparators:

(Default from NVM memory)

0b = OV and UV comparators are disabled

1b = OV and UV comparators are enabled.

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10.7.1.43 VCCA_PG_WINDOW Register (Offset = 0x2C) [Reset = 0x40]

VCCA_PG_WINDOW is shown in Figure 10-102 and described in Table 10-66.

Return to the Table 10-22.

Figure 10-102. VCCA_PG_WINDOW Register

7

6

5

4

3

2

1

0

RESERVED

VCCA_PG_SE

T

VCCA_UV_THR

VCCA_OV_THR

R/W-0b

R/W-1b

R/W-0b

Table 10-66. VCCA_PG_WINDOW Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

0b

6

VCCA_PG_SET

1b

Powergood level for VCCA pin:

(Default from NVM memory)

0b = 3.3 V

1b = 5.0 V

5:3

VCCA_UV_THR

R/W

0b

Powergood low threshold level for VCCA pin:

(Default from NVM memory)

0b = -3%

1b = -3.5%

10b = -4%

11b = -5%

100b = -6%

101b = -7%

110b = -8%

111b = -10%

2:0

VCCA_OV_THR

R/W

0b

Powergood high threshold level for VCCA pin:

(Default from NVM memory)

0b = +3%

1b = +3.5%

10b = +4%

11b = +5%

100b = +6%

101b = +7%

110b = +8%

111b = +10%

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10.7.1.44 GPIO1_CONF Register (Offset = 0x31) [Reset = 0xA]

GPIO1_CONF is shown in Figure 10-103 and described in Table 10-67.

Return to the Table 10-22.

Figure 10-103. GPIO1_CONF Register

7

6

5

4

3

2

1

0

GPIO1_SEL

GPIO1_DEGLIT GPIO1_PU_PD GPIO1_PU_SE

GPIO1_OD

GPIO1_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-67. GPIO1_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO1_SEL

R/W

0b

GPIO1 signal function:

(Default from NVM memory)

0b = GPIO1

1b = TPS6594: SCL_I2C2/CS_SPI, TPS6593: CS_SPI

10b = NRSTOUT_SOC

11b = NRSTOUT_SOC

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO1_DEGLITCH_EN

GPIO1_PU_PD_EN

GPIO1_PU_SEL

R/W

0b

1b

0b

GPIO1 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO1 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO1 pin pull-up/pull-down resistor:

GPIO1_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO1_OD

GPIO1_DIR

R/W

1b

0b

GPIO1 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO1 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.45 GPIO2_CONF Register (Offset = 0x32) [Reset = 0xA]

GPIO2_CONF is shown in Figure 10-104 and described in Table 10-68.

Return to the Table 10-22.

Figure 10-104. GPIO2_CONF Register

7

6

5

4

3

2

1

0

GPIO2_SEL

GPIO2_DEGLIT GPIO2_PU_PD GPIO2_PU_SE

GPIO2_OD

GPIO2_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-68. GPIO2_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO2_SEL

R/W

0b

GPIO2 signal function:

(Default from NVM memory)

0b = GPIO2

1b = TRIG_WDOG

10b = TPS6594: SDA_I2C2/SDO_SPI, TPS6593: SDO_SPI

11b = TPS6594: SDA_I2C2/SDO_SPI, TPS6593: SDO_SPI

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO2_DEGLITCH_EN

GPIO2_PU_PD_EN

GPIO2_PU_SEL

R/W

0b

1b

0b

GPIO2 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO2 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO2 pin pull-up/pull-down resistor:

GPIO2_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO2_OD

GPIO2_DIR

R/W

1b

0b

GPIO2 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO2 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.46 GPIO3_CONF Register (Offset = 0x33) [Reset = 0xA]

GPIO3_CONF is shown in Figure 10-105 and described in Table 10-69.

Return to the Table 10-22.

Figure 10-105. GPIO3_CONF Register

7

6

5

4

3

2

1

0

GPIO3_SEL

GPIO3_DEGLIT GPIO3_PU_PD GPIO3_PU_SE

GPIO3_OD

GPIO3_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-69. GPIO3_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO3_SEL

R/W

0b

GPIO3 signal function:

(Default from NVM memory)

0b = GPIO3

1b = CLK32KOUT

10b = TPS6594: NERR_SOC, TPS6593: reserved

11b = TPS6594: NERR_SOC, TPS6593: reserved

100b = NSLEEP1

101b = NSLEEP2

110b = LP_WKUP1

111b = LP_WKUP2

4

3

2

GPIO3_DEGLITCH_EN

GPIO3_PU_PD_EN

GPIO3_PU_SEL

R/W

0b

1b

0b

GPIO3 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO3 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO3 pin pull-up/pull-down resistor:

GPIO3_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO3_OD

GPIO3_DIR

R/W

1b

0b

GPIO3 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO3 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.47 GPIO4_CONF Register (Offset = 0x34) [Reset = 0xA]

GPIO4_CONF is shown in Figure 10-106 and described in Table 10-70.

Return to the Table 10-22.

Figure 10-106. GPIO4_CONF Register

7

6

5

4

3

2

1

0

GPIO4_SEL

GPIO4_DEGLIT GPIO4_PU_PD GPIO4_PU_SE

GPIO4_OD

GPIO4_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-70. GPIO4_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO4_SEL

R/W

0b

GPIO4 signal function:

(Default from NVM memory)

0b = GPIO4

1b = CLK32KOUT

10b = CLK32KOUT

11b = CLK32KOUT

100b = NSLEEP1

101b = NSLEEP2

110b = LP_WKUP1

111b = LP_WKUP2

4

3

2

GPIO4_DEGLITCH_EN

GPIO4_PU_PD_EN

GPIO4_PU_SEL

R/W

0b

1b

0b

GPIO4 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO4 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO4 pin pull-up/pull-down resistor:

GPIO4_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO4_OD

GPIO4_DIR

R/W

1b

0b

GPIO4 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO4 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.48 GPIO5_CONF Register (Offset = 0x35) [Reset = 0xA]

GPIO5_CONF is shown in Figure 10-107 and described in Table 10-71.

Return to the Table 10-22.

Figure 10-107. GPIO5_CONF Register

7

6

5

4

3

2

1

0

GPIO5_SEL

GPIO5_DEGLIT GPIO5_PU_PD GPIO5_PU_SE

GPIO5_OD

GPIO5_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-71. GPIO5_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO5_SEL

R/W

0b

GPIO5 signal function:

(Default from NVM memory)

0b = GPIO5

1b = SCLK_SPMI

10b = SCLK_SPMI

11b = SCLK_SPMI

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO5_DEGLITCH_EN

GPIO5_PU_PD_EN

GPIO5_PU_SEL

R/W

0b

1b

0b

GPIO5 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO5 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO5 pin pull-up/pull-down resistor:

GPIO5_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO5_OD

GPIO5_DIR

R/W

1b

0b

GPIO5 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO5 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.49 GPIO6_CONF Register (Offset = 0x36) [Reset = 0xA]

GPIO6_CONF is shown in Figure 10-108 and described in Table 10-72.

Return to the Table 10-22.

Figure 10-108. GPIO6_CONF Register

7

6

5

4

3

2

1

0

GPIO6_SEL

GPIO6_DEGLIT GPIO6_PU_PD GPIO6_PU_SE

GPIO6_OD

GPIO6_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-72. GPIO6_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO6_SEL

R/W

0b

GPIO6 signal function:

(Default from NVM memory)

0b = GPIO6

1b = SDATA_SPMI

10b = SDATA_SPMI

11b = SDATA_SPMI

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO6_DEGLITCH_EN

GPIO6_PU_PD_EN

GPIO6_PU_SEL

R/W

0b

1b

0b

GPIO6 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO6 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO6 pin pull-up/pull-down resistor:

GPIO6_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO6_OD

GPIO6_DIR

R/W

1b

0b

GPIO6 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO6 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.50 GPIO7_CONF Register (Offset = 0x37) [Reset = 0xA]

GPIO7_CONF is shown in Figure 10-109 and described in Table 10-73.

Return to the Table 10-22.

Figure 10-109. GPIO7_CONF Register

7

6

5

4

3

2

1

0

GPIO7_SEL

GPIO7_DEGLIT GPIO7_PU_PD GPIO7_PU_SE

GPIO7_OD

GPIO7_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-73. GPIO7_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO7_SEL

R/W

0b

GPIO7 signal function:

(Default from NVM memory)

0b = GPIO7

1b = TPS6594: NERR_MCU, TPS6593: reserved

10b = TPS6594: NERR_MCU, TPS6593: reserved

11b = TPS6594: NERR_MCU, TPS6593: reserved

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO7_DEGLITCH_EN

GPIO7_PU_PD_EN

GPIO7_PU_SEL

R/W

0b

1b

0b

GPIO7 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO7 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO7 pin pull-up/pull-down resistor:

GPIO7_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO7_OD

GPIO7_DIR

R/W

1b

0b

GPIO7 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO7 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.51 GPIO8_CONF Register (Offset = 0x38) [Reset = 0xA]

GPIO8_CONF is shown in Figure 10-110 and described in Table 10-74.

Return to the Table 10-22.

Figure 10-110. GPIO8_CONF Register

7

6

5

4

3

2

1

0

GPIO8_SEL

GPIO8_DEGLIT GPIO8_PU_PD GPIO8_PU_SE

GPIO8_OD

GPIO8_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-74. GPIO8_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO8_SEL

R/W

0b

GPIO8 signal function:

(Default from NVM memory)

0b = GPIO8

1b = CLK32KOUT

10b = SYNCCLKOUT

11b = TPS6594: DISABLE_WDOG, TPS6593: reserved

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO8_DEGLITCH_EN

GPIO8_PU_PD_EN

GPIO8_PU_SEL

R/W

0b

1b

0b

GPIO8 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO8 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO8 pin pull-up/pull-down resistor:

GPIO8_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO8_OD

GPIO8_DIR

R/W

1b

0b

GPIO8 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO8 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.52 GPIO9_CONF Register (Offset = 0x39) [Reset = 0xA]

GPIO9_CONF is shown in Figure 10-111 and described in Table 10-75.

Return to the Table 10-22.

Figure 10-111. GPIO9_CONF Register

7

6

5

4

3

2

1

0

GPIO9_SEL

GPIO9_DEGLIT GPIO9_PU_PD GPIO9_PU_SE

GPIO9_OD

GPIO9_DIR

CH_EN

_EN

L

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-75. GPIO9_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

GPIO9_SEL

R/W

0b

GPIO9 signal function:

(Default from NVM memory)

0b = GPIO9

1b = PGOOD

10b = TPS6594: DISABLE_WDOG, TPS6593: reserved

11b = SYNCCLKOUT

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO9_DEGLITCH_EN

GPIO9_PU_PD_EN

GPIO9_PU_SEL

R/W

0b

1b

0b

GPIO9 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

Control for GPIO9 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO9 pin pull-up/pull-down resistor:

GPIO9_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO9_OD

GPIO9_DIR

R/W

1b

0b

GPIO9 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO9 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.53 GPIO10_CONF Register (Offset = 0x3A) [Reset = 0xA]

GPIO10_CONF is shown in Figure 10-112 and described in Table 10-76.

Return to the Table 10-22.

Figure 10-112. GPIO10_CONF Register

7

6

5

4

3

2

1

0

GPIO10_SEL

GPIO10_DEGLI GPIO10_PU_P GPIO10_PU_S

GPIO10_OD

GPIO10_DIR

TCH_EN

D_EN

EL

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-76. GPIO10_CONF Register Field Descriptions

Bit

Field

GPIO10_SEL

Type

Reset

Description

7:5

R/W

0b

GPIO10 signal function:

(Default from NVM memory)

0b = GPIO10

1b = SYNCCLKIN

10b = SYNCCLKOUT

11b = CLK32KOUT

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO10_DEGLITCH_EN R/W

0b

1b

0b

GPIO10 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

GPIO10_PU_PD_EN

GPIO10_PU_SEL

R/W

Control for GPIO10 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO10 pin pull-up/pull-down resistor:

GPIO10_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO10_OD

GPIO10_DIR

R/W

1b

0b

GPIO10 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO10 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.54 GPIO11_CONF Register (Offset = 0x3B) [Reset = 0xA]

GPIO11_CONF is shown in Figure 10-113 and described in Table 10-77.

Return to the Table 10-22.

Figure 10-113. GPIO11_CONF Register

7

6

5

4

3

2

1

0

GPIO11_SEL

GPIO11_DEGLI GPIO11_PU_P GPIO11_PU_S

GPIO11_OD

GPIO11_DIR

TCH_EN

D_EN

EL

R/W-0b

R/W-1b

R/W-0b

R/W-1b

R/W-0b

Table 10-77. GPIO11_CONF Register Field Descriptions

Bit

Field

GPIO11_SEL

Type

Reset

Description

7:5

R/W

0b

GPIO11 signal function:

(Default from NVM memory)

0b = GPIO11

1b = TRIG_WDOG

10b = NRSTOUT_SOC

11b = NRSTOUT_SOC

100b = NSLEEP1

101b = NSLEEP2

110b = WKUP1

111b = WKUP2

4

3

2

GPIO11_DEGLITCH_EN R/W

0b

1b

0b

GPIO11 signal deglitch time when signal direction is input:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time.

GPIO11_PU_PD_EN

GPIO11_PU_SEL

R/W

Control for GPIO11 pin pull-up/pull-down resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for GPIO11 pin pull-up/pull-down resistor:

GPIO11_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

GPIO11_OD

GPIO11_DIR

R/W

1b

0b

GPIO11 signal type when configured to output:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

GPIO11 signal direction:

(Default from NVM memory)

0b = Input

1b = Output

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10.7.1.55 NPWRON_CONF Register (Offset = 0x3C) [Reset = 0x88]

NPWRON_CONF is shown in Figure 10-114 and described in Table 10-78.

Return to the Table 10-22.

Figure 10-114. NPWRON_CONF Register

7

6

5

4

3

2

1

0

NPWRON_SEL

R/W-10b

ENABLE_POL ENABLE_DEGL ENABLE_PU_P ENABLE_PU_S RESERVED

NRSTOUT_OD

ITCH_EN

D_EN

EL

R/W-0b

R/W-1b

R/W-0b

Table 10-78. NPWRON_CONF Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

NPWRON_SEL

R/W

10b

NPWRON/ENABLE signal function:

(Default from NVM memory)

0b = ENABLE

1b = NPWRON

10b = None

11b = None

5

4

ENABLE_POL

R/W

0b

Control for ENABLE pin polarity:

(Default from NVM memory)

0b = Active high

1b = Active low

ENABLE_DEGLITCH_EN R/W

NPWRON/ENABLE signal deglitch time:

(Default from NVM memory)

0b = No deglitch, only synchronization.

1b = 8 µs deglitch time when ENABLE, 50 ms deglitch time when

NPWRON.

3

2

ENABLE_PU_PD_EN

ENABLE_PU_SEL

R/W

1b

0b

Control for NPWRON/ENABLE pin pull-up resistor:

(Default from NVM memory)

0b = Pull-up/pull-down resistor disabled

1b = Pull-up/pull-down resistor enabled

Control for NPWRON/ENABLE pin pull-down resistor:

ENABLE_PU_PD_EN must be 1 to select the resistor.

(Default from NVM memory)

0b = Pull-down resistor selected

1b = Pull-up resistor selected

1

0

RESERVED

R/W

0b

NRSTOUT_OD

NRSTOUT signal type:

(Default from NVM memory)

0b = Push-pull output

1b = Open-drain output

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10.7.1.56 GPIO_OUT_1 Register (Offset = 0x3D) [Reset = 0x0]

GPIO_OUT_1 is shown in Figure 10-115 and described in Table 10-79.

Return to the Table 10-22.

Figure 10-115. GPIO_OUT_1 Register

7

6

5

4

3

2

1

0

GPIO8_OUT

R/W-0b

GPIO7_OUT

R/W-0b

GPIO6_OUT

R/W-0b

GPIO5_OUT

R/W-0b

GPIO4_OUT

R/W-0b

GPIO3_OUT

R/W-0b

GPIO2_OUT

R/W-0b

GPIO1_OUT

R/W-0b

Table 10-79. GPIO_OUT_1 Register Field Descriptions

Bit

Field

GPIO8_OUT

Type

Reset

Description

7

R/W

0b

Control for GPIO8 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

6

5

4

3

2

1

0

GPIO7_OUT

GPIO6_OUT

GPIO5_OUT

GPIO4_OUT

GPIO3_OUT

GPIO2_OUT

GPIO1_OUT

R/W

0b

Control for GPIO7 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

Control for GPIO6 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

Control for GPIO5 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

Control for GPIO4 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

Control for GPIO3 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

Control for GPIO2 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

Control for GPIO1 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

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10.7.1.57 GPIO_OUT_2 Register (Offset = 0x3E) [Reset = 0x0]

GPIO_OUT_2 is shown in Figure 10-116 and described in Table 10-80.

Return to the Table 10-22.

Figure 10-116. GPIO_OUT_2 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

GPIO11_OUT

R/W-0b

GPIO10_OUT

R/W-0b

GPIO9_OUT

R/W-0b

Table 10-80. GPIO_OUT_2 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:3

2

RESERVED

0b

GPIO11_OUT

0b

Control for GPIO11 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

1

0

GPIO10_OUT

GPIO9_OUT

R/W

0b

Control for GPIO10 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

Control for GPIO9 signal when configured to GPIO Output:

(Default from NVM memory)

0b = Low

1b = High

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10.7.1.58 GPIO_IN_1 Register (Offset = 0x3F) [Reset = 0x0]

GPIO_IN_1 is shown in Figure 10-117 and described in Table 10-81.

Return to the Table 10-22.

Figure 10-117. GPIO_IN_1 Register

7

6

5

4

3

2

1

0

GPIO8_IN

R-0b

GPIO7_IN

R-0b

GPIO6_IN

R-0b

GPIO5_IN

R-0b

GPIO4_IN

R-0b

GPIO3_IN

R-0b

GPIO2_IN

R-0b

GPIO1_IN

R-0b

Table 10-81. GPIO_IN_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO8_IN

GPIO7_IN

GPIO6_IN

GPIO5_IN

GPIO4_IN

GPIO3_IN

GPIO2_IN

GPIO1_IN

R

0b

Level of GPIO8 signal:

0b = Low

1b = High

6

5

4

3

2

1

0

R

0b

Level of GPIO7 signal:

0b = Low

1b = High

Level of GPIO6 signal:

0b = Low

1b = High

Level of GPIO5 signal:

0b = Low

1b = High

Level of GPIO4 signal:

0b = Low

1b = High

Level of GPIO3 signal:

0b = Low

1b = High

Level of GPIO2 signal:

0b = Low

1b = High

Level of GPIO1 signal:

0b = Low

1b = High

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10.7.1.59 GPIO_IN_2 Register (Offset = 0x40) [Reset = 0x0]

GPIO_IN_2 is shown in Figure 10-118 and described in Table 10-82.

Return to the Table 10-22.

Figure 10-118. GPIO_IN_2 Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

NPWRON_IN

R-0b

GPIO11_IN

R-0b

GPIO10_IN

R-0b

GPIO9_IN

R-0b

Table 10-82. GPIO_IN_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

R

0b

NPWRON_IN

R

0b

Level of NPWRON/ENABLE signal:

0b = Low

1b = High

2

1

0

GPIO11_IN

GPIO10_IN

GPIO9_IN

R

0b

Level of GPIO11 signal:

0b = Low

1b = High

Level of GPIO10 signal:

0b = Low

1b = High

Level of GPIO9 signal:

0b = Low

1b = High

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10.7.1.60 RAIL_SEL_1 Register (Offset = 0x41) [Reset = 0x0]

RAIL_SEL_1 is shown in Figure 10-119 and described in Table 10-83.

Return to the Table 10-22.

Figure 10-119. RAIL_SEL_1 Register

7

6

5

4

3

2

1

0

BUCK4_GRP_SEL

R/W-0b

BUCK3_GRP_SEL

R/W-0b

BUCK2_GRP_SEL

R/W-0b

BUCK1_GRP_SEL

R/W-0b

Table 10-83. RAIL_SEL_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5:4

3:2

1:0

BUCK4_GRP_SEL

R/W

0b

Rail group selection for BUCK4:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

BUCK3_GRP_SEL

BUCK2_GRP_SEL

BUCK1_GRP_SEL

R/W

0b

Rail group selection for BUCK3:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

Rail group selection for BUCK2:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

Rail group selection for BUCK1:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

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10.7.1.61 RAIL_SEL_2 Register (Offset = 0x42) [Reset = 0x0]

RAIL_SEL_2 is shown in Figure 10-120 and described in Table 10-84.

Return to the Table 10-22.

Figure 10-120. RAIL_SEL_2 Register

7

6

5

4

3

2

1

0

LDO3_GRP_SEL

LDO2_GRP_SEL

R/W-0b

LDO1_GRP_SEL

R/W-0b

BUCK5_GRP_SEL

R/W-0b

Table 10-84. RAIL_SEL_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

LDO3_GRP_SEL

R/W

0b

Rail group selection for LDO3:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

5:4

3:2

1:0

LDO2_GRP_SEL

LDO1_GRP_SEL

BUCK5_GRP_SEL

R/W

0b

Rail group selection for LDO2:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

Rail group selection for LDO1:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

Rail group selection for BUCK5:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

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10.7.1.62 RAIL_SEL_3 Register (Offset = 0x43) [Reset = 0x0]

RAIL_SEL_3 is shown in Figure 10-121 and described in Table 10-85.

Return to the Table 10-22.

Figure 10-121. RAIL_SEL_3 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

VCCA_GRP_SEL

R/W-0b

LDO4_GRP_SEL

R/W-0b

Table 10-85. RAIL_SEL_3 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3:2

RESERVED

0b

VCCA_GRP_SEL

0b

Rail group selection for VCCA monitoring:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

1:0

LDO4_GRP_SEL

R/W

0b

Rail group selection for LDO4:

(Default from NVM memory)

0b = No group assigned

1b = MCU rail group

10b = SOC rail group

11b = OTHER rail group

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10.7.1.63 FSM_TRIG_SEL_1 Register (Offset = 0x44) [Reset = 0x0]

FSM_TRIG_SEL_1 is shown in Figure 10-122 and described in Table 10-86.

Return to the Table 10-22.

Figure 10-122. FSM_TRIG_SEL_1 Register

7

6

5

4

3

2

1

0

SEVERE_ERR_TRIG

R/W-0b

OTHER_RAIL_TRIG

R/W-0b

SOC_RAIL_TRIG

R/W-0b

MCU_RAIL_TRIG

R/W-0b

Table 10-86. FSM_TRIG_SEL_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5:4

3:2

1:0

SEVERE_ERR_TRIG

R/W

0b

Trigger selection for Severe Error:

(Default from NVM memory)

0b = Immediate shutdown

1b = Orderly shutdown

10b = MCU power error

11b = SOC power error

OTHER_RAIL_TRIG

SOC_RAIL_TRIG

MCU_RAIL_TRIG

R/W

0b

Trigger selection for OTHER rail group:

(Default from NVM memory)

0b = Immediate shutdown

1b = Orderly shutdown

10b = MCU power error

11b = SOC power error

Trigger selection for SOC rail group:

(Default from NVM memory)

0b = Immediate shutdown

1b = Orderly shutdown

10b = MCU power error

11b = SOC power error

Trigger selection for MCU rail group:

(Default from NVM memory)

0b = Immediate shutdown

1b = Orderly shutdown

10b = MCU power error

11b = SOC power error

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10.7.1.64 FSM_TRIG_SEL_2 Register (Offset = 0x45) [Reset = 0x0]

FSM_TRIG_SEL_2 is shown in Figure 10-123 and described in Table 10-87.

Return to the Table 10-22.

Figure 10-123. FSM_TRIG_SEL_2 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

MODERATE_ERR_TRIG

R/W-0b

Table 10-87. FSM_TRIG_SEL_2 Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7:2

1:0

R/W

0b

MODERATE_ERR_TRIG R/W

0b

Trigger selection for Moderate Error:

(Default from NVM memory)

0b = Immediate shutdown

1b = Orderly shutdown

10b = MCU power error

11b = SOC power error

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10.7.1.65 FSM_TRIG_MASK_1 Register (Offset = 0x46) [Reset = 0x0]

FSM_TRIG_MASK_1 is shown in Figure 10-124 and described in Table 10-88.

Return to the Table 10-22.

Figure 10-124. FSM_TRIG_MASK_1 Register

7

6

5

4

3

2

1

0

GPIO4_FSM_M GPIO4_FSM_M GPIO3_FSM_M GPIO3_FSM_M GPIO2_FSM_M GPIO2_FSM_M GPIO1_FSM_M GPIO1_FSM_M

ASK_POL

ASK

ASK_POL

ASK

ASK_POL

ASK

ASK_POL

ASK

R/W-0b

Table 10-88. FSM_TRIG_MASK_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO4_FSM_MASK_POL R/W

0b

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

6

5

4

3

2

1

0

GPIO4_FSM_MASK

R/W

0b

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

GPIO3_FSM_MASK_POL R/W

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

GPIO3_FSM_MASK

R/W

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

GPIO2_FSM_MASK_POL R/W

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

GPIO2_FSM_MASK

R/W

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

GPIO1_FSM_MASK_POL R/W

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

GPIO1_FSM_MASK

R/W

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

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10.7.1.66 FSM_TRIG_MASK_2 Register (Offset = 0x47) [Reset = 0x0]

FSM_TRIG_MASK_2 is shown in Figure 10-125 and described in Table 10-89.

Return to the Table 10-22.

Figure 10-125. FSM_TRIG_MASK_2 Register

7

6

5

4

3

2

1

0

GPIO8_FSM_M GPIO8_FSM_M GPIO7_FSM_M GPIO7_FSM_M GPIO6_FSM_M GPIO6_FSM_M GPIO5_FSM_M GPIO5_FSM_M

ASK_POL

ASK

ASK_POL

ASK

ASK_POL

ASK

ASK_POL

ASK

R/W-0b

Table 10-89. FSM_TRIG_MASK_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO8_FSM_MASK_POL R/W

0b

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

6

5

4

3

2

1

0

GPIO8_FSM_MASK

R/W

0b

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

GPIO7_FSM_MASK_POL R/W

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

GPIO7_FSM_MASK

R/W

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

GPIO6_FSM_MASK_POL R/W

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

GPIO6_FSM_MASK

R/W

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

GPIO5_FSM_MASK_POL R/W

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

GPIO5_FSM_MASK

R/W

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

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10.7.1.67 FSM_TRIG_MASK_3 Register (Offset = 0x48) [Reset = 0x0]

FSM_TRIG_MASK_3 is shown in Figure 10-126 and described in Table 10-90.

Return to the Table 10-22.

Figure 10-126. FSM_TRIG_MASK_3 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

GPIO11_FSM_ GPIO11_FSM_ GPIO10_FSM_ GPIO10_FSM_ GPIO9_FSM_M GPIO9_FSM_M

MASK_POL

MASK

MASK_POL

MASK

ASK_POL

ASK

R/W-0b

Table 10-90. FSM_TRIG_MASK_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5

RESERVED

R/W

0b

GPIO11_FSM_MASK_PO R/W

L

0b

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

4

3

2

1

0

GPIO11_FSM_MASK

R/W

0b

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

GPIO10_FSM_MASK_PO R/W

L

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

GPIO10_FSM_MASK

R/W

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

GPIO9_FSM_MASK_POL R/W

FSM trigger masking polarity select for GPIOx:

(Default from NVM memory)

0b = Masking sets signal value to '0'

1b = Masking sets signal value to '1'

GPIO9_FSM_MASK

R/W

FSM trigger mask for GPIOx:

(Default from NVM memory)

0b = Not masked

1b = Masked

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10.7.1.68 MASK_BUCK1_2 Register (Offset = 0x49) [Reset = 0x0]

MASK_BUCK1_2 is shown in Figure 10-127 and described in Table 10-91.

Return to the Table 10-22.

Figure 10-127. MASK_BUCK1_2 Register

7

6

5

4

3

2

1

0

BUCK2_ILIM_M RESERVED

ASK

BUCK2_UV_M BUCK2_OV_M BUCK1_ILIM_M RESERVED

BUCK1_UV_M BUCK1_OV_M

ASK

R/W-0b

Table 10-91. MASK_BUCK1_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK2_ILIM_MASK

R/W

0b

Masking for BUCK2 current monitoring interrupt BUCK2_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

6

5

RESERVED

R/W

0b

BUCK2_UV_MASK

Masking of BUCK2 under-voltage detection interrupt

BUCK2_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

4

3

BUCK2_OV_MASK

BUCK1_ILIM_MASK

R/W

0b

Masking of BUCK2 over-voltage detection interrupt BUCK2_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking for BUCK1 current monitoring interrupt BUCK1_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2

1

RESERVED

R/W

0b

BUCK1_UV_MASK

Masking of BUCK1 under-voltage detection interrupt

BUCK1_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

BUCK1_OV_MASK

R/W

0b

Masking of BUCK1 over-voltage detection interrupt BUCK1_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.69 MASK_BUCK3_4 Register (Offset = 0x4A) [Reset = 0x0]

MASK_BUCK3_4 is shown in Figure 10-128 and described in Table 10-92.

Return to the Table 10-22.

Figure 10-128. MASK_BUCK3_4 Register

7

6

5

4

3

2

1

0

BUCK4_ILIM_M RESERVED

ASK

BUCK4_UV_M BUCK4_OV_M BUCK3_ILIM_M RESERVED

BUCK3_UV_M BUCK3_OV_M

ASK

R/W-0b

Table 10-92. MASK_BUCK3_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK4_ILIM_MASK

R/W

0b

Masking for BUCK4 current monitoring interrupt BUCK4_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

6

5

RESERVED

R/W

0b

BUCK4_UV_MASK

Masking of BUCK4 under-voltage detection interrupt

BUCK4_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

4

3

BUCK4_OV_MASK

BUCK3_ILIM_MASK

R/W

0b

Masking of BUCK4 over-voltage detection interrupt BUCK4_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking for BUCK3 current monitoring interrupt BUCK3_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2

1

RESERVED

R/W

0b

BUCK3_UV_MASK

Masking of BUCK3 under-voltage detection interrupt

BUCK3_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

BUCK3_OV_MASK

R/W

0b

Masking of BUCK3 over-voltage detection interrupt BUCK3_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.70 MASK_BUCK5 Register (Offset = 0x4B) [Reset = 0x0]

MASK_BUCK5 is shown in Figure 10-129 and described in Table 10-93.

Return to the Table 10-22.

Figure 10-129. MASK_BUCK5 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK5_ILIM_M RESERVED

ASK

BUCK5_UV_M BUCK5_OV_M

ASK

R/W-0b

Table 10-93. MASK_BUCK5 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3

RESERVED

0b

BUCK5_ILIM_MASK

0b

Masking for BUCK5 current monitoring interrupt BUCK5_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2

1

RESERVED

R/W

0b

BUCK5_UV_MASK

Masking of BUCK5 under-voltage detection interrupt

BUCK5_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

BUCK5_OV_MASK

R/W

0b

Masking of BUCK5 over-voltage detection interrupt BUCK5_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.71 MASK_LDO1_2 Register (Offset = 0x4C) [Reset = 0x0]

MASK_LDO1_2 is shown in Figure 10-130 and described in Table 10-94.

Return to the Table 10-22.

Figure 10-130. MASK_LDO1_2 Register

7

6

5

4

3

2

1

0

LDO2_ILIM_MA RESERVED

SK

LDO2_UV_MA LDO2_OV_MA LDO1_ILIM_MA RESERVED

LDO1_UV_MA LDO1_OV_MA

SK

R/W-0b

Table 10-94. MASK_LDO1_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO2_ILIM_MASK

R/W

0b

Masking for LDO2 current monitoring interrupt LDO2_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

6

5

RESERVED

R/W

0b

LDO2_UV_MASK

Masking of LDO2 under-voltage detection interrupt LDO2_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

4

3

LDO2_OV_MASK

LDO1_ILIM_MASK

R/W

0b

Masking of LDO2 over-voltage detection interrupt LDO2_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking for LDO1 current monitoring interrupt LDO1_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2

1

RESERVED

R/W

0b

LDO1_UV_MASK

Masking of LDO1 under-voltage detection interrupt LDO1_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

LDO1_OV_MASK

R/W

0b

Masking of LDO1 over-voltage detection interrupt LDO1_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.72 MASK_LDO3_4 Register (Offset = 0x4D) [Reset = 0x0]

MASK_LDO3_4 is shown in Figure 10-131 and described in Table 10-95.

Return to the Table 10-22.

Figure 10-131. MASK_LDO3_4 Register

7

6

5

4

3

2

1

0

LDO4_ILIM_MA RESERVED

SK

LDO4_UV_MA LDO4_OV_MA LDO3_ILIM_MA RESERVED

LDO3_UV_MA LDO3_OV_MA

SK

R/W-0b

Table 10-95. MASK_LDO3_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO4_ILIM_MASK

R/W

0b

Masking for LDO4 current monitoring interrupt LDO4_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

6

5

RESERVED

R/W

0b

LDO4_UV_MASK

Masking of LDO4 under-voltage detection interrupt LDO4_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

4

3

LDO4_OV_MASK

LDO3_ILIM_MASK

R/W

0b

Masking of LDO4 over-voltage detection interrupt LDO4_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking for LDO3 current monitoring interrupt LDO3_ILIM_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2

1

RESERVED

R/W

0b

LDO3_UV_MASK

Masking of LDO3 under-voltage detection interrupt LDO3_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

LDO3_OV_MASK

R/W

0b

Masking of LDO3 over-voltage detection interrupt LDO3_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.73 MASK_VMON Register (Offset = 0x4E) [Reset = 0x0]

MASK_VMON is shown in Figure 10-132 and described in Table 10-96.

Return to the Table 10-22.

Figure 10-132. MASK_VMON Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

VCCA_UV_MA VCCA_OV_MA

SK

R/W-0b

Table 10-96. MASK_VMON Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1

RESERVED

0b

VCCA_UV_MASK

0b

Masking of VCCA under-voltage detection interrupt VCCA_UV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

VCCA_OV_MASK

R/W

0b

Masking of VCCA over-voltage detection interrupt VCCA_OV_INT:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.74 MASK_GPIO1_8_FALL Register (Offset = 0x4F) [Reset = 0x0]

MASK_GPIO1_8_FALL is shown in Figure 10-133 and described in Table 10-97.

Return to the Table 10-22.

Figure 10-133. MASK_GPIO1_8_FALL Register

7

6

5

4

3

2

1

0

GPIO8_FALL_ GPIO7_FALL_ GPIO6_FALL_ GPIO5_FALL_ GPIO4_FALL_ GPIO3_FALL_ GPIO2_FALL_ GPIO1_FALL_

MASK

R/W-0b

Table 10-97. MASK_GPIO1_8_FALL Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO8_FALL_MASK

R/W

0b

Masking of interrupt for GPIO8 low state transition:

This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

6

5

4

3

2

1

0

GPIO7_FALL_MASK

GPIO6_FALL_MASK

GPIO5_FALL_MASK

GPIO4_FALL_MASK

GPIO3_FALL_MASK

GPIO2_FALL_MASK

GPIO1_FALL_MASK

R/W

0b

Masking of interrupt for GPIO7 low state transition:

This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO6 low state transition:

This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO5 low state transition:

This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO4 low state transition:

This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO3 low state transition:

This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO2 low state transition:

This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO1 low state transition:

This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.75 MASK_GPIO1_8_RISE Register (Offset = 0x50) [Reset = 0x0]

MASK_GPIO1_8_RISE is shown in Figure 10-134 and described in Table 10-98.

Return to the Table 10-22.

Figure 10-134. MASK_GPIO1_8_RISE Register

7

6

5

4

3

2

1

0

GPIO8_RISE_ GPIO7_RISE_ GPIO6_RISE_ GPIO5_RISE_ GPIO4_RISE_ GPIO3_RISE_ GPIO2_RISE_ GPIO1_RISE_

MASK

R/W-0b

Table 10-98. MASK_GPIO1_8_RISE Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO8_RISE_MASK

R/W

0b

Masking of interrupt for GPIO8 high state transition:

This bit does not affect GPIO8_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

6

5

4

3

2

1

0

GPIO7_RISE_MASK

GPIO6_RISE_MASK

GPIO5_RISE_MASK

GPIO4_RISE_MASK

GPIO3_RISE_MASK

GPIO2_RISE_MASK

GPIO1_RISE_MASK

R/W

0b

Masking of interrupt for GPIO7 high state transition:

This bit does not affect GPIO7_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO6 high state transition:

This bit does not affect GPIO6_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO5 high state transition:

This bit does not affect GPIO5_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO4 high state transition:

This bit does not affect GPIO4_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO3 high state transition:

This bit does not affect GPIO3_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO2 high state transition:

This bit does not affect GPIO2_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO1 high state transition:

This bit does not affect GPIO1_IN status bit in GPIO_IN_1 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.76 MASK_GPIO9_11 Register (Offset = 0x51) [Reset = 0x0]

MASK_GPIO9_11 is shown in Figure 10-135 and described in Table 10-99.

Return to the Table 10-22.

Figure 10-135. MASK_GPIO9_11 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

GPIO11_RISE_ GPIO10_RISE_ GPIO9_RISE_ GPIO11_FALL_ GPIO10_FALL_ GPIO9_FALL_

MASK

R/W-0b

Table 10-99. MASK_GPIO9_11 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5

RESERVED

0b

GPIO11_RISE_MASK

0b

Masking of interrupt for GPIO11 high state transition:

This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

4

3

2

1

0

GPIO10_RISE_MASK

GPIO9_RISE_MASK

GPIO11_FALL_MASK

GPIO10_FALL_MASK

GPIO9_FALL_MASK

R/W

0b

Masking of interrupt for GPIO10 high state transition:

This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO9 high state transition:

This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO11 low state transition:

This bit does not affect GPIO11_IN status bit in GPIO_IN_2 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO10 low state transition:

This bit does not affect GPIO10_IN status bit in GPIO_IN_2 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of interrupt for GPIO9 low state transition:

This bit does not affect GPIO9_IN status bit in GPIO_IN_2 register.

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.77 MASK_STARTUP Register (Offset = 0x52) [Reset = 0x0]

MASK_STARTUP is shown in Figure 10-136 and described in Table 10-100.

Return to the Table 10-22.

Figure 10-136. MASK_STARTUP Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

SOFT_REBOO

T_MASK

FSD_MASK

RESERVED

R/W-0b

ENABLE_MAS NPWRON_STA

K

RT_MASK

R/W-0b

Table 10-100. MASK_STARTUP Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5

RESERVED

0b

SOFT_REBOOT_MASK

0b

Masking of SOFT_REBOOT_MASK interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

4

FSD_MASK

R/W

0b

Masking of FSD_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

3:2

1

RESERVED

R/W

0b

ENABLE_MASK

Masking of ENABLE_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

NPWRON_START_MASK R/W

0b

Masking of NPWRON_START_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.78 MASK_MISC Register (Offset = 0x53) [Reset = 0x0]

MASK_MISC is shown in Figure 10-137 and described in Table 10-101.

Return to the Table 10-22.

Figure 10-137. MASK_MISC Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

TWARN_MASK

RESERVED EXT_CLK_MAS BIST_PASS_M

K

ASK

R/W-0b

Table 10-101. MASK_MISC Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3

RESERVED

0b

TWARN_MASK

0b

Masking of TWARN_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2

1

RESERVED

R/W

0b

EXT_CLK_MASK

Masking of EXT_CLK_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

BIST_PASS_MASK

R/W

0b

Masking of BIST_PASS_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.79 MASK_MODERATE_ERR Register (Offset = 0x54) [Reset = 0x0]

MASK_MODERATE_ERR is shown in Figure 10-138 and described in Table 10-102.

Return to the Table 10-22.

Figure 10-138. MASK_MODERATE_ERR Register

7

6

5

4

3

2

1

0

NRSTOUT_RE NINT_READBA NPWRON_LON SPMI_ERR_MA RESERVED

REG_CRC_ER BIST_FAIL_MA

RESERVED

ADBACK_MAS

K

CK_MASK

G_MASK

SK

R_MASK

SK

R/W-0b

Table 10-102. MASK_MODERATE_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7

NRSTOUT_READBACK_ R/W

MASK

0b

Masking of NRSTOUT_READBACK_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

6

5

4

NINT_READBACK_MASK R/W

NPWRON_LONG_MASK R/W

0b

Masking of NINT_READBACK_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of NPWRON_LONG_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

SPMI_ERR_MASK

R/W

Masking of SPMI_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

3

2

RESERVED

R/W

0b

REG_CRC_ERR_MASK

Masking of REG_CRC_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

1

0

BIST_FAIL_MASK

RESERVED

R/W

0b

Masking of BIST_FAIL_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.80 MASK_FSM_ERR Register (Offset = 0x56) [Reset = 0x0]

MASK_FSM_ERR is shown in Figure 10-139 and described in Table 10-103.

Return to the Table 10-22.

Figure 10-139. MASK_FSM_ERR Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

SOC_PWR_ER MCU_PWR_ER ORD_SHUTDO IMM_SHUTDO

R_MASK

WN_MASK

R/W-0b

Table 10-103. MASK_FSM_ERR Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7:4

3

R/W

0b

SOC_PWR_ERR_MASK R/W

0b

Masking of SOC_PWR_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2

1

0

MCU_PWR_ERR_MASK R/W

0b

Masking of MCU_PWR_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

ORD_SHUTDOWN_MAS R/W

K

Masking of ORD_SHUTDOWN_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

IMM_SHUTDOWN_MASK R/W

Masking of IMM_SHUTDOWN_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.81 MASK_COMM_ERR Register (Offset = 0x57) [Reset = 0x0]

MASK_COMM_ERR is shown in Figure 10-140 and described in Table 10-104.

Return to the Table 10-22.

Figure 10-140. MASK_COMM_ERR Register

7

6

5

4

3

2

1

0

I2C2_ADR_ER

R_MASK

RESERVED

I2C2_CRC_ER

R_MASK

RESERVED

COMM_ADR_E

RR_MASK

RESERVED COMM_CRC_E COMM_FRM_E

RR_MASK

R/W-0b

Table 10-104. MASK_COMM_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7

I2C2_ADR_ERR_MASK

R/W

0b

Masking of I2C2_ADR_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

6

5

RESERVED

R/W

0b

I2C2_CRC_ERR_MASK

Masking of I2C2_CRC_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

4

3

RESERVED

R/W

0b

COMM_ADR_ERR_MASK R/W

Masking of COMM_ADR_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2

1

RESERVED

R/W

0b

COMM_CRC_ERR_MAS R/W

K

Masking of COMM_CRC_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

0

COMM_FRM_ERR_MAS R/W

K

0b

Masking of COMM_FRM_ERR_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.82 MASK_READBACK_ERR Register (Offset = 0x58) [Reset = 0x0]

MASK_READBACK_ERR is shown in Figure 10-141 and described in Table 10-105.

Return to the Table 10-22.

Figure 10-141. MASK_READBACK_ERR Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

NRSTOUT_SO

C_READBACK

_MASK

RESERVED

R/W-0b

EN_DRV_REA

DBACK_MASK

R/W-0b

Table 10-105. MASK_READBACK_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

R/W

0b

NRSTOUT_SOC_READB R/W

ACK_MASK

0b

Masking of NRSTOUT_SOC_READBACK_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

2:1

0

RESERVED

R/W

0b

EN_DRV_READBACK_M R/W

ASK

Masking of EN_DRV_READBACK_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.83 MASK_ESM Register (Offset = 0x59) [Reset = 0x0]

MASK_ESM is shown in Figure 10-142 and described in Table 10-106.

Return to the Table 10-22.

Figure 10-142. MASK_ESM Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

ESM_MCU_RS ESM_MCU_FAI ESM_MCU_PIN ESM_SOC_RS ESM_SOC_FAI ESM_SOC_PIN

T_MASK

L_MASK

_MASK

T_MASK

L_MASK

_MASK

R/W-0b

Table 10-106. MASK_ESM Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5

RESERVED

0b

ESM_MCU_RST_MASK

0b

Masking of ESM_MCU_RST_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

4

3

2

1

0

ESM_MCU_FAIL_MASK R/W

0b

Masking of ESM_MCU_FAIL_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

ESM_MCU_PIN_MASK

ESM_SOC_RST_MASK

ESM_SOC_FAIL_MASK

ESM_SOC_PIN_MASK

R/W

Masking of ESM_MCU_PIN_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of ESM_SOC_RST_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of ESM_SOC_FAIL_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

Masking of ESM_SOC_PIN_INT interrupt:

(Default from NVM memory)

0b = Interrupt generated

1b = Interrupt not generated.

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10.7.1.84 INT_TOP Register (Offset = 0x5A) [Reset = 0x0]

INT_TOP is shown in Figure 10-143 and described in Table 10-107.

Return to the Table 10-22.

Figure 10-143. INT_TOP Register

7

6

5

4

3

2

1

0

FSM_ERR_INT SEVERE_ERR MODERATE_E

MISC_INT

STARTUP_INT

GPIO_INT

LDO_VMON_IN

T

BUCK_INT

_INT

RR_INT

R-0b

Table 10-107. INT_TOP Register Field Descriptions

Bit

Field

Type

Reset

Description

7

6

5

FSM_ERR_INT

R

0b

Interrupt indicating that INT_FSM_ERR register has pending

interrupt. The reason for the interrupt is indicated in INT_FSM_ERR

register.

This bit is cleared automatically when INT_FSM_ERR register is

cleared to 0x00.

SEVERE_ERR_INT

MODERATE_ERR_INT

R

0b

Interrupt indicating that INT_SEVERE_ERR register has pending

interrupt. The reason for the interrupt is indicated in

INT_SEVERE_ERR register.

This bit is cleared automatically when INT_SEVERE_ERR register is

cleared to 0x00.

Interrupt indicating that INT_MODERATE_ERR register has

pending interrupt. The reason for the interrupt is indicated in

INT_MODERATE_ERR register.

This bit is cleared automatically when INT_MODERATE_ERR

register is cleared to 0x00.

4

3

MISC_INT

R

0b

Interrupt indicating that INT_MISC register has pending interrupt.

The reason for the interrupt is indicated in INT_MISC register.

This bit is cleared automatically when INT_MISC register is cleared

to 0x00.

STARTUP_INT

Interrupt indicating that INT_STARTUP register has pending

interrupt. The reason for the interrupt is indicated in INT_STARTUP

register.

This bit is cleared automatically when INT_STARTUP register is

cleared to 0x00.

2

1

GPIO_INT

R

0b

Interrupt indicating that INT_GPIO register has pending interrupt.

The reason for the interrupt is indicated in INT_GPIO register.

This bit is cleared automatically when INT_GPIO register is cleared

to 0x00.

LDO_VMON_INT

Interrupt indicating that INT_LDO_VMON register has pending

interrupt. The reason for the interrupt is indicated in

INT_LDO_VMON register.

This bit is cleared automatically when INT_LDO_VMON register is

cleared to 0x00.

0

BUCK_INT

R

0b

Interrupt indicating that INT_BUCK register has pending interrupt.

The reason for the interrupt is indicated in INT_BUCK register.

This bit is cleared automatically when INT_BUCK register is cleared

to 0x00.

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10.7.1.85 INT_BUCK Register (Offset = 0x5B) [Reset = 0x0]

INT_BUCK is shown in Figure 10-144 and described in Table 10-108.

Return to the Table 10-22.

Figure 10-144. INT_BUCK Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

BUCK5_INT

R-0b

BUCK3_4_INT BUCK1_2_INT

R-0b R-0b

Table 10-108. INT_BUCK Register Field Descriptions

Bit

Field

Type

Reset

Description

7:3

2

RESERVED

BUCK5_INT

R

0b

R

0b

Interrupt indicating that INT_BUCK5 register has pending interrupt.

The reason for the interrupt is indicated in INT_BUCK5 register.

This bit is cleared automatically when INT_BUCK5 register is cleared

to 0x00.

1

0

BUCK3_4_INT

BUCK1_2_INT

R

0b

Interrupt indicating that INT_BUCK3_4 register has pending

interrupt.

This bit is cleared automatically when INT_BUCK3_4 register is

cleared to 0x00.

Interrupt indicating that INT_BUCK1_2 register has pending

interrupt.

This bit is cleared automatically when INT_BUCK1_2 register is

cleared to 0x00.

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10.7.1.86 INT_BUCK1_2 Register (Offset = 0x5C) [Reset = 0x0]

INT_BUCK1_2 is shown in Figure 10-145 and described in Table 10-109.

Return to the Table 10-22.

Figure 10-145. INT_BUCK1_2 Register

7

6

5

4

3

2

1

0

BUCK2_ILIM_I BUCK2_SC_IN BUCK2_UV_IN BUCK2_OV_IN BUCK1_ILIM_I BUCK1_SC_IN BUCK1_UV_IN BUCK1_OV_IN

NT

T

NT

T

R/W1C-0b

Table 10-109. INT_BUCK1_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK2_ILIM_INT

R/W1C

0b

Latched status bit indicating that BUCK2 output current limit has

been triggered.

Write 1 to clear.

6

BUCK2_SC_INT

R/W1C

0b

Latched status bit indicating that the BUCK2 (or other regulators)

output voltage has fallen below the 150 mV level during operation, or

BUCK2 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

5

4

3

2

BUCK2_UV_INT

BUCK2_OV_INT

BUCK1_ILIM_INT

BUCK1_SC_INT

R/W1C

0b

Latched status bit indicating that BUCK2 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that BUCK2 output over-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that BUCK1 output current limit has

been triggered.

Write 1 to clear.

Latched status bit indicating that the BUCK1 (or other regulators)

output voltage has fallen below the 150 mV level during operation, or

BUCK1 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

1

0

BUCK1_UV_INT

BUCK1_OV_INT

R/W1C

0b

Latched status bit indicating that BUCK1 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that BUCK1 output over-voltage has

been detected.

Write 1 to clear.

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10.7.1.87 INT_BUCK3_4 Register (Offset = 0x5D) [Reset = 0x0]

INT_BUCK3_4 is shown in Figure 10-146 and described in Table 10-110.

Return to the Table 10-22.

Figure 10-146. INT_BUCK3_4 Register

7

6

5

4

3

2

1

0

BUCK4_ILIM_I BUCK4_SC_IN BUCK4_UV_IN BUCK4_OV_IN BUCK3_ILIM_I BUCK3_SC_IN BUCK3_UV_IN BUCK3_OV_IN

NT

T

NT

T

R/W1C-0b

Table 10-110. INT_BUCK3_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK4_ILIM_INT

R/W1C

0b

Latched status bit indicating that BUCK4 output current limit has

been triggered.

Write 1 to clear.

6

BUCK4_SC_INT

R/W1C

0b

Latched status bit indicating that the BUCK4 (or other regulators)

output voltage has fallen below the 150 mV level during operation, or

BUCK4 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

5

4

3

2

BUCK4_UV_INT

BUCK4_OV_INT

BUCK3_ILIM_INT

BUCK3_SC_INT

R/W1C

0b

Latched status bit indicating that BUCK4 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that BUCK4 output over-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that BUCK3 output current limit has

been triggered.

Write 1 to clear.

Latched status bit indicating that the BUCK3 (or other regulators)

output voltage has fallen below the 150 mV level during operation, or

BUCK3 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

1

0

BUCK3_UV_INT

BUCK3_OV_INT

R/W1C

0b

Latched status bit indicating that BUCK3 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that BUCK3 output over-voltage has

been detected.

Write 1 to clear.

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10.7.1.88 INT_BUCK5 Register (Offset = 0x5E) [Reset = 0x0]

INT_BUCK5 is shown in Figure 10-147 and described in Table 10-111.

Return to the Table 10-22.

Figure 10-147. INT_BUCK5 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK5_ILIM_I BUCK5_SC_IN BUCK5_UV_IN BUCK5_OV_IN

NT

T

R/W1C-0b

Table 10-111. INT_BUCK5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

R/W

0b

BUCK5_ILIM_INT

R/W1C

0b

Latched status bit indicating that BUCK5 output current limit has

been triggered.

Write 1 to clear.

2

BUCK5_SC_INT

R/W1C

0b

Latched status bit indicating that the BUCK5 (or other regulators)

output voltage has fallen below the 150 mV level during operation, or

BUCK5 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

1

0

BUCK5_UV_INT

BUCK5_OV_INT

R/W1C

0b

Latched status bit indicating that BUCK5 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that BUCK5 output over-voltage has

been detected.

Write 1 to clear.

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10.7.1.89 INT_LDO_VMON Register (Offset = 0x5F) [Reset = 0x0]

INT_LDO_VMON is shown in Figure 10-148 and described in Table 10-112.

Return to the Table 10-22.

Figure 10-148. INT_LDO_VMON Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

VCCA_INT

R-0b

RESERVED

R-0b

LDO3_4_INT

R-0b

LDO1_2_INT

R-0b

Table 10-112. INT_LDO_VMON Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

4

RESERVED

VCCA_INT

R

0b

R

0b

Interrupt indicating that INT_VMON register has pending interrupt.

The reason for the interrupt is indicated in INT_VMON register.

This bit is cleared automatically when INT_VMON register is cleared

to 0x00.

3:2

1

RESERVED

LDO3_4_INT

R

0b

Interrupt indicating that INT_LDO3_4 register has pending interrupt.

This bit is cleared automatically when INT_LDO3_4 register is

cleared to 0x00.

0

LDO1_2_INT

R

0b

Interrupt indicating that INT_LDO1_2 register has pending interrupt.

This bit is cleared automatically when INT_LDO1_2 register is

cleared to 0x00.

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10.7.1.90 INT_LDO1_2 Register (Offset = 0x60) [Reset = 0x0]

INT_LDO1_2 is shown in Figure 10-149 and described in Table 10-113.

Return to the Table 10-22.

Figure 10-149. INT_LDO1_2 Register

7

6

5

4

3

2

1

0

LDO2_ILIM_IN LDO2_SC_INT LDO2_UV_INT LDO2_OV_INT LDO1_ILIM_IN LDO1_SC_INT LDO1_UV_INT LDO1_OV_INT

T

R/W1C-0b

Table 10-113. INT_LDO1_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO2_ILIM_INT

R/W1C

0b

Latched status bit indicating that LDO2 output current limit has been

triggered.

Write 1 to clear.

6

LDO2_SC_INT

R/W1C

0b

Latched status bit indicating that the LDO2 (or other regulators)

output voltage has fallen below the 150 mV level during operation,

or LDO2 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

5

4

3

2

LDO2_UV_INT

LDO2_OV_INT

LDO1_ILIM_INT

LDO1_SC_INT

R/W1C

0b

Latched status bit indicating that LDO2 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that LDO2 output over-voltage has been

detected.

Write 1 to clear.

Latched status bit indicating that LDO1 output current limit has been

triggered.

Write 1 to clear.

Latched status bit indicating that the LDO1 (or other regulators)

output voltage has fallen below the 150 mV level during operation,

or LDO1 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

1

0

LDO1_UV_INT

LDO1_OV_INT

R/W1C

0b

Latched status bit indicating that LDO1 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that LDO1 output over-voltage has been

detected.

Write 1 to clear.

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10.7.1.91 INT_LDO3_4 Register (Offset = 0x61) [Reset = 0x0]

INT_LDO3_4 is shown in Figure 10-150 and described in Table 10-114.

Return to the Table 10-22.

Figure 10-150. INT_LDO3_4 Register

7

6

5

4

3

2

1

0

LDO4_ILIM_IN LDO4_SC_INT LDO4_UV_INT LDO4_OV_INT LDO3_ILIM_IN LDO3_SC_INT LDO3_UV_INT LDO3_OV_INT

T

R/W1C-0b

Table 10-114. INT_LDO3_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO4_ILIM_INT

R/W1C

0b

Latched status bit indicating that LDO4 output current limit has been

triggered.

Write 1 to clear.

6

LDO4_SC_INT

R/W1C

0b

Latched status bit indicating that the LDO4 (or other regulators)

output voltage has fallen below the 150 mV level during operation,

or LDO4 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

5

4

3

2

LDO4_UV_INT

LDO4_OV_INT

LDO3_ILIM_INT

LDO3_SC_INT

R/W1C

0b

Latched status bit indicating that LDO4 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that LDO4 output over-voltage has been

detected.

Write 1 to clear.

Latched status bit indicating that LDO3 output current limit has been

triggered.

Write 1 to clear.

Latched status bit indicating that the LDO3 (or other regulators)

output voltage has fallen below the 150 mV level during operation,

or LDO3 (or other regulators) output is higher than the 150 mV level

immediately after enable.

Write 1 to clear.

1

0

LDO3_UV_INT

LDO3_OV_INT

R/W1C

0b

Latched status bit indicating that LDO3 output under-voltage has

been detected.

Write 1 to clear.

Latched status bit indicating that LDO3 output over-voltage has been

detected.

Write 1 to clear.

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10.7.1.92 INT_VMON Register (Offset = 0x62) [Reset = 0x0]

INT_VMON is shown in Figure 10-151 and described in Table 10-115.

Return to the Table 10-22.

Figure 10-151. INT_VMON Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

VCCA_UV_INT VCCA_OV_INT

R/W1C-0b R/W1C-0b

Table 10-115. INT_VMON Register Field Descriptions

Bit

Field

Type

Reset

Description

7:2

1

RESERVED

R/W

0b

VCCA_UV_INT

R/W1C

0b

Latched status bit indicating that the VCCA input voltage has

decreased below the under-voltage monitoring level. The actual

status of the VCCA under-voltage monitoring is indicated by

VCCA_UV_STAT bit.

Write 1 to clear interrupt.

0

VCCA_OV_INT

R/W1C

0b

Latched status bit indicating that the VCCA input voltage has

exceeded the over-voltage detection level. The actual status of the

over-voltage is indicated by VCCA_OV_STAT bit.

Write 1 to clear interrupt.

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10.7.1.93 INT_GPIO Register (Offset = 0x63) [Reset = 0x0]

INT_GPIO is shown in Figure 10-152 and described in Table 10-116.

Return to the Table 10-22.

Figure 10-152. INT_GPIO Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

GPIO1_8_INT

R-0b

GPIO11_INT

R/W1C-0b

GPIO10_INT

R/W1C-0b

GPIO9_INT

R/W1C-0b

Table 10-116. INT_GPIO Register Field Descriptions

Bit

Field

Type

R/W

R

Reset

Description

7:4

3

RESERVED

0b

GPIO1_8_INT

0b

Interrupt indicating that INT_GPIO1_8 has pending interrupt. The

reason for the interrupt is indicated in INT_GPIO1_8 register.

This bit is cleared automatically when INT_GPIO1_8 register is

cleared to 0x00.

2

1

0

GPIO11_INT

GPIO10_INT

GPIO9_INT

R/W1C

0b

Latched status bit indicating that GPIO11 has pending interrupt.

GPIO11_IN bit in GPIO_IN_2 register shows the status of the

GPIO11 signal.

Write 1 to clear interrupt.

Latched status bit indicating that GPIO10 has pending interrupt.

GPIO10_IN bit in GPIO_IN_2 register shows the status of the

GPIO10 signal.

Write 1 to clear interrupt.

Latched status bit indicating that GPIO9 has pending interrupt.

GPIO9_IN bit in GPIO_IN_2 register shows the status of the GPIO9

signal.

Write 1 to clear interrupt.

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10.7.1.94 INT_GPIO1_8 Register (Offset = 0x64) [Reset = 0x0]

INT_GPIO1_8 is shown in Figure 10-153 and described in Table 10-117.

Return to the Table 10-22.

Figure 10-153. INT_GPIO1_8 Register

7

6

5

4

3

2

1

0

GPIO8_INT

R/W1C-0b

GPIO7_INT

R/W1C-0b

GPIO6_INT

R/W1C-0b

GPIO5_INT

R/W1C-0b

GPIO4_INT

R/W1C-0b

GPIO3_INT

R/W1C-0b

GPIO2_INT

R/W1C-0b

GPIO1_INT

R/W1C-0b

Table 10-117. INT_GPIO1_8 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

GPIO8_INT

GPIO7_INT

GPIO6_INT

GPIO5_INT

GPIO4_INT

GPIO3_INT

GPIO2_INT

GPIO1_INT

R/W1C

0b

Latched status bit indicating that GPIO8 has has pending interrupt.

GPIO8_IN bit in GPIO_IN_1 register shows the status of the GPIO8

signal.

Write 1 to clear interrupt.

6

5

4

3

2

1

0

R/W1C

0b

Latched status bit indicating that GPIO7 has has pending interrupt.

GPIO7_IN bit in GPIO_IN_1 register shows the status of the GPIO7

signal.

Write 1 to clear interrupt.

Latched status bit indicating that GPIO6 has has pending interrupt.

GPIO6_IN bit in GPIO_IN_1 register shows the status of the GPIO6

signal.

Write 1 to clear interrupt.

Latched status bit indicating that GPIO5 has has pending interrupt.

GPIO5_IN bit in GPIO_IN_1 register shows the status of the GPIO5

signal.

Write 1 to clear interrupt.

Latched status bit indicating that GPIO4 has has pending interrupt.

GPIO4_IN bit in GPIO_IN_1 register shows the status of the GPIO4

signal.

Write 1 to clear interrupt.

Latched status bit indicating that GPIO3 has has pending interrupt.

GPIO3_IN bit in GPIO_IN_1 register shows the status of the GPIO3

signal.

Write 1 to clear interrupt.

Latched status bit indicating that GPIO2 has pending interrupt.

GPIO2_IN bit in GPIO_IN_1 register shows the status of the GPIO2

signal.

Write 1 to clear interrupt.

Latched status bit indicating that GPIO1 has pending interrupt.

GPIO1_IN bit in GPIO_IN_1 register shows the status of the GPIO1

signal.

Write 1 to clear interrupt.

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10.7.1.95 INT_STARTUP Register (Offset = 0x65) [Reset = 0x0]

INT_STARTUP is shown in Figure 10-154 and described in Table 10-118.

Return to the Table 10-22.

Figure 10-154. INT_STARTUP Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

SOFT_REBOO

T_INT

FSD_INT

RESERVED

RTC_INT

ENABLE_INT NPWRON_STA

RT_INT

R/W1C-0b

R/W-0b

R-0b

R/W1C-0b

Table 10-118. INT_STARTUP Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5

RESERVED

R/W

0b

SOFT_REBOOT_INT

R/W1C

0b

Latched status bit indicating that soft reboot event has been

detected.

Write 1 to clear.

4

FSD_INT

R/W1C

0b

Latched status bit indicating that PMIC has started from

NO_SUPPLY or BACKUP state (first supply dectection).

Write 1 to clear.

3

2

RESERVED

RTC_INT

R/W

R

0b

Latched status bit indicating that RTC_STATUS register has pending

interrupt.

This bit is cleared automatically when ALARM and TIMER interrupts

are cleared.

1

0

ENABLE_INT

R/W1C

0b

Latched status bit indicating that ENABLE pin active event has been

detected.

Write 1 to clear.

NPWRON_START_INT

Latched status bit indicating that NPWRON startup event has been

detected.

Write 1 to clear.

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10.7.1.96 INT_MISC Register (Offset = 0x66) [Reset = 0x0]

INT_MISC is shown in Figure 10-155 and described in Table 10-119.

Return to the Table 10-22.

Figure 10-155. INT_MISC Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

TWARN_INT

RESERVED

EXT_CLK_INT BIST_PASS_IN

T

R/W1C-0b

R/W-0b

R/W1C-0b

Table 10-119. INT_MISC Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

TWARN_INT

R/W

0b

R/W1C

0b

Latched status bit indicating that the die junction temperature has

exceeded the thermal warning level. The actual status of the thermal

warning is indicated by TWARN_STAT bit in STAT_MISC register.

Write 1 to clear interrupt.

2

1

RESERVED

R/W

0b

EXT_CLK_INT

R/W1C

Latched status bit indicating that external clock is not valid.

Internal clock is automatically taken into use.

Write 1 to clear.

0

BIST_PASS_INT

R/W1C

0b

Latched status bit indicating that BIST has been completed.

Write 1 to clear interrupt.

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10.7.1.97 INT_MODERATE_ERR Register (Offset = 0x67) [Reset = 0x0]

INT_MODERATE_ERR is shown in Figure 10-156 and described in Table 10-120.

Return to the Table 10-22.

Figure 10-156. INT_MODERATE_ERR Register

7

6

5

4

3

2

1

0

NRSTOUT_RE NINT_READBA NPWRON_LON SPMI_ERR_IN RECOV_CNT_I REG_CRC_ER BIST_FAIL_INT TSD_ORD_INT

ADBACK_INT

CK_INT

G_INT

T

NT

R_INT

R/W1C-0b

Table 10-120. INT_MODERATE_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7

NRSTOUT_READBACK_I R/W1C

NT

0b

Latched status bit indicating that NRSTOUT readback error has been

detected.

Write 1 to clear interrupt.

6

5

4

3

2

1

0

NINT_READBACK_INT

NPWRON_LONG_INT

SPMI_ERR_INT

R/W1C

0b

Latched status bit indicating that NINT readback error has been

detected.

Write 1 to clear interrupt.

Latched status bit indicating that NPWRON long press has been

detected.

Write 1 to clear.

Latched status bit indicating that the SPMI communication interface

has detected an error.

Write 1 to clear interrupt.

RECOV_CNT_INT

REG_CRC_ERR_INT

BIST_FAIL_INT

Latched status bit indicating that RECOV_CNT has reached the limit

(RECOV_CNT_THR).

Write 1 to clear.

Latched status bit indicating that the register CRC checking has

detected an error.

Write 1 to clear interrupt.

Latched status bit indicating that the LBIST or ABIST has detected

an error.

Write 1 to clear interrupt.

TSD_ORD_INT

Latched status bit indicating that the die junction temperature has

exceeded the thermal level causing a sequenced shutdown. The

regulators have been disabled. The regulators cannot be enabled if

this bit is active. The actual status of the temperature is indicated by

TSD_ORD_STAT bit in STAT_MODERATE_ERR register.

Write 1 to clear interrupt.

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10.7.1.98 INT_SEVERE_ERR Register (Offset = 0x68) [Reset = 0x0]

INT_SEVERE_ERR is shown in Figure 10-157 and described in Table 10-121.

Return to the Table 10-22.

Figure 10-157. INT_SEVERE_ERR Register

7

6

5

4

3

2

1

0

RESERVED

PFSM_ERR_IN VCCA_OVP_IN TSD_IMM_INT

T

R/W-0b

R/W1C-0b

Table 10-121. INT_SEVERE_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7:3

2

RESERVED

R/W

0b

PFSM_ERR_INT

R/W1C

0b

Latched status bit indicating that the PFSM sequencer has detected

an error.

Write 1 to clear interrupt.

1

0

VCCA_OVP_INT

TSD_IMM_INT

R/W1C

0b

Latched status bit indicating that the VCCA input voltage has

exceeded the over-voltage threshold level causing an immediate

shutdown. The regulators have been disabled.

Write 1 to clear interrupt.

Latched status bit indicating that the die junction temperature has

exceeded the thermal level causing an immediate shutdown. The

regulators have been disabled. The regulators cannot be enabled if

this bit is active. The actual status of the temperature is indicated by

TSD_IMM_STAT bit in THER_CLK_STATUS register.

Write 1 to clear interrupt.

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10.7.1.99 INT_FSM_ERR Register (Offset = 0x69) [Reset = 0x0]

INT_FSM_ERR is shown in Figure 10-158 and described in Table 10-122.

Return to the Table 10-22.

Figure 10-158. INT_FSM_ERR Register

7

6

5

4

3

2

1

0

WD_INT

ESM_INT

READBACK_E COMM_ERR_I SOC_PWR_ER MCU_PWR_ER ORD_SHUTDO IMM_SHUTDO

RR_INT

NT

R_INT

WN_INT

R-0b

R/W1C-0b

Table 10-122. INT_FSM_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7

WD_INT

R

0b

Interrupt indicating that WD_ERR_STATUS register has pending

interrupt.

This bit is cleared automatically when WD_RST_INT, WD_FAIL_INT

and WD_LONGWIN_TIMEOUT_INT are cleared.

6

5

ESM_INT

R

0b

Interrupt indicating that INT_ESM has pending interrupt.

This bit is cleared automatically when INT_ESM register is cleared to

0x00.

READBACK_ERR_INT

Interrupt indicating that INT_READBACK_ERR has pending

interrupt.

This bit is cleared automatically when INT_READBACK_ERR

register is cleared to 0x00.

4

COMM_ERR_INT

R

0b

Interrupt indicating that INT_COMM_ERR has pending interrupt. The

reason for the interrupt is indicated in INT_COMM_ERR register.

This bit is cleared automatically when INT_COMM_ERR register is

cleared to 0x00.

3

2

1

0

SOC_PWR_ERR_INT

MCU_PWR_ERR_INT

ORD_SHUTDOWN_INT

IMM_SHUTDOWN_INT

R/W1C

0b

Latched status bit indicating that SOC power error has been

detected.

Write 1 to clear.

Latched status bit indicating that MCU power error has been

detected.

Write 1 to clear.

Latched status bit indicating that orderly shutdown has been

detected.

Write 1 to clear.

Latched status bit indicating that immediate shutdown has been

detected.

Write 1 to clear.

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10.7.1.100 INT_COMM_ERR Register (Offset = 0x6A) [Reset = 0x0]

INT_COMM_ERR is shown in Figure 10-159 and described in Table 10-123.

Return to the Table 10-22.

Figure 10-159. INT_COMM_ERR Register

7

6

5

4

3

2

1

0

I2C2_ADR_ER

R_INT

RESERVED

I2C2_CRC_ER

R_INT

RESERVED

COMM_ADR_E

RR_INT

RESERVED COMM_CRC_E COMM_FRM_E

RR_INT

R/W1C-0b

R/W-0b

R/W1C-0b

R/W-0b

R/W1C-0b

R/W-0b

R/W1C-0b

Table 10-123. INT_COMM_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7

I2C2_ADR_ERR_INT

R/W1C

0b

Latched status bit indicating that I2C2 write to non-existing, protected

or read-only register address has been detected.

Write 1 to clear interrupt.

6

5

RESERVED

R/W

0b

I2C2_CRC_ERR_INT

R/W1C

Latched status bit indicating that I2C2 CRC error has been detected.

Write 1 to clear interrupt.

4

3

RESERVED

R/W

0b

COMM_ADR_ERR_INT

R/W1C

Latched status bit indicating that I2C1/SPI write to non-existing,

protected or read-only register address has been detected.

Write 1 to clear interrupt.

2

1

RESERVED

R/W

0b

COMM_CRC_ERR_INT

R/W1C

Latched status bit indicating that I2C1/SPI CRC error has been

detected.

Write 1 to clear interrupt.

0

COMM_FRM_ERR_INT

R/W1C

0b

Latched status bit indicating that SPI frame error has been detected.

Write 1 to clear interrupt.

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10.7.1.101 INT_READBACK_ERR Register (Offset = 0x6B) [Reset = 0x0]

INT_READBACK_ERR is shown in Figure 10-160 and described in Table 10-124.

Return to the Table 10-22.

Figure 10-160. INT_READBACK_ERR Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

NRSTOUT_SO

C_READBACK

_INT

RESERVED

R/W-0b

EN_DRV_REA

DBACK_INT

R/W1C-0b

Table 10-124. INT_READBACK_ERR Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7:4

3

R/W

0b

NRSTOUT_SOC_READB R/W1C

ACK_INT

0b

Latched status bit indicating that NRSTOUT_SOC readback error

has been detected.

Write 1 to clear interrupt.

2:1

0

RESERVED

R/W

0b

EN_DRV_READBACK_IN R/W1C

T

Latched status bit indicating that EN_DRV readback error has been

detected.

Write 1 to clear interrupt.

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10.7.1.102 INT_ESM Register (Offset = 0x6C) [Reset = 0x0]

INT_ESM is shown in Figure 10-161 and described in Table 10-125.

Return to the Table 10-22.

Figure 10-161. INT_ESM Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

ESM_MCU_RS ESM_MCU_FAI ESM_MCU_PIN ESM_SOC_RS ESM_SOC_FAI ESM_SOC_PIN

T_INT

L_INT

_INT

T_INT

L_INT

_INT

R/W1C-0b

Table 10-125. INT_ESM Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5

RESERVED

R/W

0b

ESM_MCU_RST_INT

R/W1C

0b

Latched status bit indicating that MCU ESM reset has been detected.

Write 1 to clear interrupt.

4

3

2

1

0

ESM_MCU_FAIL_INT

ESM_MCU_PIN_INT

ESM_SOC_RST_INT

ESM_SOC_FAIL_INT

ESM_SOC_PIN_INT

R/W1C

0b

Latched status bit indicating that MCU ESM fail has been detected.

Write 1 to clear interrupt.

Latched status bit indicating that MCU ESM fault has been detected.

Write 1 to clear interrupt.

Latched status bit indicating that SOC ESM reset has been detected.

Write 1 to clear interrupt.

Latched status bit indicating that SOC ESM fail has been detected.

Write 1 to clear interrupt.

Latched status bit indicating that SOC ESM fault has been detected.

Write 1 to clear interrupt.

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10.7.1.103 STAT_BUCK1_2 Register (Offset = 0x6D) [Reset = 0x0]

STAT_BUCK1_2 is shown in Figure 10-162 and described in Table 10-126.

Return to the Table 10-22.

Figure 10-162. STAT_BUCK1_2 Register

7

6

5

4

3

2

1

0

BUCK2_ILIM_S

TAT

RESERVED BUCK2_UV_ST BUCK2_OV_ST BUCK1_ILIM_S

RESERVED BUCK1_UV_ST BUCK1_OV_ST

AT

TAT

AT

R-0b

Table 10-126. STAT_BUCK1_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK2_ILIM_STAT

R

0b

Status bit indicating that BUCK2 output current is above current limit

level.

6

5

RESERVED

R

0b

BUCK2_UV_STAT

Status bit indicating that BUCK2 output voltage is below under-

voltage threshold.

4

3

BUCK2_OV_STAT

BUCK1_ILIM_STAT

R

0b

Status bit indicating that BUCK2 output voltage is above over-voltage

threshold.

Status bit indicating that BUCK1 output current is above current limit

level.

2

1

RESERVED

R

0b

BUCK1_UV_STAT

Status bit indicating that BUCK1 output voltage is below under-

voltage threshold.

0

BUCK1_OV_STAT

R

0b

Status bit indicating that BUCK1 output voltage is above over-voltage

threshold.

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10.7.1.104 STAT_BUCK3_4 Register (Offset = 0x6E) [Reset = 0x0]

STAT_BUCK3_4 is shown in Figure 10-163 and described in Table 10-127.

Return to the Table 10-22.

Figure 10-163. STAT_BUCK3_4 Register

7

6

5

4

3

2

1

0

BUCK4_ILIM_S

TAT

RESERVED BUCK4_UV_ST BUCK4_OV_ST BUCK3_ILIM_S

RESERVED BUCK3_UV_ST BUCK3_OV_ST

AT

TAT

AT

R-0b

Table 10-127. STAT_BUCK3_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BUCK4_ILIM_STAT

R

0b

Status bit indicating that BUCK4 output current is above current limit

level.

6

5

RESERVED

R

0b

BUCK4_UV_STAT

Status bit indicating that BUCK4 output voltage is below under-

voltage threshold.

4

3

BUCK4_OV_STAT

BUCK3_ILIM_STAT

R

0b

Status bit indicating that BUCK4 output voltage is above over-voltage

threshold.

Status bit indicating that BUCK3 output current is above current limit

level.

2

1

RESERVED

R

0b

BUCK3_UV_STAT

Status bit indicating that BUCK3 output voltage is below under-

voltage threshold.

0

BUCK3_OV_STAT

R

0b

Status bit indicating that BUCK3 output voltage is above over-voltage

threshold.

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10.7.1.105 STAT_BUCK5 Register (Offset = 0x6F) [Reset = 0x0]

STAT_BUCK5 is shown in Figure 10-164 and described in Table 10-128.

Return to the Table 10-22.

Figure 10-164. STAT_BUCK5 Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

BUCK5_ILIM_S

TAT

RESERVED BUCK5_UV_ST BUCK5_OV_ST

AT

R-0b

Table 10-128. STAT_BUCK5 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

R

0b

BUCK5_ILIM_STAT

R

0b

Status bit indicating that BUCK5 output current is above current limit

level.

2

1

RESERVED

R

0b

BUCK5_UV_STAT

Status bit indicating that BUCK5 output voltage is below under-

voltage threshold.

0

BUCK5_OV_STAT

R

0b

Status bit indicating that BUCK5 output voltage is above over-voltage

threshold.

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10.7.1.106 STAT_LDO1_2 Register (Offset = 0x70) [Reset = 0x0]

STAT_LDO1_2 is shown in Figure 10-165 and described in Table 10-129.

Return to the Table 10-22.

Figure 10-165. STAT_LDO1_2 Register

7

6

5

4

3

2

1

0

LDO2_ILIM_ST

AT

RESERVED

LDO2_UV_STA LDO2_OV_STA LDO1_ILIM_ST

RESERVED

LDO1_UV_STA LDO1_OV_STA

T

AT

T

R-0b

Table 10-129. STAT_LDO1_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO2_ILIM_STAT

R

0b

Status bit indicating that LDO2 output current is above current limit

level.

6

5

RESERVED

R

0b

LDO2_UV_STAT

Status bit indicating that LDO2 output voltage is below under-voltage

threshold.

4

3

LDO2_OV_STAT

LDO1_ILIM_STAT

R

0b

Status bit indicating that LDO2 output voltage is above over-voltage

threshold.

Status bit indicating that LDO1 output current is above current limit

level.

2

1

RESERVED

R

0b

LDO1_UV_STAT

Status bit indicating that LDO1 output voltage is below under-voltage

threshold.

0

LDO1_OV_STAT

R

0b

Status bit indicating that LDO1 output voltage is above over-voltage

threshold.

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10.7.1.107 STAT_LDO3_4 Register (Offset = 0x71) [Reset = 0x0]

STAT_LDO3_4 is shown in Figure 10-166 and described in Table 10-130.

Return to the Table 10-22.

Figure 10-166. STAT_LDO3_4 Register

7

6

5

4

3

2

1

0

LDO4_ILIM_ST

AT

RESERVED

LDO4_UV_STA LDO4_OV_STA LDO3_ILIM_ST

RESERVED

LDO3_UV_STA LDO3_OV_STA

T

AT

T

R-0b

Table 10-130. STAT_LDO3_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

LDO4_ILIM_STAT

R

0b

Status bit indicating that LDO4 output current is above current limit

level.

6

5

RESERVED

R

0b

LDO4_UV_STAT

Status bit indicating that LDO4 output voltage is below under-voltage

threshold.

4

3

LDO4_OV_STAT

LDO3_ILIM_STAT

R

0b

Status bit indicating that LDO4 output voltage is above over-voltage

threshold.

Status bit indicating that LDO3 output current is above current limit

level.

2

1

RESERVED

R

0b

LDO3_UV_STAT

Status bit indicating that LDO3 output voltage is below under-voltage

threshold.

0

LDO3_OV_STAT

R

0b

Status bit indicating that LDO3 output voltage is above over-voltage

threshold.

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10.7.1.108 STAT_VMON Register (Offset = 0x72) [Reset = 0x0]

STAT_VMON is shown in Figure 10-167 and described in Table 10-131.

Return to the Table 10-22.

Figure 10-167. STAT_VMON Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

VCCA_UV_STA VCCA_OV_STA

T

R-0b

Table 10-131. STAT_VMON Register Field Descriptions

Bit

Field

Type

Reset

Description

7:2

1

RESERVED

R

0b

VCCA_UV_STAT

R

0b

Status bit indicating that VCCA input voltage is below under-voltage

level.

0

VCCA_OV_STAT

R

0b

Status bit indicating that VCCA input voltage is above over-voltage

level.

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10.7.1.109 STAT_STARTUP Register (Offset = 0x73) [Reset = 0x0]

STAT_STARTUP is shown in Figure 10-168 and described in Table 10-132.

Return to the Table 10-22.

Figure 10-168. STAT_STARTUP Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

ENABLE_STAT

R-0b

RESERVED

R-0b

Table 10-132. STAT_STARTUP Register Field Descriptions

Bit

Field

Type

Reset

Description

7:2

1

RESERVED

ENABLE_STAT

RESERVED

R

0b

R

0b

Status bit indicating nPWRON / EN pin status

0

R

0b

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10.7.1.110 STAT_MISC Register (Offset = 0x74) [Reset = 0x0]

STAT_MISC is shown in Figure 10-169 and described in Table 10-133.

Return to the Table 10-22.

Figure 10-169. STAT_MISC Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

TWARN_STAT

RESERVED

EXT_CLK_STA

T

RESERVED

R-0b

Table 10-133. STAT_MISC Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

R

0b

TWARN_STAT

R

0b

Status bit indicating that die junction temperature is above the

thermal warning level.

2

1

0

RESERVED

R

0b

EXT_CLK_STAT

RESERVED

Status bit indicating that external clock is not valid.

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10.7.1.111 STAT_MODERATE_ERR Register (Offset = 0x75) [Reset = 0x0]

STAT_MODERATE_ERR is shown in Figure 10-170 and described in Table 10-134.

Return to the Table 10-22.

Figure 10-170. STAT_MODERATE_ERR Register

7

6

5

4

3

2

1

0

RESERVED

TSD_ORD_STA

T

R-0b

Table 10-134. STAT_MODERATE_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7:1

0

RESERVED

TSD_ORD_STAT

R

0b

R

0b

Status bit indicating that the die junction temperature is above the

thermal level causing a sequenced shutdown.

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10.7.1.112 STAT_SEVERE_ERR Register (Offset = 0x76) [Reset = 0x0]

STAT_SEVERE_ERR is shown in Figure 10-171 and described in Table 10-135.

Return to the Table 10-22.

Figure 10-171. STAT_SEVERE_ERR Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

VCCA_OVP_S TSD_IMM_STA

TAT

T

R-0b

Table 10-135. STAT_SEVERE_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7:2

1

RESERVED

R

0b

VCCA_OVP_STAT

R

0b

Status bit indicating that the VCCA voltage is above overvoltage

protection level.

0

TSD_IMM_STAT

R

0b

Status bit indicating that the die junction temperature is above the

thermal level causing an immediate shutdown.

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10.7.1.113 STAT_READBACK_ERR Register (Offset = 0x77) [Reset = 0x0]

STAT_READBACK_ERR is shown in Figure 10-172 and described in Table 10-136.

Return to the Table 10-22.

Figure 10-172. STAT_READBACK_ERR Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

NRSTOUT_SO NRSTOUT_RE NINT_READBA EN_DRV_REA

C_READBACK ADBACK_STAT

_STAT

CK_STAT

DBACK_STAT

R-0b

Table 10-136. STAT_READBACK_ERR Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3

RESERVED

R

0b

NRSTOUT_SOC_READB

ACK_STAT

R

0b

Status bit indicating that NRSTOUT_SOC pin output is high and

device is driving it low.

2

1

0

NRSTOUT_READBACK_

STAT

R

0b

Status bit indicating that NRSTOUT pin output is high and device is

driving it low.

NINT_READBACK_STAT

Status bit indicating that NINT pin output is high and device is driving

it low.

EN_DRV_READBACK_S

TAT

Status bit indicating that EN_DRV pin output is different than driven.

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10.7.1.114 PGOOD_SEL_1 Register (Offset = 0x78) [Reset = 0x0]

PGOOD_SEL_1 is shown in Figure 10-173 and described in Table 10-137.

Return to the Table 10-22.

Figure 10-173. PGOOD_SEL_1 Register

7

6

5

4

3

2

1

0

PGOOD_SEL_BUCK4

R/W-0b

PGOOD_SEL_BUCK3

R/W-0b

PGOOD_SEL_BUCK2

R/W-0b

PGOOD_SEL_BUCK1

R/W-0b

Table 10-137. PGOOD_SEL_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

PGOOD_SEL_BUCK4

R/W

0b

PGOOD signal source control from BUCK4

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

5:4

3:2

1:0

PGOOD_SEL_BUCK3

PGOOD_SEL_BUCK2

PGOOD_SEL_BUCK1

R/W

0b

PGOOD signal source control from BUCK3

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

PGOOD signal source control from BUCK2

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

PGOOD signal source control from BUCK1

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

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10.7.1.115 PGOOD_SEL_2 Register (Offset = 0x79) [Reset = 0x0]

PGOOD_SEL_2 is shown in Figure 10-174 and described in Table 10-138.

Return to the Table 10-22.

Figure 10-174. PGOOD_SEL_2 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

PGOOD_SEL_BUCK5

R/W-0b

Table 10-138. PGOOD_SEL_2 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1:0

RESERVED

0b

PGOOD_SEL_BUCK5

0b

PGOOD signal source control from BUCK5

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

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10.7.1.116 PGOOD_SEL_3 Register (Offset = 0x7A) [Reset = 0x0]

PGOOD_SEL_3 is shown in Figure 10-175 and described in Table 10-139.

Return to the Table 10-22.

Figure 10-175. PGOOD_SEL_3 Register

7

6

5

4

3

2

1

0

PGOOD_SEL_LDO4

R/W-0b

PGOOD_SEL_LDO3

R/W-0b

PGOOD_SEL_LDO2

R/W-0b

PGOOD_SEL_LDO1

R/W-0b

Table 10-139. PGOOD_SEL_3 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5:4

3:2

1:0

PGOOD_SEL_LDO4

R/W

0b

PGOOD signal source control from LDO4

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

PGOOD_SEL_LDO3

PGOOD_SEL_LDO2

PGOOD_SEL_LDO1

R/W

0b

PGOOD signal source control from LDO3

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

PGOOD signal source control from LDO2

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

PGOOD signal source control from LDO1

(Default from NVM memory)

0b = Masked

1b = Powergood threshold voltage

10b = Powergood threshold voltage AND current limit

11b = Powergood threshold voltage AND current limit

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10.7.1.117 PGOOD_SEL_4 Register (Offset = 0x7B) [Reset = 0x0]

PGOOD_SEL_4 is shown in Figure 10-176 and described in Table 10-140.

Return to the Table 10-22.

Figure 10-176. PGOOD_SEL_4 Register

7

6

5

4

3

2

1

0

PGOOD_WIND PGOOD_POL PGOOD_SEL_ PGOOD_SEL_ PGOOD_SEL_

RESERVED

R/W-0b

PGOOD_SEL_

VCCA

OW

NRSTOUT_SO

C

NRSTOUT

TDIE_WARN

R/W-0b

Table 10-140. PGOOD_SEL_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PGOOD_WINDOW

R/W

0b

Type of voltage monitoring for PGOOD signal:

(Default from NVM memory)

0b = Only undervoltage is monitored

1b = Both undervoltage and overvoltage are monitored

6

5

4

3

PGOOD_POL

R/W

0b

PGOOD signal polarity select:

(Default from NVM memory)

0b = PGOOD signal is high when monitored inputs are valid

1b = PGOOD signal is low when monitored inputs are valid

PGOOD_SEL_NRSTOUT R/W

_SOC

PGOOD signal source control from nRSTOUT_SOC pin:

(Default from NVM memory)

0b = Masked

1b = nRSTOUT_SOC pin low state forces PGOOD signal to low

PGOOD_SEL_NRSTOUT R/W

PGOOD signal source control from nRSTOUT pin:

(Default from NVM memory)

0b = Masked

1b = nRSTOUT pin low state forces PGOOD signal to low

PGOOD_SEL_TDIE_WAR R/W

N

PGOOD signal source control from thermal warning

(Default from NVM memory)

0b = Masked

1b = Thermal warning affecting to PGOOD signal

2:1

0

RESERVED

R/W

0b

PGOOD_SEL_VCCA

PGOOD signal source control from VCCA monitoring

(Default from NVM memory)

0b = Masked

1b = VCCA OV/UV threshold affecting PGOOD signal

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10.7.1.118 PLL_CTRL Register (Offset = 0x7C) [Reset = 0x0]

PLL_CTRL is shown in Figure 10-177 and described in Table 10-141.

Return to the Table 10-22.

Figure 10-177. PLL_CTRL Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

EXT_CLK_FREQ

R/W-0b

Table 10-141. PLL_CTRL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1:0

RESERVED

0b

EXT_CLK_FREQ

0b

Frequency of the external clock (SYNCCLKIN):

See electrical specification for input clock frequency tolerance.

(Default from NVM memory)

0b = 1.1 MHz

1b = 2.2 MHz

10b = 4.4 MHz

11b = Reserved

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10.7.1.119 CONFIG_1 Register (Offset = 0x7D) [Reset = 0xC0]

CONFIG_1 is shown in Figure 10-178 and described in Table 10-142.

Return to the Table 10-22.

Figure 10-178. CONFIG_1 Register

7

6

5

4

3

2

1

0

NSLEEP2_MAS NSLEEP1_MAS EN_ILIM_FSM_

I2C2_HS

I2C1_HS

RESERVED TSD_ORD_LEV TWARN_LEVE

K

CTRL

EL

L

R/W-1b

R/W-0b

Table 10-142. CONFIG_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

NSLEEP2_MASK

R/W

1b

Masking for NSLEEP2 pin(s) and NSLEEP2B bit:

(Default from NVM memory)

0b = NSLEEP2(B) affects FSM state transitions.

1b = NSLEEP2(B) does not affect FSM state transitions.

6

NSLEEP1_MASK

R/W

1b

Masking for NSLEEP1 pin(s) and NSLEEP1B bit:

(Default from NVM memory)

0b = NSLEEP1(B) affects FSM state transitions.

1b = NSLEEP1(B) does not affect FSM state transitions.

5

4

EN_ILIM_FSM_CTRL

I2C2_HS

R/W

0b

(Default from NVM memory)

0b = Buck/LDO regulators ILIM interrupts do not affect FSM triggers.

1b = Buck/LDO regulators ILIM interrupts affect FSM triggers.

Select I2C2 speed (input filter)

(Default from NVM memory)

0b = Standard, fast or fast+ by default, can be set to Hs-mode by

Hs-mode master code.

1b = Forced to Hs-mode

3

I2C1_HS

R/W

0b

Select I2C1 speed (input filter)

(Default from NVM memory)

0b = Standard, fast or fast+ by default, can be set to Hs-mode by

Hs-mode master code.

1b = Forced to Hs-mode

2

1

RESERVED

R/W

0b

TSD_ORD_LEVEL

Thermal shutdown threshold level.

(Default from NVM memory)

0b = 140C

1b = 145C

0

TWARN_LEVEL

R/W

0b

Thermal warning threshold level.

(Default from NVM memory)

0b = 130C

1b = 140C

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10.7.1.120 CONFIG_2 Register (Offset = 0x7E) [Reset = 0x0]

CONFIG_2 is shown in Figure 10-179 and described in Table 10-143.

Return to the Table 10-22.

Figure 10-179. CONFIG_2 Register

7

6

5

4

3

2

1

0

BB_EOC_RDY

RESERVED

BB_VEOC

R/W-0b

BB_ICHR

BB_CHARGER

_EN

R-0b

R/W-0b

Table 10-143. CONFIG_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

BB_EOC_RDY

R

0b

Backup end of charge indication

0b = Charging active or not enabled

1b = Charger has reached termination voltage set by BB_VEOC

register

6:4

3:2

RESERVED

BB_VEOC

R/W

0b

End of charge voltage for backup battery charger:

(Default from NVM memory)

0b = 2.5V

1b = 2.8V

10b = 3.0V

11b = 3.3V

1

0

BB_ICHR

R/W

0b

Backup battery charging current:

(Default from NVM memory)

0b = 100 µA

1b = 500 µA

BB_CHARGER_EN

Backup battery charging:

0b = Disabled

1b = Enabled

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10.7.1.121 ENABLE_DRV_REG Register (Offset = 0x80) [Reset = 0x0]

ENABLE_DRV_REG is shown in Figure 10-180 and described in Table 10-144.

Return to the Table 10-22.

Figure 10-180. ENABLE_DRV_REG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

ENABLE_DRV

R/W-0b

Table 10-144. ENABLE_DRV_REG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

0b

ENABLE_DRV

0b

Control for EN_DRV pin:

FORCE_EN_DRV_LOW must be 0 to control EN_DRV pin.

Otherwise EN_DRV pin is low.

0b = Low

1b = High

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10.7.1.122 MISC_CTRL Register (Offset = 0x81) [Reset = 0x0]

MISC_CTRL is shown in Figure 10-181 and described in Table 10-145.

Return to the Table 10-22.

Figure 10-181. MISC_CTRL Register

7

6

5

4

3

2

1

0

SYNCCLKOUT_FREQ_SEL

SEL_EXT_CLK AMUXOUT_EN CLKMON_EN

LPM_EN

NRSTOUT_SO

C

NRSTOUT

R/W-0b

R/W-0b R/W-0b R/W-0b

R/W-0b

Table 10-145. MISC_CTRL Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

SYNCCLKOUT_FREQ_S R/W

EL

0b

SYNCCLKOUT enable/frequency select:

0b = SYNCCLKOUT off

1b = 1.1 MHz

10b = 2.2 MHz

11b = 4.4 MHz

5

SEL_EXT_CLK

R/W

0b

Selection of external clock:

0b = Forced to internal RC oscillator.

1b = Automatic external clock used when available, interrupt is

generated if the external clock is expected (SEL_EXT_CLK = 1), but

it is not available or the clock frequency is not within the valid range.

4

3

2

AMUXOUT_EN

CLKMON_EN

LPM_EN

R/W

0b

Control bandgap voltage to AMUXOUT pin.

0b = Disabled

1b = Enabled

Control of internal clock monitoring.

0b = Disabled

1b = Enabled

Low power mode control.

LPM_EN sets device in a low power mode. Intended use case is

for the PFSM to set LPM_EN upon entering a deep sleep state.

The end objective is to disable the digital oscillator to reduce power

consumption.

The following functions are disabled when LPM_EN=1.

-TSD cycling of all sensors/thresholds

-regmap/SRAM CRC continuous checking

-SPMI WD NVM_ID request/response polling

-Disable clock monitoring

0b = Low power mode disabled

1b = Low power mode enabled

1

0

NRSTOUT_SOC

NRSTOUT

R/W

0b

Control for nRSTOUT_SOC signal:

0b = Low

1b = High

Control for nRSTOUT signal:

0b = Low

1b = High

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10.7.1.123 ENABLE_DRV_STAT Register (Offset = 0x82) [Reset = 0x8]

ENABLE_DRV_STAT is shown in Figure 10-182 and described in Table 10-146.

Return to the Table 10-22.

Figure 10-182. ENABLE_DRV_STAT Register

7

6

5

4

3

2

1

0

RESERVED

SPMI_LPM_EN FORCE_EN_D NRSTOUT_SO NRSTOUT_IN

EN_DRV_IN

RV_LOW

C_IN

R/W-0b

R/W-1b

R-0b

Table 10-146. ENABLE_DRV_STAT Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4

RESERVED

SPMI_LPM_EN

0b

This bit is read/write for PFSM and read-only for I2C/SPI

SPMI low power mode control.

SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI

WD (Bus heartbeat). PMICs should enter SPMI_LPM_EN=1 at

similar times to prevent SPMI WD failures. Therefore to mitigate

clock variations SPMI_LPM_EN=1 should be done early in the

sequence.

The following functions are disabled when SPMI_LPM_EN=1.

-SPMI WD NVM_ID request/response polling

0b = SPMI low power mode disabled

1b = SPMI low power mode enabled

3

FORCE_EN_DRV_LOW

R/W

1b

This bit is read/write for PFSM and read-only for I2C/SPI

0b = ENABLE_DRV bit can be written by I2C/SPI

1b = ENABLE_DRV bit is forced low and cannot be written high by

I2C/SPI

2

1

0

NRSTOUT_SOC_IN

NRSTOUT_IN

R

0b

Level of NRSTOUT_SOC pin:

0b = Low

1b = High

Level of NRSTOUT pin:

0b = Low

1b = High

EN_DRV_IN

Level of EN_DRV pin:

0b = Low

1b = High

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10.7.1.124 RECOV_CNT_REG_1 Register (Offset = 0x83) [Reset = 0x0]

RECOV_CNT_REG_1 is shown in Figure 10-183 and described in Table 10-147.

Return to the Table 10-22.

Figure 10-183. RECOV_CNT_REG_1 Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

RECOV_CNT

R-0b

Table 10-147. RECOV_CNT_REG_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:4

3:0

RESERVED

R

0b

RECOV_CNT

R

0b

Recovery counter status. Counter value is incremented each time

PMIC goes through warm reset.

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10.7.1.125 RECOV_CNT_REG_2 Register (Offset = 0x84) [Reset = 0x0]

RECOV_CNT_REG_2 is shown in Figure 10-184 and described in Table 10-148.

Return to the Table 10-22.

Figure 10-184. RECOV_CNT_REG_2 Register

7

6

5

4

3

2

1

0

RESERVED

RECOV_CNT_

CLR

RECOV_CNT_THR

R/W-0b

R/WSelfClrF-0b

Table 10-148. RECOV_CNT_REG_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

4

RESERVED

RECOV_CNT_CLR

R/W

0b

R/WSelfClrF 0b

Recovery counter clear. Write 1 to clear the counter. This bit is

automatically set back to 0.

3:0

RECOV_CNT_THR

R/W 0b

Recovery counter threshold value for immediate power-down of all

supply rails.

(Default from NVM memory)

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10.7.1.126 FSM_I2C_TRIGGERS Register (Offset = 0x85) [Reset = 0x0]

FSM_I2C_TRIGGERS is shown in Figure 10-185 and described in Table 10-149.

Return to the Table 10-22.

Figure 10-185. FSM_I2C_TRIGGERS Register

7

6

5

4

3

2

1

0

TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_ TRIGGER_I2C_

7

6

5

4

3

2

1

0

R/W-0b

R/WSelfClrF-0b R/WSelfClrF-0b R/WSelfClrF-0b R/WSelfClrF-0b

Table 10-149. FSM_I2C_TRIGGERS Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

TRIGGER_I2C_7

TRIGGER_I2C_6

TRIGGER_I2C_5

TRIGGER_I2C_4

TRIGGER_I2C_3

0b

Trigger for PFSM program.

6

0b

5

0b

4

0b

3

R/WSelfClrF 0b

Trigger for PFSM program.

This bit is automatically cleared. Writing this bit 1 creates PFSM

trigger pulse.

2

1

0

TRIGGER_I2C_2

TRIGGER_I2C_1

TRIGGER_I2C_0

Trigger for PFSM program.

This bit is automatically cleared. Writing this bit 1 creates PFSM

trigger pulse.

Trigger for PFSM program.

This bit is automatically cleared. Writing this bit 1 creates PFSM

trigger pulse.

Trigger for PFSM program.

This bit is automatically cleared. Writing this bit 1 creates PFSM

trigger pulse.

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10.7.1.127 FSM_NSLEEP_TRIGGERS Register (Offset = 0x86) [Reset = 0x0]

FSM_NSLEEP_TRIGGERS is shown in Figure 10-186 and described in Table 10-150.

Return to the Table 10-22.

Figure 10-186. FSM_NSLEEP_TRIGGERS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

NSLEEP2B

R/W-0b

NSLEEP1B

R/W-0b

Table 10-150. FSM_NSLEEP_TRIGGERS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:2

1

RESERVED

NSLEEP2B

0b

Parallel register bit for NSLEEP2 function:

0b = NSLEEP2 low

1b = NSLEEP2 high

0

NSLEEP1B

R/W

0b

Parallel register bit for NSLEEP1 function:

0b = NSLEEP1 low

1b = NSLEEP1 high

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10.7.1.128 BUCK_RESET_REG Register (Offset = 0x87) [Reset = 0x0]

BUCK_RESET_REG is shown in Figure 10-187 and described in Table 10-151.

Return to the Table 10-22.

Figure 10-187. BUCK_RESET_REG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

BUCK5_RESET BUCK4_RESET BUCK3_RESET BUCK2_RESET BUCK1_RESET

R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 10-151. BUCK_RESET_REG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4

RESERVED

BUCK5_RESET

0b

Reset signal for Buck logic.

Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1"

DURING DEVICE OPERATION.

3

2

1

0

BUCK4_RESET

BUCK3_RESET

BUCK2_RESET

BUCK1_RESET

R/W

0b

Reset signal for Buck logic.

Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1"

DURING DEVICE OPERATION.

Reset signal for Buck logic.

Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1"

DURING DEVICE OPERATION.

Reset signal for Buck logic.

Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1"

DURING DEVICE OPERATION.

Reset signal for Buck logic.

Warning: This bit is for debug only. DO NOT SET THIS BIT TO "1"

DURING DEVICE OPERATION.

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10.7.1.129 SPREAD_SPECTRUM_1 Register (Offset = 0x88) [Reset = 0x0]

SPREAD_SPECTRUM_1 is shown in Figure 10-188 and described in Table 10-152.

Return to the Table 10-22.

Figure 10-188. SPREAD_SPECTRUM_1 Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

SS_EN

R/W-0b

SS_DEPTH

R/W-0b

Table 10-152. SPREAD_SPECTRUM_1 Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:3

2

RESERVED

SS_EN

0b

Spread spectrum enable.

(Default from NVM memory)

0b = Spread spectrum disabled

1b = Spread spectrum enabled

1:0

SS_DEPTH

R/W

0b

Spread spectrum modulation depth.

(Default from NVM memory)

0b = No modulation

1b = +/- 6.3%

10b = +/- 8.4%

11b = RESERVED

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10.7.1.130 FREQ_SEL Register (Offset = 0x8A) [Reset = 0x0]

FREQ_SEL is shown in Figure 10-189 and described in Table 10-153.

Return to the Table 10-22.

Figure 10-189. FREQ_SEL Register

7

6

5

4

3

2

1

0

RESERVED

BUCK5_FREQ_ BUCK4_FREQ_ BUCK3_FREQ_ BUCK2_FREQ_ BUCK1_FREQ_

SEL

R/W-0b

Table 10-153. FREQ_SEL Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4

RESERVED

0b

BUCK5_FREQ_SEL

0b

Buck5 switching frequency:

This bit is Read/Write or Read-Only for I2C/SPI access depending on

EEPROM configuration. See TRM for details.

(Default from NVM memory)

0b = 2.2 MHz

1b = 4.4 MHz

3

2

1

0

BUCK4_FREQ_SEL

BUCK3_FREQ_SEL

BUCK2_FREQ_SEL

BUCK1_FREQ_SEL

R/W

0b

Buck4 switching frequency:

This bit is Read/Write or Read-Only for I2C/SPI access depending on

EEPROM configuration. See TRM for details.

(Default from NVM memory)

0b = 2.2 MHz

1b = 4.4 MHz

Buck3 switching frequency:

This bit is Read/Write or Read-Only for I2C/SPI access depending on

EEPROM configuration. See TRM for details.

(Default from NVM memory)

0b = 2.2 MHz

1b = 4.4 MHz

Buck2 switching frequency:

This bit is Read/Write or Read-Only for I2C/SPI access depending on

EEPROM configuration. See TRM for details.

(Default from NVM memory)

0b = 2.2 MHz

1b = 4.4 MHz

Buck1 switching frequency:

This bit is Read/Write or Read-Only for I2C/SPI access depending on

EEPROM configuration. See TRM for details.

(Default from NVM memory)

0b = 2.2 MHz

1b = 4.4 MHz

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10.7.1.131 FSM_STEP_SIZE Register (Offset = 0x8B) [Reset = 0x0]

FSM_STEP_SIZE is shown in Figure 10-190 and described in Table 10-154.

Return to the Table 10-22.

Figure 10-190. FSM_STEP_SIZE Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

PFSM_DELAY_STEP

R/W-0b

Table 10-154. FSM_STEP_SIZE Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4:0

RESERVED

PFSM_DELAY_STEP

0b

Step size for PFSM sequence counter.

Step size is 50ns * 2^{PFSM_DELAY_STEP}

(Default from NVM memory)

.

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10.7.1.132 LDO_RV_TIMEOUT_REG_1 Register (Offset = 0x8C) [Reset = 0x0]

LDO_RV_TIMEOUT_REG_1 is shown in Figure 10-191 and described in Table 10-155.

Return to the Table 10-22.

Figure 10-191. LDO_RV_TIMEOUT_REG_1 Register

7

6

5

4

3

2

1

0

LDO2_RV_TIMEOUT

R/W-0b

LDO1_RV_TIMEOUT

R/W-0b

Table 10-155. LDO_RV_TIMEOUT_REG_1 Register Field Descriptions

Bit

7:4

Field

Type

Reset

Description

LDO2_RV_TIMEOUT

R/W

0b

LDO residual voltage check timeout select.

(Default from NVM memory)

0b = 0.5 ms

1b = 1 ms

10b = 1.5 ms

11b = 2 ms

100b = 2.5 ms

101b = 3 ms

110b = 3.5 ms

111b = 4 ms

1000b = 2 ms

1001b = 4 ms

1010b = 6 ms

1011b = 8ms

1100b = 10 ms

1101b = 12 ms

1110b = 14 ms

1111b = 16 ms

3:0

LDO1_RV_TIMEOUT

R/W

0b

LDO residual voltage check timeout select.

(Default from NVM memory)

0b = 0.5 ms

1b = 1 ms

10b = 1.5 ms

11b = 2 ms

100b = 2.5 ms

101b = 3 ms

110b = 3.5 ms

111b = 4 ms

1000b = 2 ms

1001b = 4 ms

1010b = 6 ms

1011b = 8 ms

1100b = 10 ms

1101b = 12 ms

1110b = 14 ms

1111b = 16 ms

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10.7.1.133 LDO_RV_TIMEOUT_REG_2 Register (Offset = 0x8D) [Reset = 0x0]

LDO_RV_TIMEOUT_REG_2 is shown in Figure 10-192 and described in Table 10-156.

Return to the Table 10-22.

Figure 10-192. LDO_RV_TIMEOUT_REG_2 Register

7

6

5

4

3

2

1

0

LDO4_RV_TIMEOUT

R/W-0b

LDO3_RV_TIMEOUT

R/W-0b

Table 10-156. LDO_RV_TIMEOUT_REG_2 Register Field Descriptions

Bit

7:4

Field

Type

Reset

Description

LDO4_RV_TIMEOUT

R/W

0b

LDO residual voltage check timeout select.

(Default from NVM memory)

0b = 0.5 ms

1b = 1 ms

10b = 1.5 ms

11b = 2 ms

100b = 2.5 ms

101b = 3 ms

110b = 3.5 ms

111b = 4 ms

1000b = 2 ms

1001b = 4 ms

1010b = 6 ms

1011b = 8 ms

1100b = 10 ms

1101b = 12 ms

1110b = 14 ms

1111b = 16 ms

3:0

LDO3_RV_TIMEOUT

R/W

0b

LDO residual voltage check timeout select.

(Default from NVM memory)

0b = 0.5 ms

1b = 1 ms

10b = 1.5 ms

11b = 2 ms

100b = 2.5 ms

101b = 3 ms

110b = 3.5 ms

111b = 4 ms

1000b = 2 ms

1001b = 4 ms

1010b = 6 ms

1011b = 8 ms

1100b = 10 ms

1101b = 12 ms

1110b = 14 ms

1111b = 16 ms

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10.7.1.134 USER_SPARE_REGS Register (Offset = 0x8E) [Reset = 0x0]

USER_SPARE_REGS is shown in Figure 10-193 and described in Table 10-157.

Return to the Table 10-22.

Figure 10-193. USER_SPARE_REGS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

USER_SPARE_ USER_SPARE_ USER_SPARE_ USER_SPARE_

4

3

2

1

R/W-0b

Table 10-157. USER_SPARE_REGS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3

RESERVED

0b

USER_SPARE_4

USER_SPARE_3

USER_SPARE_2

USER_SPARE_1

0b

(Default from NVM memory)

2

0b

1

0b

0

0b

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10.7.1.135 ESM_MCU_START_REG Register (Offset = 0x8F) [Reset = 0x0]

ESM_MCU_START_REG is shown in Figure 10-194 and described in Table 10-158.

Return to the Table 10-22.

Figure 10-194. ESM_MCU_START_REG Register

7

6

5

4

3

2

1

0

RESERVED

ESM_MCU_ST

ART

R/W-0b

Table 10-158. ESM_MCU_START_REG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

ESM_MCU_START

0b

Control bit to start the ESM_MCU:

0b = ESM_MCU not started. Device clears ENABLE_DRV bit when

bit ESM_MCU_EN=1

1b = ESM_MCU started.

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10.7.1.136 ESM_MCU_DELAY1_REG Register (Offset = 0x90) [Reset = 0x0]

ESM_MCU_DELAY1_REG is shown in Figure 10-195 and described in Table 10-159.

Return to the Table 10-22.

Figure 10-195. ESM_MCU_DELAY1_REG Register

7

6

5

4

3

2

1

0

ESM_MCU_DELAY1

R/W-0b

Table 10-159. ESM_MCU_DELAY1_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_MCU_DELAY1

R/W

0b

These bits configure the duration of the ESM_MCU delay-1 time-

interval (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_MCU_START=0.

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10.7.1.137 ESM_MCU_DELAY2_REG Register (Offset = 0x91) [Reset = 0x0]

ESM_MCU_DELAY2_REG is shown in Figure 10-196 and described in Table 10-160.

Return to the Table 10-22.

Figure 10-196. ESM_MCU_DELAY2_REG Register

7

6

5

4

3

2

1

0

ESM_MCU_DELAY2

R/W-0b

Table 10-160. ESM_MCU_DELAY2_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_MCU_DELAY2

R/W

0b

These bits configure the duration of the ESM_MCU delay-2 time-

interval (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_MCU_START=0.

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10.7.1.138 ESM_MCU_MODE_CFG Register (Offset = 0x92) [Reset = 0x0]

ESM_MCU_MODE_CFG is shown in Figure 10-197 and described in Table 10-161.

Return to the Table 10-22.

Figure 10-197. ESM_MCU_MODE_CFG Register

7

6

5

4

3

2

1

0

ESM_MCU_MO ESM_MCU_EN ESM_MCU_EN

RESERVED

ESM_MCU_ERR_CNT_TH

R/W-0b

DE

DRV

R/W-0b

Table 10-161. ESM_MCU_MODE_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ESM_MCU_MODE

R/W

0b

This bit selects the mode for the ESM_MCU:

These bits can be only be written when control bit

ESM_MCU_START=0.

0b = Level Mode

1b = PWM Mode

6

ESM_MCU_EN

R/W

0b

ESM_MCU enable configuration bit:

These bits can be only be written when control bit

ESM_MCU_START=0.

0b = ESM_MCU disabled. MCU can set ENABLE_DRV bit to 1 if all

other interrupt bits are cleared

1b = ESM_MCU enabled. MCU can set ENABLE_DRV bit to 1 if:

- bit ESM_MCU_START=1, and

- (ESM_MCU_FAIL_INT=0 or ESM_MCU_ENDRV=0), and

- ESM_MCU_RST_INT=0, and

- all other interrupt bits are cleared

5

ESM_MCU_ENDRV

RESERVED

R/W

0b

Configuration bit to select ENABLE_DRV clear on ESM-error for

ESM_MCU:

These bits can be only be written when control bit

ESM_MCU_START=0.

0b = ENABLE_DRV not cleared when ESM_MCU_FAIL_INT=1

1b = ENABLE_DRV cleared when ESM_MCU_FAIL_INT=1

4

0b

3:0

ESM_MCU_ERR_CNT_T R/W

H

Configuration bits for the threshold of the ESM_MCU error-counter.

The ESM_MCU starts the Error Handling Procedure (see

Error Signal Monitor chapter) if ESM_MCU_ERR_CNT[4:0] >

ESM_MCU_ERR_CNT_TH[3:0].

These bits can be only be written when control bit

ESM_MCU_START=0.

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10.7.1.139 ESM_MCU_HMAX_REG Register (Offset = 0x93) [Reset = 0x0]

ESM_MCU_HMAX_REG is shown in Figure 10-198 and described in Table 10-162.

Return to the Table 10-22.

Figure 10-198. ESM_MCU_HMAX_REG Register

7

6

5

4

3

2

1

0

ESM_MCU_HMAX

R/W-0b

Table 10-162. ESM_MCU_HMAX_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_MCU_HMAX

R/W

0b

These bits configure the the maximum high-pulse time-threshold

(tHIGH_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_MCU_START=0.

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10.7.1.140 ESM_MCU_HMIN_REG Register (Offset = 0x94) [Reset = 0x0]

ESM_MCU_HMIN_REG is shown in Figure 10-199 and described in Table 10-163.

Return to the Table 10-22.

Figure 10-199. ESM_MCU_HMIN_REG Register

7

6

5

4

3

2

1

0

ESM_MCU_HMIN

R/W-0b

Table 10-163. ESM_MCU_HMIN_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_MCU_HMIN

R/W

0b

These bits configure the the minimum high-pulse time-threshold

(tHIGH_MIN_TH) for ESM_MCU (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_MCU_START=0.

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10.7.1.141 ESM_MCU_LMAX_REG Register (Offset = 0x95) [Reset = 0x0]

ESM_MCU_LMAX_REG is shown in Figure 10-200 and described in Table 10-164.

Return to the Table 10-22.

Figure 10-200. ESM_MCU_LMAX_REG Register

7

6

5

4

3

2

1

0

ESM_MCU_LMAX

R/W-0b

Table 10-164. ESM_MCU_LMAX_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_MCU_LMAX

R/W

0b

These bits configure the the maximum low-pulse time-threshold

(tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_MCU_START=0.

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10.7.1.142 ESM_MCU_LMIN_REG Register (Offset = 0x96) [Reset = 0x0]

ESM_MCU_LMIN_REG is shown in Figure 10-201 and described in Table 10-165.

Return to the Table 10-22.

Figure 10-201. ESM_MCU_LMIN_REG Register

7

6

5

4

3

2

1

0

ESM_MCU_LMIN

R/W-0b

Table 10-165. ESM_MCU_LMIN_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_MCU_LMIN

R/W

0b

These bits configure the the minimum low-pulse time-threshold

(tLOW_MAX_TH) for ESM_MCU (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_MCU_START=0.

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10.7.1.143 ESM_MCU_ERR_CNT_REG Register (Offset = 0x97) [Reset = 0x0]

ESM_MCU_ERR_CNT_REG is shown in Figure 10-202 and described in Table 10-166.

Return to the Table 10-22.

Figure 10-202. ESM_MCU_ERR_CNT_REG Register

7

6

5

4

3

2

ESM_MCU_ERR_CNT

R-0b

1

0

RESERVED

R-0b

Table 10-166. ESM_MCU_ERR_CNT_REG Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

4:0

RESERVED

R

0b

ESM_MCU_ERR_CNT

R

0b

Status bits to indicate the value of the ESM_MCU Error-Counter. The

device clears these bits when ESM_MCU_START bit is 0, or when

the device resets the MCU.

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10.7.1.144 ESM_SOC_START_REG Register (Offset = 0x98) [Reset = 0x0]

ESM_SOC_START_REG is shown in Figure 10-203 and described in Table 10-167.

Return to the Table 10-22.

Figure 10-203. ESM_SOC_START_REG Register

7

6

5

4

3

2

1

0

RESERVED

ESM_SOC_ST

ART

R/W-0b

Table 10-167. ESM_SOC_START_REG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

ESM_SOC_START

0b

Control bit to start the ESM_SoC:

0b = ESM_SoC not started. Device clears ENABLE_DRV bit when

bit ESM_SOC_EN=1

1b = ESM_SoC started

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10.7.1.145 ESM_SOC_DELAY1_REG Register (Offset = 0x99) [Reset = 0x0]

ESM_SOC_DELAY1_REG is shown in Figure 10-204 and described in Table 10-168.

Return to the Table 10-22.

Figure 10-204. ESM_SOC_DELAY1_REG Register

7

6

5

4

3

2

1

0

ESM_SOC_DELAY1

R/W-0b

Table 10-168. ESM_SOC_DELAY1_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_SOC_DELAY1

R/W

0b

These bits configure the duration of the ESM_SoC delay-1 time-

interval (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_SOC_START=0.

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10.7.1.146 ESM_SOC_DELAY2_REG Register (Offset = 0x9A) [Reset = 0x0]

ESM_SOC_DELAY2_REG is shown in Figure 10-205 and described in Table 10-169.

Return to the Table 10-22.

Figure 10-205. ESM_SOC_DELAY2_REG Register

7

6

5

4

3

2

1

0

ESM_SOC_DELAY2

R/W-0b

Table 10-169. ESM_SOC_DELAY2_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_SOC_DELAY2

R/W

0b

These bits configure the duration of the ESM_SoC delay-2 time-

interval (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_SOC_START=0.

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10.7.1.147 ESM_SOC_MODE_CFG Register (Offset = 0x9B) [Reset = 0x0]

ESM_SOC_MODE_CFG is shown in Figure 10-206 and described in Table 10-170.

Return to the Table 10-22.

Figure 10-206. ESM_SOC_MODE_CFG Register

7

6

5

4

3

2

1

0

ESM_SOC_MO ESM_SOC_EN ESM_SOC_EN

RESERVED

ESM_SOC_ERR_CNT_TH

R/W-0b

DE

DRV

R/W-0b

Table 10-170. ESM_SOC_MODE_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ESM_SOC_MODE

R/W

0b

This bit selects the mode for the ESM_SoC:

These bits can be only be written when control bit

ESM_SOC_START=0.

0b = Level Mode

1b = PWM Mode

6

ESM_SOC_EN

R/W

0b

ESM_SoC enable configuration bit:

These bits can be only be written when control bit

ESM_SOC_START=0.

0b = ESM_SoC disabled. MCU can set ENABLE_DRV bit to 1 if all

other interrupt bits are cleared

1b = ESM_SoC enabled. MCU can set ENABLE_DRV bit to 1 if:

- bit ESM_SOC_START=1, and

- (ESM_SOC_FAIL_INT=0 or ESM_SOC_ENDRV=0), and

- ESM_SOC_RST_INT=0, and

- all other interrupt bits are cleared.

5

ESM_SOC_ENDRV

RESERVED

R/W

0b

Configuration bit to select ENABLE_DRV clear on ESM-error for

ESM_SoC:

These bits can be only be written when control bit

ESM_SOC_START=0

0b = ENABLE_DRV not cleared when ESM_SOC_FAIL_INT=1

1b = ENABLE_DRV cleared when ESM_SOC_FAIL_INT=1.

4

0b

3:0

ESM_SOC_ERR_CNT_T R/W

H

Configuration bits for the threshold of the ESM_SoC error-counter

The ESM_SoC starts the Error Handling Procedure (see

Error Signal Monitor chapter) if ESM_SOC_ERR_CNT[4:0] >

ESM_SOC_ERR_CNT_TH[3:0].

These bits can be only be written when control bit

ESM_SOC_START=0.

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10.7.1.148 ESM_SOC_HMAX_REG Register (Offset = 0x9C) [Reset = 0x0]

ESM_SOC_HMAX_REG is shown in Figure 10-207 and described in Table 10-171.

Return to the Table 10-22.

Figure 10-207. ESM_SOC_HMAX_REG Register

7

6

5

4

3

2

1

0

ESM_SOC_HMAX

R/W-0b

Table 10-171. ESM_SOC_HMAX_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_SOC_HMAX

R/W

0b

These bits configure the the maximum high-pulse time-threshold

(tHIGH_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_SOC_START=0.

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10.7.1.149 ESM_SOC_HMIN_REG Register (Offset = 0x9D) [Reset = 0x0]

ESM_SOC_HMIN_REG is shown in Figure 10-208 and described in Table 10-172.

Return to the Table 10-22.

Figure 10-208. ESM_SOC_HMIN_REG Register

7

6

5

4

3

2

1

0

ESM_SOC_HMIN

R/W-0b

Table 10-172. ESM_SOC_HMIN_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_SOC_HMIN

R/W

0b

These bits configure the the minimum high-pulse time-threshold

(tHIGH_MIN_TH) for ESM_SoC (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_SOC_START=0.

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10.7.1.150 ESM_SOC_LMAX_REG Register (Offset = 0x9E) [Reset = 0x0]

ESM_SOC_LMAX_REG is shown in Figure 10-209 and described in Table 10-173.

Return to the Table 10-22.

Figure 10-209. ESM_SOC_LMAX_REG Register

7

6

5

4

3

2

1

0

ESM_SOC_LMAX

R/W-0b

Table 10-173. ESM_SOC_LMAX_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_SOC_LMAX

R/W

0b

These bits configure the the maximum low-pulse time-threshold

(tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_SOC_START=0.

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10.7.1.151 ESM_SOC_LMIN_REG Register (Offset = 0x9F) [Reset = 0x0]

ESM_SOC_LMIN_REG is shown in Figure 10-210 and described in Table 10-174.

Return to the Table 10-22.

Figure 10-210. ESM_SOC_LMIN_REG Register

7

6

5

4

3

2

1

0

ESM_SOC_LMIN

R/W-0b

Table 10-174. ESM_SOC_LMIN_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

ESM_SOC_LMIN

R/W

0b

These bits configure the the minimum low-pulse time-threshold

(tLOW_MAX_TH) for ESM_SoC (see Error Signal Monitor chapter).

These bits can be only be written when control bit

ESM_SOC_START=0.

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10.7.1.152 ESM_SOC_ERR_CNT_REG Register (Offset = 0xA0) [Reset = 0x0]

ESM_SOC_ERR_CNT_REG is shown in Figure 10-211 and described in Table 10-175.

Return to the Table 10-22.

Figure 10-211. ESM_SOC_ERR_CNT_REG Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

ESM_SOC_ERR_CNT

R-0b

Table 10-175. ESM_SOC_ERR_CNT_REG Register Field Descriptions

Bit

Field

Type

Reset

Description

7:5

4:0

RESERVED

ESM_SOC_ERR_CNT

R

0b

R

0b

Status bits to indicate the value of the ESM_SoC Error-Counter. The

device clears these bits when ESM_SOC_START bit is 0, or when

the device resets the SoC.

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10.7.1.153 REGISTER_LOCK Register (Offset = 0xA1) [Reset = 0x0]

REGISTER_LOCK is shown in Figure 10-212 and described in Table 10-176.

Return to the Table 10-22.

Figure 10-212. REGISTER_LOCK Register

7

6

5

4

3

2

1

0

RESERVED

REGISTER_LO

CK_STATUS

R/W-0b

Table 10-176. REGISTER_LOCK Register Field Descriptions

Bit

Field

RESERVED

Type

Reset

Description

7:1

0

R/W

0b

REGISTER_LOCK_STAT R/W

US

0b

Unlocking registers: write 0x9B to this address.

Locking registers: write anything else than 0x9B to this address.

Written 8 bit data to this address will not be stored, only lock status

can be read.

REGISTER_LOCK_STATUS bit shows the lock status:

0b = Registers are unlocked

1b = Registers are locked

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10.7.1.154 MANUFACTURING_VER Register (Offset = 0xA6) [Reset = 0x0]

MANUFACTURING_VER is shown in Figure 10-213 and described in Table 10-177.

Return to the Table 10-22.

Figure 10-213. MANUFACTURING_VER Register

7

6

5

4

3

2

1

0

SILICON_REV

R-0b

Table 10-177. MANUFACTURING_VER Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

SILICON_REV

R

0b

SILICON_REV[7:6] - Reserved

SILICON_REV[5:3] - ALR

SILICON_REV[2:0] - Metal

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10.7.1.155 CUSTOMER_NVM_ID_REG Register (Offset = 0xA7) [Reset = 0x0]

CUSTOMER_NVM_ID_REG is shown in Figure 10-214 and described in Table 10-178.

Return to the Table 10-22.

Figure 10-214. CUSTOMER_NVM_ID_REG Register

7

6

5

4

3

2

1

0

CUSTOMER_NVM_ID

R/W-0b

Table 10-178. CUSTOMER_NVM_ID_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

CUSTOMER_NVM_ID

R/W

0b

Customer defined value if customer programmed part

Same value as in TI_NVM_ID register if TI programmed part

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10.7.1.156 SOFT_REBOOT_REG Register (Offset = 0xAB) [Reset = 0x0]

SOFT_REBOOT_REG is shown in Figure 10-215 and described in Table 10-179.

Return to the Table 10-22.

Figure 10-215. SOFT_REBOOT_REG Register

7

6

5

4

3

2

1

0

RESERVED

SOFT_REBOO

T

R/W-0b

R/WSelfClrF-0b

Table 10-179. SOFT_REBOOT_REG Register Field Descriptions

Bit

Field

Type

Reset

Description

7:1

0

RESERVED

R/W

0b

SOFT_REBOOT

R/WSelfClrF 0b

Write 1 to request a soft reboot.

This bit is automatically cleared.

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10.7.1.157 RTC_SECONDS Register (Offset = 0xB5) [Reset = 0x0]

RTC_SECONDS is shown in Figure 10-216 and described in Table 10-180.

Return to the Table 10-22.

Figure 10-216. RTC_SECONDS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

SECOND_1

R/W-0b

SECOND_0

R/W-0b

Table 10-180. RTC_SECONDS Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

SECOND_1

SECOND_0

0b

6:4

3:0

0b

Second digit of seconds (range is 0 up to 5)

First digit of seconds (range is 0 up to 9)

0b

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10.7.1.158 RTC_MINUTES Register (Offset = 0xB6) [Reset = 0x0]

RTC_MINUTES is shown in Figure 10-217 and described in Table 10-181.

Return to the Table 10-22.

Figure 10-217. RTC_MINUTES Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

MINUTE_1

R/W-0b

MINUTE_0

R/W-0b

Table 10-181. RTC_MINUTES Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

MINUTE_1

MINUTE_0

0b

6:4

3:0

0b

Second digit of minutes (range is 0 up to 5)

First digit of minutes (range is 0 up to 9)

0b

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10.7.1.159 RTC_HOURS Register (Offset = 0xB7) [Reset = 0x0]

RTC_HOURS is shown in Figure 10-218 and described in Table 10-182.

Return to the Table 10-22.

Figure 10-218. RTC_HOURS Register

7

6

5

4

3

2

1

0

PM_NAM

R/W-0b

RESERVED

R/W-0b

HOUR_1

R/W-0b

HOUR_0

R/W-0b

Table 10-182. RTC_HOURS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

PM_NAM

R/W

0b

Only used in PM_AM mode (otherwise it is set to 0)

0b = AM

1b = PM

6

RESERVED

HOUR_1

R/W

0b

5:4

3:0

Second digit of hours(range is 0 up to 2)

First digit of hours (range is 0 up to 9)

HOUR_0

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10.7.1.160 RTC_DAYS Register (Offset = 0xB8) [Reset = 0x0]

RTC_DAYS is shown in Figure 10-219 and described in Table 10-183.

Return to the Table 10-22.

Figure 10-219. RTC_DAYS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

DAY_1

R/W-0b

DAY_0

R/W-0b

Table 10-183. RTC_DAYS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:4

3:0

RESERVED

DAY_1

0b

Second digit of days (range is 0 up to 3)

First digit of days (range is 0 up to 9)

DAY_0

0b

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10.7.1.161 RTC_MONTHS Register (Offset = 0xB9) [Reset = 0x0]

RTC_MONTHS is shown in Figure 10-220 and described in Table 10-184.

Return to the Table 10-22.

Figure 10-220. RTC_MONTHS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

MONTH_1

R/W-0b

MONTH_0

R/W-0b

Table 10-184. RTC_MONTHS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4

RESERVED

MONTH_1

MONTH_0

0b

Second digit of months (range is 0 up to 1)

First digit of months (range is 0 up to 9)

3:0

0b

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10.7.1.162 RTC_YEARS Register (Offset = 0xBA) [Reset = 0x0]

RTC_YEARS is shown in Figure 10-221 and described in Table 10-185.

Return to the Table 10-22.

Figure 10-221. RTC_YEARS Register

7

6

5

4

3

2

1

0

YEAR_1

R/W-0b

YEAR_0

R/W-0b

Table 10-185. RTC_YEARS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3:0

YEAR_1

YEAR_0

0b

Second digit of years (range is 0 up to 9)

First digit of years (range is 0 up to 9)

0b

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10.7.1.163 RTC_WEEKS Register (Offset = 0xBB) [Reset = 0x0]

RTC_WEEKS is shown in Figure 10-222 and described in Table 10-186.

Return to the Table 10-22.

Figure 10-222. RTC_WEEKS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

WEEK

R/W-0b

Table 10-186. RTC_WEEKS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:3

2:0

RESERVED

WEEK

0b

First digit of day of the week (range is 0 up to 6)

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10.7.1.164 ALARM_SECONDS Register (Offset = 0xBC) [Reset = 0x0]

ALARM_SECONDS is shown in Figure 10-223 and described in Table 10-187.

Return to the Table 10-22.

Figure 10-223. ALARM_SECONDS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

ALR_SECOND_1

R/W-0b

ALR_SECOND_0

R/W-0b

Table 10-187. ALARM_SECONDS Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

0b

6:4

3:0

ALR_SECOND_1

ALR_SECOND_0

0b

Second digit of alarm programmation for seconds (range is 0 up to 5)

First digit of alarm programmation for seconds (range is 0 up to 9)

0b

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10.7.1.165 ALARM_MINUTES Register (Offset = 0xBD) [Reset = 0x0]

ALARM_MINUTES is shown in Figure 10-224 and described in Table 10-188.

Return to the Table 10-22.

Figure 10-224. ALARM_MINUTES Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

ALR_MINUTE_1

R/W-0b

ALR_MINUTE_0

R/W-0b

Table 10-188. ALARM_MINUTES Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

0b

6:4

3:0

ALR_MINUTE_1

ALR_MINUTE_0

0b

Second digit of alarm programmation for minutes (range is 0 up to 5)

First digit of alarm programmation for minutes (range is 0 up to 9)

0b

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10.7.1.166 ALARM_HOURS Register (Offset = 0xBE) [Reset = 0x0]

ALARM_HOURS is shown in Figure 10-225 and described in Table 10-189.

Return to the Table 10-22.

Figure 10-225. ALARM_HOURS Register

7

6

5

4

3

2

1

0

ALR_PM_NAM

R/W-0b

RESERVED

R/W-0b

ALR_HOUR_1

R/W-0b

ALR_HOUR_0

R/W-0b

Table 10-189. ALARM_HOURS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

ALR_PM_NAM

R/W

0b

Only used in PM_AM mode for alarm programmation (otherwise it is

set to 0)

0b = AM

1b = PM

6

RESERVED

R/W

0b

5:4

3:0

ALR_HOUR_1

ALR_HOUR_0

Second digit of alarm programmation for hours(range is 0 up to 2)

First digit of alarm programmation for hours (range is 0 up to 9)

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10.7.1.167 ALARM_DAYS Register (Offset = 0xBF) [Reset = 0x0]

ALARM_DAYS is shown in Figure 10-226 and described in Table 10-190.

Return to the Table 10-22.

Figure 10-226. ALARM_DAYS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

ALR_DAY_1

R/W-0b

ALR_DAY_0

R/W-0b

Table 10-190. ALARM_DAYS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:6

5:4

3:0

RESERVED

ALR_DAY_1

ALR_DAY_0

0b

Second digit of alarm programmation for days (range is 0 up to 3)

First digit of alarm programmation for days (range is 0 up to 9)

0b

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10.7.1.168 ALARM_MONTHS Register (Offset = 0xC0) [Reset = 0x0]

ALARM_MONTHS is shown in Figure 10-227 and described in Table 10-191.

Return to the Table 10-22.

Figure 10-227. ALARM_MONTHS Register

7

6

5

4

3

2

1

0

RESERVED

ALR_MONTH_

1

ALR_MONTH_0

R/W-0b

Table 10-191. ALARM_MONTHS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:5

4

RESERVED

ALR_MONTH_1

ALR_MONTH_0

0b

Second digit of alarm programmation for months (range is 0 up to 1)

First digit of alarm programmation for months (range is 0 up to 9)

3:0

0b

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10.7.1.169 ALARM_YEARS Register (Offset = 0xC1) [Reset = 0x0]

ALARM_YEARS is shown in Figure 10-228 and described in Table 10-192.

Return to the Table 10-22.

Figure 10-228. ALARM_YEARS Register

7

6

5

4

3

2

1

0

ALR_YEAR_1

R/W-0b

ALR_YEAR_0

R/W-0b

Table 10-192. ALARM_YEARS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3:0

ALR_YEAR_1

ALR_YEAR_0

0b

Second digit of alarm programmation for years (range is 0 up to 9)

First digit of alarm programmation for years (range is 0 up to 9)

0b

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10.7.1.170 RTC_CTRL_1 Register (Offset = 0xC2) [Reset = 0x0]

RTC_CTRL_1 is shown in Figure 10-229 and described in Table 10-193.

Return to the Table 10-22.

Figure 10-229. RTC_CTRL_1 Register

7

6

5

4

3

2

1

0

RTC_V_OPT

GET_TIME

SET_32_COUN RESERVED

TER

MODE_12_24 AUTO_COMP

R/W-0b R/W-0b

ROUND_30S

STOP_RTC

R/W-0b

Table 10-193. RTC_CTRL_1 Register Field Descriptions

Bit

Field

RTC_V_OPT

Type

Reset

Description

7

R/W

0b

RTC date / time register selection:

0b = Read access directly to dynamic registers (RTC_SECONDS,

RTC_MINUTES, RTC_HOURS, RTC_DAYS, RTC_MONTHS,

RTC_YEAR, RTC_WEEKS)

1b = Read access to static shadowed registers: (see GET_TIME bit).

6

GET_TIME

R/W

0b

When writing a 1 into this register, the content of the dynamic

registers (RTC_SECONDS, RTC_MINUTES, RTC_HOURS,

RTC_DAYS, RTC_MONTHS, RTC_YEARS_ and RTC_WEEKS) is

transferred into static shadowed registers.

Each update of the shadowed registers needs to be done by re-

asserting GET_TIME bit to 1 (i.e.: reset it to 0 and then rewrite it to 1)

Note: Shadowed registers, linked to the GET_TIME feature, are a

parallel set of calendar static registers, at the same I2C addresses

as the dynamic registers.

Note: The GET_TIME feature loads the RTC counter in the shadow

registers and make the content of the shadow registers available and

stable for reading.

Note: The GET_TIME bit has to be set to 0 and again to 1 to get a

new timing value.

Note: If the time reading is done without GET_TIME, the read value

comes directly from the RTC counter and software has to manage

the counter change during the reading.

Time reading remains always at the same address, with or without

using the GET_TIME feature.

5

SET_32_COUNTER

R/W

0b

Note: This bit must only be used when the RTC is frozen.

0b = No action

1b = Set the 32kHz counter with RTC_COMP_MSB_REG/

RTC_COMP_LSB_REG value

4

3

RESERVED

R/W

0b

MODE_12_24

Note: It is possible to switch between the two modes at any time

without disturbed the RTC, read or write are always performed with

the current mode.

0b = 24 hours mode

1b = 12 hours mode (PM-AM mode)

2

1

AUTO_COMP

ROUND_30S

R/W

0b

AUTO_COMP

0b = No auto compensation

1b = Auto compensation enabled

Note: This bit is a toggle bit, the micro-controller can only write one

and RTC clears it.

If the micro-controller sets the ROUND_30S bit and then read it, the

micro-controller will read one until the rounding to the closest minute

is performed at the next second.

0b = No update

1b = When a one is written, the time is rounded to the closest minute

0

STOP_RTC

R/W

0b

STOP_RTC

0b = RTC is frozen

1b = RTC is running

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10.7.1.171 RTC_CTRL_2 Register (Offset = 0xC3) [Reset = 0x0]

RTC_CTRL_2 is shown in Figure 10-230 and described in Table 10-194.

Return to the Table 10-22.

Figure 10-230. RTC_CTRL_2 Register

7

6

5

4

3

2

1

0

FIRST_START

UP_DONE

STARTUP_DEST

FAST_BIST

LP_STANDBY_

SEL

XTAL_SEL

R/W-0b

XTAL_EN

R/W-0b

Table 10-194. RTC_CTRL_2 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

FIRST_STARTUP_DONE R/W

0b

This bit controls if EEPROM defaults are loaded to RTC domain reg

bits during EEPROM read

0b = EEPROM defaults are loaded to RTC domain bits

1b = EEPROM defaults are not loaded to RTC domain bits

6:5

STARTUP_DEST

R/W

0b

FSM startup destination select.

(Default from NVM memory)

0b = STANDBY/LP_STANDBY based on LP_STANDBY_SEL

1b = Reserved

10b = MCU_ONLY

11b = ACTIVE

4

3

FAST_BIST

R/W

0b

FAST_BIST

(Default from NVM memory)

0b = Logic and analog BIST is run at BOOT BIST.

1b = Only analog BIST is run at BOOT BIST.

LP_STANDBY_SEL

Control to enter low power standby state:

(Default from NVM memory)

0b = LDOINT is enabled in standby state.

1b = Low power standby state is used as standby state (LDOINT is

disabled).

2:1

XTAL_SEL

XTAL_EN

R/W

0b

Crystal oscillator type select

(Default from NVM memory)

0b = 6 pF

1b = 9 pF

10b = 12.5 pF

11b = Reserved

0

Crystal oscillator enable.

(Default from NVM memory)

0b = Crystal oscillator is disabled

1b = Crystal oscillator is enabled

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10.7.1.172 RTC_STATUS Register (Offset = 0xC4) [Reset = 0x80]

RTC_STATUS is shown in Figure 10-231 and described in Table 10-195.

Return to the Table 10-22.

Figure 10-231. RTC_STATUS Register

7

6

5

4

3

2

1

0

POWER_UP

R/W1C-1b

ALARM

R/W1C-0b

TIMER

RESERVED

R/W-0b

RUN

R-0b

RESERVED

R/W-0b

R/W1C-0b

Table 10-195. RTC_STATUS Register Field Descriptions

Bit

Field

POWER_UP

Type

Reset

Description

7

R/W1C

1b

Indicates that a reset occurred (bit cleared to 0 by writing 1) and that

RTC data are not valid anymore.

Note: POWER_UP is set by a reset, is cleared by writing one in this

bit.

Note: The POWER_UP (RTC_STATUS) and RESET_STATUS

(RTC_RESET_STATUS) register bits indicate the same information.

6

5

ALARM

TIMER

R/W1C

0b

Indicates that an alarm interrupt has been generated (bit clear by

writing 1).

Indicates that an timer interrupt has been generated (bit clear by

writing 1).

4:2

1

RESERVED

RUN

R/W

R

0b

Note: This bit shows the real state of the RTC, indeed because

of STOP_RTC (RTC_CTRL) signal was resynchronized on 32kHz

clock, the action of this bit is delayed.

0b = RTC is frozen

1b = RTC is running

0

RESERVED

R/W

0b

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10.7.1.173 RTC_INTERRUPTS Register (Offset = 0xC5) [Reset = 0x0]

RTC_INTERRUPTS is shown in Figure 10-232 and described in Table 10-196.

Return to the Table 10-22.

Figure 10-232. RTC_INTERRUPTS Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

IT_ALARM

R/W-0b

IT_TIMER

R/W-0b

EVERY

R/W-0b

Table 10-196. RTC_INTERRUPTS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:4

3

RESERVED

IT_ALARM

0b

Enable one interrupt when the alarm value is reached

(TC ALARM registers: ALARM_SECONDS, ALARM_MINUTES,

ALARM_HOURS, ALARM_DAYS, ALARM_MONTHS,

ALARM_YEARS) by the TC registers

NOTE: To prevent mis-firing of the ALARM interrupt, set the

IT_ALARM = 0 prior to configuring the ALARM registers

0b = interrupt disabled

1b = interrupt enabled

2

IT_TIMER

EVERY

R/W

0b

Enable periodic interrupt

NOTE: To prevent mis-firing of the TIMER interrupt, set the

IT_TIMER = 0 prior to configuring the periodic time value

0b = interrupt disabled

1b = interrupt enabled

1:0

Interrupt period

0b = every second

1b = every minute

10b = every hour

11b = every day

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10.7.1.174 RTC_COMP_LSB Register (Offset = 0xC6) [Reset = 0x0]

RTC_COMP_LSB is shown in Figure 10-233 and described in Table 10-197.

Return to the Table 10-22.

Figure 10-233. RTC_COMP_LSB Register

7

6

5

4

3

2

1

0

COMP_LSB_RTC

R/W-0b

Table 10-197. RTC_COMP_LSB Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

COMP_LSB_RTC

R/W

0b

This register contains the number of 32kHz periods to be added into

the 32kHz counter every hour [LSB]

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10.7.1.175 RTC_COMP_MSB Register (Offset = 0xC7) [Reset = 0x0]

RTC_COMP_MSB is shown in Figure 10-234 and described in Table 10-198.

Return to the Table 10-22.

Figure 10-234. RTC_COMP_MSB Register

7

6

5

4

3

2

1

0

COMP_MSB_RTC

R/W-0b

Table 10-198. RTC_COMP_MSB Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

COMP_MSB_RTC

R/W

0b

This register contains the number of 32kHz periods to be added into

the 32kHz counter every hour [MSB]

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10.7.1.176 RTC_RESET_STATUS Register (Offset = 0xC8) [Reset = 0x0]

RTC_RESET_STATUS is shown in Figure 10-235 and described in Table 10-199.

Return to the Table 10-22.

Figure 10-235. RTC_RESET_STATUS Register

7

6

5

4

3

2

1

0

RESERVED

RESET_STATU

S_RTC

R/W-0b

Table 10-199. RTC_RESET_STATUS Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:1

0

RESERVED

0b

RESET_STATUS_RTC

0b

This bit can only be set to one and is cleared when a manual reset

or a POR (case of VOUT_LDO_RTC below the LDO_RTC POR

level) occur. If this bit is reset it means that the RTC has lost its

configuration.

Note: The RESET_STATUS (RTC_RESET_STATUS) and

POWER_UP (RTC_STATUS) register bits indicate the same

information.

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10.7.1.177 SCRATCH_PAD_REG_1 Register (Offset = 0xC9) [Reset = 0x0]

SCRATCH_PAD_REG_1 is shown in Figure 10-236 and described in Table 10-200.

Return to the Table 10-22.

Figure 10-236. SCRATCH_PAD_REG_1 Register

7

6

5

4

3

2

1

0

SCRATCH_PAD_1

R/W-0b

Table 10-200. SCRATCH_PAD_REG_1 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

SCRATCH_PAD_1

R/W

0b

Scratchpad for temporary data storage. The register is reset only

when VRTC is disabled. The data is maintained when VINT regulator

is disabled, for example during LP_STANDBY state.

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10.7.1.178 SCRATCH_PAD_REG_2 Register (Offset = 0xCA) [Reset = 0x0]

SCRATCH_PAD_REG_2 is shown in Figure 10-237 and described in Table 10-201.

Return to the Table 10-22.

Figure 10-237. SCRATCH_PAD_REG_2 Register

7

6

5

4

3

2

1

0

SCRATCH_PAD_2

R/W-0b

Table 10-201. SCRATCH_PAD_REG_2 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

SCRATCH_PAD_2

R/W

0b

Scratchpad for temporary data storage. The register is reset only

when VRTC is disabled. The data is maintained when VINT regulator

is disabled, for example during LP_STANDBY state.

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10.7.1.179 SCRATCH_PAD_REG_3 Register (Offset = 0xCB) [Reset = 0x0]

SCRATCH_PAD_REG_3 is shown in Figure 10-238 and described in Table 10-202.

Return to the Table 10-22.

Figure 10-238. SCRATCH_PAD_REG_3 Register

7

6

5

4

3

2

1

0

SCRATCH_PAD_3

R/W-0b

Table 10-202. SCRATCH_PAD_REG_3 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

SCRATCH_PAD_3

R/W

0b

Scratchpad for temporary data storage. The register is reset only

when VRTC is disabled. The data is maintained when VINT regulator

is disabled, for example during LP_STANDBY state.

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10.7.1.180 SCRATCH_PAD_REG_4 Register (Offset = 0xCC) [Reset = 0x0]

SCRATCH_PAD_REG_4 is shown in Figure 10-239 and described in Table 10-203.

Return to the Table 10-22.

Figure 10-239. SCRATCH_PAD_REG_4 Register

7

6

5

4

3

2

1

0

SCRATCH_PAD_4

R/W-0b

Table 10-203. SCRATCH_PAD_REG_4 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

SCRATCH_PAD_4

R/W

0b

Scratchpad for temporary data storage. The register is reset only

when VRTC is disabled. The data is maintained when VINT regulator

is disabled, for example during LP_STANDBY state.

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10.7.1.181 PFSM_DELAY_REG_1 Register (Offset = 0xCD) [Reset = 0x0]

PFSM_DELAY_REG_1 is shown in Figure 10-240 and described in Table 10-204.

Return to the Table 10-22.

Figure 10-240. PFSM_DELAY_REG_1 Register

7

6

5

4

3

2

1

0

PFSM_DELAY1

R/W-0b

Table 10-204. PFSM_DELAY_REG_1 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

PFSM_DELAY1

R/W

0b

Generic delay1 for PFSM use.

The step size is defined by PFSM_DELAY_STEP bits.

(Default from NVM memory)

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10.7.1.182 PFSM_DELAY_REG_2 Register (Offset = 0xCE) [Reset = 0x0]

PFSM_DELAY_REG_2 is shown in Figure 10-241 and described in Table 10-205.

Return to the Table 10-22.

Figure 10-241. PFSM_DELAY_REG_2 Register

7

6

5

4

3

2

1

0

PFSM_DELAY2

R/W-0b

Table 10-205. PFSM_DELAY_REG_2 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

PFSM_DELAY2

R/W

0b

Generic delay2 for PFSM use.

The step size is defined by PFSM_DELAY_STEP bits.

(Default from NVM memory)

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10.7.1.183 PFSM_DELAY_REG_3 Register (Offset = 0xCF) [Reset = 0x0]

PFSM_DELAY_REG_3 is shown in Figure 10-242 and described in Table 10-206.

Return to the Table 10-22.

Figure 10-242. PFSM_DELAY_REG_3 Register

7

6

5

4

3

2

1

0

PFSM_DELAY3

R/W-0b

Table 10-206. PFSM_DELAY_REG_3 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

PFSM_DELAY3

R/W

0b

Generic delay3 for PFSM use.

The step size is defined by PFSM_DELAY_STEP bits.

(Default from NVM memory)

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10.7.1.184 PFSM_DELAY_REG_4 Register (Offset = 0xD0) [Reset = 0x0]

PFSM_DELAY_REG_4 is shown in Figure 10-243 and described in Table 10-207.

Return to the Table 10-22.

Figure 10-243. PFSM_DELAY_REG_4 Register

7

6

5

4

3

2

1

0

PFSM_DELAY4

R/W-0b

Table 10-207. PFSM_DELAY_REG_4 Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

PFSM_DELAY4

R/W

0b

Generic delay4 for PFSM use.

The step size is defined by PFSM_DELAY_STEP bits.

(Default from NVM memory)

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10.7.1.185 WD_ANSWER_REG Register (Offset = 0x401) [Reset = 0x0]

WD_ANSWER_REG is shown in Figure 10-244 and described in Table 10-208.

Return to the Table 10-22.

Figure 10-244. WD_ANSWER_REG Register

7

6

5

4

3

2

1

0

WD_ANSWER

R/W-0b

Table 10-208. WD_ANSWER_REG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

WD_ANSWER

R/W

0b

MCU answer byte. The MCU must write the expected reference

Answer-x into this register.

Each watchdog question requires four answer bytes:

– Three answer bytes (Answer-3, Answer-2, Answer-1) must be

written in Window-1.

– The fourth (final) answer-byte (Answer-0) must be written in

Window-2.

The number of written answer bytes is tracked with the

WD_ANSW_CNT counter in the WD_QUESTION_ANSW_CNT

register.

These bits only apply for Watchdog in Q&A mode.

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10.7.1.186 WD_QUESTION_ANSW_CNT Register (Offset = 0x402) [Reset = 0x30]

WD_QUESTION_ANSW_CNT is shown in Figure 10-245 and described in Table 10-209.

Return to the Table 10-22.

Figure 10-245. WD_QUESTION_ANSW_CNT Register

7

6

5

4

3

2

1

0

RESERVED

R-0b

WD_ANSW_CNT

R-11b

WD_QUESTION

R-0b

Table 10-209. WD_QUESTION_ANSW_CNT Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

5:4

RESERVED

R

0b

WD_ANSW_CNT

R

11b

Current, received watchdog-answer count state.

These bits only apply for Watchdog in Q&A mode.

3:0

WD_QUESTION

R

0b

Watchdog question.

The MCU must read (or calculate ) the current watchdog question

value to generate correct answers.

These bits only apply for Watchdog in Q&A mode.

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10.7.1.187 WD_WIN1_CFG Register (Offset = 0x403) [Reset = 0x7F]

WD_WIN1_CFG is shown in Figure 10-246 and described in Table 10-210.

Return to the Table 10-22.

Figure 10-246. WD_WIN1_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

WD_WIN1

R/W-1111111b

Table 10-210. WD_WIN1_CFG Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

WD_WIN1

0b

6:0

1111111b

These bits are for programming the duration of Watchdog Window-1

(see Watchdoc chapter).

These bits can be only be written when the watchdog is in the Long

Window.

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10.7.1.188 WD_WIN2_CFG Register (Offset = 0x404) [Reset = 0x7F]

WD_WIN2_CFG is shown in Figure 10-247 and described in Table 10-211.

Return to the Table 10-22.

Figure 10-247. WD_WIN2_CFG Register

7

6

5

4

3

2

1

0

RESERVED

R/W-0b

WD_WIN2

R/W-1111111b

Table 10-211. WD_WIN2_CFG Register Field Descriptions

Bit

7

Field

Type

R/W

Reset

Description

RESERVED

WD_WIN2

0b

6:0

1111111b

These bits are for programming the duration of Watchdog Window-2

(see Watchdog chapter).

These bits can be only be written when the watchdog is in the Long

Window.

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10.7.1.189 WD_LONGWIN_CFG Register (Offset = 0x405) [Reset = 0xFF]

WD_LONGWIN_CFG is shown in Figure 10-248 and described in Table 10-212.

Return to the Table 10-22.

Figure 10-248. WD_LONGWIN_CFG Register

7

6

5

4

3

2

1

0

WD_LONGWIN

R/W-11111111b

Table 10-212. WD_LONGWIN_CFG Register Field Descriptions

Bit

7:0

Field

Type

Reset

Description

WD_LONGWIN

R/W

11111111b

These bits are for programming the duration of Watchdog Long

Window (see Watchdog chapter).

These bits can be only be written when the watchdog is in the Long

Window.

(Default from NVM memory)

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10.7.1.190 WD_MODE_REG Register (Offset = 0x406) [Reset = 0x2]

WD_MODE_REG is shown in Figure 10-249 and described in Table 10-213.

Return to the Table 10-22.

Figure 10-249. WD_MODE_REG Register

7

6

5

4

3

2

1

0

RESERVED

WD_PWRHOL WD_MODE_SE WD_RETURN_

D

LECT

LONGWIN

R/W-0b

R/W-1b

R/W-0b

Table 10-213. WD_MODE_REG Register Field Descriptions

Bit

Field

Type

R/W

Reset

Description

7:3

2

RESERVED

0b

WD_PWRHOLD

0b

Device sets WD_PWRHOLD if hardware condition on pin

DISABLE_WDOG (mapped to GPIO8 pin) is applied at startup (see

Watchdog chapter).

MCU can write this bit to 1.

MCU needs to clear this bit to get out of the Long Window:

0b = watchdog goes out of the Long Window and starts the first

watchdog-sequence when the configured Long Window time-interval

elapses

1b = watchdog stays in Long Window

1

0

WD_MODE_SELECT

R/W

1b

0b

Watchdog mode-select:

MCU can set this to required value only when watchdog is in the

Long Window.

0b = Trigger Mode

1b = Q&A mode.

WD_RETURN_LONGWIN R/W

MCU can set this bit to put the watchdog from operating back to the

Long Window (see Watchdog chapter):

0b = Watchdog continues operating

1b = Watchdog returns to Long-Window after completion of the

current watchdog-sequence.

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10.7.1.191 WD_QA_CFG Register (Offset = 0x407) [Reset = 0xA]

WD_QA_CFG is shown in Figure 10-250 and described in Table 10-214.

Return to the Table 10-22.

Figure 10-250. WD_QA_CFG Register

7

6

5

4

3

2

1

0

WD_QA_FDBK

R/W-0b

WD_QA_LFSR

R/W-0b

WD_QUESTION_SEED

R/W-1010b

Table 10-214. WD_QA_CFG Register Field Descriptions

Bit

Field

Type

Reset

Description

7:6

WD_QA_FDBK

R/W

0b

Feedback configuration bits for the watchdog question. These bits

control the sequence of the generated questions and respective

reference answers (see Watchdog chapter).

These bits are only used for the watchdog in Q&A mode.

These bits can be only be written when the watchdog is in the Long

Window.

5:4

3:0

WD_QA_LFSR

R/W

0b

LFSR-equation configuration bits for the watchdog question (see

Watchdog chapter).

These bits are only used for the watchdog in Q&A mode.

These bits can be only be written when the watchdog is in the Long

Window.

WD_QUESTION_SEED

1010b

The watchdog question-seed value (see Watchdog chapter).

The MCU updates the question-seed value to generate a set of new

questions.

These bits can be only be written when the watchdog is in the Long

Window.

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10.7.1.192 WD_ERR_STATUS Register (Offset = 0x408) [Reset = 0x0]

WD_ERR_STATUS is shown in Figure 10-251 and described in Table 10-215.

Return to the Table 10-22.

Figure 10-251. WD_ERR_STATUS Register

7

6

5

4

3

2

1

0

WD_RST_INT WD_FAIL_INT WD_ANSW_ER WD_SEQ_ERR WD_ANSW_EA WD_TRIG_EAR WD_TIMEOUT WD_LONGWIN

R

RLY

LY

_TIMEOUT_INT

R/W1C-0b

Table 10-215. WD_ERR_STATUS Register Field Descriptions

Bit

Field

Type

Reset

Description

7

WD_RST_INT

R/W1C

0b

Latched status bit to indicate that the device went through

warm reset due to WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] +

WD_RST_TH[2:0]).

Write 1 to clear.

6

5

WD_FAIL_INT

R/W1C

0b

Latched status bit to indicate that the watchdog has cleared the

ENABLE_DRV bit due to WD_FAIL_CNT[3:0] > WD_FAIL_TH[2:0].

Write 1 to clear.

WD_ANSW_ERR

Latched status bit to indicate that the watchdog has detected an

incorrect answer-byte.

Write 1 to clear.

This bit only applies for Watchdog in Q&A mode.

4

3

2

WD_SEQ_ERR

R/W1C

0b

Latched status bit to indicate that the watchdog has detected an

incorrect sequence of the answer-bytes.

Write 1 to clear.

This bit only applies for Watchdog in Q&A mode.

WD_ANSW_EARLY

WD_TRIG_EARLY

WD_TIMEOUT

Latched status bit to indicate that the watchdog has received the final

answer-byte in Window-1.

Write 1 to clear.

This bit only applies for Watchdog in Q&A mode.

Latched status bit to indicate that the watchdog has received the

watchdog-trigger in Window-1.

Write 1 to clear.

This bit only applies for Watchdog in Trigger mode.

1

0

0b

Latched status bit to indicate that the watchdog has detected a time-

out event in the started watchdog sequence.

Write 1 to clear.

WD_LONGWIN_TIMEOU R/W1C

T_INT

Latched status bit to indicate that device went through warm reset

due to elapse of Long Window time-interval.

Write 1 to clear interrupt.

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10.7.1.193 WD_THR_CFG Register (Offset = 0x409) [Reset = 0xFF]

WD_THR_CFG is shown in Figure 10-252 and described in Table 10-216.

Return to the Table 10-22.

Figure 10-252. WD_THR_CFG Register

7

6

5

4

3

2

1

0

WD_RST_EN

R/W-1b

WD_EN

R/W-1b

WD_FAIL_TH

R/W-111b

WD_RST_TH

R/W-111b

Table 10-216. WD_THR_CFG Register Field Descriptions

Bit

Field

WD_RST_EN

Type

Reset

Description

7

R/W

1b

Watchdog reset configuration bit:

This bit can be only be written when the watchdog is in the Long

Window.

0b = No warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0]

+ WD_RST_TH[2:0])

1b = Warm reset when WD_FAIL_CNT[3:0] > (WD_FAIL_TH[2:0] +

WD_RST_TH[2:0]).

6

WD_EN

R/W

1b

Watchdog enable configuration bit:

This bit can be only be written when the watchdog is in the Long

Window.

(Default from NVM memory)

0b = watchdog disabled. MCU can set ENABLE_DRV bit to 1 if all

other interrupt status bits are cleared

1b = watchdog enabled. MCU can set ENABLE_DRV bit to 1 if:

- watchdog is out of the Long Window

- WD_FAIL_CNT[3:0] =< WD_FAIL_TH[2:0]

- WD_FIRST_OK=1

- all other interrupt status bits are cleared.

5:3

2:0

WD_FAIL_TH

WD_RST_TH

R/W

111b

Configuration bits for the 1st threshold of the watchdog fail counter:

Device clears ENABLE_DRV bit when WD_FAIL_CNT[3:0] >

WD_FAIL_TH[2:0].

These bits can be only be written when the watchdog is in the Long

Window.

Configuration bits for the 2nd threshold of the watchdog fail counter:

Device goes through warm reset when WD_FAIL_CNT[3:0] >

(WD_FAIL_TH[2:0] + WD_RST_TH[2:0]).

These bits can be only be written when the watchdog is in the Long

Window.

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10.7.1.194 WD_FAIL_CNT_REG Register (Offset = 0x40A) [Reset = 0x20]

WD_FAIL_CNT_REG is shown in Figure 10-253 and described in Table 10-217.

Return to the Table 10-22.

Figure 10-253. WD_FAIL_CNT_REG Register

7

6

5

4

3

2

1

0

RESERVED

WD_BAD_EVE WD_FIRST_OK RESERVED

NT

WD_FAIL_CNT

R-0b

R-1b

R-0b

Table 10-217. WD_FAIL_CNT_REG Register Field Descriptions

Bit

7

Field

RESERVED

Type

Reset

Description

R

0b

6

WD_BAD_EVENT

R

0b

Status bit to indicate that the watchdog has detected a bad event in

the current watchdog sequence.

The device clears this bit at the end of the watchdog sequence.

5

WD_FIRST_OK

R

1b

Status bit to indicate that the watchdog has detected a good event.

The device clears this bit when the watchdog goes to the Long

Window.

4

RESERVED

R

0b

3:0

WD_FAIL_CNT

Status bits to indicate the value of the Watchdog Fail Counter.

The device clears these bits when the watchdog goes to the Long

Window.

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11 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification,

and TI does not warrant its accuracy or completeness. TI’s customers are responsible for

determining suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

11.1 Application Information

The following sections will provide more detail on the proper utilization of the PMIC. Each orderable part number

has unique default non-volatile memory settings and the relevant user's guide for that orderable are available in

the product folder. Reference these user's guides for specific application information. More generic topics and

some examples are outlined here.

To help with new designs, a variety of tools and documents are available in the product folder. Some examples

are:

•

Evaluation module and user guide which allow testing of various orderable part numbers, including multi-

PMIC operation

•

GUI to communicate with the PMIC

Schematic and layout checklist

Periodically, new tools and documents will be added to aid in new designs.

11.2 Typical Application

The PMIC is generally used to power a processor. The number of regulators needed, the required sequencing,

the load current requirements, and the voltage characteristics are all critical in determining the number of PMICs

used in the system as well as the external components used with it. The following section provides a generic

case. For specific cases, refer to the relevant user's guide based on the orderable part number.

11.2.1 Powering a Processor

In this example, a single PMIC is used to power a generic processor. For this case, the PMIC is used in 2+1+1+1

buck phase configuration where BUCK1 and BUCK2 are used in parallel to supply higher currents.

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Processor Supplies

0.8V

BUCK1

3.3V

(3.5A max)

VCCA

POWER DOMAINS

VDD CORE

0.8V

BUCK2

(3.5A max)

0.85V

0.8V (AVS)

1.1V

BUCK3

(3.5A max)

MCU

CPU (AVS)

BUCK4

(4A max)

BUCK5

(2A max)

VDD DDR

1.8V

LDO1

VDDA

(500mA max)

1.8V

LDO2

1.8V PHYs

(500mA max)

0.8V

LDO3

(500mA max)

0.8V PLLs and DLLs

3.3V VDDSHVx

1.8V

LDO4

(300mA max)

VIO_IN

I2C

nRSTOUT

PORz

System

1.8V

EN

3.3V

Load Switch

1.1V

Figure 11-1. Example Power Map

11.2.1.1 Design Requirements

The design requirements for the sample processor in Figure 11-1 are outlined below:

•

VDD CORE rail requires 0.8 V, 5 A

MCU rail requires 0.85 V, 2 A

CPU (AVS) rail requires 0.8 V, 3 A and the ability to support Adaptive Voltage Scaling

LPDDR4 is used, which requires 1.1 V, 1 A and 1.8 V, 200 mA

1.8V PHYs and 0.8V PLLs and DLLs which are noise sensitive

VDDA supplies the processor's most noise sensitive components, requires 100 mA, and requires extra low

noise

•

Protection from 3.3 V overvoltage (functional safety variant only)

11.2.1.2 Detailed Design Procedure

Based on the above requirements, the PMIC was configured with the connections outlined in Figure 11-1.

BUCK1 and BUCK2 are used in multiphase operation to support the 5 A current. LDO2 and LDO3 are used to

power 1.8 V PHYs and 0.8 V PLLs and DLLs because they are lower noise than a buck regulator and it isolates

them from the noise of VDD CORE and the LPDDR4 1.8 V supply. LDO4 was used to power VDDA because it is

has even better noise performance.

Using this configuration information, components can be chosen to use with the PMIC.

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11.2.1.2.1 VCCA, VSYS_SENSE, and OVPGDRV

The VCCA pin provides power to LDOVINT and other internal functions. It is always connected in parallel with

the buck input pins (PVIN_Bx pins). The VSYS_SENSE pin and OVPGDRV pin protect the device from being

damaged by an overvoltage event from the pre-regulator by disconnecting the low voltage VCCA-powered pins

from VSYS. The VCCA pin can be connected to an optional 0.47-µF bypass capacitor close to the pin. For

cases where the pre-regulator is not located near the device, place some additional bulk capacitance before the

protection FET to stabilize the VSYS supply near the device.

For the input protection, total capacitance on the VSYS node must guarantee that VCCA does not rise above 8 V

before the PMIC disables the protection FET in case of pre-regulator high side FET short failure. The maximum

time specification is 15 µs, which leads to a maximum average slew rate of 133 mV / µs in the 6 V to 8 V

range. The capacitance varies based on the pre-regulator inductor and the pre-regulator input filter and it is

recommended to simulate this circuit to get an initial estimate on the required capacitance.

Choose a Zener diode with a breakdown voltage less than the recommended maximum of the VSYS_SENSE

pin (12 V maximum) and greater than the overvoltage detection voltage (VSYS_OVP_Rising of 6.2 V) at all

times for proper protection. Choose the protection resistors values to assure that the voltage across the Zener

diode remains within those two boundaries and that the current is not greater than the Zener diode maximum

current for the full desired input voltage protection range. For increased reliability, two resistors with 90° physical

orientation offset are recommended to reduce risk of a single point short resulting in IC damage.

Finally, choose the protection NMOS FET with sufficient current and voltage ratings for the application with

minimal gate charge values. The turn-on and turn-off time of the protection FET is generally very fast relative

to the detection time, so gate charge is not as critical as R_DSONin general. The components chosen for the

evaluation module to cover a broad set of applications are shown in Table 11-1. To determine the required

minimum FET R_DS(ON), the maximum input current is first measured or calculated based on output current

requirements multiplied by the duty cycle (V_OUT/ V_IN) and then divided by the buck efficiency. Next, determine

the VCCA_{UV_TH}from the VCCA_PG_WINDOW. VCCA_UV_THR register setting. The R_DS(ON)maximum must

be less than the VCCA_{UV_TH}minimum divided by the input current maximum to ensure that VCCA does not drop

below VCCA_{UV_TH}at maximum loading. From there, the second factor to consider is to minimize the Q_GSfor

faster FET turn off time.

For cases where input voltage protection is not required, ground VSYS_SENSE, float OVPGDRV, and the

protection diode and FET are not needed.

Table 11-1. Recommended VCCA, VSYS_SENSE, and OVPGDRV Components

EIA SIZE

CODE

COMPONENT

MANUFACTURER

PART NUMBER

VALUE

SIZE (mm)

USED for VALIDATION

Capacitor

Murata

GCM155C71A474KE36

CGA2B3X7S1A474K050BB

MM3Z10VST1G

0.47 µF, 10 V, X7R 0402

1.0 × 0.5

Yes

—

Capacitor

TDK

1.0 × 0.5

Zener Diode

Resistor⁽¹⁾

NMOS FET

ON Semiconductor

Vishay-Dale

On Semiconductor

10 V, 300 mW

240 Ω

SOD-323

2.5 × 1.25 × 0.9

3.1 × 2.6 × 1.15

1.0 × 0.5

Yes

—

BZX84B10-G3-08

SOT-23-3

0402

CRCW0402240RJNED

NVMFS4C05N

Yes

30 V, 4.0 mΩ, 127

A

—

5.15 × 6.15 × 1.0

NMOS FET

Diodes Incorporated

DMNH3010LK3

30 V, 11.5 mΩ, 50 A

—

6.70 × 10.41 × 2.39

—

(1) Two resistors are used in series to create an effective 480 Ω total resistance.

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11.2.1.2.2 Internal LDOs

The internal LDOs, VOUT_LDOVINT and VOUT_LDOVRTC, require external 2.2 µF capacitors for stabilization.

The recommended components are shown below.

Table 11-2. Recommended Internal LDO Components

COMPONE MANUFACTURE

NT

USED for

VALIDATION

PART NUMBER

VALUE

EIA SIZE CODE

SIZE (mm)

1.6 × 0.8

R

2.2 µF, 6.3 V,

X7R

Capacitor Murata

Capacitor TDK

GCM188R70J225KE22

0603

—

CGA3E1X7S1C225M080 2.2 µF, 6.3 V,

AC X7R

0603

11.2.1.2.3 Crystal Oscillator

A crystal oscillator can be used for application requiring a high accuracy real-time clock module. The

OSC32KCAP pin is bypassed with a 100-nF bypass capacitor for noise rejection. For the OSC32KIN and

OSC32KOUT pins, a simplified oscillator schematic is shown in Figure 11-2 to determine what external load

capacitors are needed for the crystal.

Figure 11-2. Crystal Oscillator Component Selection

C_IN1and C_IN2are both 12 pF for this device. C_PCB1and C_PCB2will depend on the board but is generally around

1 pF. The crystal oscillator chosen should have a required load capacitance of either 6 pF, 9 pF, or 12.5 pF and

the value of the XTAL_SEL bit in the RTC_CTRL_2 register should be updated based on the oscillator chosen.

To achieve the required load capacitance (C_L) for the oscillator, Equation 26 is used. It assumes that the crystal

series capacitance is negligible.

C_L= (C_L1+ C_PCB1+ C_IN1) × (C_L2+ C_PCB2+ C_IN2) / ((C_L1+ C_PCB1+ C_IN1) + (C_L2+ C_PCB2+ C_IN2))

(26)

Assuming C_L1= C_L2, this simplifies to C_L1= 2 × C_L- C_PCB- C_IN. Simplifying this into the standard capacitor

values typically available results in the following general capacitor recommendations. If more precise matching is

desired, complete the exercise without series capacitance neglected and with exact PCB parasitic capacitance.

Too much capacitance will result in the oscillator frequency being lower than expected, while not enough

capacitance has the opposite impact.

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Table 11-3. Approximate Crystal Oscillator Load Capacitors

Crystal C_L(pF)

Component C_L1= C_L2(pF)

6

9

0

6

12.5

The recommended components using a 9 pF oscillator as an example are in Table 11-4. If an alternate load

capacitance crystal is used, the values of the load capacitors should be adjusted to match based on the above.

Table 11-4. Recommended Crystal Oscillator Components for 9 pF Crystal

EIA size

code

Component

MANUFACTURER

PART NUMBER

VALUE

SIZE (mm)

Used for Validation

Capacitor

Crystal

Murata

TDK

GCM155R71C104JA55D

100 nF, 16 V, X7R 0402

1.0 x 0.5

Yes

-

CGA2B1X7R1C104K050BC 100 nF, 16 V, X7R 0402

1.0 x 0.5

NDK

NX3215SD-32.768K-STD-

MUS-6

32.768 kHz, ±20

ppm, 9 pF

3.2 x 1.5 x 0.9

Yes

Crystal

Abracon

Murata

TDK

ABS07AIG-32.768kHz-9-T

32.768 kHz, ±20

ppm, 9 pF

3.2 x 1.5 x 0.9

1.0 x 0.5

-

Capacitor

GCM1555C1H6R0CA16

6 pF, 50 V,

C0G/NP0

0402

Yes

-

CGA2B2C0G1H060D050BA 6 pF, 50 V,

C0G/NP0

1.0 x 0.5

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11.2.1.2.4 Buck Input Capacitors

For optimal performance, every buck needs an input capacitor, and the capacitor should be at least 10 µF, 10 V

and shall be placed as close to the buck input pins as possible. If the board size allows a larger foot print, a 22

µF, 10 V capacitor is recommended. See Table 11-5 for the recommended input capacitors, and the Section 11.4

for more information about component placement.

Table 11-5. Recommended Buck Input Capacitors

MANUFACTURER

TDK

PART NUMBER

VALUE

EIA size code

SIZE (mm)

Used for Validation

CGA4J1X7S1C106K125AC

GCM21BR71A106KE22

10 µF, 16 V, X7R

10 µF, 10 V, X7R

0805

2.0 × 1.25 × 1.25

Yes

-

Murata

0805

11.2.1.2.5 Buck Output Capacitors

The buck converters have seven potential NVM configurations which can impact the output capacitor selection.

Refer the part number specific user's guide to identify which configuration applies to each buck regulator. The

actual minimal capacitance requirements to achieve a specific accuracy or ripple target will vary depending on

the input voltage, output voltage, and load transient characteristics; some guidance, however, is provided below.

The local output capacitors shall be placed as close to the inductor as possible to minimize electromagnetic

emissions. Every buck output requires a local output capacitor to form the capacitive part of the LC output filter.

It is recommended to place all large capacitors near the inductor. See Section 11.4 for more information about

component placement.

To achieve better ripple and transient performance, additional high pass filter caps are recommended to

compensate for the parasitic impedances due to board routing and provide faster transient response to a load

step. These caps are placed close to the point of load and are also the input capacitors of the load. These

capacitors are referred to as POL caps later in this document. POL capacitor usage will vary based on the

application and generally follows the SoC or FPGA input capacitor requirements. Low ESL 3-terminal caps

are recommended, as their high performance can help reduce the total number of capacitors required which

simplifies board layout design and saves board area. They also help to reduce the total cost of the solution.

Figure 11-3 is an example power distribution network (PDN) of local and POL caps at the output of a buck for

optimal ripple and transient performance. Table 11-6 lists the local and POL capacitors used to validate the buck

transient and ripple performance specified in the parametric table for each of the seven configurations. Table

11-7 lists the actual capacitor part numbers used for the different use case tests, neglecting capacitors below 10

µF. It is recommended to simulate and validate that the capacitor network chosen for a particular design meets

the desired requirements as these are provided as guidelines.

Figure 11-3. Example Power Distribution Network (PDN) of Local and POL Capacitors

Table 11-6. Local and POL Capacitors used for Buck Use Case Validation

Configuration

C_OUT

Low

High

Low

High

Low

High

Low

High

Low

High

L

C_L1/ phase

47 µF × 2

47 µF × 4

47 µF × 1

47 µF × 4

22 µF × 1

47 µF × 1

47 µF × 2

47 µF × 3

C_L2(total)

C_POL1(total)

10 µF × 4

10 µF × 2

10 µF × 4

10 µF × 2

10 µF × 4

10 µF × 2

10 µF × 4

220 nH

470 nH

1000 nH

4.4 MHz V_OUTLess than 1.9 V, Multiphase

4.4 MHz V_OUTLess than 1.9 V, Single Phase with high C_OUT

4.4 MHz V_OUTLess than 1.9 V, Single Phase with low C_OUT

4.4 MHz V_OUTGreater than 1.7 V, Single Phase Only (V_INGreater

than 4.5 V)

2.2 MHz Full V_OUTRange and V_INGreater than 4.5 V, Single Phase

Only

680 µF × 1

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Table 11-6. Local and POL Capacitors used for Buck Use Case Validation (continued)

Configuration

C_OUT

Low

High

Low

High

-

L

C_L1/ phase

47 µF × 3

100 µF × 4

22 µF × 1

C_L2(total)

C_POL1(total)

470 nH

1000 nH

470 nH

10 µF × 4

2.2 MHz V_OUTLess than 1.9 V Multiphase or Single Phase

680 µF × 1

10 µF × 4

10 µF × 2

2.2 MHz Full V_OUTand Full V_INRange, Single Phase Only

DDR VTT Termination, 2.2 MHz Single Phase Only

10 µF × 2

10 µF × 1 + 22 µF x 1

Table 11-7. Recommended Buck Converter Output Capacitor Components

MANUFACTURER

Murata

PART NUMBER

VALUE

EIA Size Code

SIZE (mm)

Used for Validation

NFM15HC105D0G⁽¹⁾

1 µF, 4 V, X7S

1 µF, 6.3 V

0402

1.0 × 0.5

Yes

TDK

YFF18AC0J105M⁽¹⁾

0603

1206

0805

1206

0805

1210

1206

1210

1206

1210

2917

1.6 × 0.8

-

Murata

TDK

NFM18HC106D0G⁽¹⁾

10 µF, 4 V, X7S

4.7 µF, 6.3 V

1.6 × 0.8

Yes

YFF18AC0G475M⁽¹⁾

1.6 × 0.8

-

Murata

TDK

GCM31CR71A226KE02

GCM21BD7CGA5L1X7R0J226MT0J226M

CGA5L1X7R0J226MT

CGA4J1X7T0J226MT

22 µF, 10 V, X7R

22 µF, 6.3 V, X7T

22 µF, 6.3 V, X7R

22 µF, 6.3 V, X7T

47 µF, 6.3 V, X7R

47 µF, 4 V, X7T

47 µF, 10 V, X7S

47 µF, 4 V, X7T

100 µF, 4 V, X7S

100 µF, 4 V, X7T

680 µF, 6.3 V

3.2 × 1.6

Yes

2.0 × 1.25 × 1.25

3.2 × 1.6

-

TDK

2.0 × 1.25 × 1.25

3.2 × 2.5

-

Murata

TDK

GCM32ER70J476ME19

GCM31CD70G476M

Yes

3.2 × 1.6

-

CGA6P1X7S1A476MT

CGA5L1X7T0G476MT

GCM32ED70G107MEC4

CGA6P1X7T0G107MT

T510X687K006ATA023⁽²⁾

3.2 × 2.5

-

TDK

3.2 × 1.6

-

Murata

TDK

3.2 × 2.5

Yes

-

3.2 × 2.5

Kemet

7.4 × 5.0

Yes

(1) Low ESL 3-terminal cap.

(2) Dependent on availability; may switch to 470 µF.

11.2.1.2.6 Buck Inductors

Inductor should be chosen based on the buck configuration. See Table 11-6 for the appropriate nominal

inductance.

Recommended inductors based on these requirements are shown below.

Table 11-8. Recommended Buck Converter Inductors

MANUFACTURER

TDK

PART NUMBER

VALUE

SIZE (mm)

Used for Validation

TFM322512ALMA1R0MTAA

DFE322520FD-1R0M=P2

TFM322512ALMAR47MTAA

TFM252012ALMAR47MTAA

DFE2HCAHR47MJ0

1000 nH, 4 A Max, 150 °C

3.2 × 2.5 × 1.2

Yes

Murata

TDK

1000 nH, 4.1 A Max, 125 °C 3.2 x 2.5 x 2.0

-

470 nH, 5.3 A Max, 150 °C

470 nH, 4.9 A Max, 150 °C

470 nH, 4.5 A Max, 150 °C

220 nH, 7.6 A Max, 150 °C

220 nH, 5 A Max, 150 °C

240 nH, 4.2 A Max, 150 °C

3.2 × 2.5 × 1.2

2.5 x 2.0 x 1.2

2.5 × 2.0 × 1.2

3.2 x 2.5 x 1.2

2.0 x 1.6 x 1.2

Yes

TDK

-

Murata

TDK

-

TFM322512ALMAR22MTAA

TFM201610ALMAR24MTAA

DFE2MCAHR24MJ0

Yes

TDK

-

Murata

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11.2.1.2.7 LDO Input Capacitors

All LDO inputs require an input decoupling capacitor to minimize input ripple voltage. Using a 2.2-µF capacitor

for each LDO is recommended. Depending on the input voltage of the LDO, a 6.3-V, 10-V, or 16-V capacitor

can be used. For optimal performance, the input capacitors should be placed as close to the LDO input pins

as possible. See the Section 11.4 for more information about component placement. See Table 11-9 for the

recommended input capacitors.

Table 11-9. Recommended LDO Input Capacitors⁽¹⁾

MANUFACTURER

TDK

PART NUMBER

VALUE

EIA size code

SIZE (mm)

1.6 x 0.8

Used for Validation

CGA3E1X7S1C225M080AC

GCM188R70J225KE22

2.2 µF, 16 V, X7S

2.2 µF, 16 V, X7R

0603

Yes

-

Murata

0603

(1) Component minimum and maximum tolerance values are specified in the electrical parameters section of each IP.

11.2.1.2.8 LDO Output Capacitors

All LDO outputs require an output capacitor to hold up the output voltage during a load step or changes to the

input voltage. Using a 2.2-µF capacitor for each LDO output is recommended. Note: this requirement excludes

any capacitance seen at the load and only refers to the capacitance seen close to the device. Additional

capacitance placed near the load can be supported, but the end application or system should be evaluated

for stability. See Table 11-10 for the specific part number of the recommended output capacitors. For BOM

optimization purposes, the same capacitor part number was used for LDO input and LDO output.

Table 11-10. Recommended LDO Output Capacitors

MANUFACTURER

TDK

PART NUMBER

VALUE

EIA size code

SIZE (mm)

1.6 × 0.8

Used for Validation

CGA3E1X7S1C225M080AC

GCM188R70J225KE22

2.2 µF, 16 V, X7S

2.2 µF, 16 V, X7R

0603

Yes

—

Murata

0603

11.2.1.2.9 Digital Signal Connections

A detailed description of the application of each pin will go here. The VIO_IN pin may be optionally bypassed

with a 0.47 µF bypass capacitor close to the pin.

Table 11-11. Recommended VIO_IN Capacitor

EIA size

code

Component

MANUFACTURER

PART NUMBER

VALUE

SIZE (mm)

Used for Validation

Capacitor

Murata

TDK

GCM155C71A474KE36

0.47 µF, 10 V, X7S 0402

1.0 x 0.5

Yes

-

CGA2B3X7S1A474K050BB

I²C pull-up resistor values for example.

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11.2.2 Application Curves

100

80

60

40

20

0

80

60

40

20

0

V_{PVIN_Bn}= 3.3 V, FPWM mode

V_{PVIN_Bn}= 3.3 V, Auto mode

V_{PVIN_Bn}= 5 V, FPWM mode

V_{PVIN_Bn}= 5 V, Auto mode

F_sw= 2.2 MHz, FPWM mode

F_sw= 2.2 MHz, Auto mode

F_sw= 4.4 MHz, FPWM mode

F_sw= 4.4 MHz, Auto mode

0.01

0.05 0.1

0.5

1

5

10 20

0.01

0.05 0.1

0.5

1

5

10 20

I_{OUT_Bn}(A)

V_{VOUT_Bn}= 1.8 V

Fsw = 2.2 MHz

4-Phase

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1.8 V

4-Phase

Figure 11-4. BUCK Efficiency at 3.3 V or 5 V Input Voltage

Figure 11-5. BUCK Efficiency with Fsw = 2.2 MHz or 4.4 MHz

95

90

85

90

85

80

F_sw= 2.2 MHz, 1 Phase

F_sw= 2.2 MHz, 2 Phase

F_sw= 2.2 MHz, 3 Phase

F_sw= 2.2 MHz, 4 Phase

F_sw= 4.4 MHz, 1 Phase

F_sw= 2.2 MHz, 3 Phase

F_sw= 2.2 MHz, 4 Phase

F_sw= 4.4 MHz, 1 Phase

75

F_sw= 4.4 MHz, 2 Phase

F_sw= 4.4 MHz, 3 Phase

F_sw= 4.4 MHz, 4 Phase

F_sw= 4.4 MHz, 2 Phase

F_sw= 4.4 MHz, 3 Phase

F_sw= 4.4 MHz, 4 Phase

70

65

70

65

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

I_{OUT_Bn}(A)

Data valid for all bucks up to I_{OUT_Bn}

V_{PVIN_Bn}= 3.3 V Buck VSET = 1.8 V

Data valid for all bucks up to I_{OUT_Bn}

V_{PVIN_Bn}= 3.3 V Buck VSET = 1.8 V

Auto Mode

Figure 11-6. BUCK Efficiency in Varied Phase Configuration, 3.3 Figure 11-7. BUCK Efficiency in Varied Phase Configuration, 5 V

V Input Input

100

80

60

40

20

0

100

80

60

40

20

0

V_{OUT_Bn}= 0.8 V, F_sw= 4.4 MHz

V_{OUT_Bn}= 0.8 V, F_sw= 2.2 MHz

V_{OUT_Bn}= 1.2 V, F_sw= 4.4 MHz

V_{OUT_Bn}= 1.2 V, F_sw= 2.2 MHz

V_{OUT_Bn}= 1.8 V, F_sw= 4.4 MHz

V_{OUT_Bn}= 1.8 V, F_sw= 2.2 MHz

V_{OUT_Bn}= 0.8 V, F_sw= 2.2 MHz

V_{OUT_Bn}= 1.2 V, F_sw= 4.4 MHz

V_{OUT_Bn}= 1.2 V, F_sw= 2.2 MHz

V_{OUT_Bn}= 1.8 V, F_sw= 4.4 MHz

V_{OUT_Bn}= 1.8 V, F_sw= 2.2 MHz

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

I_{OUT_Bn}(A)

Data valid for all bucks up to I_{OUT_Bn}

V_{PVIN_Bn}= 3.3 V Single-Phase

Data valid for all bucks up to I_{OUT_Bn}

V_{PVIN_Bn}= 5 V Single-Phase

Forced-PWM Mode

Figure 11-8. BUCK Efficiency with different VOUT_Bn, 3.3 V

Input

Figure 11-9. BUCK Efficiency with different VOUT_Bn, 5 V Input

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11.2.2 Application Curves (continued)

90

100

80

60

40

20

0

-40^oC

25^oC

85^oC

125^oC

85

80

75

70

65

-40^oC

25^oC

85^oC

125^oC

0

0.5

1

1.5

2

2.5

3

3.5

4

0

0.5

1

1.5

2

2.5

3

3.5

4

I_{OUT_Bn}(A)

Data valid for all bucks up to I_{OUT_Bn}

V_{PVIN_Bn}= 3.3 V Buck VSET = 1 V

Data valid for all bucks up to I_{OUT_Bn}

V_{PVIN_Bn}= 3.3 V Buck VSET = 1 V

Single-Phase

Figure 11-10. BUCK Efficiency at different T_A, Auto Mode

Figure 11-11. BUCK Efficiency at different T_A, Forced-PWM

Mode

1.01

1 Phase

2 Phase

3 Phase

4 Phase

2 Phase

3 Phase

4 Phase

1.0075

1.005

1.0025

1

1.0075

1.005

1.0025

1

0.9975

0.995

0.9925

0.99

0.9975

0.995

0.9925

0.99

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-12. Buck Temperature Drift, Auto Mode, Fsw = 2.2

MHz

Figure 11-13. Buck Temperature Drift, Auto Mode, Fsw = 4.4

MHz

1.01

1 Phase

2 Phase

3 Phase

4 Phase

2 Phase

3 Phase

4 Phase

1.0075

1.005

1.0025

1

1.0075

1.005

1.0025

1

0.9975

0.995

0.9925

0.99

0.9975

0.995

0.9925

0.99

-40

-20

0

20

40

60

80

100 120 140

-40

-20

0

20

40

60

80

100 120 140

Temperature (°C)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-14. Buck Temperature Drift, Forced-PWM Mode, Fsw = Figure 11-15. Buck Temperature Drift, Forced-PWM Mode, Fsw =

2.2 MHz

4.4 MHz

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11.2.2 Application Curves (continued)

1.01

1.008

1.006

1.004

1.002

1

F_sw= 2.2 MHz, FPWM mode

F_sw= 2.2 MHz, Auto mode

F_sw= 4.4 MHz, FPWM mode

F_sw= 4.4 MHz, Auto mode

1.008

1.006

1.004

1.002

1

F_sw= 2.2 MHz, Auto mode

F_sw= 4.4 MHz, FPWM mode

F_sw= 4.4 MHz, Auto mode

0.998

0.996

0.994

0.992

0.99

0.998

0.996

0.994

0.992

0.99

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

I_{OUT_Bn}(A)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

4-Phase

V_{PVIN_Bn}= 5 V

Buck VSET = 1 V

4-Phase

Figure 11-16. Buck Load Regulation with 3.3 V Input

Figure 11-17. Buck Load Regulation with 5 V Input

1.01

1 Phase

1.008

1.006

1.004

1.002

1

1.008

1.006

1.004

1.002

1

2 Phase

3 Phase

4 Phase

2 Phase

3 Phase

4 Phase

0.998

0.996

0.994

0.992

0.99

0.998

0.996

0.994

0.992

0.99

0

2

4

6

8

10

12

14

0

2

4

6

8

10

12

14

I_{OUT_Bn}(A)

Data valid for all bucks up to I_{OUT_Bn}

V_{PVIN_Bn}= 3.3 V Buck VSET = 1 V

Data valid for all bucks up to I_{OUT_Bn}

V_{PVIN_Bn}= 3.3 V Buck VSET = 1 V

Auto Mode

Figure 11-18. Buck Load Regulation, with Fsw = 2.2 MHz

Figure 11-19. Buck Load Regulation, with Fsw = 4.4 MHz

1.01

1 Phase

1.008

1.006

1.004

1.002

1

1.008

1.006

1.004

1.002

1

2 Phase

3 Phase

4 Phase

2 Phase

3 Phase

4 Phase

0.998

0.996

0.994

0.992

0.99

0.998

0.996

0.994

0.992

0.99

3

3.25 3.5 3.75

4

4.25 4.5 4.75

5

5.25 5.5

3

3.25 3.5 3.75

4

4.25 4.5 4.75

5

5.25 5.5

V_{PVIN_Bn}(V)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Auto Mode

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Auto Mode

Figure 11-20. Buck Line Regulation, with Fsw = 2.2 MHz

Figure 11-21. Buck Line Regulation, with Fsw = 4.4 MHz

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11.2.2 Application Curves (continued)

V_{VOUT_Bn}(10mV/div)

V_{SW_Bn}(2V/div)

Time (200ns/div)

Time (40µs/div)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 10 mA

Figure 11-23. Buck Output Ripple - Single Phase, Fsw = 2.2

MHz, Forced-PWM Mode

Figure 11-22. Buck Output Ripple - Single Phase, Auto Mode

V_{VOUT_Bn}(10mV/div)

V_{SW_Bn}(2V/div)

Time (200ns/div)

Time (40µs/div)

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

V_{PVIN_Bn}= 3.3 V

I_LOAD= 10 mA

Figure 11-24. Buck Output Ripple - Single Phase, Fsw = 4.4

MHz, Forced-PWM Mode

Figure 11-25. Buck Output Ripple - 2-Phase, Auto Mode

V_{VOUT_Bn}(10mV/div)

V_{SW_Bn}(2V/div)

Time (200ns/div)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

Figure 11-27. Buck Output Ripple - 2-Phase, Fsw = 4.4 MHz,

Forced-PWM Mode

Figure 11-26. Buck Output Ripple - 2-Phase, Fsw = 2.2 MHz,

Forced-PWM Mode

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11.2.2 Application Curves (continued)

V_{VOUT_Bn}(10mV/div)

V_{VOUT_Bn}(5mV/div)

V_{SW_Bn}(2V/div)

Time (200ns/div)

Time (40µs/div)

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

V_{PVIN_Bn}= 3.3 V

I_LOAD= 10 mA

Figure 11-29. Buck Output Ripple - 3-Phase, Fsw = 2.2 MHz,

Forced-PWM Mode

Figure 11-28. Buck Output Ripple - 3-Phase, Auto Mode

V_{VOUT_Bn}(5mV/div)

V_{VOUT_Bn}(10mV/div)

V_{SW_Bn}(2V/div)

Time (40µs/div)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 10 mA

Time (200ns/div)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

Figure 11-31. Buck Output Ripple - 4-Phase, Auto Mode

Figure 11-30. Buck Output Ripple - 3-Phase, Fsw = 4.4 MHz,

Forced-PWM Mode

V_{VOUT_Bn}(10mV/div)

V_{SW_Bn}(2V/div)

Time (200ns/div)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

Figure 11-33. Buck Output Ripple - 4-Phase, Fsw = 4.4 MHz,

Forced-PWM Mode

Figure 11-32. Buck Output Ripple - 4-Phase, Fsw = 2.2 MHz,

Forced-PWM Mode

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11.2.2 Application Curves (continued)

V_{VOUT_Bn}(10mV/div)

V_{SW_Bn}(2V/div)

Time (2µs/div)

Buck VSET = 1 V

Time (2µs/div)

V_{PVIN_Bn}= 3.3 V

I_LOAD= 200 mA

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

Figure 11-34. Buck Transient from PWM mode to PFM mode, 2.2

Mhz, Single Phase

Figure 11-35. Buck Transient from PWM mode to PFM mode, 4.4

Mhz, Single Phase

V_{VOUT_Bn}(10mV/div)

V_{SW_Bn}(2V/div)

Time (2µs/div)

V_{SW_Bn}(2V/div)

Time (2µs/div)

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

I_LOAD= 200 mA

Figure 11-36. Buck Transient from PFM mode to PWM mode, 2.2 Figure 11-37. Buck Transient from PFM mode to PWM mode, 4.4

Mhz, Single Phase

V_{VOUT_Bn}(20mV/div)

I_LOAD(2A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 7 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-38. Buck Load Step Transient - 4-Phase, 2.2 MHz,

Auto Mode

Figure 11-39. Buck Load Step Transient - 4-Phase, 4.4 MHz,

Auto Mode

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11.2.2 Application Curves (continued)

V_{VOUT_Bn}(20mV/div)

I_LOAD(2A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 7 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-40. Buck Load Step Transient - 4-Phase, 2.2 MHz,

Forced-PWM Mode

Figure 11-41. Buck Load Step Transient - 4-Phase, 4.4 MHz,

Forced-PWM Mode

V_{VOUT_Bn}(20mV/div)

I_LOAD(2A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 5.25 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-42. Buck Load Step Transient - 3-Phase, 2.2 MHz,

Auto Mode

Figure 11-43. Buck Load Step Transient - 3-Phase, 4.4 MHz,

Auto Mode

V_{VOUT_Bn}(20mV/div)

I_LOAD(2A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 5.25 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-45. Buck Load Step Transient - 3-Phase, 4.4 MHz,

Forced-PWM Mode

Figure 11-44. Buck Load Step Transient - 3-Phase, 2.2 MHz,

Forced-PWM Mode

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11.2.2 Application Curves (continued)

V_{VOUT_Bn}(20mV/div)

I_LOAD(1A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 3.5 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-46. Buck Load Step Transient - 2-Phase, 2.2 MHz,

Auto Mode

Figure 11-47. Buck Load Step Transient - 2-Phase, 4.4 MHz,

Auto Mode

V_{VOUT_Bn}(20mV/div)

I_LOAD(1A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 3.5 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-49. Buck Load Step Transient - 2-Phase, 4.4 MHz,

Forced-PWM Mode

Figure 11-48. Buck Load Step Transient - 2-Phase, 2.2 MHz,

Forced-PWM Mode

V_{VOUT_Bn}(20mV/div)

I_LOAD(1A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 2 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-51. Buck Load Step Transient - Buck4, 4.4 MHz, Auto

Mode

Figure 11-50. Buck Load Step Transient - Buck4, 2.2 MHz, Auto

Mode

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11.2.2 Application Curves (continued)

V_{VOUT_Bn}(20mV/div)

I_LOAD(1A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 2 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V Buck VSET = 1 V

I_LOAD= 0.1 A → 2 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-53. Buck Load Step Transient - Buck4, 4.4 MHz,

Forced-PWM Mode

Figure 11-52. Buck Load Step Transient - Buck4, 2.2 MHz,

Forced-PWM Mode

V_{VOUT_Bn}(20mV/div)

I_LOAD(0.4A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 1 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-54. Buck Load Step Transient - Buck5, 2.2 MHz, Auto

Mode

Figure 11-55. Buck Load Step Transient - Buck5, 4.4 MHz, Auto

Mode

V_{VOUT_Bn}(20mV/div)

I_LOAD(0.4A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 1 A → 0.1 A, T_R= T_F= 1 μs

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

V_{PVIN_Bn}= 3.3 V

Buck VSET = 1 V

Figure 11-56. Buck Load Step Transient - Buck5, 2.2 MHz,

Forced-PWM Mode

Figure 11-57. Buck Load Step Transient - Buck5, 4.4 MHz,

Forced-PWM Mode

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11.2.2 Application Curves (continued)

1.81

3.005

3.004

3.003

3.002

3.001

3

V_IN(LDOn)= 3.3 V

V_IN(LDOn)= 5 V

V_IN(LDOn)= 3.3 V

V_IN(LDOn)= 5 V

1.808

1.806

1.804

1.802

1.8

1.798

1.796

1.794

1.792

1.79

2.999

2.998

2.997

2.996

2.995

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Load (A)

0

0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

Load (A)

V_IN(LDOn)= 3.3 V

Figure 11-58. GPLDO Load Regulation, Vout = 1.8 V

Figure 11-59. GPLDO Load Regulation, Vout = 3 V

0.808

1.82

T_A= -40^oC

T_A= 0^oC

0.806

0.804

0.802

1.815

1.81

1.805

T_A= 20^oC

T_A= 80^oC

T_A= 125^oC

0.8

0.798

0.796

0.794

0.792

1.8

1.795

1.79

1.785

1.78

1.2

1.5

1.8

2.1

V_IN(LDOn)(V)

2.4

2.7

3

3.3

3.6

2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

V_IN(LDOn)(V)

3

3.1 3.2 3.3

I_OUT(LDOn)= 500 mA

I_OUT(LDOn)= 50 mA

Figure 11-60. GPLDO Line Regulation over Temeprature, Vout = Figure 11-61. GPLDO Line Regulation over Temeprature, Vout =

0.8 V 1.8 V

3.4

3.2

3

3.4

3.2

3

2.8

2.6

2.4

2.2

2

2.8

2.6

2.4

2.2

2

1.8

1.6

1.8

1.6

0

0.5

1

1.5

2

2.5

Time (ms)

3

3.5

4

4.5

5

0

0.5

1

1.5

2

2.5

Time (ms)

3

3.5

4

4.5

5

V_IN(LDOn)= 3.3 V

I_OUT(LDOn)= 50 mA

V_IN(LDOn)= 3.3 V

I_OUT(LDOn)= 50 mA

Figure 11-62. GPLDO Transition from 3.3 V in Bypass Mode to Figure 11-63. GPLDO Transition from 1.8 V in Linear Mode to 3.3

1.8 V Linear Mode

V in Bypass Mode

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11.2.2 Application Curves (continued)

1.81

1.808

1.806

1.804

1.802

1.8

V_IN(LDOn)= 3.3 V

V_IN(LDOn)= 5 V

V_{VOUT_Bn}(20mV/div)

1.798

1.796

1.794

1.792

1.79

I_LOAD(0.2A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 0.4 A → 0.1 A, T_R= T_F= 1 μs

0

0.05

0.1

0.15

Load (A)

0.2

0.25

0.3

V_IN(LDOn)= 3.3 V

LDO VSET = 1 V

V_IN(LDOn)= 3.3 V

Figure 11-64. GPLDO Load Step Transient

Figure 11-65. LNLDO Load Regulation, Vout = 1.8 V

1.82

3.005

3.004

3.003

3.002

3.001

3

T_A= -40^oC

V_IN(LDOn)= 3.3 V

V_IN(LDOn)= 5 V

T_A= 0^oC

1.815

1.81

1.805

T_A= 20^oC

T_A= 80^oC

T_A= 125^oC

1.8

1.795

1.79

2.999

2.998

2.997

2.996

2.995

1.785

1.78

2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9

V_IN(LDOn)(V)

3

3.1 3.2 3.3

0

0.05

0.1

0.15

Load (A)

0.2

0.25

0.3

V_IN(LDOn)= 3.3 V

I_OUT(LDOn)= 300 mA

Figure 11-66. LNLDO Load Regulation, Vout = 3 V

Figure 11-67. LNLDO Line Regulation over Temeprature, Vout =

1.8 V

V_{VOUT_Bn}(20mV/div)

I_LOAD(0.2A/div)

Time (20µs/div)

I_LOAD= 0.1 A → 0.4 A → 0.1 A, T_R= T_F= 1 μs

V_IN(LDOn)= 3.3 V

LDO VSET = 1 V

Figure 11-68. LNLDO Load Step Transient

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11.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range from 3.0 V and 5.5 V. This input supply

must be well regulated and can withstand maximum input current and keep a stable voltage without voltage drop

even at load transition condition. The resistance of the input supply rail must be low enough that the input current

transient does not cause too high drop in the device supply voltage that can cause false UVLO fault triggering. If

the input supply is located more than a few inches from the device, additional bulk capacitance may be required

in addition to the ceramic bypass capacitors.

11.4 Layout

11.4.1 Layout Guidelines

The high frequency and large switching currents of the TPS6594-Q1 device make the choice of layout important.

Good power supply results only occur when care is given to correct design and layout. Layout affects noise

pickup and generation and can cause a good design to perform with less-than-expected results.

With a range of buck output currents from milliamps to 10 A and over, good power supply layout is much more

difficult than most general PCB design. Use the following steps as a reference to ensure the buck regulators

are stable and maintain correct voltage and current regulation across its intended operating voltage and current

range.

1. Place C_INas close as possible to the PVIN_Bx pin and the PGND/Thermal Pad. Route the V_INtrace wide

and thick to avoid IR drops. The DCR of the trace from the source to the pin should be less than 2 mΩ. The

trace between the positive node of the input capacitor and the PVIN_Bx pins of the device, as well as the

trace between the negative node of the input capacitor and PGND/Thermal Pad, must be kept as short as

possible. The input capacitance provides a low-impedance voltage source for the switching converter. The

inductance of the connection is the most important parameter of a local decoupling capacitor — parasitic

inductance on these traces must be kept as small as possible for correct device operation. The parasitic

inductance can be reduced by using a ground plane as close as possible to top layer by using thin dielectric

layer between top layer and ground plane.

2. The output filter, consisting of C_OUTand L, converts the switching signal at SW_Bx to the noiseless output

voltage. It must be placed as close as possible to the device keeping the switch node small, for best EMI

behavior. Note that the PVIN_Bx pin is directly adjacent to the SW_Bx pin. The inductor and capacitor

placement should be made as close as possible without compromising PVIN_Bx. Route the traces between

the output capacitors of the device and the load direct and wide to avoid losses due to the IR drop.

3. Input for analog blocks (VCCA and REFGND1/2) must be isolated from noisy signals. Connect VCCA

directly to a quiet system voltage node and REFGND1/2 to a quiet ground point where no IR drop occurs.

Place the decoupling capacitor as close as possible to the VCCA pin.

4. If the processor load supports remote voltage sensing, connect the feedback pins FB_Bx of the device

to the respective sense pins on the processor. If the processor does not support remote voltage sensing,

then connect the FB_Bx pin to a representative load capacitor. With differential feedback, also connect the

negative feedback pin to the negative terminal of the same load capacitor. The minimum recommended

trace width is 6 mils. The sense lines are susceptible to noise. They must be kept away from noisy signals

such as PGND, PVIN_Bx, and SW_Bx, as well as high bandwidth signals such as the I²C. Avoid capacitive

and inductive coupling by keeping the sense lines short, direct, and close to each other. Run the lines in a

quiet layer. Isolate them from noisy signals by a voltage or ground plane if possible. Running the signal as a

differential pair is recommended. If series resistors are used for load current measurement, place them after

connection of the voltage feedback.

5. PGND, PVIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers,

which are not able to withstand interference from noisy PGND, PVIN_Bx and SW_Bx.

The feedback is internal so keep PCB resistance between LDO output and target load in the range of the

acceptable voltage drop for LDOs. Similar to the buck regulators, the PVIN_LDOx input capacitor should placed

as close as possible to the PMIC. The impedance from the source ot the PVIN_LDOx pin should be low and the

DCR less than 2 mΩ. The output capacitor on VOUT_LDOx should be as close to the PMIC as possible.

A more complete complete list of layout recommendations can be found in the Schematic & PCB Checklist.

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Due to the overall small solution size, the thermal performance of the PCB layout is important. Many system-

dependent parameters, such as thermal coupling, airflow, added heat sinks and convection surfaces, and the

presence of other heat-generating components affect the power dissipation limits of a given component. Proper

PCB layout, focusing on thermal performance, results in lower die temperatures. Wide and thick power traces

come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB designs with

vias to different planes. This results in reduced junction-to-ambient (R_θJA) and junction-to-board (R_θJB) thermal

resistances and thereby reduces the device junction temperature, T_J. TI strongly recommends to perform a

careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process, by using a

thermal modeling analysis software.

11.4.2 Layout Example

Figure 11-69. Example PMIC Layout

This example shows a top and bottom layout of the key power components and the crystal oscillator based on

the EVM. Most of the digital routing is neglected in this image, see the EVM design files for full details. The

highest priority should be on the buck input capacitors, followed by the inductors. Ensure that there are sufficient

vias for high current pathways.

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12 Device and Documentation Support

12.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Device Support

12.2.1 Device Nomenclature

The following acronyms and terms are used in this data sheet. For a detailed list of terms, acronyms, and

definitions, see the TI glossary.

ADC

APE

AVS

DVS

GPIO

LDO

PM

Analog-to-digital converter

Application processor engine

Adaptive voltage scaling

Dynamic voltage scaling

General-purpose input and output

Low-dropout voltage linear regulator

Power management

PMIC

PSRR

RTC

NA

Power-management integrated circuit

Power supply rejection ratio

Real-time clock

Not applicable

NVM

ESR

PMU

PFM

PWM

SPI

Non-volatile memory

Equivalent series resistance

Power management unit

Pulse frequency

Pulse width modulation

Serial peripheral interface

Embedded power controller

First supply detection

EPC

FSD

12.3 Documentation Support

12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

12.5 Support Resources

TI E2E^™support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.6 Trademarks

TI E2E^™is a trademark of Texas Instruments.

All trademarks are the property of their respective owners.

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12.7 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.8 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OUTLINE

RWE0056C

VQFNP - 0.9 mm max height

SCALE 2.000

PLASTIC QUAD FLATPACK - NO LEAD

8.1

7.9

A

B

0.05

0.00

(0.1)

PIN 1 ID

DETAIL A

TYPICAL

8.1

7.9

D

E

T

A

I

L

A

S

C

A

L

E

2

0

.

0

(

7.75)

(0.15)

0.15 0.1

D

E

T

A

I

L

B

S

C

A

L

E

2

0

.

0

DETAIL B

TYPICAL

0.9

12 MAX

0.8

C

SEATING PLANE

0.08 C

(0.2)

SEE DETAIL A

SEE DETAIL B

4X

45 X 0.6 MAX

15

28

14

29

SYMM

4X

57

5.5 0.05

6.5

1

42

0.3

56X

52X 0.5

56

43

0.2

SYMM

0.1

0.05

C B A

C

PIN 1 ID

OPTIONAL

0.5

0.3

56X

4224586/A 10/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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TPS6594-Q1

SLVSEA7A – DECEMBER 2019 – REVISED APRIL 2021

www.ti.com

EXAMPLE BOARD LAYOUT

RWE0056C

VQFNP - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.5)

SYMM

56X (0.6)

56X (0.25)

56

43

1

42

52X (0.5)

(7.8)

SYMM

57

(1.32) TYP

(R0.05)

TYP

(2.5)

TYP

(

0.2) TYP

VIA

29

14

15

28

(1.32)

TYP

(2.5)

TYP

(7.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4224586/A 10/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

www.ti.com

Submit Document Feedback 375

Product Folder Links: TPS6594-Q1

TPS6594-Q1

SLVSEA7A – DECEMBER 2019 – REVISED APRIL 2021

www.ti.com

EXAMPLE STENCIL DESIGN

RWE0056C

VQFNP - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(7.8)

(0.66) TYP

(1.32)

TYP

43

56

56X (0.6)

56X (0.25)

1

42

52X (0.5)

(1.32) TYP

(0.66) TYP

SYMM

57

(7.8)

METAL

TYP

16X

1.12)

(

(R0.05) TYP

14

29

15

28

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 57:

66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4224586/A 10/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

376 Submit Document Feedback

Product Folder Links: TPS6594-Q1

GENERIC PACKAGE VIEW

RWE 56

8 x 8, 0.5 mm pitch

VQFNP - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224587/A

www.ti.com

PACKAGE OUTLINE

RWE0056C

VQFNP - 0.9 mm max height

SCALE 2.000

PLASTIC QUAD FLATPACK - NO LEAD

8.1

7.9

A

B

0.05

0.00

(0.1)

PIN 1 ID

DETAIL A

8.1

7.9

DETAIL

SCALE 20.000

A

TYPICAL

(

7.75)

(0.15)

0.15 0.1

DETAIL

B

S

C

A

L

E

2

0

.

0

DETAIL B

TYPICAL

0.9

0.8

12 MAX

C

SEATING PLANE

0.08 C

(0.2)

(R0.2)

SEE DETAIL A

SEE DETAIL B

4X

45 X 0.6 MAX

15

28

14

PIN 1 ID

29

OPTIONAL

SYMM

57

4X

5.5 0.05

6.5

1

42

0.3

0.2

52X 0.5

56X

56

43

SYMM

0.1

0.05

C B A

C

PIN 1 ID

OPTIONAL

0.5

0.3

56X

4224586/B 03/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RWE0056C

VQFNP - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

5.5)

SYMM

56X (0.6)

56X (0.25)

56

43

1

42

52X (0.5)

(7.8)

SYMM

57

(1.32) TYP

(R0.05)

(2.5)

TYP

(

0.2) TYP

VIA

29

14

15

28

(1.32)

TYP

(2.5)

TYP

(7.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:10X

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4224586/B 03/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RWE0056C

VQFNP - 0.9 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(7.8)

(0.66) TYP

(1.32)

TYP

43

56

56X (0.6)

56X (0.25)

1

42

52X (0.5)

(1.32) TYP

(0.66) TYP

SYMM

57

(7.8)

METAL

TYP

16X

1.12)

(

(R0.05) TYP

14

29

15

28

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 57:

66% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:12X

4224586/B 03/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, regulatory or other requirements.

These resources are subject to change without notice. TI grants you permission to use these resources only for development of an

application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license

is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you

will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these

resources.

TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with

such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for

TI products.

TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TPS65940400RWERQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有五个降压稳压器和四个低压降稳压器的汽车类 2.8V 至 5.5V PMIC \| RWE \| 56 \| -40 to 125 集成电源管理电路稳压器
文件：	总383页 (文件大小：9699K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS65940400RWERQ1 [TI]

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