TPS70345MPWPREP_技术文档

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

D

Controlled Baseline

− One Assembly/Test Site, One Fabrication

Site

D

Open Drain Power Good for Regulator 1

Ultralow 185 µA (typ) Quiescent Current

2 µA Input Current During Standby

D

Extended Temperature Performance of

−55°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Low Noise: 78 µV

Capacitor

Without Bypass

RMS

D

Quick Output Capacitor Discharge Feature

Two Manual Reset Inputs

Enhanced Product-Change Notification

2% Accuracy Over Load and Temperature

Undervoltage Lockout (UVLO) Feature

24-Pin PowerPAD TSSOP Package

Thermal Shutdown Protection

†

Qualification Pedigree

Dual Output Voltages for Split-Supply

Applications

D

Selectable Power Up Sequencing for DSP

Applications (See TPS704xx for

Independent Enabling of Each Output)

†

Component qualification in accordance with JEDEC and industry

standards to ensure reliable operation over an extended

temperature range. This includes, but is not limited to, Highly

Accelerated Stress Test (HAST) or biased 85/85, temperature

cycle, autoclave or unbiased HAST, electromigration, bond

intermetallic life, and mold compound life. Such qualification

testing should not be viewed as justifying use of this component

beyond specified performance and environmental limits.

D

Output Current Range of 1 A on

Regulator 1 and 2 A on Regulator 2

Fast Transient Response

Output Voltages of 3.3−V/1.2−V

Open Drain Power-On Reset With 120-ms

Delay

PWP PACKAGE

(TOP VIEW)

description

1

24

23

22

21

20

19

18

17

16

15

14

13

GND/HEATSINK

2

V

IN1

OUT1

The TPS70345 is designed to provide a complete

3

OUT1

power management solution for Texas

Instruments DSP, processor power, ASIC, FPGA,

and digital applications where dual output voltage

regulators are required. Easy programmability of

the sequencing function makes this family ideal

for any Texas Instruments DSP applications with

power sequencing requirement. Differentiated

features, such as accuracy, fast transient

response, SVS supervisory circuit (power on

reset), manual reset inputs, and enable function,

provide a complete system solution.

4

NC

MR2

MR1

EN

SEQ

GND

/FB1

SENSE1

5

NC

6

PG1

RESET

NC

7

8

9

V

/FB2

SENSE2

OUT2

10

11

12

V

IN2

OUT2

GND/HEATSINK

NC − No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

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Copyright  2006, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

description (continued)

TPS70345 PWP

DSP

3.3 V

I/O

V

OUT1

5 V

V

IN1

IN2

22 µF

0.22 µF

V

SENSE1

250 kΩ

PG1

MR2

MR1

>2 V

V

250 kΩ

<0.7 V

0.22 µF

RESET

EN

<0.7 V

>2 V

MR1

EN

<0.7 V

V

SENSE2

1.2 V

SEQ

V

OUT2

Core

47 µF

The TPS70345 voltage regulator offers low dropout voltage and dual outputs with power up sequence control,

which is designed primarily for DSP applications. This device has a low noise output performance without using

any added filter bypass capacitors and are designed to have a fast transient response and be stable with

47 µF low ESR capacitors.

This device has a fixed output voltage 3.3 V/1.2 V. Regulator 1 can support up to 1 A, and regulator 2 can support

up to 2 A. Separate voltage inputs allow the designer to configure the source power.

Because the PMOS pass element behaves as a low-value resistor, the dropout voltage is very low (typically

160 mV on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass

element is a voltage-driven device, the quiescent current is low and independent of output loading (maximum

of 250 µA over the full range of output current). This LDO family also features a sleep mode; applying a high

signal to EN (enable) shuts down both regulators, reducing the input current to 1 µA at T = 25°C.

J

The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two

regulators are sensed at the V

and V

pins respectively.

SENSE1

SENSE2

The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is

enabled and the SEQ terminal is pulled high or left open, V

reaches approximately 83% of its regulated output voltage. At that time V

below 83% (i.e. overload condition) of its regulated voltage, V

turns on first and V

remains off until V

OUT2

OUT1 OUT2

is turned on. If V

is pulled

OUT1

OUT2

will be turned off. Pulling the SEQ terminal

OUT1

low reverses the power-up order and V

current source.

is turned on first. The SEQ pin is connected to an internal pullup

OUT1

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator

is turned off (disabled).

The PG1 pin reports the voltage conditions at V

reset) for the circuitry supplied by regulator 1.

. The PG1 pin can be used to implement a SVS (power on

OUT1

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

description (continued)

The TPS70345 features a RESET (SVS, POR, or power on reset). RESET is an active low, open drain output

and requires a pullup resistor for normal operation. When pulled up, RESET goes to a high impedance state

(i.e. logic high) after a 120 ms delay when all three of the following conditions are met. First, V

the undervoltage condition. Second, the manual reset (MR) pin must be in a high impedance state. Third, V

must be above

IN1

OUT2

must be above approximately 95% of its regulated voltage. To monitor V

, the PG1 output pin can be

OUT1

connected to MR1 or MR2. RESET can be used to drive power on reset or a low-battery indicator. If RESET

is not used, it can be left floating.

Internal bias voltages are powered by V

undervoltage lockout circuit that prevents each output from turning on until the respective input reaches 2.5 V.

and require 2.7 V for full functionality. Each regulator input has an

IN1

AVAILABLE OPTIONS

REGULATOR 1

(V)

REGULATOR 2

(V)

TSSOP

(PWP)

T

J

V

O

−55°C to 125°C

3.3 V

1.2 V

TPS70345MPWPREP

detailed block diagram − fixed voltage version

V

(2 Pins)

V

(2 Pins)

OUT1

IN1

Current

Sense

10 kΩ

UVLO1

SENSE1

Shutdown

ENA_1

2.5 V

(see Note A)

ENA_1

FB1

−

+

Reference

V

ref

GND

Thermal

Shutdown

V

ref

UVLO1

FB1

PG1

Rising Edge

Deglitch

0.95 × V

ref

V

IN1

MR2

Shutdown

RESET

FB2

Falling Edge

Delay

Rising Edge

Deglitch

UV Comp

0.95 × V

ref

FB2

Falling Edge

V

IN1

ENA_1

Deglitch

0.83 × V

ref

Power

Sequence

Logic

FB1

ENA_2

V

ref

MR1

Falling Edge

Deglitch

FB2

0.83 × V

ref

UV Comp

2.5 V

−

+

EN

ENA_2

V

IN1

UVLO2

V

SENSE2

(see Note A)

Current

Sense

SEQ

(see Note B)

10 kΩ

V

(2 Pins)

OUT2

V

(2 Pins)

IN2

NOTES: A. For most applications, V

SENSE1

and V

SENSE2

should be externally connected to V as close as possible to the device.

OUT

For other implementations, refer to SENSE terminal connection discussion in the Application Information section.

B. If the SEQ terminal is floating at the input, V powers up first.

OUT2

3

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

RESET timing diagram (with V

powered up and MR1 and MR2 at logic high)

IN1

V

IN2

V

RES

(see Note A)

t

V

OUT2

V

IT+

(see Note B)

V (see Note B)

IT+

Threshold

Voltage

V

IT−

(see Note B)

IT−

(see Note B)

t

RESET

Output

120 ms

Delay

120 ms

Delay

Output

Undefined

Output

Undefined

t

NOTES: A.

B.

V

is the minimum input voltage for a valid RESET. The symbol V is not currently listed within EIA or JEDEC standards

RES

for semiconductor symbology.

V

−Trip voltage is typically 5% lower than the output voltage (95%V ) V

IT−

to V is the hysteresis voltage.

IT+

IT

O

PG1 timing diagram

V

IN1

V

UVLO

V

UVLO

V

PG1

(see Note A)

t

V

IT+

(see Note B)

V

IT+

(see Note B)

V

OUT2

Threshold

Voltage

V

IT−

(see Note B)

IT−

(see Note B)

t

PG1

Output

Undefined

Output

Undefined

t

NOTES: A.

B.

V

is the minimum input voltage for a valid PG. The symbol V is not currently listed within EIA or JEDEC

PG

standards for semiconductor symbology.

V

−Trip voltage is typically 5% lower than the output voltage (95%V ) V

IT−

to V

is the hysteresis

IT+

IT

voltage.

O

4

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

7

EN

I

Active low enable

Regulator ground

Ground/heatsink

GND

9

GND/HEATSINK

1, 12, 13, 24

MR1

MR2

NC

6

I

Manual reset input 1, active low, pulled up internally

Manual reset input 2, active low, pulled up internally

No connection

5

4, 17, 20

PG1

RESET

SEQ

19

18

8

O

I

Open drain output, low when V

voltage is less than 95% of the nominal regulated voltage

Open drain output, SVS (power on reset) signal, active low

OUT1

Power up sequence control: SEQ=High, V

first, SEQ terminal pulled up internally.

powers up first; SEQ=Low, V powers up

OUT1

OUT2

V

2, 3

10, 11

22, 23

14, 15

16

I

Input voltage of regulator 1

IN1

Input voltage of regulator 2

IN2

O

I

Output voltage of regulator 1

Output voltage of regulator 2

Regulator 2 output voltage sense

Regulator 1 output voltage sense

OUT1

OUT2

SENSE2

SENSE1

21

I

detailed description

The TPS70345 low dropout regulator provides dual regulated output voltages for DSP applications that require

a high performance power management solution. These devices provide fast transient response and high

accuracy, while drawing low quiescent current. Programmable sequencing provides a power solution for DSPs

without any external component requirements. This reduces the component cost and board space while

increasing total system reliability. The TPS70345 has an enable feature which puts the device in sleep mode

reducing the input current to 1 µA. Other features are the integrated SVS (power on reset, RESET) and power

good (PG1). These monitor output voltages and provide logic output to the system. These differentiated features

provide a complete DSP power solution.

The TPS70345, unlike many other LDOs, features low quiescent current which remains virtually constant even

with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly

proportional to the load current through the regulator (I = I /β). The TPS70345 uses a PMOS transistor to pass

B

C

current. Because the gate of the PMOS is voltage driven, operating current is low and stable over the full load

range.

pin functions

enable

The EN terminal is an input which enables or shuts down the device. If EN is at a logic high signal the device

is in shutdown mode. When the EN goes to voltage low, then the device is enabled.

sequence

The SEQ terminal is an input that programs which output voltage (V

or V

) is turned on first. When the

OUT1

OUT2

device is enabled and the SEQ terminal is pulled high or left open, V

turns on first and V

remains off

OUT2

OUT1

until V

reaches approximately 83% of its regulated output voltage. If V

is pulled below 83% (i.e., over

.

IN1

OUT2

load condition) V

is turned off. This terminal has a 6-µA pullup current to V

OUT1

Pulling the SEQ terminal low reverses the power-up order and V

diagrams see Figure 26 through Figure 30.

is turned on first. For detailed timing

OUT1

5

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

detailed description (continued)

power good (PG1)

The PG1 terminal is an open drain, active high output terminal which indicates the status of the V

regulator.

OUT1

When the V

impedance state when V

drain output of the PG1 terminal requires a pullup resistor

reaches 95% of its regulated voltage, PG1 goes to a high impedance state. PG1 goes to a low

OUT1

is pulled below 95% (i.e., over load condition) of its regulated voltage. The open

OUT1

.

manual reset pins (MR1 and MR2)

MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled

to logic low, a POR (RESET) occurs. These terminals have a 6-µA pullup current to V . It is recommended

IN1

that these pins be pulled high to V when they are not used.

IN

sense (V

, V

)

SENSE1 SENSE2

The sense terminals of fixed-output options must be connected to the regulator output, and the connection

should be as short as possible. Internally, the sense terminals connect to high-impedance wide-bandwidth

amplifiers through resistor-divider networks and noise pickup feeds through to the regulator output. It is

essential to route the sense connections in such a way to minimize/avoid noise pickup. Adding RC networks

between the V

regulators to oscillate.

terminals and V

terminals to filter noise is not recommended because it can cause the

SENSE

OUT

RESET indicator

RESET is an active low, open drain output and requires a pullup resistor for normal operation. When pulled up,

RESET goes to a high impedance state (i.e. logic high) after a 120 ms delay when all three of the following

conditions are met. First, V

must be in a high impedance state. Third, V

must be above the undervoltage condition. Second, the manual reset (MR) pin

IN1

must be above approximately 95% of its regulated voltage.

OUT2

To monitor V

, the PG1 output pin can be connected to MR1 or MR2.

OUT1

V

and V

IN2

IN1

V

and V

are inputs to the regulators.

IN1

IN2

and V

OUT2

V

OUT1

V

and V

are output terminals of each regulator.

OUT1

OUT2

6

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ꢊꢋꢌ ꢍꢎꢏ ꢋꢀ ꢁꢋꢀ ꢍ ꢏ ꢐꢎꢊꢑꢏ ꢁꢏ ꢋꢀ ꢒꢏ ꢍꢀꢌꢓ ꢉ ꢑꢉ ꢓ ꢋꢍ ꢌꢀꢏ ꢑ

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

†

absolute maximum ratings over operating junction temperature (unless otherwise noted)

‡

Input voltage range : V

V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

IN1

IN2

Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V

Output voltage range (V

, V

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

OUT1 SENSE1

, V

OUT2 SENSE2

Maximum RESET, PG1 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Maximum MR1, MR2, and SEQ voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

IN1

Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 150°C

J

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV

†

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

All voltages are tied to network ground.

recommended operating conditions

MIN

2.7

0

MAX

6

UNIT

¶

Input voltage, V

V

A

I

Output current, I (regulator 1)

1

O

Output current, I (regulator 2)

O

0

2

A

Operating virtual junction temperature, T

−55

125

°C

.

J

¶

To calculate the minimum input voltage for maximum output current, use the following equation: V

= V

O(max)

+ V

DO(max load)

I(min)

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

electrical characteristics over recommended operating junction temperature (T = −55°C to 125°C)

J

V

or V = V

+ 1V, I

= 1 mA, EN = 0, C

= 22 µF, C

= 47 µF(unless otherwise

IN1

IN2

OUTX(nom)

OUTX

OUT1

OUT2

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

2.7 V < V < 6 V, FB connected to V

I

J

Reference

voltage

O

1.224

T = 25°C

Output voltage

(see Note 1 and

Note 3)

2.7 V < V < 6 V, FB connected to V

I

1.196

1.176

1.248

1.224

250

V

O

V

O

2.7 V < V < 6 V, T = 25°C

1.2

185

1.2 V Output

I

J

(V

OUT2

)

2.7 V < V < 6 V

I

See Note 3, T = 25°C

Quiescent current (GND current) for regulator 1 and

regulator 2, EN = 0 V, (see Note 1)

J

µA

See Note 3

V

+ 1 V < V ≤ 6 V, T = 25°C, See Note 1

0.01%

Output voltage line regulation (∆V /V )for regulator

1 and regulator 2 (see Note 2)

O

I

J

O

V

mV

A

+ 1 V < V ≤ 6 V, See Note 1

0.1%

O

I

Load regulation for V

and V

OUT2

T = 25°C, See Note 3

J

1

1.75

3.8

150

1

OUT1

Regulator 1

Regulator 2

2.35

4.8

Output current limit

V

O

= 0 V

Thermal shutdown junction temperature

°C

µA

EN = V , T = 25°C

2

I

J

I

Standby current

I(standby)

EN = V

10

RESET terminal

Minimum input voltage for valid RESET

Trip threshold voltage

I

= 300 µA, V

≤ 0.8 V

1

95%

0.5%

120

1.3

V

(RESET)

V

decreasing

92%

80

98%

V

O

Hysteresis voltage

Measured at V

O

RESET pulse duration

O

t

160

ms

µs

V

(RESET)

Rising edge deglitch

30

r(RESET)

Output low voltage

Leakage current

V = 3.5 V, I

= 1 mA

0.15

0.4

1

I

(RESET)

= 6 V

V

µA

(RESET)

PG terminal

Minimum input voltage for valid PG

Trip threshold voltage

Hysteresis voltage

I

= 300 µA, V

) ≤ 0.8 V

1.0

95%

0.5%

30

1.3

V

(PG)

decreasing

(PG1

V

92%

98%

V

O

Measured at V

O

t

Rising edge deglitch

V = 2.7 V, I = 1 mA

µs

V

r(PG1)

Output low voltage

Leakage current

0.15

0.4

1

I

(PG)

= 6 V

V

µA

(PG1)

EN terminal

High-level EN input voltage

Low-level EN input voltage

Input current (EN)

2

V

0.7

1

−1

µA

NOTES: 1. Minimum input operating voltage is 2.7 V or V

current is 1 mA.

+ 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output

O(typ)

2. If V < 1.8 V then V

Imax

= 6 V, V = 2.7 V:

Imin

O

_Oǒ_VImax_{* 2.7 V}Ǔ

V

ǒ

Ǔ

Line regulation (mV) + %ńV

1000

100

If V > 2.5 V then V

Imax

= 6 V, V

= V + 1 V:

O

Imin

^Oǒ_V

_) 1Ǔ

_*ǒ_VO

Imax

Ǔ

V

O

ǒ

Ǔ

Line regulation (mV) + %ńV

1000

100

3.

I

O

= 1 mA to 1 A for regulator 1 and 1 mA to 2 A for regulator 2.

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋꢌ ꢍꢎꢏ ꢋꢀ ꢁꢋꢀ ꢍ ꢏ ꢐꢎꢊꢑꢏ ꢁꢏ ꢋꢀ ꢒꢏ ꢍꢀꢌꢓ ꢉ ꢑꢉ ꢓ ꢋꢍ ꢌꢀꢏ ꢑ

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

electrical characteristics over recommended operating junction temperature (T = −55°C to 125°C)

J

V

or V

= V

+ 1V, I

= 1 mA, EN = 0, C

= 22 µF, C

= 47 µF(unless otherwise

IN1

IN2

OUTX(nom)

OUTX

OUT1

OUT2

noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SEQ TERMINAL

High-level SEQ input voltage

Low-level SEQ input voltage

SEQ pullup current source

MR1 / MR2 TERMINALS

2

V

0.7

6

µA

High-level input voltage

Low-level input voltage

Pullup current source

2

V

0.7

9.5

µA

V

OUT2

TERMINAL

V

UV comparator − positive-going input

80%

83%

86%

V

O

OUT2

V

threshold voltage of V

UV comparator

V

O

V

O

OUT1

V

UV comparator − hysteresis

3% V

mV

µs

OUT2

O

UV comparator − falling edge deglitch

V

decreasing below threshold

140

3

OUT2

SENSE2

Peak output current

2 ms pulse width

A

Discharge transistor current

V

OUT2

= 1.5 V

7.5

mA

V

OUT1

TERMINAL

V

UV comparator − positive-going input

80%

83%

86%

V

O

OUT1

V

threshold voltage of V

UV comparator

V

O

V

O

OUT1

V

UV comparator − hysteresis

3% V

mV

OUT1

O

UV comparator − falling edge deglitch

V

decreasing below threshold

140

160

µs

OUT1

SENSE1

I

= 1 A, V

= 3.2 V, T = 25°C

O

IN1

J

Dropout voltage (see Note 4)

mV

= 1 A, V

= 3.2 V

255

O

Peak output current

2 ms pulse width

= 1.5 V

1.2

7.5

A

Discharge transistor current

V

mA

OUT1

V / V TERMINAL

IN1 IN2

UVLO threshold

2.3

2.65

V

UVLO hysteresis

110

mV

NOTE 4: Input voltage(V

or V ) = V (Typ) − 100 mV. For the 1.5-V, 1.8-V and 2.5-V regulators, the dropout voltage is limited by input voltage

IN2 O

IN1

range. The 3.3 V regulator input voltage is set to 3.2 V to perform this test.

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

18

16

14

12

10

8

6

4

2

0

80

90

100

110

120

130

140

Continuous Tj (5C)

Figure 1. TPS70345-PWP-EP Estimated Device Life at Elevated

Temperature Wirebond Voiding Fail Modes

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

2 − 5

Output spectral noise density

vs Frequency

z

Output impedance

6 − 9

o

Load transient response

Line transient response

Output voltage and enable voltage

Equivalent series resistance

10, 11

12, 13

14, 15

16 − 20

V

O

vs Time (start-up)

vs Output current

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋꢌ ꢍꢎꢏ ꢋꢀ ꢁꢋꢀ ꢍ ꢏ ꢐꢎꢊꢑꢏ ꢁꢏ ꢋꢀ ꢒꢏ ꢍꢀꢌꢓ ꢉ ꢑꢉ ꢓ ꢋꢍ ꢌꢀꢏ ꢑ

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

TYPICAL CHARACTERISTICS

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

10

V

= 4.3 V

= 3.3 V

V

= 2.8 V

= 1.8 V

IN1

OUT1

IN2

OUT2

C

I

= 22 µF

= 10 mA

C

I

= 47 µF

= 10 mA

OUT1

OUT2

O

T

J

= 25°C

T

J

= 25°C

1

0.1

0.01

100

1 k

10 k

100 k

100

1 k

10 k

100 k

f − Frequency − Hz

Figure 2

Figure 3

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

10

V

C

= 4.3 V

= 3.3 V

IN1

OUT1

V

C

= 2.8 V

= 1.8 V

IN2

OUT2

= 22 µF

OUT1

= 1 A

= 47 µF

OUT2

= 2 A

I

T

O

J

I

T

O

J

= 25°C

1

0.1

0.01

0.1

0.01

100

1 k

10 k

100 k

100

1 k

10 k

100 k

f − Frequency − Hz

Figure 4

Figure 5

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

TYPICAL CHARACTERISTICS

OUTPUT IMPEDANCE

vs

OUTPUT IMPEDANCE

vs

FREQUENCY

V

= 3.3 V

OUT1

= 1 A

V

= 3.3 V

= 10 mA

= 22 µF

OUT1

I

O

I

O

C

= 22 µF

o

C

o

1

0.1

1

0.1

0.01

10

100

1 k

10 k

100 k

1 M

10 M

10

100

1 k

10 k

100 k

1 M

10 M

f − Frequency − Hz

Figure 6

Figure 7

OUTPUT IMPEDANCE

vs

OUTPUT IMPEDANCE

vs

FREQUENCY

V

= 1.8 V

V

I

C

= 1.8 V

= 10 mA

= 47 µF

OUT2

= 2 A

OUT2

O

o

I

O

C

= 47 µF

o

1

0.1

1

0.1

0.01

10

100

1 k

10 k

100 k

1 M

10 M

10

100

1 k

10 k

100 k

1 M

10 M

f − Frequency − Hz

Figure 8

Figure 9

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋꢌ ꢍꢎꢏ ꢋꢀ ꢁꢋꢀ ꢍ ꢏ ꢐꢎꢊꢑꢏ ꢁꢏ ꢋꢀ ꢒꢏ ꢍꢀꢌꢓ ꢉ ꢑꢉ ꢓ ꢋꢍ ꢌꢀꢏ ꢑ

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

TYPICAL CHARACTERISTICS

LOAD TRANSIENT RESPONSE

V

= 4.3 V

= 3.3 V

V

I

= 1.8 V

IN1

OUT1

= 22 µF

OUT2

= 2 A

1

2

1

O

C

T

C

T

= 47 µF

= 25°C

o

= 25°C

J

0.5

0

50

0

50

0

−50

−100

−50

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

t − Time − ms

Figure 10

Figure 11

LINE TRANSIENT RESPONSE

V

I

C

= 3.3 V

OUT1

= 1 A

V

I

= 1.8 V

OUT2

= 2 A

5.3

4.3

O

3.8

2.8

O

= 22 µF

o

C = 47 µF

o

50

0

100

0

−50

−100

−200

−100

0

20 40 60 80 100 120 140 160 180 200

0

20 40 60 80 100 120 140 160 180 200

t − Time − µs

Figure 12

Figure 13

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

TYPICAL CHARACTERISTICS

OUTPUT VOLTAGE AND ENABLE VOLTAGE

vs

TIME (START-UP)

4

3

V

= 3.3 V

OUT1

= 1 A

I

C

O

2

1

0

2

1

0

= 22 µF

= 4.3 V

o

V

IN1

SEQ = Low

V

= 1.8 V

OUT2

= 2 A

I

C

O

= 47 µF

= 2.8 V

o

V

IN2

5

0

SEQ = High

5

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

t − Time (Start-Up) − ms

Figure 14

Figure 15

To Load

IN

V

I

OUT

+

R

L

C

o

EN

GND

ESR

Figure 16. Test Circuit for Typical Regions of Stability

†

Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added

externally, and PWB trace resistance to C .

o

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

TYPICAL CHARACTERISTICS

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE (ESR)

vs

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE (ESR)

†

vs

OUTPUT CURRENT

10

V

C

= 3.3 V

OUT1

= 22 µF

V

C

= 3.3 V

OUT1

= 220 µF

o

REGION OF INSTABILITY

1

0.1

50 mΩ

15 mΩ

0.01

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

I

O

− Output Current − A

I

O

− Output Current − A

Figure 17

Figure 18

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE (ESR)

vs

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE (ESR)

vs

†

OUTPUT CURRENT

10

REGION OF INSTABILITY

V

C

= 1.8 V

OUT2

= 47 µF

V

C

= 1.8 V

OUT2

= 680 µF

o

1

o

0.1

50 mΩ

15 mΩ

0.01

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

1

I

O

− Output Current − A

I

O

− Output Current − A

Figure 19

Figure 20

†

Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added

externally, and PWB trace resistance to C .

o

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

THERMAL INFORMATION

thermally enhanced TSSOP-24 (PWP − PowerPad)

The thermally enhanced PWP package is based on the 24-pin TSSOP, but includes a thermal pad (see

Figure 21(c)] to provide an effective thermal contact between the IC and the PWB.

Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down

TO220-type packages have leads formed as gull wings to make them applicable for surface-mount applications.

These packages, however, suffer from several shortcomings: they do not address the low profile requirements

(<2 mm) of many of today’s advanced systems, and they do not offer a pin-count high enough to accommodate

increasing integration. On the other hand, traditional low-power surface-mount packages require

power-dissipation derating that severely limits the usable range of many high-performance analog circuits.

The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal

performance comparable to much larger power packages.

The PWP package is designed to optimize the heat transfer to the PWB. Because of the small size and limited

mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that

remove heat from the component. The thermal pad is formed using a lead-frame design (patent pending) and

manufacturing technique to provide the user with direct connection to the heat-generating IC. When this pad

is soldered or otherwise coupled to an external heat dissipator, high power dissipation in the ultrathin, fine-pitch,

surface-mount package can be reliably achieved.

DIE

Side View (a)

Thermal

Pad

DIE

End View (b)

Bottom View (c)

Figure 21. Views of Thermally Enhanced PWP Package

Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal

considerations in the PWB design. For example, simply adding a localized copper plane (heat-sink surface),

which is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference

2

Figure 23(a), 8 cm of copper heat sink and natural convection). Increasing the heat-sink size increases the

power dissipation range for the component. The power dissipation limit can be further improved by adding

2

airflow to a PWB/IC assembly (see Figure 22 and Figure 23). The line drawn at 0.3 cm in Figure 22 and

Figure 23 indicates performance at the minimum recommended heat-sink size, illustrated in Figure 24.

16

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

THERMAL INFORMATION

thermally enhanced TSSOP-24 (PWP − PowerPad) (continued)

The thermal pad is directly connected to the substrate of the IC, which for the TPS70345 series is a secondary

electrical connection to device ground. The heat-sink surface that is added to the PWP can be a ground plane

or left electrically isolated. In TO220-type surface-mount packages, the thermal connection is also the primary

electrical connection for a given terminal which is not always ground. The PWP package provides up to 24

independent leads that can be used as inputs and outputs (Note: leads 1, 12, 13, and 24 are internally connected

to the thermal pad and the IC substrate).

THERMAL RESISTANCE

vs

COPPER HEAT-SINK AREA

150

125

100

Natural Convection

50 ft/min

100 ft/min

150 ft/min

200 ft/min

75

50

25

250 ft/min

300 ft/min

0 0.3

1

2

3

4

5

6

7

8

2

Copper Heat-Sink Area − cm

Figure 22

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

THERMAL INFORMATION

thermally enhanced TSSOP-24 (PWP − PowerPad) (continued)

3.5

T

A

= 25°C

T

A

= 55°C

300 ft/min

3

2.5

2

3

2.5

2

150 ft/min

300 ft/min

150 ft/min

Natural Convection

1.5

Natural Convection

1

0.5

0

1

0.5

0

2

4

6

8

0

2

4

6

8

0.3

2

Copper Heat-Sink Size − cm

(a)

(b)

3.5

T

A

= 105°C

3

2.5

2

1.5

1

150 ft/min

300 ft/min

Natural Convection

0.5

0

0.3

2

4

6

8

2

Copper Heat-Sink Size − cm

(c)

Figure 23. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

THERMAL INFORMATION

thermally enhanced TSSOP-24 (PWP − PowerPad) (continued)

Figure 24 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board

configuration was used in the thermal experiments that generated the power ratings shown in Figure 22 and

Figure 23. As discussed earlier, copper has been added on the PWB to conduct heat away from the device. R

for this assembly is illustrated in Figure 22 as a function of heat-sink area. A family of curves is included to

illustrate the effect of airflow introduced into the system.

θJA

Heat-Sink Area

1 oz Copper

Board thickness

Board size

62 mils

3.2 in. × 3.2 in.

FR4

Board material

Copper trace/heat sink 1 oz

Exposed pad mounting 63/67 tin/lead solder

Figure 24. PWB Layout (Including Copper Heatsink Area) for Thermally Enhanced PWP Package

From Figure 22, R

power-dissipation limit for the component/PWB assembly, with the equation:

for a PWB assembly can be determined and used to calculate the maximum

θJA

T max * T

J

A

P

+

D(max)

R

(1)

qJA(system)

where

T max is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended

J

operating limit) and T is the ambient temperature.

A

P

should then be applied to the internal power dissipated by the TPS70345 regulator. The equation for

D(max)

calculating total internal power dissipation of the TPS70345 is:

I

Q

2

₊ǒ_VIN1

Ǔ

₎ǒ_VIN2

Ǔ

OUT2

P

* V

I

) V

* V

I

) V

(2)

D(total)

OUT1

IN1

OUT2

IN2

2

Since the quiescent current of the TPS703xx is low, the second term is negligible, further simplifying the

equation to:

₊ǒ_VIN1

Ǔ

ǒ

Ǔ

OUT2

(3)

P

* V

I

) V

* V

I

D(total)

OUT1

IN2

OUT2

2

For the case where T = 55°C, airflow = 200 ft/min, copper heat-sink area = 4 cm , the maximum

A

power-dissipation limit can be calculated. First, from Figure 22, we find the system R

the maximum power-dissipation limit is:

is 50°C/W; therefore,

θJA

T max * T

°

J

A

125 C * 55 C

P

+

+ TBD W

(4)

D(max)

°

R

TBD CńW

qJA(system)

19

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

THERMAL INFORMATION

thermally enhanced TSSOP-24 (PWP − PowerPad) (continued)

If the system implements a TPS70345 regulator, where V = 5 V and I = 800 mA, the internal power

I

O

dissipation is:

₊ǒ_VIN1

Ǔ

₎ǒ_VIN2

Ǔ

(5)

P

* V

I

* V

I

D(total)

+ (4.3 * 3.3) 0.8 ) (2.8 * 1.8) 1 + 1.8 W

Comparing P with P reveals that the power dissipation in this example does not exceed the

OUT1

OUT2

D(total)

D(max)

calculated limit. When it does, one of two corrective actions should be made: raising the power-dissipation limit

by increasing the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by

reducing the input voltage or the load current. In either case, the above calculations should be repeated with

the new system parameters. This parameter is measured with the recommended copper heat sink pattern on

a 4-layer PCB, 2 oz. copper traces on 4-in × 4-in ground layer. Simultaneous and continuous operation of both

regulator outputs at full load may exceed the power dissipation rating of the PWP package.

mounting information

The primary requirement is to complete the thermal contact between the thermal pad and the PWB metal. The

thermal pad is a solderable surface and is fully intended to be soldered at the time the component is mounted.

Although voiding in the thermal-pad solder-connection is not desirable, up to 50% voiding is acceptable. The

data included in Figure 22 and Figure 23 is for soldered connections with voiding between 20% and 50%. The

thermal analysis shows no significant difference resulting from the variation in voiding percentage.

Figure 25 shows the solder-mask land pattern for the PWP package. The minimum recommended heat-sink

area is also illustrated. This is simply a copper plane under the body extent of the package, including metal

routed under terminals 1, 12, 13, and 24.

Location of Exposed

Minimum Recommended

Thermal Pad on

Heat-Sink Area

PWP Package

Figure 25. PWP Package Land Pattern

20

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

APPLICATION INFORMATION

sequencing timing diagrams

The following figures provide a timing diagram of how this device functions in different configurations.

application conditions not shown in block diagram:

TPS70345PWP

(Fixed Output Option)

V

and V

are tied to the same fixed input

IN2

IN1

V

OUT1

V

I

voltage greater than the V

logic low; PG1 is tied to MR2; MR1 is not used and

; SEQ is tied to

UVLO

V

OUT1

V

IN1

is connected to V .

0.22 µF

22 µF

IN

V

SENSE1

explanation of timing diagrams:

250 kΩ

PG1

MR2

EN is initially high; therefore, both regulators are

off and PG1 and RESET are at logic low. With

SEQ at logic low, when EN is taken to logic low,

MR2

V

IN2

0.22 µF

V

turns on. V

turns on after V

RESET

OUT1

OUT2 OUT1

RESET

MR1

reaches 83% of its regulated output voltage.

When V reaches 95% of its regulated output

voltage, PG1 (tied to MR2) goes to logic high.

When both V and V reach 95% of their

respective regulated output voltages and both

MR1 and MR2 (tied to PG1) are at logic high,

RESET is pulled to logic high after a 120 ms delay.

When EN is returned to logic high, both devices

power down and both PG1 (tied to MR2) and

RESET return to logic low.

OUT1

MR1

V

IN

EN

>2 V

OUT1

OUT2

<0.7 V

V

SENSE2

SEQ

V

OUT2

V

OUT2

47 µF

EN

SEQ

V

OUT2

95%

83%

95%

83%

V

OUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

t1

(see Note A)

NOTE A: t1 − Time at which both V and V

120 ms

are greater than the PG thresholds and MR1 is logic high.

OUT1 OUT2

Figure 26. Timing When SEQ = Low

21

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

APPLICATION INFORMATION

sequencing timing diagrams (continued)

TPS70345PWP

(Fixed Output Option)

application conditions not shown in block diagram:

V

I

V

OUT1

V

OUT1

IN1

IN2

V

and V

are tied to the same fixed input

IN2

IN1

voltage greater than the V

logic high; PG1 is tied to MR2; MR1 is not used

; SEQ is tied to

UVLO

0.22 µF

22 µF

V

SENSE1

and is connected to V .

IN

250 kΩ

PG1

MR2

explanation of timing diagrams:

MR2

V

EN is initially high; therefore, both regulators are

off and PG1 and RESET are at logic low. With

SEQ at logic high, when EN is taken to logic low,

0.22 µF

RESET

MR1

RESET

MR1

V

turns on. V

turns on after V

OUT2

OUT1 OUT2

reaches 83% of its regulated output voltage.

When V reaches 95% of its regulated output

V

IN

EN

>2 V

OUT1

voltage, PG1 (tied to MR2) goes to logic high.

When both V and V reach 95% of their

V

SENSE2

<0.7 V

OUT1

OUT2

SEQ

respective regulated output voltages and both

MR1 and MR2 (tied to PG1) are at logic high,

RESET is pulled to logic high after a 120 ms delay.

When EN is returned to logic high, both devices

turn off and both PG1 (tied to MR2) and RESET

return to logic low.

V

OUT2

V

OUT2

47 µF

EN

SEQ

V

OUT2

95%

83%

95%

83%

OUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

t1

(see Note A)

NOTE A: t1 − Time at which both V and V

120ms

are greater than the PG thresholds and MR1 is logic high.

OUT1 OUT2

Figure 27. Timing When SEQ = High

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

APPLICATION INFORMATION

sequencing timing diagrams (continued)

TPS70345PWP

(Fixed Output Option)

application conditions not shown in block diagram:

V

I

V

OUT1

V

OUT1

IN1

IN2

V

and V

are tied to the same fixed input

IN2

IN1

voltage greater than the V

; SEQ is tied to

0.22 µF

UVLO

22 µF

V

logic high; PG1 is tied to MR2; MR1 is initially at

logic high but is eventually toggled.

SENSE1

250 kΩ

PG1

MR2

explanation of timing diagrams:

MR2

V

EN is initially high; therefore, both regulators are

off and PG1 and RESET are at logic low. With

0.22 µF

RESET

MR1

SEQ at logic high, when EN is taken low, V

OUT2

turns on. V

turns on after V

reaches 83%

OUT1

OUT2

MR1

of its regulated output voltage. When V

EN

OUT1

EN

2 V

reaches 95% of its regulated output voltage, PG1

(tied to MR2) goes to logic high. When both V

>2 V

0.7 V

OUT1

V

<0.7 V

SENSE2

and V

reach 95% of their respective

OUT2

SEQ

regulated output voltages and both MR1 and MR2

(tied to PG1) are at logic high, RESET is pulled to

logic high after a 120 ms delay. When MR1 is

taken low, RESET returns to logic low but the

V

OUT2

V

OUT2

47 µF

outputs remain in regulation. When MR1 is returned to logic high, since both V

95% of their respective regulated output voltages and MR2 (tied to PG1) remains at logic high, RESET is pulled

and V

remain above

OUT1

OUT2

to logic high after a 120 ms delay.

EN

SEQ

V

95%

83%

OUT2

95%

83%

OUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

t1

(see Note A)

NOTE A: t1 − Time at which both V and V

120 ms

are greater than the PG thresholds and MR1 is logic high.

OUT1 OUT2

Figure 28. Timing When MR1 Is Toggled

23

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ꢀ

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ꢏ

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ꢑ

ꢉ

ꢓ

ꢋ

ꢍ

ꢌꢀꢏ

ꢑ

ꢂ

ꢔ

ꢀ

ꢔ

ꢗ

ꢙ

ꢏ

ꢑ

ꢂ

ꢁ

ꢍ

ꢔ

ꢀ

ꢒ

ꢏ

ꢍ

ꢀ

ꢌ

ꢓ

ꢉ

ꢊ

ꢂ

ꢁ

ꢂ

ꢚ

ꢂ

ꢀ

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ꢛ

ꢂ

SGLS323A − JANUARY 2006 − REVISED MARCH 2006

APPLICATION INFORMATION

sequencing timing diagrams (continued)

TPS70345PWP

(Fixed Output Option)

application conditions not shown in block diagram:

V

I

V

OUT1

V

OUT1

V

and V

are tied to the same fixed input

IN2

IN1

IN2

IN1

voltage greater than the V

logic high; PG1 is tied to MR2; MR1 is not used

; SEQ is tied to

UVLO

0.22 µF

22 µF

V

SENSE1

and is connected to V .

IN

250 kΩ

explanation of timing diagrams:

PG1

MR2

V

EN is initially high; therefore, both regulators are

off and PG1 and RESET are at logic low. With

SEQ at logic high, when EN is taken low, V

0.22 µF

RESET

MR1

RESET

MR1

OUT2

turns on. V

turns on after V

reaches 83%

OUT1

OUT2

of its regulated output voltage. When V

OUT1

V

IN

EN

reaches 95% of its regulated output voltage, PG1

(tied to MR2) goes to logic high. When both V

>2 V

OUT1

V

SENSE2

<0.7 V

and V

reach 95% of their respective

OUT2

regulated output voltages and both MR1 and MR2

(tied to PG1) are at logic high, RESET is pulled to

logic high after a 120 ms delay. When a fault on

SEQ

V

OUT2

V

OUT2

47 µF

V

causes it to fall below 95% of its regulated

OUT1

output voltage, PG1 (tied to MR2) goes to logic

low.

EN

SEQUENCE

V

OUT2

OUT1

95%

83%

95%

83%

V

Fault on V

OUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

t1

(see Note A)

NOTE A: t1 − Time at which both V

120 ms

are greater than the PG thresholds and MR1 is logic high.

and V

OUT2

OUT1

Figure 29. Timing When a Fault Occurs on V

OUT1

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢈ

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ꢉ

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ꢉ

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ꢍꢔ

ꢀ

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ꢏ

ꢍ

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ꢌ

ꢓ

ꢉ

ꢊ

ꢂ

ꢁ

ꢂ

ꢚ

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ꢀ

ꢉ

ꢛ

SGLS323A − JANUARY 2006 − REVISED MARCH 2006

APPLICATION INFORMATION

TPS70345PWP

(Fixed Output Option)

sequencing timing diagrams (continued)

V

I

V

application conditions not shown in block diagram:

OUT1

V

OUT1

IN1

IN2

V

and V

are tied to the same fixed input

IN2

IN1

voltage greater than the V

logic high; PG1 is tied to MR2; MR1 is not used

; SEQ is tied to

0.22 µF

22 µF

UVLO

V

SENSE1

and is connected to V .

IN

250 kΩ

PG1

MR2

explanation of timing diagrams:

MR2

V

EN is initially high; therefore, both regulators are

off and PG1 and RESET are at logic low. With

0.22 µF

RESET

MR1

RESET

MR1

SEQ at logic high, when EN is taken low, V

OUT2

turns on. V

turns on after V

reaches 83%

OUT1

OUT2

V

IN

of its regulated output voltage. When V

EN

OUT1

EN

reaches 95% of its regulated output voltage, PG1

>2 V

(tied to MR2) goes to logic high. When both V

V

OUT1

SENSE2

<0.7 V

and V

reach 95% of their respective

OUT2

SEQ

regulated output voltages and both MR1 and MR2

(tied to PG1) are at logic high, RESET is pulled to

logic high after a 120 ms delay. When a fault on

V

OUT2

V

OUT2

47 µF

V

causes it to fall below 95% of its regulated

OUT2

output voltage, RESET returns to logic low and V

begins to power down because SEQ is high. When V

OUT1

falls below 95% of its regulated output voltage, PG1 (tied to MR2) returns to logic low.

ENABLE

SEQUENCE

95%

83%

V

OUT2

Fault on V

OUT2

95%

83%

OUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

t1

120 ms

are greater than the PG thresholds and MR1 is logic high.

(see Note A)

NOTE A: t1 − Time at which both V

and V

OUT2

OUT1

Figure 30. Timing When a Fault Occurs on V

OUT2

25

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SGLS323A − JANUARY 2006 − REVISED MARCH 2006

APPLICATION INFORMATION

input capacitor

For a typical application, a ceramic input bypass capacitor (0.22 µF − 1 µF) is recommended to ensure device

stability. This capacitor should be as close as possible to the input pin. Due to the impedance of the input supply,

large transient currents causes the input voltage to droop. If this droop causes the input voltage to drop below

the UVLO threshold, the device turns off. Therefore, it is recommended that a larger capacitor be placed in

parallel with the ceramic bypass capacitor at the regulator’s input. The size of this capacitor depends on the

output current, response time of the main power supply, and the main power supply’s distance to the regulator.

At a minimum, the capacitor should be sized to ensure that the input voltage does not drop below the minimum

UVLO threshold voltage during normal operating conditions.

output capacitor

As with most LDO regulators, the TPS70345 requires an output capacitor connected between each OUT and

GND to stabilize the internal control loop. The minimum recommended capacitance value for V is 22 µF

OUT1

and the ESR (equivalent series resistance) must be between 50 mΩ and 800 mΩ. The minimum recommended

capacitance value for V is 47 µF and the ESR must be between 50 mΩ and 2 Ω. Solid tantalum electrolytic,

OUT2

aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements

described above. Larger capacitors provide a wider range of stability and better load transient response. Below

is a partial listing of surface-mount capacitors usable with the TPS70345 for fast transient response application.

This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the

user’s application. When necessary to achieve low height requirements along with high output current and/or

high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.

VALUE

680 µF

470 µF

150 µF

220 µF

100 µF

68 µF

MFR.

Kemet

Sanyo

Kemet

PART NO.

T510X6871004AS

4TPB470M

4TPC150M

2R5TPC220M

6TPC100M

10TPC68M

68 µF

T495D6861006AS

T495D4761010AS

T495C3361016AS

T495C2261010AS

47 µF

33 µF

22 µF

regulator protection

Both TPS70345 PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input

voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the

input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be

appropriate.

The TPS70345 also features internal current limiting and thermal protection. During normal operation, the

TPS70345 regulator 1 limits output current to approximately 1.75 A (typ) and regulator 2 limits output current

to approximately 3.8 A (typ). When current limiting engages, the output voltage scales back linearly until the

overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be

taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds

150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator

operation resumes.

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS70345MPWPREP HTSSOP PWP

24

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 24

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TPS70345MPWPREP

2000

Pack Materials-Page 2

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型号：	TPS70345MPWPREP
厂家：	TEXAS INSTRUMENTS
描述：	具有加电时序的双路输出低压降稳压器（增强型产品） \| PWP \| 24 \| -55 to 125 稳压器
文件：	总32页 (文件大小：937K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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