TPS70628DRVR [TI]

具有反向电流保护和使能功能的 150mA、超低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;


型号：	TPS70628DRVR
厂家：	TEXAS INSTRUMENTS
描述：	具有反向电流保护和使能功能的 150mA、超低 IQ、低压降稳压器 \| DRV \| 6 \| -40 to 125 稳压器
文件：	总34页 (文件大小：1694K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

TPS706 具有使能功能的 150mA、6.5V、1μA I_Q稳压器

1 特性

3 说明

•

输入电压范围：2.7V 至 6.5V

TPS706 系列线性稳压器是针对功耗敏感型应用而设计

的超低静态电流器件。一个精密带隙和误差放大器在

温度范围内的精度为 2%。只有 1µA 的静态电流使得

此器件成为由电池供电、要求非常小闲置状态功率耗散

的常开系统的理想解决方案。该系列器件还具有热关

断、电流限制和反向电流保护功能，提升了器件安全

性。

超低 I_Q：1μA

反向电流保护

低 I_SHDN：150nA

支持 200mA 峰值输出

低压降：50mA 时为 245mV

在温度范围内精度为 2%

可提供固定输出电压：1.2V 至 5V

热关断及过流保护

通过将 EN 引脚拉为低电平，可将该系列稳压器置于关

断模式。这个模式的关断电流低至 150nA（典型

值）。

封装：小外形尺寸晶体管 (SOT)-23-5 封装、晶圆

级小外形无引线 (WSON)

TPS706 系列采用 WSON-6 和 SOT-23-5 封装。

2 应用

器件信息⁽¹⁾

•

智能手机和平板电脑

器件型号

TPS706

封装

SOT-23 (5)

WSON (6)

封装尺寸（标称值）

2.90mm x 1.60mm

2.00mm x 2.00mm

便携式和电池供电类应用

摄像机模块

机顶盒

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

可穿戴产品

固态硬盘

空白

医疗设备

空白

典型应用电路

接地电流与 V_IN和温度间的关系

V_OUT

V_IN

OUT

T_J= -40°C

T_J= +25°C

2.8

1 mF

2.2 mF

T_J= +85°C

2.6

GND

T_J= +125°C

2.4

TPS706

2.2

1.8

1.6

1.4

1.2

4.25 4.5 4.75

5.25 5.5 5.75

6.25 6.5

Input Voltage (V)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

English Data Sheet: SBVS245

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

www.ti.com.cn

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 13

Application and Implementation ........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application .................................................. 15

Power Supply Recommendations...................... 15

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 5

6.7 Typical Characteristics.............................................. 6

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

10 Layout................................................................... 16

10.1 Layout Guidelines ................................................. 16

10.2 Layout Examples................................................... 18

11 器件和文档支持 ..................................................... 19

11.1 器件支持................................................................ 19

11.2 文档支持................................................................ 19

11.3 商标....................................................................... 19

11.4 静电放电警告......................................................... 19

11.5 术语表 ................................................................... 19

12 机械封装和可订购信息 .......................................... 19

4 修订历史记录

Changes from Original (October 2014) to Revision A

Page

•

已更改产品预览数据表；以量产数据状态发布........................................................................................................................ 1

TPS706

www.ti.com.cn

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

5 Pin Configuration and Functions

DBV Package

SOT-23-5

(Top View)

DRV Package

WSON-6

(Top View)

GND

OUT

GND

Pin Functions

NO.

I/O

DESCRIPTION

NAME

DRV

DBV

Enable pin. Driving this pin high enables the device. Driving this pin low puts the

device into low current shutdown. This pin can be left floating to enable the device.

The maximum voltage must remain below 6.5 V.

GND

—

Ground

Unregulated input to the device

No internal connection

2, 5

—

Regulated output voltage. Connect a small 2.2-µF or greater ceramic capacitor

from this pin to ground to assure stability.

OUT

The thermal pad is electrically connected to the GND node.

Connect to the GND plane for improved thermal performance.

Thermal pad

—

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

specified at T_J= –40°C to 125°C, unless otherwise noted; all voltages are with respect to GND⁽¹⁾

MIN

MAX

UNIT

V_IN

–0.3

Voltage

V_EN

V_OUT

I_OUT

Internally limited

Indefinite

Maximum output current

Output short-circuit duration

Continuous total power dissipation

Junction temperature, T_J

P_DISS

See Thermal Information

150

–55

°C

Storage temperature, T_stg

150

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

V_(ESD)

Electrostatic discharge

(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

MIN

2.7

1.2

NOM

MAX

6.5

UNIT

V_IN

Input voltage

V_OUT

I_OUT

V_EN

C_IN

Output voltage

Output current

150

6.5

Enable voltage

Input capacitor

µF

°C

C_OUT

T_J

Output capacitor

Operating junction temperature

2.2

–40

125

6.4 Thermal Information

TPS706

THERMAL METRIC⁽¹⁾

DBV

DRV

UNIT

5 PINS

212.1

78.5

6 PINS

73.1

97.0

42.6

2.9

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

R_θJC(top)

R_θJB

39.5

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

2.86

ψ_JB

38.7

42.9

12.8

R_θJC(bot)

N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS706

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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

6.5 Electrical Characteristics

At T_J= –40°C to 125°C, V_IN= V_OUT(nom)+ 1 V or 2.7 V (whichever is greater), I_OUT= 1 mA, V_EN= 2 V, and C_IN= C_OUT= 2.2-μF

ceramic, unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

TEST CONDITIONS

MIN

2.7

TYP

MAX

6.5

5.0

UNIT

V_IN

Input voltage range

Output voltage range

V_OUT

1.2

V_OUT< 3.3 V

_OUT≥ 3.3 V, T_J= –40°C to 85°C

–2%

–1%

V_{OUT(accuracy)}

DC output accuracy

Line regulation

Load regulation

(V_OUT(nom)+ 1 V, 2.7 V) ≤ V_IN≤ 6.5 V

ΔV_OUT

V_IN= V_OUT(nom)+ 1.5 V or 3 V (whichever is

greater), 100 µA ≤ I_OUT≤ 150 mA

2.8 V ≤ V_OUT≤ 3.3 V, I_OUT= 50 mA

2.8 V ≤ V_OUT≤ 3.3 V, I_OUT= 150 mA

V_OUT= 0.9 × V_OUT(nom)

295

975

320

1.3

350

150

650

1540

500

µA

V_DO

I_(CL)

I_GND

I_SHDN

Dropout voltage⁽¹⁾⁽²⁾

Output current limit⁽³⁾

Ground pin current

Shutdown current

200

I_OUT= 0 mA, V_OUT≤ 3.3 V

I_OUT= 150 mA

2.55

V_EN≤ 0.4 V, V_IN= 2.7 V

f = 10 Hz

PSRR

V_n

Power-supply rejection ratio f = 100 Hz

f = 1 kHz

BW = 10 Hz to 100 kHz, I_OUT= 10 mA,

V_IN= 2.7 V, V_OUT= 1.2 V

Output noise voltage

190

μV_RMS

Enable pin high (enabled)

Enable pin high (disabled)

EN pin current

0.9

V_EN(HI)

I_EN

0.4

EN = 1.0 V, V_IN= 5.5 V

300

Reverse current

(flowing out of IN pin)

V_OUT= 3 V, V_IN= V_EN= 0 V

I_REV

Reverse current

(flowing into OUT pin)

V_OUT= 3 V, V_IN= V_EN= 0 V

100

Shutdown, temperature increasing

Reset, temperature decreasing

158

140

°C

Thermal shutdown

temperature

T_SD

T_J

Operating junction

temperature

–40

125

°C

(1) V_DOis measured with V_IN= 0.98 × V_OUT(nom)

(2) Dropout is only valid when V_OUT≥ 2.8 V because of the minimum input voltage limits.

(3) Measured with V_IN= V_OUT+ 3 V for V_OUT≤ 2.5 V. Measured with V_IN= V_OUT+ 2.5 V for V_OUT> 2.5 V.

6.6 Timing Requirements

At T_J= –40°C to 125°C, V_IN= V_OUT(nom)+ 1 V or 2.7 V (whichever is greater), R_L= 47 Ω, V_EN= 2 V, and C_IN= C_OUT= 2.2-μF

ceramic, unless otherwise noted. Typical values are at T_J= 25°C.

PARAMETER

MIN

TYP

200

500

MAX

600

UNIT

µs

_OUT(nom)≤ 3.3 V

t_STR

Start-up time⁽¹⁾

V_OUT> 3.3 V

1500

µs

(1) Startup time = time from EN assertion to 0.95 × V_OUT(nom)and load = 47 Ω.

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

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6.7 Typical Characteristics

Over operating temperature range (T_J= –40°C to 125°C), I_OUT= 10 mA, V_EN= 2 V, C_OUT= 2.2 μF, and V_IN= V_OUT(nom)+ 1 V

or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at T_J= 25°C.

1.205

1.204

1.203

1.202

1.201

1.2

3.31

3.308

3.306

3.304

3.302

3.3

T_J= -40°C

T_J= +25°C

T_J= +85°C

T_J= +125°C

T_J= -40°C

T_J= +25°C

T_J= +85°C

T_J= +125°C

1.199

1.198

1.197

1.196

1.195

3.298

3.296

3.294

3.292

3.29

2.5

3.5

4.5

5.5

6.5

4.25 4.5 4.75

5.25 5.5 5.75

Input Voltage (V)

6.25 6.5

Input Voltage (V)

TPS70612

TPS70633

Figure 1. 1.2-V Line Regulation vs V_INand Temperature

Figure 2. 3.3-V Line Regulation vs V_INand Temperature

1.205

3.308

T_J= -40°C

T_J= +25°C

T_J= +85°C

T_J= +125°C

T_J= -40°C

1.2025

3.304

3.3

T_J= +25°C

T_J= +85°C

T_J= +125°C

1.2

1.1975

3.296

3.292

3.288

3.284

3.28

1.195

1.1925

1.19

1.1875

1.185

1.1825

1.18

3.276

3.272

100

120

140

100

120

140

Output Current (mA)

Input Current (mA)

TPS70612

TPS70633

Figure 3. 1.2-V Load Regulation vs I_OUTand Temperature

Figure 4. 3.3-V Load Regulation vs I_OUTand Temperature

1.205

500

I_OUT= 10 mA

I_OUT= 150 mA

T_J= -40°C

T_J= +25°C

T_J= +85°C

T_J= +125°C

480

460

440

420

400

380

360

340

320

300

280

260

240

220

200

1.2025

1.2

1.1975

1.195

1.1925

1.19

1.1875

1.185

1.1825

1.18

-40

-20

100 120 140

3.5

4.5

5.5

6.5

Junction Temperature (qC)

Input Voltage (V)

TPS70612

Figure 5. V_OUTvs Temperature

Figure 6. 1.2-V Current Limit vs V_INand Temperature

TPS706

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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

Typical Characteristics (continued)

Over operating temperature range (T_J= –40°C to 125°C), I_OUT= 10 mA, V_EN= 2 V, C_OUT= 2.2 μF, and V_IN= V_OUT(nom)+ 1 V

or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at T_J= 25°C.

440

430

420

410

400

390

380

370

360

350

340

330

320

310

300

2.5

T_J= -40°C

T_J= +25°C

T_J= +85°C

T_J= +125°C

T_J= +125 qC

T_J= +85 qC

T_J= +25 qC

T_J= -40 qC

1.5

0.5

5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9

6.1 6.2 6.3 6.4 6.5

2.5

3.5

4.5

5.5

6.5

Input Voltage (V)

TPS70633

TPS70612

Figure 7. 3.3-V Current Limit vs V_INand Temperature

Figure 8. GND Current vs V_INand Temperature

800

700

600

500

400

300

200

100

T_J= +125 qC

T_J= +85 qC

T_J= +25 qC

T_J= -40 qC

T_J= -40°C

2.8

T_J= +25°C

T_J= +85°C

T_J= +125°C

2.6

2.4

2.2

1.8

1.6

1.4

1.2

4.25 4.5 4.75

5.25 5.5 5.75

6.25 6.5

100

125

150

Input Voltage (V)

Output Current (mA)

TPS70633, EN = open

TPS70612

Figure 9. GND Current vs V_INand Temperature

Figure 10. GND Current vs I_OUTand Temperature

0.6

0.5

0.4

0.3

0.2

0.1

T_J= +125 qC

T_J= +85 qC

T_J= +25 qC

T_J= -40 qC

2.5

3.5

4.5

5.5

6.5

1E+1

1E+2

1E+3

1E+4

1E+5

1E+6

1E+7

Input Voltage (V)

Frequency (Hz)

Shutdown current, TPS70612

V_OUT= 2.8 V, V_IN= 3.8 V, C_OUT= 2.2 µF

Figure 11. Shutdown Current vs V_INand Temperature

Figure 12. Power-Supply Rejection Ratio vs Frequency

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

www.ti.com.cn

Typical Characteristics (continued)

Over operating temperature range (T_J= –40°C to 125°C), I_OUT= 10 mA, V_EN= 2 V, C_OUT= 2.2 μF, and V_IN= V_OUT(nom)+ 1 V

or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at T_J= 25°C.

6.5

140

130

120

110

100

5.5

4.5

3.5

2.5

1.5

0.5

10 25 40 55 70 85 100 115 130

±50 ±35 ±20 ±5

1E+1

1E+2

1E+3

Frequency (Hz)

1E+4

1E+5

Temperature (C)

C019

TPS70612

V_OUT= 2.8 V

Figure 14. Start-Up Time vs Temperature

Figure 13. Noise

Channel 2

(200 mV / div)

Channel 2

(200 mV / div)

Channel 4

(50 mA / div)

Channel 4

(100 mA / div)

Time (100 ms / div)

Time (500 ms / div)

Channel 2 = V_OUT, channel 4 = I_OUT, V_IN= 2.7 V

Figure 15. TPS70612 Load Transient (0 mA to 50 mA)

Figure 16. TPS70612 Load Transient (1 mA to 150 mA)

Channel 2

(200 mV / div)

Channel 2

(200 mV / div)

Channel 4

(50 mA / div)

Channel 4

(100 mA / div)

Time (10 ms / div)

Time (100 ms / div)

Channel 2 = V_OUT, channel 4 = I_OUT, V_IN= 2.7 V

Figure 17. TPS70612 Load Transient (50 mA to 0 mA)

Figure 18. TPS70612 Load Transient (50 mA to 150 mA)

TPS706

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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

Typical Characteristics (continued)

Over operating temperature range (T_J= –40°C to 125°C), I_OUT= 10 mA, V_EN= 2 V, C_OUT= 2.2 μF, and V_IN= V_OUT(nom)+ 1 V

or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at T_J= 25°C.

Channel 2

(200 mV / div)

Channel 2

(200 mV / div)

Channel 4

(50 mA / div)

Channel 4

(100 mA / div)

Time (100 ms / div)

Time (500 ms / div)

Channel 2 = V_OUT, channel 4 = I_OUT, V_IN= 4.3 V

Figure 19. TPS70633 Load Transient (0 mA to 50 mA)

Figure 20. TPS70633 Load Transient (1 mA to 150 mA)

Channel 2

(200 mV / div)

Channel 2

(200 mV / div)

Channel 4

(50 mA / div)

Channel 4

(50 mA / div)

Time (10 ms / div)

Time (500 ms / div)

Channel 2 = V_OUT, channel 4 = I_OUT, V_IN= 4.3 V

Figure 21. TPS70633 Load Transient (50 mA to 0 mA)

Figure 22. TPS70633 Load Transient (50 mA to 150 mA)

Channel 2

(50 mV / div)

Channel 2

(50 mV / div)

Channel 4

(2 V / div)

Channel 4

(2 V / div)

Time (50 ms / div)

Channel 2 = V_OUT, channel 4 = V_IN, I_OUT= 10 mA

Channel 2 = V_OUT, channel 4 = V_IN, I_OUT= 50 mA

Figure 23. TPS70612 Line Transient (2.7 V to 3.7 V)

Figure 24. TPS70612 Line Transient (2.7 V to 3.7 V)

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

www.ti.com.cn

Typical Characteristics (continued)

Over operating temperature range (T_J= –40°C to 125°C), I_OUT= 10 mA, V_EN= 2 V, C_OUT= 2.2 μF, and V_IN= V_OUT(nom)+ 1 V

or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at T_J= 25°C.

Channel 2

(50 mV / div)

Channel 2

(50 mV / div)

Channel 4

(2 V / div)

Channel 4

(2 V / div)

Time (50 ms / div)

Channel 2 = V_OUT, channel 4 = V_IN, I_OUT= 10 mA

Channel 2 = V_OUT, channel 4 = V_IN, I_OUT= 50 mA

Figure 25. TPS70633 Line Transient (4.3 V to 5.3 V)

Figure 26. TPS70633 Line Transient (4.3 V to 5.3 V)

Channel 2

(1 V / div)

Channel 2

(1 V / div)

Channel 1

(500 mV / div)

Channel 1

(1 V / div)

Time (50 ms / div)

Time (500 ms / div)

Channel 1 = EN, channel 2 = V_OUT, V_IN= 4.3 V, C_OUT= 2.2 µF,

TPS70633

Channel 1 = V_IN, channel 2 = V_OUT, I_OUT= 3 mA, TPS70633

Figure 27. Power-Up with Enable

Figure 28. Power-Up and Power-Down Response

Channel 2

(1 V / div)

Channel 1

(1 V / div)

Time (500 ms / div)

Channel 1 = V_IN, channel 2 = V_OUT, I_OUT= 150 mA, TPS70633

Figure 29. Power-Up and Power-Down Response

TPS706

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ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

7 Detailed Description

7.1 Overview

The TPS706 series are ultralow quiescent current, low-dropout (LDO) linear regulators. The TPS706 offers

reverse current protection to block any discharge current from the output into the input. The TPS706 also

features current limit and thermal shutdown for reliable operation.

7.2 Functional Block Diagram

OUT

Current

Limit

Thermal

Shutdown

Bandgap

Logic

Device

GND

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)

The TPS706 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry

operates properly.

7.3.2 Shutdown

The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed V_EN(HI)(0.9 V, minimum).

Turn off the device by forcing the EN pin to drop below 0.4 V. If shutdown capability is not required, connect EN

to IN.

7.3.3 Reverse Current Protection

The TPS706 has integrated reverse current protection. Reverse current protection prevents the flow of current

from the OUT pin to the IN pin when output voltage is higher than input voltage. The reverse current protection

circuitry places the power path in high impedance when the output voltage is higher than the input voltage. This

setting reduces leakage current from the output to the input to 10 nA, typical. The reverse current protection is

always active regardless of the enable pin logic state or if the OUT pin voltage is greater than 1.8 V. Reverse

current can flow if the output voltage is less than 1.8 V and if input voltage is less than the output voltage.

If voltage is applied to the input pin, then the maximum voltage that can be applied to the OUT pin is the lower of

three times the nominal output voltage or 6.5 V. For example, if the 1.2-V output voltage version is used, then the

maximum reverse bias voltage that can be applied to the OUT pin is 3.6 V. If the 3.3-V output voltage version is

used, then the maximum reverse bias voltage that can be applied to the OUT pin is 6.5 V.

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

www.ti.com.cn

Feature Description (continued)

7.3.4 Internal Current Limit

The TPS706 internal current limit helps protect the regulator during fault conditions. During current limit, the

output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output

voltage is not regulated, and can be measured as (V_OUT= I_LIMIT× R_LOAD). The PMOS pass transistor dissipates

[(V_IN– V_OUT) × I_LIMIT] until a thermal shutdown is triggered and the device turns off. When cool, the device is

turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between

current limit and thermal shutdown; see the Thermal Information section for more details.

The TPS706 is characterized over the recommended operating output current range up to 150 mA. The internal

current limit begins to limit the output current at a minimum of 200 mA of output current.

7.3.5 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 158°C, allowing the

device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again

enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection

circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a

result of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate

heatsink. For reliable operation, limit junction temperature to 125°C, maximum. To estimate the margin of safety

in a complete design (including heatsink), increase the ambient temperature until the thermal protection is

triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least

35°C above the maximum expected ambient condition of the particular application. This configuration produces a

worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The TPS706 internal protection circuitry is designed to protect against overload conditions. This circuitry is not

intended to replace proper heatsinking. Continuously running the TPS706 into thermal shutdown degrades

device reliability.

TPS706

www.ti.com.cn

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

•

The input voltage is at least as high as V_IN(min).

The input voltage is greater than the nominal output voltage added to the dropout voltage.

The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased

below the enable falling threshold.

•

The output current is less than the current limit.

The device junction temperature is less than the maximum specified junction temperature.

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the

output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the

device is significantly degraded because the pass device is in the linear region and no longer controls the current

through the LDO. Line or load transients in dropout can result in large output voltage deviations.

7.4.3 Disabled

The device is disabled under the following conditions:

•

The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising

threshold.

•

The device junction temperature is greater than the thermal shutdown temperature.

Table 1 shows the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_EN

I_OUT

I_OUT< I_LIM

—

T_J

V_IN> V_OUT(nom)+ V_DOand

V_IN> V_IN(min)

Normal mode

Dropout mode

V_EN> V_EN(HI)

T_J< 125°C

V_IN(min)< V_IN< V_OUT(nom)+ V_DO

Disabled mode

(any true condition disables the

device)

—

V_EN< V_EN(low)

—

T_J> 158°C

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

www.ti.com.cn

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS706 consumes low quiescent current and delivers excellent line and load transient performance. This

performance, combined with low noise and good PSRR with little (V_IN– V_OUT) headroom, makes these devices

ideal for RF portable applications, current limit, and thermal protection. The TPS706 devices are specified from

–40°C to 125°C.

8.1.1 Input and Output Capacitor Considerations

The TPS706 devices are stable with output capacitors with an effective capacitance of 2.0 μF or greater for

output voltages below 1.5 V. For output voltages equal or greater than 1.5 V, the minimum effective capacitance

for stability is 1.5 µF. The maximum capacitance for stability is 47 µF. The equivalent series resistance (ESR) of

the output capacitor must be between 0 Ω and 0.2 Ω for stability.

The effective capacitance is the minimum capacitance value of a capacitor after taking into account variations

resulting from tolerances, temperature, and dc bias effects. X5R- and X7R-type ceramic capacitors are

recommended because these capacitors have minimal variation in value and ESR over temperature.

Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to

2.2-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient

response, input ripple rejection, and PSRR.

8.1.2 Dropout Voltage

The TPS706 uses a PMOS pass transistor to achieve low dropout. When (V_IN– V_OUT) is less than the dropout

voltage (V_DO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the

R_DS(ON)of the PMOS pass element. V_DOapproximately scales with the output current because the PMOS device

functions like a resistor in dropout.

The ground pin current of many linear voltage regulators increases substantially when the device is operated in

dropout. This increase in ground pin current while operating in dropout can be several orders of magnitude larger

than when the device is not in dropout. The TPS706 employs a special control loop that limits the increase in

ground pin current while operating in dropout. This functionality allows for the most efficient operation while in

dropout conditions that can greatly increase battery run times.

8.1.3 Transient Response

As with any regulator, increasing the output capacitor size reduces over- and undershoot magnitude, but

increases transient response duration.

TPS706

www.ti.com.cn

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

8.2 Typical Application

V_IN

V_OUT

OUT

1 mF

2.2 mF

GND

TPS70633

Figure 30. 3.3-V, Low-I_QRail

8.2.1 Design Requirements

Table 2 summarizes the design requirements for Figure 30.

Table 2. Design Requirements for a 3.3-V, Low-I_QRail Application

PARAMETER

V_IN

DESIGN SPECIFICATION

4.3 V

3.3 V

V_OUT

I_(IN)(no load)

I_OUT(max)

< 5 µA

150 mA

8.2.2 Detailed Design Procedure

Select a 2.2-µF, 10-V X7R output capacitor to satisfy the minimum output capacitance requirement with a 3.3-V

dc bias.

Select a 1.0-µF, 6.3-V X7R input capacitor to provide input noise filtering and eliminate high-frequency voltage

transients.

8.2.3 Application Curves

Channel 2

(200 mV / div)

Channel 2

(1 V / div)

Channel 1

(500 mV / div)

Channel 4

(50 mA / div)

Time (500 ms / div)

Time (50 ms / div)

Channel 2 = V_OUT, channel 4 = I_OUT, V_IN= 4.3 V

Channel 1 = EN, channel 2 = V_OUT, V_IN= 4.3 V, C_OUT= 2.2 µF,

TPS70633

Figure 32. Power-Up with Enable

Figure 31. TPS70633 Load Transient (50 mA to 150 mA)

9 Power Supply Recommendations

This device is designed to operate with an input supply range of 2.7 V to 6.5 V. The input voltage range must

provide adequate headroom in order for the device to have a regulated output. This input supply must be well-

regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve the

output noise performance.

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

www.ti.com.cn

10 Layout

10.1 Layout Guidelines

10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance

Input and output capacitors must be placed as close to the device pins as possible. To improve ac performance

(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate

ground planes for V_INand V_OUT, with the ground plane connected only at the device GND pin. In addition, the

output capacitor ground connection must be connected directly to the device GND pin.

10.1.2 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in

the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves

the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the

Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The

addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (P_D) can be approximated by

the product of the output current times the voltage drop across the output pass element (V_INto V_OUT), as shown

in Equation 1.

P_D= (V_IN– V_OUT) × I_OUT

(1)

Figure 33 shows the maximum ambient temperature versus the power dissipation of the TPS706. This figure

assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board

thermal impedances vary widely. If the application requires high power dissipation, having a thorough

understanding of the board temperature and thermal impedances is helpful to ensure the TPS706 does not

operate above a junction temperature of 125°C.

125

TPS706, DBV Package

TPS706, DRV Package

100

0.2

0.4

0.6

0.8

Power Dissipation (W)

Figure 33. Maximum Ambient Temperature vs Device Power Dissipation

TPS706

www.ti.com.cn

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

Layout Guidelines (continued)

Estimating the junction temperature can be done by using the thermal metrics Ψ_JTand Ψ_JB, shown in the

Thermal Information. These metrics are a more accurate representation of the heat transfer characteristics of the

die and the package than R_θJA. The junction temperature can be estimated with Equation 2.

Y_JT: T_J= T_T+ Y_JT· P_D

Y_JB: T_J= T_B+ Y_JB· P_D

where:

•

P_Dis the power dissipation shown by Equation 1,

T_Tis the temperature at the center-top of the IC package,

T_Bis the PCB temperature measured 1 mm away from the IC package on the PCB surface.

(2)

NOTE

Both T_Tand T_Bcan be measured on actual application boards using a thermo-gun (an

infrared thermometer).

For more information about measuring T_Tand T_B, see the application note Using New Thermal Metrics

(SBVA025), available for download at www.ti.com.

TPS706

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

www.ti.com.cn

10.2 Layout Examples

Input Capacitor

Input

Trace

Enable

Trace

Grounded

Thermal Plane

Input Ground

Plane

Thermal Pad

GND

Output Trace

OUT

Grounded

Thermal Plane

Output Ground

Plane

Output Capacitor

Designates thermal vias.

Figure 34. WSON Layout Example

V_OUT

V_IN

OUT

C_IN

C_OUT

GND

GND PLANE

Represents via used for application-specific connections.

Figure 35. SOT23-5 Layout Example

TPS706

www.ti.com.cn

ZHCSDI0A –OCTOBER 2014–REVISED MARCH 2015

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 Spice 模型

分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以从产品文件夹中的

仿真模型下获取 TPS706 的 SPICE 模型。

11.1.2 器件命名规则

表 3. 器件命名规则⁽¹⁾

产品

V_OUT

TPS706xx yyy z

xx 为标称输出电压。对于分辨率为 100mV 的输出电压，订货编号中使用两位数字；否则，

使用三位数字（例如，28 = 2.8V）。

yyy 为封装标识符。

z 为卷带数量（R = 3000，T = 250）。

(1) 要获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者登录 TI 的网站 www.ti.com.cn进行查询。

11.2 文档支持

11.2.1 相关文档

SBVU002 — DEM-SOT23LDO 演示固定装置

SBVA025 — 《使用新的热指标》

11.3 商标

All trademarks are the property of their respective owners.

11.4 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 ,

可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

11.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、首字母缩略词和定义。

12 机械封装和可订购信息

以下页中包括机械封装和可订购信息。这些信息是针对指定器件可提供的最新数据。这些数据会在无通知且不对

本文档进行修订的情况下发生改变。欲获得该数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS70612DBVR

TPS70612DBVT

TPS70612DRVR

TPS70612DRVT

TPS70615DBVR

TPS70615DBVT

TPS70615DRVR

TPS70615DRVT

TPS70618DBVR

TPS70618DBVT

TPS70618DRVR

TPS70618DRVT

TPS70625DBVR

TPS70625DBVT

TPS70625DRVR

TPS70625DRVT

TPS70628DBVR

TPS70628DBVT

TPS70628DRVR

TPS70628DRVT

ACTIVE

SOT-23

WSON

SOT-23

WSON

SOT-23

WSON

SOT-23

WSON

SOT-23

WSON

DBV

DRV

DBV

DRV

DBV

DRV

DBV

DRV

DBV

DRV

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

SJC

SIW

SIX

NIPDAU

SIX

SIY

SJU

250

RoHS & Green

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS70630DBVR

TPS70630DBVT

TPS70630DRVR

TPS70630DRVT

TPS70633DBVR

TPS70633DBVT

TPS70633DRVR

TPS70633DRVT

ACTIVE

SOT-23

WSON

SOT-23

WSON

DBV

DRV

DBV

DRV

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

3000 RoHS & Green

250 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

SIZ

SJA

NIPDAU

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS70612DBVR

TPS70612DBVT

TPS70612DRVR

TPS70612DRVT

TPS70615DBVR

TPS70615DBVT

TPS70615DRVR

TPS70615DRVT

TPS70618DBVR

TPS70618DBVT

TPS70618DRVR

TPS70618DRVT

TPS70625DBVR

TPS70625DBVT

SOT-23

WSON

SOT-23

WSON

SOT-23

WSON

SOT-23

DBV

DRV

DBV

DRV

DBV

DRV

DBV

3000

250

178.0

180.0

178.0

180.0

178.0

180.0

178.0

9.0

8.4

9.0

8.4

9.0

8.4

9.0

3.3

2.3

3.3

2.3

3.3

2.3

3.3

3.2

2.3

3.2

2.3

3.2

2.3

3.2

1.4

4.0

8.0

3000

250

1.15

1.4

3000

250

1.4

3000

250

1.15

1.4

3000

250

1.4

3000

250

1.15

1.4

250

3000

250

1.4

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS70625DRVR

TPS70625DRVT

TPS70628DBVR

TPS70628DBVT

TPS70628DRVR

TPS70628DRVT

TPS70630DBVR

TPS70630DBVT

TPS70630DRVR

TPS70630DRVT

TPS70633DBVR

TPS70633DBVT

TPS70633DRVR

TPS70633DRVT

WSON

SOT-23

WSON

SOT-23

WSON

SOT-23

WSON

DRV

DBV

DRV

DBV

DRV

DBV

DRV

3000

250

180.0

178.0

180.0

178.0

180.0

178.0

180.0

8.4

9.0

8.4

9.0

8.4

9.0

8.4

2.3

3.3

2.3

3.3

2.3

3.3

2.3

3.2

2.3

3.2

2.3

3.2

2.3

1.15

1.4

4.0

8.0

250

3000

250

1.4

3000

250

1.15

1.4

250

3000

250

1.4

3000

250

1.15

1.4

250

3000

250

1.4

3000

250

1.15

250

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS70612DBVR

TPS70612DBVT

TPS70612DRVR

TPS70612DRVT

TPS70615DBVR

TPS70615DBVT

TPS70615DRVR

TPS70615DRVT

TPS70618DBVR

TPS70618DBVT

TPS70618DRVR

TPS70618DRVT

TPS70625DBVR

TPS70625DBVT

TPS70625DRVR

SOT-23

WSON

SOT-23

WSON

SOT-23

WSON

SOT-23

WSON

DBV

DRV

DBV

DRV

DBV

DRV

DBV

DRV

3000

250

180.0

182.0

180.0

182.0

180.0

182.0

210.0

182.0

180.0

210.0

182.0

180.0

182.0

180.0

182.0

180.0

182.0

185.0

182.0

180.0

185.0

182.0

18.0

20.0

18.0

20.0

18.0

20.0

35.0

20.0

18.0

35.0

20.0

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

3000

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS70625DRVT

TPS70628DBVR

TPS70628DBVT

TPS70628DRVR

TPS70628DRVT

TPS70630DBVR

TPS70630DBVT

TPS70630DRVR

TPS70630DRVT

TPS70633DBVR

TPS70633DBVT

TPS70633DRVR

TPS70633DRVT

WSON

SOT-23

WSON

SOT-23

WSON

SOT-23

WSON

DRV

DBV

DRV

DBV

DRV

DBV

DRV

250

210.0

182.0

180.0

210.0

182.0

210.0

180.0

182.0

210.0

182.0

210.0

180.0

210.0

182.0

210.0

185.0

182.0

180.0

185.0

182.0

185.0

180.0

182.0

185.0

182.0

185.0

180.0

185.0

182.0

185.0

35.0

20.0

18.0

35.0

20.0

35.0

18.0

20.0

35.0

20.0

35.0

18.0

35.0

20.0

35.0

3000

250

3000

250

3000

250

3000

250

3000

250

3000

250

Pack Materials-Page 4

GENERIC PACKAGE VIEW

DRV 6

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4206925/F

PACKAGE OUTLINE

DRV0006A

WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD

2.1

1.9

PIN 1 INDEX AREA

2.1

1.9

0.8

0.7

SEATING PLANE

0.08 C

(0.2) TYP

0.05

0.00

0.1

EXPOSED

THERMAL PAD

1.3

1.6 0.1

4X 0.65

0.35

0.25

PIN 1 ID

(OPTIONAL)

0.3

0.2

0.1

C A

0.05

4222173/B 04/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

6X (0.45)

6X (0.3)

(1)

SYMM

(1.6)

(1.1)

4X (0.65)

SYMM

(1.95)

(R0.05) TYP

(

0.2) VIA

TYP

LAND PATTERN EXAMPLE

SCALE:25X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4222173/B 04/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.

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EXAMPLE STENCIL DESIGN

DRV0006A

WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

SYMM

6X (0.45)

METAL

6X (0.3)

(0.45)

SYMM

4X (0.65)

(0.7)

(R0.05) TYP

(1)

(1.95)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD #7

88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:30X

4222173/B 04/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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PACKAGE OUTLINE

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

3.0

2.6

0.1 C

1.75

1.45

0.90

PIN 1

INDEX AREA

(0.1)

2X 0.95

1.9

3.05

2.75

1.9

(0.15)

0.5

0.3

0.15

0.00

(1.1)

TYP

0.2

C A B

NOTE 5

0.25

GAGE PLANE

0.22

0.08

TYP

0.6

0.3

TYP

SEATING PLANE

4214839/G 03/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

5. Support pin may differ or may not be present.

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EXAMPLE BOARD LAYOUT

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X (0.95)

(R0.05) TYP

(2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

METAL

EXPOSED METAL

0.07 MIN

ARROUND

0.07 MAX

ARROUND

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4214839/G 03/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

DBV0005A

SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR

PKG

5X (1.1)

5X (0.6)

SYMM

(1.9)

2X(0.95)

(R0.05) TYP

(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:15X

4214839/G 03/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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