TPS70751PWP [TI]
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS; 与POWER UP测序SPLIT电压DSP系统双输出低压差稳压器
| 型号： | TPS70751PWP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS |
| 文件： | 总34页 (文件大小：505K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
Dual Output Voltages for Split-Supply
Applications
Open Drain Power Good for Regulator 1
Ultra Low 190 µA (typ) Quiescent Current
1 µA Input Current During Standby
Selectable Power Up Sequencing for DSP
Applications
Low Noise: 65 µV
Capacitor
Without Bypass
RMS
Output Current Range of 250 mA on
Regulator 1 and 125 mA on Regulator 2
Quick Output Capacitor Discharge Feature
Two Manual Reset Inputs
Fast Transient Response
Voltage Options are 3.3-V/2.5-V, 3.3-V/1.8-V,
3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable
Outputs
2% Accuracy Over Load and Temperature
Undervoltage Lockout (UVLO) Feature
20-Pin PowerPAD TSSOP Package
Thermal Shutdown Protection
Open Drain Power-On Reset With 120-ms
Delay
PWP PACKAGE
(TOP VIEW)
description
TPS707xx family devices are designed to provide
a complete power management solution for DSP,
processor power, ASIC, FPGA, and digital
applications where dual output voltage regulators
are required. Easy programmability of the
sequencing function makes this family ideal for
any DSP applications with power sequencing
requirement. Differentiated features, such as
accuracy, fast transient response, SVS supervi-
sory circuit (power on reset), manual reset inputs,
and enable function, provide a complete system
solution.
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
V
V
V
IN1
IN1
OUT1
V
V
OUT1
MR1
MR2
EN
SEQ
GND
/FB1
/FB2
SENSE1
PG1
RESET
V
V
V
SENSE2
OUT2
V
V
IN2
IN2
OUT2
NC
TPS70751 PWP
DSP
I/O
3.3 V
V
OUT1
5 V
V
IN1
10 µF
0.1 µF
V
SENSE1
250 kΩ
PG1
PG1
MR2
MR2
MR1
>2 V
V
IN2
250 kΩ
<0.7 V
0.1 µF
RESET
RESET
MR1
EN
<0.7 V
>2 V
>2 V
EN
<0.7 V
V
SENSE2
SEQ
1.8 V
Core
V
OUT2
10 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
description (continued)
The TPS707xx family of voltage regulators offers very low dropout voltage and dual outputs with power up
sequence control, which is designed primarily for DSP applications. These devices have extremely low noise
output performance without using any added filter bypass capacitors and are designed to have a fast transient
response and be stable with 10 uF low ESR capacitors.
These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable/adjustable voltage
options. Regulator 1 can support up to 250 mA and regulator 2 can support up to 125 mA. Separate voltage
inputs allow the designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 83 mV
on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is
a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of
230 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal
to EN (enable) shuts down both regulators, reducing the input current to 1 µA at T = 25°C.
J
The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two
regulators are sensed at the V
and V
pins respectively.
SENSE1
SENSE2
The input signal at the SEQ pin controls the power-up sequence of the two regulators. When the device is
enabled and the SEQ terminal is pulled high or left open, V will turn on first and V will remain off until
OUT2
OUT1
V
reachesapproximately83%ofitsregulatedoutputvoltage.AtthattimeV
willbeturnedon. IfV
OUT2
OUT1 OUT2
is pulled below 83% (i.e. over load condition) V
the power-up order and V
source.
will be turned off. Pulling the SEQ terminal low, reverses
will be turned on first. The SEQ pin is connected to an internal pullup current
OUT1
OUT1
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off(disabled).
The PG1 pin reports the voltage conditions at VOUT1. Power good can be used to implement a SVS for the
circuitry supplied by regulator 1.
The TPS707xx features a RESET (SVS, POR, or Power On Reset). RESET output initiates a reset in DSP
systems and related digital applications in the event of an undervoltage condition. RESET indicates the status
of V
and both manual reset pins (MR1 and MR2). When V
reaches 95% of its regulated voltage and
OUT2
OUT2
MR1 and MR2 are in the logic high state, RESET will go to a high impedance state after 120 ms delay. RESET
will go to logic low state when V regulated output voltage is pulled below 95% (i.e. over load condition) of
OUT2
its regulated voltage. To monitor V
, the PG1 output pin can be connected to MR1 or MR2.
OUT1
ThedevicehasanundervoltagelockoutUVLOcircuitwhichpreventstheinternalregulatorsfromturningonuntil
VIN1 reaches 2.5V.
AVAILABLE OPTIONS
REGULATOR 1
(V)
REGULATOR 2
(V)
TSSOP
(PWP)
T
J
V
V
O
O
3.3 V
3.3 V
3.3 V
3.3 V
1.2 V
1.5 V
1.8 V
2.5 V
TPS70745PWP
TPS70748PWP
TPS70751PWP
TPS70758PWP
–40°C to 125°C
Adjustable
(1.22 V to 5.5 V)
Adjustable
(1.22 V to 5.5 V)
TPS70702PWP
NOTE: The TPS70702 is programmable using external resistor dividers (see
application information) The PWP package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS70702PWPR).
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
detailed block diagram – fixed voltage version
VIN1 (2 Pins)
VOUT1 (2 Pins)
10 kΩ
Current
Sense
ENA_1
VSENSE1
(see Note A)
UVLO
Shutdown
ENA_1
2.5 V
–
+
Reference
VREF
FB1
GND
Thermal
Shutdown
VREF
PG1
FB1
0.95 × VREF
Rising Edge
Deglitch
V
IN1
MR2
SHUTDOWN
RESET
FB2
Falling Edge
Delay
Rising Edge
Deglitch
UV Comp
0.95 × VREF
FB2
Falling Edge
Deglitch
V
IN1
ENA_1
0.83 × VREF
Power
Sequence
Logic
FB1
ENA_2
MR1
Falling Edge
Deglitch
VREF
FB2
0.83 × VREF
UV Comp
–
+
ENA_2
ENA_2
EN
V
IN1
VSENSE2
(see Note A)
Current
Sense
SEQ
(see Note B)
10 kΩ
VOUT2(2 Pins)
VIN2 (2 Pins)
NOTES: A. For most applications, V
and V
should be externally connected to V
as close as possible to the device.
OUT
SENSE1
SENSE2
For other implementations, refer to SENSE terminal connection discussion in the application information section.
B. If the SEQ terminal is floating at the input, V
will power up first.
OUT2
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
detailed block diagram – adjustable voltage version
VIN1 (2 Pins)
VOUT1 (2 Pins)
Current
Sense
ENA_1
UVLO
FB1
(see Note A)
Shutdown
ENA_1
2.5 V
–
+
Reference
VREF
GND
Thermal
Shutdown
VREF
PG1
FB1
Rising Edge
Deglitch
0.95 × VREF
V
IN1
MR2
SHUTDOWN
RESET
FB2
Falling Edge
Delay
UV Comp
Rising Edge
Deglitch
0.95 × VREF
FB2
Falling Edge
Deglitch
V
IN1
ENA_1
Power
Sequence
Logic
0.83 × VREF
FB1
ENA_2
Falling Edge
Deglitch
MR1
VREF
0.83 × VREF
UV Comp
–
+
EN
V
ENA_2
ENA_2
IN1
FB2
(see Note A)
Current
Sense
SEQ
(see Note B)
VOUT2 (2 Pins)
VIN2 (2 Pins)
NOTES: A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device.
For other implementations, refer to FB terminals connection discussion in the application information section.
B. If the SEQ terminal is floating at the input, V
will power up first.
OUT2
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
RESET timing diagram (with V
powered up and MR1 AND MR2 at logic high)
IN1
V
IN2
V
V
RES
RES
(see Note A)
t
V
OUT2
V (see Note B)
IT+
V (see Note B)
IT+
Threshold
Voltage
V
V
IT–
(see Note B)
IT–
(see Note B)
t
RESET
Output
120 ms
Delay
120 ms
Delay
Output
Undefined
Output
Undefined
t
NOTES: A.
V
is the minimum input voltage for a valid RESET. The symbol V is not currently listed within EIA or JEDEC standards
res
RES
for semiconductor symbology.
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%V ) V
to V
is the hysteresis voltage.
IT+
O
IT–
PG1 timing diagram
V
IN1
V
UVLO
V
UVLO
V
V
PG1
PG1
(see Note A)
t
V
OUT2
V (see Note B)
IT+
V
IT+
(see Note B)
Threshold
Voltage
V
V
IT–
(see Note B)
IT–
(see Note B)
30 µs
t
PG1
Output
Output
Undefined
Output
Undefined
t
NOTES: A.
V
is the minimum input voltage for a valid PG1. The symbol V
PG1
is not currently listed within EIA or JEDEC
to V is the hysteresis voltage.
PG1
standards for semiconductor symbology.
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%V ) V
O
IT–
IT+
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
EN
6
I
Active low enable
Ground
GND
MR1
MR2
NC
8
4
I
I
Manual reset input 1, active low, pulled up internally
Manual reset input 2, active low, pulled up internally
No connection
5
1, 11, 20
PG1
RESET
SEQ
16
15
7
O
O
I
Open drain output, low when V
voltage is less than 95% of the nominal regulated voltage
Open drain output, SVS (power on reset) signal, active low
OUT1
Power up sequence control: SEQ=High, V
terminal pulled up internally.
powers up first; SEQ=Low, V
OUT1
powers up first, SEQ
OUT2
V
V
V
V
V
V
2, 3
9, 10
18, 19
12, 13
14
I
I
Input voltage of regulator 1
Input voltage of regulator 2
Output voltage of regulator 1
Output voltage of regulator 2
IN1
IN2
O
O
I
OUT1
OUT2
SENSE2
SENSE1
/FB2
/FB1
Regulator 2 output voltage sense/ regulator 2 feedback for adjustable
Regulator 1 output voltage sense/ regulator 1 feedback for adjustable
17
I
†
absolute maximum ratings over operating junction temperature (unless otherwise noted)
‡
Input voltage range : V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
IN1
IN2
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7 V
Output voltage range (V
Output voltage range (V
, V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
OUT1 SENSE1
, V
OUT2 SENSE2
Maximum RESET, PG1 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Maximum MR1, MR2, and SEQ voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
IN1
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are tied to network ground.
DISSIPATION RATING TABLE
AIR FLOW
PACKAGE
T
A
≤ 25°C
DERATING FACTOR
T
A
= 70°C
T = 85°C
A
(CFM)
0
3.067 W
4.115 W
30.67 mW/°C
41.15 mW/°C
1.687 W
2.265 W
1.227 W
1.646 W
§
PWP
250
§
This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on 4-in × 4-in
ground layer. For more information, refer to TI technical brief SLMA002.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
recommended operating conditions
MIN
2.7
0
MAX
6
UNIT
V
†
Input voltage, V
I
Output current, I (regulator 1)
250
125
5.5
125
mA
mA
V
O
Output current, I (regulator 2)
O
0
Output voltage range (for adjustable option)
1.22
–40
Operating virtual junction temperature, T
°C
.
J
†
To calculate the minimum input voltage for maximum output current, use the following equation: V
I(min)
= V
+ V
O(max) DO(max load)
electrical characteristics over recommended operating junction temperature (T = –40°C to 125°C)
J
V
or V
= V
+ 1 V, I = 1 mA, EN = 0, C = 33 µF(unless otherwise noted)
IN1
IN2
O(nom)
O
O
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2.7 V < V < 6 V,
FB connected to V
I
O
1.22
Reference
voltage
T
= 25°C
J
2.7 V < V < 6 V,
FB connected to V
1.196
1.176
1.47
1.244
1.224
1.53
I
O
2.7 V < V < 6 V,
T
T
T
T
T
T
T
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
= 25°C
1.2
1.5
I
J
J
J
J
J
J
J
1.2 V Output
1.5 V Output
1.8 V Output
2.5 V Output
3.3 V Output
2.7 V < V < 6 V
I
2.7 V < V < 6 V,
I
V
Output voltage
(see Notes 1 and 3)
2.7 V < V < 6 V
I
V
O
2.8 V < V < 6 V,
1.8
I
2.8 V < V < 6 V
1.764
2.45
1.836
2.55
I
3.5 V < V < 6 V,
2.5
I
3.5 V < V < 6 V
I
4.3 V < V < 6 V,
3.3
I
V
4.3 V < V < 6 V
I
3.234
3.366
230
See Note 3,
See Note 3
190
Quiescent current (GND current) for regulator 1 and
regulator 2, EN = 0 V, (see Note 1)
µA
V
V
+ 1 V < V ≤ 6 V,
= 25°C, See Note 1
0.01%
Output voltage line regulation (∆V /V )for
O
I
O
O
V
regulator 1 and regulator 2 (see Note 2)
+ 1 V < V ≤ 6 V,
See Note 1
See Note 3
0.1%
O
I
Load regulation for V and V
T = 25°C,
J
1
65
mV
OUT1
OUT2
Regulator 1
Regulator 2
Regulator 1
Regulator 2
V
Output noise voltage
BW = 300 Hz to 50 kHz,
C
= 33 µF,
T = 25°C
J
µVrms
n
O
65
1.6
1.9
1
Output current limit
Thermal shutdown junction temperature
V
= 0 V
A
O
0.750
150
°C
µA
dB
EN = V ,
T
= 25°C
2
6
I
J
Regulator 1 and
Regulator 2
I
Standby current
I(standby)
EN = V
I
PSRR
Power supply ripple rejection
f = 1 kHz, C = 33 µF,
T
= 25°C, See Note 1
60
O
J
NOTES: 1. Minimuminputoperatingvoltageis2.7VorV
1 mA.
+1V,whicheverisgreater.Maximuminputvoltage=6V,minimumoutputcurrent
O(typ)
2. If V < 1.8 V then V
imax
= 6 V, V
= 2.7 V:
O
Imin
V
V 2.7 V
O
imax
100
Line Regulation (mV)
% V
1000
If V > 2.5 V then V
= 6 V, V
= Vo + 1 V:
O
imax
Imin
V
V
V
1
O
imax
100
O
Line Regulation (mV)
% V
1000
3.
I
O
= 1 mA to 250 mA for Regulator 1 and 1 mA to 125 mA for Regulator 2.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
electrical characteristics over recommended operating junction temperature (T = –40°C to 125°C)
J
V
or V
= V
+ 1 V, I = 1 mA, EN = 0, C = 33 µF(unless otherwise noted) (continued)
IN1
IN2
O(nom)
O
O
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Minimum input voltage for valid RESET
Trip threshold voltage
I
= 300 µA,
V
≤ 0.8 V
1.0
1.3
V
(RESET)
(RESET)
V
decreasing
92%
95%
0.5%
120
98%
160
V
O
O
O
Hysteresis voltage
Measured at V
O
V
RESET
t
t
RESET pulse duration
Rising edge deglitch
80
ms
µs
V
(RESET)
30
r(RESET)
Output low voltage
Leakage current
V = 3.5 V,
I
= 1 mA
0.15
0.4
1
I
(RESET)
V
= 6 V
µA
V
(RESET)
Minimum input voltage for valid PG1
Trip threshold voltage
I
= 300 µA,
V
) ≤ 0.8 V
1.0
95%
0.5%
30
1.3
98%
O(PG1)
decreasing
(PG1
V
92%
V
V
O
O
Hysteresis voltage
Measured at V
O
O
PG1
t
Falling edge deglitch
V = 2.7 V,
µs
V
f(PG1)
Output low voltage
I
= 1 mA
0.15
0.4
1
I
(PG1)
Leakage current
V
= 6 V
µA
V
(PG1)
High level EN input voltage
Low level EN input voltage
Input current (EN)
2
0.7
1
V
EN
–1
2
µA
V
High level SEQ input voltage
Low level SEQ input voltage
SEQ pull up current source
High level input voltage
Low level input voltage
Pull up current source
0.7
0.7
V
SEQ
6
6
µA
V
2
V
MR1 / MR2
µA
V
UV comparator – positive-going input
OUT2
threshold voltage of V
80%V
O
83% V
86%V
O
V
O
UV comparator
OUT1
V
V
UV comparator – hysteresis
0.5%V
mV
OUT2
O
V
OUT2
UV comparator – falling edge deglitch
V
decreasing below threshold
140
µs
OUT2
SENSE_2
Peak output current
2 ms pulse width
375
7.5
mA
mA
Discharge transistor current
V = 1.5 V
OUT2
V
UV comparator – positive-going input
OUT1
threshold voltage of V
80%V
O
83% V
86%V
O
V
O
UV comparator
OUT1
V
V
UV comparator – hysteresis
0.5%V
mV
OUT1
O
UV comparator – falling edge deglitch
V
decreasing below threshold
140
µs
OUT1
SENSE_1
V
OUT1
I
T
= 250 mA,
= 25°C
V
= 3.2 V,
O
J
IN1
IN1
83
Dropout voltage (see Note 4)
mV
I
= 250 mA,
V
= 3.2 V
140
O
Peak output current
2 ms pulse width
V = 1.5 V
OUT1
750
7.5
mA
mA
V
Discharge transistor current
VOUT1 UVLO UVLO threshold
2.4
2.65
FB
Input current – TPS70702
FB = 1.8 V
1
µA
NOTE 4: Inputvoltage(V
or V ) = V (Typ)–100mV. Forthe1.5V, 1.8Vand2.5Vregulators, thedropoutvoltageislimitedbyinputvoltage
IN2 O
IN1
range. The 3.3 V regulator input voltage is to 3.2 V to perform this test.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
Table of Graphs
FIGURE
vs Output current
vs Junction temperature
vs Junction temperature
vs Frequency
1 – 3
4 – 7
V
Output voltage
O
Ground current
8
PSRR
Power supply rejection ratio
Output spectral noise density
Output impedance
9 – 12
13 – 16
17 – 20
21, 22
23, 24
25, 26
27, 28
29, 30
32 – 35
vs Frequency
Z
o
vs Frequency
vs Junction temperature
vs Input voltage
Dropout voltage
Load transient response
Line transient response
Output voltage
vs Time (start-up)
vs Output current
Stability
Equivalent series resistance (ESR)
TYPICAL CHARACTERISTICS
TPS70751
OUTPUT VOLTAGE
vs
TPS70751
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
1.802
1.801
1.800
3.303
3.302
3.301
3.3
V
= 2.8V
IN2
= 25°C
V
= 4.3 V
IN1
= 25°C
T
V
J
T
V
J
OUT2
OUT1
1.799
1.798
3.299
3.298
3.297
1.797
1.796
1.795
3.296
3.295
0
0.025
0.05
0.075
0.1
0.125
0
0.05
0.1
0.15
0.2
0.25
I
O
– Output Current – A
I
O
– Output Current – A
Figure 1
Figure 2
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
TPS70745
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.201
V
= 2.7 V
IN2
= 25°C
T
V
J
1.200
1.199
1.198
1.197
OUT2
1.196
1.195
0
0.025
0.05
0.075
0.1
0.125
I
O
– Output Current – A
Figure 3
TPS70751
OUTPUT VOLTAGE
vs
TPS70751
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
3.35
3.33
3.35
3.33
V
= 4.3 V
V
= 4.3 V
= 250 mA
IN1
= 1 mA
IN1
I
V
I
V
O
O
OUT1
OUT1
3.31
3.29
3.31
3.29
3.27
3.27
3.25
3.23
3.25
3.23
–40 –25 –10
T
5
20 35 50 65 80 95 110 125
–40 –25 –10
T
5
20 35 50 65 80 95 110 125
– Junction Temperature – °C
– Junction Temperature – °C
J
J
Figure 4
Figure 5
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
TPS70751
OUTPUT VOLTAGE
vs
TPS70751
OUTPUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.800
1.798
1.799
1.798
1.797
1.796
1.795
1.794
1.793
V
= 2.8 V
V
= 2.8 V
IN2
= 1 mA
IN2
I
V
I
= 125 mA
V
OUT2
O
O
OUT2
1.796
1.794
1.792
1.790
1.792
1.791
1.790
1.788
1.786
–40 –25 –10
5
20 35 50 65 80 95 110 125
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
J
– Junction Temperature – °C
T – Junction Temperature – °C
J
Figure 6
Figure 7
GROUND CURRENT
vs
JUNCTION TEMPERATURE
210
200
190
Regulator 1 and Regulator 2
I
= 1 mA
OUT1
OUT2
I
= 1 mA
180
170
I
I
= 250 mA
= 125 mA
OUT1
OUT2
160
150
–40 –25 –10
5
20 35 50 65 80 95 110 125
T
J
– Junction Temperature – °C
Figure 8
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
TPS70751
TPS70751
POWER SUPPLY REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
10
0
–10
–20
–30
–40
I
C
V
= 250 mA
I
C
V
= 10 mA
O
O
= 22 µF
= 22 µF
O
O
OUT1
OUT1
–10
–20
–30
–40
–50
–50
–60
–70
–60
–70
–80
–90
–80
–90
10
100
1 k
10 k
100 k
1 M
10
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
f – Frequency – Hz
Figure 9
Figure 10
TPS70751
TPS70751
POWER SUPPLY REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
10
0
–10
–20
I
C
V
= 10 mA
O
I
C
V
= 150 mA
O
= 22 µF
O
= 22 µF
O
OUT2
OUT2
–10
–20
–30
–40
–30
–40
–50
–50
–60
–70
–60
–70
–80
–90
–80
–90
10
100
1 k
10 k
100 k
1 M
10
100
1 k
10 k
100 k
1 M
f – Frequency – Hz
f – Frequency – Hz
Figure 11
Figure 12
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
V
V
I
= 4.3 V
= 3.3 V
V
V
I
= 4.3 V
= 3.3 V
IN1
OUT1
= 250 mA
IN1
OUT1
= 10 mA
O
O
1
1
0.1
0.01
0.1
0.01
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 13
Figure 14
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
V
= 2.8 V
= 1.8 V
V
= 2.8 V
= 1.8 V
IN2
IN2
V
I
V
I
OUT2
= 10 mA
OUT2
= 125 mA
O
O
1
1
0.1
0.1
0.01
0.01
100
1 k
10 k
100 k
100
1 k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 15
Figure 16
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
OUTPUT IMPEDANCE
vs
vs
FREQUENCY
FREQUENCY
10
100
C
I
= 33 µF
= 10 mA
= 3.3 V
= 25°C
C
I
= 33 µF
= 250 mA
O
O
O
O
V
OUT1
T
V
T
= 3.3 V
OUT1
= 25°C
J
J
10
1
1
0.1
0.01
0.1
0.01
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
Figure 18
f – Frequency – Hz
Figure 17
OUTPUT IMPEDANCE
vs
OUTPUT IMPEDANCE
vs
FREQUENCY
FREQUENCY
10
100
C
= 33 µF
= 125 mA
C
= 33 µF
= 10 mA
O
O
I
V
I
V
O
O
= 1.8 V
= 1.8 V
OUT2
= 25°C
OUT2
T = 25°C
J
T
J
10
1
1
0.1
0.1
0.01
10
100
1 k
10 k
100 k
1 M
10 M
10
100
1 k
10 k
100 k
1 M
10 M
f – Frequency – Hz
f – Frequency – Hz
Figure 19
Figure 20
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
DROPOUT VOLTAGE
vs
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
6
5
120
100
C
V
= 33 µF
C
V
= 33 µF
O
O
= 3.2 V
= 3.2 V
IN1
IN1
I
O
= 10 mA
I
O
= 250 mA
4
3
2
80
60
40
20
0
1
0
I
O
= 0 mA
–40 –25 –10
T
5
20 35 50 65 80 95 110 125
–40 –25 –10
T
5
20 35 50 65 80 95 110 125
– Junction Temperature – °C
– Junction Temperature – °C
J
J
Figure 21
Figure 22
TPS70702
DROPOUT VOLTAGE
vs
TPS70702
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
INPUT VOLTAGE
250
140
I
V
= 250 mA
I
V
= 125 mA
O
O
OUT1
OUT2
120
100
80
200
T
= 125°C
J
T
= 125°C
J
T
J
= 25°C
150
100
T
J
= 25°C
60
T = –40°C
J
40
T
J
= –40°C
50
0
20
0
2.5
3
3.5
4
4.5
5
2.5
3
3.5
4
4.5
5
V – Input Voltage – V
I
V – Input Voltage – V
I
Figure 23
Figure 24
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
C
T
= 33 µF
= 25°C
C
T
= 33 µF
O
O
J
= 25°C
250
0
125
0
J
V
OUT1
= 3.3 V
V
OUT2
= 1.8 V
20
0
20
0
–20
–40
–20
–40
–60
–80
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t – Time – ms
t – Time – ms
Figure 25
Figure 26
LINE TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
3.8
2.8
5.3
4.3
50
0
10
0
I
C
V
= 125 mA
I
C
V
= 250 mA
O
O
= 33 µF
–50
= 33 µF
–10
O
O
OUT2
OUT1
0
20 40 60 80 100 120 140 160 180 200
0
20 40 60 80 100 120 140 160 180 200
t – Time – µs
t – Time – µs
Figure 27
Figure 28
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
TIME (START-UP)
TIME (START-UP)
V
= 1.8 V
= 33 µF
= 125 mA
V
= 3.3 V
= 33 µF
= 250 mA
O
O
O
O
3
2
2
1
C
I
C
I
O
O
V
V
OUT2
OUT1
SEQ = High
SEQ = Low
1
0
0
–1
5
5
0
0
–5
–5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
t – Time – ms
t – Time – ms
Figure 29
Figure 30
To Load
IN
V
I
OUT
+
R
C
O
R
EN
L
GND
ESR
Figure 31. Test Circuit for Typical Regions of Stability
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C
.
O
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
†
†
vs
OUTPUT CURRENT
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
REGION OF INSTABILITY
= 3.3 V
= 6.8 µF
= 25°C
V
= 3.3 V
= 10 µF
= 25°C
O
O
V
C
C
T
O
O
J
T
J
1
1
0.1
50 mΩ
250 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
0.1
0.01
0
50
100
150
200
250
0
50
100
150
200
250
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 32
Figure 33
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
†
†
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
10
10
REGION OF INSTABILITY
REGION OF INSTABILITY
V
C
= 1.8 V
= 6.8 µF
= 25°C
O
O
V
C
= 1.8 V
= 10 µF
= 25°C
O
O
T
J
T
J
1
1
0.1
50 mΩ
250 mΩ
REGION OF INSTABILITY
REGION OF INSTABILITY
0.1
0.01
0
25
50
75
100
125
0
25
50
75
100
125
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 34
Figure 35
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C
.
O
18
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TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
detailed description
The TPS707xx low dropout regulator family provides dual regulated output voltages for DSP applications that
require a high-performance power management solution. These devices provide fast transient response and
high accuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing
provides a power solution for DSPs without any external component requirements. This reduces the component
costandboardspacewhileincreasingtotalsystemreliability. TPS707xxfamilyhasanenablefeaturewhichputs
thedeviceinsleepmodereducingtheinput currentstolessthan3µA. OtherfeaturesareintegratedSVS(power
on reset, RESET) and power good (PG1) that monitor output voltages and provide logic output to the system.
These differentiated features provide a complete DSP power solution.
The TPS707xx, unlike many other LDOs, feature very low quiescent current which remains virtually constant
even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is
directly proportional to the load current through the regulator (I = I /β). The TPS707xx uses a PMOS transistor
B
C
to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the
full load range.
pin functions
enable
The EN terminal is an input which enables or shuts down the device. If EN is at a voltage high signal the device
will be in shutdown mode. When the EN goes to voltage low, then the device will be enabled.
sequence
The SEQ terminal is an input that programs which output voltage (V
or V
) will be turned on first. When
OUT1
OUT2
the device is enabled and the SEQ terminal is pulled high or left open, V
will turn on first and V
will
will
OUT2
OUT1
reaches approximately 83% of its regulated output voltage. At that time the V
OUT1
remain off until V
be turned on. If V
a 6-µA pullup current to V
OUT2
OUT2
is pulled below 83% (i.e., over load condition) V
will be turned off. This terminal has
OUT1
.
IN1
Pulling the SEQ terminal low reverses the power-up order and V
diagrams refer to Figures 36 and 42.
will be turned on first. For detail timing
OUT1
power–good
The PG1 terminal is an open drain, active high output terminal which indicates the status of the V
regulator.
OUT1
When the V
a low impedance state when V
open drain output of the PG1 terminal requires a pullup resistor
reaches 95% of its regulated voltage, PG1 goes into a high impedance state. PG1 goes into
OUT1
is pulled below 95% (i.e. over-load condition) of its regulated voltage. The
OUT1
.
manual reset pins (MR1 and MR2)
MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled
to logic low, a POR (RESET) will occur. These terminals have a 6-µA pullup current to V
.
IN1
sense (V
, V
)
SENSE1 SENSE2
The sense terminals of fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, sense connects to high-impedance wide-bandwidth amplifiers
through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route
the sense connection in such a way to minimize/avoid noise pickup. Adding RC networks between the V
SENSE
terminalsandV
terminalstofilternoiseisnotrecommendedbecauseitcancausetheregulatorstooscillate.
OUT
FB1 and FB2
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and V
terminals to filter noise is not recommended because it can cause the regulators to oscillate.
OUT
19
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TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
detailed description (continued)
RESET indicator
The TPS707xx features a RESET (SVS, POR, or power on reset). RESET can be used to drive power-on reset
circuitry or a low-battery indicator. RESET is an active low, open drain output which indicates the status of the
V
regulatorandbothmanualresetpins(MR1andMR2).WhenV
exceeds95%ofitsregulatedvoltage,
OUT2
OUT2
and MR1 and MR2 are in the high impedance state, RESET will go to a high-impedance state after 120-ms
delay. RESET will go to a low impedance state when V is pulled below 95% (i.e. over load condition) of
OUT2
its regulated voltage. To monitor V
, PG1 output pin can be connected to MR1 or MR2. The open drain
OUT1
output of the RESET terminal requires a pullup resistor. If RESET is not used, it can be left floating.
V
and V
IN1
IN2
V
and V
are input to the regulators. Internal bias voltages are powered by V
.
IN1
IN2
and V
OUT2
IN1
V
OUT1
V
and V
are output terminals.
OUT2
OUT1
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
sequencing timing diagrams
The following figures provide a timing diagram of how this device functions in different configurations.
application conditions not shown in block diagram:
TPS707xxPWP
V
and V
are tied to the same fixed input
(Fixed Output Option)
IN1
IN2
voltage greater than the V
logic low; PG1 is tied to MR2; MR1 is left
unconnected and is therefore at logic high.
; SEQ is tied to
V
OUT1
V
I
UVLO
V
OUT1
V
IN1
0.1 µF
10 µF
V
SENSE1
explanation of timing diagrams:
250 kΩ
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
SEQ at logic low, when EN is taken to logic low,
PG1
MR2
MR2
V
IN2
V
turns on. V
turns on after V
OUT1
OUT2 OUT1
0.1 µF
RESET
RESET
MR1
reaches 83% of its regulated output voltage.
When V reaches 95% of its regulated output
voltage, PG1 (tied to MR2) goes to logic high.
When both V and V reach 95% of their
OUT1
MR1
EN
EN
>2 V
OUT1
OUT2
respective regulated output voltages and both
MR1 and MR2 (tied to PG1) are at logic high,
RESET is pulled to logic high after a 120 ms delay.
When EN is returned to logic high, both devices
power down and both PG1 (tied to MR2) and
RESET return to logic low.
<0.7 V
V
SENSE2
SEQ
V
OUT2
V
OUT2
10 µF
EN
SEQ
V
OUT2
95%
83%
95%
83%
V
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V and V
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
OUT1
Figure 36. Timing When SEQ = Low
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
sequencing timing diagrams (continued)
TPS707xxPWP
(Fixed Output Option)
application conditions not shown in block diagram:
V
I
V
OUT1
V
OUT1
V
IN1
V
and V
are tied to the same fixed input
IN1
IN2
voltage greater than the V
; SEQ is tied to
UVLO
0.1 µF
10 µF
V
SENSE1
logic high; PG1 is tied to MR2; MR1 is left
unconnected and is therefore at logic high.
250 kΩ
PG1
MR2
explanation of timing diagrams:
MR2
V
IN2
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
SEQ at logic high, when EN is taken to logic low,
0.1 µF
RESET
MR1
RESET
MR1
V
turns on. V
turns on after V
OUT2
OUT1 OUT2
reaches 83% of its regulated output voltage.
When V reaches 95% of its regulated output
EN
EN
>2 V
OUT1
voltage, PG1 (tied to MR2) goes to logic high.
When both V and V reach 95% of their
V
SENSE2
<0.7 V
OUT1
OUT2
SEQ
respective regulated output voltages and both
MR1 and MR2 (tied to PG1) are at logic high,
RESET is pulled to logic high after a 120 ms delay.
When EN is returned to logic high, both devices
turn off and both PG1 (tied to MR2) and RESET
return to logic low.
V
OUT2
V
OUT2
10 µF
EN
SEQ
V
V
OUT2
95%
83%
95%
83%
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V and V
120ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
OUT1
Figure 37. Timing When SEQ = High
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
sequencing timing diagrams (continued)
TPS707xxPWP
(Fixed Output Option)
application conditions not shown in block diagram:
V
I
V
OUT1
V
V
OUT1
IN1
IN2
V
and V
are tied to the same fixed input
IN1
IN2
voltage greater than the V
; SEQ is tied to
UVLO
0.1 µF
10 µF
V
logic high; PG1 is tied to MR2; MR1 is initially at
logic high but is eventually toggled.
SENSE1
250 kΩ
PG1
MR2
explanation of timing diagrams:
MR2
V
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
0.1 µF
RESET
RESET
MR1
SEQ at logic high, when EN is taken low, V
OUT2
turnson.V
turnsonafterV
reaches83%
OUT1
OUT2
MR1
of its regulated output voltage. When V
EN
OUT1
EN
2 V
reaches 95% of its regulated output voltage, PG1
(tiedtoMR2)goestologichigh.WhenbothV
>2 V
0.7 V
OUT1
V
<0.7 V
SENSE2
and V
reach 95% of their respective
OUT2
SEQ
regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to
logic high after a 120 ms delay. When MR1 is
taken low, RESET returns to logic low but the
V
OUT2
V
OUT2
10 µF
outputs remain in regulation. When MR1 is returned to logic high, since both V
95% of their respective regulated output voltages and MR2 (tied to PG1) remains at logic high, RESET is pulled
and V
remain above
OUT1
OUT2
to logic high after a 120 ms delay.
EN
SEQ
V
V
95%
83%
OUT2
95%
83%
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V and V
120 ms
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
OUT1
Figure 38. Timing When MR1 is Toggled
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
sequencing timing diagrams (continued)
TPS707xxPWP
(Fixed Output Option)
application conditions not shown in block diagram:
V
I
V
OUT1
V
OUT1
V
IN1
V
and V
are tied to the same fixed input
IN1
IN2
voltage greater than the V
; SEQ is tied to
UVLO
0.1 µF
10 µF
logic high; PG1 is tied to MR2; MR1 is left
unconnected and is therefore at logic high.
V
SENSE1
250 kΩ
explanation of timing diagrams:
PG1
MR2
MR2
V
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
SEQ at logic high, when EN is taken low, V
IN2
0.1 µF
RESET
MR1
RESET
MR1
OUT2
turnson.V
turnsonafterV
reaches83%
OUT1
OUT2
of its regulated output voltage. When V
reaches 95% of its regulated output voltage, PG1
(tiedtoMR2)goestologichigh.WhenbothV
OUT1
EN
EN
>2 V
OUT1
V
SENSE2
<0.7 V
and V
reach 95% of their respective
OUT2
regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to
logic high after a 120 ms delay. When a fault on
SEQ
V
OUT2
V
OUT2
10 µF
V
causes it to fall below 95% of its regulated
OUT1
output voltage, PG1 (tied to MR2) goes to logic
low, causing RESET to return to logic low. V
remains on because SEQ is high.
OUT2
EN
SEQUENCE
V
OUT2
OUT1
95%
83%
95%
83%
V
Fault on V
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
and V
OUT1
Figure 39. Timing When V
Faults Out
OUT1
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
TPS707xxPWP
(Fixed Output Option)
sequencing timing diagrams (continued)
V
I
V
OUT1
application conditions not shown in block diagram:
V
V
OUT1
IN1
IN2
V
and V
are tied to the same fixed input
IN1
IN2
voltage greater than the V
; SEQ is tied to
0.1 µF
10 µF
UVLO
V
SENSE1
logic high; PG1 is tied to MR2; MR1 is left
unconnected and is therefore at logic high.
250 kΩ
PG1
MR2
explanation of timing diagrams:
MR2
V
EN is initially high; therefore, both regulators are
off and PG1 and RESET are at logic low. With
0.1 µF
RESET
MR1
RESET
MR1
SEQ at logic high, when EN is taken low, V
OUT2
turnson.V
turnsonafterV
reaches83%
OUT1
OUT2
of its regulated output voltage. When V
EN
OUT1
EN
reaches 95% of its regulated output voltage, PG1
>2 V
(tiedtoMR2)goestologichigh.WhenbothV
V
OUT1
SENSE2
<0.7 V
and V
reach 95% of their respective
OUT2
SEQ
regulated output voltages and both MR1 and MR2
(tied to PG1) are at logic high, RESET is pulled to
logic high after a 120 ms delay. When a fault on
V
OUT2
V
OUT2
10 µF
V
causes it to fall below 95% of its regulated
OUT2
outputvoltage,RESETreturnstologiclowandV
beginstopowerdownbecauseSEQishigh.WhenV
OUT1
OUT1
falls below 95% of its regulated output voltage, PG1 (tied to MR2) returns to logic low.
ENABLE
SEQUENCE
95%
83%
V
V
OUT2
Fault on V
OUT2
95%
83%
OUT1
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
(see Note A)
NOTE A: t1 – Time at which both V
and V
OUT1
Figure 40. Timing When V
Faults Out
OUT2
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
split voltage DSP application
Figure 41 shows a typical application where the TPS70751 is powering up a DSP. In this application by grounding
the SEQ pin, V
(I/O) will be powered up first, and then V
(core).
OUT1
OUT2
TPS70751 PWP
DSP
I/O
3.3 V
V
OUT1
5 V
V
IN1
IN2
10 µF
0.1 µF
250 kΩ
V
SENSE1
PG1
PG1
MR2
MR2
MR1
>2 V
V
250 kΩ
<0.7 V
0.1 µF
RESET
RESET
MR1
EN
>2 V
>2 V
EN
<0.7 V
<0.7 V
V
SENSE2
SEQ
1.8 V
V
OUT2
Core
10 µF
EN
SEQ
V
OUT2
(Core)
95%
83%
V
OUT1
(I/O)
95%
83%
PG1
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V and V
120 ms
are greater than the PG thresholds and MR1 is logic high.
OUT2
OUT1
Figure 41. Application Timing Diagram (SEQ = Low)
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
split voltage DSP application (continued)
Figure 42 shows a typical application where the TPS70751 is powering up a DSP. In this application by pulling
up the SEQ pin, V
(Core) will be powered up first, and then V
(I/O).
OUT2
OUT1
TPS70751 PWP
DSP
I/O
5 V
3.3 V
V
OUT1
V
IN1
IN2
10 µF
0.1 µF
250 kΩ
V
SENSE1
PG1
PG1
MR2
MR2
MR1
>2 V
V
250 kΩ
<0.7 V
0.1 µF
RESET
RESET
MR1
>2 V
EN
>2 V
EN
<0.7 V
<0.7 V
V
SENSE2
SEQ
1.8 V
V
OUT2
Core
10 µF
EN
SEQ
V
OUT2
95%
83%
(Core)
95%
83%
V
OUT1
(I/O)
PG1
RESET
t1
(see Note A)
NOTE A: t1 – Time at which both V
120 ms
and V
are greater than the PG thresholds and MR1 is logic high.
OUT2
OUT1
Figure 42. Application Timing Diagram (SEQ = High)
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
input capacitor
For a typical application, an input bypass capacitor (0.1 µF – 1 µF) is recommended. This capacitor will filter
any high frequency noise generated in the line. For fast transient condition where droop at the input of the LDO
may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The
size of this capacitor is dependant on the output current and response time of the main power supply, as well
as the distance to the V pins of the LDO.
I
output capacitor
As with most LDO regulators, the TPS707xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance values are 10 µF ceramic
capacitors with an ESR (equivalent series resistance) between 50 mΩ and 2.5 Ω or 6.8 µF tantalum capacitors
with ESR between 250 mΩ and 4 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic
capacitors with capacitance values greater than 10 µF are all suitable, provided they meet the requirements
described above. Larger capacitors provide a wider range of stability and better load transient response. Below
is a partial listing of surface-mount capacitors usable with the TPS707xx. for fast transient response application.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the
user’s application. When necessary to achieve low height requirements along with high output current and/or
high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
†
VALUE
22 µF
33 µF
47 µF
68 µF
MFR.
Kemet
Sanyo
Sanyo
Sanyo
MAX ESR
345 mΩ
100 mΩ
100 mΩ
45 mΩ
PART NO.
7495C226K0010AS
10TPA33M
6TPA47M
10TPC68M
ESR and transient response
LDOs typically require an external output capacitor for stability. In fast transient response applications,
capacitors are used to support the load current while LDO amplifier is responding. In most applications, one
capacitor is used to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are
resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the
inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any
capacitor can therefore be drawn as shown in Figure 43.
R
L
ESL
ESR
C
Figure 43. – ESR and ESL
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application
focuses mainly on the parasitic resistance ESR.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
Figure 44 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
I
O
LDO
–
R
V
ESR
ESR
+
+
V
V
–
I
O
R
LOAD
C
O
Figure 44. LDO Output Stage With Parasitic Resistances ESR
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V(C ) = V ). This means no current is flowing into the C
O
O
O
branch. If I suddenly increases (transient condition), the following occurs:
O
The LDO is not able to supply the sudden current need due to its response time (t in Figure 45). Therefore,
1
capacitor C provides the current for the new load condition (dashed arrow). C now acts like a battery with
O
O
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at R
.
ESR
This voltage is shown as V
in Figure 44.
ESR
When C is conducting current to the load, initial voltage at the load will be V = V(C ) – V . Due to the
ESR
O
O
O
discharge of C , the output voltage V will drop continuously until the response time t of the LDO is reached
O
O
1
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches
the regulated voltage. This period is shown as t in Figure 45.
2
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
The higher the ESR, the larger the droop at the beginning of load transient.
The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
I
O
V
O
1
2
ESR 1
ESR 2
3
ESR 3
t
t
1
2
Figure 45. – Correlation of Different ESRs and Their Influence to the Regulation of V at a
O
Load Step From Low-to-High Output Current
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
APPLICATION INFORMATION
programming the TPS70702 adjustable LDO regulator
The output voltage of the TPS70702 adjustable regulators is programmed using external resistor dividers as
shown in Figure 46.
Resistors R1 and R2 should be chosen for approximately 7 µA divider current. Lower value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at the sense terminal increase the output voltage error. The recommended design procedure is to
choose R2 = 169 kΩ to set the divider current at approximately 7 µA and then calculate R1 using:
V
O
R1
1
R2
V
ref
Where:
V
= 1.224 V typ (the internal reference voltage)
ref
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS70702
OUTPUT
VOLTAGE
V
I
R1
R2
UNIT
IN
0.1 µF
2.5 V
3.3 V
3.6 V
174
287
324
169
169
169
kΩ
kΩ
kΩ
>2.0 V
EN
OUT
FB
V
O
<0.7V
+
R1
GND
R2
Figure 46. TPS70702 Adjustable LDO Regulator Programming
regulator protection
Both TPS707xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS707xx also features internal current limiting and thermal protection. During normal operation, the
TPS707xx regulator 1 limits output current to approximately 1.6 A (typ) and regulator 2 limits output current to
approximately 750 mA (typ). When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator
operation resumes.
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P
, and the actual dissipation, P , which must be less than
D(max)
D
or equal to P
.
D(max)
The maximum-power-dissipation limit is determined using the following equation:
T max
J
T
A
P
D(max)
R
JA
Where:
T max is the maximum allowable junction temperature.
J
R
is the thermal resistance junction-to-ambient for the package, i.e., 32.6°C/W for the 20-terminal
θJA
PWP with no airflow.
T is the ambient temperature.
A
The regulator dissipation is calculated using:
P
V
V
I
D
I
O
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS70745, TPS70748, TPS70751, TPS70758, TPS70702
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS291 – MAY 2000
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,65
20
M
0,10
0,19
11
Thermal Pad
(See Note D)
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
1
10
0,25
A
0°–8°
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
28
DIM
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
A MAX
A MIN
4073225/E 03/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusions.
D. Thepackagethermalperformancemaybeenhancedbybondingthethermalpadtoanexternalthermalplane.Thispadiselectrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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