TPS70848PWPRG4_技术文档

TPS70845, TPS70848

TPS70851, TPS70858

TPS70802

www.ti.com

SLVS301D–JUNE 2000–REVISED DECEMBER 2007

DUAL-OUTPUT, LOW DROPOUT VOLTAGE REGULATORS

WITH INTEGRATED SVS FOR SPLIT VOLTAGE SYSTEMS

1

FEATURES

DESCRIPTION

23

•

Dual Output Voltages for Split-Supply

The TPS708xx is a low dropout voltage regulator with

integrated SVS (RESET, POR, or power on reset)

and power good (PG) functions. These devices are

capable of supplying 250 mA and 125 mA by

regulator 1 and regulator 2 respectively. Quiescent

current is typically 190 µA at full load. Differentiated

features, such as accuracy, fast transient response,

SVS supervisory circuit (power on reset), manual

reset input, and independent enable functions provide

a complete system solution.

Applications

•

Independent Enable Functions (See Part

Number TPS707xx for Sequenced Outputs)

Output Current Range of 250 mA on Regulator

1 and 125 mA on Regulator 2

Voltage Options: 3.3-V/2.5-V, 3.3-V/1.8-V,

3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable

Outputs

•

Open Drain Power-On Reset with 120-ms Delay

PWP PACKAGE

(TOP VIEW)

Open Drain Power Good for Regulator 1 and

Regulator 2

NC

1

20

19

18

17

16

15

14

13

12

11

NC

V

•

Ultralow 190-µA (typ) Quiescent Current

1-µA Input Current During Standby

V

2

IN1

OUT1

V

3

OUT1

/FB1

/FB2

4

MR

SENSE1

Low Noise: 65 µV_RMSWithout Bypass

Capacitor

5

PG1

EN1

EN2

6

PG2

V

•

Quick Output Capacitor Discharge Feature

One Manual Reset Input

7

RESET

GND

SENSE2

V

8

OUT2

V

9

OUT2

IN2

2% Accuracy Over Load and Temperature

Undervoltage Lockout (UVLO) Feature

20-Pin PowerPAD™ TSSOP Package

Thermal Shutdown Protection

V

10

NC

IN2

NC: No internal connection

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

3

PowerPAD is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS70845, TPS70848

TPS70851, TPS70858

TPS70802

www.ti.com

SLVS301D–JUNE 2000–REVISED DECEMBER 2007

TPS70851PWP

I/O

3.3 V

V

OUT1

5V

IN1

10 mF

0.1 mF

V

SENSE1

250 kW

PG1

250 kW

PG1

MR

>2 V

V

IN2

<0.7 V

0.1 mF

RESET

PG2

RESET

PG2

EN1

>2 V

EN1

EN2

<0.7 V

EN2

V

SENSE2

1.8 V

V

Core

OUT2

10 mF

DESCRIPTION (CONTINUED)

The TPS708xx family of voltage regulators offers very low dropout voltage and dual outputs. These devices have

extremely low noise output performance without using any added filter bypass capacitors and are designed to

have a fast transient response and be stable with 10-µF low ESR capacitors.

These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable voltage options.

Regulator 1 can support up to 250 mA, and regulator 2 can support up to 125 mA. Separate voltage inputs allow

the designer to configure the source power.

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV on

regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is a

voltage-driven device, the quiescent current is very low and independent of output loading (maximum of 230 µA

over the full range of output current and full range of temperature). This LDO family also features a sleep mode;

applying a high signal to EN1 or EN2 (enable) shuts down regulator 1 or regulator 2, respectively. When a high

signal is applied to both EN1 and EN2, both regulators enter sleep mode, thereby reducing the input current to 2

µA at T_J= +25°C.

For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator

is turned off (disabled).

The PG1 pin reports the voltage condition at V_OUT1. The PG1 pin can be used to implement a SVS (RESET,

POR, or power on reset) for the circuitry supplied by regulator 1. The PG2 pin reports the voltage conditions at

V_OUT2. The PG2 pin can be used to implement a SVS (power on reset) for the circuitry supplied by regulator 2.

The TPS708xx features a RESET (SVS, POR, or power on reset). RESET output initiates a reset in the event of

an undervoltage condition. RESET also indicates the status of the manual reset pin (MR). When MR is in the

logic high state, RESET goes to a high impedance state after a 120-ms delay. To monitor V_OUT1, the PG1 output

pin can be connected to MR. To monitor V_OUT2, the PG2 output pin can be connected to MR.

The device has an undervoltage lockout UVLO circuit that prevents the internal regulators from turning on until

V_IN1reaches 2.5V.

2

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION⁽¹⁾

VOLTAGE (V)⁽²⁾

PACKAGE-

LEAD

(DESIGNATOR)

SPECIFIED

TEMPERATURE

RANGE (T_J)

ORDERING

NUMBER

TRANSPORT

MEDIA, QUANTITY

PRODUCT

V_OUT1

V_OUT2

TPS70802PWP

TPS70802PWPR

TPS70845PWP

TPS70845PWPR

TPS70848PWP

TPS70848PWPR

TPS70851PWP

TPS70851PWPR

TPS70858PWP

TPS70858PWPR

Tube, 70

Tape and Reel, 2000

Tube, 70

TPS70802

Adjustable

Adjustable HTSSOP-20 (PWP)

–40°C to +125°C

TPS70845

TPS70848

TPS70851

TPS70858

3.3 V

1.2 V

1.5 V

1.8 V

2.5 V

HTSSOP-20 (PWP)

Tape and Reel, 2000

Tube, 70

Tape and Reel, 2000

Tube, 70

Tape and Reel, 2000

Tube, 70

Tape and Reel, 2000

(1) For the most current package and ordering information see the Package Option Addendum located at the end of this document, or see

the TI web site at www.ti.com.

(2) For fixed 1.20 V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

TPS708xx

UNIT

V

(2)

Input voltage range: V_IN1, V_IN2

Voltage range at EN1, EN2

–0.3 to +7

V

Output voltage range (V_OUT1, V_SENSE1

Output voltage range (V_OUT2, V_SENSE2

Maximum RESET, PG1, PG2 voltage

Maximum MR voltage

)

5.5

V

)

5.5

V

7

V

V_IN1

Internally limited

See Dissipation Ratings Table

–40 to +150

V

Peak output current

—

°C

kV

Continuous total power dissipation

Operating virtual junction temperature range, T_J

Storage temperature range, T_stg

ESD rating, HBM

–65 to +150

2

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are tied to network ground.

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

DISSIPATION RATINGS

DERATING

FACTOR

PACKAGE

AIR FLOW (CFM)

T_A≤ +25°C

T_A= +70°C

T_A= +85°C

0

3.067 W

4.115 W

30.67 mW/°C

41.15 mW/°C

1.687 W

2.265 W

1.227 W

1.646 W

PWP⁽¹⁾

250

(1) This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on a 4-in by 4-in ground

layer. Simultaneous and continuous operation of both regulator outputs at full load may exceed the power dissipation rating of the PWP

package. For more information, refer to TI technical brief SLMA002.

RECOMMENDED OPERATING CONDITIONS

Over operating temperature range (unless otherwise noted).

MIN

2.7

0

MAX

6

UNIT

V

Input voltage, V_I⁽¹⁾(regulator 1 and 2)

Output current, I_O(regulator 1)

500

250

5.5

mA

V

Output current, I_O(regulator 2)

0

Output voltage range (for adjustable option)

Operating virtual junction temperature, T_J

1.22

–40

+125

°C

(1) To calculate the minimum input voltage for maximum output current, use the following equation: V_I(min)= V_O(max)+ V_{DO(max load)}

.

4

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

ELECTRICAL CHARACTERISTICS

Over recommended operating junction temperature range (T_J= –40°C to +125°C), V_IN1or V_IN2= V_OUT(nom)+ 1 V, I_O= 1 mA,

EN = 0 V, and C_OUT= 33 µF (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

2.7 V < V_IN< 6 V,

T_J= +25°C

FB connected to V_O

1.22

Reference

voltage

2.7 V < V_IN< 6 V,

2.8 V < V_IN< 6 V,

3.5 V < V_IN< 6 V,

4.3 V < V_IN< 6 V,

FB connected to V_O

1.196

1.176

1.47

1.244

1.224

T_J= +25°C

1.2

1.5

1.8

2.5

3.3

190

1.2 V Output

1.5 V Output

1.8 V Output

2.5 V Output

3.3 V Output

T_J= +25°C

Output

voltage

1.53

1.836

2.55

V_O

V

(1),(2)

1.764

2.45

3.234

3.366

(2)

Quiescent current (GND current) for

regulator 1 and regulator 2, EN1 = EN2

= 0 V⁽¹⁾

See

µA

(2)

See

230

0.1

V_O+ 1 V < V_IN≤ 6 V,

V_O+ 1 V < V_IN≤ 6 V

T_J= +25°C

T_J= +25°C⁽¹⁾

(1)

0.01

Output voltage line regulation (∆V_O/V_O)

for regulator 1 and regulator 2

%V

mV

(3)

Load regulation for V_{OUT 1}and V_OUT2

1

65

Regulator 1

Regulator 2

Regulator 1

Regulator 2

Output noise

voltage

V_n

BW = 300 Hz to 50 kHz,

V_OUT= 0 V

C_O= 33 µF, T_J= +25°C

µV_RMS

65

1.6

1.9

1

Output current limit

A

0.750

+150

Thermal shutdown junction temperature

°C

µA

Regulator 1

Regulator 2

EN1 = V_IN, EN2 = V_IN

T_J= +25°C

2

6

I_I

Standby

(standby) current

f = 1 kHz, C_OUT= 33 µF,

I_OUT1= 250 mA

Regulator 1

Regulator 2

T_J= +25°C⁽¹⁾

60

50

Power-

supply ripple

rejection

PSRR

dB

V

f = 1 kHz, C_OUT= 33 µF,

I_OUT2= 125 mA

UVLO threshold

2.4

80

2.65

RESET Terminal

Minimum input voltage for valid RESET I_(RESET)= 300 µA,

V

_(RESET)≤ 0.8 V

1.0

120

1.3

160

0.4

1

V

ms

V

t_(RESET)

RESET pulse duration

V_IN= 3.5 V,

Output low voltage

Leakage current

I_(RESET)= 1 mA

0.15

V_(RESET)= 6 V

µA

(1) Minimum input operating voltage is 2.7 V or V_O(typ)+ 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output

current = 1 mA.

(2) I_O= 1 mA to 250 mA for Regulator 1 and 1 mA to 125 mA for Regulator 2.

(V_Imax- 2.7)

Line regulation (mV) = (%/V) x V_o

x 1000

100

[V_Imax- (V_o+ 1)]

(3) If V_O< 1.8 V then V_Imax= 6 V, V_Imin= 2.7 V:

Line regulation (mV) = (%/V) x V_o

x 1000

100

If V_O> 2.5 V then V_Imax= 6 V, V_Imin= V_O+ 1 V:

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

Over recommended operating junction temperature range (T_J= –40°C to +125°C), V_IN1or V_IN2= V_OUT(nom)+ 1 V, I_O= 1 mA,

EN = 0 V, and C_OUT= 33 µF (unless otherwise noted).

PARAMETER

PG1/PG2 Terminal

TEST CONDITIONS

MIN

TYP

MAX UNIT

Minimum input voltage for valid PGx

Trip threshold voltage

Hysteresis voltage

I_(PGx)= 300 µA,

V_Odecreasing

Measured at V_O

Rising edge deglitch

V_IN= 2.7V,

V

_(PGx)≤ 0.8 V

1.0

95

1.3

V

92

98 %V_OUT

%V_OUT

µs

0.5

30

t_r(PGx)

Output low voltage

Leakage current

I_(PGx)= 1 mA

0.15

0.4

1

V

V_(PGx)= 6V

µA

EN1/EN2 Terminal

High-level ENx input voltage

Low-level ENx input voltage

Input current (ENx)

MR Terminal

2

–1

2

V

0.7

1

µA

High-level input voltage

Low-level input voltage

Falling edge delay

V

0.7

Measured at V_O

140

6

µs

µA

Pull-up current source

V_OUT1Terminal

I_O= 250 mA, V_IN1= 3.2 V

2 ms pulse width

T_J= +25°C

83

Dropout voltage⁽⁴⁾

mV

140

Peak output current

Discharge transistor current

V_OUT2Terminal

750

7.5

mA

V_OUT1= 1.5 V

Peak output current

Discharge transistor current

FB Terminal

2 ms pulse width

V_OUT2= 1.5 V

375

7.5

mA

Input current: TPS70802

FB = 1.8 V

1

µA

(4) Input voltage (V_IN1or V_IN2) = V_O(typ)– 100 mV. For 1.5-V, 1.8-V, and 2.5-V regulators, the dropout voltage is limited by input voltage

range. The 3.3-V regulator input is set to 3.2 V to perform this test.

6

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

DEVICE INFORMATION

Fixed Voltage Version

V

(2 Pins)

IN1

V

(2 Pins)

OUT1

UVLO

Comp

10 kW

Current

Sense

-

ENA_1

SENSE1

+

2.5 V

(see Note A)

-

+

ENA_1

Reference

V

ref

FB1

GND

Thermal

V

ref

Shutdown

PG1

-

V

SENSE1

Rising Edge

Deglitch

+

0.95 x Vref

V

IN1

PG1

Comp

MR

RESET

Falling Edge

Delay

ENA_1

EN1

PG2

Comp

-

V

SENSE2

Rising Edge

Deglitch

0.95 x V

ref

+

ENA_2

V

ref

FB2

EN2

-

+

ENA_2

V

SENSE2

Current

Sense

ENA_2

(see Note A)

10 kW

V

(2 Pins)

OUT2

V

(2 Pins)

IN2

A. For most applications, V_SENSE1and V_SENSE2should be externally connected to V_OUT1and V_OUT2, respectively, as

close as possible to the device. For other implementations, refer to SENSE terminal connection discussion in the

Application Information section.

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

Adjustable Voltage Version

V

(2 Pins)

IN1

V

(2 Pins)

OUT1

UVLO

Comp

Current

Sense

-

FB1

ENA_1

+

2.5 V

(see Note A)

-

+

ENA_1

Reference

V

ref

GND

Thermal

V

ref

Shutdown

PG1

-

FB1

0.95 x V

Rising Edge

Deglitch

+

V

ref

IN1

PG1

Comp

MR

RESET

Falling Edge

Delay

ENA_1

EN1

PG2

Comp

-

FB2

0.95 x V

Rising Edge

Deglitch

+

ref

ENA_2

V

ref

FB2

EN2

-

+

ENA_2

FB2

Current

Sense

ENA_2

(see Note A)

V (2 Pins)

OUT2

V

(2 Pins)

IN2

A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the

device. For other implementations, refer to FB terminals connection discussion in the Application Information

section.

8

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

RESET Timing Diagram

V

IN1

V

UVLO

V

UVLO

V

RES

(see Note A)

t

MR Input

t

RESET Output

120 ms

Delay

120 ms

Delay

Output

Undefined

t

NOTE A: V_RESis the minimum input voltage for a valid RESET. The symbol V_RESis not currently listed within EIA or JEDEC

standards for semiconductor symbology.

PG1 Timing Diagram

V

IN1

V

UVLO

V

UVLO

V

PG1

V

PG

(see Note A)

t

V

OUT1

V

IT+

(see Note B)

Threshold

Voltage

V

IT-

(see Note B)

t

PG1 Output

Output

PG1

Output

Undefined

t

NOTES A: V_PG1is the minimum input voltage for a valid PG. The symbol V_PG1is not currently listed within EIA or JEDEC

standards for semiconductor symbology.

NOTES B: V_IT-trip voltage is typically 5% lower than the output voltage (95%V_O). V_IT-to V_IT+is the hysteresis voltage.

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

PG2 Timing Diagram (assuming V_IN1already powered up)

V

IN2

t

V

OUT2

V

IT+

(see Note A)

Threshold

Voltage

V

IT-

(see Note A)

t

PG2

Output

t

NOTE A: V_IT-trip voltage is typically 5% lower than the output voltage (95%V_O). V_IT-to V_IT+is the hysteresis voltage.

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

EN1

NO.

5

6

I

Active low enable for V_OUT1

EN2

Active low enable for V_OUT2

GND

8

—

I

Ground

MR

4

Manual reset input, active low, pulled up internally

No connection

NC

1, 11, 20

16

—

O

I

PG1

Open drain output, low when V_OUT1voltage is less than 95% of the nominal regulated voltage

Open drain output, low when V_OUT2voltage is less than 95% of the nominal regulated voltage

Open drain output, SVS (power-on reset) signal, active low

Input voltage of regulator 1

PG2

15

RESET

V_IN1

7

2, 3

9, 10

18, 19

12, 13

14

I

V_IN2

I

Input voltage of regulator 2

V_OUT1

V_OUT2

V_SENSE2/FB2

V_SENSE1/FB1

O

I

Output voltage of regulator 1

Output voltage of regulator 2

Regulator 2 output voltage sense/regulator 2 feedback for adjustable

Regulator 1 output voltage sense/regulator 1 feedback for adjustable

17

I

10

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

Detailed Description

The TPS708xx low dropout regulator family provides dual regulated output voltages with independent enable

functions. These devices provide fast transient response and high accuracy with small output capacitors, while

drawing low quiescent current. Other features are integrated SVS (power-on reset, RESET) and power good

(PG1, PG2) that monitor output voltages and provide logic output to the system. These differentiated features

provide a complete power solution.

The TPS708xx, unlike many other LDOs, features very low quiescent current that remains virtually constant even

with varying loads. Conventional LDO regulators use a PNP pass element, the base current of which is directly

proportional to the load current through the regulator (I_B= I_C/β). The TPS708xx uses a PMOS transistor to pass

current; because the gate of the PMOS is voltage-driven, operating current is low and stable over the full load

range.

Pin Functions

Enable (EN1, EN2)

The EN terminals are inputs that enable or shut down each respective regulator. If EN is at a voltage high signal,

the respective regulator is in shutdown mode. When EN goes to voltage low, the respective regulator is enabled.

Power-Good (PG1, PG2)

The PG terminals are open drain, active high output terminals that indicate the status of each respective

regulator. When V_OUT1reaches 95% of its regulated voltage, PG1 goes to a high impedance state. When V_OUT2

reaches 95% of its regulated voltage, PG2 goes to a high impedance state. Each PG goes to a low impedance

state when its respective output voltage is pulled below 95% (that is, goes to an overload condition) of its

regulated voltage. The open drain outputs of the PG terminals require a pull-up resistor.

Manual Reset Pin

MR is an active low input terminal used to trigger a reset condition. When MR is pulled to logic low, a POR

(RESET) occurs. The terminal has a 6-µA pull-up current to V_IN1

.

Sense (V_SENSE1, V_SENSE2

)

The sense terminals of fixed-output options must be connected to the regulator outputs, and the connection

should be as short as possible. Internally, the sense terminal connects to high-impedance, wide-bandwidth

amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential

to route the sense connection in such a way as to minimize or avoid noise pickup. Adding RC networks between

sense terminals and V_OUTterminals to filter noise is not recommended because these networks can cause the

regulators to oscillate.

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FB1 and FB2

FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external

feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them

in such a way as to minimize or avoid noise pickup. Adding RC networks between FB terminals and V_OUT

terminals to filter noise is not recommended because these networks can cause the regulators to oscillate.

RESET Indicator

The TPS708xx features a RESET (SVS, POR, or power on reset). RESET can be used to drive power on reset

circuitry or a low-battery indicator. RESET is an active low, open drain output that indicates the status of the

manual reset pin (MR). When MR is in a high-impedance state, RESET goes to a high impedance state after a

120-ms delay. To monitor V_OUT1, the PG1 output pin can be connected to MR. To monitor V_OUT2, the PG2 output

pin can be connected to MR. The open drain output of the RESET terminal requires a pull-up resistor. If RESET

is not used, it can be left floating.

V_IN1and V_IN2

V_IN1and V_IN2are inputs to each regulator. Internal bias voltages are powered by V_IN1

.

V_OUT1and V_OUT2

V_OUT1and V_OUT2are output terminals of each regulator.

12

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

TYPICAL CHARACTERISTICS

Table of Graphs

FIGURE

vs Output current

vs Junction temperature

vs Frequency

Figure 1 to Figure 3

Figure 4 to Figure 5

Figure 6

V_O

Output voltage

Ground current

PSRR

Z_O

Power-supply rejection ratio

Output spectral noise density

Output impedance

Figure 7 to Figure 10

Figure 11 to Figure 14

Figure 15 to Figure 18

Figure 19 and Figure 20

Figure 21 and Figure 22

Figure 23 and Figure 24

Figure 25

vs Frequency

vs Temperature

vs Input voltage

Dropout voltage

Load transient response

Line transient response (V_OUT1

Line transient response (V_OUT2

Output voltage

)

Figure 26

V_O

vs Time (start-up)

vs Output current

Figure 27 and Figure 28

Figure 30 to Figure 33

Equivalent series resistance (ESR)

TPS70851

OUTPUT VOLTAGE

vs

TPS70851

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

3.303

3.302

3.301

3.3

1.802

1.801

1.800

1.799

1.798

1.797

V

T

= 4.3 V

IN1

V

T

= 2.8 V

IN2

= +25°C

J

= +25°C

J

V

OUT1

V

OUT2

3.299

3.298

3.297

1.796

1.795

3.296

3.295

0

0.05

0.1

0.15

0.2

0.25

0

0.025

0.05

0.075

0.1

0.125

I

- Output Current - A

I

- Output Current - A

O

Figure 1.

Figure 2.

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SLVS301D–JUNE 2000–REVISED DECEMBER 2007

TPS70845

OUTPUT VOLTAGE

vs

TPS70851

OUTPUT VOLTAGE

vs

OUTPUT CURRENT

JUNCTION TEMPERATURE

1.201

1.200

3.35

3.33

V

= 4.3 V

V

T

= 2.7 V

IN1

IN2

= +25°C

OUT1

J

V

OUT2

I

O

= 250 mA

1.199

1.198

1.197

3.31

3.29

I

O

= 1 mA

3.27

3.25

3.23

1.196

1.195

-40 -25 -10

5

20 35 50 65 80 95 110 125

0

0.025

0.05

0.075

0.1

0.125

T

- Junction Temperature - °C

J

I

- Output Current - A

O

Figure 3.

Figure 4.

TPS70851

GROUND CURRENT

vs

OUTPUT VOLTAGE

vs

JUNCTION TEMPERATURE

210

1.85

1.83

1.81

1.79

1.77

1.75

1.73

V

= 2.8 V

IN2

Regulator 1 and Regulator 2

OUT2

200

190

I

= 1 mA

OUT1

I

= 1 mA

I

O

= 1 mA

OUT2

180

170

I

O

= 250 mA

I

= 250 mA

= 125 mA

OUT1

OUT2

160

150

40 25 10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T

- Junction Temperature - °C

T

- Junction Temperature - °C

J

Figure 5.

Figure 6.

14

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TPS70851

POWER-SUPPLY REJECTION RATIO

vs

FREQUENCY

10

0

-10

I = 250 mA

O

I

= 10 mA

O

C

V

= 22 mF

O

-20

-30

-40

C

= 22 mF

O

V

OUT1

-10

-20

OUT1

-30

-40

-50

-60

-70

-50

-60

-70

-80

-90

-80

-90

10

100

1 k

10 k

100 k

1 M

10

100

1 k

10 k

100 k

1 M

f - Frequency - Hz

Figure 7.

Figure 8.

TPS70851

POWER-SUPPLY REJECTION RATIO

vs

FREQUENCY

-10

-20

10

0

I

= 10 mA

O

I

= 150 mA

O

C

V

= 22 mF

O

C

V

= 22 mF

O

OUT2

-10

-20

OUT2

-30

-40

-30

-40

-50

-60

-70

-60

-70

-80

-90

-80

-90

10

100

1 k

10 k

100 k

1 M

10

100

1 k

10 k

100 k

1 M

f - Frequency - Hz

Figure 9.

Figure 10.

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OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

10

V

I

= 4.3 V

V

I

= 4.3 V

IN1

= 3.3 V

= 250 mA

= 3.3 V

= 10 mA

OUT1

O

1

0.1

0.01

100

1 k

10 k

100 k

1 k

10 k

100 k

f - Frequency - Hz

Figure 11.

Figure 12.

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

10

V

I

= 2.8 V

V

I

= 2.8 V

IN2

= 1.8 V

OUT2

= 125 mA

= 10 mA

O

1

0.1

0.01

100

0.01

100

1 k

10 k

100

1 k

10 k

100 k

f - Frequency - Hz

Figure 13.

Figure 14.

16

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OUTPUT IMPEDANCE

vs

OUTPUT IMPEDANCE

vs

FREQUENCY

100

10

C

I

= 33 mF

O

= 33 mF

O

= 10 mA

I

= 250 mA

O

V

T

= 3.3 V

V

T

= 3.3 V

OUT1

= +25°C

OUT1

= +25°C

J

10

1

J

1

0.1

0.01

10

100

1 k

10 k

100 k

1 M

10 M

10

100

1 k

10 k

100 k

1 M

10 M

f - Frequency - Hz

Figure 15.

Figure 16.

OUTPUT IMPEDANCE

vs

OUTPUT IMPEDANCE

vs

FREQUENCY

10

100

C

= 33 mF

O

C

I

= 33 mF

O

I

= 10 mA

O

= 125 mA

O

V

T

= 1.8 V

OUT2

V

T

= 1.8 V

OUT2

= +25°C

J

10

1

J

1

0.1

0.01

0.1

10

100

1 k

10 k

100 k

1 M

10 M

10

100

1 k

10 k

100 k

1 M

10 M

f - Frequency - Hz

Figure 17.

Figure 18.

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TPS70851

DROPOUT VOLTAGE

vs

TPS70851

DROPOUT VOLTAGE

vs

TEMPERATURE

120

6

5

C

V

= 33 mF

C

V

= 33 mF

O

= 3.2 V

IN1

100

I

O

= 10 mA

I

O

= 250 mA

80

60

40

4

3

2

20

0

1

0

I

O

= 0 mA

-40 -25 -10

5

20 35 50 65 80 95 110 125

-40 -25 -10

5

20 35 50 65 80 95 110 125

T

- Junction Temperature - °C

T

- Junction Temperature - °C

J

Figure 19.

Figure 20.

TPS70802

DROPOUT VOLTAGE

vs

TPS70802

DROPOUT VOLTAGE

vs

INPUT VOLTAGE

140

250

I

= 250 mA

O

I

= 125 mA

O

V

OUT1

V

120

100

80

OUT2

T

= +125°C

200

J

T

= +125°C

J

T

J

= +25°C

J

150

100

T

= +25°C

J

60

T

= -40°C

40

T

= -40°C

J

50

0

20

0

2.5

3

3.5

4

4.5

5

2.5

3

3.5

4

4.5

5

V - Input Voltage - V

I

Figure 21.

Figure 22.

18

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LOAD TRANSIENT RESPONSE

C

T

= 33 mF

C

T

= 33 mF

O

= +25°C

250

0

125

0

J

V

= 3.3 V

V

= 1.8 V

OUT1

OUT2

20

0

20

0

-20

-40

-20

-40

-60

-80

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

0

0.2 0.4 0.6 0.8

1

1.2 1.4 1.6 1.8

2

T - Time - ms

Figure 23.

Figure 24.

LINE TRANSIENT RESPONSE

3.8

2.8

5.3

4.3

50

0

10

0

I

= 125 mA

I

= 250 mA

O

C

V

= 33 mF

C

V

= 33 mF

O

-50

-10

OUT2

OUT1

0

20 40 60 80 100 120 140 160 180 200

0

20 40 60 80 100 120 140 160 180 200

T - Time - ms

Figure 25.

Figure 26.

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OUTPUT VOLTAGE AND ENABLE VOLTAGE

vs

TIME (START-UP)

V = 1.5 V

O

V

= 3.3 V

O

C

I

= 33 mF

O

3

2

1

0

3

2

1

0

C

I

= 33 mF

O

= 125 mA

= 250 mA

O

V = Standby

OUT1

V

= Standby

OUT2

5

0

5

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

0

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

T - Time - ms

Figure 27.

Figure 28.

To Load

V_IN

IN

OUT

+

C_OUT

R_L

EN

GND

ESR

Figure 29. Test Circuit for Typical Regions of Stability

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TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE⁽¹⁾

vs

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE⁽¹⁾

vs

OUTPUT CURRENT

10

REGION OF INSTABILITY

V

= 3.3 V

O

V

= 3.3 V

O

C

T

= 10 mF

O

C

T

= 6.8 mF

O

= +25°C

J

= +25°C

J

1

0.1

50 mW

250 mW

REGION OF INSTABILITY

0.1

0.01

0

50

100

150

200

250

0

50

I

100

150

200

250

I

- Output Current - mA

O

Figure 30.

Figure 31.

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE⁽¹⁾

vs

TYPICAL REGION OF STABILITY

EQUIVALENT SERIES RESISTANCE⁽¹⁾

vs

OUTPUT CURRENT

10

REGION OF INSTABILITY

V

= 1.8 V

O

V

= 1.8 V

O

C

T

= 6,8 mF

O

C

T

= 10 mF

O

= +25°C

J

= +25°C

1

J

1

0.1

50 mW

250 mW

REGION OF INSTABILITY

0.1

0.01

0

25

50

75

100

125

0

25

50

75

100

125

I

- Output Current - mA

I

- Output Current - mA

O

Figure 32.

Figure 33.

⁽¹⁾Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any

series resistance added externally, and PWB trace resistance to C_O.

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APPLICATION INFORMATION

TPS708xxPWP

(Fixed Output Option)

Sequencing Timing Diagrams

V

OUT1

V

IN

This section provides a number of timing diagrams

showing how this device functions in different

configurations.

V

IN1

OUT1

10 mF

0.1 mF

V

SENSE1

Application condition: V_IN1and V_IN2are tied to the

same fixed input voltage greater than V_UVLO. PG2 is

tied to MR.

250 kW

PG1

MR

V

IN2

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 and PG2 (tied to MR) are

at logic low. Since MR is at logic low, RESET is also

at logic low. When EN1 is taken to logic low, V_OUT1

turns on. Later, when EN2 is taken to logic low, V_OUT2

turns on. When V_OUT1reaches 95% of its regulated

output voltage, PG1 goes to logic high. When V_OUT2

reaches 95% of its regulated output voltage, PG2

(tied to MR) goes to logic high. When V_IN1is greater

than V_UVLOand MR (tied to PG2) is at logic high,

RESET is pulled to logic high after a 120-ms delay.

When EN1 and EN2 return to logic high, both devices

power down and both PG1, PG2 (tied to MR2), and

RESET return to logic low.

RESET

0.1 mF

RESET

PG2

EN1

EN2

>2 V

<0.7 V

EN2

V

SENSE2

V

OUT2

V

OUT2

<0.7 V

10 mF

EN2

EN1

95%

V

OUT2

95%

V

OUT1

PG2

PG1

MR

(PG2 tied to MR)

RESET

t₁

120 ms

NOTES: A. t₁: Time at which V_INis greater than V_UVLOand MR is logic high.

B. The timing diagram is not drawn to scale.

Figure 34. Timing When V_OUT1Is Enabled Before V_OUT2

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Application condition: V_IN1and V_IN2are tied to the

same fixed input voltage greater than V_UVLO. MR is

initially logic high but is eventually toggled.

TPS708xxPWP

(Fixed Output Option)

V

IN

V

OUT1

V

OUT1

V

IN1

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 and PG2 are at logic low.

Since V_IN1is greater than V_UVLOand MR is at logic

high, RESET is also at logic high. When EN2 is taken

to logic low, V_OUT2turns on. Later, when EN1 is taken

to logic low, V_OUT1turns on. When V_OUT2reaches

95% of its regulated output voltage, PG2 goes to

logic high. When V_OUT1reaches 95% of its regulated

output voltage, PG1 goes to logic high. When MR is

taken to logic low, RESET is taken low. When MR

returns to logic high, RESET returns to logic high

after a 120-ms delay.

250 kW

0.1 mF

V

SENSE1

10 mF

250 kW

PG1

V

IN2

250 kW

0.1 mF

RESET

PG2

MR

EN1

EN2

>2 V

MR

2 V

V

0.7 V

OUT2

10 mF

<0.7 V

EN2

SENSE2

V

OUT2

<0.7 V

EN2

EN1

95%

V

OUT2

95%

V

OUT1

PG2

PG1

MR

RESET

t₁

120 ms

NOTES: A. t₁: Time at which V_INis greater than V_UVLOand MR is logic high.

B. The timing diagram is not drawn to scale.

Figure 35. Timing When MR is Toggled

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Application condition: V_IN1and V_IN2are tied to

same fixed input voltage greater than V_UVLO. PG1 is

tied to MR.

TPS708xxPWP

(Fixed Output Option)

V

OUT1

V

IN

V

OUT1

V

IN1

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 (tied to MR) and PG2 are

at logic low. Since MR is at logic low, RESET is also

at logic low. When EN2 is taken to logic low, V_OUT2

turns on. Later, when EN1 is taken to logic low, V_OUT1

turns on. When V_OUT2reaches 95% of its regulated

output voltage, PG2 goes to logic high. When V_OUT1

reaches 95% of its regulated output voltage, PG1

goes to logic high. When V_IN1is greater than V_UVLO

and MR (tied to PG2) is at logic high, RESET is

pulled to logic high after a 120-ms delay. When a

fault on V_OUT1causes it to fall below 95% of its

regulated output voltage, PG1 (tied to MR) goes to

logic low. Since MR is logic low, RESET goes to logic

low. V_OUT2is unaffected.

0.1 mF

10 mF

V

SENSE1

250 kW

PG1

MR

V

IN2

250 kW

RESET

0.1 mF

RESET

PG2

EN1

EN2

>2 V

V

SENSE2

<0.7 V

EN2

V

OUT2

V

OUT2

<0.7 V

10 mF

EN2

EN1

95%

V

OUT2

95%

V

OUT1

FAULT ON V_OUT1

PG2

PG1

MR

(PG1 tied to MR)

RESET

t₁

120 ms

NOTES: A. t₁: Time at which V_INis greater than V_UVLOand MR is logic high.

B. The timing diagram is not drawn to scale.

Figure 36. Timing When There is a Fault on V_OUT1

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APPLICATION INFORMATION

Input Capacitor

For a typical application, an input bypass capacitor (0.1 µF to 1 µF) is recommended. This capacitor will filter any

high frequency noise generated in the line. For fast transient conditions where droop at the input of the LDO may

occur because of high inrush current, it is recommended to place a larger capacitor at the input as well. The size

of this capacitor depends on the output current and response time of the main power supply, as well as the

distance to the V_Ipins of the LDO.

Output Capacitor

As with most LDO regulators, the TPS708xx requires an output capacitor connected between OUT and GND to

stabilize the internal control loop. The minimum recommended capacitance values are 10-µF ceramic capacitors

with an ESR (equivalent series resistance) between 50-mΩ and 2.5-Ω or 6.8-µF tantalum capacitors with ESR

between 250 mΩ and 4 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic capacitors

with capacitance values greater than 10 µF are all suitable, provided they meet the requirements described

above. Larger capacitors provide a wider range of stability and better load transient response. Table 1 gives a

partial listing of surface-mount capacitors suitable for use with the TPS708xx for fast transient response

application.

This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for user

applications. When necessary to achieve low height requirements along with high output current and/or high load

capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.

Table 1. Partial Listing of TPS708xx-Compatible Surface-Mount Capacitors

VALUE

22 µF

33 µF

47 µF

68 µF

MANUFACTURER

Kemet

MAX ESR

345 mΩ

100 mΩ

45 mΩ

MFR PART NO.

7495C226K0010AS

10TPA33M

Sanyo

6TPA47M

Sanyo

10TPC68M

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ESR and Transient Response

LDOs typically require an external output capacitor for stability. In fast transient response applications, capacitors

are used to support the load current while the LDO amplifier is responding. In most applications, one capacitor is

used to support both functions.

Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are

resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the

inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any

capacitor can therefore be drawn as shown in Figure 37.

R_SER

L_ESL

C

Figure 37. ESR and ESL

In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application

focuses mainly on the parasitic resistance ESR.

Figure 38 shows the output capacitor and its parasitic resistances in a typical LDO output stage.

I

OUT

LDO

-

ESR

R

ESR

V

+

V

I

V

OUT

R

LOAD

-

C

OUT

Figure 38. LDO Output Stage with Parasitic Resistances ESR

In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across

the capacitor is the same as the output voltage (V_(CO)= V_OUT). This condition means no current is flowing into the

C_Obranch. If I_OUTsuddenly increases (a transient condition), the following results occur:

•

The LDO is not able to supply the sudden current need because of its response time. Therefore, capacitor C_O

provides the current for the new load condition (dashed arrow). C_Onow acts like a battery with an internal

resistance, ESR. Depending on the current demand at the output, a voltage drop occurs at R_ESR. This voltage

is shown as V_ESRin Figure 38.

•

When C_Ois conducting current to the load, initial voltage at the load will be V_O= V_(CO)– V_ESR. As a result of

the discharge of C_O, the output voltage V_Odrops continuously until the response time t₁of the LDO is

reached and the LDO resumes supplying the load. From this point, the output voltage starts rising again until

it reaches the regulated voltage. This period is shown as t₂in Figure 39.

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I_OUT

V_OUT

1

2

3

ESR 1

ESR 2

ESR 3

t₁

t₂

Figure 39. Correlation of Different ESRs and Their Influence on the Regulation of V_Oat a Load Step from

Low-to-High Output Current

Figure 39 also shows the impact of different ESRs on the output voltage. The left brackets show different levels

of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.

From above, the following conclusions can be drawn:

•

The higher the ESR, the larger the droop at the beginning of load transient.

The smaller the output capacitor, the faster the discharge time and the greater the voltage droop during the

LDO response period.

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Programming the TPS70802 Adjustable LDO Regulator

The output voltage of the TPS70802 adjustable regulators is programmed using external resistor dividers as

shown in Figure 40.

Resistors R1 and R2 should be chosen for approximately a 50-µA divider current. Lower value resistors can be

used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage

currents at the sense terminal increase the output voltage error. The recommended design procedure is to

choose R2 = 30.1 kΩ to set the divider current at approximately 50 µA, and then calculate R1 using Equation 1:

V_OUT

R1 =

- 1 ´ R2

(

V_REF

(1)

where:

•

V_REF= 1.224 V typ (the internal reference voltage)

OUTPUT VOLTAGE

PROGRAMMING GUIDE

TPS70802

OUTPUT

VOLTAGE

V

I

R1

R2

UNIT

IN

0.1 mF

2.5 V

3.3 V

3.6 V

31.6

51.1

59.0

30.1

kW

>2.0 V

EN

OUT

FB

V

O

<0.7 V

+

R1

GND

R2

Figure 40. TPS70802 Adjustable LDO Regulator Programming

Regulator Protection

Both TPS708xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input

voltage drops below the output voltage (for example, during power-down). Current is conducted from the output

to the input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be

appropriate.

The TPS708xx also features internal current limiting and thermal protection. During normal operation, the

TPS708xx regulator 1 limits output current to approximately 1.6 A (typ) and regulator 2 limits output current to

approximately 750 mA (typ). When current limiting engages, the output voltage scales back linearly until the

overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be

taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds

+150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below +130°C (typ),

regulator operation resumes.

28

Submit Documentation Feedback

TPS70845, TPS70848

TPS70851, TPS70858

TPS70802

www.ti.com

SLVS301D–JUNE 2000–REVISED DECEMBER 2007

Power Dissipation and Junction Temperature

Specified regulator operation is assured to a junction temperature of +125°C; the maximum junction temperature

should be restricted to +125°C under normal operating conditions. This restriction limits the power dissipation the

regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,

calculate the maximum allowable dissipation, P_D(max), and the actual dissipation, P_D, which must be less than or

equal to P_D(max)

.

The maximum-power-dissipation limit is determined using the following equation:

T_Jmax *T_A

P_D(max)

+

R_qJA

(2)

where:

•

T_Jmaxis the maximum allowable junction temperature

R_θJAis the thermal resistance junction-to-ambient for the package, that is, 32.6°C/W for the 20-terminal PWP with no

airflow.

•

T_Ais the ambient temperature

The regulator dissipation is calculated using:

ǒ

Ǔ

P_D+ V_I*V_O I_O

(3)

Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal

protection circuit.

Submit Documentation Feedback

29

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS70851PWPR

HTSSOP PWP

20

2000

330.0

16.4

6.95

7.1

1.6

8.0

16.0

Q1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

HTSSOP PWP 20

SPQ

Length (mm) Width (mm) Height (mm)

367.0 367.0 38.0

TPS70851PWPR

2000

Pack Materials-Page 2

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型号：	TPS70848PWPRG4
厂家：	TEXAS INSTRUMENTS
描述：	IC VREG DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO20, GREEN, PLASTIC, HTSSOP-20, Fixed Positive Multiple Output LDO Regulator 光电二极管输出元件调节器
文件：	总37页 (文件大小：874K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS70848PWPRG4 [TI]

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