TPS70918QDRVRQ1 [TI]
具有反向电流保护功能的汽车类 150mA、30V、超低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;
| 型号： | TPS70918QDRVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有反向电流保护功能的汽车类 150mA、30V、超低 IQ、低压降稳压器 | DRV | 6 | -40 to 125 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总35页 (文件大小：2372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS709-Q1
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
具有使能功能的 TPS709-Q1 150mA、30V、1µA IQ 稳压器
1 特性
3 说明
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符合汽车应用 标准
具有符合 AEC Q100 标准的下列结果：
TPS709-Q1 系列线性稳压器是针对功耗敏感型应用设
计的超低静态电流 器件。一个精密带隙和误差放大器
在温度范围内的精度为 2%。只有 1µA 的静态电流使
得此器件成为由电池供电、要求非常小闲置状态功率耗
散的常开系统的理想解决方案。为了增加安全性，这些
器件还具有热关断、电流限制和反向电流保护功能。
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–
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器件温度等级 1：环境工作温度范围为 –40°C
至 125°C
器件人体放电模式 (HBM) 静电放电 (ESD) 分类
等级 2
器件 CDM ESD 分类等级 C4B
通过将 EN 引脚拉为低电平，可将该系列稳压器置于关
断模式。这个模式的关断电流低至 150nA（典型
值）。
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输入电压范围：2.7V 至 30V
超低 IQ：1μA
反向电流保护
TPS709-Q1 系列可提供 WSON-6 和 SOT-23-5 封
装。
低 ISHUTDOWN：150nA
支持 200mA 峰值输出
在温度范围内精度为 2%
器件信息(1)
可提供固定输出电压：
1.2V 至 6.5V
器件型号
TPS709-Q1
封装
SOT-23 (5)
WSON (6)
封装尺寸（标称值）
2.90mm × 1.60mm
2.00mm x 2.00mm
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热关断及过流保护
封装：小外形尺寸晶体管 (SOT)-23-5 封装、晶圆
级小外形无引线 (WSON)
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
2 应用
空白
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汽车
空白
信息娱乐系统
车身控制模块
导航系统
空白
空白
微控制器备用电源
空白
space
典型应用电路
接地电流与 VIN 和温度间的关系
3.5
VO
VI
IN
OUT
NC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
1 µF
2.2 µF
3
GND
EN
TPS709-Q1
2.5
2
1.5
1
0.5
0
5
10
15
20
25
30
Input Voltage (V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLVSCE6
TPS709-Q1
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 16
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 18
Power Supply Recommendations...................... 18
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements................................................ 6
6.7 Typical Characteristics.............................................. 7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
8
9
10 Layout................................................................... 19
10.1 Layout Guidelines ................................................. 19
10.2 Layout Examples................................................... 21
11 器件和文档支持 ..................................................... 22
11.1 器件支持................................................................ 22
11.2 文档支持................................................................ 22
11.3 接收文档更新通知 ................................................. 22
11.4 社区资源................................................................ 22
11.5 商标....................................................................... 22
11.6 静电放电警告......................................................... 22
11.7 术语表 ................................................................... 23
12 机械、封装和可订购信息....................................... 23
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Revision B (March 2015) to Revision C
Page
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Changed from: Dropout Voltage (V) to: Dropout Voltage (mV) in Figure 8, Figure 9, and Figure 10 ................................... 7
Deleted last sentence from Shutdown section .................................................................................................................... 14
Changed text From: "input supply range of 2.7 V to 6.5 V:" To: " input supply range of 2.7 V to 30 V." in the Power
Supply Recommendations section ....................................................................................................................................... 18
Changes from Revision A (December 2013) to Revision B
Page
•
在文档中增加了 DRV 封装、ESD 额定值、建议运行条件、时序要求 表、概述、器件功能模式、典型应用、器件和文
档支持 以及机械、封装和可订购信息 部分............................................................................................................................. 1
更改了应用信息、特性 说明、电源建议 和布局 部分 ............................................................................................................. 1
已删除低压降 特性 要点.......................................................................................................................................................... 1
更改了应用部分....................................................................................................................................................................... 1
更改了说明部分的最后一句..................................................................................................................................................... 1
添加了器件信息表................................................................................................................................................................... 1
添加了首页曲线....................................................................................................................................................................... 1
Added DRV package drawing to Pin Configuration and Functions section ........................................................................... 4
Changed Pin Functions table: added DRV and I/O columns, added Thermal pad row, and changed EN pin description.... 4
Changed Recommended Operating Conditions table............................................................................................................ 5
Added DRV column to Thermal Information table.................................................................................................................. 5
Changed Electrical Characteristics conditions ...................................................................................................................... 6
Changed VOUT, ICL, ISHDN, and IREV symbols in Electrical Characteristics table ..................................................................... 6
Changed VEN(HI) parameter into VEN(HI) and VEN(LO) parameters in Electrical Characteristics table ....................................... 6
Changed TA parameter to TJ in Electrical Characteristics table............................................................................................. 6
Changed Typical Characteristics section ............................................................................................................................... 7
Changed junction temperature values in first paragraph of Thermal Protection section ..................................................... 15
Changed 6.3-V to 10-V in second sentence of Detailed Design Procedure section............................................................ 18
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版权 © 2013–2018, Texas Instruments Incorporated
TPS709-Q1
www.ti.com.cn
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
Changes from Original (December 2013) to Revision A
Page
•
已发布至生产 .......................................................................................................................................................................... 1
Copyright © 2013–2018, Texas Instruments Incorporated
3
TPS709-Q1
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
www.ti.com.cn
5 Pin Configuration and Functions
DBV Package
SOT-23-5
(Top View)
DRV Package
WSON-6
(Top View)
IN
GND
EN
1
2
3
5
4
OUT
NC
OUT
NC
1
2
3
6
5
4
IN
NC
EN
GND
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DRV
DBV
Enable pin. Driving this pin high enables the device. Driving this pin low puts the
device into low current shutdown. This pin can be left floating to enable the device.
The maximum voltage must remain below 6.5 V.
EN
4
3
I
GND
IN
3
6
2
1
4
—
I
Ground
Unregulated input to the device
No internal connection
NC
2, 5
—
Regulated output voltage. Connect a small 2.2-µF or greater ceramic capacitor
from this pin to ground to assure stability.
OUT
1
5
O
The thermal pad is electrically connected to the GND node.
Connect to the GND plane for improved thermal performance.
Thermal pad
—
—
4
Copyright © 2013–2018, Texas Instruments Incorporated
TPS709-Q1
www.ti.com.cn
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
6 Specifications
6.1 Absolute Maximum Ratings
specified at TJ = –40°C to 125°C, unless otherwise noted; all voltages are with respect to GND(1)
MIN
MAX
UNIT
VIN
–0.3
–0.3
–0.3
32
V
V
V
Voltage
VEN
VOUT
IOUT
7
7
Maximum output current
Internally limited
Output short-circuit duration
Continuous total power dissipation
Junction temperature, TJ
Ambient temperature, TA
Storage temperature, Tstg
Indefinite
PDISS
See Thermal Information
–55
–40
–55
150
125
150
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±750
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
2.7
1.2
0
NOM
MAX
UNIT
VIN
Input voltage
30
6.5
V
V
VOUT
IOUT
VEN
CIN
Output voltage
Output current
150
6.5
mA
V
Enable voltage
0
Input capacitor
1
µF
µF
°C
COUT
TJ
Output capacitor
Operating junction temperature
2
2.2
47
–40
125
6.4 Thermal Information
TPS709-Q1
THERMAL METRIC(1)
DBV (SOT-23)
5 PINS
210.9
DRV (WSON)
6 PINS
73.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
127.4
97.0
39.4
42.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
16.8
2.9
ψJB
38.4
42.9
RθJC(bot)
N/A
12.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2013–2018, Texas Instruments Incorporated
5
TPS709-Q1
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
www.ti.com.cn
6.5 Electrical Characteristics
At –40°C ≤ TJ, TA ≤ 125°C, VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), IOUT = 1 mA, VEN = 2 V, and CIN = COUT = 2.2-
μF ceramic, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.7
TYP
MAX
30
UNIT
V
VIN
Input voltage range
Output voltage range
VOUT
1.2
6.5
2%
1%
10
V
VOUT < 3.3 V
OUT ≥ 3.3 V
–2%
–1%
VOUT
DC output accuracy
V
Line regulation
Load regulation
(VOUT(nom) + 1 V, 2.7 V) ≤ VIN ≤ 30 V
3
mV
mV
ΔVOUT
VIN = VOUT(nom) + 1.5 V or 3 V (whichever is
greater), 100 µA ≤ IOUT ≤ 150 mA
20
50
TPS70933-Q1, IOUT = 50 mA
TPS70933-Q1, IOUT = 150 mA
TPS70950-Q1, IOUT = 50 mA
TPS70950-Q1, IOUT = 150 mA
VOUT = 0.9 × VOUT(nom)
295
975
245
690
320
1.3
1.4
6.7
350
150
80
650
1540
500
1200
500
2.55
2.7
VDO
Dropout voltage(1)(2)
Output current limit(3)
Ground pin current
Shutdown current
mV
mA
µA
ICL
200
IOUT = 0 mA, VOUT ≤ 3.3 V
IOUT = 0 mA, VOUT > 3.3 V
IOUT = 100 μA, VIN = 30 V
IOUT = 150 mA
IGND
10
ISHDN
VEN ≤ 0.4 V, VIN = 2.7 V
nA
dB
f = 10 Hz
PSRR
Power-supply rejection ratio f = 100 Hz
f = 1 kHz
62
52
BW = 10 Hz to 100 kHz, IOUT = 10 mA,
VIN = 2.7 V, VOUT = 1.2 V
Vn
Output noise voltage
190
μVRMS
VEN(HI)
VEN(LO)
IEN
Enable pin high (enabled)
Enable pin high (disabled)
Enable pin current
0.9
0
V
V
0.4
EN = 1.0 V, VIN = 5.5 V
300
10
nA
Reverse current
(flowing out of IN pin)
VOUT = 3 V, VIN = VEN = 0 V
nA
nA
IREV
Reverse current
(flowing into OUT pin)
VOUT = 3 V, VIN = VEN = 0 V
100
Shutdown, temperature increasing
Reset, temperature decreasing
158
140
Thermal shutdown
temperature
TSD
TJ
°C
°C
Operating junction
temperature
–40
125
(1) VDO is measured with VIN = 0.98 × VOUT(nom)
.
(2) Dropout is only valid when VOUT ≥ 2.8 V because of the minimum input voltage limits.
(3) Measured with VIN = VOUT + 3 V for VOUT ≤ 2.5 V. Measured with VIN = VOUT + 2.5 V for VOUT > 2.5 V.
6.6 Timing Requirements
At TJ = –40°C to 125°C, VIN = VOUT(nom) + 1 V or 2.7 V (whichever is greater), RL = 47 Ω, VEN = 2 V, and CIN = COUT = 2.2-μF
ceramic, unless otherwise noted. Typical values are at TJ = 25°C.
MIN
NOM
200
MAX
600
UNIT
µs
V
OUT(nom) ≤ 3.3 V
tSTR
Start-up time(1)
VOUT(nom) > 3.3 V
500
1500
µs
(1) Startup time = time from EN assertion to 0.95 × VOUT(nom) and load = 47 Ω.
6
Copyright © 2013–2018, Texas Instruments Incorporated
TPS709-Q1
www.ti.com.cn
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
6.7 Typical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
1.203
1.202
1.201
1.2
3.305
3.3025
3.3
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
3.2975
3.295
3.2925
1.199
1.198
0
6
12
18
24
30
5
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
Figure 1. 1.2-V Line Regulation vs VIN and Temperature
Figure 2. 3.3-V Line Regulation vs VIN and Temperature
1.204
6.507
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
1.2
1.196
1.192
1.188
1.184
6.504
6.501
6.498
6.495
6.492
5
10
15
20
25
30
0
30
60
90
120
150
Input Voltage (V)
Output Current (mA)
Figure 3. 6.5-V Line Regulation vs VIN and Temperature
Figure 4. 1.2-V Load Regulation vs IOUT and Temperature
3.306
6.5
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
6.495
TJ = 25èC
3.3
3.294
3.288
3.282
3.276
TJ = -40èC
6.49
6.485
6.48
6.475
6.47
0
30
60
90
120
150
0
30
60
90
120
150
Output Current (mA)
Output Current (mA)
Figure 5. 3.3-V Load Regulation vs IOUT and Temperature
Figure 6. 6.5-V Load Regulation vs IOUT and Temperature
Copyright © 2013–2018, Texas Instruments Incorporated
7
TPS709-Q1
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
www.ti.com.cn
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
2400
2000
1600
1200
800
1.204
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
IOUT = 10 mA
IOUT = 150 mA
1.2
1.196
1.192
1.188
1.184
400
2.4
3.2
4
4.8
5.6
6.4
-50
0
50
100
150
Input Voltage (V)
Input Voltage (V)
Figure 8. 6.5-V Dropout Voltage vs VIN and Temperature
Figure 7. 1.2-V Output Voltage vs Temperature
1500
1200
900
600
300
0
1000
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
800
TJ = -40èC
600
400
200
0
0
30
60
90
120
150
0
30
60
90
120
150
Output Current (mA)
Output Current (mA)
Figure 9. 3.3-V Dropout Voltage vs IOUT and Temperature
Figure 10. Dropout Voltage vs IOUT and Temperature
540
480
TJ = 125èC
TJ = 85èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 25èC
480
440
400
360
320
280
TJ = -40èC
420
360
300
240
3.5
4
4.5
5
5.5
6
6.5
4.8
5.4
6
6.6
7.2
7.8
8.4
Input Voltage (V)
Input Voltage (V)
Figure 11. 1.2-V Current Limit vs VIN and Temperature
Figure 12. 3.3-V Current Limit vs VIN and Temperature
8
Copyright © 2013–2018, Texas Instruments Incorporated
TPS709-Q1
www.ti.com.cn
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
3.5
520
480
440
400
360
320
280
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
3
2.5
2
1.5
1
0.5
8.5
9
9.5
10
10.5
11
11.5
0
5
0
5
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
Figure 13. 6.5-V Current Limit vs VIN and Temperature
Figure 14. 1.2-V Ground Pin Current vs VIN and
Temperature
3.5
3.5
3
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0.5
0
5
10
15
20
25
30
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
Figure 15. 3.3-V Ground Pin Current vs VIN and
Temperature
Figure 16. 6.5-V Ground Pin Current vs VIN and
Temperature
4
3.5
3
750
600
450
300
150
0
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
2.5
2
1.5
1
0
5
10
15
20
25
30
30
60
90
120
150
Input Voltage (V)
Output Current
Figure 17. 3.3-V Ground Current vs VIN and
Temperature with EN Floating
Figure 18. 1.2-V Ground Pin Current vs IOUT and
Temperature
Copyright © 2013–2018, Texas Instruments Incorporated
9
TPS709-Q1
ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
www.ti.com.cn
Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
750
600
450
300
150
0
750
600
450
300
150
0
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
0
30
60
90
120
150
0
30
60
90
120
150
Output Current
Output Current
Figure 19. 3.3-V Ground Pin Current vs IOUT and
Temperature
Figure 20. 6.5-V Ground Pin Current vs IOUT and
Temperature
0.9
0.75
0.6
0.9
0.75
0.6
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
TJ = 125èC
TJ = 85èC
TJ = 25èC
TJ = -40èC
0.45
0.3
0.45
0.3
0.15
0
0.15
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
Figure 21. 1.2-V Shutdown Current vs VIN and Temperature
Figure 22. 3.3-V Shutdown Current vs VIN and Temperature
0.9
600
TJ = 125èC
TJ = 85èC
1.2V Output
3.3V Output
6.5V Output
0.75
500
TJ = 25èC
TJ = -40èC
0.6
400
300
200
100
0
0.45
0.3
0.15
0
5
10
15
20
25
30
-50
0
50
100
150
Input Voltage (V)
Temperature (èC)
Figure 23. 6.5-V Shutdown Current vs VIN and Temperature
Figure 24. Start-Up Time vs Temperature
10
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
90
80
70
60
50
40
30
20
10
0
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
1E+1
1E+2
1E+3
1E+4
1E+5
1E+6
1E+7
1E+1
1E+2
1E+3
1E+4
1E+5
Frequency (Hz)
Frequency (Hz)
Figure 25. Power-Supply Rejection Ratio vs Frequency
Figure 26. Noise
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (100 ms / div)
Time (500 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Figure 27. TPS70912-Q1 Load Transient (0 mA to 50 mA)
Figure 28. TPS70912-Q1 Load Transient (1 mA to 150 mA)
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (10 ms / div)
Time (100 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Channel 2 = VOUT, channel 4 = IOUT, VIN = 2.7 V
Figure 29. TPS70912-Q1 Load Transient (50 mA to 0 mA)
Figure 30. TPS70912-Q1 Load Transient (50 mA to 150 mA)
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (100 ms / div)
Time (500 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Figure 31. TPS70933-Q1 Load Transient (0 mA to 50 mA)
Figure 32. TPS70933-Q1 Load Transient (1 mA to 150 mA)
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 4
(50 mA / div)
Channel 4
(50 mA / div)
Time (10 ms / div)
Time (500 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Figure 33. TPS70933-Q1 Load Transient (50 mA to 0 mA)
Figure 34. TPS70933-Q1 Load Transient (50 mA to 150 mA)
Channel 2
(50 mV / div)
Channel 2
(50 mV / div)
Channel 4
(2 V / div)
Channel 4
(2 V / div)
Time (50 ms / div)
Time (50 ms / div)
Channel 2 = VOUT, channel 4 = VIN, IOUT = 10 mA
Channel 2 = VOUT, channel 4 = VIN, IOUT = 50 mA
Figure 35. TPS70912-Q1 Line Transient (2.7 V to 3.7 V)
Figure 36. TPS70912-Q1 Line Transient (2.7 V to 3.7 V)
12
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(nom) + 1 V
or 2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
Channel 2
(50 mV / div)
Channel 2
(50 mV / div)
Channel 4
(2 V / div)
Channel 4
(2 V / div)
Time (50 ms / div)
Time (50 ms / div)
Channel 2 = VOUT, channel 4 = VIN, IOUT = 10 mA
Channel 2 = VOUT, channel 4 = VIN, IOUT = 50 mA
Figure 37. TPS70933-Q1 Line Transient (4.3 V to 5.3 V)
Figure 38. TPS70933-Q1 Line Transient (4.3 V to 5.3 V)
Channel 2
(1 V / div)
Channel 2
(1 V / div)
Channel 1
(500 mV / div)
Channel 1
(1 V / div)
Time (50 ms / div)
Time (500 ms / div)
Channel 1 = EN, channel 2 = VOUT, VIN = 4.3 V, COUT = 2.2 µF,
TPS70633
Channel 1 = VIN, channel 2 = VOUT, IOUT = 3 mA, TPS70633
Figure 39. Power-Up with Enable
Figure 40. Power-Up and Power-Down Response
Channel 2
(1 V / div)
Channel 1
(1 V / div)
Time (500 ms / div)
Channel 1 = VIN, channel 2 = VOUT, IOUT = 150 mA, TPS70633
Figure 41. Power-Up and Power-Down Response
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www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS709-Q1 series are ultralow quiescent current, low-dropout (LDO) linear regulators. The TPS709-Q1
offers reverse current protection to block any discharge current from the output into the input. The TPS709-Q1
also features current limit and thermal shutdown for reliable operation.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
Bandgap
EN
Logic
Device
GND
7.3 Feature Description
7.3.1 Undervoltage Lockout (UVLO)
The TPS709-Q1 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry
operates properly.
7.3.2 Shutdown
The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI) (0.9 V, minimum).
Turn off the device by forcing the EN pin to drop below 0.4 V.
7.3.3 Reverse Current Protection
The TPS709-Q1 has integrated reverse current protection. Reverse current protection prevents the flow of
current from the OUT pin to the IN pin when output voltage is higher than input voltage. The reverse current
protection circuitry places the power path in high impedance when the output voltage is higher than the input
voltage. This setting reduces leakage current from the output to the input to 10 nA, typical. The reverse current
protection is always active regardless of the enable pin logic state or if the OUT pin voltage is greater than 1.8 V.
Reverse current can flow if the output voltage is less than 1.8 V and if input voltage is less than the output
voltage.
If voltage is applied to the input pin, then the maximum voltage that can be applied to the OUT pin is the lower of
three times the nominal output voltage or 6.5 V. For example, if the 1.2-V output voltage version is used, then the
maximum reverse bias voltage that can be applied to the OUT pin is 3.6 V. If the 3.3-V output voltage version is
used, then the maximum reverse bias voltage that can be applied to the OUT pin is 6.5 V.
14
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Feature Description (continued)
7.3.4 Internal Current Limit
The TPS709-Q1 internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output
voltage is not regulated, and can be measured as (VOUT = ILIMIT × RLOAD). The PMOS pass transistor dissipates
[(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. When cool, the device is
turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between
current limit and thermal shutdown; see the Thermal Information section for more details.
The TPS709-Q1 is characterized over the recommended operating output current range up to 150 mA. The
internal current limit begins to limit the output current at a minimum of 200 mA of output current.
7.3.5 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 158°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C, maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least
35°C above the maximum expected ambient condition of the particular application. This configuration produces a
worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The TPS709-Q1 internal protection circuitry is designed to protect against overload conditions. This circuitry is
not intended to replace proper heatsinking. Continuously running the TPS709-Q1 into thermal shutdown
degrades device reliability.
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7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is at least as high as VIN(min)
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
.
•
•
The output current is less than the current limit.
The device junction temperature is less than the maximum specified junction temperature.
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the
output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the
device is significantly degraded because the pass device is in the linear region and no longer controls the current
through the LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
•
The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
•
The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
IOUT < ILIM
—
TJ
VIN > VOUT(nom) + VDO and
VIN > VIN(min)
Normal mode
Dropout mode
VEN > VEN(HI)
VEN > VEN(HI)
TJ < 125°C
TJ < 125°C
VIN(min) < VIN < VOUT(nom) + VDO
Disabled mode
(any true condition disables the
device)
—
VEN < VEN(low)
—
TJ > 158°C
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS709-Q1 consumes low quiescent current and delivers excellent line and load transient performance.
This performance, combined with low noise and good PSRR with little (VIN – VOUT) headroom, makes these
devices ideal for RF portable applications, current limit, and thermal protection. The TPS709-Q1 devices are
specified from –40°C to 125°C.
8.1.1 Input and Output Capacitor Considerations
The TPS709-Q1 devices are stable with output capacitors with an effective capacitance of 2.0 μF or greater for
output voltages below 1.5 V. For output voltages equal or greater than 1.5 V, the minimum effective capacitance
for stability is 1.5 µF. The maximum capacitance for stability is 47 µF. The equivalent series resistance (ESR) of
the output capacitor must be between 0 Ω and 0.2 Ω for stability.
The effective capacitance is the minimum capacitance value of a capacitor after taking into account variations
resulting from tolerances, temperature, and dc bias effects. X5R- and X7R-type ceramic capacitors are
recommended because these capacitors have minimal variation in value and ESR over temperature.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
2.2-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple rejection, and PSRR.
8.1.2 Dropout Voltage
The TPS709-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with the output current because
the PMOS device functions like a resistor in dropout.
The ground pin current of many linear voltage regulators increases substantially when the device is operated in
dropout. This increase in ground pin current while operating in dropout can be several orders of magnitude larger
than when the device is not in dropout. The TPS709-Q1 employs a special control loop that limits the increase in
ground pin current while operating in dropout. This functionality allows for the most efficient operation while in
dropout conditions that can greatly increase battery run times.
8.1.3 Transient Response
As with any regulator, increasing the output capacitor size reduces over- and undershoot magnitude, but
increases transient response duration.
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8.2 Typical Application
VO
VI
IN
OUT
NC
1 µF
2.2 µF
GND
EN
TPS70933-Q1
Figure 42. 3.3-V, Low-IQ Rail
8.2.1 Design Requirements
Table 2 summarizes the design requirements for Figure 42.
Table 2. Design Requirements for a 3.3-V, Low-IQ Rail Application
PARAMETER
VIN
DESIGN SPECIFICATION
4.3 V
3.3 V
VOUT
I(IN) (no load)
IOUT (max)
< 5 µA
150 mA
8.2.2 Detailed Design Procedure
Select a 2.2-µF, 10-V X7R output capacitor to satisfy the minimum output capacitance requirement with a 3.3-V
dc bias.
Select a 1.0-µF, 10-V X7R input capacitor to provide input noise filtering and eliminate high-frequency voltage
transients.
8.2.3 Application Curves
Channel 2
(200 mV / div)
Channel 2
(1 V / div)
Channel 1
(500 mV / div)
Channel 4
(50 mA / div)
Time (500 ms / div)
Time (50 ms / div)
Channel 2 = VOUT, channel 4 = IOUT, VIN = 4.3 V
Channel 1 = EN, channel 2 = VOUT, VIN = 4.3 V, COUT = 2.2 µF,
TPS70933-Q1
Figure 44. Power-Up with Enable
Figure 43. TPS70933-Q1 Load Transient (50 mA to 150 mA)
9 Power Supply Recommendations
This device is designed to operate with an input supply range of 2.7 V to 30 V. The input voltage range must
provide adequate headroom in order for the device to have a regulated output. This input supply must be well-
regulated and stable. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
18
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10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
Input and output capacitors must be placed as close to the device pins as possible. To improve ac performance
(such as PSRR, output noise, and transient response), TI recommends that the board be designed with separate
ground planes for VIN and VOUT, with the ground plane connected only at the device GND pin. In addition, the
output capacitor ground connection must be connected directly to the device GND pin. High ESR capacitors may
degrade PSRR performance.
10.1.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the
Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) can be approximated by
the product of the output current times the voltage drop across the output pass element (VIN to VOUT), as shown
in Equation 1.
PD = (VIN – VOUT) × IOUT
(1)
Figure 45 shows the maximum ambient temperature versus the power dissipation of the TPS709-Q1. This figure
assumes the device is soldered on a JEDEC standard, high-K layout with no airflow over the board. Actual board
thermal impedances vary widely. If the application requires high power dissipation, having a thorough
understanding of the board temperature and thermal impedances is helpful to ensure the TPS709-Q1 does not
operate above a junction temperature of 125°C.
125
DBV Package
DRV Package
100
75
50
25
0
0.25
0.5
0.75
1
1.2
Power Dissipation (W)
Figure 45. Maximum Ambient Temperature vs Device Power Dissipation
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Layout Guidelines (continued)
Estimating the junction temperature can be done by using the thermal metrics ΨJT and ΨJB, shown in the Thermal
Information. These metrics are a more accurate representation of the heat transfer characteristics of the die and
the package than RθJA. The junction temperature can be estimated with Equation 2.
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
where:
•
•
•
PD is the power dissipation shown by Equation 1,
TT is the temperature at the center-top of the IC package,
TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface.
(2)
NOTE
Both TT and TB can be measured on actual application boards using a thermo-gun (an
infrared thermometer).
For more information about measuring TT and TB, see the application note Using New Thermal Metrics
(SBVA025), available for download at www.ti.com.
20
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TPS709-Q1
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ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
10.2 Layout Examples
Input Capacitor
Input
Trace
Enable
Trace
Grounded
Thermal Plane
NC
EN
Input Ground
Plane
IN
Thermal Pad
GND
NC
Output Trace
OUT
Grounded
Thermal Plane
Output Ground
Plane
Output Capacitor
Designates thermal vias.
Figure 46. WSON Layout Example
VOUT
VIN
OUT
IN
CIN
COUT
GND
EN
NC
GND PLANE
Represents via used for application-specific connections.
Figure 47. SOT23-5 Layout Example
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11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
评估模块 (EVM) 可与 TPS709-Q1 配套使用，帮助评估初始电路性能。TPS70933EVM-110 评估模块（和相关的
用户指南）可在德州仪器 (TI) 网站上的产品文件夹中获取，也可直接从 TI 网上商店购买。
11.1.1.2 Spice 模型
分析模拟电路和系统的性能时，使用 SPICE 模型对电路性能进行计算机仿真非常有用。您可以从产品文件夹中的
仿真模型下获取 TPS709 的 SPICE 模型。
11.1.2 器件命名规则
表 3. 器件命名规则(1)
产品
VOUT
TPS709xx(x)yyyz-Q1
XX(X) 是标称输出电压。对于分辨率为 100mV 的输出电压，订货编号中使用两位数字；否
则，使用三位数字（例如，28 = 2.8V；125 = 1.25V）。
YYY 为封装标识符。
Z 为卷带数量（R = 3000，T = 250）。
(1) 要获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者登录 TI 的网站 www.ti.com.cn进行查询。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
《TPS70933EVM-110 评估模块用户指南》
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
22
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ZHCSC15C –DECEMBER 2013–REVISED JUNE 2018
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请参阅左侧的导航栏。
版权 © 2013–2018, Texas Instruments Incorporated
23
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS70912QDBVRQ1
TPS70912QDRVRQ1
TPS70915QDRVRQ1
TPS70918QDBVRQ1
TPS70918QDRVRQ1
TPS70925QDBVRQ1
TPS70925QDRVRQ1
TPS70927QDRVRQ1
TPS70928QDBVRQ1
TPS70928QDRVRQ1
TPS70930QDBVRQ1
TPS70930QDRVRQ1
TPS70933QDBVRQ1
TPS70933QDRVRQ1
TPS70936QDBVRQ1
TPS70950QDBVRQ1
TPS70950QDRVRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
WSON
WSON
SOT-23
WSON
SOT-23
WSON
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
SOT-23
WSON
DBV
DRV
DRV
DBV
DRV
DBV
DRV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DBV
DRV
5
6
6
5
6
5
6
6
5
6
5
6
5
6
5
5
6
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SLR
SJD
SJE
SLS
SJF
SLT
SJG
SJH
SLU
SJI
NIPDAUAG
NIPDAUAG
NIPDAU
NIPDAUAG
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAU
NIPDAUAG
NIPDAU
SLV
SJJ
NIPDAUAG
NIPDAU
SLJ
SJK
SLW
SLX
SJL
NIPDAUAG
NIPDAU
NIPDAU
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS70912QDBVRQ1
TPS70912QDRVRQ1
TPS70915QDRVRQ1
TPS70918QDBVRQ1
TPS70918QDRVRQ1
TPS70925QDBVRQ1
TPS70925QDRVRQ1
TPS70927QDRVRQ1
TPS70928QDBVRQ1
TPS70928QDRVRQ1
TPS70930QDBVRQ1
TPS70930QDRVRQ1
TPS70933QDBVRQ1
TPS70933QDRVRQ1
TPS70936QDBVRQ1
TPS70950QDBVRQ1
TPS70950QDRVRQ1
SOT-23
WSON
WSON
SOT-23
WSON
SOT-23
WSON
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
SOT-23
WSON
DBV
DRV
DRV
DBV
DRV
DBV
DRV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DBV
DRV
5
6
6
5
6
5
6
6
5
6
5
6
5
6
5
5
6
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
178.0
179.0
179.0
178.0
179.0
178.0
179.0
179.0
178.0
179.0
178.0
179.0
178.0
179.0
178.0
178.0
179.0
9.0
8.4
8.4
9.0
8.4
9.0
8.4
8.4
9.0
8.4
9.0
8.4
9.0
8.4
9.0
9.0
8.4
3.23
2.2
3.17
2.2
1.37
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q2
Q2
Q3
Q2
Q3
Q2
Q2
Q3
Q2
Q3
Q2
Q3
Q2
Q3
Q3
Q2
2.2
2.2
1.2
3.23
2.2
3.17
2.2
1.37
1.2
3.23
2.2
3.17
2.2
1.37
1.2
2.2
2.2
1.2
3.23
2.2
3.17
2.2
1.37
1.2
3.23
2.2
3.17
2.2
1.37
1.2
3.23
2.2
3.17
2.2
1.37
1.2
3.23
3.23
2.2
3.17
3.17
2.2
1.37
1.37
1.2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS70912QDBVRQ1
TPS70912QDRVRQ1
TPS70915QDRVRQ1
TPS70918QDBVRQ1
TPS70918QDRVRQ1
TPS70925QDBVRQ1
TPS70925QDRVRQ1
TPS70927QDRVRQ1
TPS70928QDBVRQ1
TPS70928QDRVRQ1
TPS70930QDBVRQ1
TPS70930QDRVRQ1
TPS70933QDBVRQ1
TPS70933QDRVRQ1
TPS70936QDBVRQ1
TPS70950QDBVRQ1
TPS70950QDRVRQ1
SOT-23
WSON
WSON
SOT-23
WSON
SOT-23
WSON
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
WSON
SOT-23
SOT-23
WSON
DBV
DRV
DRV
DBV
DRV
DBV
DRV
DRV
DBV
DRV
DBV
DRV
DBV
DRV
DBV
DBV
DRV
5
6
6
5
6
5
6
6
5
6
5
6
5
6
5
5
6
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
200.0
200.0
180.0
200.0
180.0
200.0
200.0
180.0
200.0
180.0
200.0
180.0
200.0
180.0
180.0
200.0
180.0
183.0
183.0
180.0
183.0
180.0
183.0
183.0
180.0
183.0
180.0
183.0
180.0
183.0
180.0
180.0
183.0
18.0
25.0
25.0
18.0
25.0
18.0
25.0
25.0
18.0
25.0
18.0
25.0
18.0
25.0
18.0
18.0
25.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006D
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A B
C
0.05
4225563/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225563/A 12/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4225563/A 12/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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