TPS70936DRVR [TI]
TPS709 150-mA, 30-V, 1-μA IQ Voltage Regulators with Enable;
| 型号： | TPS70936DRVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TPS709 150-mA, 30-V, 1-μA IQ Voltage Regulators with Enable |
| 文件： | 总39页 (文件大小：2112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS709
SBVS186G –MARCH 2012–REVISED NOVEMBER 2015
TPS709 150-mA, 30-V, 1-µA IQ Voltage Regulators with Enable
1 Features
3 Description
The TPS709 series of linear regulators are ultralow,
1
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Ultralow IQ: 1 μA
quiescent current devices designed for power-
sensitive applications. A precision band-gap and error
amplifier provides 2% accuracy over temperature.
Quiescent current of only 1 µA makes these devices
ideal solutions for battery-powered, always-on
systems that require very little idle-state power
dissipation. These devices have thermal-shutdown,
current-limit, and reverse-current protections for
added safety.
Reverse Current Protection
Low ISHUTDOWN: 150 nA
Input Voltage Range: 2.7 V to 30 V
Supports 200-mA Peak Output
2% Accuracy Over Temperature
Available in Fixed-Output Voltages:
1.2 V to 6.5 V
•
•
Thermal Shutdown and Overcurrent Protection
Packages: SOT-23-5, WSON-6
Shutdown mode is enabled by pulling the EN pin low.
The shutdown current in this mode goes down to 150
nA, typical.
2 Applications
The TPS709 series is available in WSON-6 and
SOT-23-5 packages.
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Zigbee™ Networks
Home Automation
Metering
Device Information(1)
PART NUMBER
TPS709
PACKAGE
SOT-23 (5)
WSON (6)
BODY SIZE (NOM)
2.90 mm × 1.60 mm
2.00 mm × 2.00 mm
Weighing Scales
Portable Power Tools
Remote Control Devices
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Wireless Handsets, Smart Phones, PDAs, WLAN,
and Other PC Add-On Cards
•
White Goods
Typical Application Circuit
GND Current vs VIN and Temperature
2
VIN
VOUT
IN
OUT
1 mF
2.2 mF
1.8
1.5
1.2
GND
EN
TPS709xx
NC
1
TA = −40°C
TA = +25°C
0.8
TA = +85°C
TPS70912
5
0.5
0
10
15
20
25
30 35
Input Voltage (V)
G014
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS709
SBVS186G –MARCH 2012–REVISED NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagram ....................................... 13
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 14
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
Power Supply Recommendations...................... 16
9.1 Power Dissipation ................................................... 16
9
10 Layout................................................................... 17
10.1 Layout Guidelines ................................................. 17
10.2 Layout Example .................................................... 17
11 Device and Documentation Support ................. 18
11.1 Device Support...................................................... 18
11.2 Documentation Support ........................................ 18
11.3 Community Resources.......................................... 18
11.4 Trademarks........................................................... 19
11.5 Electrostatic Discharge Caution............................ 19
11.6 Glossary................................................................ 19
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (December 2014) to Revision G
Page
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•
Added DBV package for TPS709A to Pin Configurations and Functions section.................................................................. 4
Added DBV package for TPS709B to Pin Configurations and Functions section.................................................................. 4
Added TPS709A and TPS709B to Pin Functions table ......................................................................................................... 4
Moved operating junction temperature from Electrical Characteristics to Recommended Operating Conditions ................. 5
Changes from Revision E (November 2013) to Revision F
Page
•
•
Changed title format to meet latest data sheet standards...................................................................................................... 1
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
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Deleted SOT-223-4 package from document ........................................................................................................................ 1
Deleted Low Dropout Features bullet .................................................................................................................................... 1
Changed Packages Feature bullet: deleted SOT-223-4 and footnote .................................................................................. 1
Deleted SOT-223-4 from last paragraph of Description section ........................................................................................... 1
Deleted pinout graphics from page 1 .................................................................................................................................... 1
Deleted DCY package and footnote from Pin Configurations section ................................................................................... 4
Changed Pin Functions table: changed title and deleted DCY package................................................................................ 4
Changed EN pin description in Pin Functions table .............................................................................................................. 4
Deleted the word 'range' from the last 2 rows of the Absolute Maximum Ratings table........................................................ 5
Deleted DCY column from Thermal Information table ........................................................................................................... 5
Added description text to the enabled mode discussion in the Device Functional Modes section ..................................... 14
2
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SBVS186G –MARCH 2012–REVISED NOVEMBER 2015
Changes from Revision D (October 2013) to Revision E
Page
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Changed DRV (SON-6) package status from Preview to Production Data............................................................................ 1
Deleted SON-6 package from footnote 1 in Features section................................................................................................ 1
Deleted DRV package from pinout diagram note................................................................................................................... 1
Deleted DRV from pinout note in the Pin Configurations section........................................................................................... 4
Changes from Revision C (June 2013) to Revision D
Page
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•
Changed device status from Production Data to Mixed Status.............................................................................................. 1
Changed last Features bullet: added footnote and changed device order............................................................................. 1
Added note to pinout diagrams............................................................................................................................................... 1
Added product preview footnote to pin configurations ........................................................................................................... 4
Changes from Revision B (November 2012) to Revision C
Page
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•
•
Added DCY (SOT-223) and DRV (SON) packages to data sheet ......................................................................................... 1
Changed IQ feature bullet value from 1.35 µA to 1 µA........................................................................................................... 1
Changed quiescent current value in first paragraph of Description section from 1.35 µA to 1 µA ........................................ 1
Changed text in second paragraph of Description section from "leakage" to "shutdown." .................................................... 1
Added typical application circuit ............................................................................................................................................. 1
Added DCY and DRV packages to Pin Configuration section .............................................................................................. 4
Added DCY and DRV packages to Pin Descriptions table ................................................................................................... 4
Added DRV and DCY packages to Thermal Information table .............................................................................................. 5
Changed ground pin current typical values for IOUT = 0-mA test conditions........................................................................... 6
Changes from Revision A (October 2012) to Revision B
Page
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Added Pin Configuration section ............................................................................................................................................ 4
Changed Line regulation and Load regulation parameters in Electrical Characteristics table............................................... 6
Changed IGND parameter test conditions in Electrical Characteristics table........................................................................... 6
Changed ISHUTDOWN parameter test conditions in Electrical Characteristics table .................................................................. 6
Changed footnote 4 in Electrical Characteristics table........................................................................................................... 6
Changed second paragraph of Dropout Voltage section ..................................................................................................... 13
Changes from Original (March 2012) to Revision A
Page
•
Changed device status from Product Preview to Production Data ........................................................................................ 1
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SBVS186G –MARCH 2012–REVISED NOVEMBER 2015
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5 Pin Configuration and Functions
TPS709: DBV Package
5-Pin SOT-23
TPS709B: DBV Package
5-Pin SOT-23
Top View
Top View
IN
GND
EN
1
2
3
5
4
OUT
NC
1
2
3
5
4
EN
NC
GND
IN
OUT
TPS709A: DBV Package
5-Pin SOT-23
DRV Package
6-Pin WSON
Top View
Top View
OUT
GND
IN
1
2
3
5
4
EN
NC
OUT
NC
1
2
3
6
5
4
IN
NC
EN
GND
Pin Functions
PIN
DRV
DBV
I/O
DESCRIPTION
NAME
TPS709
TPS709 TPS709A TPS709B
Enable pin. Drive this pin high to enable the device. Drive this pin low
to put the device into low current shutdown. This pin can be left
floating to enable the device. The maximum voltage must remain
below 6.5 V.
EN
4
3
5
5
I
GND
IN
3
6
2
1
4
2
3
4
1
2
4
—
I
Ground
Unregulated input to the device
No internal connection
NC
2, 5
—
Regulated output voltage. Connect a small 2.2-µF or greater ceramic
capacitor from this pin to ground to assure stability.
OUT
1
5
1
3
O
The thermal pad is electrically connected to the GND node. Connect
this pad to the GND plane for improved thermal performance.
Thermal pad
—
—
—
—
4
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SBVS186G –MARCH 2012–REVISED NOVEMBER 2015
6 Specifications
6.1 Absolute Maximum Ratings
specified at TJ = –40°C to 125°C (unless otherwise noted); all voltages are with respect to GND(1)
MIN
MAX
UNIT
VIN
–0.3
–0.3
–0.3
32
Voltage
VEN
VOUT
IOUT
7
V
7
Internally limited
Indefinite
Maximum output current
Output short-circuit duration
Continuous total power dissipation
Operating junction temperature, TJ
Storage temperature, Tstg
PDISS
See Thermal Information
150
–55
–55
°C
°C
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 2-kV HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 500-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
2.7
1.2
0
NOM
MAX
UNIT
VIN
Input voltage
30
6.5
V
V
VOUT
VEN
TJ
Output voltage
Enable voltage
6.5
V
Operating junction temperature
–40
125
°C
6.4 Thermal Information
TPS709
THERMAL METRIC(1)
DBV
DRV
UNIT
5 PINS
212.1
78.5
6 PINS
73.1
97.0
42.6
2.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
39.5
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.86
ψJB
38.7
42.9
12.8
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At ambient temperature (TA) = –40°C to +85°C, VIN = VOUT(typ) + 1 V or 2.7 V (whichever is greater), IOUT = 1 mA, VEN = 2 V,
and CIN = COUT = 2.2-μF ceramic, unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.7
TYP
MAX
30
UNIT
V
VIN
Input voltage range
Output voltage range
VOUT
1.2
6.5
2%
1%
10
V
VOUT < 3.3 V
OUT ≥ 3.3 V
–2%
–1%
VOUT
DC output accuracy
V
Line regulation
Load regulation
(VOUT(nom) + 1 V, 2.7 V) ≤ VIN ≤ 30 V
3
ΔVOUT
mV
mV
VIN = VOUT(typ) + 1.5 V or 3 V (whichever is
greater), 100 µA ≤ IOUT ≤ 150 mA
20
50
TPS70933, IOUT = 50 mA
TPS70933, IOUT = 150 mA
TPS70950, IOUT = 50 mA
TPS70950, IOUT = 150 mA
TPS70965, IOUT = 50 mA
TPS70965, IOUT = 150 mA
VOUT = 0.9 × VOUT(nom)
IOUT = 0 mA, VOUT ≤ 3.3 V
IOUT = 0 mA, VOUT > 3.3 V
IOUT = 150 mA
295
960
245
690
180
460
320
1.3
1.4
350
150
80
650
1400
500
VDO
Dropout voltage(1)(2)
1200
500
1000
500
I(CL)
Output current limit(3)
Ground pin current
Shutdown current
200
mA
µA
nA
dB
2.05
2.25
IGND
ISHUTDOWN
V
EN ≤ 0.4 V, VIN = 2.7 V
f = 10 Hz
PSRR
Power-supply rejection ratio f = 100 Hz
f = 1 kHz
62
52
BW = 10 Hz to 100 kHz, IOUT = 10 mA,
VIN = 2.7 V, VOUT = 1.2 V
Vn
Output noise voltage
Start-up time(4)
190
μVRMS
VOUT(nom) ≤ 3.3 V
200
500
600
tSTR
µs
VOUT(nom) > 3.3 V
1500
Enable pin high (enabled)
Enable pin high (disabled)
EN pin current
0.9
0
VEN(HI)
IEN
V
0.4
EN = 1.0 V, VIN = 5.5 V
300
10
nA
Reverse current
(flowing out of IN pin)
VOUT = 3 V, VIN = VEN = 0 V
I(REV)
nA
°C
Reverse current
(flowing into OUT pin)
VOUT = 3 V, VIN = VEN = 0 V
100
Shutdown, temperature increasing
Reset, temperature decreasing
158
140
Thermal shutdown
temperature
tSD
(1) VDO is measured with VIN = 0.98 × VOUT(nom)
.
(2) Dropout is only valid when VOUT ≥ 2.8 V because of the minimum input voltage limits.
(3) Measured with VIN = VOUT + 3 V for VOUT ≤ 2.5 V. Measured with VIN = VOUT + 2.5 V for VOUT > 2.5 V.
(4) Startup time = time from EN assertion to 0.95 × VOUT(nom) and load = 47 Ω.
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SBVS186G –MARCH 2012–REVISED NOVEMBER 2015
6.6 Typical Characteristics
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(typ) + 1 V or
2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
1.205
3.31
3.305
3.3
TJ = −40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = −40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
1.2
3.295
3.29
TPS70912
5
TPS70933
5
1.195
0
10
15
20
25
30
0
10
15
20
25
30
Input Voltage (V)
Input Voltage (V)
G001
G002
Figure 1. 1.2-V Line Regulation vs VIN and Temperature
Figure 2. 3.3-V Line Regulation vs VIN and Temperature
6.51
1.205
TJ = −40°C
TJ = +25°C
TJ = +85°C
TJ = −40°C
TJ = +25°C
TJ = +85°C
1.2
1.195
1.19
6.505
6.5
TJ = +125°C
TJ = +125°C
6.495
6.49
1.185
1.18
TPS70965
10
TPS70912
20
5
15
20
25
30
0
40
60
80
100
120
140
160
Input Voltage (V)
Output Current (mA)
G003
G004
Figure 3. 6.5-V Line Regulation vs VIN and Temperature
Figure 4. 1.2-V Load Regulation vs IOUT and Temperature
3.305
6.505
TJ = −40°C
TJ = +25°C
TJ = +85°C
TJ = −40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
6.5
3.3
6.495
6.49
TJ = +125°C
3.295
6.485
6.48
3.29
3.285
3.28
6.475
6.47
6.465
TPS70933
3.275
TPS70965
6.46
0
20
40
60
80
100
120
140
160
0
20
40
60
80
100
120
140
160
Output Current (mA)
Output Current (mA)
G005
G006
Figure 5. 3.3-V Load Regulation vs IOUT and Temperature
Figure 6. 6.5-V Load Regulation vs IOUT and Temperature
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(typ) + 1 V or
2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
1.205
6.505
IOUT = 10 mA
IOUT = 150 mA
IOUT = 10 mA
IOUT = 150 mA
6.5
1.2
6.495
6.49
1.195
1.19
1.185
1.18
6.485
6.48
6.475
6.47
TPS70912
TPS70965
6.465
−50 −35 −20 −5 10 25 40 55 70 85 100 115 130
Junction Temperature (°C)
−50 −35 −20 −5 10 25 40 55 70 85 100 115 130
Junction Temperature (°C)
G007
G008
Figure 7. VOUT vs Temperature
Figure 8. VOUT vs Temperature
1600
1400
1200
1000
800
600
400
200
0
1600
1400
1200
1000
800
600
400
200
0
TJ = −40°C
TJ = −40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TPS70965
IOUT = 150 mA
TPS70965
120 140 160
2.5
3.5
4.5
5.5
6.5
0
20
40
60
80
100
Input Voltage (V)
Output Current (mA)
G009
G010
Figure 9. Dropout Voltage vs VIN and Temperature
Figure 10. Dropout Voltage vs IOUT and Temperature
500
500
TJ = −40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = −40°C
TJ = +25°C
TJ = +85°C
450
400
350
300
250
200
450
400
350
300
TJ = +125°C
TPS70912
6.5
TPS70933
8.5
3
3.5
4
4.5
5
5.5
6
7
5
5.5
6
6.5
7
7.5
8
Input Voltage (V)
Input Voltage (V)
G011
G012
Figure 11. 1.2-V Current Limit vs VIN and Temperature
Figure 12. 3.3-V Current Limit vs VIN and Temperature
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(typ) + 1 V or
2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
500
450
400
350
300
2
1.8
1.5
1.2
1
TJ = −40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TPS70965
TA = −40°C
TA = +25°C
TA = +85°C
0.8
0.5
TPS70912
5
8
8.5
9
9.5
10
10.5
11
11.5
12
0
10
15
20
25
30
35
Input Voltage (V)
Input Voltage (V)
G013
G014
Figure 13. 6.5-V Current Limit vs VIN and Temperature
Figure 14. GND Current vs VIN and Temperature
2.5
600
500
400
300
200
100
0
TA = −40°C
TA = +25°C
TA = +85°C
2.25
2
1.75
1.5
1.25
1
TA = −40°C
TA = +25°C
TA = +85°C
TPS70933
EN = open
0.75
0.5
TPS70912
0
5
10
15
20
25
30
35
0
20
40
60
80
100
120
140
160
Input Voltage (V)
Output Current (mA)
G035
G015
Figure 15. GND Current vs VIN and Temperature
Figure 16. GND Current vs IOUT and Temperature
0.4
0.3
0.2
0.1
0
100
TA = −40°C
TA = +25°C
TA = +85°C
80
60
40
20
0
VOUT = 2.8 V
VIN = 3.8 V
COUT = 2.2 µF
Shutdown Current
TPS70912
0
5
10
15
20
25
30
35
10
100
1k
10k
100k
1M
10M
Input Voltage (V)
Frequency (Hz)
G016
G017
Figure 17. Shutdown Current vs VIN and Temperature
Figure 18. Power-Supply Rejection Ratio vs Frequency
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(typ) + 1 V or
2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
7
6
5
4
3
2
1
0
140
130
120
110
100
VOUT = 2.8 V
TPS70912
10
100
1k
10k
100k
−50 −35 −20 −5 10 25 40 55 70 85 100 115 130
Temperature (°C)
Frequency (Hz)
G018
G019
Figure 19. Noise
Figure 20. Start-Up Time vs Temperature
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 2.7 V
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 2.7 V
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (100 ms / div)
Time (500 ms / div)
G020
G021
Figure 21. TPS70912 Load Transient (0 mA to 50 mA)
Figure 22. TPS70912 Load Transient (1 mA to 150 mA)
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 2.7 V
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 2.7 V
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (10 ms / div)
Time (100 ms / div)
G022
G023
Figure 23. TPS70912 Load Transient (50 mA to 0 mA)
Figure 24. TPS70912 Load Transient (50 mA to 150 mA)
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(typ) + 1 V or
2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 4.3 V
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 4.3 V
Channel 4
(50 mA / div)
Channel 4
(100 mA / div)
Time (100 ms / div)
Time (500 ms / div)
G024
G025
Figure 25. TPS70933 Load Transient (0 mA to 50 mA)
Figure 26. TPS70933 Load Transient (1 mA to 150 mA)
Channel 2
(200 mV / div)
Channel 2
(200 mV / div)
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 4.3 V
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 4.3 V
Channel 4
(50 mA / div)
Channel 4
(50 mA / div)
Time (10 ms / div)
Time (500 ms / div)
G026
G027
Figure 27. TPS70933 Load Transient (50 mA to 0 mA)
Figure 28. TPS70933 Load Transient (50 mA to 150 mA)
Channel 2 = VOUT
Channel 4 = VIN
IOUT = 10 mA
Channel 2 = VOUT
Channel 4 = VIN
IOUT = 50 mA
Channel 2
(50 mV / div)
Channel 2
(50 mV / div)
Channel 4
(2 V / div)
Channel 4
(2 V / div)
Time (50 ms / div)
Time (50 ms / div)
G028
G029
Figure 29. TPS70912 Line Transient (2.7 V to 3.7 V)
Figure 30. TPS70912 Line Transient (2.7 V to 3.7 V)
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Typical Characteristics (continued)
Over operating temperature range (TJ = –40°C to 125°C), IOUT = 10 mA, VEN = 2 V, COUT = 2.2 μF, and VIN = VOUT(typ) + 1 V or
2.7 V (whichever is greater), unless otherwise noted. Typical values are at TJ = 25°C.
Channel 2 = VOUT
Channel 4 = VIN
IOUT = 10 mA
Channel 2 = VOUT
Channel 4 = VIN
IOUT = 50 mA
Channel 2
(50 mV / div)
Channel 2
(50 mV / div)
Channel 4
(2 V / div)
Channel 4
(2 V / div)
Time (50 ms / div)
Time (50 ms / div)
G030
G031
Figure 31. TPS70933 Line Transient (4.3 V to 5.3 V)
Figure 32. TPS70933 Line Transient (4.3 V to 5.3 V)
Channel 1 = EN
Channel 2 = VOUT
Channel 2
(1 V / div)
Channel 2
(1 V / div)
VIN = 4.3 V
COUT = 2.2 mF
TPS70933
Channel 1
(500 mV / div)
Channel 1
(1 V / div)
Channel 1 = VIN
Channel 2 = VOUT
IOUT = 3 mA
TPS70933
Time (50 ms / div)
Time (500 ms / div)
G032
G033
Figure 33. Power-Up with Enable
Figure 34. Power-Up and Power-Down Response
Channel 2
(1 V / div)
Channel 1
(1 V / div)
Channel 1 = VIN
Channel 2 = VOUT
IOUT = 150 mA
TPS70933
Time (500 ms / div)
G034
Figure 35. Power-Up and Power-Down Response
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7 Detailed Description
7.1 Overview
The TPS709 series of devices are ultralow quiescent current, low-dropout (LDO) linear regulators. The TPS709
offers reverse current protection to block any discharge current from the output into the input. The TPS709 also
features current limit and thermal shutdown for reliable operation.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
Bandgap
EN
Logic
Device
GND
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS709 internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output
voltage is not regulated, and can be measured as (VOUT = ILIMIT × RLOAD). The PMOS pass transistor dissipates
[(VIN – VOUT) × ILIMIT] until a thermal shutdown is triggered and the device turns off. When cool, the device is
turned on by the internal thermal shutdown circuit. If the fault condition continues, the device cycles between
current limit and thermal shutdown; see the Thermal Protection section for more details.
The TPS709 is characterized over the recommended operating output current range up to 150 mA. The internal
current limit begins to limit the output current at a minimum of 200 mA of output current. The TPS709 continues
to operate for output currents between 150 mA and 200 mA but some data sheet parameters may not be met.
7.3.2 Dropout Voltage
The TPS709 use a PMOS pass transistor to achieve low dropout voltage. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element. VDO approximately scales with the output current because
the PMOS device functions like a resistor in dropout.
The ground pin current of many linear voltage regulators increases substantially when the device is operated in
dropout. This increase in ground pin current while operating in dropout can be several orders of magnitude larger
than when the device is not in dropout. The TPS709 employs a special control loop that limits the increase in
ground pin current while operating in dropout. This functionality allows for the most efficient operation while in
dropout conditions that can greatly increase battery run times.
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Feature Description (continued)
7.3.3 Undervoltage Lockout (UVLO)
The TPS709 uses an undervoltage lockout (UVLO) circuit to keep the output shut off until the internal circuitry
operates properly.
7.3.4 Reverse-Current Protection
The TPS709 has integrated reverse-current protection. Reverse-current protection prevents the flow of current
from the OUT pin to the IN pin when output voltage is higher than input voltage. The reverse-current protection
circuitry places the power path in high impedance when the output voltage is higher than the input voltage. This
setting reduces leakage current from the output to the input to 10 nA, typical. The reverse current protection is
always active regardless of the enable pin logic state or if the OUT pin voltage is greater than 1.8 V. Reverse
current can flow if the output voltage is less than 1.8 V and if input voltage is less than the output voltage.
If voltage is applied to the input pin, then the maximum voltage that can be applied to the OUT pin is the lower of
three times the nominal output voltage or 6.5 V. For example, if the 1.2-V output voltage version is used, then the
maximum reverse bias voltage that can be applied to the OUT pin is 3.6 V. If the 5.0-V output voltage version is
used, then the maximum reverse bias voltage that can be applied to the OUT pin is 6.5 V.
7.4 Device Functional Modes
The TPS709 has the following functional modes:
1. Enabled: When the enable pin (EN) goes above 0.9 V, the device is enabled. EN is pulled high by a 300-nA
current source; therefore, EN can be left floating to enable the device. Do not connect EN to VIN. The EN pin
is clamped by a 6.5-V Zener diode. Do not exceed the 7-V absolute maximum rating on the enable pin or
excessive current flowing into the Zener clamp will destroy the device.
2. Disabled: When EN goes below 0.4 V, the device is disabled. During this time, OUT is high impedance and
the current into IN (I(SHUTDOWN)) is typically 150 nA.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS709 is a series of devices that belong to a new family of next-generation voltage regulators. These
devices consume low quiescent current and deliver excellent line and load transient performance. This
performance, combined with low noise and very good PSRR with little (VIN – VOUT) headroom, makes these
devices ideal for RF portable applications, current limit, and thermal protection. The TPS709 is specified from
–40°C to +125°C.
8.1.1 Input and Output Capacitor
The TPS709 devices are stable with output capacitors with an effective capacitance of 2.0 μF or greater for
output voltages below 1.5 V. For output voltages equal or greater than 1.5 V, the minimum effective capacitance
for stability is 1.5 µF. The maximum capacitance for stability is 47 µF. The equivalent series resistance (ESR) of
the output capacitor must be between 0 Ω and 0.2 Ω for stability.
The effective capacitance is the minimum capacitance value of a capacitor after taking into account variations
resulting from tolerances, temperature, and dc bias effects. X5R- and X7R-type ceramic capacitors are
recommended because these capacitors have minimal variation in value and ESR over temperature.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
2.2-µF capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient
response, input ripple, and PSRR. An input capacitor is necessary if line transients greater than 10 V in
magnitude are anticipated.
8.1.2 Transient Response
As with any regulator, increasing the output capacitor size reduces over- and undershoot magnitude, but
increases transient response duration.
8.2 Typical Application
VIN
VOUT
IN
OUT
1 mF
2.2 mF
GND
EN
TPS70933
NC
Figure 36. Wide Input, 3.3-V, Low-IQ Rail
8.2.1 Design Requirements
Table 1 summarizes the design requirements for Figure 36.
Table 1. Design Requirements for a Wide Input, 3.3-V, Low-IQ Rail Application
PARAMETER
VIN
DESIGN SPECIFICATION
5 V to 20 V
3.3 V
VOUT
I(IN) (no load)
IOUT (max)
< 5 µA
150 mA
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8.2.2 Detailed Design Procedure
Select a 2.2-µF, 10-V X7R output capacitor to satisfy the minimum output capacitance requirement with a 3.3-V
dc bias.
Select a 1.0-µF, 25-V X7R input capacitor to provide input noise filtering and eliminate high-frequency voltage
transients.
8.2.3 Application Curves
Channel 2
(200 mV / div)
Channel 1 = EN
Channel 2 = VOUT
Channel 2
(1 V / div)
VIN = 4.3 V
Channel 2 = VOUT
Channel 4 = IOUT
VIN = 4.3 V
COUT = 2.2 mF
TPS70933
Channel 1
(500 mV / div)
Channel 4
(50 mA / div)
Time (500 ms / div)
Time (50 ms / div)
G027
G032
Figure 37. TPS70933 Load Transient (50 mA to 150 mA)
Figure 38. Power-Up with Enable
9 Power Supply Recommendations
This device is designed to operate with an input supply range of 2.7 V to 30 V. If the input supply is noisy,
additional input capacitors with low ESR can help improve output noise performance.
9.1 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to ambient air. Performance data for JEDEC low and high-K boards are given in the
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PDISS) is equal to the product
of the output current and the voltage drop across the output pass element, as shown in Equation 1:
PDISS = (VIN – VOUT) × IOUT
(1)
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10 Layout
10.1 Layout Guidelines
Place input and output capacitors as close to the device pins as possible. To improve ac performance (such as
PSRR, output noise, and transient response), TI recommends that the board be designed with separate ground
planes for VIN and VOUT, with the ground plane connected only at the GND pin of the device. In addition, the
ground connection for the output capacitor must be connected directly to the device GND pin.
10.1.1 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the
device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a
result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C, maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least
35°C above the maximum expected ambient condition of the particular application. This configuration produces a
worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The TPS709 internal protection circuitry is designed to protect against overload conditions. This circuitry is not
intended to replace proper heatsinking. Continuously running the TPS709 into thermal shutdown degrades
device reliability.
10.2 Layout Example
VOUT
VIN
5
1
CIN
COUT
2
3
4
GND PLANE
Represents via used for
application specific connections
Figure 39. Layout Example for DBV Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the
TPS709xx. The TPS70933EVM-110 evaluation module (and related user guide) can be requested at the Texas
Instruments website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS709 is available through the product folders under
Simulation Models.
11.1.2 Device Nomenclature
Table 2. Device Nomenclature(1)
PRODUCT
VOUT
TPS709xx(x)yyyz
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two
digits are used in the ordering number; otherwise, three digits are used (for example, 28 =
2.8 V; 125 = 1.25 V).
YYY is the package designator.
Z is the tape and reel quantity (R = 3000, T = 250).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
•
TPS70933EVM-110 Evaluation Module User Guide, SLVU689
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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11.4 Trademarks
E2E is a trademark of Texas Instruments.
Zigbee is a trademark of ZigBee Alliance.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DRV
DRV
Qty
3000
250
(1)
(2)
(3)
(4/5)
(6)
TPS70912DBVR
TPS70912DBVT
TPS70912DRVR
TPS70912DRVT
TPS709135DBVR
TPS709135DBVT
TPS70915DBVR
TPS70915DBVT
TPS70915DRVR
TPS70915DRVT
TPS70916DBVR
TPS70916DBVT
TPS70918DBVR
TPS70918DBVT
TPS70918DRVR
TPS70918DRVRM3
ACTIVE
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
5
5
6
6
5
5
5
5
6
6
5
5
5
5
6
6
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SCX
SCX
SCX
SCX
SCY
SCY
SIM
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SIM
3000
250
Green (RoHS
& no Sb/Br)
SIM
Green (RoHS
& no Sb/Br)
SIM
3000
250
Green (RoHS
& no Sb/Br)
SCZ
SCZ
SDA
SDA
SDA
SDA
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
3000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DRV
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS70918DRVT
TPS70919DBVR
TPS70919DBVT
TPS70925DBVR
TPS70925DBVT
TPS70925DRVR
TPS70925DRVT
TPS70927DBVR
TPS70927DBVT
TPS70928DBVR
TPS70928DBVT
TPS70930DBVR
TPS70930DBVT
TPS70930DRVR
TPS70930DRVT
TPS70933DBVR
TPS70933DBVT
ACTIVE
WSON
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
6
5
5
5
5
6
6
5
5
5
5
5
5
6
6
5
5
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SDA
SDB
SDB
SDC
SDC
SDC
SDC
SDD
SDD
SDE
SDE
SDF
SDF
SDF
SDF
SDG
SDG
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DRV
DRV
DRV
DBV
DBV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
DRV
DRV
DRV
DBV
DBV
Qty
3000
3000
250
(1)
(2)
(3)
(4/5)
(6)
TPS70933DRVR
TPS70933DRVRM3
TPS70933DRVT
TPS70936DBVR
TPS70936DBVT
TPS70936DRVR
TPS70938DBVR
TPS70938DBVT
TPS70939DBVR
TPS70939DBVT
TPS70950DBVR
TPS70950DBVT
TPS70950DRVR
TPS70950DRVRM3
TPS70950DRVT
TPS70960DBVR
TPS70960DBVT
ACTIVE
WSON
WSON
WSON
SOT-23
SOT-23
WSON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
WSON
SOT-23
SOT-23
6
6
6
5
5
6
5
5
5
5
5
5
6
6
6
5
5
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
SDG
SDG
SDG
SEJ
SEJ
1FV
SIC
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SIC
3000
250
Green (RoHS
& no Sb/Br)
SID
Green (RoHS
& no Sb/Br)
SID
3000
250
Green (RoHS
& no Sb/Br)
SDH
SDH
SDH
SDH
SDH
SIT
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SIT
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
Qty
3000
250
(1)
(2)
(3)
(4/5)
(6)
TPS709A30DBVR
TPS709A30DBVT
TPS709A33DBVR
TPS709A33DBVT
TPS709B33DBVR
TPS709B33DBVT
TPS709B345DBVR
TPS709B50DBVR
TPS709B50DBVT
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
5
5
5
5
5
5
5
5
5
Green (RoHS
& no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
11RF
11RF
11SF
11SF
13C7
13C7
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
1XSW
13D7
13D7
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
26-Oct-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS709 :
Automotive: TPS709-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS70912DBVR
TPS70912DBVT
TPS70912DRVR
TPS70912DRVT
TPS709135DBVR
TPS709135DBVT
TPS70915DBVR
TPS70915DBVT
TPS70915DRVR
TPS70915DRVR
TPS70915DRVT
TPS70915DRVT
TPS70916DBVR
TPS70916DBVT
TPS70918DBVR
TPS70918DBVT
TPS70918DRVR
TPS70918DRVT
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DRV
DRV
DRV
DRV
DBV
DBV
DBV
DBV
DRV
DRV
5
5
6
6
5
5
5
5
6
6
6
6
5
5
5
5
6
6
3000
250
178.0
178.0
180.0
180.0
178.0
178.0
178.0
178.0
180.0
179.0
180.0
179.0
178.0
178.0
178.0
178.0
180.0
180.0
9.0
9.0
8.4
8.4
9.0
9.0
9.0
9.0
8.4
8.4
8.4
8.4
9.0
9.0
9.0
9.0
8.4
8.4
3.3
3.23
2.3
3.2
3.17
2.3
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q2
Q3
Q3
Q3
Q3
Q2
Q2
Q2
Q2
Q3
Q3
Q3
Q3
Q2
Q2
1.37
1.15
1.15
1.37
1.37
1.37
1.37
1.15
1.2
3000
250
2.3
2.3
3000
250
3.23
3.23
3.23
3.23
2.3
3.17
3.17
3.17
3.17
2.3
3000
250
3000
3000
250
2.2
2.2
2.3
2.3
1.15
1.2
250
2.2
2.2
3000
250
3.23
3.23
3.23
3.23
2.3
3.17
3.17
3.17
3.17
2.3
1.37
1.37
1.37
1.37
1.15
1.15
3000
250
3000
250
2.3
2.3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS70919DBVR
TPS70919DBVT
TPS70925DBVR
TPS70925DBVT
TPS70925DRVR
TPS70925DRVT
TPS70927DBVR
TPS70927DBVT
TPS70928DBVR
TPS70928DBVT
TPS70930DBVR
TPS70930DBVT
TPS70930DRVR
TPS70930DRVT
TPS70933DBVR
TPS70933DBVT
TPS70933DRVR
TPS70933DRVT
TPS70936DBVR
TPS70936DBVT
TPS70936DRVR
TPS70938DBVR
TPS70938DBVT
TPS70939DBVR
TPS70939DBVT
TPS70950DBVR
TPS70950DBVT
TPS70950DRVR
TPS70950DRVT
TPS70960DBVR
TPS70960DBVT
TPS709A30DBVR
TPS709A30DBVT
TPS709A33DBVR
TPS709A33DBVT
TPS709B33DBVR
TPS709B33DBVT
TPS709B345DBVR
TPS709B50DBVR
TPS709B50DBVT
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
6
6
5
5
5
5
5
5
6
6
5
5
6
6
5
5
6
5
5
5
5
5
5
6
6
5
5
5
5
5
5
5
5
5
5
5
3000
250
178.0
178.0
178.0
178.0
180.0
180.0
178.0
178.0
178.0
178.0
178.0
178.0
180.0
180.0
178.0
178.0
180.0
180.0
178.0
178.0
180.0
178.0
178.0
178.0
178.0
178.0
178.0
180.0
180.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
178.0
9.0
9.0
9.0
9.0
8.4
8.4
9.0
9.0
9.0
9.0
9.0
9.0
8.4
8.4
9.0
9.0
8.4
8.4
9.0
9.0
8.4
9.0
9.0
9.0
9.0
9.0
9.0
8.4
8.4
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
9.0
3.23
3.23
3.23
3.3
3.17
3.17
3.17
3.2
1.37
1.37
1.37
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q2
Q2
Q3
Q3
Q3
Q3
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q3
Q3
Q3
Q3
Q3
Q3
Q2
Q2
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
250
2.3
2.3
1.15
1.15
1.37
1.37
1.37
1.37
1.37
1.37
1.15
1.15
1.4
2.3
2.3
3000
250
3.23
3.23
3.23
3.23
3.23
3.23
2.3
3.17
3.17
3.17
3.17
3.17
3.17
2.3
3000
250
3000
250
3000
250
2.3
2.3
3000
250
3.3
3.2
3.23
2.3
3.17
2.3
1.37
1.15
1.15
1.4
3000
250
2.3
2.3
3000
250
3.3
3.2
3.23
2.3
3.17
2.3
1.37
1.15
1.37
1.37
1.37
1.37
1.37
1.37
1.15
1.15
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
1.37
3000
3000
250
3.23
3.23
3.23
3.23
3.23
3.23
2.3
3.17
3.17
3.17
3.17
3.17
3.17
2.3
3000
250
3000
250
3000
250
2.3
2.3
3000
250
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.23
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3.17
3000
250
3000
250
3000
250
3000
3000
250
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS70912DBVR
TPS70912DBVT
TPS70912DRVR
TPS70912DRVT
TPS709135DBVR
TPS709135DBVT
TPS70915DBVR
TPS70915DBVT
TPS70915DRVR
TPS70915DRVR
TPS70915DRVT
TPS70915DRVT
TPS70916DBVR
TPS70916DBVT
TPS70918DBVR
TPS70918DBVT
TPS70918DRVR
TPS70918DRVT
TPS70919DBVR
TPS70919DBVT
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DRV
DRV
DRV
DRV
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
5
5
6
6
5
5
5
5
6
6
6
6
5
5
5
5
6
6
5
5
3000
250
180.0
180.0
182.0
182.0
180.0
180.0
180.0
180.0
182.0
203.0
182.0
203.0
180.0
180.0
180.0
180.0
182.0
182.0
180.0
180.0
180.0
180.0
182.0
182.0
180.0
180.0
180.0
180.0
182.0
203.0
182.0
203.0
180.0
180.0
180.0
180.0
182.0
182.0
180.0
180.0
18.0
18.0
20.0
20.0
18.0
18.0
18.0
18.0
20.0
35.0
20.0
35.0
18.0
18.0
18.0
18.0
20.0
20.0
18.0
18.0
3000
250
3000
250
3000
250
3000
3000
250
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2020
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS70925DBVR
TPS70925DBVT
TPS70925DRVR
TPS70925DRVT
TPS70927DBVR
TPS70927DBVT
TPS70928DBVR
TPS70928DBVT
TPS70930DBVR
TPS70930DBVT
TPS70930DRVR
TPS70930DRVT
TPS70933DBVR
TPS70933DBVT
TPS70933DRVR
TPS70933DRVT
TPS70936DBVR
TPS70936DBVT
TPS70936DRVR
TPS70938DBVR
TPS70938DBVT
TPS70939DBVR
TPS70939DBVT
TPS70950DBVR
TPS70950DBVT
TPS70950DRVR
TPS70950DRVT
TPS70960DBVR
TPS70960DBVT
TPS709A30DBVR
TPS709A30DBVT
TPS709A33DBVR
TPS709A33DBVT
TPS709B33DBVR
TPS709B33DBVT
TPS709B345DBVR
TPS709B50DBVR
TPS709B50DBVT
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
WSON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
WSON
WSON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DRV
DBV
DBV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
DRV
DRV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
6
6
5
5
5
5
5
5
6
6
5
5
6
6
5
5
6
5
5
5
5
5
5
6
6
5
5
5
5
5
5
5
5
5
5
5
3000
250
180.0
180.0
182.0
182.0
180.0
180.0
180.0
180.0
180.0
180.0
182.0
182.0
180.0
180.0
182.0
182.0
180.0
180.0
210.0
180.0
180.0
180.0
180.0
180.0
180.0
182.0
182.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
182.0
182.0
180.0
180.0
180.0
180.0
180.0
180.0
182.0
182.0
180.0
180.0
182.0
182.0
180.0
180.0
185.0
180.0
180.0
180.0
180.0
180.0
180.0
182.0
182.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
18.0
18.0
20.0
20.0
18.0
18.0
18.0
18.0
18.0
18.0
20.0
20.0
18.0
18.0
20.0
20.0
18.0
18.0
35.0
18.0
18.0
18.0
18.0
18.0
18.0
20.0
20.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
18.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
3000
250
Pack Materials-Page 4
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DRV0006D
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A B
C
0.05
4225563/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225563/A 12/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4225563/A 12/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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