TPS71256DRC [TI]
DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO10, 3 X 3 MM, PLASTIC, SON-10;
| 型号： | TPS71256DRC |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO10, 3 X 3 MM, PLASTIC, SON-10 转换器 开关 |
| 文件： | 总28页 (文件大小：537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS61130
TPS61131
TPS61132
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SLVS431A–JUNE 2002–REVISED AUGUST 2003
SYNCHRONOUS SEPIC / FLYBACK CONVERTER WITH 1.1A SWITCH
AND INTEGRATED LDO
FEATURES
DESCRIPTION
•
Synchronous, Up To 90% Efficient, SEPIC
Converter With 300-mA Output Current From
2.5-V Input
The TPS6113x devices provide a complete power
supply solution for products powered by either a
one-cell Li-Ion or Li-Polymer or a two up to four-cell
Alkaline, NiCd or NiMH batteries. The device can gen-
erate two regulated output voltages that are either
adjusted by an external resistor divider or fixed
internally on the chip. It also provides a simple and
efficient buck-boost solution for generating 3.3 V out of
a one-cell Li-Ion or Li-Polymer battery at a maximum
output current of at least 300 mA with supply voltages
down to 1.8 V. The implemented SEPIC converter is
based on a fixed frequency, pulse-width-modulation
(PWM) controller using a synchronous rectifier to ob-
tain maximum efficiency. The maximum peak current in
the SEPIC switch is limited to a value of 1600 mA.
•
Integrated 200-mA Reverse Voltage Protected
LDO for DC/DC Output Voltage Post Regu-
lation or Second Output Voltage
•
•
Dual Input or Dual Output Mode
Available in a 16 pin QFN 4x4 or in a
TSSOP-16 Package
•
40-µA (Typical) Total Device Quiescent Cur-
rent
•
•
Input Voltage Range: 1.8-V to 5.5-V
Adjustable Output Voltage up to 5.5-V, Fixed
Output Voltage Options
The converter can be disabled to minimize battery
drain. During shutdown, the load is completely discon-
nected from the battery. A low-EMI mode is im-
plemented to reduce ringing and in effect lower radi-
ated electromagnetic energy when the converter enters
the discontinuous conduction mode. A power good
output at the SEPIC stage provides additional control of
any connected circuits like cascaded power supply
stages or microprocessors.
•
Power Save Mode for Improved Efficiency at
Low Output Power
•
•
•
•
High Efficient Li-Ion to 3.3-V Conversion
Low Battery Comparator
Power Good Output
Low EMI-Converter (Integrated Antiringing
Switch)
The built-in LDO can be used for a second output
voltage derived either from the SEPIC output or directly
from the battery. The output voltage of this LDO can be
programmed by an external resistor divider or is fixed
internally on the chip. The LDO can be enabled separ-
ately i.e., using the power good of the SEPIC stage.
•
•
Load Disconnect During Shutdown
Overtemperature Protection
APPLICATIONS
•
All Single Cell Li, Dual or Triple Cell Battery or
USB Powered Products as MP-3 Player, PDAs,
and Other Portable Equipment
The device is packaged in a 16-pin QFN 4 x 4 mm
(16RSA) or in a 16-pin TSSOP (16 PW) package.
22 mH
SWN
VBAT
LBI
22 mH
10 mF
1.8 V up to 6 V
Input
SWP
10 mF
V
VOUT
Out1
e.g. 3.3 V up to 300 mA
TPS61130
100 mF
FB
ON
OFF
SKIPEN
EN
PGOOD
LBO
Control
Outputs
Control
OFF
ON
ON
Inputs
LDOIN
LDOEN
V
Out2
OFF
LDOOUT
e.g. 1.5 V up to 300 mA
2.2 mF
LDOSENSE
GND PGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily in-
cludetestingofallparameters.
Copyright © 2002–2003, Texas Instruments Incorporated
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
(1)
AVAILABLE OUTPUT VOLTAGE OPTIONS
OUTPUT VOLTAGE
DC/DC
OUTPUT VOLTAGE
LDO
(2)
TA
PACKAGE
16-Pin TSSOP
PART NUMBER
TPS61130PW
Adjustable
3.3 V
Adjustable
3.3 V
16-Pin TSSOP
TPS61131PW
TPS61132PW
TPS61130RSA
TPS61132RSA
40°C to 85°C
3.3 V
1.5 V
16-Pin TSSOP
Adjustable
3.3 V
Adjustable
1.5 V
16-Pin QFN 4x4mm
16-Pin QFN 4x4mm
(1)
(2)
Contact the factory to check availability of other fixed output voltage versions.
The packages are available taped and reeled. Add R suffix to device type (e.g., TPS61130PWR or TPS61130RSAR) to order
quantities of 2000 devices per reel for the TSSOP (PW) package and 3000 devices per reel for the QFN (RSA) package.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
TPS61130
TPS61131
TPS61132
Input voltage range on FB
-0.3 V to 3.6 V
-0.3 V to 12 V
-7.0 V to 7.0 V
-12 V
Input voltage range on SWN
Input voltage range on SWP
Maximum voltage between SWP and VOUT
Input voltage range on SWN, VOUT, LDOIN, LDOOUT, LDOEN, LDOSENSE, PGOOD, LBO, VBAT, LBI,
SKIPEN, EN
-0.3 V to 7 V
Operating free air temperature range TA
Maximum junction temperature TJ
Storage temperature range Tstg
-40°C to 85°C
150°C
-65°C to 150°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
1.8
10
NOM MAX UNIT
Supply voltage at VBAT, VI
6.5
V
DC/DC—inductance, L
22
10
µH
µF
µF
µF
µF
DC/DC—input capacitance, Ci
DC/DC—output capacitance, Co
LDO—input capacitance, Ci
LDO—output capacitance, Co
Operating virtual junction temperature, TJ
22
100
1
1
2.2
-40
125 °C
2
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
ELECTRICAL CHARACTERISITICS
over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25°C) (unless otherwise noted)
DC/DC STAGE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI
Input voltage range
1.8
6.5
V
Adjustable output voltage
range (TPS61130)
VO
2.5
5.5
V
Vref
f
Reference voltage
485
400
500
500
515
600
mV
kHz
mA
mA
mΩ
mΩ
Oscillator frequency
Switch current limit
ISW
VOUT= 3.3 V
1100
1300
1600
Startup current limit
SWN switch on resistance
SWP switch on resistance
0.4 x ISW
200
VOUT= 3.3 V
VOUT= 3.3 V
350
500
250
Total accuracy (including line
and load regulation)
3
%
IO= 0 mA, VEN = VBAT = 1.8 V, VOUT =
3.3 V, ENLDO = 0 V
into VBAT
10
25
µA
DC/DC quiescent
current
IO = 0 mA, VEN = VBAT = 1.8 V, VOUT =
3.3 V, ENLDO = 0 V
into VOUT
10
25
1
µA
µA
DC/DC shutdown current
VEN = 0 V
0.2
LDO STAGE
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VI(LDO)
VO(LDO)
IO(max)
Input voltage range
1.8
7
V
Adjustable output voltage range
(TPS61130)
0.9
5.5
V
Output current
200
320
mA
mA
mV
LDO short circuit current limit
Minimum voltage drop
500
300
IO =200 mA
Total accuracy (including line
and load regulation)
IO≥ 1 mA
±3%
0.6%
0.6%
LDOIN change from 1.8 V to 2.6 V at 100
mA, LDOOUT = 1.5 V
Line regulation
Load regulation
Load change from 10% to 90%,LDOIN = 3.3
V
LDO quiescent current
LDO shutdown current
LDOIN = 7 V, VBAT = 1.8 V, EN = VBAT
LDOEN = 0 V, LDOIN = 7 V
20
30
1
µA
µA
0.1
3
TPS61130
TPS61131
TPS61132
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SLVS431A–JUNE 2002–REVISED AUGUST 2003
CONTROL STAGE
PARAMETER
TEST CONDITIONS
VLBI voltage decreasing
MIN
TYP
500
10
MAX
UNIT
VIL
LBI voltage threshold
LBI input hysteresis
490
510
mV
mV
µA
V
LBI input current
EN = VBAT or GND
0.01
0.04
100
0.01
0.1
0.4
LBO output low voltage
LBO output low current
LBO output leakage current
EN, SKIPEN input low voltage
VO = 3.3 V, IOI = 100 µA
µA
µA
V
VLBO = 7 V
0.1
VIL
0.2 ×
VBAT
VIH
VIL
VIH
EN, SKIPEN input high voltage
LDOEN input low voltage
0.8 × VBAT
V
V
0.2 ×
VLDOIN
LDOEN input high voltage
EN, SKIPEN input current
Power-Good threshold
0.8 × VLDOIN
V
µA
V
Clamped on GND or VBAT
VO = 3.3 V
0.01
0.92xVo
30
0.1
0.9xVo
0.95xVo
Power-Good delay
µs
V
Power-Good output low voltage
Power-Good output low current
VO = 3.3 V, IOI = 100 µA
VPG = 7 V
0.04
0.4
0.1
100
µA
µA
Power-Good output leakage cur-
rent
0.01
Over-Temperature protection
Over-Temperature hysteresis
140
20
°C
°C
PIN ASSIGNMENTS
PW Package
(Top View)
RSA Package
(Top View)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SWP
SWN
PGND
VBAT
LBI
SKIPEN
EN
LDOEN
VOUT
FB
PGOOD
LBO
GND
LDOSENSE
LDOOUT
LDOIN
PGND
VBAT
PGOOD
LBO
LBI
GND
SKIPEN
LDOSENSE
4
TPS61130
TPS61131
TPS61132
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SLVS431A–JUNE 2002–REVISED AUGUST 2003
Terminal Functions
TERMINAL
NO.
I/O
Description
NAME
PW
RSA
EN
7
5
I
I
DC/DC-enable input. (1/VBAT enabled,
0/GND disabled)
FB
15
13
DC/DC voltage feedback of adjustable
versions
GND
LBI
12
5
10
3
I/O
I
Control/logic ground
Low battery comparator input
(comparator enabled with EN)
LBO
13
8
11
6
O
I
Low battery comparator output (open
drain)
LDOEN
LDO-enable input (1/LDOIN enabled,
0/GND disabled)
LDOOUT
LDOIN
10
9
8
7
9
O
I
LDO output
LDO input
LDOSENSE
11
I
LDO feedback for voltage adjustment,
must be connected to LDOOUT at fixed
output voltage versions
SWP
PGND
1
3
15
1
I
DC/DC rectifying switch input
Power ground
I/O
O
PGOOD
14
12
DC/DC output power good (1 : good, 0 :
failure) (open drain)
SKIPEN
6
4
I
Enable/disable power save mode
(1/VBAT enabled, 0/GND disabled)
SWN
VBAT
VOUT
2
4
16
2
I
I
DC/DC switch input
Supply pin
16
14
O
DC/DC output
5
TPS61130
TPS61131
TPS61132
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SLVS431A–JUNE 2002–REVISED AUGUST 2003
FUNCTIONAL BLOCK DIAGRAM
SWP
SWN
Backgate
Control
Anti-
VBAT
Ringing
VOUT
100 kΩ
VOUT
20 pF
V
Gate
Control
max
Control
PGND
FB
PGND
PGND
Error
Amplifier
_
+
Regulator
+
_
V
ref
= 0.5 V
GND
Control Logic
Oscillator
Temperature
Control
EN
PGOOD
ENLDO
SYNC
LDOIN
Backgate
Control
GND
LDOOUT
LDOFB
Error
Amplifier
LBO
LBI
_
+
Low Battery
Comparator
_
+
_
V
ref
= 0.5 V
+
GND
+
_
V
ref
= 0.5 V
GND
6
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
C7
10 µF
U1
L1−A
L1−B
SWN
VBAT
SWP
22 µH
22 µH
V
VOUT
FB
CC1
R3
Boost Output
C6
2.2 µF
C4
100 µF
R1
C3
Power
10 µF
Supply
LBI
R6
R5
R2
LDOIN
V
CC2
SKIPEN
EN
LDOOUT
LDO Output
C5
LDOSENSE
LBO
2.2 µF
R7
R4
List of Components:
U1 = TPS6113xPW
L1 = Coiltronics DRQ74−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
R9
LDOEN
Control
Outputs
PGOOD
PGND
GND
TPS6113xPW
7
TPS61130
TPS61131
TPS61132
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SLVS431A–JUNE 2002–REVISED AUGUST 2003
TYPICAL CHARACTERISTICS
Table of Graphs
SEPIC Converter
Figure
Maximum output current
vs Input voltage (TPS61130) (VO = 3.3 V, 5.0V, 2.5V)
vs Output current (TPS61130) (VO = 2.5 V, VI = 1.8 V)
vs Output current (TPS61132) (VO = 3.3 V, VI = 1.8 V, 3.8 V)
vs Output current (TPS61130) (VO = 5.0 V, VI = 3.6 V, 6.0 V)
vs Input voltage (TPS61132)
1, 2
3
4
Efficiency
5
6
Output voltage
vs Output current (TPS61132)
7
No-load supply current into VBAT
No-load supply current into VOUT
vs Input voltage (TPS61132)
8
vs Input voltage (TPS61132)
9
Output voltage in continuous mode (TPS61132)
Output voltage in power save mode (TPS61132)
Load transient response (TPS61132)
10
11
12
13
14
Waveforms
Line transient response (TPS61132)
Start-up after enable (TPS61132)
LDO
vs Input voltage (VO = 2.5 V, 3.3 V)
vs Input voltage (VO = 1.5 V, 1.8 V)
vs Output current (TPS61131)
vs Output current (TPS61131, TPS61132)
vs LDOIN input voltage (TPS61132)
vs Frequency (TPS61132)
15
16
17
18
19
20
21
22
23
Maximum output current
Output voltage
Dropout voltage
Supply current into LDOIN
PSRR
Load transient response
Waveforms
Line transient response
Start-up after enable
TPS61130
TPS61130
MAXIMUM SEPIC CONVERTER OUTPUT CURRENT
MAXIMUM SEPIC CONVERTER OUTPUT CURRENT
vs
INPUT VOLTAGE
0.7
vs
INPUT VOLTAGE
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.6
V
= 2.5 V
O
V
O
= 3.3 V
0.5
0.4
0.3
0.2
V
O
= 5 V
0.1
0
0.05
0
1.8 2.2 2.6 3 3.4 3.8 4.2 4.6 5 5.4 5.8 6.2 6.6 7
1.8 2
4
5
7
3
6
V − Input Voltage − V
I
V − Input Voltage − V
I
Figure 1.
Figure 2.
8
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
TPS61130
SEPIC CONVERTER EFFICIENCY
vs
TPS61132
SEPIC CONVERTER EFFICIENCY
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
100
90
80
70
60
50
40
30
20
TPS61132
V
= 2.5 V
O
VBAT = 3.8 V
90
80
70
60
50
40
30
20
10
0
V = 1.8 V
I
VBAT = 1.8 V
10
0
0.10
1
I
10
100
1000
0
1
I
10
100
1000
− Output Current − mA
− Output Current − mA
O
O
Figure 3.
Figure 4.
TPS61130
TPS61132
SEPIC CONVERTER EFFICIENCY
SEPIC CONVERTER EFFICIENCY
vs
vs
OUTPUT CURRENT
INPUT VOLTAGE
100
100
90
80
70
60
50
40
30
20
TPS61130
VBAT = 6 V
VBAT = 3.6 V
95
90
I
O
= 100 mA
I
O
= 200 mA
85
80
75
I
O
= 10 mA
70
65
60
10
0
1.8
3
5
7
0
1
10
100
1000
V − Input Voltage − V
I
I
O
− Output Current − mA
Figure 5.
Figure 6.
9
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
TPS61132
TPS61132
SEPIC CONVERTER OUTPUT VOLTAGE
NO-LOAD SUPPLY CURRENT INTO VBAT
vs
vs
OUTPUT CURRENT
INPUT VOLTAGE
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
14
12
10
8
V = 2.4 V
I
85°C
25°C
−40°C
6
4
2
3.22
3.20
0
0
100
200
300
400
1.8
2
2.2
2.4
2.6
2.8
3
3.2
I
O
− Output Current − mA
V − Input Voltage − V
I
Figure 7.
Figure 8.
TPS61132
NO-LOAD SUPPLY CURRENT INTO VOUT
TPS61132
vs
SEPIC CONVERTER OUTPUT VOLTAGE
IN CONTINUOUS MODE
INPUT VOLTAGE
14
12
10
8
V = 3.3 V, R = 33 W
85°C
I
L
Output Voltage
20 mV/Div, AC
25°C
−40°C
6
Inductor Current
100 mA/Div, DC
4
2
V
O
= 3.3 V
0
Timebase − 1 µs/Div
1.8
2
2.2
2.4
2.6
2.8
3
3.2
V − Input Voltage − V
I
Figure 9.
Figure 10.
10
TPS61130
TPS61131
TPS61132
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SLVS431A–JUNE 2002–REVISED AUGUST 2003
TPS61132
SEPIC CONVERTER OUTPUT VOLTAGE
IN POWER SAVE MODE
TPS61132
SEPIC CONVERTER LOAD TRANSIENT RESPONSE
V = 3.3 V
I
V = 3.3 V, R = 330 W
I
L
I
L
= 60 mA to 140 mA
Input Current
100 mA/Div, DC
Output Voltage
50 mV/Div, AC
Output Voltage
20 mV/Div, AC
Inductor Current
100 mA/Div, DC
V
O
= 3.3 V
V
O
= 3.3 V
Timebase − 200 µs/Div
Timebase − 500 µs/Div
Figure 11.
Figure 12.
TPS61132
TPS61132
SEPIC CONVERTER LINE TRANSIENT RESPONSE
V = 3.0 V to 4.2 V
SEPIC CONVERTER START-UP AFTER ENABLE
I
Enable
5 V/Div, DC
Input Voltage
1 V/Div, DC
R
L
= 33 W
Output Voltage
2 V/Div, DC
Voltage at SW
5 V/Div, DC
Output Voltage
50 mV/Div, AC
Input Current
200 mA/Div, DC
V = 3.6 V, RL = 66 W
I
V
O
= 3.3 V
V
O
= 3.3 V
Timebase − 400 µs/Div
Timebase − 200 µs/Div
Figure 13.
Figure 14.
11
TPS61130
TPS61131
TPS61132
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SLVS431A–JUNE 2002–REVISED AUGUST 2003
TPS61130
MAXIMUM LDO OUTPUT CURRENT
MAXIMUM LDO OUTPUT CURRENT
vs
vs
LDO INPUT VOLTAGE
LDO INPUT VOLTAGE
400
400
V
O
= 3.3 V
V
O
= 1.5 V
350
300
250
350
300
250
200
150
100
V
O
= 1.8 V
V
O
= 2.5 V
200
150
100
50
0
50
0
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5 7
LDO Input Voltage − V
LDO Input Voltage − V
Figure 15.
Figure 16.
TPS61131
LDO OUTPUT VOLTAGE
vs
LDO DROPOUT VOLTAGE
vs
LDO OUTPUT CURRENT
LDO OUTPUT CURRENT
3.5
3.4
3.38
3
3.36
3.34
3.32
3.3
TPS61131
(LDO OUTPUT
VOLTAGE 1.5 V)
2.5
2
TPS61132
(LDO OUTPUT
VOLTAGE 3.3 V)
1.5
3.28
3.26
3.24
1
0.5
0
3.22
3.2
10
60
110
160
210
260
310
0
50
100 150 200 250 300 350 400
LDO Output Current − mA
Figure 17.
LDO Output Current − mA
Figure 18.
12
TPS61130
TPS61131
TPS61132
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SLVS431A–JUNE 2002–REVISED AUGUST 2003
TPS61132
SUPPLY CURRENT INTO LDOIN
vs
TPS61132
PSRR
vs
LDOIN INPUT VOLTAGE
FREQUENCY
80
70
LDOIN = 3.3 V
85°C
20
15
10
LDO Output Current 10 mA
25°C
60
50
−40°C
40
30
LDO Output Current 200 mA
20
5
10
0
0
1.8
2
2.2
2.4
2.6
2.8
3
3.2
10k
100k
1k
10M
1M
f − Frequency − Hz
LDOIN Input Voltage − V
Figure 19.
Figure 20.
TPS61132
TPS61132
LDO LOAD TRANSIENT RESPONSE
LDO LINE TRANSIENT RESPONSE
V = 1.8 V to 2.6 V
V = 3.3 V
I
I
I
L
= 20 mA to 180 mA
Output Current
100 mA/Div, DC
R
L
= 15 W
Input Voltage
1 V/Div, DC
Output Voltage
10 mV/Div, AC
Output Voltage
20 mV/Div, AC
V
O
= 1.5 V
V
O
= 1.5 V
Timebase − 500 µs/Div
Figure 21.
Timebase − 2 ms/Div
Figure 22.
13
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
TPS61132
LDO START-UP AFTER ENABLE
V = 3.3 V
I
LDO-Enable
5 V/Div, DC
R
L
= 15 W
LDO-Output Voltage
1 V/Div, DC
Input Current
200 mA/Div, DC
V
O
= 1.5 V
Timebase − 20 µs/Div
Figure 23.
14
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
APPLICATION INFORMATION
DESIGN PROCEDURE
The TPS6113x dc/dc converters are intended for systems powered by a dual up to 4 cell NiCd or NiMH battery
with a typical terminal voltage between 1.8 V and 6.0 V. They can also be used in systems powered by one-cell
Li-Ion with a typical stack voltage between 2.5 V and 4.2 V. Additionally, two up to four primary and secondary
alkaline battery cells can be the power source in systems where the TPS6113x is used.
Programming the Output Voltage
DC/DC Converter
The output voltage of the TPS61130 dc/dc converter section can be adjusted with an external resistor divider.
The typical value of the voltage on the FB pin is 500 mV. The maximum allowed value for the output voltage is
5.5 V. The current through the resistive divider should be about 100 times greater than the current into the FB
pin. The typical current into the FB pin is 0.01 µA and the voltage across R6 is typically 500 mV. Based on those
two values, the recommended value for R6 should be lower than 500 kΩ, in order to set the divider current at 1
µA or higher. Because of internal compensation circuitry the value for this resistor should be in the range of 200
kΩ. From that, the value of resistor R3, depending on the needed output voltage (VO), can be calculated using
Equation 1:
V
V
O
O
R3 + R6
* 1 + 180 kW
* 1
ǒ Ǔ ǒ Ǔ
V
500 mV
FB
(1)
If as an example, an output voltage of 3.3 V is needed, a 1-MΩ resistor should be chosen for R3. If for any
reason the value for R6 is chosen significantly lower than 200 kΩ additional capacitance in parallel to R3 is
recommended. The required capacitance value can be easily calculated using Equation 2.
200 kW
R6
ǒ
* 1Ǔ
C
+ 20 pF
parR3
(2)
C7
10 µF
U1
L1–A
22 µH
L1–B
SWP
SWN
VBAT
22 µH
V
CC1
VOUT
FB
R3
Boost Output
C6
2.2 µF
C4
100 µF
R1
C3
10 µF
Power
Supply
LBI
R6
R5
R2
LDOIN
V
CC2
SKIPEN
EN
LDOOUT
C5
2.2 µF
LDO Output
LDOSENSE
R7
R9
R4
LDOEN
LBO
Control
Outputs
PGOOD
PGND
GND
TPS6113xPW
Figure 24. Typical Application Circuit for Adjustable Output Voltage Option
15
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
APPLICATION INFORMATION (continued)
LDO
Programming the output voltage at the LDO follows almost the same rules as at the dc/dc converter section. The
maximum programmable output voltage at the LDO is 5.5 V. Since reference and internal feedback circuitry are
similar, as they are at the boost converter section, R4 also should be in the 200-kΩ range. The calculation of the
value of R5 can be done using the following Equation 3:
V
V
O
O
R5 + R4
–1 + 180 kW
–1
ǒ Ǔ ǒ Ǔ
V
500 mV
FB
(3)
If as an example, an output voltage of 1.5 V is needed, a 360 kΩ-resistor should be chosen for R5.
Programming the LBI/LBO Threshold Voltage
The current through the resistive divider should be about 100 times greater than the current into the LBI pin. The
typical current into the LBI pin is 0.01 µA, and the voltage across R2 is equal to the LBI voltage threshold that is
generated on-chip, which has a value of 500 mV. The recommended value for R2 is therefore in the range of 500
kΩ. From that, the value of resistor R1, depending on the desired minimum battery voltage VBAT, can be
calculated using Equation 4.
V
V
BAT
LBI*threshold
BAT
R1 + R2
* 1 + 390 kW
* 1
ǒ
Ǔ ǒ Ǔ
V
500 mV
(4)
The output of the low battery supervisor is a simple open-drain output that goes active low if the dedicated
battery voltage drops below the programmed threshold voltage on LBI. The output requires a pullup resistor with
a recommended value of 1 MΩ. The maximum voltage which is used to pull up the LBO outputs should not
exceed the output voltage of the dc/dc converter. If not used, the LBO pin can be left floating or tied to GND.
Inductor Selection
A SEPIC converter normally requires three main passive components for storing energy during the conversion.
Two inductors, a flying capacitor, and a storage capacitor at the output are required. To select the two inductors,
it is recommended to keep the possible peak inductor current below the current limit threshold of the power
switch in the chosen configuration. For example, the current limit threshold of the TPS6113x’s switch is 1600 mA
at an output voltage of 3.3 V. The highest peak current through the switch is the sum of the two inductors
currents and depends on the output load, the input (VBAT), and the output voltage (VOUT). Estimation of the
maximum average inductor current of each inductor can be done using Equation 5:
V
OUT
0.8
I
+ I
+ I
L1*A
L1*B
OUT
V
BAT
(5)
For example, for an output current of 300 mA at 3.3 V, at least 680 mA of average current flows through each of
the the inductors at a minimum input voltage of 1.8 V.
The second parameter for choosing the inductor is the desired current ripple in the inductor. Normally, it is
advisable to work with a ripple of around ±20% of the average inductor current. A smaller ripple reduces the
magnetic hysteresis losses in the inductor, as well as output voltage ripple and EMI. But in the same way,
regulation time at load changes rises. In addition, a larger inductor increases the total system costs. With those
parameters, it is possible to calculate the value for the inductor by using Equation 6:
V
V
BAT
OUT
L1 * A + L1 * B +
DI ƒ ǒVOUT BATǓ
)V
L
(6)
16
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
APPLICATION INFORMATION (continued)
Parameter f is the switching frequency and∆ IL is the ripple current in the inductor, i.e., 40% × IL. In this example,
the desired inductance value is in the range of 20 µH. With this calculated value and the calculated currents, it is
possible to choose a suitable inductor. Care has to be taken that load transients and losses in the circuit can
lead to higher currents as estimated in Equation 6. Also, the losses in the inductor caused by magnetic
hysteresis losses and copper losses are a major parameter for total circuit efficiency.
The following inductor series from different suppliers were tested. All work with the TPS6113x converter within
their specified parameters.
List of Inductors
VENDOR
RECOMMENDED INDUCTOR SERIES
COUPLED INDUCTOR SERIES
CDRH73
CDRH74
CDRH5D18
7447789___
7447779___
DR73
Sumida
Wurth Electronik
744878220
744877220
DRQ73
Cooper Electronics Technologies
EPCOS
DR74
DRQ74
B82462G
Capacitor Selection
Input Capacitor
At least a 10-µF input capacitor is recommended to improve transient behavior of the regulator and EMI behavior
of the total power supply circuit. A ceramic capacitor or a tantalum capacitor with a 100-nF ceramic capacitor in
parallel, placed close to the IC, is recommended.
Flying Capacitor DC/DC Converter
In the normal operating mode, the flying capacitor (C7) must be large enough so that the voltage across the
capacitor is small. This means the resonance frequency formed by the flying capacitor and the inductors must be
at least ten times lower than the switching frequency (see Equation 7).
100
C
+
4p2 ƒ2 L
min
(7)
Where L is the inductance of L1-A or L1-B.
To optimize efficiency, capacitors with very low ESR such as ceramic capacitors are recommended. The voltage
rating of the flying capacitor must be higher than the input voltage VBAT
.
Output Capacitor DC/DC Converter
The major parameter necessary to define the output capacitor is the maximum allowed output voltage ripple of
the converter. This ripple is determined by two parameters of the capacitor, the capacitance and the ESR. It is
possible to calculate the minimum capacitance needed for the defined ripple, supposing that the ESR is zero, by
using Equation 8:
I
V
OUT
OUT
C
+
min
ǒ
BATǓ
ƒ DV V
) V
OUT
(8)
Parameter f is the switching frequency and ∆V is the maximum allowed ripple.
With a chosen ripple voltage of 15 mV, a minimum capacitance of 26 µF is needed. The total ripple is larger due
to the ESR of the output capacitor. This additional component of the ripple can be calculated using Equation 9:
17
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
DV
I
R
ESR
OUT
ESR
(9)
An additional ripple of 24 mV is the result of using a tantalum capacitor with a low ESR of 80 mΩ. The total ripple
is the sum of the ripple caused by the capacitance and the ripple caused by the ESR of the capacitor. In this
example, the total ripple is 39 mV. Additional ripple is caused by load transients. This means that the output
capacitance needs to be larger than calculated above to meet the total ripple requirements. The output capacitor
has to completely supply the load during the charging phase of the inductor. A reasonable value of the output
capacitance depends on the speed of the load transients and the load current during the load change. With the
calculated minimum value of 26 µF and load transient considerations, a reasonable output capacitance value is
in a 100 µF range. For economical reasons this usually is a tantalum capacitor. Because of this the control loop
has been optimized for using output capacitors with an ESR of above 30 mΩ.
Small Signal Stability
When using output capacitors with lower ESR, like ceramics, it is recommended to use the adjustable voltage
version. The missing ESR can be easily compensated there in the feedback divider. Typically a capacitor in the
range of 10 pF in parallel with R3 helps to obtain small signal stability, with the lowest ESR output capacitors.
For more detailed analysis the small signal transfer function of the error amplifier and regulator, which is given in
Equation 10, can be used.
10 (R3 ) R6)
R6 (1 ) i w 1.6 ms)
d
A
+
+
REG
V
FB
(10)
Output Capacitor LDO
To ensure stable output regulation, it is required to use an output capacitor at the LDO output. We recommend
using ceramic capacitors in the range from 1 µF up to 4.7 µF. At 4.7 µF and above it is recommended to use
standard ESR tantalum. There is no maximum capacitance value.
Layout Considerations
For all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulator could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. The input capacitor, output capacitor, and the inductor should be placed as close as possible to the IC.
Use a common ground node for power ground and a different one for control ground to minimize the effects of
ground noise. Connect these ground nodes at any place close to one of the ground pins of the IC.
The feedback divider should be placed as close as possible to the control ground pin of the IC. To lay out the
control ground, it is recommended to use short traces as well, separated from the power ground traces. This
avoids ground shift problems, which can occur due to superimposition of power ground current and control
ground current.
18
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
APPLICATION EXAMPLES
C7
10 µF
U1
L1−A
L1−B
SWN
SWP
22 µH
22 µH
3.3 V,
>250 mA
VBAT
VOUT
C6
C4
R1
C3
10 µF
2.2 µF
100 µF
LBI
R2
LDOIN
1.5 V,
>120 mA
SKIPEN
EN
LDOOUT
C5
2.2 µF
LDOSENSE
R7
R9
LDOEN
List of Components:
U1 = TPS61132PW
LBO
LBO
L1 = Coiltronics DRQ74−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
PGOOD
PGND
PGOOD
GND
TPS61132PW
Figure 25. Solution for Maximum Output Power
C7
10 µF
U1
L1
L2
SWP
SWN
22 µH
22 µH
3.3 V
1.5 V
VBAT
VOUT
C6
2.2 µF
C4
100 µF
R1
C3
10 µF
LBI
R2
LDOIN
SKIPEN
EN
LDOOUT
C5
2.2 µF
LDOSENSE
LBO
R7
R9
List of Components:
U1 = TPS61132PW
L1 , L2 = Sumida 5D18–220
LDOEN
LBO
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR, Low Profile Tantalum
PGOOD
PGND
PGOOD
GND
TPS61132PW
Figure 26. Low Profile Solution, Maximum Height 1,8 mm
19
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
APPLICATION EXAMPLES (continued)
C7
10 µF
U1
L1−A
L1−B
SWN
VBAT
SWP
22 µH
22 µH
VOUT
FB
R3
C6
22 µF
R1
R2
C3
10 µF
LBI
R6
R5
LDOIN
LDOOUT
SKIPEN
EN
3.3 V
C5
LDOSENSE
2.2 µF
R7
R9
R4
LDOEN
List of Components:
U1 = TPS61130PW
LBO
LBO
L1 = Coiltronics DRQ74−220
C3, C5, C7 = X7R/X5R Ceramic
C6 = X7R/X5R Ceramic or Low
ESR Tantalum
PGOOD
PGND
PGOOD
GND
TPS61130PW
Figure 27. Single Output Using LDO as Filter
USB Input
4.2 V...5.5 V
D1
C7
10 µF
U1
L1−B
L1−A
22 µH
SWN
VBAT
SWP
22 µH
V
CC
VOUT
FB
3.3 V System Supply
R3
1 MΩ
C6
2.2 µF
R1
C4
C3
10 µF
100 µF
LBI
R6
R2
LDOIN
LDOOUT
180 kΩ
SYNC
EN
R5
LDOSENSE
1.022 MΩ
R7
R8
R4
180 kΩ
List of Components:
U1 = TPS61130PW
LDOEN
LBO
L1 = Coiltronics DRQ74−220
C3, C5, C6, C7 = X7R/X5R Ceramic
C4 = Low ESR Tantalum
Control
Outputs
PGOOD
PGND
GND
D1 = On- Semiconductor MBR0520
TPS61130PW
Figure 28. Dual Input Power Supply Solution
20
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
DETAILED DESCRIPTION
Synchronous Rectifier
The device integrates an N-channel and a P-channel MOSFET transistor to realize a synchronous rectifier.
Because the commonly used discrete Schottky rectifier is replaced with a low RDS(ON) PMOS switch, the power
conversion efficiency reaches 90%. To avoid ground shift due to the high currents in the NMOS switch, two
separate ground pins are used. The reference for all control functions is the GND pin. The source of the NMOS
switch is connected to PGND. Both grounds must be connected on the PCB at only one point close to the GND
pin. Due to the nature of the SEPIC topology, there is no dc path from the battery to the output. No additional
components must be added in a SEPIC or Flyback topology to make sure the battery is disconnected from the
output of the converter.
Nevertheless, the backgate diode of the high-side PMOS which is forward biased in standard operation, is turned
off in shutdown. This is done by a special circuit which takes the cathode of the backgate diode of the high-side
PMOS and disconnects it from the source when the regulator is not enabled (EN = low).
Controller Circuit
The controller circuit of the device is based on a fixed frequency multiple feedforward controller topology. Input
voltage, output voltage, and voltage drop on the NMOS switch are monitored and forwarded to the regulator. So
changes in the operating conditions of the converter directly affect the duty cycle and must not take the indirect
and slow way through the control loop and the error amplifier. The control loop, determined by the error amplifier,
only has to handle small signal errors. The input for it is the feedback voltage on the FB pin or, at fixed output
voltage versions, the voltage on the internal resistor divider. It is compared with the internal reference voltage to
generate an accurate and stable output voltage.
The peak current of the NMOS switch is also sensed to limit the maximum current flowing through the switch and
the inductor. The typical peak current limit is set to 1300 mA.
An internal temperature sensor prevents the device from getting overheated in case of excessive power
dissipation.
Device Enable
The device is put into operation when EN is set high. It is put into a shutdown mode when EN is set to GND. In
shutdown mode, the regulator stops switching, all internal control circuitry including the low-battery comparator is
switched off, and the backgate diode of the rectifying switch is turned off (as described in the Synchronous
Rectifier Section). This also means that the output voltage can drop below the input voltage during shutdown.
During start-up of the converter, the duty cycle and the peak current are limited in order to avoid high peak
currents drawn from the battery.
Undervoltage Lockout
An undervoltage lockout function prevents device start-up if the supply voltage on VBAT is lower than
approximately 1.6 V. When in operation and the battery is being discharged, the device automatically enters the
shutdown mode if the voltage on VBAT drops below approximately 1.6 V. This undervoltage lockout function is
implemented in order to prevent the malfunctioning of the converter.
Softstart
When the SEPIC section is enabled, the internal startup cycle starts with switching at a duty cycle of 50%. After
the output voltage has reached approximately 1.4V the device continues switching with a variable duty cycle.
Until the programmed output voltage is reached, the main switch current limit is set to 40% of its nominal value to
avoid high peak inrush currents at the battery during startup. Also the maximum output power during output short
circuit conditions is reduced. When the programmed output voltage is reached, the regulator takes control and
the switch current limit is set back to 100%.
21
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
DETAILED DESCRIPTION (continued)
LDO Enable
The LDO can be separately enabled and disabled by using the LDOEN pin in the same way as the EN pin at the
dc/dc converter stage described above. This is completely independent of the status of the EN pin. The voltage
levels of the logic signals which need to be applied at LDOEN are related to LDOIN.
Power Good
The PGOOD pin stays high impedance when the dc/dc converter delivers an output voltage within a defined
voltage window. So it can be used to enable any connected circuitry such as cascaded converters (LDO) or
microprocessor circuits.
Power Save Mode
The SKIPEN pin can be used to select different operation modes. To enable the power save mode, SKIPEN
must be set high. Power save mode is used to improve efficiency at light loads. In power save mode, the
converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output
voltage with several pulses, and goes again into power save mode once the output voltage exceeds the set
threshold voltage. The power save mode can be disabled by setting the SKIPEN to GND.
Low Battery Detector Circuit—LBI/LBO
The low-battery detector circuit is typically used to supervise the battery voltage and to generate an error flag
when the battery voltage drops below a user-set threshold voltage. The function is active only when the device is
enabled. When the device is disabled, the LBO pin is high-impedance. The switching threshold is 500 mV at LBI.
During normal operation, LBO stays at high impedance when the voltage, applied at LBI, is above the threshold.
It is active low when the voltage at LBI goes below 500 mV.
The battery voltage, at which the detection circuit switches, can be programmed with a resistive divider
connected to the LBI pin. The resistive divider scales down the battery voltage to a voltage level of 500 mV,
which is then compared to the LBI threshold voltage. The LBI pin has a built-in hysteresis of 10 mV. See the
application section for more details about the programming of the LBI threshold. If the low-battery detection
circuit is not used, the LBI pin should be connected to GND (or to VBAT) and the LBO pin can be left
unconnected. Do not let the LBI pin float.
Low-EMI Switch
The device integrates a circuit that removes the ringing that typically appears on the SW node when the
converter enters discontinuous current mode. In this case, the current through the inductor ramps to zero and the
rectifying PMOS switch is turned off to prevent a reverse current flowing from the output capacitors back to the
battery. Due to the remaining energy that is stored in parasitic components of the semiconductor and the
inductor, a ringing on the SW pin is induced. The integrated antiringing switch clamps this voltage to VBAT and
therefore dampens ringing.
LDO
The built-in LDO can be used to generate a second output voltage derived from the dc/dc converter output, from
the battery, or from another power source like an ac adapter or a USB power rail. The LDO is capable of being
back biased. This allows the user just to connect the outputs of dc/dc converter and LDO. So the device is able
to supply the load via dc/dc converter when the energy comes from the battery and efficiency is most important
and from another external power source via the LDO when lower efficiency is not critical. The LDO must be
disabled if the LDOIN voltage drops below LDOOUT to block reverse current flowing. The status of the dc/dc
stage (enabled or disabled) does not matter.
22
TPS61130
TPS61131
TPS61132
www.ti.com
SLVS431A–JUNE 2002–REVISED AUGUST 2003
THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below.
•
•
•
Improving the power dissipation capability of the PCB design.
Improving the thermal coupling of the component to the PCB.
Introducing airflow in the system.
The maximum junction temperature (TJ) of the TPS6113x devices is 150°C. The thermal resistance of the 16-pin
TSSOP package (PW) isRΘJA = 155 °C/W. The 16-pin QFN PowerPAD package (RSA) has a thermal resistance
of RΘJA = 38.1 °C/W, if the PowerPAD is soldered and the board layout is optimized. Specified regulator
operation is assured to a maximum ambient temperature TA of 85°C. Therefore, the maximum power dissipation
is about 420 mW for the TSSOP (PW) package and 1700 mW for the QFN (RSA) package. More power can be
dissipated if the maximum ambient temperature of the application is lower.(see Equation 11).
T
* T
J(MAX)
R
A
150° C * 85° C
155° CńW
P
+
+
+ 420 mW
D(MAX)
qJA
(11)
If designing for a lower junction temperature of 125°C, which is recommended, maximum heat dissipation is
lower. Using the above Equation 11 results in 1050 mW power dissipation for the RSA package and 260 mW for
the PW package.
23
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
TSSOP
TSSOP
QFN
Drawing
TPS61130PW
TPS61130PWR
TPS61130RSAR
TPS61131PW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PW
16
16
16
16
16
16
16
16
90
2000
3000
90
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-2-235C-1 YEAR
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-1-220C-UNLIM
CU NIPDAU Level-2-235C-1 YEAR
PW
RSA
PW
TSSOP
TSSOP
TSSOP
TSSOP
QFN
TPS61131PWR
TPS61132PW
PW
2000
90
PW
TPS61132PWR
TPS61132RSAR
PW
2000
1
RSA
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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