TPS71319DRCRG4 [TI]

Dual 250 mA Output, UltraLow Noise, High PSRR, Low-Dropout Linear Regulator with Integrated SVS; 双路250mA输出,超低噪声,高PSRR ,低压差线性调节器,集成SVS
TPS71319DRCRG4
型号: TPS71319DRCRG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

Dual 250 mA Output, UltraLow Noise, High PSRR, Low-Dropout Linear Regulator with Integrated SVS
双路250mA输出,超低噪声,高PSRR ,低压差线性调节器,集成SVS

线性稳压器IC 调节器 电源电路 光电二极管 输出元件
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TPS71319  
TPS71334  
A ct ual S i ze  
(3 m m x 3 m m )  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
Dual 250 mA Output, UltraLow Noise, High PSRR,  
Low-Dropout Linear Regulator with Integrated SVS  
FEATURES  
DESCRIPTION  
Dual 250 mA High-Performance RF LDOs  
The TPS713xx family of low-dropout (LDO) voltage  
regulators is tailored to noise-sensitive and RF appli-  
cations. These products feature dual 250 mA LDOs  
with ultralow noise, high power-supply rejection ratio  
(PSRR), and fast transient and start-up response.  
These devices also feature an integrated supply  
voltage supervisor (SVS) that monitors the voltage at  
OUT2 and will assert if the voltage falls to 95%  
(typical) of the measured output. Each regulator  
output is stable with low-cost 2.2 µF ceramic output  
capacitors and features very low dropout voltages  
(125 mV typical at 250 mA). Each regulator achieves  
fast start-up times (approximately 60 µs with a  
0.001 µF bypass capacitor) while consuming very low  
quiescent current (300 µA typical with both outputs  
enabled). When the device is placed in standby  
mode, the supply current is reduced to less than  
0.3 µA typical. Each regulator exhibits approximately  
32 µVrms of output voltage noise with VOUT = 2.8 V  
and a 0.01 µF noise reduction (NR) capacitor. Appli-  
Integrated Supply Voltage Supervisor  
Monitors VOUT2  
Available in Fixed and Adjustable  
Voltage Options (1.2 V to 5.5 V)  
High PSRR: 65 dB at 10 kHz  
UltraLow Noise: 32 µVrms  
Fast Start-Up Time: 60 µs  
Stable with 2.2 µF Ceramic Capacitor  
Excellent Load/Line Transient Response  
Very Low Dropout Voltage: 125 mV at 250 mA  
Independent Enable Pins  
Thermal Shutdown and Independent Current  
Limit  
Available in Thermally-Enhanced SON  
Package: 3mm x 3mm x 1mm  
cations with analog components  
that  
are  
APPLICATIONS  
noise-sensitive, such as portable RF electronics, will  
benefit from high PSRR, low noise, and fast line and  
load transient features. The TPS713xx family is  
offered in a thin 3mm x 3mm SON package and is  
fully specified from -40°C to +125°C (TJ).  
Cellular and Cordless Phones  
Wireless PDA/Handheld Products  
PCMCIA/Wireless LAN Applications  
Digital Camera/Camcorder/Internet Audio  
DSP/FPGA/ASIC/Controllers and Processors  
PSRR (RIPPLE REJECTION) vs FREQUENCY  
80  
70  
60  
50  
40  
30  
20  
10  
0
IOUT = 250 mA  
DRC PACKAGE  
3mm x 3mm SON  
(TOP VIEW)  
IN  
RESET  
OUT1  
OUT2  
GND  
1
2
3
4
5
10 EN1  
9
8
7
6
NC  
IOUT = 1 mA  
EN2  
FB2/NC  
NR  
VOUT = 2.8 V (adj)  
µ
COUT = 2.2  
CNR = 0.01  
F
µ
F
10  
100  
1k  
10k  
100k  
1M  
10M  
Frequency (Hz)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2005, Texas Instruments Incorporated  
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated  
circuits be handled with appropriate precautions. Failure to observe proper handling and installation  
procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision  
integrated circuits may be more susceptible to damage because very small parametric changes could  
cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
VOLTAGE (TJ)  
PACKAGE-  
LEAD  
(DESIGNATOR)  
SPECIFIED  
TEMPERATURE  
RANGE (TJ)  
PACKAGE  
MARKING  
ORDERING  
NUMBER  
TRANSPORT  
MEDIA, QUANTITY  
PRODUCT  
VOUT1  
VOUT2  
TPS71319DRCT  
TPS71319DRCR  
TPS71334DRCT  
TPS71334DRCR  
Tape and Reel, 250  
Tape and Reel, 3000  
Tape and Reel, 250  
Tape and Reel, 3000  
TPS71319  
1.8 V  
3.3 V  
Adjustable  
SON-10 (DRC)  
SON-10 (DRC)  
-40°C to +125°C  
-40°C to +125°C  
ARP  
ARO  
TPS71334  
Adjustable  
(1) For the most current package and ordering information, see the Package Ordering Addendum located at the end of this data sheet.  
ABSOLUTE MAXIMUM RATINGS  
over operating junction temperature range unless otherwise noted(1)  
TPS713xx  
-0.3 to 6.0  
UNIT  
VIN range  
V
V
V
V
VRESET range  
-0.3 to VIN + 0.3  
-0.3 to VIN + 0.3  
-0.3 to 6.0  
VEN1, VEN2 range  
VOUT range  
Peak output current  
Output short-circuit duration  
Continuous total power dissipation  
Junction temperature range, TJ  
Storage temperature range  
ESD rating, HBM  
Internally limited  
Indefinite  
See Dissipation Ratings Table  
-40 to +150  
-65 to +150  
2
°C  
°C  
kV  
V
ESD rating, CDM  
500  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics  
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.  
POWER DISSIPATION RATINGS  
DERATING FACTOR  
ABOVE TA = 25°C  
T
A 25°C  
TA = 70°C  
TA = 85°C  
BOARD  
PACKAGE  
RθJC  
RθJA  
POWER RATING POWER RATING POWER RATING  
High-K(1)  
DRC  
48  
52  
19 mW/°C  
1.92 W 1.06 W 0.77 W  
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and  
ground planes and 2-ounce copper traces on the top and bottom of the board.  
2
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
ELECTRICAL CHARACTERISTICS  
Over operating temperature range (TJ = -40°C to +125°C), VIN = highest VOUT(nom) + 1.0 V or 2.7 V (whichever is greater),  
IOUT = 1 mA, VEN1, 2 = 1.2 V, COUT = 10 µF, CNR = 0.01 µF, and adjustable LDOs are tested at VOUT = 3.0 V, unless otherwise  
noted. Typical values are at TJ = 25°C.  
PARAMETER  
Input voltage range(1)  
TEST CONDITIONS  
MIN  
2.7  
TYP  
MAX UNIT  
VIN  
5.5  
V
V
VFB  
Internal reference (adjustable LDOs)  
1.200  
1.225 1.250  
5.5 - VDO  
+1.5  
Output voltage range  
(adjustable LDOs)  
VFB  
-1.5  
-3  
V
VOUT  
Nominal  
TJ = 25°C, IOUT = 0 mA  
VOUT + 1.0 V VIN 5.5 V,  
IOUT, and T 0 µA IOUT 250 mA  
VOUT + 1.0 V VIN 5.5 V  
0 µA IOUT 250 mA  
2.8 V,  
Accuracy(1)  
%
Over VIN  
,
±1  
+3  
VOUT%/VIN  
Line regulation(1)  
0.05  
0.8  
%/V  
VOUT%/IOUT Load regulation  
%/mA  
Dropout voltage(2)  
VDO  
2.85 V  
Adjustable  
IOUT1 = IOUT2 = 250 mA  
125  
230  
mV  
mA  
(VIN = VOUT(nom) - 0.1V)  
ICL  
Output current limit  
Ground pin current  
VOUT = 0.9 × VOUT(nom)  
400  
600  
190  
800  
250  
One LDO  
enabled  
IOUT = 1 mA (enabled channel)  
IGND  
µA  
Both LDOs  
enabled  
IOUT1 = IOUT2 = 1 mA to 250 mA  
300  
600  
V
EN 0.4 V, 0 V VIN 5.5 V,  
ISHDN  
IFB  
Shutdown current(3)  
0.3  
0.1  
2.0  
1
µA  
µA  
RESET open  
FB pin current (adjustable LDOs)  
No CNR, IOUT = 250 mA  
80.0 × VOUT  
Output noise voltage,  
BW = 10 Hz - 100 kHz  
Vn  
µVrms  
dB  
CNR = 0.01 µF, IOUT = 250 mA  
f = 100 Hz, IOUT = 250 mA  
11.8 × VOUT  
65  
65  
60  
Power-supply rejection ratio  
(ripple rejection)  
PSRR  
f = 10 kHz, IOUT = 250 mA  
tSTR  
VIH  
VIL  
Startup time  
VOUT = 2.85 V, RL = 30, CNR = 0.001 µF  
µs  
V
Enable threshold high (EN1, EN2)  
Enable threshold low (EN1, EN2)  
Enable pin current (EN1, EN2)  
Minimum VIN for valid RESET  
RESET output low voltage  
RESET leakage current  
1.2  
VIN  
0.4  
1
0
V
IEN  
VIN = VEN = 5.5 V  
IRESET = 10 µA  
IRESET = 1 mA  
-1  
µA  
V
0.6  
10  
VRESET, LO  
ILKG, RESET  
VIT  
0.4  
V
VIN = VRESET = 5.5 V  
VOUT2 falling(4)  
VOUT2 rising(4)  
500  
nA  
RESET threshold voltage  
RESET threshold hysteresis  
RESET delay time  
92.5  
50  
97.5 %VOUT  
%VOUT  
VHYS  
0.5  
100  
TD  
200  
ms  
µs  
TP  
RESET propagation delay  
10  
Shutdown  
Reset  
Temp increasing  
Temp decreasing  
+160  
+140  
TSD  
Thermal shutdown temperature  
°C  
Under-voltage lockout threshold  
Under-voltage lockout hysteresis  
VIN rising  
VIN falling  
2.25  
2.65  
V
UVLO  
100  
mV  
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.  
(2) VDO is not measured for 1.8 V regulators since minimum VIN = 2.7 V.  
(3) For the adjustable version, this applies only after VIN is applied; then VEN transitions from high to low.  
(4) RESET threshold and hysteresis is a percentage of the measured output.  
3
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
FUNCTIONAL BLOCK DIAGRAM  
IN  
OUT1  
Current  
Limit  
µ
30  
A
EN1  
Thermal  
Shutdown  
OUT2  
Current  
Limit  
90 k  
UVLO  
FB2  
Delay  
(VFB2 Rising)  
EN2  
RESET  
100 ms  
×
0.95 VREF  
250 k  
NR  
VREF  
1.225 V  
5 pF  
TPS713xx  
Fixed/Fixed  
Quickstart  
Table 1. TERMINAL FUNCTIONS  
TERMINAL  
DESCRIPTION  
NAME  
DRC  
1
IN  
Unregulated input supply. A 0.1 µF capacitor should be connected from IN to GND.  
Ground  
GND  
5, Pad  
Output of the regulator. A small 2.2 µF ceramic capacitor is required from this pin to ground to assure  
stability.  
OUT1  
OUT2  
EN1  
3
4
Same as OUT1 but for LDO2.  
Driving the enable pin (EN) high turns on LDO1. Driving this pin low puts LDO1 into shutdown mode,  
reducing operating current. The enable pin should be connected to IN if not used.  
10  
EN2  
NC  
8
9
7
6
Same as EN1 but controls LDO2.  
No connection.  
FB2/NC  
NR  
Feedback for CH2 adjustable version; no connection for non-adjustable CH2.  
Noise reduction pin; connect an external bypass capacitor to reduce LDO output noise.  
Open-drain reset output; monitors OUT2. A 10 kto 1 Mpull-up resistor is suitable for most  
applications. The open-drain RESET pull-up voltage should not exceed VDD + 0.3 V.  
RESET  
2
4
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS  
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 µF, and CNR = 0.01 µF,  
unless otherwise noted.  
OUTPUT VOLTAGE vs INPUT VOLTAGE  
OUTPUT VOLTAGE vs OUTPUT CURRENT  
1.0  
0.8  
0.6  
0.4  
0.2  
0
1.0  
0.8  
0.6  
0.4  
0.2  
0
_
_
+25 C  
+25  
C
_
40  
C
0.2  
0.4  
0.6  
0.8  
1.0  
0.2  
0.4  
0.6  
0.8  
1.0  
_
+125  
C
_
40  
C
_
+125  
C
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
0
50  
100  
150  
200  
250  
VIN (V)  
IOUT (mA)  
Figure 1.  
Figure 2.  
DROPOUT VOLTAGE vs INPUT VOLTAGE  
(ADJUSTABLE OUTPUTS)  
OUTPUT VOLTAGE vs TEMPERATURE  
200  
180  
160  
140  
120  
100  
80  
1.0  
0.5  
0
_
TJ = +125  
C
IOUT = 10 mA  
_
TJ = +25 C  
IOUT = 125 mA  
0.5  
1.0  
1.5  
60  
IOUT = 250 mA  
_
TJ  
=
40 C  
40  
20  
0
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9  
VIN (V)  
40 25 10  
5
20 35 50 65 80 95 110 125  
_
Junction Temperature ( C)  
Figure 3.  
Figure 4.  
DROPOUT VOLTAGE vs OUTPUT CURRENT  
DROPOUT VOLTAGE vs JUNCTION TEMPERATURE  
200  
150  
100  
50  
250  
Adjustable Set to 2.8 V  
Adjustable Set to 2.8 V  
_
TJ = +125  
C
200  
150  
100  
50  
IOUT = 250 mA  
_
40  
TJ  
=
C
_
TJ = +25 C  
0
0
0
50  
100  
150  
200  
250  
40 25 10  
5
20 35 50 65 80 95 110 125  
IOUT (mA)  
Junction Temperature (mA)  
Figure 5.  
Figure 6.  
5
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS (continued)  
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 µF, and CNR = 0.01 µF,  
unless otherwise noted.  
GROUND CURRENT vs INPUT VOLTAGE  
GROUND PIN CURRENT vs IOUT  
400  
375  
350  
325  
300  
275  
250  
225  
200  
400  
375  
350  
325  
300  
275  
250  
225  
200  
_
+125  
C
_
+125  
C
_
+25  
C
_
40  
C
_
+25  
C
_
40 C  
2.7  
3.2  
3.7  
4.2  
IN (V)  
4.7  
5.2  
5.7  
0
50  
100  
150  
200  
250  
V
IOUT (mA)  
Figure 7.  
Figure 8.  
GROUND PIN CURRENT vs JUNCTION TEMPERATURE  
(DISABLED)  
GROUND PIN CURRENT vs JUNCTION TEMPERATURE  
400  
500  
VEN1 = VEN2 = 1.2 V  
VIN = 3.8 V  
VEN1 = VEN2 = 0.4V  
VIN = 3.8 V  
450  
400  
350  
300  
250  
200  
150  
100  
50  
375  
350  
325  
300  
275  
250  
225  
200  
0
40 25 10  
5
20 35 50 65 80 95 110 125  
40 25 10  
5
20 35 50 65 80 95 110 125  
_
_
Junction Temperature ( C)  
Junction Temperature ( C)  
Figure 9.  
Figure 10.  
TPS71334  
LINE TRANSIENT RESPONSE  
CURRENT LIMIT vs JUNCTION TEMPERATURE  
800  
750  
700  
650  
600  
550  
500  
450  
400  
µ
COUT1 = COUT2 = 10  
F
VOUT2 Set to 1.225 V  
4.3 V  
VIN  
3.8 V  
IOUT = 250 mA  
IOUT = 1 mA  
VOUT1  
10 mV/div  
10 mV/div  
VOUT2  
µ
100 s/div  
40 25 10  
5
20 35 50 65 80 95 110 125  
_
Junction Temperature ( C)  
Figure 11.  
Figure 12.  
6
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS (continued)  
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 µF, and CNR = 0.01 µF,  
unless otherwise noted.  
TPS71334  
LOAD TRANSIENT RESPONSE  
AND VOUT2 CROSSTALK  
TPS71334  
CHANNEL-TO-CHANNEL ISOLATION vs FREQUENCY  
60  
µ
COUT2 = 10  
F
2 mV/div  
VOUT2  
50  
40  
30  
20  
10  
0
µ
COUT1 = 10  
F
100 mV/div  
VOUT1  
250 mA  
VOUT2 Set to 2.225 V  
µ
COUT1 = COUT2 = 10  
F
10 mA  
IOUT1 = 0 mA to 500 mA Sinusoidal Load  
IOUT2 = 25 mA  
Adjustable Set to 3.3 V  
200 mA/div  
IOUT1  
µ
20 s/div  
0.1  
1
10  
100  
1k  
Frequency (Hz)  
Figure 13.  
TPS71334  
TURN-ON/OFF RESPONSE  
AND VOUT2 CROSSTALK  
Figure 14.  
TPS71334  
POWER-UP/POWER-DOWN  
IOUT1 = IOUT2 = 250 mA  
IOUT1 = IOUT2 = 250 mA  
µ
COUT1 = COUT 2 = 10  
F
VOUT2 Set to 1.225 V  
20 mV/div  
VOUT2  
VOUT2  
µ
CNR = 0.001  
F
VOUT2  
VIN  
VOUT1  
VEN1  
1 V/div  
VRESET  
µ
50 s/div  
50 ms/div  
Figure 15.  
Figure 16.  
NOISE SPECTRAL DENSITY  
COUT = 2.2 µF  
TOTAL NOISE vs CNR  
250  
200  
150  
100  
50  
350  
300  
250  
200  
150  
100  
50  
µ
COUT = 2.2  
F
µ
F
VOUT = 2.8 V (adj)  
CNR = 0.1  
IOUT = 250 mA  
VOUT = 2.8 V (adj)  
IOUT = 250 mA  
µ
COUT = 2.2  
F
IOUT = 0 mA  
µ
COUT = 10  
F
IOUT = 250 mA  
IOUT = 1 mA  
µ
COUT = 10  
F
IOUT = 0 mA  
0
0
1
10  
100  
1k  
10k  
100k  
100  
1k  
10k  
100k  
CNR (pF)  
Frequency (Hz)  
Figure 17.  
Figure 18.  
7
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
TYPICAL CHARACTERISTICS (continued)  
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 1 V, IOUT = 1 mA,VEN = 1.2 V, COUT = 2.2 µF, and CNR = 0.01 µF,  
unless otherwise noted.  
NOISE SPECTRAL DENSITY  
COUT = 10 µF  
NOISE SPECTRAL DENSITY vs CNR  
350  
300  
250  
200  
150  
100  
50  
180  
160  
140  
120  
100  
80  
µ
CNR = 0.01  
F
µ
COUT = 10  
F
VOUT = 2.8 V (adj)  
IOUT = 250 mA  
VOUT = 2.8 V (adj)  
µ
0.001  
F
µ
0.047  
F
IOUT = 1 mA  
µ
0.01  
F
IOUT = 250 mA  
60  
40  
µ
0.1  
F
20  
0
100  
0
1k  
10k  
100k  
100  
1k  
10k  
100k  
Frequency (Hz)  
Frequency (Hz)  
Figure 19.  
Figure 20.  
PSRR (RIPPLE REJECTION) vs FREQUENCY  
PSRR (RIPPLE REJECTION) vs FREQUENCY  
80  
70  
60  
50  
40  
30  
20  
10  
0
80  
70  
60  
50  
40  
30  
20  
10  
0
IOUT = 1 mA  
IOUT = 250 mA  
IOUT = 1 mA  
IOUT = 250 mA  
VOUT = 2.8 V (adj)  
VOUT = 2.8 V (adj)  
µ
COUT = 10 F  
µ
COUT = 2.2  
CNR = 0.01  
F
µ
F
µ
F
CNR = 0.01  
10  
100  
1k  
10k  
100k  
1M  
10M  
10  
100  
1k  
10k  
100k  
1M  
10M  
Frequency (Hz)  
Frequency (Hz)  
Figure 21.  
Figure 22.  
PSRR (RIPPLE REJECTION) vs VIN - VOUT  
80  
70  
60  
50  
40  
30  
20  
10  
0
f = 1 kHz  
f = 10 kHz  
f = 100 kHz  
VOUT = 2.8 V (adj)  
IOUT = 250 mA  
µ
µ
COUT = 10  
CNR = 0.01  
F
F
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0  
VIN VOUT (V)  
Figure 23.  
8
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
APPLICATION INFORMATION  
1.8 V or less is chosen, the minimum recommended  
output capacitor is 4.7 µF. Any ceramic capacitor that  
meets the minimum output capacitor requirements is  
suitable. Capacitors with higher ESR may be used,  
provided the worst-case ESR is less than 1.  
The TPS713xx family of dual low-dropout (LDO)  
regulators has been optimized for use in  
noise-sensitive battery-operated equipment. The de-  
vice features extremely low dropout, high PSRR,  
ultralow output noise, and low quiescent current  
(190 µA typically per channel). When both outputs  
are disabled, the supply currents are reduced to less  
than 2µA. A typical application circuit with sequencing  
is shown in Figure 24.  
OUTPUT NOISE  
The internal voltage reference is a key source of  
noise in an LDO regulator. The TPS713xx has an NR  
pin that is connected to the voltage reference through  
a 250 kinternal resistor. The 250 kinternal  
resistor, in conjunction with an external ceramic  
bypass capacitor connected to the NR pin, creates a  
low-pass filter to reduce the voltage reference noise  
and, therefore, the noise at the regulator output. To  
achieve a fast startup, the 250 kinternal resistor is  
shorted for 400 µs after the device is enabled.  
TPS71334  
VIN  
VOUT1  
IN  
OUT1  
µ
2.2  
2.2  
F
100 k  
EN2  
EN1  
RESET  
OUT2  
µ
0.1  
F
VOUT2  
R1  
R2  
C1  
µ
F
NR  
FB2  
GND  
Because the primary noise source is the internal  
voltage reference, the output noise will be greater for  
higher output voltage versions. For the case where  
no noise reduction capacitor is used, the typical noise  
(µVrms) over 10 Hz to 100 kHz is 30 times the output  
voltage. If a 0.01 µF capacitor is used from the NR  
pin to ground, the noise (µVrms) drops to 11.8 times  
the output voltage. For example, the TPS71334 with  
the adjustable output set to 2.8 V exhibits only  
33 µVrms of output voltage noise using a 0.01 µF  
ceramic bypass capacitor and a 2.2 µF ceramic  
output capacitor.  
µ
0.01  
F
64.9 k  
Figure 24. Typical Application Circuit  
(with output sequencing)  
INPUT AND OUTPUT CAPACITOR  
REQUIREMENTS  
A 0.1 µF or larger ceramic input bypass capacitor,  
connected between IN and GND and located close to  
the TPS713xx, is required for stability. It improves  
transient response, noise rejection, and ripple rejec-  
tion. A higher-value input capacitor may be necessary  
if large, fast-rise-time load transients are anticipated  
and the device is located several inches from the  
power source.  
STARTUP CHARACTERISTICS  
To minimize startup overshoot, the TPS713xx will  
initially target an output voltage that is approximately  
80% of the final value. To avoid a delayed startup  
time, noise reduction capacitors of 0.01 µF or less  
are recommended. Larger noise reduction capacitors  
will cause the output to hold at 80% until the voltage  
on the noise reduction capacitor exceeds 80% of the  
bandgap voltage. The typical startup time with a  
0.001 µF noise reduction capacitor is 60 µs. Once  
one of the output voltages is present, the startup time  
of the other output will not be affected by the noise  
reduction capacitor.  
The TPS713xx requires an output capacitor connec-  
ted between the outputs and GND to stabilize the  
internal control loops. The minimum recommended  
output capacitor is 2.2 µF. If an output voltage of  
9
 
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
5
(
)
(
)
3   10   R1 ) R2  
PROGRAMMING THE TPS71202  
ADJUSTABLE LDO REGULATOR  
(
)
pF  
C1 +  
(
)
R1   R2  
(3)  
The output voltage of the TPS71202 dual adjustable  
regulator is programmed using an external resistor  
divider, as shown in Figure 24. The output voltage is  
calculated using Equation 1:  
The suggested value of this capacitor for several  
resistor ratios is shown in Figure 25. If this capacitor  
is not used (such as in a unity-gain configuration) or if  
an output voltage 1.8 V is chosen, then the  
minimum recommended output capacitor is 4.7 µF  
instead of 2.2 µF.  
R1  
R2  
  ǒ1 ) Ǔ  
VOUT + VREF  
(1)  
where VREF = 1.225 V (the internal reference volt-  
age).  
DROPOUT VOLTAGE  
The TPS713xx uses a PMOS pass transistor to  
achieve extremely low dropout. When (VIN - VOUT) is  
less than the dropout voltage (VDO), the PMOS pass  
device is in its linear region of operation and the  
input-to-output resistance is the RDS, ON of the PMOS  
pass element. Dropout voltages at lower currents can  
Resistors R2 and R4 should be chosen for approxi-  
mately a 40 µA divider current. Lower value resistors  
can be used for improved noise performance, but will  
consume more power. Higher values should be  
avoided because leakage current at FB increases the  
output voltage error. The recommended design pro-  
cedure is to choose R2 = 30.1 kto set the divider  
current at 40 µA, and then calculate R1 using  
Equation 2:  
be approximated by calculating the effective RDS,  
ON  
of the pass element and multiplying that resistance by  
the load current. RDS, ON of the pass element can be  
obtained by dividing the dropout voltage by the rated  
output current. For the TPS71334, the RDS, ON of the  
pass element is 84 m. The dropout voltage of the  
TPS713xx will be less for higher output voltage  
versions. This is because the PMOS pass element  
will have lower on-resistance due to increased gate  
drive.  
VOUT  
R1 + ǒ Ǔ  
* 1   R2  
VREF  
(2)  
To improve the stability and noise performance of the  
adjustable version, a small compensation capacitor  
can be placed between OUT and FB.  
For voltages 1.8 V, the value of this capacitor  
should be 100 pF. For voltages > 1.8 V, the approxi-  
mate value of this capacitor can be calculated as  
Equation 3:  
TPS71334  
Output Voltage Programming Guide  
VIN  
VOUT1  
IN  
OUT1  
µ
2.2  
2.2  
F
V
R1  
R2  
C1  
OUT2  
1.225 V  
1.5 V  
Short  
Open  
Open  
100 pF  
22 pF  
15 pF  
15 pF  
15 pF  
EN2  
EN1  
RESET  
OUT2  
µ
0.1  
F
7.15 k  
31.6 kΩ  
43.2 kΩ  
49.9 kΩ  
86.6 kΩ  
30.1 kΩ  
30.1 kΩ  
30.1 kΩ  
30.1 kΩ  
30.1 kΩ  
VOUT2  
2.5 V  
R1  
R2  
C1  
µ
F
NR  
FB2  
3.0 V  
GND  
3.3 V  
µ
0.01  
F
4.75 V  
Figure 25. TPS71334 Adjustable LDO Regulator Programming  
10  
 
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
output will remain unasserted during transients  
shorter than the reset circuit propagation delay (TP).  
Even with a 2.2 µF output capacitor, typical load  
transient conditions will not cause RESET to falsely  
assert.  
SUPERVISOR DESCRIPTION  
The TPS713xx has an on-chip supply voltage super-  
visor (SVS) that monitors the voltage at OUT2. The  
RESET output will assert if VOUT2 is below the reset  
threshold (VIT). When OUT2 exceeds the reset  
threshold plus hysteresis (VHYS), the RESET output  
will remain low for the specified delay time (tD). When  
OUT2 is disabled by EN2 or the input voltage is  
below the under-voltage lockout (UVLO), the reset  
signal is automatically asserted. The functionality of  
the reset circuit is shown in Figure 26 and Table 2.  
The RESET pin requires an external resistor to pull  
the pin high during the unasserted state. A 10 kto 1  
Mresistor is suitable for most applications. If the  
resistance is too low, the pin may not pull low enough  
to be recognized as a valid logic signal. If the pull-up  
resistor is too large, the reset pin leakage may cause  
the device not to pull high enough in the unasserted  
state. The pull-up voltage for the RESET pin should  
not exceed VIN + 0.3 V; doing so will turn on internal  
ESD protection devices and may damage the device.  
The output accuracy or output divider resistor toler-  
ances have minimal effect on the relative VIT  
threshold accuracy. The reset threshold VIT will scale  
accordingly to the actual output voltage. The RESET  
VIN  
0.6 V  
0.0 V  
VOUT1  
VIT + VHYS  
VIT  
VOUT2  
tD = Reset Delay  
= Undefined State  
EN1  
EN2  
tD  
tD  
RESET  
Figure 26. RESET Timing Diagram  
Table 2. Reset Pin Truth Table  
UVLO  
RESET  
EN2  
Asserted  
VOUT2  
Asserted  
X(1)  
Low  
High  
High  
Yes  
X
X
Yes  
Yes  
No  
X
No  
No  
VOUT2 > VIT  
VOUT2 < VIT  
Yes  
(1) X = don't care.  
11  
 
TPS71319  
TPS71334  
www.ti.com  
SBVS055ADECEMBER 2004REVISED JANUARY 2005  
TRANSIENT RESPONSE  
Depending on power dissipation, thermal resistance,  
and ambient temperature, the thermal protection  
circuit may cycle on and off. This limits the dissipation  
of the regulator, protecting it from damage due to  
overheating.  
As with any regulator, increasing the size of the  
output capacitor will reduce over/undershoot magni-  
tude but increase duration of the transient response.  
In the adjustable version, the addition of a capacitor,  
CFB, from the output to the feedback pin will also  
improve stability and transient response. The transi-  
ent response of the TPS713xx is enhanced with an  
active pull-down that engages when the output is  
over-voltaged. The active pull-down decreases the  
output recovery time when the load is removed.  
Figure 14 in the Typical Characteristics section shows  
the output transient response.  
Any tendency to activate the thermal protection circuit  
indicates excessive power dissipation or an inad-  
equate heatsink. For reliable operation, junction tem-  
perature should be limited to +125°C maximum. To  
estimate the margin of safety in a complete design  
(including heatsink), increase the ambient tempera-  
ture until the thermal protection is triggered; use  
worst-case loads and signal conditions. For good  
reliability, thermal protection should trigger at least  
+35°C above the maximum expected ambient con-  
dition of your application. This produces a worst-case  
junction temperature of +125°C at the highest ex-  
pected ambient temperature and worst-case load.  
SHUTDOWN  
Both enable pins are active high and are compatible  
with standard TTL-CMOS levels. The device is only  
completely disabled when both EN1 and EN2 are  
logic low. In this state, the LDO is completely off and  
the ground pin current drops to approximately  
100 nA. With one output disabled, the ground pin  
current is slightly greater than half the nominal value.  
When shutdown capability is not required, the enable  
pins should be connected to the input supply.  
The internal protection circuitry of the TPS713xx was  
designed to protect against overload conditions. It  
was not intended to replace proper heatsinking.  
Continuously running the TPS713xx into thermal  
shutdown will degrade device reliability.  
POWER DISSIPATION  
INTERNAL CURRENT LIMIT  
The ability to remove heat from the die is different for  
each package type, presenting different consider-  
ations in the PCB layout. The PCB area around the  
device that is free of other components moves the  
heat from the device to the ambient air. Performance  
data for a JEDEC high-K board is shown in the  
Dissipation Ratings table. Using heavier copper will  
increase the effectiveness in removing heat from the  
device. The addition of plated through-holes to  
heat-dissipating layers will also improve the heat-sink  
effectiveness.  
The TPS713xx internal current limit helps protect the  
regulator during fault conditions. During current limit,  
the output will source a fixed amount of current that is  
largely independent of the output voltage.  
The TPS713xx PMOS-pass transistors have a built-in  
back diode that conducts reverse current when the  
input voltage drops below the output voltage (that is,  
during power-down). Current is conducted from the  
output to the input and is not internally limited. If  
extended reverse voltage operation is anticipated,  
external limiting may be appropriate.  
Power dissipation depends on input voltage and load  
conditions. Power dissipation is equal to the product  
of the output current times the voltage drop across  
the output pass element (VIN to VOUT):  
THERMAL PROTECTION  
Thermal protection disables both outputs when the  
junction temperature of either channel rises to ap-  
proximately +160°C, allowing the device to cool.  
When the junction temperature cools to approxi-  
mately +140°C, the output circuitry is again enabled.  
PD  
(VIN VOUT  
)
IOUT  
(4)  
Power dissipation can be minimized by using the  
lowest possible input voltage necessary to assure the  
required output voltage.  
12  
PACKAGE OPTION ADDENDUM  
www.ti.com  
16-May-2005  
PACKAGING INFORMATION  
Orderable Device  
TPS71319DRCR  
TPS71319DRCRG4  
TPS71319DRCT  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SON  
DRC  
10  
10  
10  
10  
10  
10  
10  
10  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
SON  
SON  
SON  
SON  
SON  
SON  
SON  
DRC  
DRC  
DRC  
DRC  
DRC  
DRC  
DRC  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
TPS71319DRCTG4  
TPS71334DRCR  
TPS71334DRCRG4  
TPS71334DRCT  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
TPS71334DRCTG4  
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
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to Customer on an annual basis.  
Addendum-Page 1  
IMPORTANT NOTICE  
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