TPS715A-NM [TI]
24V、80mA、低 Iq、低压降线性稳压器;
| 型号： | TPS715A-NM |
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TEXAS INSTRUMENTS |
| 描述： | 24V、80mA、低 Iq、低压降线性稳压器 稳压器 |
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TPS715A-NM
SBVS340 –JUNE 2017
TPS715A-NM
24-V High Input Voltage, Micropower, 80-mA LDO Voltage Regulator
1 Features
3 Description
The TPS715A-NM low-dropout (LDO) voltage
regulators offer the benefits of high input voltage, low-
1
•
24-V Maximum Input Voltage
•
•
•
•
Low 3.2-μA Quiescent Current at 80 mA
Stable With Any Capacitor (≥ 0.47 μF)
80-mA Specified Current
dropout
voltage,
low-power
operation,
and
miniaturized packaging. The devices operate over an
input range of 2.5 V to 24 V and are stable with any
capacitor (≥ 0.47 μF). The high maximum input
voltage combined with excellent power dissipation
capability makes this device particularly well-suited to
industrial and automotive applications.
Available in Fixed and Adjustable (1.2 V to 15 V)
Versions
•
•
•
Specified Current Limit
3-mm × 3-mm and 2-mm × 2-mm SON Packages
A PMOS pass element functions as a low-value
resistor. The low dropout voltage, typically 670 mV at
80 mA of load current, is directly proportional to the
load current. The low quiescent current (3.2 μA
typically) is nearly constant over the entire range of
output load current (0 mA to 80 mA).
–40°C to 125°C Specified Junction
Temperature Range
•
For MSP430-Specific Output Voltages See
TPS715xx
2 Applications
The TPS715A-NM is available in a 3-mm × 3-mm
package ideal for high power dissipation and a small
2-mm × 2-mm package ideal for handheld and ultra-
portable applications. The 3-mm × 3-mm package is
also available as a non-magnetic package for medical
imaging applications.
•
•
•
•
•
Ultralow Power Microcontrollers
Industrial and Automotive Applications
Video Surveillance and Security Systems
Portable, Battery-Powered Equipment
Medical Imaging
Device Information(1)
PART NUMBER
PACKAGE
SON (8), DRB
SON (6), DRV
BODY SIZE (NOM)
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
TPS715A-NM
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
TPS715A33
OUT
IN
MSP430
GND
Li+
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS715A-NM
SBVS340 –JUNE 2017
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Table of Contents
7.1 Application Information............................................ 10
7.2 Typical Applications ................................................ 10
7.3 Do's and Don'ts....................................................... 12
Power Supply Recommendations...................... 12
Layout ................................................................... 13
9.1 Layout Guidelines ................................................... 13
9.2 Layout Example ...................................................... 13
9.3 Power Dissipation ................................................... 13
1
2
3
4
5
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
5.1 Absolute Maximum Ratings ...................................... 3
5.2 ESD Ratings.............................................................. 3
5.3 Recommended Operating Conditions....................... 3
5.4 Thermal Information.................................................. 4
5.5 Electrical Characteristics........................................... 4
5.6 Typical Characteristics.............................................. 5
Detailed Description .............................................. 8
6.1 Overview ................................................................... 8
6.2 Functional Block Diagrams ....................................... 8
6.3 Feature Description................................................... 9
6.4 Device Functional Modes.......................................... 9
Application and Implementation ........................ 10
8
9
10 Device and Documentation Support ................. 14
10.1 Device Support...................................................... 14
10.2 Documentation Support ....................................... 14
10.3 Community Resources.......................................... 14
10.4 Trademarks........................................................... 14
10.5 Electrostatic Discharge Caution............................ 15
10.6 Glossary................................................................ 15
6
7
11 Mechanical, Packaging, and Orderable
Information ........................................................... 15
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4 Pin Configuration and Functions
DRV Package
6-Pin SON
Top View
DRB Package
8-Pin SON
Top View
1
2
3
4
8
7
6
5
IN
NC
OUT
NC
1
2
3
6
5
4
IN
NC
OUT
NC
NC
NC
GND
FB/NC
GND
FB/NC
Pin Functions
PIN
8-PIN SON
6-PIN SON
I/O
DESCRIPTION
NAME
FIXED
—
ADJ.
FIXED
—
ADJ.
FB
5
4, Pad
1
4
3, Pad
1
I
—
I
Adjustable version. This pin is used to set the output voltage.
GND
IN
4, Pad
1
3, Pad
1
Ground
Unregulated input voltage
2, 3, 5,
6, 7
No connection. Can be left open or tied to ground for improved
thermal performance.
NC
2, 3, 6, 7
8
2, 4, 5
6
2, 5
6
—
O
Regulated output voltage, any output capacitor ≥ 0.47 μF can be
used for stability.
OUT
8
5 Specifications
5.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Input supply voltage, VIN
Peak output current
–0.3
24
V
Internally limited
See Thermal Information
Continuous total power dissipation
Junction temperature, TJ
Storage temperature, Tstg
–40
–65
125
150
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
0
NOM
MAX
24
UNIT
VIN
Input supply voltage
Output current
V
IOUT
CIN
80
mA
µF
µF
Input capacitor
0
0.047
1
COUT
Output capacitor
0.47
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5.4 Thermal Information
TPS715A-NM
THERMAL METRIC(1)
DRV (SON)
DRB (SON)
8 PINS
69
UNIT
6 PINS
79.5
110.5
48.9
5.2
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
76.8
44.6
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
8.1
ψJB
49.3
18.3
44.8
RθJC(bot)
27.5
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
5.5 Electrical Characteristics
Over operating junction temperature range (TJ = –40°C to 125°C), VIN = VOUT(NOM) + 1 V, IOUT = 1 mA, COUT = 1 μF, unless
otherwise noted. The TPS715A01 device is tested with VOUT = 2.8 V. Typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.5
3
TYP
MAX UNIT
IOUT = 10 mA
IOUT = 80 mA
24
V
Input voltage(1)
VIN
24
Voltage range
(TPS715A01)
V
VOUT
1.2
15
VOUT + 1 V ≤ VIN ≤ 24 V,
1.2 V ≤ VOUT ≤ 15V, 0 ≤ IOUT ≤ 80 mA
0.96 ×
VOUT(nom)
1.04 ×
VOUT(nom)
TPS715A01
TPS715A33
ΔVOUT/ΔVIN
ΔVOUT/ΔIOUT
VDO
VOUT(nom)
3.3
Output voltage accuracy(1)
V
4.3 V < VIN < 24 V, 0 ≤ IOUT ≤ 80 mA
VOUT + 1 V < VIN ≤ 24 V
IOUT = 100 μA to 80 mA
IOUT = 80 mA
3.135
3.465
Output voltage
20
60
mV
mV
mV
mA
line regulation(1)
Load regulation
35
Dropout voltage
VIN = VOUT(NOM) – 0.1 V
670
1120
Output current limit
Ground pin current
ICL
VOUT = 0 V
160
1100
4.2
TJ = –40°C to 85°C, 0 mA ≤ IOUT ≤ 80 mA
0 mA ≤ IOUT ≤ 80 mA
3.2
3.2
IGND
4.8
μA
VIN = 24 V, 0 mA ≤ IOUT ≤ 80 mA
5.8
Power-supply ripple
rejection
PSRR
VIN
f = 100 kHz, COUT = 10 μF
60
dB
BW = 200 Hz to 100 kHz,
COUT = 10 μF, IOUT = 50 mA
Output noise voltage
575
μVrms
(1) Minimum VIN = VOUT + VDO, or the value shown for input voltage, whichever is greater.
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5.6 Typical Characteristics
3.465
VIN = 4.3 V
3.432
3.465
3.432
3.399
3.366
3.333
3.300
3.267
3.234
3.201
3.168
3.135
VIN = 4.3 V
3.399
3.366
3.333
3.300
3.267
3.234
3.201
3.168
3.135
IOUT = 10 mA
IOUT = 80 mA
-
- -
40 25 10 5 20 35 50 65 80 95 110 125
0
10 20 30 40 50 60 70 80
IOUT – Output Current – mA
°
TJ – Junction Temperature –
C
Figure 2. TPS715A33 Dropout Voltage vs
Junction Temperature
Figure 1. TPS715A33 Output Voltage vs Output Current
4.5
8
V
V
= 4.3 V
V
V
I
= 4.3 V
IN
IN
7
6
5
4
3
2
1
0
= 3.3 V
= 3.3 V
= 1 mF
OUT
OUT
I
= 1 mA
OUT
4.0
C
= 1 mF
OUT
OUT
I
= 50 mA
OUT
3.5
3.0
2.5
2.0
−40 −25 −10
5
20 35 50 65 80 95 110 125
100
1 k 10 k
f − Frequency − Hz
100 k
T
J
− Junction Temperature − °C
Figure 4. Output Spectral Noise Density vs Frequency
Figure 3. Ground Current vs Junction Temperature
1000
18
VIN = 4.3 V
900
V
= 4.3 V
IN
16
14
TJ = +125ºC
V
= 3.3 V
OUT
800
C
= 1 mF
OUT
T
J
= 25°C
700
12
10
8
600
TJ = +25ºC
500
400
300
6
4
2
0
I
= 1 mA
OUT
200
TJ =-40 ºC
100
0
I
= 50 mA
OUT
0
10 20 30 40 50 60 70 80
10
100
1k
10k 100k
1 M 10 M
- -
IOUT Output Current mA
f − Frequency − Hz
Figure 6. TPS715A33 Dropout Voltage vs Output Current
Figure 5. Output Impedance vs Frequency
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Typical Characteristics (continued)
1400
1000
900
800
700
600
500
400
300
200
100
0
VIN = 4.3 V
1200
1000
IOUT = 80 mA
T
J = +125ºC
800
600
400
200
0
TJ = +25ºC
TJ = –40ºC
IOUT = 10 mA
-
- -
40 25 10 5 20 35 50 65 80 95 110 125
3
4
5
6
7
8
9
10 11 12 13 14 15
°
TJ – Junction Temperature –
C
-
VIN Input Voltage
-
V
Figure 8. TPS715A33 Dropout Voltage vs
Junction Temperature
Figure 7. TPS715A01 Dropout Voltage vs Input Voltage
3.5
100
V
= 4.3 V
VIN = 4.3 V
IN
90
80
3.0
V
= 3.3 V
OUT
VOUT = 3.3 V
C
= 10 mF
OUT
T
J
= 25°C
2.5
2.0
1.5
1.0
0.5
0
70
60
50
I
= 1 mA
OUT
40
30
20
I
= 50 mA
OUT
10
0
0
100
200
300
400
500
10
100
1k
10k 100k
1 M 10 M
- -
IOUT Current Limit mA
f − Frequency − Hz
Figure 9. Output Voltage vs Current Limit
Figure 10. Power-Supply Ripple Rejection vs Frequency
8
V
I
= 3.3 V
V
= 3.3 V
OUT
OUT
100
50
7
= 50 mA
R
= 66 W
OUT
L
C
= 10 mF
C
= 10 mF
OUT
OUT
6
5
4
0
−50
3
V
IN
5.3
4.3
2
1
0
V
OUT
0
50 100 150 200 250 300 350 400 450 500
0
2
4
6
8
10 12 14 16 18 20
t − Time − ms
t − Time − ms
Figure 12. Line Transient Response
Figure 11. Power-Up and Power-Down
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Typical Characteristics (continued)
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10mF
200
0
-200
100
50
0
-0.5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
-
-
Time ms
t
Figure 13. Load Transient Response
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6 Detailed Description
6.1 Overview
The TPS715A-NM family of low dropout regulators consumes only 3.2 µA of current and offers a wide input
voltage range and low-dropout voltage in a small package. The devices operate over an input range of 2.5 V to
24 V and are stable with any capacitor greater than or equal to 0.47 μF. The low quiescent current makes the
TPS715A-NM ideal for powering battery management devices. Specifically, because the TPS715A-NM is
enabled as soon as the applied voltage reaches the minimum input voltage, the output is quickly available to
power continuously-operating, battery-charging devices.
6.2 Functional Block Diagrams
V(OUT)
V(IN)
Current
Sense
Leakage Null
Control Circuit
ILIM
R1
R2
_
+
GND
FB
Vref = 1.205 V
Bandgap
Reference
Figure 14. Functional Block Diagram—Adjustable Version
V(OUT)
V(IN)
Current
Sense
Leakage Null
Control Circuit
ILIM
R1
R2
_
+
GND
Vref = 1.205 V
Bandgap
Reference
Figure 15. Functional Block Diagram—Fixed Version
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6.3 Feature Description
6.3.1 Wide Supply Range
This device has an operational input supply range of 2.5 V to 24 V, allowing for a wide range of applications. This
wide supply range is ideal for applications that have either large transients or high dc voltage supplies.
6.3.2 Low Supply Current
This device only requires 3.2 µA (typical) of supply current and has a maximum current consumption of 5.8 µA at
–40°C to 125°C.
6.3.3 Stable With Any Capacitor ≥ 0.47 µF
Any capacitor, including both ceramic and tantalum, greater than or equal to 0.47 μF properly stabilizes this loop.
6.3.4 Internal Current Limit
The internal current limit circuit is used to protect the LDO against high-load current faults or shorting events. The
LDO is not designed to operate in a steady-state current limit. During a current limit event, the LDO sources
constant current. Therefore, the output voltage falls when load impedance decreases.
NOTE
If a current limit occurs and the resulting output voltage is low, excessive power is
dissipated across the LDO, resulting in possible damage to the device.
6.3.5 Reverse Current
The TPS715A-NM device PMOS-pass transistor has a built-in back diode that conducts current when the input
voltage drops below the output voltage (for example, during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting may
be required.
6.4 Device Functional Modes
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
IOUT
IOUT < ICL
IOUT < ICL
—
Normal
Dropout
Disabled
VIN > VOUT(nom) + VDO
VIN < VOUT(nom) + VDO
—
6.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO).
The output current is less than the current limit (IOUT < ICL).
The device junction temperature is less than 125°C.
6.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass device is in the linear region and no longer controls the current through the LDO.
Line or load transients in dropout can result in large output-voltage deviations.
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7 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
7.1 Application Information
The TPS715A-NM family of LDO regulators is optimized for ultralow-power applications such as the MSP430
microcontroller. The ultralow-supply current of the TPS715A-NM device maximizes efficiency at light loads, and
its high input voltage range makes the device suitable for supplies such as unconditioned solar panels.
7.2 Typical Applications
7.2.1 Typical Application (Fixed-Voltage Version)
TPS715A33
VIN
VOUT
IN
OUT
GND
C1
m
0.47
F
m
0.1
F
Figure 16. Typical Application Circuit (Fixed-Voltage Version)
7.2.1.1 Design Requirements
7.2.1.1.1 Power the MSP430 Microcontroller
Several versions of the TPS715A-NM are ideal for powering the MSP430 microcontroller. Table 2 shows
potential applications of some voltage versions.
Table 2. Typical MSP430 Applications
DEVICE
VOUT (TYP)
1.9 V
APPLICATION
TPS715A19
TPS715A23
TPS715A30
TPS715A345
VOUT(min) > 1.8 V required by many MSP430s. Allows lowest power consumption operation.
VOUT(min) > 2.2 V required by some MSP430s flash operation.
2.3 V
3 V
VOUT(min) > 2.7 V required by some MSP430s flash operation.
3.45 V
VOUT(max) < 3.6 V required by some MSP430s. Allows highest speed operation.
The TPS715A-NM family of devices offers many output voltage versions to allow the supply voltage to be
optimized for the MSP430, thereby minimizing the supply current consumed by the MSP430.
7.2.1.2 Detailed Design Procedure
7.2.1.2.1 External Capacitor Requirements
Although not required, a 0.047-μF or larger input bypass capacitor, connected between IN and GND and located
close to the device, is recommended to improve transient response and noise rejection of the power supply as a
whole. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and
the device is located several inches from the power source.
The TPS715A-NM device requires an output capacitor connected between OUT and GND to stabilize the internal
control loop. Any capacitor (including ceramic and tantalum) greater than or equal to 0.47 μF properly stabilizes
this loop. The X7R- or X5R-type capacitors are recommended because these capacitors have a wider
temperature specification and lower temperature coefficient, but other types of capacitors can be used.
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7.2.1.2.2 Dropout Voltage (VDO
)
Generally speaking, the dropout voltage often refers to the voltage difference between the input and output
voltage (VDO = VIN – VOUT). However, in the Electrical Characteristics table, VDO is defined as the VIN – VOUT
voltage at the rated current, where the pass-FET is fully enhanced in the ohmic region of operation and is
characterized by the classic RDS(on) of the FET. VDO indirectly specifies a minimum input voltage above the
nominal programmed output voltage at which the output voltage is expected to remain within its accuracy
boundary. If the input falls below this VDO limit (VIN < VOUT + VDO), then the output voltage decreases to follow the
input voltage.
Dropout voltage is always determined by the RDS(on) of the main pass-FET. Therefore, if the LDO operates below
the rated current, then the VDO for that current scales accordingly. RDS(on) can be calculated using Equation 1.
VDO
RDS(ON)
=
IRATED
(1)
7.2.1.3 Application Curves
8
V
= 3.3 V
V
I
= 3.3 V
OUT
OUT
100
50
7
R
= 66 W
= 50 mA
L
OUT
C
= 10 mF
C
= 10 mF
OUT
OUT
6
5
4
0
−50
3
V
IN
5.3
4.3
2
1
0
V
OUT
0
50 100 150 200 250 300 350 400 450 500
0
2
4
6
8
10 12 14 16 18 20
t − Time − ms
t − Time − ms
Figure 17. Power-Up and Power-Down
Figure 18. Line Transient Response
VIN = 4.3 V
VOUT = 3.3 V
COUT = 10mF
200
0
-200
100
50
0
-0.5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
-
-
Time ms
t
Figure 19. Load Transient Response
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7.2.2 TPS715A01 Adjustable LDO Regulator Programming
TPS715A01
OUTPUT VOLTAGE
PROGRAMMING GUIDE
V
IN
IN
0.1 mF
OUTPUT
R1
R2
VOLTAGE
1.8 V
OUT
FB
V
OUT
806 kW
806 kW
806 kW
392 kW
1.07 MW
2.55 MW
R1
R2
0.47 mF
2.8 V
5.0 V
GND
Figure 20. TPS715A01 Adjustable LDO Regulator Programming
7.2.2.1 Detailed Design Procedure
7.2.2.1.1 Setting VOUT for the TPS715A01 Adjustable LDO
The TPS715A-NM family of devices contains an adjustable-version, the TPS715A01 device, that sets the output
voltage using an external resistor divider as shown in Figure 20. The output voltage operating range is 1.2 V to
15 V, and is calculated using Equation 2.
R1
æ
ö
VOUT = VREF ´ 1+
ç
÷
R2
è
ø
where
•
VREF = 1.205 V (typical)
(2)
Choose resistors R1 and R2 to allow approximately 1.5-μA of current through the resistor divider. Lower value
resistors can be used for improved noise performance, but consume more power. Avoid higher resistor values
because leakage current into or out of FB across R1, R2 creates an offset voltage that is proportional to VOUT
divided by VREF. The recommended design procedure is to choose R2 = 1 MΩ to set the divider current at
1.5 μA, and then calculate R1 using Equation 3.
æ
ç
è
ö
VOUT
R1=
-1 ´ 2
÷
VREF
ø
(3)
Figure 20 shows this configuration.
7.3 Do's and Don'ts
Place at least one 0.47-µF capacitor as close as possible to the OUT and GND pins of the regulator.
Do not connect the output capacitor to the regulator using a long, thin trace.
Connect an input capacitor of 0.047 µF as close as possible to the IN and GND pins of the regulator for best
performance.
Do not exceed the absolute maximum ratings.
8 Power Supply Recommendations
The TPS715A-NM is designed to operate with an input voltage supply range from 2.5 V to 24 V. The input
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply
must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the
output noise performance.
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SBVS340 –JUNE 2017
9 Layout
9.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the printed-circuit-board and as
near as practical to the respective LDO pin connections. Place ground return connections for the input and output
capacitors as close to the GND pin as possible, using wide, component-side, copper planes. TI strongly
discourages using vias and long traces to create LDO circuit connections to the input capacitor, output capacitor,
or the resistor divider because doing so negatively affects system performance. This grounding and layout
scheme minimizes inductive parasitics, and thereby reduces load-current transients, minimizes noise, and
increases circuit stability. A ground reference plane is recommended to be embedded either in the PCB itself or
located on the bottom side of the PCB opposite the components. This reference plane assures accuracy of the
output voltage and shields the LDO from noise.
9.2 Layout Example
GND PLANE
CIN
COUT
TPS715A01
VOUT
VIN
1
2
3
IN
NC
6
5
4
OUT
NC
GND
FB/NC
R1
GND PLANE
R2
Figure 21. Example Layout for the TPS715A01DRV
9.3 Power Dissipation
To ensure reliable operation, worst-case junction temperature must not exceed 125°C. This restriction limits the
power dissipation the regulator can handle in any given application. To ensure the junction temperature is within
acceptable limits, calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which
must be less than or equal to PD(max)
.
The maximum-power-dissipation limit is determined using Equation 4.
TJ max- TA
PD(max)
=
RqJA
where
•
•
•
TJmax is the maximum allowable junction temperature
θJA is the thermal resistance junction-to-ambient for the package (see the Thermal Information table)
TA is the ambient temperature
R
(4)
(5)
The regulator power dissipation is calculated using Equation 5.
PD = (VIN - VOUT )´IOUT
For a higher power package version of the TPS715A-NM, see the TPS715A-NM.
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10 Device and Documentation Support
10.1 Device Support
10.1.1 Development Support
10.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS715A-
NM. The TPS715AXXEVM-065 evaluation module (and related user's guide) can be requested at the TI website
through the product folders or purchased directly from the TI eStore.
10.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS715A-NM is available through the product folders under
Tools & Software.
10.1.2 Device Nomenclature
Table 3. Device Nomenclature(1)
PRODUCT
VOUT
xx is nominal output voltage (for example 33 = 3.3V, 01 = adjustable)
yyy is package designator
TPS715A-NMxxyyyz
z is package quantity
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
10.2 Documentation Support
10.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
TPS715AxxEVM User Guide, SLVU122
LDO Noise Demystified, SLAA412
LDO PSRR Measurement Simplified, SLAA414
A Topical Index of TI LDO Application Notes, SBVA026
10.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
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10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
10.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS715A01DRBT-NM
ACTIVE
SON
DRB
8
250
RoHS & Green
SN
Level-2-260C-1 YEAR
-40 to 125
ANONM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OUTLINE
DRB0008A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
DIM A
OPT 1
(0.1)
OPT 2
(0.2)
1.5 0.1
4X (0.23)
EXPOSED
THERMAL PAD
(DIM A) TYP
4
5
2X
1.95
1.75 0.1
8
1
6X 0.65
0.37
0.25
8X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
(0.65)
0.05
0.5
0.3
8X
4218875/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.5)
(0.65)
SYMM
8X (0.6)
(0.825)
8
8X (0.31)
1
SYMM
(1.75)
(0.625)
6X (0.65)
4
5
(R0.05) TYP
(
0.2) VIA
(0.23)
TYP
(0.5)
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218875/A 01/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRB0008A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.65)
4X (0.23)
SYMM
METAL
TYP
8X (0.6)
4X
(0.725)
8
1
8X (0.31)
(2.674)
(1.55)
SYMM
6X (0.65)
4
5
(R0.05) TYP
(1.34)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
84% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218875/A 01/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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