TPS71710DRVRG4 [TI]
Low Noise, High-Bandwidth PSRR Low-Dropout 150mA Linear Regulator; 低噪声，高带宽PSRR低压降150mA线性稳压器
| 型号： | TPS71710DRVRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Low Noise, High-Bandwidth PSRR Low-Dropout 150mA Linear Regulator |
| 文件： | 总28页 (文件大小：1152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS717xx
www.ti.com .................................................................................................................................................. SBVS068G–FEBRUARY 2006–REVISED APRIL 2009
Low Noise, High-Bandwidth PSRR
Low-Dropout 150mA Linear Regulator
1
FEATURES
DESCRIPTION
23
•
150mA Low-Dropout Regulator with Enable
The TPS717xx family of low-dropout (LDO),
low-power linear regulators offers very high power
supply rejection (PSRR) while maintaining very low
45µA ground current in an ultra-small, five-pin SC70
package. The family uses an advanced BiCMOS
process and a PMOSFET pass device to achieve fast
start-up, very low noise, excellent transient response,
and excellent PSRR performance. The TPS717xx is
stable with a 1.0µF ceramic output capacitor, and
uses a precision voltage reference and feedback loop
to achieve a worst-case accuracy of 3% over all load,
line, process, and temperature variations. It is fully
specified from TJ = –40°C to +125°C and is offered in
a small SC70-5 package, a 2mm × 2mm SON-6
package with a thermal pad, and a 1.5mm × 1.5mm
SON package, which are ideal for small form factor
portable equipment such as wireless handsets and
PDAs.
•
•
Low IQ: 45µA (typical)
Available in Multiple Output Versions:
–
Fixed Output with Voltages from 0.9V to
5.0V Using Innovative Factory EEPROM
Programming
–
Adjustable Output Voltage from 0.9V to
6.2V
•
Ultra-High PSRR:
–
70dB at 1kHz, 67dB at 100kHz and 45dB at
1MHz
•
•
•
•
•
Low Noise: 30µV typical (100Hz to 100kHz)
Stable with a 1.0µF Ceramic Capacitor
Excellent Load/Line Transient Response
3% Overall Accuracy (over Load/Line/Temp)
Over-Current and Over-Temperature
Protection
VIN
VOUT
IN
OUT
TPS717xx
GND
1mF
Ceramic
1mF
Ceramic
•
•
Very Low Dropout: 170mV Typical at 150mA
EN
NR
Small SC70-5, 2mm x 2mm SON-6, and 1.5mm
× 1.5mm SON-6 Packages
VEN
0.01mF
(Optional)
APPLICATIONS
Typical Application Circuit for Fixed Voltage Versions
•
•
•
Mobile Phone Handsets
Wireless LAN, Bluetooth®
PDAs and Smartphones
80
70
60
50
40
30
20
10
0
150mA
TPS717xx DCK
SC70-5 PACKAGE
(TOP VIEW)
10mA
1
2
3
5
4
OUT
IN
GND
EN
TPS717xx DSE
1.5mm x 1.5mm SON
(TOP VIEW)
75mA
NR/FB
OUT
GND
1
2
3
6
5
4
IN
N/C(1)
TPS717xx DRV
2mm x 2mm SON
(TOP VIEW)
COUT = 1mF
CNR = 10nF
NR/FB
EN
10
100
1k
10k
100k
1M
10M
OUT
NR/FB
GND
1
2
3
6
5
4
IN
N/C(1)
Frequency (Hz)
GND
NOTE: (1) N/C = Not connected.
EN
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
TPS717xx
SBVS068G–FEBRUARY 2006–REVISED APRIL 2009.................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS717xxyyyz
XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 0.9V to 5.0V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating temperature range (unless otherwise noted). All voltages are with respect to GND.
PARAMETER
TPS717xx
–0.3 to +7.0
UNIT
Input voltage range, VIN
V
V
V
V
Feedback input voltage range, VFB, VNR
Enable voltage range, VEN
Output voltage range, VOUT
Maximum output current, IOUT
Continuous total power dissipation, PDISS
Junction temperature range, TJ
Storage junction temperature range, TSTG
ESD rating, HBM
–0.3 to +3.6
–0.3 to VIN + 0.3V(2)
–0.3 to +7.0
Internally limited
See Dissipation Ratings Table
–55 to +150
°C
°C
kV
V
–55 to +150
2
ESD rating, CDM
500
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) VEN absolute maximum rating is VIN + 0.3V or +7.0V, whichever is greater.
DISSIPATION RATINGS
DERATING FACTOR
BOARD
Low-K(1)
High-K(2)
Low-K(1)
High-K(2)
High-K(2)
PACKAGE
DCK
RθJC
165°C/W
165°C/W
20°C/W
20°C/W
—
RθJA
ABOVE TA = +25°C
TA < +25°C
250mW
TA = +70°C
140mW
175mW
395mW
845mW
269mW
TA = +85°C
100mW
130mW
285mW
615mW
194mW
395°C/W
315°C/W
140°C/W
65°C/W
206°C/W
2.5mW/°C
DCK
3.2mW/°C
320mW
DRV
7.1mW/°C
715mW
DRV
15.4mW/°C
4.85mW/°C
1540mW
485mW
DSE
(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
2
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TPS717xx
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ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater;
IOUT = 0.5mA, VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V.
Typical values are at TJ = +25°C.
PARAMETER
Input voltage range(1)
TEST CONDITIONS
MIN
2.5
TYP
MAX
6.5
UNIT
V
VIN
VFB
Internal reference (TPS71701)
Output voltage range (TPS717xx)
Output voltage range (TPS71701)
0.790
0.9
0.800
0.810
V
5.0
V
VOUT
0.9
6.5 – VDO
V
Output accuracy
Nominal
TJ = +25°C
±2.5
mV
Output accuracy
(VOUT < 1.0V)
Over VIN, IOUT
Temp(2)
,
,
VOUT + 0.5V ≤ VIN ≤ 6.5V
0mA ≤ IOUT ≤ 150mA
–30
+30
mV
%
VOUT
Output accuracy
(VOUT ≥ 1.0V)
Over VIN, IOUT
Temp(2)
VOUT + 0.5V ≤ VIN ≤ 6.5V
0mA ≤ IOUT ≤ 150mA
–3.0
+3.0
VOUT(NOM) + 0.5V ≤ VIN ≤ 6.5V,
IOUT = 5mA
(1)
ΔVOUT/ ΔVIN
ΔVOUT/ ΔIOUT
VDO
Line regulation
Load regulation
125
120
170
µV/V
µV/mA
mV
0mA ≤ IOUT ≤ 150mA
Dropout voltage(3)
(VIN = VOUT(NOM) – 0.1V)
IOUT = 150mA
300
ICL (Fixed)
Output current limit (fixed output)
VOUT = 0.9 × VOUT(NOM)
VOUT = 0.9 × VOUT(NOM)
IOUT = 0.1mA
200
200
325
325
45
575
575
80
mA
mA
µA
ICL (Adjustable) Output current limit (TPS71701)
IGND
Ground pin current
IOUT = 150mA
100
µA
V
EN ≤ 0.4V, 2.5V ≤ VIN < 4.5V,
0.20
0.90
1.5
1.0
µA
µA
TJ = –40°C to +85°C
Shutdown current
ISHDN
(IGND
)
VEN ≤ 0.4V, 4.5V ≤ VIN ≤ 6.5V,
TJ = –40°C to +85°C
IFB
Feedback pin current (TPS71701)
0.02
70
µA
dB
dB
dB
dB
dB
f = 100Hz
f = 1kHz
70
Power-supply rejection ratio
VIN = 3.8V, VOUT = 2.8V,
IOUT = 150mA
PSRR
f = 10kHz
f = 100kHz
f = 1MHz
67
67
45
CNR = none
(fixed output, TPS71701)
95 × VOUT
µVRMS
Output noise voltage
BW = 100Hz to 100kHz,
VIN = 3.8V, VOUT = 2.8V,
IOUT = 10mA
CNR = 0.001µF
25 × VOUT
12.5 × VOUT
11.5 × VOUT
0.700
µVRMS
µVRMS
µVRMS
ms
VN
CNR = 0.01µF
CNR = 0.1µF
Startup time
0.9V ≤ VOUT ≤ 1.6V, CNR = 0.001µF
TSTR
VOUT = 90% VOUT(NOM),
RL = 19Ω, COUT = 1.0µF
1.6V < VOUT < VMAX, CNR = 0.01µF
0.160
ms
V
IN ≤ 5.5V
1.2
1.25
0
6.5(4)
6.5
V
V
VEN(HI)
Enable high (enabled)
5.5V < VIN ≤ 6.5V
VEN(LO)
IEN(HI)
Enable low (shutdown)
Enable pin current, enabled
Under-voltage lockout
Hysteresis
0.4
V
EN = 6.5V
0.02
2.45
150
1.0
µA
V
VIN rising
2.41
2.49
UVLO
VIN falling
mV
°C
°C
°C
Shutdown, temperature increasing
Reset, temperature decreasing
+160
+140
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
–40
+125
(1) Minimum VIN = VOUT + VDO or 2.5V, whichever is greater.
(2) Does not include external resistor tolerances.
(3) VDO is not measured for devices with VOUT(NOM) < 2.6V because minimum VIN = 2.5V.
(4) Maximum VEN(HI) = VIN + 0.3 or 6.5V, whichever is smaller.
Copyright © 2006–2009, Texas Instruments Incorporated
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DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAMS
IN
OUT
2.5mA
Current
Limit
EN
Thermal
Shutdown
UVLO
Quickstart
VOUT > 1.6V
1.20V
Bandgap
NR
360kW
250kW
0.8V
VOUT £ 1.6V
640kW
GND
Figure 1. Fixed Voltage Versions
IN
OUT
Current
Limit
EN
Thermal
Shutdown
3.3MW
UVLO
1.20V
Bandgap
360kW
FB
0.8V
250kW
640kW
GND
Figure 2. Adjustable Voltage Version
4
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TPS717xx
www.ti.com .................................................................................................................................................. SBVS068G–FEBRUARY 2006–REVISED APRIL 2009
PIN CONFIGURATIONS
TPS717xx DCK
SC70-5 PACKAGE
(TOP VIEW)
TPS717xx DRV
2mm x 2mm SON
(TOP VIEW)
TPS717xx DSE
1.5mm x 1.5mm SON
(TOP VIEW)
IN
GND
EN
1
2
3
5
4
OUT
OUT
NR/FB
GND
1
2
3
OUT
GND
1
2
3
6
5
4
IN
N/C(1)
6
5
4
IN
N/C(1)
GND
NR/FB
NR/FB
EN
EN
NOTE: (1) N/C = Not connected.
Table 1. PIN DESCRIPTIONS
TPS717xx
1.5×1.5
SC70
(DCK)
2×2 SON
(DRV)
SON
(DSE)
NAME
IN
DESCRIPTION
1
2
6
3
6
2
Input to the device.
Ground.
GND
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
regulator into standby mode, thereby reducing operating current.
EN
NR
FB
3
4
4
4
2
2
4
3
3
Fixed voltage versions only. An external capacitor connected to this terminal bypasses
noise generated by the internal bandgap, lowering output noise.
Adjustable voltage version only. The voltage at this pin is fed to the error amplifier. A
resistor divider from OUT to FB sets the output voltage when in regulation.
This is the regulated output voltage. A small capacitor is needed from this pin to ground
to assure stability; a 1.0µF ceramic capacitor is adequate.
OUT
NC
5
–
1
5
1
5
Not connected. This pin can be tied to ground to improve thermal dissipation.
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TPS717xx
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TYPICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA,
VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V.
Typical values are at TJ = +25°C.
LOAD REGULATION
LOAD REGULATION UNDER LIGHT LOADS
50
40
50
40
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
30
30
20
20
10
10
0
0
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
0
2.5
0
1
2
3
4
5
6.5
150
150
0
50
100
IOUT (mA)
IOUT (mA)
Figure 3.
Figure 4.
LINE REGULATION
IOUT = 5mA
LINE REGULATION
IOUT = 150mA
1.0
0.8
3.0
2.0
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = -40°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
0.6
0.4
1.0
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.0
-2.0
-3.0
2.5
3.5
4.5
5.5
6.5
3.5
4.5
5.5
VIN (V)
VIN (V)
Figure 5.
Figure 6.
OUTPUT VOLTAGE vs
TEMPERATURE
DROPOUT VOLTAGE vs
OUTPUT CURRENT
2.0
1.5
250
200
150
100
50
TJ = +125°C
1.0
0.5
IOUT = 5mA
TJ = +85°C
0
-0.5
-1.0
-1.5
-2.0
IOUT = 100mA
TJ = +25°C
IOUT = 150mA
TJ = -40°C
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
50
100
TJ (°C)
IOUT (mA)
Figure 7.
Figure 8.
6
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA,
VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V.
Typical values are at TJ = +25°C.
DROPOUT VOLTAGE vs
TEMPERATURE
GROUND PIN CURRENT vs
INPUT VOLTAGE
300
250
200
150
100
50
150
120
90
60
30
0
VOUT = 2.8V
IOUT = 150mA
IOUT = 150mA
IOUT = 100mA
IOUT = 10mA
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.5
3.5
4.5
5.5
6.5
TJ (°C)
VIN (V)
Figure 9.
Figure 10.
GROUND PIN CURRENT vs
OUTPUT CURRENT
GROUND PIN CURRENT vs
TEMPERATURE (ENABLED)
150
120
90
60
30
0
150
120
90
60
30
0
IOUT = 150mA
IOUT = 100mA
0
50
100
150
-40 -25 -10
5
20 35 50 65 80 95 110 125
IOUT (mA)
TJ (°C)
Figure 11.
Figure 12.
GROUND PIN CURRENT vs
TEMPERATURE (DISABLED)
CURRENT LIMIT vs
INPUT VOLTAGE
5
4
3
2
1
0
600
500
400
300
200
VEN = 0.4V
TJ = -40°C
TJ = +25°C
TJ = +85°C
VIN = 4.5V
VIN = 6.5V
TJ = +125°C
VIN = 3.3V
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.5
3.5
4.5
5.5
6.5
TJ (°C)
VIN (V)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA,
VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V.
Typical values are at TJ = +25°C.
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN – VOUT = 1V)
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN – VOUT = 0.5V)
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
10mA
150mA
75mA
150mA
10mA
75mA
COUT = 1mF
CNR = 10nF
COUT = 1mF
CNR = 10nF
10
100
1k
10k
100k
1M
10M
10
10
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 15.
Figure 16.
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN – VOUT = 0.25V)
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN – VOUT = 1V)
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
10mA
10mA
75mA
150mA
150mA
COUT = 1mF
COUT = 10mF
CNR = 10nF
CNR = 10nF
10
100
1k
10k
100k
1M
10M
100
10k
100k
10M
1k
1M
Frequency (Hz)
Frequency (Hz)
Figure 17.
Figure 18.
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN – VOUT = 0.25V)
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN – VOUT = 1V)
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
10mA
10mA
150mA
150mA
COUT = 10mF
COUT = 10mF
CNR = 10nF
CNR = 0nF
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 19.
Figure 20.
8
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA,
VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V.
Typical values are at TJ = +25°C.
POWER-SUPPLY RIPPLE REJECTION vs
(VIN – VOUT
POWER-SUPPLY RIPPLE REJECTION vs
(VIN – VOUT
)
)
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
1kHz
1kHz
10kHz
100kHz
10kHz
1MHz
100kHz
1MHz
IOUT = 10mA
COUT = 1mF
CNR = 10nF
IOUT = 75mA
COUT = 1mF
CNR = 10nF
0
0.5
1.0
1.5
2.0
IN - VOUT (V)
Figure 21.
2.5
3.0
3.5
4.0
0
0.5
1.0
1.5
2.0
IN - VOUT (V)
Figure 22.
2.5
3.0
3.5
4.0
V
V
POWER-SUPPLY RIPPLE REJECTION vs
(VIN – VOUT
OUTPUT SPECTRAL NOISE DENSITY vs
OUTPUT CURRENT
)
80
70
60
50
40
30
20
10
0
16
14
12
10
8
1kHz
100kHz
COUT = 1mF
CNR = 10nF
IOUT = 150mA
IOUT = 10mA
10kHz
1MHz
6
4
IOUT = 150mA
COUT = 1mF
CNR = 10nF
2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
100
1k
10k
100k
VIN - VOUT (V)
Frequency (Hz)
Figure 23.
Figure 24.
OUTPUT SPECTRAL NOISE DENSITY vs
OUTPUT CAPACITANCE
OUTPUT SPECTRAL NOISE DENSITY vs
NOISE REDUCTION
16
14
12
10
8
30
25
20
15
10
5
IOUT = 10mA
IOUT = 10mA
CNR = 10nF
COUT = 1mF
COUT = 10mF
COUT = 1mF
6
CNR = 10nF
CNR = 100nF
CNR = 0nF
4
CNR = 1nF
2
0
0
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 25.
Figure 26.
Copyright © 2006–2009, Texas Instruments Incorporated
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9
TPS717xx
SBVS068G–FEBRUARY 2006–REVISED APRIL 2009.................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.5V, whichever is greater; IOUT = 0.5mA,
VEN = VIN, COUT = 1.0µF, CNR = 0.01µF, unless otherwise noted. For TPS71701, VOUT = 2.8V.
Typical values are at TJ = +25°C.
TOTAL OUTPUT NOISE vs
NOISE REDUCTION
TOTAL OUTPUT NOISE vs
OUTPUT CAPACITANCE
300
270
240
210
180
150
120
90
50
45
40
35
30
25
20
15
10
5
IOUT = 10mA
VOUT = 2.8V, CNR = 10nF
VOUT = 1.3V, CNR = 1nF
COUT = 1mF
60
30
0
0
0
1
10
100
0
5
10
15
20
25
CNR (nF)
COUT (mF)
Figure 27.
Figure 28.
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
VIN = 3.3V
COUT = 1mF
10mV/div
VOUT
COUT = 1mF
dVIN
dt
50mV/div
VOUT
= 1V/ms
6.5V
150mA
3.3V
0mA
1V/div
VIN
40mV/div
IOUT
100ms/div
100ms/div
Figure 29.
Figure 30.
TURN-ON RESPONSE
POWER-UP/POWER-DOWN
VOUT
VIN
IOUT = 150mA
COUT = 1mF
6
5
VOUT
COUT = 10mF
1V/div
1V/div
4
3
2
VOUT
1
0
6.5V
VIN
0V
4V/div
50ms/div
Figure 31.
50ms/div
Figure 32.
10
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Copyright © 2006–2009, Texas Instruments Incorporated
TPS717xx
www.ti.com .................................................................................................................................................. SBVS068G–FEBRUARY 2006–REVISED APRIL 2009
APPLICATION INFORMATION
The TPS717xx belongs to a family of new generation
For the adjustable version (TPS71701), the NR pin is
LDO regulators that use innovative circuitry to
replaced with a feedback (FB) pin. The voltage on
achieve ultra-wide bandwidth and high loop gain,
this pin sets the output voltage and is determined by
resulting in extremely high PSRR (up to 1MHz) at
the values of R1 and R2. The values of R1 and R2 can
very low headroom (VIN – VOUT). Fixed voltage
be calculated for any voltage using the formula given
versions provide a noise reduction pin to bypass
in Equation 1:
noise generated by the bandgap reference and to
improve PSRR while a quick-start circuit fast-charges
(R1 + R2 )
this capacitor. These features, combined with low
noise, enable, low ground pin current, and ultra-small
packaging, make this part ideal for portable
applications. This family of regulators offers
sub-bandgap output voltages, current limit and
thermal protection, and is fully specified from –40°C
to +125°C.
VOUT
=
x 0.800, R2 ~ 320kW
R2
(1)
The value of R2 directly impacts the stability of the
device and should be chosen at approximately 160kΩ
or 320kΩ. Sample resistor values for common output
voltages are shown in Table 2.
Figure 33 shows the basic circuit connections for the
fixed voltage options. Figure 34 gives the connections
for the adjustable output version (TPS71701). Note
that the NR pin is not available on the adjustable
version.
Table 2. Sample 1% Resistor Values for Common
Output Voltages
VOUT
1.0
1.2
1.5
1.8
2.5
3.3
5.0
R1
R2
80.6kΩ
162kΩ
294kΩ
402kΩ
665kΩ
1.02MΩ
1.74MΩ
324kΩ
324kΩ
332kΩ
324kΩ
316kΩ
324kΩ
332kΩ
Optional 1.0mF input
capacitor. May improve
source impedance, noise
or PSRR.
VIN
VOUT
IN
OUT
TPS717xx
1mF
Ceramic
EN
GND
NR
Input and Output Capacitor Requirements
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1.0µF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor will counteract reactive input
sources and improve transient response, noise
VEN
Optional 0.01mF bypass
capacitor to reduce
output noise and
increase PSRR.
Figure 33. Typical Application Circuit
(Fixed Voltage Versions)
rejection, and ripple rejection.
A
higher-value
capacitor may be necessary if large, fast rise-time
load transients are anticipated or if the device is
located several inches from the power source. If
source impedance is not sufficiently low, a 0.1µF
input capacitor may be necessary to ensure stability.
Optional 1.0mF input
capacitor. May improve
source impedance, noise
or PSRR.
The TPS717xx is designed to be stable with standard
ceramic capacitors of values 1.0µF or larger. X5R-
and X7R-type capacitors are best because they have
minimal variation in value and ESR over temperature.
Maximum ESR should be <1.0Ω.
VIN
VOUT
IN
OUT
TPS71701
1mF
Ceramic
R1
R2
EN
GND
FB
The TPS717xx implements an innovative internal
compensation circuit that does not require a feedback
capacitor across R2 for stability. A feedback capacitor
should not be used for this device.
VEN
Figure 34. Typical Application Circuit
(Adjustable Voltage Version)
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TPS717xx
SBVS068G–FEBRUARY 2006–REVISED APRIL 2009.................................................................................................................................................. www.ti.com
Output Noise
Dropout Voltage
In most LDOs, the bandgap is the dominant noise
source. If a noise reduction capacitor (CNR) is used
with the TPS717xx, the bandgap does not contribute
significantly to noise. Instead, noise is dominated by
the output resistor divider and the error amplifier
input. To minimize noise in a given application, use a
0.01µF (minimum) noise reduction capacitor; for the
adjustable version, smaller value resistors in the
The TPS717xx uses a PMOS pass transistor to
achieve low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the PMOS pass device is
in its linear region of operation and the input-to-output
resistance is the RDS(ON) of the PMOS pass element.
VDO will approximately scale with output current
because the PMOS device behaves like a resistor in
dropout.
output resistor divider reduce noise.
A parallel
As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in Figure 21 through
Figure 23 in the Typical Characteristics section.
combination that gives 2.5µA of divider current has
the same noise performance as a fixed voltage
version.
Equation 2 approximates the total noise referred to
the feedback point (FB pin) when CNR = 0.01µF, total
noise is approximately given by Equation 2:
Startup
Fixed voltage versions of the TPS717xx use a
quick-start circuit to fast-charge the noise reduction
capacitor, CNR, if present (see Functional Block
Diagrams, Figure 1). This circuit allows the
combination of very low output noise and fast start-up
times. The NR pin is high impedance, so a low
leakage CNR capacitor must be used; most ceramic
capacitors are appropriate in this configuration.
mVRMS
VN = 11.5
x VOUT
V
(2)
Board Layout Recommendations to Improve
PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Note that for fastest startup, VIN should be applied
first, then the enable pin (EN) driven high. If EN is
tied to IN, startup will be somewhat slower. Refer to
Figure 31 in the Typical Characteristics section. The
quick-start switch is closed for approximately 135µs.
To ensure that CNR is fully charged during the
quick-start time, a 0.01µF or smaller capacitor should
be used.
Internal Current Limit
The TPS717xx internal current limit helps protect the
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
largely independent of output voltage. For reliable
operation, the device should not be operated in a
current limit state for extended periods of time.
For output voltages below 1.6V, a voltage divider on
the bandgap reference voltage is employed to
optimize output regulation performance for lower
output voltages. This configuration results in an
additional resistor in the quick-start path and
combined with the noise reduction capacitor (CNR
)
The PMOS pass element in the TPS717xx has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting may be
appropriate.
results in slower start-up times for output voltages
below 1.6V.
Equation 3 approximates the start-up time as a
function of CNR for output voltages below 1.6V:
ms
tSTART = 160ms + (540
x CNRnF)ms
nF
(3)
Shutdown
Transient Response
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN.
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response.
12
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TPS717xx
www.ti.com .................................................................................................................................................. SBVS068G–FEBRUARY 2006–REVISED APRIL 2009
Under-Voltage Lock-Out (UVLO)
+35°C above the maximum expected ambient
condition of your particular application. This
The TPS717xx utilizes an under-voltage lock-out
circuit to keep the output shut off until internal
circuitry is operating properly. The UVLO circuit has a
de-glitch feature so that it typically ignores
undershoot transients on the input if they are less
than 50µs duration.
configuration produces
a
worst-case junction
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
The internal protection circuitry of the TPS717xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS717xx into thermal
shutdown will degrade device reliability.
Minimum Load
The TPS717xx is stable and well-behaved with no
output load. Traditional PMOS LDO regulators suffer
from lower loop gain at very light output loads. The
TPS717xx employs an innovative low-current mode
circuit to increase loop gain under very light or
no-load conditions, resulting in improved output
voltage regulation performance down to zero output
current.
Power Dissipation
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
of other components moves the heat from the device
to the ambient air. Performance data for JEDEC low-
and high-K boards are given in the Dissipation
Ratings table. Using heavier copper will increase the
effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating
layers also improves the heatsink effectiveness.
THERMAL INFORMATION
Thermal Protection
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage because of
overheating.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT), as
shown in Equation 4:
ǒ
Ǔ
PD + VIN * VOUT IOUT
(4)
Package Mounting
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
Solder pad footprint recommendations for the
TPS717xx are available from the Texas Instruments
web site at www.ti.com.
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
Copyright © 2006–2009, Texas Instruments Incorporated
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2009
PACKAGING INFORMATION
Orderable Device
TPS71701DCKR
TPS71701DCKRG4
TPS71701DCKT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SC70
DCK
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
SC70
SC70
DCK
DCK
DCK
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71701DCKTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71701DRVR
TPS71701DRVT
TPS71709DSER
PREVIEW
PREVIEW
ACTIVE
SON
SON
SON
DRV
DRV
DSE
6
6
6
TBD
TBD
Call TI
Call TI
Call TI
Call TI
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71709DSERG4
TPS71709DSET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
DSE
DSE
DSE
DCK
DCK
DCK
DCK
DRV
DRV
DRV
DRV
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
6
6
6
5
5
5
5
6
6
6
6
5
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71709DSETG4
TPS71710DCKR
TPS71710DCKRG4
TPS71710DCKT
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
SC70
SC70
SC70
SON
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71710DCKTG4
TPS71710DRVR
TPS71710DRVRG4
TPS71710DRVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71710DRVTG4
TPS71711DCKR
TPS71711DCKRG4
TPS71711DCKT
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71711DCKTG4
TPS71712DCKR
TPS71712DCKRG4
TPS71712DCKT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71712DCKTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2009
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
TPS71713DCKR
TPS71713DCKRG4
TPS71713DCKT
TPS71713DCKTG4
TPS71715DCKR
TPS71715DCKRG4
TPS71715DCKT
TPS71715DCKTG4
TPS717185DSER
TPS717185DSET
TPS71718DCKR
TPS71718DCKRG4
TPS71718DCKT
TPS71718DCKTG4
TPS71718DSER
TPS71718DSERG4
TPS71718DSET
TPS71718DSETG4
TPS71719DCKR
TPS71719DCKRG4
TPS71719DCKT
TPS71719DCKTG4
TPS71721DCKR
TPS71721DCKT
TPS71725DCKR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SON
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DSE
DSE
DCK
DCK
DCK
DCK
DSE
DSE
DSE
DSE
DCK
DCK
DCK
DCK
DCK
DCK
DCK
5
5
5
5
5
5
5
5
6
6
5
5
5
5
6
6
6
6
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
SC70
SC70
SC70
SON
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
SC70
SC70
SC70
SC70
SC70
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2009
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS71725DCKRG4
TPS71725DCKT
SC70
DCK
5
5
5
5
5
5
5
5
5
5
5
6
6
5
5
5
5
5
5
5
5
6
6
6
6
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SON
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DSE
DSE
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DSE
DSE
DSE
DSE
DCK
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71725DCKTG4
TPS71726DCKR
TPS71726DCKRG4
TPS71726DCKT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71726DCKTG4
TPS71727DCKR
TPS71727DCKRG4
TPS71727DCKT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71727DCKTG4
TPS71727DSER
TPS71727DSET
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS717285DCKR
TPS717285DCKRG4
TPS717285DCKT
TPS717285DCKTG4
TPS71728DCKR
TPS71728DCKRG4
TPS71728DCKT
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SON
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71728DCKTG4
TPS71728DSER
TPS71728DSERG4
TPS71728DSET
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS71728DSETG4
TPS71729DCKR
SON
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2009
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPS71729DCKRG4
TPS71729DCKT
TPS71729DCKTG4
TPS71730DCKR
TPS71730DCKRG4
TPS71730DCKT
TPS71730DCKTG4
TPS71733DCKR
TPS71733DCKRG4
TPS71733DCKT
TPS71733DCKTG4
TPS71733DRVR
TPS71733DRVRG4
TPS71733DRVT
TPS71733DRVTG4
TPS71733DSER
TPS71733DSERG4
TPS71733DSET
TPS71733DSETG4
TPS71745DSER
TPS71745DSET
SC70
DCK
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DRV
DRV
DRV
DRV
DSE
DSE
DSE
DSE
DSE
DSE
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
1-May-2009
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS71701DCKR
TPS71701DCKT
TPS71709DSER
TPS71709DSET
TPS71710DCKR
TPS71710DCKT
TPS71710DRVR
TPS71710DRVT
TPS71711DCKR
TPS71711DCKT
TPS71712DCKT
TPS71713DCKR
TPS71713DCKT
TPS71715DCKR
TPS71715DCKT
TPS71718DCKR
TPS71718DCKT
TPS71718DSER
SC70
SC70
SON
DCK
DCK
DSE
DSE
DCK
DCK
DRV
DRV
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DSE
5
5
6
6
5
5
6
6
5
5
5
5
5
5
5
5
5
6
3000
250
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.25
2.2
2.4
2.5
1.8
1.8
2.4
2.4
2.2
2.2
2.4
2.4
2.4
2.4
2.4
2.5
2.5
2.5
2.5
1.8
1.22
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q2
Q2
Q3
Q3
Q2
Q2
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q2
3000
250
1.8
1.0
SON
1.8
1.0
SC70
SC70
SON
3000
250
2.25
2.25
2.2
1.22
1.22
1.2
3000
250
SON
2.2
1.2
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SON
3000
250
2.25
2.25
2.25
2.25
2.25
2.2
1.22
1.22
1.22
1.22
1.22
1.2
250
3000
250
3000
250
2.2
1.2
3000
250
2.2
1.2
2.2
1.2
3000
1.8
1.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2009
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
TPS71718DSET
TPS71719DCKT
TPS71721DCKR
TPS71721DCKT
TPS71725DCKR
TPS71725DCKT
TPS71726DCKR
TPS71726DCKT
TPS71727DCKR
TPS71727DCKT
TPS71727DSER
TPS71727DSET
TPS717285DCKR
TPS717285DCKT
TPS71728DCKR
TPS71728DCKT
TPS71728DSER
TPS71728DSET
TPS71729DCKT
TPS71730DCKR
TPS71730DCKT
TPS71733DCKR
TPS71733DCKT
TPS71733DRVR
TPS71733DRVT
TPS71733DSER
TPS71733DSET
TPS71745DSER
TPS71745DSET
SON
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SON
SON
SC70
SC70
SC70
SC70
SON
SON
SC70
SC70
SC70
SC70
SC70
SON
SON
SON
SON
SON
SON
DSE
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DSE
DSE
DCK
DCK
DCK
DCK
DSE
DSE
DCK
DCK
DCK
DCK
DCK
DRV
DRV
DSE
DSE
DSE
DSE
6
5
5
5
5
5
5
5
5
5
6
6
5
5
5
5
6
6
5
5
5
5
5
6
6
6
6
6
6
250
250
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.8
2.25
2.2
1.8
2.4
2.5
2.5
2.5
2.5
2.4
2.4
2.4
2.4
1.8
1.8
2.4
2.4
2.5
2.4
1.8
1.8
2.4
2.4
2.4
2.5
2.4
2.2
2.2
1.8
1.8
1.8
1.8
1.0
1.22
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q2
Q2
Q3
Q3
Q3
Q3
Q2
Q2
Q3
Q3
Q3
Q3
Q3
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
2.2
1.2
3000
250
2.2
1.2
2.2
1.2
3000
250
2.25
2.25
2.25
2.25
1.8
1.22
1.22
1.22
1.22
1.0
3000
250
3000
250
1.8
1.0
3000
250
2.25
2.25
2.2
1.22
1.22
1.2
3000
250
2.25
1.8
1.22
1.0
3000
250
1.8
1.0
250
2.25
2.25
2.25
2.2
1.22
1.22
1.22
1.2
3000
250
3000
250
2.25
2.2
1.22
1.2
3000
250
2.2
1.2
3000
250
1.8
1.0
1.8
1.0
3000
250
1.8
1.0
1.8
1.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS71701DCKR
TPS71701DCKT
TPS71709DSER
TPS71709DSET
TPS71710DCKR
TPS71710DCKT
TPS71710DRVR
TPS71710DRVT
TPS71711DCKR
TPS71711DCKT
TPS71712DCKT
TPS71713DCKR
TPS71713DCKT
TPS71715DCKR
TPS71715DCKT
TPS71718DCKR
TPS71718DCKT
TPS71718DSER
TPS71718DSET
TPS71719DCKT
SC70
SC70
SON
DCK
DCK
DSE
DSE
DCK
DCK
DRV
DRV
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DSE
DSE
DCK
5
5
6
6
5
5
6
6
5
5
5
5
5
5
5
5
5
6
6
5
3000
250
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
3000
250
SON
SC70
SC70
SON
3000
250
3000
250
SON
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SON
3000
250
250
3000
250
3000
250
3000
250
3000
250
SON
SC70
250
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2009
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS71721DCKR
TPS71721DCKT
TPS71725DCKR
TPS71725DCKT
TPS71726DCKR
TPS71726DCKT
TPS71727DCKR
TPS71727DCKT
TPS71727DSER
TPS71727DSET
TPS717285DCKR
TPS717285DCKT
TPS71728DCKR
TPS71728DCKT
TPS71728DSER
TPS71728DSET
TPS71729DCKT
TPS71730DCKR
TPS71730DCKT
TPS71733DCKR
TPS71733DCKT
TPS71733DRVR
TPS71733DRVT
TPS71733DSER
TPS71733DSET
TPS71745DSER
TPS71745DSET
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SC70
SON
SON
SC70
SC70
SC70
SC70
SON
SON
SC70
SC70
SC70
SC70
SC70
SON
SON
SON
SON
SON
SON
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DCK
DSE
DSE
DCK
DCK
DCK
DCK
DSE
DSE
DCK
DCK
DCK
DCK
DCK
DRV
DRV
DSE
DSE
DSE
DSE
5
5
5
5
5
5
5
5
6
6
5
5
5
5
6
6
5
5
5
5
5
6
6
6
6
6
6
3000
250
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 4
IMPORTANT NOTICE
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
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