TPS71733QDRVRQ1 [TI]
具有使能功能的汽车类、150mA、高 PSRR、低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;
| 型号： | TPS71733QDRVRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的汽车类、150mA、高 PSRR、低 IQ、低压降稳压器 | DRV | 6 | -40 to 125 信息通信管理 光电二极管 输出元件 稳压器 调节器 |
| 文件： | 总40页 (文件大小：2455K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS717-Q1
SLVSBM4C –SEPTEMBER 2012–REVISED JANUARY 2016
TPS717-Q1
Low-Noise, High-Bandwidth PSRR, Low-Dropout, 150-mA Linear Regulator
1 Features
3 Description
The TPS717-Q1 family of low-dropout (LDO), low-
power linear regulators offers very high power-supply
rejection (PSRR) and maintains very low 45-μA
ground current in an ultra-small, five-pin SOT
package. The family uses an advanced BiCMOS
process and a PMOSFET pass device to achieve fast
start-up, very low noise, excellent transient response,
and excellent PSRR performance. The TPS717-Q1 is
stable with a 1-μF ceramic output capacitor and uses
a precision voltage reference and feedback loop to
achieve a worst-case accuracy of 3% over all load,
line, process, and temperature variations. The device
family is fully specified from TJ, TA = –40°C to 125°C
and is offered in a small SOT (SC70-5) package, a
2-mm × 2-mm WSON-6 package with a thermal pad,
and a 1.5-mm × 1.5-mm WSON-6 package, which
are ideal for small form-factor portable equipment
(such as wireless handsets and PDAs). The TPS717-
Q1 family of LDOs is qualified for AEC-Q100 grade 1.
1
•
AEC-Q100 Qualified with the Following Results:
–
Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
–
–
Device HBM ESD Classification Level 2
Device HBM ESD Classification Level C4B
•
•
Input Voltage: 2.5 V to 6.5 V
Available in Multiple Output Versions:
–
–
Fixed Output with Voltages from 0.9 V to 5 V
Adjustable Output Voltage from 0.9 V to 6.2 V
•
Ultra-High PSRR:
–
70 dB at 1 kHz, 67 dB at 100 kHz, and 45 dB
at 1 MHz
•
•
•
•
Excellent Load and Line Transient Response
Very Low Dropout: 170 mV typical at 150 mA
Low Noise: 30 μVRMS typical (100 Hz to 100 kHz)
Small 5-pin SOT, 2-mm × 2-mm WSON-6, and
1.5-mm × 1.5-mm WSON-6 Packages
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
2.00 mm × 1.25 mm
2.00 mm × 2.00 mm
1.50 mm × 1.50 mm
SOT (5)
2 Applications
TPS717-Q1
WSON (6)
WSON (6)
•
•
•
•
•
•
PLLs
VCOs
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Camera Sensor Power
Microcontroller Power
Wireless LAN, Bluetooth®
ADAS and Infotainment Systems
Typical Application Circuit for Fixed-Voltage
Versions
PSRR vs Frequency
80
150 mA
VIN
VOUT
IN
OUT
TPS717-Q1
70
10 mA
1 mF
Ceramic
1 mF
Ceramic
60
50
40
30
20
10
0
EN
GND
NR
VEN
75 mA
0.01 mF
(Optional)
COUT = 1 mF
CNR = 10 nF
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Power-Supply Rejection Ratio (VIN - VOUT = 1 V)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS717-Q1
SLVSBM4C –SEPTEMBER 2012–REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Typical Characteristics.............................................. 8
Detailed Description ............................................ 13
7.1 Overview ................................................................. 13
7.2 Functional Block Diagrams ..................................... 13
7.3 Feature Description................................................. 14
7.4 Device Functional Modes........................................ 15
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 18
8.3 Do's and Don'ts ...................................................... 20
Power Supply Recommendations...................... 20
9
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 21
11 Device and Documentation Support ................. 23
11.1 Device Support .................................................... 23
11.2 Documentation Support ....................................... 23
11.3 Community Resources.......................................... 23
11.4 Trademarks........................................................... 24
11.5 Electrostatic Discharge Caution............................ 24
11.6 Glossary................................................................ 24
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2014) to Revision C
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Moved AEC-Q100 qualification bullet to first in Features list ................................................................................................. 1
Added TI Design .................................................................................................................................................................... 1
Changed TPS717xx-Q1 to TPS717-Q1 throughout document ............................................................................................. 1
Added footnote and CIN, R2, and CNR parameters to Recommended Operating Conditions table ....................................... 6
Changed VFB parameter in Electrical Characteristics table ................................................................................................... 7
Changed ΔVOUT(ΔIOUT) parameter typical specification in Electrical Characteristics table ..................................................... 7
Changed units of Vn parameter in Electrical Characteristics table......................................................................................... 7
Deleted UVLO parameter minimum specification from Electrical Characteristics table......................................................... 7
Changed TA to TJ in x-axis of Figure 7, Figure 10, and Figure 11 ......................................................................................... 9
Changed 40 mV/div to 40 mA/div in y-axis of Figure 28 ..................................................................................................... 12
Added last two sentences to Undervoltage Lockout (UVLO) section .................................................................................. 15
Changed last bulleted condition in Normal Operation section ............................................................................................ 15
Changed TJ specification in Normal mode row of Table 1 .................................................................................................. 16
Added last sentence to Input and Output Capacitor Requirements section......................................................................... 17
Clarified discussion of R2 in second paragraph of Design Considerations section ............................................................. 19
Changed first and third paragraphs of Do's and Don'ts section .......................................................................................... 20
2
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SLVSBM4C –SEPTEMBER 2012–REVISED JANUARY 2016
Changes from Revision A (August 2013) to Revision B
Page
•
•
•
Changed format to meet latest data sheet standards ............................................................................................................ 1
Changed Features list on front page: added, deleted, and reordered several bullets .......................................................... 1
Added ESD Ratings table and Feature Description, Device Functional Modes, Application and
Implementation, Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical,
Packaging, and Orderable Information sections..................................................................................................................... 1
•
•
•
•
•
•
•
•
•
•
•
Added several Applications list bullets on front page ............................................................................................................ 1
Deleted pinout drawings from front page .............................................................................................................................. 1
Changed pin descriptions throughout Pin Functions table..................................................................................................... 4
Added parametric measurement for ISHDN for DRV package ................................................................................................ 7
Changed Figure 1, Figure 2, Figure 3, and Figure 4: removed legend, added call-outs for clarity ....................................... 8
Changed title of Figure 15 and Figure 17............................................................................................................................... 9
Changed Overview section .................................................................................................................................................. 13
Corrected input and output symbols in operational amplifiers in Functional Block Diagrams ............................................. 13
Changed Undervoltage Lockout (UVLO) section text: reworded for clarity.......................................................................... 15
Deleted Reverse Current Protection section ....................................................................................................................... 17
Changed Equation 4 ............................................................................................................................................................ 19
Changes from Original (September 2012) to Revision A
Page
•
•
•
•
•
•
•
Changed front page to two-column format............................................................................................................................. 1
Added part number TPS71745-Q1......................................................................................................................................... 1
Changed C3B to C4B in Features list .................................................................................................................................... 1
Removed Ordering Information table ..................................................................................................................................... 4
Added Junction Temperature to Absolute Maximum Ratings table ....................................................................................... 5
Changed C3B to C4B in Absolute Maximum Ratings table. .................................................................................................. 5
Changed Application Information section to one-column format.......................................................................................... 18
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5 Pin Configuration and Functions
DCK Package
5-Pin SOT
Top View
DRV Package
2-mm × 2-mm, 6-Pin WSON
Top View
IN
GND
EN
1
2
3
5
4
OUT
OUT
NR/FB
GND
1
2
3
6
5
4
IN
N/C(1)
GND
NR/FB
EN
DSE Package
1.5-mm × 1.5-mm, 6-Pin WSON
Top View
OUT
GND
1
2
3
6
5
4
IN
N/C(1)
NR/FB
EN
(1) N/C = No connection
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DCK
DRV
DSE
(SOT)
(WSON)
(WSON)
Driving the enable pin (EN) above VEN(high) turns on the regulator. Driving
this pin below VEN(low) puts the regulator into standby mode, thereby
disabling the output and reducing operating current.
EN
FB
3
4
4
2
4
3
I
I
Adjustable voltage version only. The voltage at this pin is fed to the error
amplifier. A resistor divider from OUT to FB sets the output voltage when in
regulation.
GND
IN
2
1
3
6
2
6
—
I
Ground
Input to the device. A 0.1-μF to 1-μF capacitor is recommended for better
performance.
Not connected. This pin can be tied to ground to improve thermal
dissipation.
N/C
NR
—
4
5
2
1
5
3
1
—
—
O
Fixed voltage versions only. An external capacitor connected to this pin
bypasses noise generated by the internal band gap, thus lowering output
noise.
This pin is the regulated output voltage. A minimum capacitance of 1 μF is
required for stability from this pin to ground.
OUT
5
4
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SLVSBM4C –SEPTEMBER 2012–REVISED JANUARY 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted), all voltages are with respect to GND(1)
MIN
MAX
UNIT
V
VIN
–0.3
–0.3
–0.3
–0.3
–0.3
7
VFB
VNR
VEN
VOUT
IOUT
PDISS
TA
3.6
Voltage
3.6
VIN + 0.3 V(2)
7
Current
Internally limited
See Thermal Information table
A
Continuous total power dissipation
Ambient temperature
Operating junction temperature
Storage temperature
–40
–55
–55
125
150
150
°C
°C
°C
TJ
Tstg
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) VEN absolute maximum rating is VIN + 0.3 V or 7 V, whichever is greater.
6.2 ESD Ratings
VALUE
UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1)
TPS717-Q1 in DCK and DSE packages
±2000
V
All pins
±750
±750
Corner pins,
V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011 DCK (1, 3, 4, and 5)
V
V
Corner pins,
DSE (1, 3, 4, and 6)
±750
TPS717-Q1 in DRV package
All pins
±500
±750
V(ESD) Electrostatic discharge Charged device model (CDM), per AEC Q100-011
Corner pins (1, 3, 4, and 6)
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.5
0.9
0
NOM
MAX
6.5
5
UNIT
V
VIN
Input voltage
VOUT
IOUT
VEN
CIN
Output voltage
V
Output current
150
VIN
mA
V
Enable voltage
0
Input capacitor
1
320
10
µF
kΩ
nF
µF
°C
R2
Lower feedback resistor
Noise reduction capacitor
Output capacitor
Junction temperature
160
332
CNR
COUT
TJ
1(1)
–40
100
125
(1) Adjustable voltage version only. When using feedback resistors that are smaller than recommended, the minimum output capacitance
must be greater than 5 µF.
6.4 Thermal Information
TPS717-Q1
THERMAL METRIC(1)
DCK (SOT)
5 PINS
279.2
57.5
DRV (WSON) DSE (WSON)
UNIT
6 PINS
71.1
96.5
40.5
2.7
6 PINS
190.5
94.9
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
74.1
149.3
6.4
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.8
ψJB
73.1
40.9
10.7
152.8
n/a
RθJC(bot)
n/a
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6
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SLVSBM4C –SEPTEMBER 2012–REVISED JANUARY 2016
6.5 Electrical Characteristics
Over operating temperature range (TJ, TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT
=
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT
=
2.8 V. Typical values are at TA = 25°C.
PARAMETER
Input voltage range(1)
TEST CONDITIONS
MIN
2.5
TYP
MAX
UNIT
V
VIN
6.5
2%
VFB
Feedback pin voltage (TPS71701)
IOUT = 5 mA
TA = 25°C
–2%
0.9
0.793
V
TPS717-Q1
Output voltage range
5
VOUT
V
TPS71701-Q1
0.9
6.5 – VDO
Output accuracy (nominal)
±2.5
mV
Output accuracy
(VOUT < 1 V)
Over VIN, IOUT
,
VOUT + 0.5 V ≤ VIN ≤ 6.5 V,
0 mA ≤ IOUT ≤ 150 mA
–30
30
VOUT
temperature(2)
Output accuracy
(VOUT ≥ 1 V)
Over VIN, IOUT
,
VOUT + 0.5 V ≤ VIN ≤ 6.5 V,
0 mA ≤ IOUT ≤ 150 mA
–3%
3%
temperature(2)
VOUT(nom) + 0.5 V ≤ VIN ≤ 6.5 V,
IOUT = 5 mA
ΔVOUT(ΔVIN)
ΔVOUT(ΔIOUT)
VDO
Line regulation(1)
125
70
μV/V
μV/mA
mV
Load regulation
Dropout voltage(3)
0 mA ≤ IOUT ≤ 150 mA
IOUT = 150 mA
170
300
(VIN = VOUT(nom) – 0.1 V)
ILIM (fixed)
Output current limit (fixed output)
Output current limit (TPS71701-Q1)
VOUT = 0.9 × VOUT(nom)
VOUT = 0.9 × VOUT(nom)
IOUT = 0.1 mA
200
200
325
325
45
575
575
80
mA
mA
ILIM (adjustable)
IGND
Ground pin current
μA
IOUT = 150 mA
100
V
EN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V,
0.20
0.90
1.5
TA = –40°C to 125°C
VEN ≤ 0.4 V, 4.5 V ≤ VIN ≤ 6.5 V,
ISHDN
Shutdown current (IGND
)
μA
μA
dB
TA = –40°C to 125°C
V
EN ≤ 0.4 V, 2.5 V ≤ VIN < 4.5 V,
2
1
TA = –40°C to 125°C, DRV package
IFB
Feedback pin current (TPS71701-Q1)
Power-supply rejection ratio
0.02
70
f = 100 Hz
f = 1 kHz
70
VIN = 3.8 V,
VOUT = 2.8 V,
IOUT = 150 mA
PSRR
f = 10 kHz
67
f = 100 kHz
f = 1 MHz
67
45
CNR = none
CNR = 0.001 μF
CNR = 0.01 μF
CNR = 0.1 μF
95 × VOUT
25 × VOUT
12.5 × VOUT
11.5 × VOUT
BW = 100 Hz to
100 kHz,
VIN = 3.8 V,
VOUT = 2.8 V,
IOUT = 10 mA
Vn
Output noise voltage
μVRMS/V
0.9 V ≤ VOUT ≤ 1.6 V,
CNR = 0.001 μF
VOUT = 90%
0.700
0.160
VOUT(nom)
,
tSTR
Startup time
ms
V
RL = 19 Ω,
COUT = 1 μF
1.6 V < VOUT < VOUT(max)
CNR = 0.01 μF
,
VIN ≤ 5.5 V
1.2
1.25
0
6.5(4)
6.5
0.4
1
VEN(high)
Enable high (enabled)
5.5 V < VIN ≤ 6.5 V
VEN(low)
IEN(high)
Enable low (shutdown)
V
Enable pin current, enabled
EN = 6.5 V
0.02
160
140
2.45
150
μA
Shutdown, temperature increasing
Reset, temperature decreasing
VIN rising
Tsd
Thermal shutdown temperature
°C
Undervoltage lockout
Hysteresis
2.49
V
UVLO
VIN falling
mV
(1) Minimum VIN = VOUT + VDO or 2.5 V, whichever is greater.
(2) Does not include external resistor tolerances.
(3) VDO is not measured for devices with VOUT(nom) < 2.6 V because minimum VIN = 2.5 V.
(4) Maximum VEN(high) = VIN + 0.3 or 6.5 V, whichever is smaller.
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6.6 Typical Characteristics
Over operating temperature range (TJ, TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT
=
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT
=
2.8 V. Typical values are at TA = 25°C.
50
40
50
40
30
30
20
20
25°C
85°C
10
10
-40°C
0
0
25°C
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
-40°C
125°C
85°C
125°C
0
1
2
3
4
5
150
0
50
100
IOUT (mA)
IOUT (mA)
Figure 2. Load Regulation Under Light Loads
Figure 1. Load Regulation
1
3
2
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
TJ = -40°C
TJ = 25°C
TJ = 85°C
TJ = 125°C
0.8
0.6
0.4
1
0.2
0
0
-0.2
-0.4
-0.6
-0.8
-1
-1
-2
-3
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VIN (V)
VIN (V)
Figure 3. Line Regulation (IOUT = 5 mA)
Figure 4. Line Regulation (IOUT = 150 mA)
250
200
150
100
50
2
1.5
1
TA = 125°C
0.5
0
IOUT = 5 mA
TA = 85°C
-0.5
-1
IOUT = 100 mA
TA = 25°C
IOUT = 150 mA
TA = -40°C
-1.5
-2
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
50
100
150
TJ (°C)
IOUT (mA)
Figure 5. Output Voltage vs Temperature
Figure 6. Dropout Voltage vs Output Current
8
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Typical Characteristics (continued)
Over operating temperature range (TJ, TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT
=
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT
=
2.8 V. Typical values are at TA = 25°C.
150
120
90
60
30
0
300
250
200
150
100
50
VOUT = 2.8 V
IOUT = 150 mA
IOUT = 150 mA
IOUT = 100 mA
IOUT = 10 mA
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.5
3.5
4.5
5.5
6.5
TJ (°C)
VIN (V)
Figure 7. Dropout Voltage vs Temperature
Figure 8. Ground Pin Current vs Input Voltage
150
120
90
60
30
0
150
120
90
60
30
0
IOUT = 150 mA
IOUT = 100 mA
0
50
100
150
-40 -25 -10
5
20 35 50 65 80 95 110 125
TJ (°C)
IOUT (mA)
Figure 9. Ground Pin Current vs Output Current
Figure 10. Ground Pin Current vs Temperature (Enabled)
5
4
3
2
1
0
600
VEN = 0.4 V
TJ = -40°C
TJ = +25°C
500
400
300
200
TJ = +85°C
VIN = 4.5 V
VIN = 6.5 V
TJ = +125°C
VIN = 3.3 V
2.5
3.5
4.5
5.5
6.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
VIN (V)
TJ (°C)
Figure 11. Ground Pin Current vs Temperature (Disabled)
Figure 12. Current Limit vs Input Voltage
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Typical Characteristics (continued)
Over operating temperature range (TJ, TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT
=
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT
=
2.8 V. Typical values are at TA = 25°C.
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
10 mA
150 mA
75 mA
150 mA
10 mA
75 mA
COUT = 1 mF
COUT = 1 mF
CNR = 10 nF
CNR = 10 nF
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 13. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 1 V)
Figure 14. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 0.5 V)
80
80
10 mA
70
60
50
40
30
20
10
0
70
10 mA
60
75 mA
50
40
150 mA
150 mA
30
20
COUT = 10 mF
COUT = 1 mF
10
CNR = 10 nF
CNR = 10 nF
0
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 15. Power-Supply Ripple Rejection vs Frequency in
Dropout Conditions (VIN – VOUT = 0.25 V)
Figure 16. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 1 V)
80
80
70
60
50
40
30
20
10
0
70
10 mA
10 mA
60
50
40
150 mA
30
150 mA
20
COUT = 10 mF
COUT = 10 mF
10
CNR = 0 nF
CNR = 10 nF
0
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 17. Power-Supply Ripple Rejection vs Frequency in
Dropout Conditions (VIN – VOUT = 0.25 V)
Figure 18. Power-Supply Ripple Rejection vs Frequency
(VIN – VOUT = 1 V)
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Typical Characteristics (continued)
Over operating temperature range (TJ, TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT
=
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT
=
2.8 V. Typical values are at TA = 25°C.
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
1 kHz
1 kHz
10 kHz
1 MHz
10 kHz
1 MHz
100 kHz
100 kHz
IOUT = 10 mA
COUT = 1 mF
CNR = 10 nF
IOUT = 75 mA
COUT = 1 mF
CNR = 10 nF
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
V
IN - VOUT (V)
VIN - VOUT (V)
Figure 19. Power-Supply Ripple Rejection vs (VIN – VOUT
)
Figure 20. Power-Supply Ripple Rejection vs (VIN – VOUT)
16
80
1 kHz
100 kHz
COUT = 1 mF
CNR = 10 nF
IOUT = 150 mA
70
60
14
12
10
8
IOUT = 10 mA
10 kHz
50
40
1 MHz
30
6
20
4
IOUT = 150 mA
COUT = 1 mF
10
2
CNR = 10 nF
0
0
100
1k
10k
100k
0
0.5
1
1.5
2
2.5
3
3.5 4
Frequency (Hz)
VIN - VOUT (V)
Figure 22. Output Spectral Noise Density vs
Output Current
Figure 21. Power-Supply Ripple Rejection vs (VIN – VOUT
)
16
30
25
20
15
10
5
IOUT = 10 mA
IOUT = 10 mA
14
12
10
8
CNR = 10 nF
COUT = 1 mF
COUT = 10 mF
COUT = 1 mF
6
CNR = 10 nF
CNR = 100 nF
CNR = 0 nF
4
CNR = 1 nF
2
0
0
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 23. Output Spectral Noise Density vs
Output Capacitance
Figure 24. Output Spectral Noise Density vs
Noise Reduction
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Typical Characteristics (continued)
Over operating temperature range (TJ, TA = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.5 V, whichever is greater; IOUT
=
0.5 mA, VEN = VIN, COUT = 1 μF, CNR = 0.01 μF, unless otherwise noted. For the adjustable version (TPS71701-Q1), VOUT
=
2.8 V. Typical values are at TA = 25°C.
50
45
40
35
30
25
20
15
10
5
300
270
240
210
180
150
120
90
IOUT = 10 mA
VOUT = 2.8 V, CNR = 10 nF
VOUT = 1.3 V, CNR = 1 nF
COUT = 1 mF
60
30
0
0
0
1
10
100
0
5
10
15
20
25
CNR (nF)
COUT (mF)
Figure 25. Total Output Noise vs Noise Reduction
Figure 26. Total Output Noise vs Output Capacitance
VIN = 3.3 V
COUT = 1 mF
10 mV/div
VOUT
COUT = 1 mF
dVIN
dt
50 mV/div
VOUT
= 1 V/ms
6.5 V
150 mA
3.3 V
1 mA
1 V/div
VIN
40 mA/div
IOUT
100 ms/div
100 ms/div
Figure 27. Line Transient Response
Figure 28. Load Transient Response
VOUT
VIN
IOUT = 150 mA
COUT = 1 mF
6
5
VOUT
COUT = 10 mF
1 V/div
1 V/div
4
3
2
VOUT
1
0
6.5 V
VIN
0 V
4 V/div
50 ms/div
50 ms/div
Figure 30. Power-Up and Power-Down
Figure 29. Turn-On Response
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7 Detailed Description
7.1 Overview
The TPS717-Q1 family of low-dropout (LDO) regulators combines the high performance required by many RF
and precision analog applications with ultra-low current consumption. High PSRR is provided by a high-gain,
high-bandwidth error loop with good supply rejection with very low headroom (VIN – VOUT). Fixed voltage versions
provide a noise reduction pin to bypass noise generated by the band-gap reference and to improve PSRR. A
quick-start circuit fast-charges this capacitor at startup. The combination of high performance and low ground
current also make the TPS717-Q1 family of devices an excellent choice for battery-powered applications. All
versions have thermal and overcurrent protection. These devices are all also AEC-100 qualified for the grade 1
temperature range.
7.2 Functional Block Diagrams
IN
OUT
2.5 mA
Current
Limit
EN
Thermal
Shutdown
UVLO
Quick-Start
VOUT > 1.6 V
1.20-V
Band Gap
NR
360 kW
250 kW
0.8 V
VOUT £ 1.6 V
640 kW
GND
Figure 31. Fixed Voltage Versions
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Functional Block Diagrams (continued)
IN
OUT
Current
Limit
EN
Thermal
Shutdown
3.3 MW
UVLO
1.20-V
Band Gap
360 kW
FB
0.8 V
250 kW
640 kW
GND
Figure 32. Adjustable Voltage Version
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS717-Q1 internal current limit helps protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do
not operate the device in a current-limit state for extended periods of time.
The PMOS pass element in the TPS717-Q1 has a built-in body diode that conducts current when the voltage at
OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting may be appropriate.
7.3.2 Shutdown
The enable pin (EN) is active high and compatible with standard and low voltage, TTL-CMOS levels. When
shutdown capability is not required, EN can be connected to IN.
7.3.3 Startup and Noise Reduction Capacitor
Fixed voltage versions of the TPS717-Q1 use a quick-start circuit to fast-charge the noise reduction capacitor,
CNR, if present (see Figure 31). This circuit allows the combination of very low output noise and fast start-up
times. The NR pin is high impedance, so a low-leakage CNR capacitor must be used; most ceramic capacitors
are appropriate in this configuration.
Note that for fastest startup, apply VIN first, then the enable pin (EN) driven high. If EN is tied to IN, startup is
somewhat slower; see Figure 29 in the Typical Characteristics section. The quick-start switch is closed for
approximately 135 μs. To ensure that CNR is fully charged during the quick-start time, use a 0.01-μF or smaller
capacitor.
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Feature Description (continued)
For output voltages below 1.6 V, a voltage divider on the band-gap reference voltage is employed to optimize
output regulation performance for lower output voltages. This configuration results in an additional resistor in the
quick-start path and combined with the noise reduction capacitor (CNR) results in slower start-up times for output
voltages below 1.6 V.
Equation 1 approximates the start-up time as a function of CNR for output voltages below 1.6 V:
ms
tSTART = 160ms + (540
x CNRnF)ms
nF
(1)
7.3.4 Undervoltage Lockout (UVLO)
The TPS717-Q1 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is
operating properly. The UVLO circuit has a limited glitch immunity so undershoot transients are typically ignored
on the input if these transients are less than 5 μs in duration. Note that a slow VIN ramp can cause the output
voltage to rise when VIN is between 1.1 V to 1.4 V when at hot temperatures. When the input is lower than 1.4 V,
the UVLO circuit may not have enough headroom to keep the output fully off.
7.3.5 Minimum Load
The TPS717-Q1 is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at
very light output loads. The TPS717-Q1 employs an innovative low-current mode circuit to increase loop gain
under very light or no-load conditions, resulting in improved output voltage regulation performance down to zero
output current.
7.3.6 Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C the output circuitry is again enabled.
Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage because of
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 125°C maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C
above the maximum expected ambient condition of a particular application. This configuration produces a worst-
case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS717-Q1 is designed to protect against overload conditions. This
circuitry is not intended to replace proper heatsinking. Continuously running the TPS717-Q1 into thermal
shutdown degrades device reliability.
7.4 Device Functional Modes
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO
falling threshold.
•
•
The input voltage is greater than the nominal output voltage added to the dropout voltage.
The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased
below the enable falling threshold.
•
•
The output current is less than the current limit.
The device junction temperature is within the specified junction temperature range.
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Device Functional Modes (continued)
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout can result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
•
•
The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
•
The device junction temperature is greater than the thermal shutdown temperature.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
I OUT < ICL
—
TJ
Normal mode
Dropout mode
VIN > VOUT(nom) + VDO and VIN > UVLO
UVLO < VIN < VOUT(nom) + VDO
VEN > VEN(high)
VEN > VEN(high)
T J < 125°C
TJ < 165°C
Disabled mode
(any true condition disables the device)
VIN < UVLO – Vhys
VEN < VEN(low)
—
TJ > 165°C
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS717-Q1 belongs to a family of new generation LDO regulators that use innovative circuitry to achieve
ultra-wide bandwidth and high loop gain, resulting in extremely high PSRR at very low headroom (VIN – VOUT).
Fixed voltage versions provide a noise reduction pin to bypass noise generated by the band-gap reference and
to improve PSRR when a quick-start circuit fast-charges this capacitor. These features, combined with low noise,
enable, low ground pin current, and ultra-small packaging, make this part ideal for automotive applications. This
family of regulators offers sub-band-gap output voltages, current limit, and thermal protection, and is fully
specified from –40°C to 125°C.
8.1.1 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot or undershoot magnitude but
increases duration of the transient. The TPS717-Q1 has an ultra-wide loop bandwidth that allows it to respond
quickly to load transient events. As with any regulator, the loop bandwidth is finite and the initial transient voltage
peak is controlled by the sizing of the output capacitor. Typically, larger output capacitors reduce the peak and
also reduce the bandwidth of the LDO, thus slowing the response time.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF or
larger low equivalent series resistance (ESR) capacitor from IN to GND near the regulator. This capacitor
counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A
higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated or if the device is
located several inches from the power source. If source impedance is not sufficiently low, a 0.1-μF input
capacitor may be necessary to ensure stability.
The TPS717-Q1 is designed to be stable with ceramic output capacitors of values 1 μF or larger. The X5R- and
X7R-type capacitors are best because they have minimal variation in value and ESR over temperature. The
maximum ESR of the output capacitor must be less than 1 Ω. The minimum output capacitance is increased to
5 μF or larger if using an R2 value outside of the range of 160 kΩ to 320 kΩ.
8.1.3 Dropout Voltage
The TPS717-Q1 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDSon of the PMOS pass element. VDO scales approximately with output current because the
PMOS device functions as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded when (VIN – VOUT) approaches dropout.
This effect is illustrated in Figure 15 through Figure 17 in the Typical Characteristics section.
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Application Information (continued)
8.1.4 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of
the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2:
P = VIN - VOUT ìIOUT
D
(2)
8.1.5 Output Noise
In most LDOs, the band gap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the
TPS717-Q1, the band gap does not contribute significantly to noise. Instead, noise is dominated by the output
resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF (minimum)
noise reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce
noise. A parallel combination that gives 2.5 μA of divider current has the same noise performance as a fixed
voltage version.
Equation 3 approximates the total noise referred to the feedback point (FB pin) when CNR = 0.01 μF:
mVRMS
VN = 11.5
x VOUT
V
(3)
8.2 Typical Application
Figure 33 shows the basic circuit connections for the fixed voltage options. Figure 34 gives the connections for
the adjustable output version (TPS71701-Q1). Note that the NR pin is not available on the adjustable
version.
Optional 1-mF input
capacitor. May improve
source impedance, noise
or PSRR.
Optional 1-mF input
capacitor. May improve
source impedance, noise
or PSRR.
VIN
VIN
VOUT
VOUT
IN
OUT
FB
IN
OUT
TPS717-Q1
TPS71701-Q1
1 mF
Ceramic
R1
R2
1 mF
Ceramic
EN
GND
NR
EN
GND
VEN
VEN
Optional 0.01-mF bypass
capacitor to reduce
output noise and
increase PSRR.
Figure 33. Typical Application Circuit
(Fixed Voltage Versions)
Figure 34. Typical Application Circuit
(Adjustable Voltage Version)
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8.2.1 Design Requirements
Table 2 summarizes the design requirements for Figure 35.
Table 2. Design Requirements
PARAMETER
DESIGN REQUIREMENT
Input voltage
3.3 V, ±10%
2.8 V, ±5%
Output voltage
Output current
100 mA typical, 150 mA peak
Output voltage transient deviation
Maximum ambient temperature
5%
85°C
8.2.2 Detailed Design Procedure
8.2.2.1 Design Considerations
For the adjustable version (TPS71701-Q1), the NR pin is replaced with a feedback (FB) pin. The voltage on this
pin sets the output voltage and is determined by the values of R1 and R2. The values of R1 and R2 can be
calculated for any voltage using the formula given in Equation 4:
R1
1 +
x
VOUT = VREF
R2
(4)
The value of R2 directly affects the operation of the device and must be chosen in the range of approximately
160 kΩ to 332 kΩ. Sample resistor values for common output voltages are shown in Table 3.
Table 3. Sample 1% Resistor Values For Common
Output Voltages
VOUT
1
R1
R2
80.6 kΩ
162 kΩ
294 kΩ
402 kΩ
665 kΩ
1.02 MΩ
1.74 MΩ
324 kΩ
324 kΩ
332 kΩ
324 kΩ
316 kΩ
324 kΩ
332 kΩ
1.2
1.5
1.8
2.5
3.3
5
8.2.2.2 Powering a PLL Integrated on an SOC
Figure 35 shows the TPS71701-Q1 powering a phase-locked loop (PLL) that is integrated into a system-on-a-
chip (SOC).
3.3 V
2.8 V
PLL
IN
OUT
CIN
COUT
TPS71701-Q1
Buck Regulator
R1
R2
SOC
EN
FB
GND
Figure 35. Typical Application Circuit: PLL on an SOC
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8.2.2.3 Design Considerations
Use the input and output capacitors to ensure the voltage transient requirements. A 1-µF input and 1-µF output
capacitor are selected to maximize the capacitance and minimize capacitor size.
R2 is chosen to be 158 kΩ for optimal noise and PSRR, and by Equation 2, R1 is selected to be 402 kΩ. Both
R1 and R2 must be 1% tolerance resistors to meet the dc accuracy specification over line, load, and
temperature.
8.2.3 Application Curve
VIN = 3.3 V
COUT = 1 mF
50 mV/div
VOUT
150 mA
1 mA
40 mA/div
IOUT
100 ms/div
Figure 36. Load Transient Response
8.3 Do's and Don'ts
Do place at least one 1-µF ceramic capacitor as close as possible to both the input and output pins of the LDO.
Do not place the output capacitor more than 10 mm away from the regulator.
Do not place any components in the feedback loop except for the input, output, and feed-forward capacitor and
the feedback resistors.
Do not exceed the device absolute maximum ratings.
Do not float the enable (EN) pin.
9 Power Supply Recommendations
The TPS717-Q1 is designed to operate from an input voltage between 2.5 V and 6.5 V. The input supply must
provide adequate headroom for the device to operate in a normal mode of operation.
Connect a low output impedance power supply directly to the IN pin of the TPS717-Q1. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or
load transient events. If inductive impedances are unavoidable, use an input capacitor. To increase the overall
PSRR of the power solution, use a pi-filter before the input of the LDO or after the FB network of the LDO.
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10 Layout
10.1 Layout Guidelines
For best overall performance, place all circuit components on the same side of the circuit board and as near as
practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close to the GND pin as possible, connected by wide, component-side,
copper surface area. The use of vias and long traces to create LDO component connections is strongly
discouraged and negatively affects system performance. This grounding and layout scheme minimizes inductive
parasitics, and thereby reduces load-current transients, minimizes noise, and increases circuit stability. A ground
reference plane is also recommended and is either embedded in the printed circuit board (PCB) itself or located
on the bottom side of the PCB opposite the components. This reference plane serves to assure accuracy of the
output voltage, shields the LDO from noise, and functions similar to a thermal plane to spread (or sink) heat from
the LDO device when connected to the thermal pad. In most applications, this ground plane is necessary to meet
thermal requirements.
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor must connect directly to the
GND pin of the device.
10.2 Layout Examples
CNR
COUT
(1)
Thermal Pad
CIN
(1) Circles within thermal pad area indicate vias to other layers on the board.
Figure 37. Fixed Voltage Layout
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Layout Examples (continued)
R1
R2
COUT
(1)
Thermal Pad
CIN
(1) Circles within thermal pad area indicate vias to other layers on the board.
Figure 38. Adjustable Voltage Layout
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Module
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS717.
The TPS717xxEVM-134 evaluation module (and related user guide) can be requested at the Texas Instruments
website through the product folders or purchased directly from the TI eStore.
11.1.2 Device Nomenclature
Table 4. Device Nomenclature(1)
PRODUCT
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). An 01
denotes an adjustable voltage version.
TPS717xx(x)QYYYz-Q1
YYY is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
Q and -Q1 denote an automotive device that is qualified at grade 1.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
11.2 Documentation Support
11.2.1 Related Documentation
PMP10651 Test Results, TIDUAE4
TPS717xxEVM-134 Evaluation Module User Guide, SLVU148
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
23
Product Folder Links: TPS717-Q1
TPS717-Q1
SLVSBM4C –SEPTEMBER 2012–REVISED JANUARY 2016
www.ti.com
11.4 Trademarks
E2E is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
24
Submit Documentation Feedback
Copyright © 2012–2016, Texas Instruments Incorporated
Product Folder Links: TPS717-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Mar-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS71701QDRVRQ1
TPS71709QDRVRQ1
TPS71709QDSERQ1
TPS71712QDRVRQ1
TPS71715QDRVRQ1
TPS71718QDRVRQ1
TPS71725QDRVRQ1
TPS71728QDRVRQ1
TPS71730QDRVRQ1
TPS71733QDRVRQ1
TPS71745QDCKRQ1
TPS71745QDRVRQ1
TPS71750QDRVRQ1
TPS71750QDSERQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
SC70
DRV
DRV
DSE
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DCK
DRV
DRV
DSE
6
6
6
6
6
6
6
6
6
6
5
6
6
6
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
13B
SHW
BD
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SHX
SHY
SHZ
SIA
SIB
SIC
SID
SHF
SIE
SIF
WSON
WSON
WSON
AV
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Mar-2023
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS717-Q1 :
Catalog : TPS717
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS71701QDRVRQ1
TPS71709QDRVRQ1
TPS71709QDSERQ1
TPS71712QDRVRQ1
TPS71715QDRVRQ1
TPS71718QDRVRQ1
TPS71725QDRVRQ1
TPS71728QDRVRQ1
TPS71730QDRVRQ1
TPS71733QDRVRQ1
TPS71745QDCKRQ1
TPS71745QDRVRQ1
TPS71750QDRVRQ1
TPS71750QDSERQ1
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
SC70
DRV
DRV
DSE
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DCK
DRV
DRV
DSE
6
6
6
6
6
6
6
6
6
6
5
6
6
6
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
178.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
9.0
8.4
8.4
8.4
2.2
2.2
1.8
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.4
2.2
2.2
1.8
2.2
2.2
1.8
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.5
2.2
2.2
1.8
1.2
1.2
1.0
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q3
Q2
Q2
Q2
WSON
WSON
WSON
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jan-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS71701QDRVRQ1
TPS71709QDRVRQ1
TPS71709QDSERQ1
TPS71712QDRVRQ1
TPS71715QDRVRQ1
TPS71718QDRVRQ1
TPS71725QDRVRQ1
TPS71728QDRVRQ1
TPS71730QDRVRQ1
TPS71733QDRVRQ1
TPS71745QDCKRQ1
TPS71745QDRVRQ1
TPS71750QDRVRQ1
TPS71750QDSERQ1
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
WSON
SC70
DRV
DRV
DSE
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DCK
DRV
DRV
DSE
6
6
6
6
6
6
6
6
6
6
5
6
6
6
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
180.0
200.0
200.0
200.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
183.0
180.0
183.0
183.0
183.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
18.0
25.0
25.0
25.0
WSON
WSON
WSON
Pack Materials-Page 2
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006D
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A B
C
0.05
4225563/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225563/A 12/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4225563/A 12/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DSE0006A
WSON - 0.8 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.55
1.45
A
B
1.55
1.45
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
0.6
0.4
5X
3
4
2X 1
4X 0.5
6
1
0.3
6X
0.7
0.5
0.2
0.1
0.05
PIN 1 ID
C A B
C
4220552/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
(0.8)
5X (0.7)
1
6
6X (0.25)
SYMM
4X 0.5
4
3
(R0.05) TYP
(1.6)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
PADS 4-6
NON SOLDER MASK
DEFINED
PADS 1-3
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220552/A 04/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.7)
(0.8)
6X (0.25)
1
6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:40X
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated
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