TPS71830-30DRVT [TI]
DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO6, 2 X 2 MM, PLASTIC, SON-6;
| 型号： | TPS71830-30DRVT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PDSO6, 2 X 2 MM, PLASTIC, SON-6 信息通信管理 光电二极管 输出元件 调节器 |
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TPS718xx
TPS719xx
www.ti.com..................................................................................................................................................... SBVS088C–FEBRUARY 2007–REVISED MAY 2008
Dual, 200mA Output, Low Noise, High PSRR
Low-Dropout Linear Regulators
1
FEATURES
DESCRIPTION
23
•
Dual, 200mA High-Performance LDOs
The TPS718xx and TPS719xx families of low-dropout
(LDO) regulators offer a high power-supply rejection
ratio (PSRR), low noise, fast start-up, and excellent
line and load transient responses while consuming a
very low 90µA (typical) at no load ground current with
both LDOs enabled. The TPS719xx also provides an
active pulldown circuit to quickly discharge output
loads. The TPS718xx and TPS719xx are stable with
ceramic capacitors and use an advanced BiCMOS
fabrication process to yield a typical dropout voltage
of 230mV at 200mA output loads. The TPS718xx and
TPS719xx also use a precision voltage reference and
feedback loop to achieve 3% overall accuracy over all
load, line, process, and temperature variations. Both
families of devices are fully specified from TJ = –40°C
to +125°C and are offered in 2mm × 2mm SON-6 and
6-ball Wafer Chip-Scale (WCSP) packages that are
ideal for applications such as mobile handsets and
WLAN that require good thermal dissipation while
maintaining a very small footprint.
•
Low Total Quiescent Current: 90µA with Both
LDOs Enabled
•
•
•
•
•
Low Noise: 70µVRMS/V
Active Output Pulldown (TPS719xx)
Independent Enables for Each LDO
PSRR: 65dB at 1kHz, 45dB at 1MHz
Available in Multiple Fixed-Output Voltage
Combinations from 0.9V to 3.6V Using
Innovative Factory EEPROM Programming
•
•
Fast Start-Up Time: 160µs
Over-Current, Over-Temperature and
Under-Voltage Protection
•
•
•
Low Dropout: 230mV at 200mA
Stable with 1µF Ceramic Output Capacitor
Available in 2mm × 2mm SON-6 and 6-Ball
WCSP Packages
APPLICATIONS
•
•
•
•
Digital Cameras and Camera Modules
Cellular Camera and TV Phones
Wireless LAN, Bluetooth®
Handheld Products
TPS718xx, TPS719xx
YZC Package
TPS718Axx, TPS719Axx
YZC Package
2.7V to 6.5V
0.9V to 3.6V
TPS718xx, TPS719xx
DRV Package
VIN
VOUT
IN
OUT1
6-BALL WCSP
(Top View)
6-BALL WCSP
(Top View)
2mm x 2mm SON-6
(Top View)
1mF
1mF
TPS718xx
TPS719xx
C2
B2
A2
C1
B1
A1
A1
B1
C1
A2
B2
C2
On
EN1
EN2
OUT1
IN
1
2
3
6
5
4
EN1
GND
EN2
EN1
GND
EN2
OUT1
IN
EN1
GND
EN2
OUT1
IN
0.9V - 3.6V
1mF
Off
VOUT
OUT2
GND
On
OUT2
OUT2
OUT2
Off
GND
Typical Application Circuit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2008, Texas Instruments Incorporated
TPS718xx
TPS719xx
SBVS088C–FEBRUARY 2007–REVISED MAY 2008..................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)(3)
PRODUCT
VOUT
TPS718xx-yywwwz
TPS718Axx-yywwwz
TPS719xx-yywwwz
TPS719Axx-yywwwz
A denotes device with rotated pin 1 orientation of wafer-chipscale package.
XX is nominal output voltage for LDO1 (for example, 28 = 2.8V).
YY is nominal output voltage for LDO2.
WWW is package designator.
Z is tape and reel quantity (R = 3000, T = 250).
Examples: TPS71918–285DRVR
XX = 18 = 1.8V, YYY = 285 = 2.85V
XXX = 185 = 1.85V, YY = 33 = 3.3V
DRV = 2mm x 2mm SON package
Z = R = 3000 piece reel
TPS719185-33DRVR
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Both outputs are programmable from 0.9V to 3.6V in 50mV increments.
(3) Output voltages from 0.9V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating temperature range (unless otherwise noted). All voltages are with respect to GND.
PARAMETER
TPS718xx, TPS719xx
–0.3 to +7.0
UNIT
Input voltage range, VIN
V
V
V
Enable voltage range, VEN1 and VEN2
Output voltage range, VOUT
Peak output current
–0.3 to VIN + 0.3V
–0.3 to +7.0
Internally limited
Indefinite
Output short-circuit duration
Junction temperature range, TJ
Storage temperature range , TSTG
Total continuous power dissipation, PDISS
ESD rating, HBM
–55 to +150
–55 to +150
°C
°C
See Dissipation Ratings Table
2
kV
V
ESD rating, CDM
500
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATINGS
DERATING FACTOR
BOARD
High-K(1)
High-K(1)
PACKAGE
DRV
RθJC
RθJA
ABOVE TA = +25°C
TA < +25°C
1053mW
530mW
TA = +70°C
579mW
TA = +85°C
421mW
20°C/W
27°C/W
95°C/W
190°C/W
10.53mW/°C
YZC
5.3mW/°C
295mW
215mW
(1) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground
planes and 2-ounce copper traces on top and bottom of the board.
2
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TPS719xx
www.ti.com..................................................................................................................................................... SBVS088C–FEBRUARY 2007–REVISED MAY 2008
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater;
IOUT = 0.5mA, VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
Input voltage range(1)
TEST CONDITIONS
MIN
2.7
TYP
MAX
6.5
UNIT
V
VIN
VOUT1, VOUT2 Output voltage range
0.9
3.6
V
Nominal
TJ = +25°C
±2.5
mV
VOUT1, VOUT2 Output accuracy
Over VIN, IOUT
Temp
,
VOUT + 0.5V ≤ VIN ≤ 6.5V
0mA ≤ IOUT ≤ 200mA
–3.0
+3.0
%
VOUT(NOM) + 0.5V ≤ VIN ≤ 6.5V,
IOUT = 5mA
ΔVOUT/ ΔVIN Line regulation
ΔVOUT/ ΔIOUT Load regulation
130
75
µV/V
µV/mA
mV
0mA ≤ IOUT ≤ 200mA
Dropout voltage(2)
VDO
IOUT = 200mA
230
400
(VIN = VOUT(NOM) – 0.1V)
ICL
Output current limit (per output)
VOUT = 0.9 × VOUT(NOM)
IOUT1 = IOUT2 = 0.1mA
IOUT1 = IOUT2 = 200mA
240
340
90
575
160
mA
µA
µA
IGND
Ground pin current
250
V
EN1,2 ≤ 0.4V, 2.7V ≤ VIN < 4.5V,
0.3
1.8
3.0
µA
µA
TJ = –40°C to +85°C
ISHDN
Shutdown current (IGND)
VEN1,2 ≤ 0.4V, 4.5V ≤ VIN ≤ 6.5V,
TJ = –40°C to +85°C
f = 100Hz
63
63
72
58
44
dB
dB
dB
dB
dB
f = 1kHz
Power-supply rejection ratio
VIN = 3.8V, VOUT = 2.8V,
IOUT = 200mA
PSRR
f = 10kHz
f = 100kHz
f = 1MHz
Output noise voltage
BW = 100Hz to 100kHz
VN
70 × VOUT
160
µVRMS
µs
RL = 14Ω, VOUT = 2.8V,
COUT = 1.0µF
TSTR
TSHUT
Startup time(3)
Shutdown time(4) (5)
,
RL = ∞, COUT = 1.0µF,
VOUT = 2.8V
180
µs
(TPS719xx only)
V
IN ≤ 5.5V
1.2
6.5
6.5
V
V
Enable high (enabled)
(EN1 and EN2)
VEN(HI)
5.5V < VIN ≤ 6.5V
1.25
Enable low (shutdown)
(EN1 and EN2)
VEN(LO)
IEN
0
0.4
V
Enable pin current, enabled
(EN1 and EN2)
EN1 = EN2 = 6.5V
0.04
1.0
µA
Undervoltage lockout
Hysteresis
VIN rising
2.38
2.45
150
2.52
V
UVLO
VIN falling
mV
°C
°C
°C
Shutdown, temperature increasing
Reset, temperature decreasing
+160
+140
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
–40
+125
(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.
(2) VDO is not measured for devices with VOUT(NOM) < 2.8V because minimum VIN = 2.7V.
(3) Time from VEN = 1.25V to VOUT = 95% (VOUT(NOM)).
(4) Time from VEN = 0.4V to VOUT = 5% (VOUT(NOM)).
(5) See Shutdown section in the Applications Information for more details.
Copyright © 2007–2008, Texas Instruments Incorporated
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TPS719xx
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DEVICE INFORMATION
TPS719 only
60W
Bandgap
UVLO
Current
Limit
Thermal
Shutdown
2.5mA
OUT1
EN1
Enable and
Power
Control
Logic
EN2
OUT2
Thermal
Shutdown
2.5mA
Current
Limit
IN
UVLO
Bandgap
60W
TPS719 only
GND
Figure 1. Functional Block Diagram
4
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Product Folder Link(s): TPS718xx TPS719xx
TPS718xx
TPS719xx
www.ti.com..................................................................................................................................................... SBVS088C–FEBRUARY 2007–REVISED MAY 2008
DRV PACKAGE
SON-6
(TOP VIEW)
OUT1
IN
1
2
3
6
5
4
EN1
GND
EN2
GND
OUT2
YZC PACKAGE
6-BALL WCSP
(TOP VIEW)
C2
B2
A2
C1
B1
A1
EN1
OUT1
GND
EN2
IN
OUT2
TPS718xx
TPS719xx
YZC PACKAGE
6-BALL WCSP
(TOP VIEW)
A1
B1
C1
A2
B2
C2
EN1
GND
EN2
OUT1
IN
OUT2
TPS718Axx
TPS719Axx
PIN DESCRIPTIONS
TPS718xx
TPS719xx
TPS718Axx(1)
TPS719Axx(1)
YZC
NAME
OUT1
IN
DRV
YZC
C1
DESCRIPTION
Output of Regulator 1. A small ceramic capacitor (typically ≥ 1µF) is
needed from this pin to ground to assure stability.
1
2
3
A2
B2
C2
B1
Input supply to both regulators.
Output of Regulator 2. A small ceramic capacitor (typically ≥ 1µF) is
needed from this pin to ground to assure stability.
OUT2
A1
Enable pin for Regulator 2. Driving the Enable pin (EN2) high turns on
Regulator 2. Driving this pin low puts Regulator 2 into shutdown mode,
reducing operating current.
EN2
GND
EN1
4
5
6
A2
B2
C2
C1
B1
A1
Ground. DRV thermal pad should also be connected to ground.
Enable pin for Regulator 1. Driving the Enable pin (EN1) high turns on
Regulator 1. Driving this pin low puts Regulator 1 into shutdown mode,
reducing operating current.
(1) A option denotes devices with rotated Pin 1 orientation on Wafer Chipscale packages.
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TPS719xx
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TYPICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater;
IOUT = 0.5mA, VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
LINE REGULATION
LINE REGULATION
4
3
0
-1
-2
-3
-4
-5
TJ = +85°C
IOUT = 5mA
IOUT = 200mA
TJ = +125°C
2
TJ = +25°C
TJ = -40°C
1
TJ = +25°C
0
-1
-2
-3
-4
TJ = +85°C
TJ = -40°C
TJ = +125°C
2.5
3.5
4.5
5.5
6.5
2.5
3.5
4.5
5.5
6.5
VIN (V)
VIN (V)
Figure 2.
Figure 3.
LOAD REGULATION UNDER LIGHT LOADS
LOAD REGULATION
4
5
0
TJ = +85°C
TJ = +25°C
2
0
-5
-10
-15
-20
-25
-30
-35
-40
-2
-4
-6
-8
-10
TJ = -40°C
TJ = +125°C
TJ = +85°C
TJ = +25°C
TJ = -40°C
TJ = +125°C
0
1
2
3
4
5
0
50
100
IOUT (mA)
150
200
IOUT (mA)
Figure 4.
Figure 5.
OUTPUT VOLTAGE vs
TEMPERATURE
DROPOUT VOLTAGE vs
OUTPUT CURRENT
2.805
2.800
2.795
2.790
2.785
2.780
2.775
2.770
2.765
2.760
350
IOUT = 5mA
TJ = +125°C
TJ = +85°C
300
250
200
150
100
50
IOUT = 0.1mA
IOUT = 200mA
TJ = +25°C
TJ = -40°C
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
50
100
150
200
TJ (°C)
IOUT (mA)
Figure 6.
Figure 7.
6
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater;
IOUT = 0.5mA, VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
GROUND PIN CURRENT vs
OUTPUT CURRENT
GROUND PIN CURRENT vs
INPUT VOLTAGE
200
160
120
80
60
50
40
30
20
10
0
TJ = +125°C
IOUT = 1mA
TJ = +25°C
TJ = +85°C
TJ = -40°C
40
0
0
50
100
150
200
2.5
3.5
4.5
5.5
6.5
IOUT (mA)
VIN (V)
Figure 8.
Figure 9.
GROUND PIN CURRENT vs
TEMPERATURE (BOTH LDOs ENABLED)
SHUTDOWN CURRENT vs
INPUT VOLTAGE
140
120
100
80
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
IOUT = 0mA
TJ = +125°C
TJ = -40°C
60
TJ = +85°C
40
TJ = +25°C
20
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
2.5
3.5
4.5
5.5
6.5
TJ (°C)
VIN (V)
Figure 10.
Figure 11.
CURRENT LIMIT vs
INPUT VOLTAGE
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN – VOUT = 0.5V)
90
450
100mA
80
70
60
50
40
30
20
10
0
425
400
375
350
325
300
275
250
5mA
200mA
TJ = +125°C
TJ = +85°C
TJ = +25°C
TJ = -40°C
10
100
1k
10k
100k
1M
10M
2.5
3.5
4.5
5.5
6.5
Frequency (Hz)
VIN (V)
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater;
IOUT = 0.5mA, VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
POWER-SUPPLY RIPPLE REJECTION vs
FREQUENCY (VIN – VOUT = 1V)
POWER-SUPPLY RIPPLE REJECTION vs
INPUT VOLTAGE
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
100mA
1kHz
5mA
10kHz
100kHz
1MHz
200mA
VOUT = 2.80V
IOUT = 5mA
10
100
1k
10k
100k
1M
10M
3.0
3.2
3.4
3.6
3.8
4.0
VIN (V)
Frequency (Hz)
Figure 14.
Figure 15.
POWER-SUPPLY RIPPLE REJECTION vs
INPUT VOLTAGE
OUTPUT SPECTRAL NOISE DENSITY vs
FREQUENCY
80
70
60
50
40
30
20
10
0
10
1
VOUT = 2.80V
10kHz
1kHz
100kHz
1MHz
0.1
0.01
VOUT = 2.80V
IOUT = 200mA
100
1k
10k
100k
3.0
3.2
3.4
3.6
3.8
4.0
VIN (V)
Frequency (Hz)
Figure 16.
Figure 17.
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
IOUTmin = 3mA
dVIN
6.5V
dt
dIOUT
dt
= 1V/ms
= 200mA/ms
250mA/div
10mV/div
IOUT1
3.3V
1V/div
VIN
VOUT1
VOUT1
10mV/div
10mV/div
VOUT2
VOUT2
10mV/div
10ms/div
20ms/div
Figure 18.
Figure 19.
8
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.5V or 2.7V, whichever is greater;
IOUT = 0.5mA, VEN1 = VEN2 = VIN, COUT = 1.0µF, unless otherwise noted. Typical values are at TJ = +25°C.
TPS719 ENABLE RESPONSE
POWER-UP/POWER-DOWN
IOUT = 200mA
VIN
6.5V
0V
EN1, EN2
4V/div
1V/div
VOUT
VOUT1
VOUT2
1V/div
1V/div
40ms/div
400ms/div
Figure 20.
Figure 21.
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APPLICATION INFORMATION
The TPS718xx/TPS719xx belong to a family of new
Board Layout Recommendations to Improve
generation LDO regulators that use innovative
PSRR and Noise Performance
circuitry to achieve ultra-wide bandwidth and high
loop gain, resulting in extremely high PSRR (up to
1MHz) at very low headroom (VIN – VOUT). These
features, combined with low noise, two independent
enables, low ground pin current and ultra-small
packaging, make this part ideal for portable
applications. This family of regulators offer
sub-bandgap output voltages, current limit and
thermal protection, and is fully specified from –40°C
to +125°C.
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the output capacitor should
connect directly to the GND pin of the device. High
ESR capacitors may degrade PSRR.
Internal Current Limit
Figure 22 shows the basic circuit connections.
The TPS718xx/TPS719xx internal current limits help
protect the regulator during fault conditions. During
current limit, the output sources a fixed amount of
current that is largely independent of output voltage.
For reliable operation, the device should not be
operated in a current limit state for extended periods
of time.
2.7V - 6.5V
0.9V - 3.6V
1mF
VIN
VOUT
IN
OUT1
TPS718xx
TPS719xx
1mF
On
EN1
0.9V - 3.6V
1mF
Off
VOUT
OUT2
The PMOS pass element in the TPS718xx/TPS719xx
has a built-in body diode that conducts current when
the voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting to 5% of
rated output current may be appropriate.
On
EN2
Off
GND
Figure 22. Typical Application Circuit
Shutdown
Input and Output Capacitor Requirements
The enable pin (EN) is active high and is compatible
with standard and low voltage, TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN. The TPS719 with internal active
output pulldown circuitry discharges the output with a
time constant (t) of:
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1.0µF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input
sources and improves transient response, noise
60 ´ RL
rejection, and ripple rejection.
A
higher-value
´ COUT
t = 3
60 + RL
capacitor may be necessary if large, fast rise-time
load transients are anticipated or if the device is
located close to the power source. If source
impedance is not sufficiently low, a 0.1µF input
capacitor may be necessary to ensure stability.
with:
RL = output load resistance
COUT = output capacitance
The TPS718xx/TPS719xx are designed to be stable
with standard ceramic capacitors of values 1.0µF or
larger at the output. X5R- and X7R-type capacitors
are best because they have minimal variation in value
and ESR over temperature. Maximum ESR should be
<1.0Ω.
Dropout Voltage
The TPS718xx/TPS719xx use
transistor to achieve low dropout. When (VIN – VOUT
a
PMOS pass
)
is less than the dropout voltage (VDO), the PMOS
pass device is in its linear region of operation and the
input-to-output resistance is the RDS(ON) of the PMOS
pass element. VDO approximately scales with output
current because the PMOS device behaves like a
resistor in dropout.
10
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS718xx TPS719xx
TPS718xx
TPS719xx
www.ti.com..................................................................................................................................................... SBVS088C–FEBRUARY 2007–REVISED MAY 2008
As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in Figure 13 and
Figure 14 in the Typical Characteristics section.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
Transient Response
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This
As with any regulator, increasing the size of the
output capacitor will reduce over/undershoot
magnitude but increase duration of the transient
response.
configuration produces
temperature of +125°C at the highest expected
a
worst-case junction
Undervoltage Lock-Out (UVLO)
ambient temperature and worst-case load.
The TPS718xx/TPS719xx utilize an undervoltage
lock-out circuit to keep the output shut off until
internal circuitry is operating properly. The UVLO
circuit has a de-glitch feature so that it typically
ignores undershoot transients on the input if they are
less than 50µs duration. On the TPS719xx, the active
pulldown discharges VOUT when the device is in
UVLO off condition. However, the input voltage needs
to be greater than 0.8V for active pulldown to work.
The
internal
protection
circuitry
of
the
TPS718xx/TPS719xx has been designed to protect
against overload conditions. It was not intended to
replace proper heatsinking. Continuously running the
TPS718xx/TPS719xx
into
thermal
shutdown
degrades device reliability.
Power Dissipation
The ability to remove heat from the die is different for
each package type, presenting different
Minimum Load
The TPS718xx/TPS719xx are stable with no output
load. Traditional PMOS LDO regulators suffer from
lower loop gain at very light output loads. The
considerations in the printed circuit board (PCB)
layout. The PCB area around the device that is free
of other components moves the heat from the device
to the ambient air. Performance data for JEDEC low-
and high-K boards are given in the Dissipation
Ratings table. Using heavier copper increases the
effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating
layers also improves the heatsink effectiveness.
TPS718xx/TPS719xx
employ
an
innovative,
low-current mode circuit under very light or no-load
conditions, resulting in improved output voltage
regulation performance down to zero output current.
THERMAL INFORMATION
Thermal Protection
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT), as
shown in Equation 1:
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage due to
overheating.
PD = (VIN - VOUT) x IOUT
(1)
Package Mounting
Solder pad footprint recommendations for the
TPS718xx/TPS719xxx are available from the Texas
Instruments web site at www.ti.com.
Copyright © 2007–2008, Texas Instruments Incorporated
Submit Documentation Feedback
11
Product Folder Link(s): TPS718xx TPS719xx
TPS718xx
TPS719xx
SBVS088C–FEBRUARY 2007–REVISED MAY 2008..................................................................................................................................................... www.ti.com
1,690
1,590
1,088
0,988
Figure 23. YZC Wafer Chip-Scale Package Dimensions (in mm)
12
Submit Documentation Feedback
Copyright © 2007–2008, Texas Instruments Incorporated
Product Folder Link(s): TPS718xx TPS719xx
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS71812-33DRVR
TPS71812-33DRVRG4
TPS71812-33DRVT
TPS71812-33DRVTG4
TPS71818-27YZCR
TPS71818-27YZCT
TPS71818-33DRVR
TPS71818-33DRVT
TPS71825-12DRVR
TPS71825-12DRVT
TPS71828-28YZCR
TPS71828-28YZCT
TPS71828-30DRVR
TPS71828-30DRVRG4
TPS71828-30DRVT
TPS71828-30DRVTG4
TPS71913-28DRVR
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SON
SON
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
BVC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DRV
DRV
DRV
YZC
YZC
DRV
DRV
DRV
DRV
YZC
YZC
DRV
DRV
DRV
DRV
DRV
3000
250
Green (RoHS
& no Sb/Br)
BVC
BVC
BVC
FX
SON
Green (RoHS
& no Sb/Br)
SON
250
Green (RoHS
& no Sb/Br)
DSBGA
DSBGA
SON
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SNAGCU
FX
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
SNAGCU
OEI
OEI
BVO
BVO
FZ
SON
Green (RoHS
& no Sb/Br)
SON
3000
250
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
DSBGA
DSBGA
SON
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SNAGCU
FZ
3000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
BVX
BVX
BVX
BVX
BWP
SON
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
SON
250
Green (RoHS
& no Sb/Br)
SON
3000
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS71913-28DRVRG4
TPS71913-28DRVT
TPS71913-28DRVTG4
TPS71918-12DRVR
TPS71918-12DRVRG4
TPS71918-12DRVT
TPS71918-12DRVTG4
TPS71918-28DRVR
TPS71918-28DRVT
TPS71921-22DRVR
TPS71921-22DRVT
TPS71926-15DRVR
TPS71926-15DRVRG4
TPS71926-15DRVT
TPS71926-15DRVTG4
TPS71928-28DRVR
TPS71928-28DRVRG4
TPS71928-28DRVT
ACTIVE
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
BWP
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
250
250
Green (RoHS
& no Sb/Br)
BWP
BWP
BWW
BWW
BWW
BWW
ODQ
ODQ
OBW
OBW
CAJ
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CAJ
Green (RoHS
& no Sb/Br)
CAJ
250
Green (RoHS
& no Sb/Br)
CAJ
3000
3000
250
Green (RoHS
& no Sb/Br)
CAK
CAK
CAK
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS71928-28DRVTG4
ACTIVE
SON
DRV
6
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CAK
TPS719285-285DRVR
TPS719285-285DRVT
ACTIVE
ACTIVE
SON
SON
DRV
DRV
6
6
3000
250
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
OAU
OAU
TPS719285-285DSET
TPS71933-28DRVR
PREVIEW
ACTIVE
SON
SON
DRV
DRV
6
6
Call TI
Call TI
-40 to 125
-40 to 125
3000
3000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CAH
CAH
CAH
CAH
BWL
BWL
BWL
BWL
CVZ
CVZ
TPS71933-28DRVRG4
TPS71933-28DRVT
TPS71933-28DRVTG4
TPS71933-33DRVR
TPS71933-33DRVRG4
TPS71933-33DRVT
TPS71933-33DRVTG4
TPS71936-315DRVR
TPS71936-315DRVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
250
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS71812-33DRVR
TPS71812-33DRVT
TPS71818-33DRVR
TPS71818-33DRVT
TPS71825-12DRVR
TPS71825-12DRVT
TPS71828-30DRVR
TPS71828-30DRVT
TPS71913-28DRVR
TPS71913-28DRVT
TPS71918-12DRVR
TPS71918-12DRVT
TPS71918-28DRVR
TPS71918-28DRVT
TPS71921-22DRVR
TPS71921-22DRVT
TPS71926-15DRVR
TPS71926-15DRVT
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
3000
250
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2012
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS71928-28DRVR
TPS71928-28DRVT
TPS71933-28DRVR
TPS71933-28DRVT
TPS71933-33DRVR
TPS71933-33DRVT
TPS71936-315DRVR
TPS71936-315DRVT
SON
SON
SON
SON
SON
SON
SON
SON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
3000
250
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q2
Q2
3000
250
3000
250
3000
250
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS71812-33DRVR
TPS71812-33DRVT
TPS71818-33DRVR
TPS71818-33DRVT
TPS71825-12DRVR
TPS71825-12DRVT
TPS71828-30DRVR
TPS71828-30DRVT
TPS71913-28DRVR
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
3000
250
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Sep-2012
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS71913-28DRVT
TPS71918-12DRVR
TPS71918-12DRVT
TPS71918-28DRVR
TPS71918-28DRVT
TPS71921-22DRVR
TPS71921-22DRVT
TPS71926-15DRVR
TPS71926-15DRVT
TPS71928-28DRVR
TPS71928-28DRVT
TPS71933-28DRVR
TPS71933-28DRVT
TPS71933-33DRVR
TPS71933-33DRVT
TPS71936-315DRVR
TPS71936-315DRVT
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
SON
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
DRV
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
250
3000
250
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 3
D: Max = 1.67 mm, Min =1.609 mm
E: Max = 1.068 mm, Min =1.007 mm
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