TPS720285QDRVRQ1 [TI]

具有使能功能的汽车类、350mA、低输入电压 (1.1V)、高 PSRR、低 IQ、低压降稳压器 | DRV | 6 | -40 to 125;


型号：	TPS720285QDRVRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有使能功能的汽车类、350mA、低输入电压 (1.1V)、高 PSRR、低 IQ、低压降稳压器 \| DRV \| 6 \| -40 to 125 信息通信管理光电二极管输出元件稳压器调节器
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中文：	中文翻译
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TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

TPS720-Q1

具有偏置引脚的 350mA、超低 V_IN、RF 低压降线性稳压器

1 特性

3 说明

•

适用于汽车电子应用

具有符合 AEC-Q100 标准的下列结果：

TPS720-Q1 系列双轨、低压降线性稳压器 (LDO) 具有

出色的交流性能（PSRR，负载和线路瞬态响应），静

态流耗非常低，低至 38μA。

•

–

器件温度 1 级：-40℃ 至 +125℃ 的环境运行温

度范围

为 LDO 控制电路供电的 V_BIAS轨消耗极低的电流（与

LDO 静态电流差不多），并且可以连接至任何超过输

出电压 1.4V 及以上的电源。主要电源路径为 V_IN，且

可低于 V_BIAS；此路径可低至 V_OUT+ V_DO，有助于提高

许多功耗敏感型应用解决方案的效率。例如，V_IN可作

为高效的直流 - 直流降压稳压器的输出。

器件人体放电模式 (HBM) 静电放电 (ESD) 分类

等级 H2

器件组件充电模式 (CDM) ESD 分类等级 C6

•

输入电压范围：1.1V 至 4.5V

输出电压范围：0.9V 至 3.6V

高性能 LDO：350mA

TPS720-Q1 支持一种新特性，当 IN 引脚保持悬空

时，LDO 的输出稳定在轻负载以下。这种情况下的轻

负载驱动电流来源于 V_BIAS。此特性对于节能应用特别

有效，在这些应用中，禁止直流-直流转换器连接至 IN

引脚，但仍需要 LDO 将电压稳定至轻负载。

低静态电流：38μA

绝佳的负载瞬态响应：

±15mV（当 1μs 内 I_LOAD= 0mA 跳至 350 mA 时）

•

低噪声：48μV_RMS（10Hz 至 100kHz）

80dB V_INPSRR（10Hz 至 10kHz）

70dB V_BIASPSRR (10Hz 至 10kHz)

快速启动时间：140μs

TPS720-Q1 与陶瓷电容器搭配使用时可保持稳定，并

且该器件使用先进的 BICMOS 制造工艺，能够在

350mA 输出负载电流时产生仅 110mV 的压降。

TPS720-Q1 搭配 2.2μF 输出电容时，可实现 V_OUT单

调升高（过冲限制为 3%）的同时 V_IN浪涌电流限制为

内置软启动，单调 V_OUT升高并且启动电流限制在

100mA + I_LOAD

•

过流和热保护

低压降：110mV（当 I_LOAD= 350mA 时）

与 2.2μF 输出电容一起工作时保持稳定

封装：2.00mm × 2.00mm、６引脚 WSON

100mA + I_LOAD

。

TPS720-Q1 使用一个高精度电压基准和反馈环路来实

现负载、线路、过程和温度变化范围上 2% 的总精

度。TPS720-Q1 采用 6 引脚 WSON 封装。该系列器

件的额定工作温度范围为 T_J= –40°C 至 +125°C。

2 应用

•

摄像机模块

平板显示 (FPD) 链路电源

车用信息娱乐系统

器件信息⁽¹⁾

器件型号

TPS720-Q1

封装

WSON (6)

封装尺寸（标称值）

USB 网络集线器 (HUB) 电源

2.00mm x 2.00mm

简化电路原理图

(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。

V_BATT

C_BIAS

BIAS

2.3 V

1.8 V

Standalone

V_CORE

OUT

DC-DC

Converter

or PMU

TPS720-Q1

C_IN

C_OUT

GND

V_EN

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SBVS278

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 3

6.1 Absolute Maximum Ratings ...................................... 3

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 6

6.7 Typical Characteristics.............................................. 7

Detailed Description ............................................ 11

7.1 Overview ................................................................. 11

7.2 Functional Block Diagram ....................................... 11

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 12

Application and Implementation ........................ 13

8.1 Application Information............................................ 13

8.2 Typical Application .................................................. 14

Power Supply Recommendations...................... 16

10 Layout................................................................... 16

10.1 Layout Guidelines ................................................. 16

10.2 Layout Example .................................................... 16

10.3 Thermal Considerations........................................ 17

10.4 Power Dissipation ................................................. 17

11 器件和文档支持 ..................................................... 18

11.1 器件支持................................................................ 18

11.2 文档支持................................................................ 18

11.3 接收文档更新通知 ................................................. 18

11.4 社区资源................................................................ 18

11.5 商标....................................................................... 18

11.6 静电放电警告......................................................... 19

11.7 Glossary................................................................ 19

12 机械、封装和可订购信息....................................... 19

4 修订历史记录

Changes from Original (February 2016) to Revision A

Page

•

已更改特性部分中的输出电压范围要点从“0.9V 至 3.0V”更改为“0.9V 至 3.6V” ..................................................................... 1

Changed maximum value of "output voltage" parameter from 3.0 V to 3.6 V in Recommended Operating Conditions

table........................................................................................................................................................................................ 4

•

Reformatted Thermal Information table note ......................................................................................................................... 4

Changed maximum value of output voltage parameter from 3.0 V to 3.6 V in Electrical Characteristics table .................... 5

已更改器件命名规则部分 ..................................................................................................................................................... 18

已更改相关文档部分的格式.................................................................................................................................................. 18

已添加接收文档更新通知部分 ............................................................................................................................................. 18

TPS720-Q1

www.ti.com.cn

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

5 Pin Configuration and Functions

DRV Package

6-Pin WSON With Exposed Thermal Pad

Top View

OUT

Thermal

(1)

Pad

GND

BIAS

(1) TI recommends connecting the WSON (DRV) package thermal pad to ground.

Pin Functions

I/O

DESCRIPTION

NAME

OUT

NO.

Output pin. A 2.2-μF ceramic capacitor is connected from this pin to ground for stability and to provide load

transients; see Input and Output Capacitor Requirements

—

No connection.

Enable pin. A logic high signal on this pin turns the device on and regulates the voltage from IN to OUT.

A logic low on this pin turns the device off.

Bias supply pin. For better transient performance, TI recommends bypassing this input with a ceramic

capacitor to ground; see Input and Output Capacitor Requirements

BIAS

GND

—

Ground pin.

Input pin. This pin can be a maximum of 4.5 V; V_INmust not exceed V_BIAS. Bypass this input with a ceramic

capacitor to ground; see Input and Output Capacitor Requirements.

6 Specifications

6.1 Absolute Maximum Ratings

at T_J= –40°C to +125°C (unless otherwise noted); all voltages are with respect to GND⁽¹⁾

MIN

MAX

UNIT

(2)

V_IN

Input voltage (steady-state)

Peak transient input

–0.3

V_BIASor 5⁽³⁾

(4)

V_{IN_PEAK}

V_BIAS

V_EN

5.5

Bias voltage

–0.3

Enable voltage

V_OUT

I_OUT

Output voltage

Peak output current

Internally limited

Output short-circuit duration

Total continuous power dissipation

Operating junction temperature

Storage temperature

Indefinite

P_DISS

T_J

See Thermal Information

–55

125

150

°C

T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) To ensure proper device operation, V_INmust be less than or equal to V_BIASunder all conditions.

(3) Whichever is less.

(4) For durations no longer than 1 ms each, for a total of no more than 1000 occurrences over the lifetime of the device.

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

±2000

±500

±100

V_(ESD)

Electrostatic discharge

Machine model (MM)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted).

MIN

NOM

MAX

V_BIASor 4.5⁽¹⁾

UNIT

V_IN

Input voltage (steady-state)

Bias voltage

1.1

V_BIAS

V_OUT

I_OUT

V_EN

2.6 or V_OUT+ 1.4⁽²⁾

5.5

3.6

350

5.5

Output voltage

0.9

Peak output current

Enable voltage

C_IN

Input capacitance

Bias capacitance

Output capacitance

µF

C_BIAS

C_OUT

0.1

(3)

2.2

(1) Whichever is less.

(2) Whichever is greater.

(3) Maximum ESR must be less than 250 mΩ.

6.4 Thermal Information

TPS720-Q1

THERMAL METRIC⁽¹⁾

DRV (WSON)

6 PINS

66.5

UNIT

R_θJA

Junction-to-ambient thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

86.2

36.1

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

1.7

ψ_JB

36.6

R_θJC(bot)

7.4

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics (SPRA953).

TPS720-Q1

www.ti.com.cn

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

6.5 Electrical Characteristics

over operating temperature range (T_J= –40°C to +125°C), V_BIAS= (V_OUT+ 1.4 V ) or 2.6 V (whichever is greater), V_IN≥ V_OUT

+ 0.5 V, I_OUT= 1 mA, V_EN= 1.1 V, and C_OUT= 2.2 μF (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_BIASor

4.5⁽²⁾

V_IN

Input voltage

1.1⁽¹⁾

V_BIAS

Bias voltage

Output voltage⁽⁴⁾

2.6

0.9

5.5

3.6

V_OUT+ 1.4 V ≤ V_BIAS≤ 5.5 V,

V_OUT+ 0.5 V ≤ V_IN≤ 4.5 V,

0 mA ≤ I_OUT≤ 350 mA

Over V_BIAS, V_IN, I_OUT

T_J= –40°C to +125°C

–2%

–25

(3)

V_OUT

Output

accuracy

V_OUT+ 1.4 V ≤ V_BIAS≤ 5.5 V,

V_OUT+ 0.5 V ≤ V_IN≤ 4.5 V,

0 mA ≤ I_OUT≤ 350 mA, V_OUT< 1.2 V

Over V_BIAS, V_IN, I_OUT

T_J= –40°C to +125°C

V_OUT+ 1.4 V ≤ V_BIAS≤ 5.5 V,

0 μA ≤ I_OUT≤ 500 μA

V_INfloating

±1%

ΔV_OUT/ΔV_IN

V_INline regulation

V_IN= (V_OUT+ 0.5 V) to 4.5 V, I_OUT= 1 mA

μV/V

V_BIAS= (V_OUT+ 1.4 V) or 2.6 V (whichever is

greater) to 5.5 V, I_OUT= 1 mA

ΔV_OUT/ΔV_BIASV_BIASline regulation

V_INline transient

V_BIASline transient

ΔV_IN= 400 mV, t_RISE= t_FALL= 1 μs

±200

±0.8

–15

μV

ΔV_BIAS= 600 mV, t_RISE= t_FALL= 1 μs

0 mA ≤ I_OUT≤ 350 mA (no load to full load)

0 mA ≤ I_OUT≤ 350 mA, t_RISE= t_FALL= 1 μs

ΔV_OUT/ΔI_OUTLoad regulation

Load transient

μV/mA

±15

V_IN= V_OUT(NOM)– 0.1 V,

(V_BIAS– V_OUT(NOM)) = 1.4 V,

I_OUT= 350 mA

V_{DO_IN}

V_INdropout voltage⁽⁵⁾

110

200

V_{DO_BIAS}

I_CL

V_BIASdropout voltage⁽⁶⁾

Output current limit

V_IN= V_OUT(NOM)+ 0.3 V, I_OUT= 350 mA

V_OUT= 0.9 × V_OUT(NOM)

I_OUT= 100 μA

1.09

600

0.5

1.4

420

800

I_GND

Ground pin current

μA

I_OUT= 0 mA to 350 mA

V_EN≤ 0.4 V

I_SHDN

Shutdown current (I_GND

)

2.5

f = 10 Hz

f = 100 Hz

V_IN– V_OUT≥ 0.5 V,

V_BIAS= V_OUT+ 1.4 V,

I_OUT= 350 mA

f = 1 kHz

PSRR

V_INpower-supply rejection ratio

f = 10 kHz

f = 100 kHz

f = 1 MHz

f = 10 Hz

f = 100 Hz

V_IN– V_OUT≥ 0.5 V,

f = 1 kHz

V_BIASpower-supply rejection ratio V_BIAS= V_OUT+ 1.4 V,

I_OUT= 350 mA

f = 10 kHz

f = 100 kHz

f = 1 MHz

Bandwidth = 10 Hz to 100 kHz, V_BIAS≥ 2.6 V,

V_IN= V_OUT+ 0.5 V

V_N

Output noise voltage

Inrush current on V_IN

μV_RMS

V_BIAS= (V_OUT+1.4 V) or 2.6 V (whichever is

greater), V_IN= V_OUT+ 0.5 V

I_{VIN_INRUSH}

100 + I_LOAD

1.1

V_EN(HI)

V_EN(LO)

Enable pin high (enabled)

Enable pin low (disabled)

0.4

(1) Performance specifications are ensured to a minimum V_IN= V_OUT+ 0.5 V.

(2) Whichever is less.

(3) Minimum V_BIAS= (V_OUT+ 1.4 V) or 2.6 V (whichever is greater) and V_IN= V_OUT+ 0.5 V.

(4) V_Onominal value is factory programmable through the on-chip EEPROM.

(5) Measured for devices with V_OUT(NOM)≥ 1.2 V.

(6) V_BIAS– V_OUTwith V_OUT= V_OUT(NOM)– 0.1 V. Measured for devices with V_OUT(NOM)≥ 1.8 V.

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

Electrical Characteristics (continued)

over operating temperature range (T_J= –40°C to +125°C), V_BIAS= (V_OUT+ 1.4 V ) or 2.6 V (whichever is greater), V_IN≥ V_OUT

+ 0.5 V, I_OUT= 1 mA, V_EN= 1.1 V, and C_OUT= 2.2 μF (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

V_EN= 5.5 V, V_IN= 4.5 V, V_BIAS= 5.5 V

V_BIASrising

MIN

TYP

MAX

UNIT

µA

I_EN

Enable pin current

Undervoltage lockout

UVLO hysteresis

2.35

2.45

150

160

140

2.59

UVLO

V_BIASfalling

Shutdown, temperature increasing

Reset, temperature decreasing

T_SD

T_J

Thermal shutdown temperature

Operating junction temperature

°C

–40

125

6.6 Timing Requirements

MIN

NOM

MAX

UNIT

t_STR

Start-up time

V_OUT= 95%, V_{OUT (NOM)}, I_OUT= 350 mA, C_OUT= 2.2 μF

140

µs

TPS720-Q1

www.ti.com.cn

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

6.7 Typical Characteristics

over operating temperature range (T_J= –40°C to +125°C), V_BIAS= (V_OUT+ 1.4 V) or 2.6 V (whichever is greater), V_IN= V_OUT

0.5 V, I_OUT= 1 mA, V_EN= 1.1 V, and C_OUT= 2.2 μF (unless otherwise noted); typical values are at T_J= 25°C

1.83

1.82

1.81

1.8

1.83

1.82

1.81

1.8

T_J= -40°C

T_J= 0°C

T_J= 25°C

T_J= 85°C

T_J= 105°C

T_J= 125°C

T_J= -40°C

T_J= 0°C

T_J= 25°C

T_J= 85°C

T_J= 105°C

T_J= 125°C

1.79

3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

4.1 4.2 4.3 4.4 4.5

3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

4.1 4.2 4.3 4.4 4.5

Input Voltage (V)

I_OUT= 0 mA

I_OUT= 350 mA

Figure 1. V_INLine Regulation (No Load)

Figure 2. V_INLine Regulation (350 mA)

1.83

1.82

1.81

1.8

1.83

1.82

1.81

1.8

T_J= -40°C

T_J= 0°C

T_J= 25°C

T_J= 85°C

T_J= 105°C

T_J= 125°C

T_J= -40°C

T_J= 0°C

T_J= 25°C

T_J= 85°C

T_J= 105°C

T_J= 125°C

1.79

3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

4.1 4.2 4.3 4.4 4.5

3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

4.1 4.2 4.3 4.4 4.5

Bias Voltage (V)

Input Voltage (V)

I_OUT= 0 mA

I_OUT= 350 mA

Figure 3. V_BIASLine Regulation (No Load)

Figure 4. V_BIASLine Regulation (350 mA)

1.83

1.82

1.81

1.8

1.83

1.82

1.81

1.8

T_J= -40°C

T_J= 0°C

T_J= 25°C

T_J= 85°C

T_J= 105°C

T_J= 125°C

T_J= -40°C

T_J= 0°C

T_J= 25°C

T_J= 85°C

T_J= 105°C

T_J= 125°C

1.79

100

150

200

250

300

350

Output Current (mA)

Figure 5. Load Regulation Under Light Loads

Figure 6. Load Regulation

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

Typical Characteristics (continued)

over operating temperature range (T_J= –40°C to +125°C), V_BIAS= (V_OUT+ 1.4 V) or 2.6 V (whichever is greater), V_IN= V_OUT

0.5 V, I_OUT= 1 mA, V_EN= 1.1 V, and C_OUT= 2.2 μF (unless otherwise noted); typical values are at T_J= 25°C

1.96

1.92

1.88

1.84

1.8

1.96

1.92

1.88

1.84

1.8

V_BIAS= 3.2 V

V_BIAS= 3.5 V

V_BIAS= 4 V

V_BIAS= 4.5 V

V_BIAS= 5 V

T_J= 125èC

T_J= 105èC

T_J= 85èC

T_J= 25èC

T_J= 0èC

V_BIAS= 5.5 V

T_J= -40èC

1.76

1.72

1.68

1.64

1.6

1.76

1.72

1.68

1.64

1.6

0.5

1.5

2.5

3.5

0.25

0.5

0.75

Output Current (mA)

V_BIAS= 3.2 V

Figure 7. Load Regulation With V_INFloating

Figure 8. Load Regulation With V_INFloating

1.15

1.14

1.13

1.12

1.11

1.1

160

140

120

100

125°C

105°C

1.09

1.08

1.07

1.06

1.05

1.04

-40°C

-10°C

25°C

85°C

350

20 35 50 65 80 95 110 125

100

150

200

250

300

-40 -25 -10

Output Current (mA)

Junction Temperature (°C)

I_OUT= 350 mA

V_OUT= V_OUT(NOM)– 0.1 V

Figure 9. V_INDropout Voltage vs Output Current

Figure 10. V_BIASDropout Voltage vs Junction Temperature

1.83

I_OUT= 0 mA

I_OUT= 1 mA

I_OUT= 350 mA

1.82

1.81

1.8

125°C

105°C

85°C

25°C

-10°C

-40°C

1.79

4.5

5.5

2.5

3.5

-40 -25 -10

20 35 50 65 80 95 110 125

Junction Temperature (èC)

V_BIAS(V)

I_OUT= 1 mA

Figure 11. Output Voltage vs Junction Temperature

Figure 12. Ground Pin Current vs V_BIASVoltage

TPS720-Q1

www.ti.com.cn

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

Typical Characteristics (continued)

over operating temperature range (T_J= –40°C to +125°C), V_BIAS= (V_OUT+ 1.4 V) or 2.6 V (whichever is greater), V_IN= V_OUT

0.5 V, I_OUT= 1 mA, V_EN= 1.1 V, and C_OUT= 2.2 μF (unless otherwise noted); typical values are at T_J= 25°C

105°C

25°C

125°C

85°C

-40°C

-10°C

350

20 35 50 65 80 95 110 125

100

150

200

250

300

-40 -25 -10

Output Current (mA)

Junction Temperature (°C)

I_OUT= 350 mA

Figure 13. Ground Pin Current vs Output Current

Figure 14. Ground Pin Current vs Junction Temperature

675

2.5

650

-10°C

-40°C

25°C

625

600

575

550

-40°C

-10°C

25°C

85°C

1.5

125°C

105°C

85°C

105°C

125°C

0.5

4.5

5.5

4.5

5.5

2.5

3.5

2.5

3.5

V_BIAS(V)

Figure 15. Shutdown Current vs V_BIASVoltage

Figure 16. Current Limit vs V_BIASVoltage

675

650

625

600

575

550

120

100

I_OUT= 0 mA

-10°C

-40°C

25°C

I_OUT= 50 mA

I_OUT= 350 mA

85°C

105°C

125°C

4.5

10M

2.5

3.5

Input Voltage (V)

100

10k

100k

Frequency (Hz)

V_IN– V_OUT= 0.5 V, V_BIAS– V_OUT= 1.4 V

Figure 18. V_INPower-Supply Rejection Ratio vs Frequency

Figure 17. Current Limit vs Input Voltage

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

Typical Characteristics (continued)

over operating temperature range (T_J= –40°C to +125°C), V_BIAS= (V_OUT+ 1.4 V) or 2.6 V (whichever is greater), V_IN= V_OUT

0.5 V, I_OUT= 1 mA, V_EN= 1.1 V, and C_OUT= 2.2 μF (unless otherwise noted); typical values are at T_J= 25°C

100

(V_IN- V_OUT) = 350 mV

I_OUT= 1 mA

(V_IN- V_OUT) = 300 mV

(V_IN- V_OUT) = 250 mV

I_OUT= 350 mA

10M

100

10k

100k

100

10k

100k

Frequency (Hz)

I_OUT= 350 mA

V_IN– V_OUT= 0.5 V

V_BIAS– V_OUT= 1.4 V

Figure 19. V_INPower-Supply Rejection Ratio vs Frequency

Figure 20. V_BIASPower-Supply Rejection Ratio vs Frequency

V_OUT

1 mV/div

0.1

V_IN

200 mV/div

0.01

100k

100

10k

100 ms/div

Frequency (Hz)

V_IN= 2.1 to 2.5 V

V_OUT= 1.8 V

V_BIAS= 3.2 V

V_INslew rate = 1 V/μs

I_OUT= 350 mA

Figure 22. V_INLine Transient Response

Figure 21. Output Spectral Noise Density vs Frequency

V_OUT

10 mV/div

1 mV/div

300 mA

I_OUT

V_BIAS

0 mA

200 mV/div

100 mA/div

100 ms/div

V_IN= 2.3 V

V_OUT= 1.8 V

V_BIAS= 3.2 V to 3.8 V

I_OUT= 350 mA

V_OUT= 1.8 V

V_IN= 2.3 V

V_BIAS= 3.2 V

t_RISE= 1 μs

V_BIASslew rate = 600 m/μs

Figure 23. V_BIASLine Transient Response

Figure 24. Load Transient Response

TPS720-Q1

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ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

7 Detailed Description

7.1 Overview

The TPS720-Q1 family of LDO regulators uses innovative circuitry to achieve ultra-wide bandwidth and high loop

gain, resulting in extremely high PSRR (up to 1 MHz) at very low headroom (V_IN– V_OUT). The implementation of

the BIAS pin on the TPS720-Q1 vastly improves efficiency of low V_OUTapplications by allowing the use of a pre-

regulated, low-voltage input supply. The TPS720-Q1 supports a novel feature where the output of the LDO

regulates under light loads (< 500 μA) when the IN pin is left floating. The light-load drive current is sourced from

V_BIASunder this condition. This feature is particularly useful in power-saving applications where the dc-dc

converter connected to the IN pin is disabled but the LDO is still required to regulate the voltage to a light load.

These features, combined with low noise, low ground pin current, and ultra-small packaging, make this device

ideal for portable applications. This family of regulators offers sub-band-gap output voltages, current limit, and

thermal protection, and is fully specified from –40°C to +125°C.

7.2 Functional Block Diagram

OUT

Current

Limit

Thermal

Shutdown

BIAS

UVLO

Band Gap

7.3 Feature Description

7.3.1 Internal Current Limit

The TPS720-Q1 internal current limits help protect the regulator during fault conditions. During current limit, the

output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output

voltage is not regulated, and is V_OUT= I_LIMIT× R_LOAD. The NMOS pass transistor dissipates (V_IN– V_OUT) × I_OUT

until thermal shutdown is triggered and the device is turned off. When the device cools down, the internal thermal

shutdown circuit turns the device back on. If the fault condition continues, the device cycles between current limit

and thermal shutdown; see Thermal Considerations for more details.

The NMOS pass element in the TPS720-Q1 has a built-in body diode that conducts current when the voltage at

OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is

anticipated, TI recommends external limiting to 5% of rated output current.

7.3.2 Inrush Current Limit

The TPS720-Q1 family of LDO regulators implements a novel inrush current limit circuit architecture: the current

drawn through the IN pin is limited to a finite value. This I_INRUSHLIMITcharges the output to the final voltage. All

current drawn through V_INcharges the output capacitance when the load is disconnected. Equation 1 shows the

inrush current limit performed by the circuit.

I_INRUSHLIMIT( A ) = C_OUT(mF)x0.454545(V / ms)+ I_LOAD(A)

(1)

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

Feature Description (continued)

Assuming a C_OUTof 2.2 μF with the load disconnected (that is, I_LOAD= 0), the I_INRUSHLIMITis calculated to be

100 mA. The inrush current charges the LDO output capacitor. If the output of the LDO regulates to 1.3 V, then

the LDO charges the output capacitor to the final output value in approximately 28.6 μs.

Another consideration is when a load is connected to the output of an LDO. The TPS720-Q1 inrush current limit

circuit employs a technique that supplies not only the I_INRUSHLIMIT, but the additional current required by the load.

If I_LOAD= 350 mA, then I_INRUSHLIMITcalculates to be approximately 450 mA (from Equation 1).

7.3.3 Shutdown

The enable pin (EN) is active high and is compatible with standard and low-voltage, TTL-CMOS levels. When

shutdown capability is not required, EN can be connected to the IN pin.

7.3.4 Undervoltage Lockout (UVLO)

The TPS720-Q1 uses an undervoltage lockout circuit on the BIAS pin to keep the output shut off until the internal

circuitry is operating properly. The UVLO circuit has a deglitch feature that typically ignores undershoot transients

on the input if these transients are less than 50 μs in duration.

7.4 Device Functional Modes

Driving the EN pin over 1.1 V turns on the regulator. Driving the EN pin below 0.4 V causes the regulator to enter

shutdown mode. In shutdown, the current consumption of the device is typically reduced to 500 nA.

TPS720-Q1

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ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Input and Output Capacitor Requirements

Although a capacitor is not required for stability on the IN pin, good analog design practice is to connect a 0.1-μF

to 1-μF low equivalent series resistance (ESR) capacitor across the IN pin input supply near the regulator. This

capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple

rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if

the device is located far from the power source. If source impedance is not sufficiently low, a 0.1-μF input

capacitor may be necessary to ensure stability.

The BIAS pin does not require an input capacitor because BIAS does not source high currents. However, if

source impedance is not sufficiently low, TI recommends a small 0.1-µF bypass capacitor.

The TPS720-Q1 is designed to be stable with standard ceramic capacitors with values of 2.2 μF or larger at the

output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over

temperature. Maximum ESR must be less than 250 mΩ.

8.1.2 Output Regulation With the IN Pin Floating

The TPS720-Q1 supports a novel feature where the output of the LDO regulates under light loads when the IN

pin is left floating. Under normal conditions when the IN pin is connected to a power source, the BIAS pin draws

only tens of milliamperes. However, when the IN pin is floating, an innovative circuit allows a maximum current of

500 μA to be drawn by the load through the BIAS pin and maintains the output in regulation. This feature is

particularly useful in power-saving applications where a dc-dc converter connected to the IN pin is disabled, but

the LDO is required to regulate the output voltage to a light load.

Figure 25 shows an application example where a microcontroller is not turned off (to maintain the state of the

internal memory), but where the regulated supply (shown as the TPS62xxx) is turned off to reduce power. In this

case, the TPS720-Q1 BIAS pin provides sufficient load current to maintain a regulated voltage to the

microcontroller.

10 mH

2.6 V to 5.5 V

BIAS

VIN

OUT

TPS62xxx

TPS720-Q1

2.2 mF

10 mF

GND

Microcontroller

Control to turn on or off the dc-dc.

The output of the dc-dc is floating when

the TPS62xxx EN pin is low.

Figure 25. Floating IN Pin Regulation Example

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

Application Information (continued)

8.1.3 Dropout Voltage

The TPS720-Q1 uses a NMOS pass transistor to achieve low dropout. When (V_IN– V_OUT) is less than the

dropout voltage (V_DO), the NMOS pass device is in the linear region of operation and the input-to-output

resistance is the R_DS(ON)of the NMOS pass element. V_DOapproximately scales with output current because the

NMOS device behaves like a resistor in dropout.

PSRR and transient response are degraded when (V_IN– V_OUT) approaches dropout. This effect is shown in

Figure 19.

8.1.4 Transient Response

Increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases duration

of the transient response.

8.1.5 Minimum Load

The TPS720-Q1 is stable with no output load. Although some LDOs suffer from low loop gain at very light output

loads, the TPS720-Q1 employs an innovative, low-current mode circuit under very light or no-load conditions

which improves output voltage regulation performance.

8.2 Typical Application

V_BATT

C_BIAS

BIAS

1.8 V

1.3 V

Standalone

dc/dc

V_CORE

OUT

TPS720xx

Converter

or PMU

C_IN

C_OUT

GND

V_EN

Figure 26. Typical Application Schematic

8.2.1 Design Requirements

Table 1 lists the parameters for this design example.

Table 1. Design Parameters

DESIGN PARAMETER

EXAMPLE VALUE

V_IN

2.3 V

3.2 V

1.8 V

V_BIAS

V_OUT

I_OUT

10-mA typical, 350-mA peak

TPS720-Q1

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ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

8.2.2 Detailed Design Procedures

TI recommends selecting the minimum component size; a small size solution for this design example is desired.

Set C_IN= 1 µF, C _BIAS= 100 nF, and C_OUT= 2.2 µF.

8.2.3 Application Curves

1.83

1.82

1.81

1.8

1.83

1.82

1.81

1.8

T_J= -40°C

T_J= 0°C

T_J= 25°C

T_J= 85°C

T_J= 105°C

T_J= 125°C

T_J= -40°C

T_J= 0°C

T_J= 25°C

T_J= 85°C

T_J= 105°C

T_J= 125°C

1.79

3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9

4.1 4.2 4.3 4.4 4.5

100

150

200

250

300

350

Input Voltage (V)

Output Current (mA)

I_OUT= 350 mA

Figure 27. V_INLine Regulation

Figure 28. Load Regulation

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

9 Power Supply Recommendations

The input supply and bias supply for the LDO must be within the recommended operating conditions and must

provide adequate headroom for the device to have a regulated output. The minimum capacitor requirements

must be met, and if the input supply is noisy, additional input capacitors with low ESR can improve transient

performance.

10 Layout

10.1 Layout Guidelines

TI recommends designing the board with separate ground planes for V_INand V_OUT, with the ground plane

connected only at the GND pin of the device to improve ac performance (such as PSRR, output noise, and

transient response.) In addition, the ground connection for the output capacitor must be connected directly to the

GND pin of the device. High equivalent series resistance (ESR) capacitors can degrade PSRR. The BIAS pin

draws very little current and can be routed as a signal. Take care to shield the BIAS pin from high frequency

coupling.

10.2 Layout Example

Ground Plane

To Enable

Signal

To Bias Supply

BIAS

GND

C_BIAS

C_OUT

C_IN

OUT

To Load

To Input Supply

Ground Plane

Figure 29. Recommended Layout

TPS720-Q1

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ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

10.3 Thermal Considerations

Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing

the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is again

enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection

circuit can cycle on and off. This cycling limits the dissipation of the regulator, protecting the regulator from

damage as a result of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate

heat sink. For reliable operation, limit junction temperature to a maximum of +125°C. To estimate the margin of

safety in a complete design (including heat sink), increase the ambient temperature until the thermal protection is

triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C

above the maximum expected ambient condition of the particular application. This configuration produces a

worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS720-Q1 is designed to protect against overload conditions. This

circuitry is not intended to replace proper heat sinking. Continuously running the TPS720-Q1 into thermal

shutdown degrades device reliability.

10.4 Power Dissipation

The printed-circuit-board (PCB) area around the device that is free of other components moves the heat from the

device to ambient air. Performance data for JEDEC boards are given in the Thermal Information table. Using

heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-

holes to heat-dissipating layers also improves the heat sink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (P_D) is equal to the product of

the output current times the voltage drop across the output pass element (V_INto V_OUT), as shown in Equation 2:

P_D=(V_IN- V_OUT)ì I_OUT

(2)

TPS720-Q1

ZHCSEN1A –FEBRUARY 2016–REVISED OCTOBER 2016

www.ti.com.cn

11 器件和文档支持

11.1 器件支持

11.1.1 开发支持

11.1.1.1 评估模块

评估模块 (EVM) 可与 TPS720-Q1 配套使用，帮助评估初始电路性能。TPS720xxDRVEVM 评估模块（和相关用

户指南）可在德州仪器 (TI) 网站上的产品文件夹中获取，也可直接从 TI 网上商店购买。

的表注中的输出电压范围从“0.9V 至 3.0V”更改为“0.9V 至 3.3V”

11.1.2 器件命名规则

表 2. 器件命名规则⁽¹⁾⁽²⁾

产品

V_OUT

xx(x) 为标称输出电压。对于分辨率为 100mV 的输出电压，订货编号中使用两位数字；否则，使用三位数

字（例如，28 = 2.8V；125 = 1.25V）。

yyy 为封装标识符。

TPS720xx(x)QyyyzQ1

z 为封装数量。R 表示 3000 片，T 表示 250 片。

(1) 要获得最新的封装和订货信息，请参见本文档末尾的封装选项附录，或者访问器件产品文件夹（www.ti.com.cn）。

(2) 可提供 0.9V 至 3.3V 范围内的输出电压（以 50mV 为单位增量）。更多详细信息及可用性，请联系制造商。

11.2 文档支持

11.2.1 相关文档ꢀ

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TPS721

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