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TPS727_V01 [TI]

TPS727 250-mA, Ultralow IQ, Fast Transient Response, RF Low-Dropout Linear Regulator;
TPS727_V01
型号： TPS727_V01
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

TPS727 250-mA, Ultralow IQ, Fast Transient Response, RF Low-Dropout Linear Regulator
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TPS727  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
TPS727 250-mA, Ultralow IQ, Fast Transient Response,  
RF Low-Dropout Linear Regulator  
1 Features  
3 Description  
The TPS727 family of low-dropout (LDO) linear  
regulators are ultralow quiescent current LDOs with  
excellent line and ultra-fast load transient  
performance and are designed for power-sensitive  
applications. The LDO output voltage level is preset  
by the use of innovative factory EEPROM  
1
•
Very Low Dropout:  
–
–
–
65 mV Typical at 100 mA  
130 mV Typical at 200 mA  
163 mV Typical at 250 mA  
•
•
•
2% Accuracy Over Load, Line, Temperature  
programming.  
A
precision band-gap and error  
Ultralow IQ: 7.9 μA  
amplifier provides overall 2% accuracy over load, line,  
and temperature extremes. The TPS727 family is  
available in 1.5-mm × 1.5-mm SON and wafer chip-  
scale (WCSP) packages that make the devices ideal  
for handheld applications. This family of devices is  
fully specified over a temperature range of TJ  
–40°C to +125°C.  
Excellent Load Transient Performance:±50 mV for  
200 mA Loading and Unloading Transient  
•
Available in Fixed-Output Voltages From 0.9 V to  
5 V Using Innovative Factory EEPROM  
Programming  
=
•
•
•
•
High PSRR: 70 dB at 1 kHz  
Stable with a 1.0-μF Ceramic Capacitor  
Thermal Shutdown and Overcurrent Protection  
Device Information  
PART NUMBER  
TPS727xxDSE  
TPS727xxYFF  
PACKAGE  
WSON (6)  
DSBGA (4)  
BODY SIZE (NOM)  
Available in 4-Ball, 0.4-mm Pitch Wafer-Level  
1.50 mm × 1.50 mm  
1.20 mm × 0.80 mm  
Chip Scale and 1.5-mm × 1.5-mm SON Packages  
(1) For all available packages, see the orderable addendum at  
the end of the datasheet.  
2 Applications  
•
•
•
•
•
Wireless Handsets, Smart Phones, PDAs  
MP3 Players and Other Handheld Products  
Wireless LAN, Bluetooth®, Zigbee®  
Remote Controls  
Portable Consumer Products  
TYPICAL APPLICATION CIRCUIT  
VIN  
VOUT  
IN  
OUT  
1mF  
CIN  
COUT  
Ceramic  
TPS727xx  
On  
Off  
EN  
GND  
PSRR vs FREQUENCY  
GROUND PIN CURRENT vs TEMPERATURE  
15  
12  
9
100  
VIN = 2.1V  
IOUT = 0mA  
90  
80  
70  
IOUT = 10mA  
60  
50  
40  
30  
20  
10  
0
6
3
IOUT = 200mA  
0
10  
100  
1k  
10k  
100k  
1M  
10M  
-40 -25 -10  
5
20 35 50 65 80 95 110 125  
Frequency (Hz)  
Temperature (°C)  
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,  
intellectual property matters and other important disclaimers. PRODUCTION DATA.  
 
 
 
 
 
 
 
TPS727  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
www.ti.com  
Table of Contents  
7.4 Device Functional Modes........................................ 12  
Applications and Implementation ...................... 13  
8.1 Application Information............................................ 13  
8.2 Typical Application .................................................. 13  
8.3 Do's and Don'ts....................................................... 17  
Power-Supply Recommendations...................... 17  
1
2
3
4
5
6
Features.................................................................. 1  
Applications ........................................................... 1  
Description ............................................................. 1  
Revision History..................................................... 2  
Pin Configurations and Functions....................... 4  
Specifications......................................................... 5  
6.1 Absolute Maximum Ratings ...................................... 5  
6.2 ESD Ratings.............................................................. 5  
6.3 Recommended Operating Conditions....................... 5  
6.4 Thermal Information.................................................. 5  
6.5 Electrical Characteristics........................................... 6  
6.6 Typical Characteristics.............................................. 7  
Detailed Description ............................................ 11  
7.1 Overview ................................................................. 11  
7.2 Functional Block Diagram ....................................... 11  
7.3 Feature Description................................................. 11  
8
9
10 Layout................................................................... 17  
10.1 Layout Guidelines ................................................. 17  
10.2 Layout Example .................................................... 18  
11 Device and Documentation Support ................. 22  
11.1 Documentation Support ........................................ 22  
11.2 Community Resources.......................................... 22  
11.3 Trademarks........................................................... 22  
11.4 Electrostatic Discharge Caution............................ 22  
11.5 Glossary................................................................ 22  
7
12 Mechanical, Packaging, and Orderable  
Information ........................................................... 22  
4 Revision History  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision E (September 2014) to Revision F  
Page  
•
Changed DSBGA body size in Device Information table ...................................................................................................... 1  
Changes from Revision D (February 2014) to Revision E  
Page  
•
•
•
•
•
•
•
•
•
Added TPS727105 to document ............................................................................................................................................ 1  
Changed terminal to pin throughout document ...................................................................................................................... 1  
Updated Device Information table to current standards......................................................................................................... 1  
Changed Pin Configurations note .......................................................................................................................................... 4  
Changed Pin Functions table: reordered table by pin name, added I/O column ................................................................... 4  
Updated Handling Ratings table to current standard ............................................................................................................. 5  
Changed Thermal Information table: updated symbols.......................................................................................................... 5  
Deleted new generation from first sentence of Overview section ........................................................................................ 11  
Added note to Applications and Implementation section...................................................................................................... 13  
Changes from Revision C (January, 2011) to Revision D  
Page  
•
•
•
•
•
Changed format to meet latest data sheet standards; added new sections and moved existing sections............................ 1  
Deleted pinout diagrams from front page; see Pin Configurations and Functions section. ................................................... 1  
Changed Pin Configurations section and moved to Pin Configurations and Functions section ............................................ 4  
Changed note in Pin Configurations and Functions section. ................................................................................................. 4  
Deleted Figure 26 and Figure 27.......................................................................................................................................... 17  
Changes from Revision B (April, 2010) to Revision C  
Page  
•
•
•
Updated YFF front page pin drawing to show pin locations................................................................................................... 1  
Revised Pin Configurations section ....................................................................................................................................... 4  
Changed graph title for Figure 6............................................................................................................................................. 7  
2
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Copyright © 2009–2015, Texas Instruments Incorporated  
 
TPS727  
www.ti.com  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
Changes from Revision A (September, 2009) to Revision B  
Page  
•
•
•
•
•
•
•
•
Updated Features list ............................................................................................................................................................. 1  
Changed title of data sheet..................................................................................................................................................... 1  
Changed footnote 2 to Absolute Maximum Ratings table ...................................................................................................... 5  
Revised numerous specifications and parameters in Electrical Characteristics table ........................................................... 6  
Revised operating parameters for Figure 4............................................................................................................................ 7  
Replaced Figure 5 .................................................................................................................................................................. 7  
Added operating parameters to Figure 6................................................................................................................................ 7  
Updated Figure 9.................................................................................................................................................................... 7  
Copyright © 2009–2015, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
TPS727  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
www.ti.com  
5 Pin Configurations and Functions  
TPS72715, TPS72718, TPS72728, TPS72748  
All Other TPS727 Devices  
YFF Package  
DSBGA-4  
YFF Package  
DSBGA-4  
Top View  
Top View  
OUT  
GND  
OUT  
GND  
B2  
B1  
B2  
B1  
A2  
IN  
A1  
A2  
IN  
A1  
EN  
EN  
See note.  
See note.  
DSE Package  
1,5mm × 1,5mm WSON-6  
Top View  
OUT  
NC  
1
2
3
6
5
4
IN  
NC  
EN  
GND  
Tape and Reel  
Sprocket Holes  
Tape and Reel  
Sprocket Holes  
Top Dot  
Mark  
Top Dot  
Mark  
TPS72715YFF, TPS72718YFF  
TPS72728YFF, TPS72748YFF  
TPS727xxDSE  
TPS72711YFF  
(Example)  
See Note  
See Note  
NOTE  
The EN pin is marked with a dot for the 1.5-V, 1.8-V, 2.8-V, and 4.8-V versions of the YFF  
package. The GND pin is marked with a dot for all other voltage versions of the YFF  
package. Refer to YFF0004 Package Outline page included at the end of this document  
for dimensions of the YFF package. On the package outline, the shaded box indicates the  
location of ball A1 and does not correlate to any marking on the topside of the physical  
package.  
Pin Functions  
PIN  
I/O  
NAME  
EN  
YFF  
A1  
B1  
A2  
—
DSE  
4
DESCRIPTION  
Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown  
mode, thus reducing the operating current to 120 nA, nominal.  
I
GND  
IN  
3
—
I
Ground pin.  
Input pin. A small capacitor is needed from this pin to ground to assure stability. See Input and Output Capacitor  
Requirements in the Application Information section for more details.  
6
NC  
2, 5  
1
—
O
No connection. This pin can be tied to ground to improve thermal dissipation.  
Regulated output voltage pin. A small 1-μF ceramic capacitor is needed from this pin to ground to assure stability.  
See Input and Output Capacitor Requirements in the Application Information section for more details.  
OUT  
B2  
4
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Copyright © 2009–2015, Texas Instruments Incorporated  
TPS727  
www.ti.com  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
6 Specifications  
6.1 Absolute Maximum Ratings  
at TJ = –40°C to +125°C (unless otherwise noted); all voltages are with respect to GND(1)  
MIN  
MAX  
+6.0  
+6.0(2)  
UNIT  
Input voltage range, VIN  
–0.3  
–0.3  
–0.3  
V
V
V
Enable voltage range, VEN  
Output voltage range, VOUT  
Maximum output current, IOUT  
Output short-circuit duration  
Operating junction temperature, TJ  
Storage temperature, Tstg  
+6.0  
Internally limited  
Indefinite  
+150  
–55  
–55  
°C  
°C  
+150  
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not implied.  
(2) VEN absolute maximum rating is VIN or 6.0 V, whichever is less.  
6.2 ESD Ratings  
VALUE  
UNIT  
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)  
±2000  
V(ESD)  
Electrostatic discharge  
V
Charged device model (CDM), per JEDEC specification JESD22-C101,  
all pins(2)  
±500  
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.  
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.  
6.3 Recommended Operating Conditions  
over operating junction temperature range (unless otherwise noted)  
MIN  
2
NOM  
MAX  
5.5  
UNIT  
VIN  
IOUT  
TJ  
Input voltage  
V
Output current  
0
250  
mA  
°C  
Operating junction temperature range  
–40  
+125  
6.4 Thermal Information  
TPS727  
THERMAL METRIC(1)  
DSE (WSON)  
6 PINS  
190.5  
94.9  
YFF (DSBGA)  
UNITS  
4 PINS  
160  
75  
RθJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
RθJC(top)  
RθJB  
149.3  
6.4  
76  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance(2)  
3
ψJB  
152.8  
N/A  
74  
RθJC(bot)  
N/A  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) θJCbot is not applicable because there is no thermal pad.  
Copyright © 2009–2015, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
 
TPS727  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
www.ti.com  
6.5 Electrical Characteristics  
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater;  
IOUT = 10 mA, VEN = 0.9 V, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C.  
PARAMETER  
Input voltage range  
Output voltage range  
TEST CONDITIONS  
MIN  
2.0  
TYP  
MAX  
5.5  
UNIT  
V
VIN  
VO  
0.9  
5.0  
V
TJ = +25°C  
–2.5  
+2.5  
mV  
VOUT + 0.3 V ≤ VIN ≤ 5.5 V,  
0 mA ≤ IOUT ≤ 200 mA  
–2.0%  
±1.0%  
±1.0%  
±50.0  
±65  
+2.0%  
(1)  
VOUT  
DC output accuracy  
Load transient  
VOUT + 0.3 V ≤ VIN ≤ 5.5 V,  
0 mA ≤ IOUT ≤ 250 mA  
1 mA to 200 mA or  
200 mA to 1 mA in 1 μs, COUT = 1 μF  
ΔVOUT  
mV  
1 mA to 250 mA or  
250 mA to 1 mA in 1 μs, COUT = 1 μF  
VOUT(NOM) + 0.3 V ≤ VIN ≤ 5.5 V,  
IOUT = 10 mA  
ΔVO/ΔVIN Line regulation  
ΔVO/ΔIOUT Load regulation  
8
μV/V  
0 mA ≤ IOUT ≤ 250 mA  
20  
6.5  
μV/mA  
VIN = 0.98 × VOUT(NOM), IOUT = 10 mA  
VIN = 0.98 × VOUT(NOM), IOUT = 50 mA  
VIN = 0.98 × VOUT(NOM), IOUT = 100 mA  
VIN = 0.98 × VOUT(NOM), IOUT = 200 mA  
VIN = 0.98 × VOUT(NOM), IOUT = 250 mA  
VOUT = 0.9 × VOUT(NOM)  
32.5  
65  
VDO  
Dropout voltage(2)  
mV  
130  
162.5  
400  
7.9  
200  
ICL  
Output current limit  
Ground pin current  
300  
550  
12  
mA  
µA  
IOUT = 0 mA, TJ = –40°C to +125°C  
IOUT = 200 mA  
IGND  
110  
130  
0.12  
IOUT = 250 mA  
VEN ≤ 0.4 V, VIN = 2 V, TJ = +25°C  
ISHDN  
Shutdown current (IGND  
)
µA  
VEN ≤ 0.4 V, 2.0 V < VIN ≤ 4.5 V,  
TJ = –40°C to +85°C  
0.55  
2
f = 10 Hz  
85  
75  
70  
55  
40  
45  
f = 100 Hz  
VIN = 2.3 V,  
f = 1 kHz  
PSRR  
Power-supply rejection ratio  
Output noise voltage  
VOUT = 1.8 V,  
IOUT = 10 mA  
dB  
f = 10 kHz  
f = 100 kHz  
f = 1 MHz  
BW = 100 Hz to 100 kHz, VIN = 2.1 V,  
VOUT = 1.8 V, IOUT = 10 mA  
VN  
33.5  
100  
μVRMS  
tSTR  
VHI  
Startup time(3)  
COUT = 1.0 μF, 0 ≤ IOUT ≤ 250 mA  
μs  
V
Enable pin high (enabled)  
Enable pin low (disabled)  
Enable pin current  
0.9  
0
VIN  
0.4  
VLO  
IEN  
V
EN = 5.5 V  
40  
1.90  
500  
1.95  
nA  
V
UVLO  
Undervoltage lock-out  
VIN rising  
1.85  
–40  
Shutdown, temperature increasing  
Reset, temperature decreasing  
+160  
+140  
TSD  
TJ  
Thermal shutdown temperature  
Operating junction temperature  
°C  
°C  
+125  
(1) The output voltage is programmed at the factory.  
(2) VDO is measured for devices with VOUT(NOM) ≥ 2.35 V so that VIN ≥ 2.3 V.  
(3) Startup time: time from EN assertion to 0.98 × VOUT(NOM)  
.
6
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Copyright © 2009–2015, Texas Instruments Incorporated  
TPS727  
www.ti.com  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
6.6 Typical Characteristics  
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT  
10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C.  
=
1.90  
1.88  
1.86  
1.84  
1.82  
1.80  
1.78  
1.76  
1.74  
1.72  
1.70  
1.90  
1.88  
1.86  
1.84  
1.82  
1.80  
1.78  
1.76  
1.74  
1.72  
1.70  
+125°C  
+85°C  
+25°C  
-40°C  
+125°C  
+85°C  
+25°C  
-40°C  
2.1  
2.6  
3.1  
3.6  
4.1  
4.6  
5.1  
5.6  
2.1  
2.6  
3.1  
3.6  
4.1  
4.6  
5.1  
5.6  
VIN (V)  
VIN (V)  
IOUT = 10 mA  
IOUT = 200 mA  
Figure 1. Line Regulation  
(TPS72718)  
Figure 2. Line Regulation  
(TPS72718)  
1.90  
1.88  
1.86  
1.84  
1.82  
1.80  
1.78  
1.76  
1.74  
1.72  
1.70  
1.90  
1.88  
1.86  
1.84  
1.82  
1.80  
1.78  
1.76  
1.74  
1.72  
1.70  
+125°C  
+125°C  
+85°C  
+25°C  
-40°C  
+85°C  
+25°C  
-40°C  
0
25  
50  
75 100 125 150 175 200 225 250  
IOUT (mA)  
0
1
2
3
4
5
6
7
8
9
10  
IOUT (mA)  
0 mA ≤ IOUT ≤ 250 mA  
0 mA ≤ IOUT ≤ 10 mA  
Figure 4. Load Regulation  
(TPS72718)  
Figure 3. Load Regulation Under Light Loads  
(TPS72718)  
160  
140  
120  
100  
80  
160  
140  
120  
100  
80  
60  
60  
40  
40  
+125°C  
+85°C  
+25°C  
-40°C  
+125°C  
+85°C  
+25°C  
-40°C  
20  
20  
0
0
0
50  
100  
150  
200  
250  
2.25  
2.75  
3.25  
3.75  
4.25  
4.75  
VIN (V)  
IOUT (mA)  
IOUT = 200 mA  
Figure 6. Dropout Voltage vs Input Voltage  
Figure 5. Dropout Voltage vs Output Current (TPS72750)  
Copyright © 2009–2015, Texas Instruments Incorporated  
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TPS727  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
www.ti.com  
Typical Characteristics (continued)  
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT  
=
10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C.  
1.90  
1.88  
1.86  
1.84  
1.82  
1.80  
1.78  
1.76  
1.74  
1.72  
1.70  
12.0  
11.5  
11.0  
10.5  
10.0  
9.5  
+125°C  
+85°C  
+25°C  
-40°C  
IOUT = 10 mA  
9.0  
IOUT = 200 mA  
8.5  
8.0  
7.5  
7.0  
-40 -25 -10  
5
20 35 50 65 80 95 110 125  
2.1  
2.6  
3.1  
3.6  
4.1  
4.6  
5.1  
5.6  
Temperature (°C)  
VIN (V)  
IOUT = 0 mA  
Figure 7. Output Voltage vs Temperature  
(TPS72718)  
Figure 8. Ground Pin Current vs Input Voltage  
(TPS72718)  
15  
12  
9
140  
120  
100  
80  
60  
6
+125°C  
40  
+85°C  
+25°C  
-40°C  
3
20  
0
0
0
25  
50  
75 100 125 150 175 200 225 250  
IOUT (mA)  
-40 -25 -10  
5
20 35 50 65 80 95 110 125  
Temperature (°C)  
VIN = 2.1 V, IOUT = 0 mA  
0 mA ≤ IOUT ≤ 250 mA  
Figure 10. Ground Pin Current vs Temperature  
(TPS72718)  
Figure 9. Ground Pin Current vs Load  
(TPS72718)  
550  
500  
450  
400  
350  
2.0  
1.6  
1.2  
0.8  
0.4  
0
+125°C  
+85°C  
+25°C  
-40°C  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
VIN (V)  
VIN (V)  
Figure 11. Shutdown Current vs Input Voltage  
(TPS72718)  
Figure 12. Current Limit vs Input Voltage  
(TPS72718)  
8
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Copyright © 2009–2015, Texas Instruments Incorporated  
TPS727  
www.ti.com  
SBVS128F –JUNE 2009–REVISED DECEMBER 2015  
Typical Characteristics (continued)  
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT  
10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C.  
=
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
IOUT = 10 mA  
IOUT = 10 mA  
IOUT = 200 mA  
IOUT = 200 mA  
1M 10M  
10  
100  
1k  
10k  
100k  
1M  
10M  
10  
100  
1k  
10k  
100k  
Frequency (Hz)  
Frequency (Hz)  
Figure 13. PSRR vs Frequency  
(VIN – VOUT = 0.5 V, TPS72718)  
Figure 14. PSRR vs Frequency  
(VIN – VOUT = 0.3 V, TPS72718)  
80  
70  
60  
50  
40  
30  
20  
10  
0
10.00  
1.00  
0.10  
0.01  
0
1 kHz  
10 kHz  
100 kHz  
2.1  
2.2  
2.3  
2.4  
2.5  
2.6  
2.7  
2.8  
10  
100  
1k  
10k  
100k  
1M  
10M  
VIN (V)  
Frequency (Hz)  
IOUT = 10 mA, CIN = COUT = 1 µF  
Figure 15. PSRR vs Input Voltage  
(TPS72718)  
Figure 16. Output Spectral Noise Density vs Output Voltage  
(TPS72718)  
200 mA  
IOUT  
200 mA  
IOUT  
1 mA  
0.1 mA  
VOUT  
VOUT  
100 ms/div  
50 ms/div  
VIN = 2.3 V, tR = tF = 1 µs  
VIN = 2.3 V, tR = tF = 1 µs  
Figure 17. Load Transient Response: 0.1 mA to 200 mA  
(TPS72718)  
Figure 18. Load Transient Response: 1 mA to 200 mA  
(TPS72718)  
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Typical Characteristics (continued)  
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3 V or 2.0 V, whichever is greater; IOUT  
=
10 mA, VEN = VIN, and COUT = 1.0 μF (unless otherwise noted). Typical values are at TJ = +25°C.  
200 mA  
VOUT  
IOUT  
10 mA  
2.7 V  
VOUT  
VIN  
2.1 V  
1 ms/div  
50 ms/div  
Slew rate = 1 V/µs, IOUT = 100 µA  
VIN = 2.3 V, tR = tF = 1 µs  
Figure 20. Line Transient Response  
(TPS72718)  
Figure 19. Load Transient Response: 10 mA to 200 mA  
(TPS72718)  
EN  
VOUT  
VOUT  
2.7 V  
VIN  
IIN  
2.1 V  
100 ms/div  
20 ms/div  
Slew rate = 1 V/µs, IOUT = 200 µA  
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 100 µA  
Figure 21. Line Transient Response  
(TPS72718)  
Figure 22. VIN Inrush Current  
(TPS72718)  
EN  
VIN  
VOUT  
VOUT  
IIN  
200 ms/div  
20 ms/div  
IOUT = 200 mA  
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 200 mA  
Figure 24. VIN Ramp Up, Ramp Down Response  
(TPS72718)  
Figure 23. VIN Inrush Current  
(TPS72718)  
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7 Detailed Description  
7.1 Overview  
The TPS727 devices belong to a family of LDO regulators that consume extremely low quiescent current while  
simultaneously delivering excellent PSRR with very little headroom (VIN – VOUT differential voltage), and very  
good transient response. These features, combined with low noise without a noise reduction pin in an ultrasmall  
package, make these devices ideal for portable applications. This family of regulators offers sub-band-gap output  
voltages, current limit and thermal protection, and is fully specified from –40°C to +125°C.  
7.2 Functional Block Diagram  
IN  
OUT  
Current  
Limit  
Thermal  
Shutdown  
UVLO  
EEPROM  
Bandgap  
EN  
LOGIC  
7.3 Feature Description  
7.3.1 Internal Current Limit  
The TPS727 internal current limit helps protect the regulator during fault conditions. During current limit, the  
output sources a fixed amount of current that is largely independent of output voltage. In such a case, the output  
voltage is not regulated and is VOUT = ILIMIT × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ILIMIT  
until thermal shutdown is triggered and the device is turned off. As the device cools down, it is turned on by the  
internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and  
thermal shutdown. See the Thermal Protection section for more details.  
The PMOS pass element in the TPS727 has a built-in body diode that conducts current when the voltage at the  
OUT pin exceeds the voltage at the IN pin. This current is not limited, so if extended reverse voltage operation is  
anticipated, external limiting to 5% of rated output current is recommended.  
7.3.2 Soft Start  
The startup current is given by Equation 1:  
ISOFT START (mA) = COUT(mF) ´ 0.07(V/ms) + ILOAD(mA)  
(1)  
Equation 1 shows that soft-start current is directly proportional to COUT  
.
The output voltage ramp rate is independent of COUT and load current, and has a typical value of 0.07 V/μs.  
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Feature Description (continued)  
The TPS727 automatically adjusts the soft-start current to supply both the load current and the COUT charge  
current. For example, if ILOAD = 0 mA upon enabling the LDO, ISOFT START = 1 μF × 0.07 V/μs + 0 mA = 70 mA,  
the current that charges the output capacitor.  
If ILOAD = 200 mA, ISOFT START = 1 μF × 0.07 V/μs + 200 mA = 270 mA, the current required for charging output  
capacitor and supplying the load current.  
If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, the  
current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, 10 μF  
× 0.07 V/μs + 200 mA = 900 mA is not supplied. Instead, the current is clamped at 400 mA.  
7.3.3 Shutdown  
The enable pin (EN) is active high and is compatible with standard and low voltage, TTL-CMOS levels. When  
shutdown capability is not required, EN can be connected to the IN pin.  
7.3.4 Dropout Voltage  
The TPS727 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout  
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the  
RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS device  
functions like a resistor in dropout.  
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.  
This effect is illustrated in Figure 15 in the Typical Characteristics section.  
7.3.5 Undervoltage Lock-out (UVLO)  
The TPS727 uses an undervoltage lock-out circuit that keeps the output shut off until the input voltage reaches  
the UVLO threshold voltage.  
7.3.6 Thermal Protection  
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing  
the device to cool. When the junction temperature cools to approximately +140°C the output circuitry is again  
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection  
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a  
result of overheating.  
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate  
heatsink. For reliable operation, limit junction temperature to +125°C maximum. To estimate the margin of safety  
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is  
triggered; use worst-case loads and signal conditions. For good reliability, thermal protection triggers at least  
+35°C above the maximum expected ambient condition of a particular application. This configuration produces a  
worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load.  
The internal protection circuitry of the TPS727 is designed to protect against overload conditions. This circuitry is  
not intended to replace proper heatsinking. Continuously running the TPS727 into thermal shutdown degrades  
device reliability.  
7.4 Device Functional Modes  
7.4.1 Operation with EN Control  
Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode,  
thus reducing the operating current to 120 nA, nominal.  
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8 Applications and Implementation  
NOTE  
Information in the following applications sections is not part of the TI component  
specification, and TI does not warrant its accuracy or completeness. TI’s customers are  
responsible for determining suitability of components for their purposes. Customers should  
validate and test their design implementation to confirm system functionality.  
8.1 Application Information  
The TPS727 family of low-dropout (LDO) linear regulators are utralow quiescent current LDOs with excellent line  
and ultra-fast load transient performance and are designed for power-sensitive applications.  
8.2 Typical Application  
Figure 25. TPS72718YFF 2.5 VIN to 1.8 VOUT at 200 mA Schematic  
8.2.1 Design Requirements  
8.2.1.1 Input and Output Capacitor Requirements  
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-μF to  
1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input of the regulator. This  
capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple  
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if  
the device is not located close to the power source. If source impedance is not sufficiently low, a 0.1-μF input  
capacitor may be necessary to ensure stability.  
The TPS727 is designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at the  
output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over  
temperature. Maximum ESR must be less than 200 mΩ.  
8.2.1.2 Transient Response  
As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but  
increases duration of the transient response.  
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Typical Application (continued)  
8.2.2 Detailed Design Procedure  
Select the desired device based on the output voltage.  
Provide an input supply with adequate headroom to include dropout and output current to account for the GND  
pin current and to power the load.  
Select adequate input and output capacitors.  
The startup current is given by Equation 2:  
ISOFT START (mA) = COUT(mF) ´ 0.07(V/ms) + ILOAD(mA)  
(2)  
Equation 2 shows that soft-start current is directly proportional to COUT  
.
The output voltage ramp rate is independent of COUT and load current and has a typical value of 0.07 V/μs.  
The TPS727 automatically adjusts the soft-start current to supply both the load current and the COUT charge  
current. For example, if ILOAD = 0 mA upon enabling the LDO, ISOFT START = 1 μF × 0.07 V/μs + 0 mA = 70 mA,  
the current that charges the output capacitor.  
If ILOAD = 200 mA, ISOFT START = 1 μF × 0.07 V/μs + 200 mA = 270 mA, the current required for charging output  
capacitor and supplying the load current.  
If the output capacitor and load are increased such that the soft-start current exceeds the output current limit, the  
current is clamped at the typical current limit of 400 mA. For example, if COUT = 10 μF and IOUT = 200 mA, 10 μF  
× 0.07 V/μs + 200 mA = 900 mA is not supplied. Instead, the current is clamped at 400 mA.  
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Typical Application (continued)  
8.2.3 Application Curves  
10.00  
1.00  
0.10  
0.01  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
IOUT = 10 mA  
IOUT = 200 mA  
10  
100  
1k  
10k  
100k  
1M  
10M  
10  
100  
1k  
10k  
100k  
1M  
10M  
Frequency (Hz)  
Frequency (Hz)  
IOUT = 10 mA, CIN = COUT = 1 µF  
Figure 26. PSRR vs Frequency  
(VIN – VOUT = 0.5 V, TPS72718)  
Figure 27. Output Spectral Noise Density vs Output  
Voltage (TPS72718)  
200 mA  
IOUT  
200 mA  
IOUT  
1 mA  
0.1 mA  
VOUT  
VOUT  
100 ms/div  
50 ms/div  
VIN = 2.3 V, tR = tF = 1 µs  
VIN = 2.3 V, tR = tF = 1 µs  
Figure 28. Load Transient Response: 0.1 mA to 200 mA  
(TPS72718)  
Figure 29. Load Transient Response: 1 mA to 200 mA  
(TPS72718)  
200 mA  
VOUT  
IOUT  
10 mA  
2.7 V  
VOUT  
VIN  
2.1 V  
1 ms/div  
50 ms/div  
Slew rate = 1 V/µs, IOUT = 100 µA  
VIN = 2.3 V, tR = tF = 1 µs  
Figure 31. Line Transient Response (TPS72718)  
Figure 30. Load Transient Response: 10 mA to 200 mA  
(TPS72718)  
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Typical Application (continued)  
EN  
VOUT  
VOUT  
2.7 V  
VIN  
IIN  
2.1 V  
100 ms/div  
20 ms/div  
Slew rate = 1 V/µs, IOUT = 200 µA  
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 100 µA  
Figure 32. Line Transient Response (TPS72718)  
Figure 33. VIN Inrush Current (TPS72718)  
EN  
VIN  
VOUT  
VOUT  
IIN  
200 ms/div  
20 ms/div  
IOUT = 200 mA  
VIN = 2.1 V, VOUT = 1.8 V, IOUT = 200 mA  
Figure 35. VIN Ramp Up, Ramp Down Response  
(TPS72718)  
Figure 34. VIN Inrush Current (TPS72718)  
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8.3 Do's and Don'ts  
Do place at least one 1.0-µF ceramic capacitor as close as possible to the OUT pin of the regulator.  
Do not place the output capacitor more than 10 mm away from the regulator.  
For DSE devices, do tie the NC pins to ground to improve thermal dissipation.  
Do connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND input  
of the regulator.  
Do not exceed the absolute maximum ratings.  
9 Power-Supply Recommendations  
These devices are designed to operate from an input voltage supply range between 2.0 V and 5.5 V. The input  
voltage range provides adequate headroom in order for the device to have a regulated output. This input supply  
must be well regulated. If the input supply is noisy, additional input capacitors with low ESR can help improve the  
output noise performance.  
10 Layout  
10.1 Layout Guidelines  
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance  
To improve ac performance (such as PSRR, output noise, and transient response), TI recommends that the  
board be designed with separate ground planes for VIN and VOUT, with the ground plane connected only at the  
GND pin of the device. In addition, the ground connection for the output capacitor must be connected directly to  
the GND pin of the device. High ESR capacitors may degrade PSRR.  
10.1.2 Power Dissipation  
The ability to remove heat from the die is different for each package type, presenting different considerations in  
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves  
the heat from the device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the  
Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device.  
The addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness.  
Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of  
the output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 3:  
PD = (VIN - VOUT) ´ IOUT  
(3)  
10.1.3 Package Mounting  
Solder pad footprint recommendations and recommended land patterns are attached to the end of this  
document.  
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10.2 Layout Example  
10.2.1 DSE EVM Board Layout  
This section provides the TPS727xxDSEEVM-406 board layout and illustrations.  
Figure 36. Top Layer Assembly  
Figure 37. Top Layer Routing  
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Layout Example (continued)  
Figure 38. Bottom Layer Routing  
Figure 39. Bottom Layer Assembly  
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Layout Example (continued)  
10.2.2 YFF EVM Board Layout  
This section provides the TPS727xxYFFEVM-407 board layout and illustrations.  
Figure 40. Top Layer Assembly  
Figure 41. Top Layer Routing  
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Layout Example (continued)  
Figure 42. Bottom Layer Routing  
Figure 43. Bottom Layer Assembly  
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11 Device and Documentation Support  
11.1 Documentation Support  
11.1.1 Related Documentation  
Application report SLAA414, LDO PSRR Measurement Simplified.  
Application report SLAA412, LDO Noise Demystified.  
User guide SLVU323, TPS727xxYFF EVM  
User guide SLVU325, TPS727xxDSE EVM  
11.1.2 Device Nomenclature  
Table 1. Device Nomenclature(1)  
(2)  
PRODUCT  
VOUT  
TPS727xxx yyy z  
XXX is the nominal output voltage.  
YYY is package designator.  
Z is package tape and reel quantity (R = 3000, T = 250).  
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the  
device product folder at www.ti.com.  
(2) Output voltages from 0.9 V to 5.0 V in 50-mV increments are available through the use of innovative factory EEPROM programming;  
minimum order quantities may apply. Contact factory for details and availability.  
11.2 Community Resources  
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective  
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of  
Use.  
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration  
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help  
solve problems with fellow engineers.  
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and  
contact information for technical support.  
11.3 Trademarks  
E2E is a trademark of Texas Instruments.  
Bluetooth is a registered trademark of Bluetooth SIG.  
Zigbee is a registered trademark of Zigbee Alliance.  
All other trademarks are the property of their respective owners.  
11.4 Electrostatic Discharge Caution  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
11.5 Glossary  
SLYZ022 — TI Glossary.  
This glossary lists and explains terms, acronyms, and definitions.  
12 Mechanical, Packaging, and Orderable Information  
The following pages include mechanical packaging and orderable information. This information is the most  
current data available for the designated devices. This data is subject to change without notice and revision of  
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.  
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PACKAGE OUTLINE  
TPS727xxYFF  
YFF0004  
DSBGA - 0.625 mm max height  
SCALE 13.000  
DIE SIZE BALL GRID ARRAY  
A
B
E
BALL A1  
CORNER  
D
0.625 MAX  
C
SEATING PLANE  
0.30  
0.12  
BALL TYP  
0.4 TYP  
B
A
D: Max = 0.82 mm, Min = 0.76 mm  
E: Max = 1.19 mm, Min = 1.13 mm  
SYMM  
0.4  
TYP  
1
2
0.3  
0.2  
SYMM  
4X  
C A  
0.015  
B
02/2014  
NanoFree Is a trademark of Texas Instruments.  
NOTES:  
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing  
per ASME Y14.5M.  
2. This drawing is subject to change without notice.  
3. NanoFreeTM package configuration.  
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EXAMPLE BOARD LAYOUT  
TPS727xxYFF  
YFF0004  
DSBGA - 0.625 mm max height  
DIE SIZE BALL GRID ARRAY  
(0.4) TYP  
4
0.23 0.02  
2
1
A
SYMM  
(0.4) TYP  
B
SYMM  
LAND PATTERN EXAMPLE  
SCALE:50X  
0.05 MAX  
0.05 MIN  
( 0.23)  
METAL  
METAL  
UNDER  
MASK  
(
0.23)  
SOLDER MASK  
OPENING  
SOLDER MASK  
OPENING  
NON-SOLDER MASK  
DEFINED  
(PREFERRED)  
SOLDER MASK  
DEFINED  
SOLDER MASK DETAILS  
NOT TO SCALE  
02/2014  
NOTES: (continued)  
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.  
Refer to Texas Instruments Literature No. SBVA017 (www.ti.com/lit/sbva017).  
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EXAMPLE STENCIL DESIGN  
TPS727xxYFF  
YFF0004  
DSBGA - 0.625 mm max height  
DIE SIZE BALL GRID ARRAY  
(0.4) TYP  
4X ( 0.25)  
(R0.05) TYP  
1
2
A
B
SYMM  
(0.4)  
TYP  
METAL  
TYP  
SYMM  
SOLDER PASTE EXAMPLE  
BASED ON 0.1 mm THICK STENCIL  
SCALE:50X  
02/2014  
NOTES: (continued)  
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.  
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PACKAGE OPTION ADDENDUM  
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27-Aug-2020  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
Qty  
3000  
250  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPS727105YFFR  
TPS727105YFFT  
TPS72710DSER  
TPS72710DSET  
TPS72711YFFR  
TPS72711YFFT  
TPS72715DSER  
TPS72715DSET  
TPS72715YFFR  
TPS72715YFFT  
TPS727185YFFR  
TPS727185YFFT  
TPS72718DSER  
TPS72718DSET  
TPS72718YFFR  
TPS72718YFFT  
ACTIVE  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
4
4
6
6
4
4
6
6
4
4
4
4
6
6
4
4
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
GA  
GA  
UR  
UR  
QL  
QL  
GS  
GS  
GS  
GS  
RW  
RW  
GT  
GT  
GT  
GT  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
3000  
250  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
3000  
250  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
SNAGCU  
NIPDAUAG  
NIPDAUAG  
SNAGCU  
SNAGCU  
SNAGCU  
SNAGCU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
3000  
250  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
3000  
250  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
27-Aug-2020  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
DSE  
DSE  
YFF  
Qty  
3000  
250  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPS72719DSER  
TPS72719DSET  
TPS72719YFFR  
TPS72719YFFT  
TPS72725DSER  
TPS72725DSET  
TPS72727DSER  
TPS72727DSET  
TPS727285DSER  
TPS727285DSET  
TPS72728DSER  
TPS72728DSET  
TPS72728YFFR  
TPS72728YFFT  
TPS72730DSER  
TPS72730DSET  
TPS72730YFFR  
ACTIVE  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
6
6
4
4
6
6
6
6
6
6
6
6
4
4
6
6
4
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
CB  
CB  
AA  
AA  
QA  
QA  
TS  
TS  
QK  
QK  
GU  
GU  
GU  
GU  
QB  
QB  
ZZ  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
3000  
250  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
YFF  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
YFF  
3000  
250  
Green (RoHS  
& no Sb/Br)  
NIPDAUAG  
NIPDAUAG  
Green (RoHS  
& no Sb/Br)  
3000  
250  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
3000  
250  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
3000  
250  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
3000  
250  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
YFF  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
DSE  
DSE  
YFF  
3000  
250  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
3000  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
27-Aug-2020  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan  
Lead finish/  
Ball material  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
(6)  
TPS72730YFFT  
TPS72733DSER  
TPS72733DSET  
TPS72733YFFR  
TPS72733YFFT  
ACTIVE  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
YFF  
4
6
6
4
4
250  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
ZZ  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DSE  
3000  
250  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
QC  
QC  
ZY  
ZY  
DSE  
Green (RoHS NIPDAU | NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
YFF  
3000  
250  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
YFF  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
TPS72748DSER  
TPS72748YFFR  
PREVIEW  
ACTIVE  
WSON  
DSE  
YFF  
6
4
3000  
3000  
TBD  
Call TI  
Call TI  
-40 to 125  
-40 to 125  
DSBGA  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
EY  
EY  
CA  
CA  
TPS72748YFFT  
TPS72750YFFR  
TPS72750YFFT  
ACTIVE  
ACTIVE  
ACTIVE  
DSBGA  
DSBGA  
DSBGA  
YFF  
YFF  
YFF  
4
4
4
250  
3000  
250  
Green (RoHS  
& no Sb/Br)  
SNAGCU  
SNAGCU  
SNAGCU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 125  
-40 to 125  
-40 to 125  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance  
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may  
reference these types of products as "Pb-Free".  
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.  
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based  
flame retardants must also meet the <=1000ppm threshold requirement.  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Addendum-Page 3  
PACKAGE OPTION ADDENDUM  
www.ti.com  
27-Aug-2020  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6)  
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two  
lines if the finish value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 4  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
1-Feb-2018  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS727105YFFR  
TPS727105YFFT  
TPS72710DSER  
TPS72710DSER  
TPS72710DSET  
TPS72710DSET  
TPS72711YFFR  
TPS72711YFFT  
TPS72715DSER  
TPS72715DSET  
TPS72715YFFR  
TPS72715YFFT  
TPS727185YFFR  
TPS727185YFFT  
TPS72718DSER  
TPS72718DSET  
TPS72718YFFR  
TPS72718YFFT  
DSBGA  
DSBGA  
WSON  
WSON  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
YFF  
YFF  
DSE  
DSE  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
4
4
6
6
6
6
4
4
6
6
4
4
4
4
6
6
4
4
3000  
250  
180.0  
180.0  
179.0  
178.0  
178.0  
179.0  
180.0  
180.0  
179.0  
179.0  
180.0  
180.0  
180.0  
180.0  
178.0  
178.0  
180.0  
180.0  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
0.89  
0.89  
1.8  
1.26  
1.26  
1.8  
0.69  
0.69  
1.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q1  
Q1  
Q2  
Q2  
Q2  
Q2  
Q1  
Q1  
Q2  
Q2  
Q2  
Q2  
Q1  
Q1  
Q2  
Q2  
Q2  
Q2  
3000  
3000  
250  
1.7  
1.7  
0.95  
0.95  
1.0  
1.7  
1.7  
250  
1.8  
1.8  
3000  
250  
0.89  
0.89  
1.8  
1.26  
1.26  
1.8  
0.69  
0.69  
1.0  
3000  
250  
1.8  
1.8  
1.0  
3000  
250  
0.89  
0.89  
0.89  
0.89  
1.7  
1.26  
1.26  
1.26  
1.26  
1.7  
0.69  
0.69  
0.69  
0.69  
0.95  
0.95  
0.69  
0.69  
3000  
250  
3000  
250  
1.7  
1.7  
3000  
250  
0.89  
0.89  
1.26  
1.26  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
1-Feb-2018  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS72719DSER  
TPS72719DSER  
TPS72719DSET  
TPS72719DSET  
TPS72719YFFR  
TPS72719YFFT  
TPS72725DSER  
TPS72725DSET  
TPS72727DSER  
TPS72727DSER  
TPS72727DSET  
TPS72727DSET  
TPS727285DSER  
TPS727285DSER  
TPS727285DSET  
TPS727285DSET  
TPS72728DSER  
TPS72728DSER  
TPS72728DSET  
TPS72728DSET  
TPS72728YFFR  
TPS72728YFFT  
TPS72730DSER  
TPS72730DSET  
TPS72730YFFR  
TPS72730YFFT  
TPS72733DSER  
TPS72733DSET  
TPS72733YFFR  
TPS72733YFFT  
TPS72748YFFR  
TPS72748YFFT  
TPS72750YFFR  
TPS72750YFFT  
WSON  
WSON  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
DSE  
DSE  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
YFF  
YFF  
YFF  
YFF  
6
6
6
6
4
4
6
6
6
6
6
6
6
6
6
6
6
6
6
6
4
4
6
6
4
4
6
6
4
4
4
4
4
4
3000  
3000  
250  
178.0  
179.0  
178.0  
179.0  
180.0  
180.0  
179.0  
179.0  
179.0  
178.0  
179.0  
178.0  
178.0  
179.0  
179.0  
178.0  
178.0  
179.0  
179.0  
178.0  
180.0  
180.0  
178.0  
178.0  
180.0  
180.0  
178.0  
178.0  
180.0  
180.0  
180.0  
180.0  
180.0  
180.0  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
1.7  
1.8  
1.7  
1.8  
0.95  
1.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q2  
Q2  
Q2  
Q2  
Q1  
Q1  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q1  
Q1  
Q2  
Q2  
Q1  
Q1  
Q2  
Q2  
Q1  
Q1  
1.7  
1.7  
0.95  
1.0  
250  
1.8  
1.8  
3000  
250  
0.89  
0.89  
1.8  
1.26  
1.26  
1.8  
0.69  
0.69  
1.0  
3000  
250  
1.8  
1.8  
1.0  
3000  
3000  
250  
1.8  
1.8  
1.0  
1.7  
1.7  
0.95  
1.0  
1.8  
1.8  
250  
1.7  
1.7  
0.95  
0.95  
1.0  
3000  
3000  
250  
1.7  
1.7  
1.8  
1.8  
1.8  
1.8  
1.0  
250  
1.7  
1.7  
0.95  
0.95  
1.0  
3000  
3000  
250  
1.7  
1.7  
1.8  
1.8  
1.8  
1.8  
1.0  
250  
1.7  
1.7  
0.95  
0.69  
0.69  
0.95  
0.95  
0.69  
0.69  
0.95  
0.95  
0.69  
0.69  
0.69  
0.69  
0.69  
0.69  
3000  
250  
0.89  
0.89  
1.7  
1.26  
1.26  
1.7  
3000  
250  
1.7  
1.7  
3000  
250  
0.89  
0.89  
1.7  
1.26  
1.26  
1.7  
3000  
250  
1.7  
1.7  
3000  
250  
0.89  
0.89  
0.89  
0.89  
0.89  
0.89  
1.26  
1.26  
1.26  
1.26  
1.26  
1.26  
3000  
250  
3000  
250  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
1-Feb-2018  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS727105YFFR  
TPS727105YFFT  
TPS72710DSER  
TPS72710DSER  
TPS72710DSET  
TPS72710DSET  
TPS72711YFFR  
TPS72711YFFT  
TPS72715DSER  
TPS72715DSET  
TPS72715YFFR  
TPS72715YFFT  
TPS727185YFFR  
TPS727185YFFT  
TPS72718DSER  
TPS72718DSET  
TPS72718YFFR  
TPS72718YFFT  
TPS72719DSER  
TPS72719DSER  
DSBGA  
DSBGA  
WSON  
WSON  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
YFF  
YFF  
DSE  
DSE  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
4
4
6
6
6
6
4
4
6
6
4
4
4
4
6
6
4
4
6
6
3000  
250  
182.0  
182.0  
203.0  
205.0  
205.0  
203.0  
182.0  
182.0  
203.0  
203.0  
182.0  
182.0  
182.0  
182.0  
205.0  
205.0  
182.0  
182.0  
205.0  
203.0  
182.0  
182.0  
203.0  
200.0  
200.0  
203.0  
182.0  
182.0  
203.0  
203.0  
182.0  
182.0  
182.0  
182.0  
200.0  
200.0  
182.0  
182.0  
200.0  
203.0  
20.0  
20.0  
35.0  
33.0  
33.0  
35.0  
20.0  
20.0  
35.0  
35.0  
20.0  
20.0  
20.0  
20.0  
33.0  
33.0  
20.0  
20.0  
33.0  
35.0  
3000  
3000  
250  
250  
3000  
250  
3000  
250  
3000  
250  
3000  
250  
3000  
250  
3000  
250  
3000  
3000  
Pack Materials-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
1-Feb-2018  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS72719DSET  
TPS72719DSET  
TPS72719YFFR  
TPS72719YFFT  
TPS72725DSER  
TPS72725DSET  
TPS72727DSER  
TPS72727DSER  
TPS72727DSET  
TPS72727DSET  
TPS727285DSER  
TPS727285DSER  
TPS727285DSET  
TPS727285DSET  
TPS72728DSER  
TPS72728DSER  
TPS72728DSET  
TPS72728DSET  
TPS72728YFFR  
TPS72728YFFT  
TPS72730DSER  
TPS72730DSET  
TPS72730YFFR  
TPS72730YFFT  
TPS72733DSER  
TPS72733DSET  
TPS72733YFFR  
TPS72733YFFT  
TPS72748YFFR  
TPS72748YFFT  
TPS72750YFFR  
TPS72750YFFT  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
WSON  
WSON  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
DSBGA  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
DSE  
DSE  
YFF  
YFF  
YFF  
YFF  
YFF  
YFF  
6
6
4
4
6
6
6
6
6
6
6
6
6
6
6
6
6
6
4
4
6
6
4
4
6
6
4
4
4
4
4
4
250  
250  
205.0  
203.0  
182.0  
182.0  
203.0  
203.0  
203.0  
205.0  
203.0  
205.0  
205.0  
203.0  
203.0  
205.0  
205.0  
203.0  
203.0  
205.0  
182.0  
182.0  
205.0  
205.0  
182.0  
182.0  
205.0  
205.0  
182.0  
182.0  
182.0  
182.0  
182.0  
182.0  
200.0  
203.0  
182.0  
182.0  
203.0  
203.0  
203.0  
200.0  
203.0  
200.0  
200.0  
203.0  
203.0  
200.0  
200.0  
203.0  
203.0  
200.0  
182.0  
182.0  
200.0  
200.0  
182.0  
182.0  
200.0  
200.0  
182.0  
182.0  
182.0  
182.0  
182.0  
182.0  
33.0  
35.0  
20.0  
20.0  
35.0  
35.0  
35.0  
33.0  
35.0  
33.0  
33.0  
35.0  
35.0  
33.0  
33.0  
35.0  
35.0  
33.0  
20.0  
20.0  
33.0  
33.0  
20.0  
20.0  
33.0  
33.0  
20.0  
20.0  
20.0  
20.0  
20.0  
20.0  
3000  
250  
3000  
250  
3000  
3000  
250  
250  
3000  
3000  
250  
250  
3000  
3000  
250  
250  
3000  
250  
3000  
250  
3000  
250  
3000  
250  
3000  
250  
3000  
250  
3000  
250  
Pack Materials-Page 4  
IMPORTANT NOTICE AND DISCLAIMER  
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE  
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”  
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY  
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD  
PARTY INTELLECTUAL PROPERTY RIGHTS.  
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate  
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable  
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you  
permission to use these resources only for development of an application that uses the TI products described in the resource. Other  
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third  
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,  
damages, costs, losses, and liabilities arising out of your use of these resources.  
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on  
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable  
warranties or warranty disclaimers for TI products.  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2020, Texas Instruments Incorporated  

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