TPS73047DBVTG4 [TI]
LOW-NOISE, HIGH PSRR, RF 200-mA LOW-DROPOUT LINEAR REGULATORS; 低噪声，高PSRR ，射频200mA的低压差线性稳压器
| 型号： | TPS73047DBVTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-NOISE, HIGH PSRR, RF 200-mA LOW-DROPOUT LINEAR REGULATORS |
| 文件： | 总16页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS730xx
www.ti.com
SBVS054G–NOVEMBER 2004–REVISED DECEMBER 2006
LOW-NOISE, HIGH PSRR, RF 200-mA
LOW-DROPOUT LINEAR REGULATORS
FEATURES
DESCRIPTION
•
200-mA RF Low-Dropout Regulator
With Enable
The TPS730xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power-supply rejection ratio (PSRR), ultralow-noise,
fast start-up, and excellent line and load transient
responses a small SOT23 package. NanoStar™
packaging gives an ultrasmall footprint as well as an
ultralow profile and package weight, making it ideal
for portable applications such as handsets and
PDAs. Each device in the family is stable, with a
small 2.2µF ceramic capacitor on the output. The
TPS730xx family uses an advanced, proprietary
BiCMOS fabrication process to yield low dropout
voltages (e.g., 120mV at 200mA, TPS73030). Each
device achieves fast start-up times (approximately
•
Available in Fixed Voltages from 1.8V to 3.3V
and Adjustable (1.22V to 5.5V)
•
•
•
•
•
•
•
High PSRR (68dB at 1kHz)
Ultralow-Noise (23µVRMS, TPS73018)
Fast Start-Up Time (50µs)
Stable With a 2.2µF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (120mV at 200mA)
5- and 6-Pin SOT23 (DBV), and Wafer Chip
Scale (YZQ) Packages
50µs with
a 0.001µF bypass capacitor) while
consuming low quiescent current (170µA typical).
Moreover, when the device is placed in standby
mode, the supply current is reduced to less than
1µA. The TPS73018 exhibits approximately 23µVRMS
of output voltage noise at 2.8V output with a 0.01µF
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Cellular and Cordless Telephones
Bluetooth®, Wireless LAN
Handheld Organizers, PDAs
bypass
capacitor.
Applications
with
analog
components that are noise-sensitive, such as
portable RF electronics, benefit from the high PSRR
and low-noise features as well as the fast response
time.
DBV PACKAGE
(TOP VIEW)
TPS73028
TPS73028
OUT
NR
IN
1
2
5
RIPPLE REJECTION
vs
OUTPUT SPECTRAL NOISE DENSITY
vs
GND
FREQUENCY
FREQUENCY
0.30
100
90
3
4
EN
V
= 3.8 V
IN
I
= 200 mA
OUT
Fixed Option
C
C
= 2.2 µF
OUT
= 0.1 µF
0.25
0.20
80
NR
DBV PACKAGE
(TOP VIEW)
70
IN
GND
EN
OUT
FB
1
2
6
5
60
0.15
50
40
30
I
= 1 mA
OUT
I
= 10 mA
OUT
3
4
NR
0.10
0.05
I
= 200 mA
OUT
Adjustable Option
20
10
0
V
C
C
= 3.8 V
= 10 µF
IN
YZQ PACKAGE
(TOP VIEW)
OUT
= 0.01 µF
NR
0
100
1 k
10 k
100 k
10
100
1 k
10 k 100 k 1 M 10 M
IN
OUT
C3 C1
B2
A3 A1
Frequency (Hz)
Frequency (Hz)
NR
GND
EN
Figure 1.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth Sig, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2006, Texas Instruments Incorporated
TPS730xx
www.ti.com
SBVS054G–NOVEMBER 2004–REVISED DECEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS730xxyyyz
XX is nominal output voltage (for example, 28 = 2.8V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 1.2V to 4.5V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
over operating temperature range (unless otherwise noted)(1)
UNIT
VIN range
–0.3V to +6V
–0.3V to VIN + 0.3V
–0.3V to VIN + 0.3V
Internally limited
2kV
VEN range
VOUT range
Peak output current
ESD rating, HBM
ESD rating, CDM
500V
Continuous total power dissipation
Junction temperature range
Storage temperature range, Tstg
See Dissipation Ratings Table
–40°C to +150°C
–65°C to +150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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SBVS054G–NOVEMBER 2004–REVISED DECEMBER 2006
DISSIPATION RATINGS TABLE
T
A ≤ +25°C
POWER
RATING
TA = +70°C
POWER
RATING
TA = +85°C
POWER
RATING
DERATING FACTOR
BOARD
Low-K(1)
High-K(2)
Low-K(1)
High-K(2)
PACKAGE
DBV
RθJC
RθJA
ABOVE TA = +25°C
65°C/W
65°C/W
27°C/W
27°C/W
255°C/W
180°C/W
255°C/W
190°C/W
3.9mW/°C
5.6mW/°C
3.9mW/°C
5.3mW/°C
390mW
560mW
390mW
530mW
215mW
310mW
215mW
296mW
155mW
225mW
155mW
216mW
DBV
YZQ
YZQ
(1) The JEDEC low-K (1s) board design used to derive this data was a 3-inch × 3-inch, two layer board with 2 ounce copper traces on top
of the board.
(2) The JEDEC high-K (2s2p) board design used to derive this data was a 3-inch × 3-inch, multilayer board with 1 ounce internal power and
ground planes and 2 ounce copper traces on top and bottom of the board.
ELECTRICAL CHARACTERISTICS
over recommended operating temperature range TJ = –40 to +125°C, VEN = VIN, VIN = VOUT(nom) + 1 V(1), IOUT = 1mA,
COUT = 10µF, CNR = 0.01µF (unless otherwise noted). Typical values are at +25°C.
PARAMETER
VIN Input voltage(1)
TEST CONDITIONS
MIN
2.7
0
TYP
MAX
5.5
UNIT
V
IOUT Continuous output current
VFB Internal reference (TPS73001)
200
mA
V
1.201 1.225
1.250
5.5 –
VDO
Output voltage range (TPS73001)
VFB
V
Output voltage accuracy
0µA ≤ IOUT ≤ 200mA,
2.75V ≤ VIN < 5.5V
TJ = +25°C
–2%
285
VOUT(nom) +2%
V
(1)
Line regulation (∆VOUT%/∆VIN
)
VOUT + 1V ≤ VIN ≤ 5.5V
0µA ≤ IOUT ≤ 200mA,
IOUT = 200mA
0.05
5
%/V
mV
mV
mA
µA
Load regulation (∆VOUT%/∆IOUT
Dropout voltage(2)(VIN = VOUT(nom) – 0.1V)
)
120
210
600
250
1
Output current limit
VOUT = 0V
GND pin current
Shutdown current(3)
0µA ≤ IOUT ≤ 200mA
VEN = 0V, 2.7V ≤ VIN ≤ 5.5V
VFB = 1.8V
170
0.07
µA
FB pin current
1
µA
Power-supply ripple rejection TPS73028
f = 100kHz, TJ = +25°C,
IOUT = 200mA
CNR = 0.01µF
CNR = 0.001µF
68
33
50
dB
BW = 200Hz to 100kHz,
IOUT = 200mA
Output noise voltage (TPS73018)
µVRMS
Time, start-up (TPS73018)
High level enable input voltage
Low level enable input voltage
EN pin current
RL = 14Ω, COUT = 1µF
2.7V ≤ VIN ≤ 5.5V
2.7V ≤ VIN ≤ 5.5V
VEN = 0
µs
V
1.7
0
VIN
0.7
1
V
–1
µA
V
UVLO threshold
VCC rising
2.25
2.65
UVLO hysteresis
100
mV
(1) Minimum VIN is 2.7V or VOUT + VDO, whichever is greater.
(2) Dropout is not measured for the TPS73018 and TPS73025 since minimum VIN = 2.7V.
(3) For adjustable versions, this applies only after VIN is applied; then VEN transitions high to low.
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SBVS054G–NOVEMBER 2004–REVISED DECEMBER 2006
FUNCTIONAL BLOCK DIAGRAMS
ADJUSTABLE VERSION
IN
OUT
59 k
UVLO
2.45V
Current
Sense
R1
R2
ILIM
SHUTDOWN
GND
EN
_
+
FB
UVLO
Thermal
Shutdown
External to
the Device
QuickStart
Bandgap
Reference
1.22V
250 kΩ
V
ref
IN
NR
FIXED VERSION
IN
OUT
UVLO
2.45V
Current
Sense
GND
EN
SHUTDOWN
+
ILIM
R1
R2
_
UVLO
Thermal
Shutdown
R2 = 40 kΩ
QuickStart
Bandgap
Reference
1.22V
250 kΩ
V
ref
NR
IN
Table 1. Terminal Functions
TERMINAL
SOT23
ADJ
SOT23
FIXED
WCSP
FIXED
NAME
DESCRIPTION
Connecting an external capacitor to this pin bypasses noise generated by the internal
bandgap. This improves power-supply rejection and reduces output noise.
NR
4
4
3
B2
A3
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator
into shutdown mode. EN can be connected to IN if not used.
EN
3
FB
GND
IN
5
2
1
6
N/A
2
N/A
A1
This terminal is the feedback input voltage for the adjustable device.
Regulator ground
1
C3
C1
Input to the device.
Output of the regulator.
OUT
5
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SBVS054G–NOVEMBER 2004–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (SOT23 PACKAGE)
TPS73028
OUTPUT VOLTAGE
vs
TPS73028
OUTPUT VOLTAGE
vs
TPS73028
GROUND CURRENT
vs
OUTPUT CURRENT
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.805
2.804
2.803
2.802
2.801
2.800
2.799
250
200
2.805
2.800
2.795
2.790
2.785
V
= 3.8 V
= 10 µF
OUT
= 25°C
IN
V
C
= 3.8 V
IN
C
T
= 10 µF
I
= 1 mA
OUT
OUT
J
I
= 1 mA
OUT
I
= 200 mA
OUT
150
100
50
0
I
= 200 mA
OUT
2.798
2.797
2.780
2.775
V
C
= 3.8 V
= 10 µF
IN
2.796
OUT
2.795
0
−40 −25 −10 5 20 35 50 65 80 95 110 125
(°C)
50
100
(mA)
150
200
−40 −25−10 5 20 35 50 65 80 95 110 125
I
T
J
(°C)
T
J
OUT
Figure 2.
Figure 3.
Figure 4.
TPS73028 OUTPUT SPECTRAL
ROOT MEAN SQUARE OUTPUT
TPS73028
DROPOUT VOLTAGE
vs
NOISE DENSITY
vs
NOISE
vs
FREQUENCY
CNR
JUNCTION TEMPERATURE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
180
160
140
120
100
80
60
50
40
30
20
10
V
C
= 2.7 V
IN
V
= 2.8 V
= 200 mA
= 10 µF
V
I
C
= 3.8 V
OUT
IN
= 10 µF
I
= 200 mA
OUT
OUT
C
OUT
= 10 µF
OUT
= 0.001 µF
OUT
C
NR
C
= 0.0047 µF
I
= 200 mA
NR
C
OUT
= 0.01 µF
NR
C
= 0.1 µF
NR
60
40
I
= 10 mA
OUT
20
BW = 100 Hz to 100 kHz
0.01
0
0
100
1 k
10 k
100 k
−40 −25−10 5 20 35 50 65 80 95 110 125
0.001
0.1
Frequency (Hz)
T
(°C)
C
NR
(µF)
J
Figure 5.
Figure 6.
Figure 7.
TPS73028
RIPPLE REJECTION
vs
TPS73028 OUTPUT VOLTAGE,
ENABLE VOLTAGE
vs
TPS73028
LINE TRANSIENT RESPONSE
FREQUENCY
TIME (START-UP)
100
90
80
70
4.8
3.8
4
I
= 200 mA
OUT
V
V
= 3.8 V
2
0
IN
= 2.8 V
OUT
I
= 200 mA
OUT
60
C
T
= 2.2 µF
I
= 200 mA
OUT
OUT
= 25°C
50
40
30
C
C
= 2.2 µF
= 0.01 µF
J
OUT
C
NR
= 0.001 µF
dv
dt
0µ.4sV
NR
+
20
0
3
2
1
0
I
= 10 mA
OUT
C
= 0.0047 µF
= 0.01 µF
20
NR
V
= 3.8 V
= 10 µF
IN
-20
C
C
OUT
= 0.01 µF
10
0
C
NR
NR
10
100
1 k
10 k 100 k 1 M 10 M
0
20 40 60 80 100 120 140 160 180 200
0
10 20 30 40 50 60 70 80 90 100
Frequency (Hz)
Time (µs)
Time (µs)
Figure 8.
Figure 9.
Figure 10.
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SBVS054G–NOVEMBER 2004–REVISED DECEMBER 2006
TYPICAL CHARACTERISTICS (SOT23 PACKAGE) (continued)
DROPOUT VOLTAGE
TPS73028
LOAD TRANSIENT RESPONSE
vs
POWER-UP/POWER-DOWN
OUTPUT CURRENT
250
200
150
100
V
C
= 3.8 V
IN
V
R
= 3 V
= 15 Ω
OUT
20
= 10 µF
OUT
L
0
T
= 125°C
J
−20
T
J
= 25°C
−40
300
di
dt
0.02A
µs
+
V
IN
V
OUT
200
100
T
= −55°C
J
50
0
1mA
0
0
50 100 150200 250 300 350 400 450 500
0
20 40 60 80 100 120 140 160 180 200
(mA)
1s/div
I
Time (µs)
OUT
Figure 11.
Figure 12.
Figure 13.
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
EQUIVALENT SERIES RESISTANCE
(ESR)
vs
OUTPUT CURRENT
(ESR)
vs
OUTPUT CURRENT
100
10
100
10
C
= 2.2 µF
OUT
C
= 10 µF
OUT
= 5.5 V
V
= 5.5 V, V
≥ 1.5 V
IN
OUT
V
IN
= −40°C to 125°C
T
J
= −40°C to 125°C
T
J
Region of Instability
Region of Instability
1
1
0.1
0.1
Region of Stability
Region of Stability
0.01
0.01
0.20
0
0.02
0.04
0.06
(A)
0.08
0.20
0
0.02
0.04
0.06
(A)
0.08
I
I
OUT
OUT
Figure 14.
Figure 15.
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SBVS054G–NOVEMBER 2004–REVISED DECEMBER 2006
APPLICATION INFORMATION
The TPS730xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive
battery-operated equipment. The device features extremely low dropout voltages, high PSRR, ultralow output
noise, low quiescent current (170µA typically), and enable-input to reduce supply currents to less than 1µA when
the regulator is turned off.
A typical application circuit is shown in Figure 16.
VOUT
VIN
VIN
VOUT
IN
OUT
NR
TPS730xx
EN
GND
µ
µ
2.2 F
0.1
F
(1)
µ
0.01
F
NOTE: (1) This capacitor is optional.
Figure 16. Typical Application Circuit
External Capacitor Requirements
A 0.1µF or larger ceramic input bypass capacitor, connected between IN and GND and located close to the
TPS730xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A
higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated or the
device is located several inches from the power source.
Like most low dropout regulators, the TPS730xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance is 2.2µF. Any 2.2µF or larger
ceramic capacitor is suitable, provided the capacitance does not vary significantly over temperature. If load
current is not expected to exceed 100mA, a 1.0µF ceramic capacitor can be used.
The internal voltage reference is a key source of noise in an LDO regulator. The TPS730xx has an NR pin which
is connected to the voltage reference through a 250kΩ internal resistor. The 250kΩ internal resistor, in
conjunction with an external bypass capacitor connected to the NR pin, creates a low pass filter to reduce the
voltage reference noise and, therefore, the noise at the regulator output. In order for the regulator to operate
properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR
drop across the internal resistor thus creating an output error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor should be no more than 0.1µF to ensure that it is fully charged
during the quickstart time provided by the internal switch shown in the Functional Block Diagrams.
As an example, the TPS73018 exhibits only 23µVRMS of output voltage noise using a 0.01µF ceramic bypass
capacitor and a 2.2µF ceramic output capacitor. Note that the output starts up slower as the bypass capacitance
increases due to the RC time constant at the NR pin that is created by the internal 250kΩ resistor and external
capacitor.
Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the
GND pin of the device.
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APPLICATION INFORMATION (continued)
Power Dissipation and Junction Temperature
Specified regulator operation is assured to a junction temperature of +125°C; the maximum junction temperature
should be restricted to +125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max)
.
The maximum power dissipation limit is determined using Equation 1:
TJ max *TA
PD max
+
(
)
RQJA
(1)
Where:
•
•
•
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package (see the Dissipation Ratings Table).
TA is the ambient temperature.
The regulator dissipation is calculated using Equation 2:
ǒ
Ǔ
PD + VIN*VOUT IOUT
(2)
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the thermal
protection circuit.
Programming the TPS73001 Adjustable LDO Regulator
The output voltage of the TPS73001 adjustable regulator is programmed using an external resistor divider as
shown in Figure 17. The output voltage is calculated using Equation 3:
R1
R2
ǒ1 ) Ǔ
VOUT + VREF
(3)
Where:
•
VREF = 1.225V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50µA divider current. Lower value resistors can be
used for improved noise performance, but the solution consumes more power. Higher resistor values should be
avoided as leakage current into/out of FB across R1/R2 creates an offset voltage that artificially
increases/decreases the feedback voltage and thus erroneously decreases/increases VOUT. The recommended
design procedure is to choose R2 = 30.1kΩ to set the divider current at 50µA, C1 = 15pF for stability, and then
calculate R1 using Equation 4:
VOUT
R1 =
- 1 ´ R2
VREF
(4)
In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be
placed between OUT and FB. For voltages < 1.8V, the value of this capacitor should be 100pF. For voltages >
1.8V, the approximate value of this capacitor can be calculated as shown in Equation 5:
*7
(3 x 10 ) x (R1 ) R2)
C1
+
(R1 x R2)
(5)
The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is
not used (such as in a unity-gain configuration) or if an output voltage < 1.8V is chosen, then the minimum
recommended output capacitor is 4.7µF instead of 2.2µF.
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APPLICATION INFORMATION (continued)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VIN
VOUT
IN
OUT
FB
TPS73001
OUTPUT
R1
R2
C1
1mF
R1
R2
C1
EN
NR
VOLTAGE
2.2mF
GND
1.22V
2.5V
3.3V
3.6V
short
open
0pF
0.01mF
22pF
31.6kW
51kW
59kW
30.1kW
30.1kW
30.1kW
15pF
15pF
Figure 17. TPS73001 Adjustable LDO Regulator Programming
Regulator Protection
The TPS730xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (for example, during power-down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting
might be appropriate.
The TPS730xx features internal current limiting and thermal protection. During normal operation, the TPS730xx
limits output current to approximately 400mA. When current limiting engages, the output voltage scales back
linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package or the absolute maximum
voltage ratings of the device. If the temperature of the device exceeds approximately +165°C, thermal-protection
circuitry shuts it down. Once the device has cooled down to below approximately +140°C, regulator operation
resumes.
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APPLICATION INFORMATION (continued)
TPS730xxYZQ NanoStar™ Wafer Chip Scale Information
0,79
0,84
1,30
1,34
0.625 Max
NOTES:A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration.
D. This package is tin-lead (SnPb); consult the factory for availability of lead-free material.
NanoStar is a trademark of Texas Instruments.
Figure 18. NanoStar™ Wafer Chip Scale Package
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PACKAGE OPTION ADDENDUM
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7-Dec-2006
PACKAGING INFORMATION
Orderable Device
TPS73001DBVR
TPS73001DBVRG4
TPS73001DBVT
TPS73001DBVTG4
TPS73018DBVR
TPS73018DBVRG4
TPS73018DBVT
TPS73018DBVTG4
TPS73018YZQR
TPS73018YZQT
TPS73025DBVR
TPS73025DBVRG4
TPS73025DBVT
TPS73025DBVTG4
TPS73025YZQR
TPS73025YZQT
TPS730285DBVR
TPS730285DBVRG4
TPS730285DBVT
TPS730285DBVTG4
TPS730285YZQR
TPS730285YZQT
TPS73028DBVR
TPS73028DBVRG4
TPS73028DBVT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
6
6
6
6
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
YZQ
YZQ
DBV
DBV
DBV
DBV
YZQ
YZQ
DBV
DBV
DBV
DBV
YZQ
YZQ
DBV
DBV
DBV
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS &
no Sb/Br)
SNAG
Level-1-260C-UNLIM
250 Green (RoHS &
no Sb/Br)
SNAG
Level-1-260C-UNLIM
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS &
no Sb/Br)
SNAG
Level-1-260C-UNLIM
250 Green (RoHS &
no Sb/Br)
SNAG
Level-1-260C-UNLIM
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS &
no Sb/Br)
SNAG
Level-1-260C-UNLIM
250 Green (RoHS &
no Sb/Br)
SNAG
Level-1-260C-UNLIM
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2006
Orderable Device
TPS73028DBVTG4
TPS73028YZQR
TPS73028YZQT
TPS73030DBVR
TPS73030DBVRG4
TPS73030DBVT
TPS73030DBVTG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
5
5
5
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
YZQ
YZQ
DBV
DBV
DBV
DBV
3000 Green (RoHS &
no Sb/Br)
SNAG
Level-1-260C-UNLIM
250 Green (RoHS &
no Sb/Br)
SNAG
Level-1-260C-UNLIM
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73030YZQR
TPS73030YZQT
TPS73033DBVR
PREVIEW
PREVIEW
ACTIVE
DSBGA
DSBGA
SOT-23
YZQ
YZQ
DBV
5
5
5
3000
250
TBD
TBD
Call TI
Call TI
Call TI
Call TI
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73033DBVRG4
TPS73033DBVT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73033DBVTG4
TPS73047DBVR
TPS73047DBVRG4
TPS73047DBVT
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS73047DBVTG4
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
7-Dec-2006
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
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