TPS73201QDRBRQ1 [TI]
CAP-FREE NMOS 250-mA LOW-DROPOUT REGULATOR WITH REVERSE-CURRENT PROTECTION; 无电容NMOS 250毫安低压降与反向电流保护稳压器
| 型号： | TPS73201QDRBRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | CAP-FREE NMOS 250-mA LOW-DROPOUT REGULATOR WITH REVERSE-CURRENT PROTECTION |
| 文件： | 总26页 (文件大小：1024K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
www.ti.com ........................................................................................................................................................... SGLS303D–MAY 2005–REVISED MARCH 2009
CAP-FREE NMOS 250-mA LOW-DROPOUT REGULATOR
WITH REVERSE-CURRENT PROTECTION
1
FEATURES
DESCRIPTION
•
Qualified for Automotive Applications
The TPS732xx family of low-dropout (LDO) voltage
regulators uses a new topology: an NMOS pass
element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly constant
over all values of output current.
•
Stable with No Output Capacitor or Any Value
or Type of Capacitor
•
•
Input Voltage Range: 1.7 V to 5.5 V
Ultralow Dropout Voltage:
40 mV Typ at 250 mA
•
•
Excellent Load Transient Response—With or
Without Optional Output Capacitor
The TPS732xx uses an advanced BiCMOS process
to yield high precision while delivering low dropout
voltages and low ground pin current. Current
consumption, when not enabled, is under 1 µA and
ideal for portable applications. The extremely low
output noise (30 µVRMS with 0.1 µF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
New NMOS Topology Provides Low Reverse
Leakage Current
•
•
•
Low Noise: 30 µVRMS Typ (10 kHz to 100 kHz)
0.5% Initial Accuracy
1% Overall Accuracy (Line, Load, and
Temperature)
•
•
Less Than 1 µA Max IQ in Shutdown Mode
DRB PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
Thermal Shutdown and Specified Min/Max
Current Limit Protection
OUT
NC
1
2
3
4
8
7
6
5
IN
1
2
3
5
IN
GND
EN
OUT
•
Available in Multiple Output Voltage Versions
NC
NC
EN
–
Fixed Outputs of 1.2 V, 1.5 V, 1.6 V, 1.8 V,
2.5 V, 3 V, 3.3 V, and 5 V
NR/FB
GND
4
NR/FB
–
–
Adjustable Outputs From 1.2 V to 5.5 V
Custom Outputs Available
NC – No internal connection
Optional
Optional
APPLICATIONS
VIN
VOUT
IN
OUT
TPS732xx
GND
•
•
•
•
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry Such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
EN
NR
Optional
Typical Application Circuit for Fixed-Voltage Versions
Figure 1.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2009, Texas Instruments Incorporated
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
SGLS303D–MAY 2005–REVISED MARCH 2009........................................................................................................................................................... www.ti.com
ORDERING INFORMATION(1)
VOUT
TJ
PACKAGE(3)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
(TYP)(2)
SOT23-5 – DBV
Reel of 3000
Reel of 3000
Reel of 3000
Reel of 3000
Reel of 3000
Reel of 3000
Reel of 3000
Reel of 3000
Reel of 3000
TPS73201QDBVRQ1
TPS73201QDRBRQ1
TPS73215DBVRQ1(5)
TPS73216DBVRQ1(5)
TPS73218DBVRQ1(5)
TPS73225QDBVRQ1
TPS73230DBVRQ1(5)
TPS73233DBVRQ1(5)
TPS73250DBVRQ1(5)
PJOQ
Adjustable
or 1.2 V(4)
VSON-8 – DRB
SOT23-5 – DBV
SOT23-5 – DBV
SOT23-5 – DBV
SOT23-5 – DBV
SOT23-5 – DBV
SOT23-5 – DBV
SOT23-5 – DBV
PSAQ
1.5 V
1.6 V
1.8 V
2.5 V
3 V
PREVIEW
PREVIEW
PREVIEW
PJNQ
–40°C to 125°C
PREVIEW
PREVIEW
PREVIEW
3.3 V
5 V
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Custom output voltages from 1.3 V to 4 V in 100-mV increments are available on a quick-turn basis for prototyping. Production
quantities are available; minimum order quantities apply. Contact Texas Instruments for details and availability.
(3) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(4) For fixed 1.2-V operation, tie FB to OUT.
(5) Product Preview
ABSOLUTE MAXIMUM RATINGS
over operating junction temperature range unless otherwise noted(1)
TPS732xx
–0.3 to 6
UNIT
VIN range
V
V
V
VEN range
–0.3 to 6
VOUT range
–0.3 to 5.5
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM(2)
ESD rating, CDM(2)
ESD rating, MM(2)
Internally limited
Indefinite
See Power Dissipation Ratings
–55 to +150
–65 to +150
(H2) 4
°C
°C
kV
kV
V
(C4) 1
(M2) 200
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) ESD Protection Level per AEC Q100 Classification
POWER DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
PACKAGE
RθJC
RθJA
POWER RATING POWER RATING POWER RATING
Low-K(2)
High-K(3)
DBV
DBV
DRB
64°C/W
64°C/W
1.2°C/W
255°C/W
180°C/W
40°C/W
3.9 mW/°C
5.6 mW/°C
25.0 mW/°C
390 mW
560 mW
2.50 W
215 mW
310 mW
1.38 W
155 mW
225 mW
1 W
(3)
High-K
(1) See Power Dissipation in the Application Information section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 inch x 3 inch, two-layer board with 2-ounce copper traces on top
of the board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on the top and bottom of the board.
2
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Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
www.ti.com ........................................................................................................................................................... SGLS303D–MAY 2005–REVISED MARCH 2009
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V(1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 µF, unless otherwise noted. Typical values are at TJ = 25°C
PARAMETER
Input voltage range(1)
TEST CONDITIONS
MIN
1.7
TYP
MAX UNIT
VIN
5.5
1.21
V
V
V
VFB
Internal reference (TPS73201)
Output voltage range (TPS73201)(2)
Accuracy(1)
TJ = 25°C
TJ = 25°C
1.198
VFB
1.2
5.5–VDO
+0.5%
Nominal
–0.5%
VOUT
(VOUT + 0.5 V) ≤ VIN ≤ 5.5 V,
10 mA ≤ IOUT ≤ 250 mA
VIN, IOUT, and TJ
–1%
0.5%
+1%
ΔVOUT%/ΔVIN
Line regulation(1)
(VOUT(nom) + 0.5 V) ≤ VIN ≤ 5.5 V
1 mA ≤ IOUT ≤ 250 mA
0.06
0.002
%/V
ΔVOUT%/ΔIOUT Load regulation
%/mA
10 mA ≤ IOUT ≤ 250 mA
0.0008
Dropout voltage(3)
VDO
IOUT = 250 mA
40
150
600
mV
(VIN = VOUT (nom) – 0.1 V)
ZO(DO)
ICL
Output impedance in dropout
1.7 V ≤ VIN ≤ (VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0 V
)
0.25
425
Ω
Output current limit
250
mA
mA
µA
ISC
Short-circuit current
300
IREV
Reverse leakage current(4) (–IIN
)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
10
550
950
1
IOUT = 10 mA (IQ)
IOUT = 250 mA
400
IGND
Ground pin current
µA
µA
dB
650
ISHDN
PSRR
Shutdown current (IGND
)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5
0.02
f = 100 Hz, IOUT = 250 mA
f = 10 kHz, IOUT = 250 mA
COUT = 10 µF, No CNR
58
Power-supply rejection ratio
(ripple rejection)
37
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10 Hz – 100 kHz
VN
µVRMS
µs
COUT= 10 µF, CNR = 0.01 µF
VOUT = 3 V, RL = 30 Ω
COUT = 1 µF, CNR= 0.01 µF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
Enable high (enabled)
1.7
0
VIN
0.5
0.1
V
V
Enable low (shutdown)
Enable pin current (enabled)
VEN = 5.5 V
0.02
160
140
µA
Shutdown, Temperature increasing
TSD
Thermal shutdown temperature
°C
Reset,
Temperature decreasing
(1) Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
(2) TPS73201 is tested at VOUT = 2.5 V.
(3) VDO is not measured for the TPS73215 or TPS73216, because minimum VIN = 1.7 V.
(4) Fixed-voltage versions only; see the Application Information section for more information.
Copyright © 2005–2009, Texas Instruments Incorporated
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3
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
SGLS303D–MAY 2005–REVISED MARCH 2009........................................................................................................................................................... www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
IN
Charge
Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 2. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
OUT
R
1
R
2
Charge
Pump
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
5.0V
Short
Open
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
78.7kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
24.9kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
OUT
Current
Limit
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
R
R
19kΩ for best
1
2
GND
Ω
80k
Ω
8k
R1
R2
accuracy.
FB
Figure 3. Adjustable Voltage Version
4
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Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
www.ti.com ........................................................................................................................................................... SGLS303D–MAY 2005–REVISED MARCH 2009
PIN ASSIGNMENTS
DRB PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
OUT
NC
1
2
3
4
8
7
6
5
IN
1
2
3
5
IN
GND
EN
OUT
NC
NC
EN
NR/FB
GND
4
NR/FB
NC – No internal connection
TERMINAL FUNCTIONS
TERMINAL
NO.
DESCRIPTION
NAME
DBV
DRB
IN
1
2
8
Unregulated input supply
GND
4, Pad Ground
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown
mode. See the Shutdown section under Applications Information for more details. EN can be connected to IN
if not used.
EN
3
5
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by the
internal bandgap. This allows output noise to be reduced to low levels.
NR
FB
4
4
3
3
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set the
output voltage of the device.
NC
—
5
2, 6, 7 No internal connection
Output of the regulator. There are no output capacitor requirements for stability.
OUT
1
Copyright © 2005–2009, Texas Instruments Incorporated
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5
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
SGLS303D–MAY 2005–REVISED MARCH 2009........................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted
LOAD REGULATION
Referred to IOUT = 10mA
LINE REGULATION
0.5
0.4
0.3
0.2
0.1
0
0.20
0.15
0.10
0.05
0
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
−
_
40 C
_
+25 C
_
+25 C
_
_
+125 C
+125 C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
0.05
0.10
0.15
0.20
−
_
40 C
−
−
−
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
50
100
IOUT (mA)
Figure 4.
150
200
250
−
VIN VOUT (V)
Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
TPS73225DBV
100
80
60
40
20
0
100
80
60
50
20
0
TPS73225DBV
_
+125 C
_
+25 C
−
_
40 C
−
−
25
0
50
100
IOUT (mA)
Figure 6.
150
200
250
50
0
25
50
75
100
125
_
Temperature ( C)
Figure 7.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
IOUT = 10mA
All Voltage Versions
IOUT = 10mA
25
20
15
10
5
6
4
2
0
0
_
VOUT Error (%)
Worst Case dVOUT/dT (ppm/ C)
Figure 8.
Figure 9.
6
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Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
www.ti.com ........................................................................................................................................................... SGLS303D–MAY 2005–REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
1000
900
800
700
600
500
400
300
200
100
0
800
700
600
500
400
300
200
100
0
IOUT = 250mA
VIN = 5.5V
VIN = 4V
VIN = 2V
VIN = 5.5V
VIN = 4V
VIN = 2V
−
−
25
0
50
100
150
OUT (mA)
200
250
50
0
25
50
75
100
125
_
I
Temperature ( C)
Figure 10.
Figure 11.
CURRENT LIMIT vs VOUT
(FOLDBACK)
GROUND PIN CURRENT IN SHUTDOWN
vs TEMPERATURE
500
450
400
350
300
250
200
150
100
50
1
VENABLE = 0.5V
VIN = VOUT + 0.5V
ICL
ISC
0.1
TPS73233
0.5
0
0.01
−
−
25
0
1.0
1.5
2.0
2.5
3.0
3.5
50
0
25
50
75
100
125
_
VOUT (V)
Temperature ( C)
Figure 12.
CURRENT LIMIT vs VIN
Figure 13.
CURRENT LIMIT vs TEMPERATURE
600
550
500
450
400
350
300
250
600
550
500
450
400
350
300
250
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
_
VIN (V)
Temperature ( C)
Figure 14.
Figure 15.
Copyright © 2005–2009, Texas Instruments Incorporated
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Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
SGLS303D–MAY 2005–REVISED MARCH 2009........................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
IOUT = 100mA
COUT = Any
IOUT = 1mA
µ
COUT = 1 F
IOUT = 1mA
COUT = 10 F
µ
IO = 100mA
µ
C
O = 1 F
IOUT = 1mA
COUT = Any
IOUT = 100mA
COUT = 10 F
Frequency = 100kHz
µ
C
C
= 10µF
= 0.01µF
IOUT = Any
COUT = 0 F
OUT
µ
NR
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
−
VIN VOUT (V)
Frequency (Hz)
Figure 16.
Figure 17.
NOISE SPECTRAL DENSITY
NOISE SPECTRAL DENSITY
CNR = 0 µF
CNR = 0.01 µF
1
1
µ
COUT = 1 F
µ
COUT = 1 F
µ
COUT = 0 F
0.1
0.1
µ
COUT = 10 F
µ
COUT = 0 F
µ
COUT = 10 F
IOUT = 150mA
IOUT = 150mA
0.01
0.01
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 18.
Figure 19.
RMS NOISE VOLTAGE vs COUT
RMS NOISE VOLTAGE vs CNR
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
VOUT = 3.3V
VOUT = 1.5V
60
40
20
µ
CNR = 0.01 F
µ
COUT = 0 F
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p
10p
100p
1n
10n
µ
COUT ( F)
CNR (F)
Figure 20.
Figure 21.
8
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Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
www.ti.com ........................................................................................................................................................... SGLS303D–MAY 2005–REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted
TPS73233
LOAD TRANSIENT RESPONSE
TPS73233
LINE TRANSIENT RESPONSE
µ
COUT = 0 F
VIN = 3.8V
IOUT = 250mA
50mV/tick
50mV/tick
VOUT
VOUT
VOUT
µ
COUT = 0 F
50mV/div
VOUT
µ
OUT = 1 F
C
µ
COUT = 100 F
µ
COUT = 10 F
50mV/div
1V/div
VOUT
50mV/tick
50mA/tick
dVIN
dt
5.5V
µ
= 0.5V/
s
250mA
4.5V
VIN
10mA
IOUT
µ
µ
10 s/div
10 s/div
Figure 22.
Figure 23.
TPS73233
TURN-ON RESPONSE
TPS73233
TURN-OFF RESPONSE
Ω
Ω
RL = 1k
RL = 20
VOUT
µ
COUT = 0
F
COUT = 10µF
RL = 20Ω
COUT = 1µF
RL = 20Ω
1V/div
1V/div
1V/div
1V/div
µ
COUT = 1
F
Ω
RL = 1k
RL = 20Ω
COUT = 10
µ
COUT = 0
F
µ
F
VOUT
2V
2V
VEN
0V
0V
VEN
µ
100 s/div
µ
100 s/div
Figure 24.
Figure 25.
TPS73233
POWER UP / POWER DOWN
IENABLE vs TEMPERATURE
10
1
6
5
4
3
2
1
0
VIN
VOUT
0.1
0.01
−
−
1
2
50ms/div
−
−
25
50
0
25
50
75
100
125
Temperature (°C)
Figure 26.
Figure 27.
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TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
SGLS303D–MAY 2005–REVISED MARCH 2009........................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF, unless otherwise
noted
TPS73201
RMS NOISE VOLTAGE vs CADJ
TPS73201
IFB vs TEMPERATURE
60
55
50
45
40
35
30
25
20
160
140
120
100
80
60
VOUT = 2.5V
40
µ
COUT = 0 F
Ω
R1 = 39.2k
20
10Hz < Frequency < 100kHz
0
10p
100p
1n
10n
−
−
25
50
0
25
50
75
100
125
CFB (F)
_
Temperature ( C)
Figure 28.
Figure 29.
TPS73201
TPS73201
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10nF
VOUT = 2.5V
Ω
R1 = 39.2k
CFB = 10nF
µ
COUT = 0 F
µ
COUT = 0 F
VOUT
VOUT
100mV/div
100mV/div
100mV/div
100mV/div
µ
COUT = 10 F
µ
COUT = 10 F
VOUT
VOUT
4.5V
250mA
3.5V
VIN
10mA
IOUT
µ
5 s/div
µ
10 s/div
Figure 30.
Figure 31.
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Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
www.ti.com ........................................................................................................................................................... SGLS303D–MAY 2005–REVISED MARCH 2009
APPLICATION INFORMATION
The TPS732xx belongs to a family of new generation LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse current blockage, and freedom from output capacitor constraints.
These features, combined with low noise and an enable input, make the TPS732xx ideal for portable
applications. This regulator family offers a wide selection of fixed output voltage versions and an adjustable
output version. All versions have thermal and over-current protection, including foldback current limit.
Figure 32 shows the basic circuit connections for the fixed voltage models. Figure 33 gives the connections for
the adjustable output version (TPS73201).
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
TPS732xx
GND
EN
NR
Optional bypass
capacitor to reduce
output noise.
Figure 32. Typical Application Circuit for Fixed-Voltage Versions
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
FB
TPS732xx
R1
R2
CFB
EN
GND
Optional capacitor
reduces output noise.
(R1 + R2)
×
1.204
VOUT
=
R2
Figure 33. Typical Application Circuit for
Adjustable-Voltage Versions
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 33. Sample resistor values
for common output voltages are shown in Figure 3. For best accuracy, make the parallel combination of R1 and
R2 approximately 19 kΩ.
Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-µF to
1-µF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and
improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if
large, fast rise-time load transients are anticipated or the device is located several inches from the power source.
The TPS732xx does not require an output capacitor for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available types and values of capacitors. In applications where
VIN – VOUT < 0.5 V and multiple low ESR capacitors are in parallel, ringing may occur when the product of COUT
and total ESR drops below 50 nF. Total ESR includes all parasitic resistances, including capacitor ESR and
board, socket, and solder joint resistance. In most applications, the sum of capacitor ESR and trace resistance
will meet this requirement.
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TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
SGLS303D–MAY 2005–REVISED MARCH 2009........................................................................................................................................................... www.ti.com
Output Noise
A precision band-gap reference is used to generate the internal reference voltage, VREF. This reference is the
dominant noise source within the TPS732xx and it generates approximately 32 µVRMS (10 Hz to 100 kHz) at the
reference output (NR). The regulator control loop gains up the reference noise with the same gain as the
reference voltage, so that the noise voltage of the regulator is approximately given by:
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
R2
(1)
Since the value of VREF is 1.2 V, this relationship reduces to:
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
(2)
for the case of no CNR
.
An internal 27-kΩ resistor in series with the noise reduction pin (NR) forms a low-pass filter for the voltage
reference when an external noise reduction capacitor, CNR, is connected from NR to ground. For CNR = 10 nF,
the total noise in the 10-Hz to 100-kHz bandwidth is reduced by a factor of ~3.2, giving the approximate
relationship:
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
(3)
for CNR = 10 nF.
This noise reduction effect is shown as RMS Noise Voltage vs CNR in the Typical Characteristics section.
The TPS73201 adjustable version does not have the noise-reduction pin available. However, connecting a
feedback capacitor, CFB, from the output to the FB pin will reduce output noise and improve load transient
performance.
The TPS732xx uses an internal charge pump to develop an internal supply voltage sufficient to drive the gate of
the NMOS pass element above VOUT. The charge pump generates ~250 µV of switching noise at ~2 MHz;
however, charge-pump noise contribution is negligible at the output of the regulator for most values of IOUT and
COUT
.
Board Layout Recommendation to Improve PSRR and Noise Performance
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the
PCB be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the
GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the
GND pin of the device.
Internal Current Limit
The TPS732xx internal current limit helps protect the regulator during fault conditions. Foldback helps to protect
the regulator from damage during output short-circuit conditions by reducing current limit when VOUT drops below
0.5 V. See Figure 12 in the Typical Characteristics section for a graph of IOUT vs VOUT
.
Shutdown
The Enable pin is active high and is compatible with standard TTL-CMOS levels. VEN below 0.5 V (max) turns
the regulator off and drops the ground pin current to approximately 10 nA. When shutdown capability is not
required, the Enable pin can be connected to VIN. When a pullup resistor is used, and operation down to 1.8 V is
required, use pullup resistor values below 50 kΩ.
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Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
www.ti.com ........................................................................................................................................................... SGLS303D–MAY 2005–REVISED MARCH 2009
Dropout Voltage
The TPS732xx uses an NMOS pass transistor to achieve extremely low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the NMOS pass device is in its linear region of operation and the input-to-output
resistance is the RDS-ON of the NMOS pass element.
For large step changes in load current, the TPS732xx requires a larger voltage drop from VIN to VOUT to avoid
degraded transient response. The boundary of this transient dropout region is approximately twice the dc
dropout. Values of VIN – VOUT above this line ensure normal transient response.
Operating in the transient dropout region can cause an increase in recovery time. The time required to recover
from a load transient is a function of the magnitude of the change in load current rate, the rate of change in load
current, and the available headroom (VIN to VOUT voltage drop). Under worst-case conditions [full-scale
instantaneous load change with (VIN – VOUT) close to dc dropout levels], the TPS732xx can take a couple of
hundred microseconds to return to the specified regulation accuracy.
Transient Response
The low open-loop output impedance provided by the NMOS pass element in a voltage follower configuration
allows operation without an output capacitor for many applications. As with any regulator, the addition of a
capacitor (nominal value 1 µF) from the output pin to ground will reduce undershoot magnitude but increase
duration. In the adjustable version, the addition of a capacitor, CFB, from the output to the adjust pin will also
improve the transient response.
The TPS732xx does not have active pulldown when the output is over-voltage. This allows applications that
connect higher voltage sources, such as alternate power supplies, to the output. This also results in an output
overshoot of several percent if the load current quickly drops to zero when a capacitor is connected to the output.
The duration of overshoot can be reduced by adding a load resistor. The overshoot decays at a rate determined
by output capacitor COUT and the internal/external load resistance. The rate of decay is given by:
(Fixed voltage version)
VOUT
dVńdt +
COUT 80kW
(4)
(Adjustable voltage version)
VOUT
dVńdt +
(
)
COUT 80kW ø R1 ) R2
(5)
Reverse Current
The NMOS pass element of the TPS732xx provides inherent protection against current flow from the output of
the regulator to the input when the gate of the pass device is pulled low. To ensure that all charge is removed
from the gate of the pass element, the enable pin must be driven low before the input voltage is removed. If this
is not done, the pass element may be left on due to stored charge on the gate.
After the enable pin is driven low, no bias voltage is needed on any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out of the IN pin due to voltage applied on the OUT pin. There
will be additional current flowing into the OUT pin due to the 80-kΩ internal resistor divider to ground (see
Figure 2 and Figure 3).
For the TPS73201, reverse current may flow when VFB is more than 1 V above VIN.
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Product Folder Link(s): TPS73201-Q1 TPS73215-Q1 TPS73216-Q1 TPS73218-Q1 TPS73225-Q1 TPS73230-Q1
TPS73233-Q1 TPS73250-Q1
TPS73201-Q1, TPS73215-Q1, TPS73216-Q1
TPS73218-Q1, TPS73225-Q1, TPS73230-Q1
TPS73233-Q1, TPS73250-Q1
SGLS303D–MAY 2005–REVISED MARCH 2009........................................................................................................................................................... www.ti.com
Thermal Protection
Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the
device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off. This limits the dissipation of the regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should
trigger at least 35°C above the maximum expected ambient condition of your application. This produces a
worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS732xx has been designed to protect against overload conditions. It
was not intended to replace proper heatsinking. Continuously running the TPS732xx into thermal shutdown will
degrade device reliability.
Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are shown in the Power
Dissipation Ratings table. Using heavier copper will increase the effectiveness in removing heat from the device.
The addition of plated through-holes to heat-dissipating layers will also improve the heat-sink effectiveness.
Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the
output current times the voltage drop across the output pass element (VIN to VOUT):
PD + (VIN * VOUT) IOUT
(6)
Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required
output voltage.
Package Mounting
Solder pad footprint recommendations for the TPS732xx are presented in the Solder Pad Recommendations for
Surface-Mount Devices (SBFA015) application bulletin, available from the Texas Instruments web site at
www.ti.com.
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TPS73233-Q1 TPS73250-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS73201QDBVRQ1
TPS73201QDRBRQ1
TPS73225QDBVRQ1
TPS73250QDCQRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SON
DBV
DRB
DBV
DCQ
5
8
5
6
3000
3000
3000
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-3-260C-168 HR
SOT-23
SOT-223
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73201-Q1, TPS73225-Q1, TPS73250-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Jul-2012
Catalog: TPS73201, TPS73225, TPS73250
•
Enhanced Product: TPS73201-EP, TPS73225-EP, TPS73250-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73250QDCQRQ1 SOT-223 DCQ
6
2500
330.0
12.4
7.05
7.45
1.88
8.0
12.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-223 DCQ
SPQ
Length (mm) Width (mm) Height (mm)
358.0 335.0 35.0
TPS73250QDCQRQ1
6
2500
Pack Materials-Page 2
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