TPS734XX_V01 [TI]
250mA, Low Quiescent Current, Ultra-Low Noise, High PSRR Low-Dropout Linear Regulator;
| 型号： | TPS734XX_V01 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 250mA, Low Quiescent Current, Ultra-Low Noise, High PSRR Low-Dropout Linear Regulator |
| 文件： | 总23页 (文件大小：1889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS734xx
www.ti.com ........................................................................................................................................ SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009
250mA, Low Quiescent Current, Ultra-Low Noise, High PSRR
Low-Dropout Linear Regulator
1
FEATURES
DESCRIPTION
2
•
250mA Low Dropout Regulator with EN
The TPS734xx family of low-dropout (LDO),
low-power linear regulators offers excellent ac
performance with very low ground current. High
power-supply rejection ratio (PSRR), low noise, fast
start-up, and excellent line and load transient
response are provided while consuming a very low
44µA (typical) ground current. The TPS734xx is
stable with ceramic capacitors and uses an advanced
BiCMOS fabrication process to yield a typical dropout
voltage of 125mV at 250mA output. The TPS734xx
uses a precision voltage reference and feedback loop
to achieve overall accuracy of 2% over all load, line,
process, and temperature variations. It is fully
specified from TJ = –40°C to +125°C and is offered in
low-profile ThinSOT-23, 2mm × 2mm SON, and 3mm
x 3mm SON packages that are ideal for wireless
handsets, printers, and WLAN cards.
•
•
Low IQ: 44µA
Multiple Output Voltage Versions Available:
–
Fixed Outputs of 1.0V to 4.3V Using
Innovative Factory EEPROM Programming
–
Adjustable Outputs from 1.25V to 6.2V
•
•
•
•
High PSRR: 60dB at 1kHz
Ultra-low Noise: 28µVRMS
Fast Start-Up Time: 45µs
Stable with a Low-ESR, 2.0µF Typical Output
Capacitance
•
•
•
•
Excellent Load/Line Transient Response
2% Overall Accuracy (Load/Line/Temp)
Very Low Dropout: 125mV at 250mA
ThinSOT-23, 2mm × 2mm SON-6, and 3mm x
3mm SON-8 Packages
APPLICATIONS
•
•
•
•
WiFi, WiMax
Printers
Cellular Phones, SmartPhones
Handheld Organizers, PDAs
TPS734xxDDC
TSOT23-5
TPS73401DDC
TSOT23-5
TPS734xxDRV
2mm x 2mm SON-6
(TOP VIEW)
TPS73401DRV
2mm x 2mm SON-6
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
OUT
NR
1
2
3
OUT
FB
1
2
3
6
5
4
IN
6
5
4
IN
5
4
5
4
1
2
3
1
2
3
IN
GND
EN
OUT
FB
IN
GND
EN
OUT
NR
GND
GND
N/C
EN
N/C
EN
GND
GND
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2009, Texas Instruments Incorporated
TPS734xx
SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS734xxyyyz
XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Output voltages from 1.0V to 3.6V in 50mV increments are available through the use of innovative factory EEPROM programming;
minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating temperature range (unless otherwise noted).
PARAMETER
TPS734xx
–0.3 to +7.0
UNIT
VIN range
V
V
V
V
VEN range
–0.3 to VIN +0.3
–0.3 to VIN +0.3
–0.3 to VFB (TYP) +0.3
Internally limited
VOUT range
VFB range
Peak output current
Continuous total power dissipation
Junction temperature range, TJ
Storage junction temperature range, TSTG
ESD rating, HBM
See Dissipation Ratings Table
–55 to +150
°C
°C
kV
V
–55 to +150
2
ESD rating, CDM
500
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATINGS
DERATING FACTOR
BOARD
Low-K(1)
High-K(2)
Low-K(1)
High-K(2)
PACKAGE
DDC
RθJC
RθJA
ABOVE TA = +25°C
TA < +25°C
360mW
500mW
715mW
1.54W
TA = +70°C
200mW
275mW
395mW
845mW
TA = +85°C
145mW
200mW
285mW
615mW
90°C/W
90°C/W
20°C/W
20°C/W
280°C/W
200°C/W
140°C/W
65°C/W
3.6mW/°C
DDC
5.0mW/°C
DRV
7.1mW/°C
DRV
15.4mW/°C
(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), two-layer board with 2-ounce (56,699g)
copper traces on top of the board.
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in (7,62cm × 7,62cm), multilayer board with 1-ounce (28,35g)
internal power and ground planes and 2-ounce (56,699g) copper traces on top and bottom of the board
2
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TPS734xx
www.ti.com ........................................................................................................................................ SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN, COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V.
Typical values are at TJ = +25°C.
PARAMETER
Input voltage range(1)
TEST CONDITIONS
MIN
2.7
TYP
MAX
6.5
UNIT
V
VIN
VFB
Internal reference (TPS73401)
Output voltage range (TPS73401)
1.184
VFB
1.208
1.232
6.3
V
VOUT
VOUT
V
Output accuracy
Nominal
Over VIN
IOUT, Temp 1mA ≤ IOUT ≤ 250mA
VOUT(NOM) + 0.3V ≤ VIN ≤ 6.5V
TJ = +25°C
–1.0
+1.0
%
,
VOUT + 0.3V ≤ VIN ≤ 6.5V
VOUT
Output accuracy(1)
–2.0
±1.0
+2.0
%
ΔVOUT%/ ΔVIN Line regulation(1)
ΔVOUT%/ ΔIOUT Load regulation
0.02
%/V
500µA ≤ IOUT ≤ 250mA
0.005
%/mA
Dropout voltage(2)
(VIN = VOUT(NOM) – 0.1V)
VDO
IOUT = 250mA
125
219
mV
ICL
IGND
ISHDN
IFB
Output current limit
VOUT = 0.9 × VOUT(NOM)
300
580
45
900
65
mA
µA
µA
µA
dB
dB
dB
dB
µVRMS
µVRMS
µs
Ground pin current
500µA ≤ IOUT ≤ 250mA
Shutdown current (IGND
)
VEN ≤ 0.4V
0.15
1.0
0.5
Feedback pin current (TPS73401)
–0.5
f = 100Hz
60
Power-supply rejection ratio
VIN = 3.85V, VOUT = 2.85V,
CNR = 0.01µF, IOUT = 100mA
f = 1kHz
56
PSRR
VN
f = 10kHz
41
f = 100kHz
CNR = 0.01µF
CNR = none
CNR = none
CNR = 0.001µF
CNR = 0.01µF
CNR = 0.047µF
28
11 x VOUT
95 x VOUT
45
Output noise voltage
BW = 10Hz to 100kHz, VOUT = 2.8V
Startup time,
VOUT = 0 ~ 90%,
VOUT = 2.85V,
45
µs
TSTR
50
µs
RL = 14Ω, COUT = 2.2µF
50
µs
VEN(HI)
VEN(LO)
IEN(HI)
Enable high (enabled)
Enable low (shutdown)
Enable pin current, enabled
1.2
0
VIN
0.4
1.0
V
V
VEN = VIN = 6.5V
0.03
165
145
µA
°C
Shutdown, temperature increasing
Reset, temperature decreasing
TSD
TJ
Thermal shutdown temperature
°C
Operating junction temperature
Undervoltage lock-out
Hysteresis
–40
+125
2.65
°C
VIN rising
VIN falling
1.90
2.20
70
V
UVLO
mV
(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.
(2) VDO is not measured for devices with VOUT(NOM) < 2.8V because minimum VIN = 2.7V.
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TPS734xx
SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAMS
IN
IN
OUT
OUT
400W
400W
2mA
3.3MW
Current
Limit
Current
Limit
Overshoot
Detect
EN
Thermal
Overshoot
Detect
EN
Thermal
Shutdown
Shutdown
UVLO
UVLO
Quickstart
1.208V
Bandgap(1)
1.208V
NR
FB
Bandgap
500kW
500kW
GND
GND
NOTE (1): Fixed voltage versions between 1.0V to 1.2V have a 1.0V bandgap circuit
instead of a 1.208V bandgap circuit.
Figure 1. Fixed Voltage Versions
Figure 2. Adjustable Voltage Versions
PIN CONFIGURATIONS
TPS734xxDDC
TSOT23-5
TPS73401DDC
TSOT23-5
TPS734xxDRV
TPS73401DRV
2mm x 2mm SON-6
(TOP VIEW)
2mm x 2mm SON-6
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
OUT
NR
1
2
3
OUT
FB
1
2
3
6
5
4
IN
6
5
4
IN
5
4
5
4
1
2
3
1
2
3
IN
GND
EN
OUT
IN
GND
EN
OUT
NR
GND
GND
N/C
EN
N/C
EN
GND
GND
FB
PIN DESCRIPTIONS
TPS734xx
NAME
IN
DDC
DRV
6
DRB DESCRIPTION
1
2
8
4
Input supply.
Ground. The pad must be tied to GND.
GND
3, Pad
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the
regulator into shutdown mode. EN can be connected to IN if not used.
EN
NR
FB
3
4
4
4
2
2
5
Fixed voltage versions only; connecting an external capacitor to this pin bypasses noise
generated by the internal bandgap. This allows output noise to be reduced to very low
levels.
3
Adjustable version only; this is the input to the control loop error amplifier, and is used to set
the output voltage of the device.
3
1
Output of the regulator. A small capacitor (total typical capacitance ≥ 2.0µF ceramic) is
needed from this pin to ground to assure stability.
OUT
N/C
5
1
5
—
2, 6, 7 Not internally connected. This pin must either be left open, or tied to GND.
4
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TPS734xx
www.ti.com ........................................................................................................................................ SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ =
+25°C.
TPS73401 LINE REGULATION
TPS73425 LINE REGULATION
0.5
0.4
0.5
0.4
IOUT = 100mA
IOUT = 100mA
0.3
0.3
TJ = -40°C
TJ = 0°C
TJ = -40°C
0.2
0.2
TJ = 0°C
0.1
0.1
0
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
TJ = +25°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
TJ = +85°C
TJ = +125°C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
VIN (V)
VIN (V)
Figure 3.
TPS73401 LOAD REGULATION
Figure 4.
TPS73425 LOAD REGULATION
2.86
2.85
2.84
2.83
2.82
2.81
2.80
2.79
2.78
2.77
2.76
2.75
2.74
2.55
2.54
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.46
2.45
Y-axis range is ±2% of 2.8V
Y-axis range is ±2% of 2.5V
TJ = -40°C
TJ = 0°C
TJ = -40°C
TJ = +85°C
TJ = +125°C
TJ = +25°C
TJ = +85°C
TJ = +125°C
0
50
100
150
200
250
0
50
100
150
200
250
Load (mA)
Load (mA)
Figure 5.
Figure 6.
TPS73425 GROUND PIN CURRENT vs
OUTPUT CURRENT
TPS73425 GROUND PIN CURRENT (DISABLE)
vs TEMPERATURE
500
450
400
350
300
250
200
150
100
50
60
50
40
30
20
10
0
VEN = 0.4V
TJ = +125°C
TJ = +25°C
TJ = +85°C
TJ = -40°C
TJ = 0°C
VIN = 3.3V
VIN = 5.0V
VIN = 6.5V
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
0
50
100
150
200
250
TJ (°C)
IOUT (mA)
Figure 7.
Figure 8.
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TPS734xx
SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ =
+25°C.
TPS73401 DROPOUT VOLTAGE vs
OUTPUT CURRENT
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
(VIN – VOUT = 1.0V)
90
400
350
300
250
200
150
100
50
80
70
60
50
40
30
20
10
0
IOUT = 1mA
IOUT = 250mA
TJ = +125°C
TJ = +85°C
IOUT
=
100mA
TJ = +25°C
TJ = 0°C
COUT = 10mF
CNR = 0.01mF
TJ = -40°C
IOUT = 200mA
100k
1M
0
10
100
1k
10k
10M
0
50
100
150
200
250
Frequency (Hz)
IOUT (mA)
Figure 9.
Figure 10.
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
(VIN – VOUT = 0.5V)
POWER-SUPPLY RIPPLE REJECTION vs FREQUENCY
(VIN – VOUT = 0.3V)
90
90
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
IOUT = 1mA
IOUT = 1mA
IOUT = 200mA
IOUT = 200mA
IOUT
=
IOUT
=
100mA
100mA
IOUT
=
COUT = 2.2mF
CNR = 0.01mF
COUT = 2.2mF
CNR = 0.01mF
200mA
IOUT = 250mA
10k 100k
10
100
1k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 11.
Figure 12.
TPS73425
TOTAL NOISE vs CNR
TPS73425
TOTAL NOISE vs COUT
140
120
100
80
30
25
20
15
10
5
IOUT = 1mA
COUT = 2.2mF
60
40
20
IOUT = 1mA
CNR = 0.01mF
0
0
0
5
10
15
20
25
0.01
0.1
1
10
COUT (mF)
CNR (nF)
Figure 13.
Figure 14.
6
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TPS734xx
www.ti.com ........................................................................................................................................ SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ = –40°C to +125°C); VIN = VOUT(TYP) + 0.3V or 2.7V, whichever is greater; IOUT = 1mA,
VEN = VIN,COUT = 2.2µF, CNR = 0.01µF, unless otherwise noted. For TPS73401, VOUT = 3.0V. Typical values are at TJ =
+25°C.
TPS73425
TURN-ON RESPONSE
TPS73425
(VIN = VEN
)
ENABLE RESPONSE OVER STABLE VIN
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
VEN
VEN
VOUT
VOUT
COUT = 2.2mF
COUT = 2.2mF
COUT = 10mF
COUT = 10mF
-0.5
-0.5
10ms/div
10ms/div
Figure 15.
Figure 16.
TPS73410
POWER-UP/POWER-DOWN
TPS73410
LOAD TRANSIENT RESPONSE
7
6
VIN = 2.7V
COUT = 1.0mF
IOUT = 250mA
100mV/div
100mV/div
VOUT
VIN
5
COUT = 2.2mF
VOUT
4
3
VOUT
2
250mA
1
0
100mA/div
1mA
IOUT
-1
20ms/div
50ms/div
Figure 17.
Figure 18.
TPS73410
LINE TRANSIENT RESPONSE
IOUT = 250mA
COUT = 2.2mF
20mV/div
VOUT
COUT = 1.0mF
20mV/div
1V/div
VOUT
3.7V
dVIN
= 1V/ms
dt
2.7V
VIN
20ms/div
Figure 19.
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TPS734xx
SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com
APPLICATION INFORMATION
Input and Output Capacitor Requirements
The TPS734xx family of LDO regulators combines
the high performance required of many RF and
precision analog applications with ultra-low current
consumption. High PSRR is provided by a high gain,
high bandwidth error loop with good supply rejection
at very low headroom (VIN – VOUT). Fixed voltage
versions provide a noise reduction pin to bypass
noise generated by the bandgap reference and to
improve PSRR while a quick-start circuit fast-charges
this capacitor at startup. The combination of high
performance and low ground current also make the
TPS734xx an excellent choice for portable
applications. All versions have thermal and
over-current protection and are fully specified from
–40°C to +125°C.
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1µF to 1µF low equivalent series resistance
(ESR) capacitor across the input supply near the
regulator. The ground of this capacitor should be
connected as close as the ground of output capacitor;
a capacitor value of 0.1µF is enough in this condition.
When it is difficult to place these two ground points
close together, a 1µF capacitor is recommended.
This capacitor counteracts reactive input sources and
improves transient response, noise rejection, and
ripple rejection. A higher-value capacitor may be
necessary if large, fast rise-time load transients are
anticipated, or if the device is located several inches
from the power source. If source impedance is not
sufficiently low, a 0.1µF input capacitor may be
necessary to ensure stability.
Figure 20 shows the basic circuit connections for
fixed voltage models. Figure 21 gives the connections
for the adjustable output version (TPS73401). R1 and
R2 can be calculated for any output voltage using the
formula in Figure 21.
The TPS734xx is designed to be stable with standard
ceramic output capacitors of values 2.2µF or larger.
X5R and X7R type capacitors are best because they
have minimal variation in value and ESR over
temperature. Maximum ESR of the output capacitor
should be < 1.0Ω, so output capacitor type should be
either ceramic or conductive polymer electrolytic.
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
VIN
VOUT
IN
OUT
TPS734xx
Feedback Capacitor Requirements
(TPS73401 only)
2.2mF
Ceramic
EN
GND
NR
The feedback capacitor, CFB, shown in Figure 21 is
required for stability. For a parallel combination of R1
and R2 equal to 250kΩ, any value from 3pF to 1nF
can be used. Fixed voltage versions have an internal
30pF feedback capacitor that is quick-charged at
start-up. The adjustable version does not have this
quick-charge circuit, so values below 5pF should be
used to ensure fast startup; values above 47pF can
be used to implement an output voltage soft-start.
Larger value capacitors also improve noise slightly.
The TPS73401 is stable in unity-gain configuration
VEN
Optional bypass capacitor
to reduce output noise
and increase PSRR.
Figure 20. Typical Application Circuit for
FIxed Voltage Versions
Optional input capacitor.
(R1 + R2)
May improve source
impedance, noise, or PSRR.
VOUT
=
´ 1.208
R2
(OUT tied to FB) without CFB
.
VIN
VOUT
IN
OUT
FB
TPS73401
R1
CFB
Output Noise
2.2mF
EN
GND
Ceramic
In most LDOs, the bandgap is the dominant noise
source. If a noise reduction capacitor (CNR) is used
with the TPS734xx, the bandgap does not contribute
significantly to noise. Instead, noise is dominated by
the output resistor divider and the error amplifier
input. To minimize noise in a given application, use a
0.01µF noise reduction capacitor; for the adjustable
version, smaller value resistors in the output resistor
divider reduce noise. A parallel combination that
gives 2µA of divider current has the same noise
performance as a fixed voltage version. To further
R2
VEN
Figure 21. Typical Application Circuit for
Adjustable Voltage Versions
space
space
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optimize noise, equivalent series resistance of the
output capacitor can be set to approximately 0.2Ω.
This configuration maximizes phase margin in the
control loop, reducing total output noise by up to
10%.
As with any linear regulator, PSRR and transient
response are degraded as (VIN – VOUT) approaches
dropout. This effect is shown in the Typical
Characteristics section.
Startup and Noise Reduction Capacitor
Noise can be referred to the feedback point (FB pin)
such that with CNR = 0.01µF, total noise is given
approximately by Equation 1:
Fixed voltage versions of the TPS734xx use a
quick-start circuit to fast-charge the noise reduction
capacitor, CNR, if present (see the Functional Block
Diagrams). This architecture allows the combination
of very low output noise and fast start-up times. The
NR pin is high impedance so a low leakage CNR
capacitor must be used; most ceramic capacitors are
appropriate in this configuration.
11mVRMS
VN =
x VOUT
V
(1)
The TPS73401 adjustable version does not have the
noise-reduction pin available, so ultra-low noise
operation is not possible. Noise can be minimized
according to the above recommendations.
Note that for fastest startup, VIN should be applied
first, then the enable pin (EN) driven high. If EN is
tied to IN, startup is somewhat slower. Refer to the
Typical Characteristics section. The quick-start switch
is closed for approximately 135µs. To ensure that
CNR is fully charged during the quick-start time, a
0.01µF or smaller capacitor should be used.
Board Layout Recommendations to Improve
PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Transient Response
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. In
the adjustable version, adding CFB between OUT and
FB improves stability and transient response. The
transient response of the TPS734xx is enhanced by
an active pull-down that engages when the output
overshoots by approximately 5% or more when the
device is enabled. When enabled, the pull-down
device behaves like a 400Ω resistor to ground.
Internal Current Limit
The TPS734xx internal current limit helps protect the
regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
largely independent of output voltage. For reliable
operation, the device should not be operated in
current limit for extended periods of time.
The PMOS pass element in the TPS734xx has a
built-in body diode that conducts current when the
voltage at OUT exceeds the voltage at IN. This
current is not limited, so if extended reverse voltage
operation is anticipated, external limiting may be
appropriate.
Undervoltage Lock-Out (UVLO)
The TPS734xx utilizes an undervoltage lock-out
circuit to keep the output shut off until internal
circuitry is operating properly. The UVLO circuit has a
de-glitch feature so that it typically ignores
undershoot transients on the input if they are less
than 50µs duration.
Shutdown
The enable pin (EN) is active high and is compatible
with standard and low voltage TTL-CMOS levels.
When shutdown capability is not required, EN can be
connected to IN.
Minimum Load
The TPS734xx is stable and well-behaved with no
output load. To meet the specified accuracy, a
minimum load of 1mA is required. Below 1mA at
junction temperatures near +125°C, the output can
drift up enough to cause the output pull-down to turn
on. The output pull-down limits voltage drift to 5%
typically but ground current could increase by
approximately 50µA. In typical applications, the
junction cannot reach high temperatures at light loads
because there is no appreciable dissipated power.
The specified ground current would then be valid at
no load conditions in most applications.
Dropout Voltage
The TPS734xx uses a PMOS pass transistor to
achieve low dropout. When (VIN – VOUT) is less than
the dropout voltage (VDO), the PMOS pass device is
in its linear region of operation and the input-to-output
resistance is the RDS, ON of the PMOS pass element.
Because the PMOS device behaves like a resistor in
dropout, VDO approximately scales with output
current.
Copyright © 2007–2009, Texas Instruments Incorporated
Submit Documentation Feedback
9
TPS734xx
SBVS089F–DECEMBER 2007–REVISED FEBRUARY 2009 ........................................................................................................................................ www.ti.com
Thermal Information
Thermal Protection
Power Dissipation
Thermal protection disables the output when the
junction temperature rises to approximately +165°C,
allowing the device to cool. When the junction
temperature cools to approximately +145°C the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are given in the Dissipation Ratings table. Using
heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also
improves the heatsink effectiveness.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
of the output current time the voltage drop across the
output pass element, as shown in Equation 2:
(including
heatsink),
increase
the
ambient
ǒ
Ǔ
PD + VIN*VOUT @ IOUT
(2)
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your particular application. This
configuration produces
temperature of +125°C at the highest expected
ambient temperature and worst-case load.
Package Mounting
Solder pad footprint recommendations for the
TPS734xx are available from the Texas Instruments
web site at www.ti.com.
a
worst-case junction
The internal protection circuitry of the TPS734xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS734xx into thermal
shutdown degrades device reliability.
10
Submit Documentation Feedback
Copyright © 2007–2009, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
DDC
DDC
DRV
DRV
DDC
DRV
DRV
DRV
DRV
DDC
DDC
DRV
DRV
Qty
3000
250
(1)
(2)
(3)
(4/5)
(6)
TPS73401DDCR
TPS73401DDCT
TPS73401DRVR
TPS73401DRVT
TPS73410DDCR
TPS73418DRVR
TPS73418DRVT
TPS73430DRVR
TPS73430DRVT
TPS73433DDCR
TPS73433DDCT
TPS73433DRVR
TPS73433DRVT
ACTIVE SOT-23-THIN
5
5
6
6
5
6
6
6
6
5
5
6
6
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
OCW
OCW
CBG
CBG
CBJ
ACTIVE SOT-23-THIN
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAUAG
NIPDAUAG
NIPDAU
ACTIVE
ACTIVE
WSON
WSON
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
ACTIVE SOT-23-THIN
3000
3000
250
Green (RoHS
& no Sb/Br)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
Green (RoHS
& no Sb/Br)
NIPDAU
CBI
Green (RoHS
& no Sb/Br)
NIPDAUAG
NIPDAU
CBI
3000
250
Green (RoHS
& no Sb/Br)
CVW
CVW
OEV
OEV
CVX
CVX
Green (RoHS
& no Sb/Br)
NIPDAU
ACTIVE SOT-23-THIN
ACTIVE SOT-23-THIN
3000
250
Green (RoHS
& no Sb/Br)
NIPDAU
Green (RoHS
& no Sb/Br)
NIPDAU
ACTIVE
ACTIVE
WSON
WSON
3000
250
Green (RoHS
& no Sb/Br)
NIPDAUAG
NIPDAUAG
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2020
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73401DDCR
TPS73401DDCT
SOT-
23-THIN
DDC
DDC
5
5
3000
250
180.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
SOT-
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
23-THIN
TPS73401DRVR
TPS73401DRVT
TPS73410DDCR
WSON
WSON
DRV
DRV
DDC
6
6
5
3000
250
179.0
179.0
179.0
8.4
8.4
8.4
2.2
2.2
3.2
2.2
2.2
3.2
1.2
1.2
1.4
4.0
4.0
4.0
8.0
8.0
8.0
Q2
Q2
Q3
SOT-
3000
23-THIN
TPS73418DRVR
TPS73418DRVT
TPS73430DRVR
TPS73430DRVR
TPS73430DRVT
TPS73430DRVT
TPS73433DDCR
WSON
WSON
WSON
WSON
WSON
WSON
DRV
DRV
DRV
DRV
DRV
DRV
DDC
6
6
6
6
6
6
5
3000
250
179.0
179.0
179.0
178.0
179.0
178.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
2.2
2.2
2.2
2.2
1.2
1.2
1.2
1.0
1.2
1.0
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
Q2
Q2
Q3
3000
3000
250
2.2
2.2
2.25
2.2
2.25
2.2
250
2.25
3.2
2.25
3.2
SOT-
3000
23-THIN
TPS73433DDCT
TPS73433DRVR
SOT-
23-THIN
DDC
DRV
5
6
250
179.0
179.0
8.4
8.4
3.2
2.2
3.2
2.2
1.4
1.2
4.0
4.0
8.0
8.0
Q3
Q2
WSON
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Aug-2020
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73433DRVT
WSON
DRV
6
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS73401DDCR
TPS73401DDCT
TPS73401DRVR
TPS73401DRVT
TPS73410DDCR
TPS73418DRVR
TPS73418DRVT
TPS73430DRVR
TPS73430DRVR
TPS73430DRVT
TPS73430DRVT
TPS73433DDCR
TPS73433DDCT
TPS73433DRVR
TPS73433DRVT
SOT-23-THIN
SOT-23-THIN
WSON
DDC
DDC
DRV
DRV
DDC
DRV
DRV
DRV
DRV
DRV
DRV
DDC
DDC
DRV
DRV
5
5
6
6
5
6
6
6
6
6
6
5
5
6
6
3000
250
195.0
195.0
203.0
203.0
195.0
203.0
203.0
203.0
205.0
203.0
205.0
195.0
195.0
203.0
203.0
200.0
200.0
203.0
203.0
200.0
203.0
203.0
203.0
200.0
203.0
200.0
200.0
200.0
203.0
203.0
45.0
45.0
35.0
35.0
45.0
35.0
35.0
35.0
33.0
35.0
33.0
45.0
45.0
35.0
35.0
3000
250
WSON
SOT-23-THIN
WSON
3000
3000
250
WSON
WSON
3000
3000
250
WSON
WSON
WSON
250
SOT-23-THIN
SOT-23-THIN
WSON
3000
250
3000
250
WSON
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRV 6
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4206925/F
PACKAGE OUTLINE
DRV0006A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A
C
B
0.05
4222173/B 04/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222173/B 04/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4222173/B 04/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DRV0006D
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
A
B
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
1
0.1
EXPOSED
THERMAL PAD
3
4
6
2X
7
1.3
1.6 0.1
1
4X 0.65
0.35
0.25
6X
PIN 1 ID
(OPTIONAL)
0.3
0.2
6X
0.1
C A B
C
0.05
4225563/A 12/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.45)
6X (0.3)
(1)
1
7
6
SYMM
(1.6)
(1.1)
4X (0.65)
4
3
SYMM
(1.95)
(R0.05) TYP
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225563/A 12/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
DRV0006D
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
7
6X (0.45)
METAL
1
6
6X (0.3)
(0.45)
SYMM
4X (0.65)
(0.7)
4
3
(R0.05) TYP
(1)
(1.95)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD #7
88% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4225563/A 12/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Copyright © 2020, Texas Instruments Incorporated
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