TPS736-Q1 [TI]
具有反向电流保护功能的汽车类 400mA、高精度、低压降稳压器;
| 型号： | TPS736-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有反向电流保护功能的汽车类 400mA、高精度、低压降稳压器 电源电路 线性稳压器IC |
| 文件： | 总22页 (文件大小：576K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
www.ti.com
SLVSAI3 –SEPTEMBER 2010
Cap-Free, NMOS, 400mA Low-Dropout Regulator
with Reverse Current Protection
Check for Samples: TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
1
FEATURES
DESCRIPTION
2
•
Qualified for Automotive Applications
•
Stable with No Output Capacitor or Any Value
or Type of Capacitor
The TPS736xx family of low-dropout (LDO) linear
voltage regulators uses a new topology: an NMOS
pass element in a voltage-follower configuration. This
topology is stable using output capacitors with low
ESR, and even allows operation without a capacitor.
It also provides high reverse blockage (low reverse
current) and ground pin current that is nearly constant
over all values of output current.
•
•
•
Input Voltage Range of 1.7V to 5.5V
Ultra-Low Dropout Voltage: 75mV typ
Excellent Load Transient Response—with or
without Optional Output Capacitor
•
New NMOS Topology Delivers Low Reverse
Leakage Current
The TPS736xx uses an advanced BiCMOS process
to yield high precision while delivering very low
dropout voltages and low ground pin current. Current
consumption, when not enabled, is under 1mA and
ideal for portable applications. The extremely low
output noise (30mVRMS with 0.1mF CNR) is ideal for
powering VCOs. These devices are protected by
thermal shutdown and foldback current limit.
•
•
•
Low Noise: 30mVRMS typ (10Hz to 100kHz)
0.5% Initial Accuracy
1% Overall Accuracy Over Line, Load, and
Temperature
•
•
Less Than 1mA max IQ in Shutdown Mode
Thermal Shutdown and Specified Min/Max
Current Limit Protection
space
•
Available in Multiple Output Voltage Versions
–
–
Fixed Outputs of 1.20V to 3.3V
Adjustable Output from 1.20V to 5.5V
Optional
Optional
VIN
VOUT
IN
OUT
TPS736xx
GND
EN
NR
ON
OFF
Optional
Typical Application Circuit for Fixed-Voltage Versions
space
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
SLVSAI3 –SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
ORDERABLE PART
NUMBER
TOP-SIDE
MARKING
TA
OUTPUT VOLTAGE
PACKAGE(2)
adjustable
2.5 V
TPS73601QDBVRQ1
TPS73625QDBVRQ1(3)
TPS73633QDBVRQ1(3)
PTWQ
SOT (SOT-23) –
DBV
–40°C to 125°C
Reel of 3000
PREVIEW
PREVIEW
3.3 V
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Product Preview
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
PARAMETER
TPS736xx
–0.3 to 6.0
–0.3 to 6.0
–0.3 to 5.5
–0.3 to 6.0
Internally limited
Indefinite
UNIT
VIN range
V
V
V
V
VEN range
VOUT range
VNR, VFB range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
See Thermal Information Table
–40 to +150
–65 to +150
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2
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TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
www.ti.com
SLVSAI3 –SEPTEMBER 2010
THERMAL INFORMATION
DBV(2)
UNITS
5 PINS
THERMAL METRIC(1)
qJA
Junction-to-ambient thermal resistance(3)
Junction-to-case (top) thermal resistance(4)
Junction-to-board thermal resistance(5)
180
64
qJCtop
qJB
35
°C/W
N/A
yJT
Junction-to-top characterization parameter(6)
Junction-to-board characterization parameter(7)
Junction-to-case (bottom) thermal resistance(8)
yJB
N/A
N/A
qJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) Thermal data for the DBV package is derived by thermal simulations based on JEDEC-standard methodology as specified in the
JESD51 series. The following assumptions are used in the simulations:
(a) DBV: There is no exposed pad with the DBV package.
(b) DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.
(3) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(6) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2010, Texas Instruments Incorporated
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TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
SLVSAI3 –SEPTEMBER 2010
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ELECTRICAL CHARACTERISTICS
Over operating temperature range (TA = –40°C to +125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and
COUT = 0.1mF, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
Input voltage range(1) (2)
TEST CONDITIONS
MIN
1.7
TYP
MAX
5.5
UNIT
V
VIN
VFB
Internal reference (TPS73601)
TJ = +25°C
1.198
1.20
1.210
V
Output voltage range
(TPS73601)(3)
VFB
–0.5
–1.0
5.5 – VDO
+0.5
V
VOUT
Nominal
TJ = +25°C
Accuracy(1)
%
(4)
over VIN, IOUT
and T
,
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10mA ≤ IOUT ≤ 400mA
±0.5
+1.0
ΔVOUT%/ΔVIN Line regulation(1)
VO(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 400mA
0.01
0.002
0.0005
%/V
ΔVOUT%/ΔIOUT Load regulation
%/mA
10mA ≤ IOUT ≤ 400mA
Dropout voltage(5)
VDO
IOUT = 400mA
75
200
mV
(VIN = VOUT(nom) – 0.1V)
ZO(DO)
ICL
Output impedance in dropout
Output current limit
1.7V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
3.6V ≤ VIN ≤ 4.2V, 0°C ≤ TJ ≤ +70°C
VOUT = 0V
0.25
650
Ω
400
500
800
800
mA
mA
mA
mA
ISC
Short-circuit current
Reverse leakage current(6) (–IIN
450
0.1
IREV
)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT
10
IOUT = 10mA (IQ)
IOUT = 400mA
400
800
550
IGND
GND pin current
mA
1000
V
EN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5,
ISHDN
IFB
Shutdown current (IGND
)
0.02
1.3
mA
mA
–40°C ≤ TJ ≤ +100°C
FB pin current (TPS73601)
0.1
58
0.45
f = 100Hz, IOUT = 400mA
f = 10KHz, IOUT = 400mA
COUT = 10mF, No CNR
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
37
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10Hz – 100KHz
VN
mVRMS
ms
COUT = 10mF, CNR = 0.01mF
VOUT = 3V, RL = 30Ω COUT = 1mF,
CNR = 0.01mF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
EN pin high (enabled)
EN pin low (shutdown)
EN pin current (enabled)
1.7
0
VIN
0.5
0.1
V
V
VEN = 5.5V
0.02
+160
+140
mA
Shutdown, temperature increasing
Reset, temperature decreasing
TSD
TA
Thermal shutdown temperature
Operating ambient temperature
°C
°C
–40
+125
(1) Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.
(2) For VOUT(nom) < 1.6V, when VIN ≤ 1.6V, the output will lock to VIN and may result in a damaging over-voltage level on the output. To
avoid this situation, disable the device before powering down the VIN
.
(3) TPS73601 is tested at VOUT = 2.5V.
(4) Tolerance of external resistors not included in this specification.
(5) VDO is not measured for fixed output versions with VOUT(nom) < 1.8V.
(6) Fixed-voltage versions only; refer to Applications section for more information.
4
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TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
www.ti.com
SLVSAI3 –SEPTEMBER 2010
FUNCTIONAL BLOCK DIAGRAMS
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
R2
Ω
R1 + R2 = 80k
NR
Figure 1. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
O
R
1
R
2
4MHz
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
Short
Open
Charge Pump
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
OUT
FB
Current
Limit
R
R
19kΩ for best
1
2
accuracy.
GND
Ω
80k
Ω
8k
R1
R2
Figure 2. Adjustable Voltage Version
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TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
SLVSAI3 –SEPTEMBER 2010
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PIN CONFIGURATION
PIN DESCRIPTIONS
SOT23 (DBV)
PIN NO.
NAME
IN
DESCRIPTION
1
2
Input supply
Ground
GND
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. Refer to the Shutdown section under Applications Information for more details. EN
can be connected to IN if not used.
EN
NR
3
4
Fixed voltage versions only—connecting an external capacitor to this pin bypasses noise generated by
the internal bandgap, reducing output noise to very low levels.
Adjustable voltage version only—this is the input to the control loop error amplifier, and is used to set
the output voltage of the device.
FB
4
5
OUT
Output of the Regulator. There are no output capacitor requirements for stability.
6
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Product Folder Link(s): TPS73601-Q1 TPS73625-Q1 TPS73633-Q1
TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
www.ti.com
SLVSAI3 –SEPTEMBER 2010
TYPICAL CHARACTERISTICS
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.20
0.15
0.10
0.05
0
0.5
0.4
0.3
0.2
0.1
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 0.5V at IOUT = 10mA
−
_
40 C
_
+25
C
_
+25
C
_
+125 C
_
+125
C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
−
−
−
0.05
0.10
0.15
0.20
−
_
40
C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
50
100
150
200
250
300
350 400
−
VIN VOUT (V)
IOUT (mA)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
100
80
60
40
20
0
100
80
60
40
20
0
TPS73625DBV
IOUT = 400mA
TPS73625DBV
_
+125
C
_
+25
C
−
_
40
C
−
−
25
0
50
100
150
200
250
300
350
400
50
0
25
50
75
100
125
_
IOUT (mA)
Temperature ( C)
Figure 5.
Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
IOUT = 10mA
All Voltage Versions
IOUT = 10mA
25
20
15
10
5
6
4
2
0
0
VOUT Error (%)
_
Worst Case dVOUT/dT (ppm/ C)
Figure 7.
Figure 8.
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SLVSAI3 –SEPTEMBER 2010
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
IOUT = 400mA
VIN = 5.5V
VIN = 4V
VIN = 2V
VIN = 5.5V
VIN = 3V
VIN = 2V
0
100
200
300
400
−
−
25
50
0
25
50
75
100
125
IOUT (mA)
_
Temperature ( C)
Figure 9.
Figure 10.
GROUND PIN CURRENT in SHUTDOWN
vs TEMPERATURE
CURRENT LIMIT vs VOUT
(FOLDBACK)
1
800
700
600
500
400
300
200
100
0
TPS73633
ICL
VENABLE = 0.5V
VIN = VO + 0.5V
ISC
0.1
0.01
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−
−
25
50
0
25
50
75
100
125
Output Voltage (V)
_
Temperature ( C)
Figure 11.
Figure 12.
CURRENT LIMIT vs VIN
CURRENT LIMIT vs TEMPERATURE
800
750
700
650
600
550
500
450
400
800
750
700
650
600
550
500
450
400
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
_
VIN (V)
Temperature ( C)
Figure 13.
Figure 14.
8
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SLVSAI3 –SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
IOUT = 100mA
COUT = Any
IOUT = 1mA
µ
COUT = 1
F
IOUT = 1mA
COUT = 10 F
µ
IO = 100mA
µ
CO = 1 F
IOUT = 1mA
COUT = Any
Frequency = 10kHz
COUT = 10mF
IOUT = 100mA
COUT = 10
µ
F
VOUT = 2.5V
IOUT = Any
VIN = VOUT + 1V
µ
IOUT = 100mA
COUT = 0
F
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
V
IN - VOUT (V)
Frequency (Hz)
Figure 15.
Figure 16.
NOISE SPECTRAL DENSITY
NOISE SPECTRAL DENSITY
CNR = 0mF
CNR = 0.01mF
1
1
µ
COUT = 1
F
µ
COUT = 1
F
µ
COUT = 0
F
0.1
0.1
µ
COUT = 10 F
µ
COUT = 0
F
µ
COUT = 10
F
IOUT = 150mA
IOUT = 150mA
10 100
0.01
0.01
10
100
1k
10k
100k
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs COUT
RMS NOISE VOLTAGE vs CNR
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 1.5V
VOUT = 3.3V
VOUT = 1.5V
60
40
20
µ
CNR = 0.01 F
µ
COUT = 0 F
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p
10p
100p
1n
10n
µ
COUT ( F)
CNR (F)
Figure 19.
Figure 20.
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SLVSAI3 –SEPTEMBER 2010
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted.
TPS73633
TPS73633
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
µ
µ
µ
VIN = 3.8V
COUT = 0
F
F
F
IOUT = 400mA
100mV/tick
50mV/tick
20mV/tick
50mA/tick
VOUT
VOUT
VOUT
IOUT
µ
COUT = 0
F
50mV/div
VOUT
COUT = 1
µ
COUT = 100
F
COUT = 10
50mV/div
1V/div
VOUT
dVIN
dt
5.5V
µ
= 0.5V/
s
400mA
4.5V
VIN
10mA
µ
10 s/div
µ
10 s/div
Figure 21.
Figure 22.
TPS73633
TPS73633
TURN-ON RESPONSE
TURN-OFF RESPONSE
Ω
RL = 1k
RL = 20Ω
COUT = 10µF
VOUT
COUT = 0µF
Ω
RL = 20
Ω
RL = 20
1V/div
1V/div
1V/div
1V/div
µ
COUT = 1
F
µ
COUT = 1
F
Ω
RL = 1k
Ω
RL = 20
COUT = 0µF
µ
COUT = 10
F
VOUT
2V
2V
VEN
0V
0V
VEN
µ
100 s/div
100µs/div
Figure 23.
Figure 24.
TPS73633
POWER UP / POWER DOWN
IENABLE vs TEMPERATURE
10
1
6
5
4
3
2
1
0
VIN
VOUT
0.1
−
−
1
2
0.01
−
−
25
50ms/div
50
0
25
50
75
100
125
_
Temperature ( C)
Figure 25.
Figure 26.
10
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SLVSAI3 –SEPTEMBER 2010
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise
noted.
TPS73601
TPS73601
RMS NOISE VOLTAGE vs CFB
IFB vs TEMPERATURE
60
55
50
45
40
35
30
25
20
160
140
120
100
80
60
VOUT = 2.5V
40
µ
COUT = 0 F
Ω
R1 = 39.2k
20
10Hz < Frequency < 100kHz
0
10p
100p
1n
10n
−
−
25
50
0
25
50
75
100
125
CFB (F)
_
Temperature ( C)
Figure 27.
Figure 28.
TPS73601
TPS73601
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
CFB = 10nF
VOUT = 2.5V
CFB = 10nF
Ω
R1 = 39.2k
µ
COUT = 0
F
µ
COUT = 0 F
VOUT
VOUT
100mV/div
100mV/div
200mV/div
200mV/div
µ
COUT = 10 F
VOUT
µ
COUT = 10
F
VOUT
4.5V
400mA
3.5V
VIN
10mA
IOUT
µ
µ
s/div
5
25 s/div
Figure 29.
Figure 30.
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SLVSAI3 –SEPTEMBER 2010
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APPLICATION INFORMATION
For best accuracy, make the parallel combination of
R1 and R2 approximately equal to 19kΩ. This 19kΩ,
in addition to the internal 8kΩ resistor, presents the
same impedance to the error amp as the 27kΩ
bandgap reference output. This impedance helps
compensate for leakages into the error amp
terminals.
The TPS736xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS736xx ideal for
portable applications. This regulator family offers a
wide selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback
current limit.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1mF to 1mF low ESR capacitor across the input
supply near the regulator. This counteracts reactive
input sources and improves transient response, noise
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections
for the adjustable output version (TPS73601).
rejection, and ripple rejection.
A
higher-value
Optional input capacitor.
May improve source
Optional output capacitor.
May improve load transient,
noise, or PSRR.
capacitor may be necessary if large, fast rise-time
load transients are anticipated or the device is
located several inches from the power source.
impedance, noise, or PSRR.
VIN
VOUT
IN
OUT
TPS736xx
The TPS736xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
multiple low ESR capacitors are in parallel, ringing
may occur when the product of COUT and total ESR
drops below 50nΩF. Total ESR includes all parasitic
resistances, including capacitor ESR and board,
socket, and solder joint resistance. In most
applications, the sum of capacitor ESR and trace
resistance will meet this requirement.
EN
GND
NR
ON
OFF
Optional bypass
capacitor to reduce
output noise.
Figure 31. Typical Application Circuit for
Fixed-Voltage Versions
OUTPUT NOISE
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS736xx and
it generates approximately 32mVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
VIN
VOUT
IN
OUT
TPS73601
R1
CFB
EN
GND
FB
ON
R2
OFF
Optional capacitor
reduces output noise
and improves
(R1 + R2)
R2
VOUT
=
x 1.204
transient response.
VOUT
VREF
(R1 ) R2)
VN + 32mVRMS
+ 32mVRMS
R2
(1)
Figure 32. Typical Application Circuit for
Adjustable-Voltage Version
Since the value of VREF is 1.2V, this relationship
reduces to:
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 32. Sample
resistor values for common output voltages are
shown in Figure 2.
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
(2)
for the case of no CNR
.
12
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SLVSAI3 –SEPTEMBER 2010
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
ENABLE PIN AND SHUTDOWN
The enable pin (EN) is active high and is compatible
with standard TTL-CMOS levels. A VEN below 0.5V
(max) turns the regulator off and drops the GND pin
current to approximately 10nA. When EN is used to
shutdown the regulator, all charge is removed from
the pass transistor gate, and the output ramps back
up to a regulated VOUT (see Figure 23).
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
(3)
When shutdown capability is not required, EN can be
connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass
transistor may be left on (enhanced) for a significant
time after VIN has been removed. This scenario can
result in reverse current flow (if the IN pin is low
impedance) and faster ramp times upon power-up. In
addition, for VIN ramp times slower than a few
milliseconds, the output may overshoot upon
power-up.
for CNR = 10nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
The TPS73601 adjustable version does not have the
NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin
(FB) reduces output noise and improves load
transient performance.
Note that current limit foldback can prevent device
start-up under some conditions. See the Internal
Current Limit section for more information.
The TPS736xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250mV of switching noise at
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
DROPOUT VOLTAGE
The TPS736xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
values of IOUT and COUT
.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
For large step changes in load current, the TPS736xx
requires a larger voltage drop from VIN to VOUT to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of VIN – VOUT above this line
ensure normal transient response.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
INTERNAL CURRENT LIMIT
The TPS736xx internal current limit helps protect the
regulator during fault conditions. Foldback current
limit helps to protect the regulator from damage
during output short-circuit conditions by reducing
current limit when VOUT drops below 0.5V. See
Figure 12 in the Typical Characteristics section.
the TPS736xx can take
a couple of hundred
Note from Figure 12 that approximately –0.2V of VOUT
results in a current limit of 0mA. Therefore, if OUT is
forced below –0.2V before EN goes high, the device
may not start up. In applications that work with both a
positive and negative voltage supply, the TPS736xx
should be enabled first.
microseconds to return to the specified regulation
accuracy.
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SLVSAI3 –SEPTEMBER 2010
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TRANSIENT RESPONSE
After the EN pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin due to voltage applied on the OUT
pin. There will be additional current flowing into the
OUT pin due to the 80kΩ internal resistor divider to
ground (see Figure 1 and Figure 2).
The low open-loop output impedance provided by the
NMOS pass element in
a
voltage follower
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1mF) from the OUT pin to ground will reduce
undershoot magnitude but increase its duration. In
the adjustable version, the addition of a capacitor,
CFB, from the OUT pin to the FB pin will also improve
the transient response.
For the TPS73601, reverse current may flow when
VFB is more than 1.0V above VIN.
THERMAL PROTECTION
The TPS736xx does not have active pull-down when
the output is over-voltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if
load current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heat sink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including heat sink), increase the ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
(Fixed Voltage Version)
VOUT
dVńdt +
COUT 80kW ø RLOAD
(4)
(Adjustable Voltage Version)
VOUT
condition of your application. This produces
worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
a
dVńdt +
(
)
COUT 80kW ø R1 ) R2 ø RLOAD
(5)
REVERSE CURRENT
The internal protection circuitry of the TPS736xx has
been designed to protect against overload conditions.
It was not intended to replace proper heat sinking.
Continuously running the TPS736xx into thermal
shutdown degrades device reliability.
The NMOS pass element of the TPS736xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
the EN pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on due to stored charge on the
gate.
14
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TPS73601-Q1, TPS73625-Q1, TPS73633-Q1
www.ti.com
SLVSAI3 –SEPTEMBER 2010
POWER DISSIPATION
space
PD + (VIN * VOUT) IOUT
(6)
The ability to remove heat from the die is different for
each
package
type,
presenting
different
Power dissipation can be minimized by using the
lowest possible input voltage necessary to assure the
required output voltage.
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Thermal Information table. Using
heavier copper will increase the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers will also
improve the heat-sink effectiveness.
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TPS736xx are presented in Application Bulletin
Solder Pad Recommendations for Surface-Mount
Devices (SBFA015), available from the Texas
Instruments web site at www.ti.com.
Power dissipation depends on input voltage and load
conditions. Power dissipation (PD) is equal to the
product of the output current times the voltage drop
across the output pass element (VIN to VOUT):
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Nov-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS73601QDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73601-Q1 :
Catalog: TPS73601
•
Enhanced Product: TPS73601-EP
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Nov-2010
Catalog - TI's standard catalog product
•
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73601QDBVRQ1
SOT-23
DBV
5
3000
179.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2010
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-23 DBV
SPQ
Length (mm) Width (mm) Height (mm)
203.0 203.0 35.0
TPS73601QDBVRQ1
5
3000
Pack Materials-Page 2
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