TPS73615-EP [TI]
具有反向电流保护功能的无电容 NMOS 400mA 低压降稳压器（增强型产品）;
| 型号： | TPS73615-EP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有反向电流保护功能的无电容 NMOS 400mA 低压降稳压器（增强型产品） 稳压器 |
| 文件： | 总27页 (文件大小：1063K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C–APRIL 2006–REVISED FEBRUARY 2009
CAP-FREE NMOS 400 mA LOW-DROPOUT REGULATORS
WITH REVERSE CURRENT PROTECTION
1
FEATURES
–
–
Adjustable Output from 1.2 V to 5.5 V
Custom Outputs Available
2
•
Controlled Baseline
–
–
–
One Assembly
APPLICATIONS
One Test Site
•
•
•
•
Portable/Battery-Powered Equipment
Post-Regulation for Switching Supplies
Noise-Sensitive Circuitry Such as VCOs
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
One Fabrication Site
•
•
Extended Temperature Performance of
–55°C to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
•
•
•
Enhanced Product-Change Notification
Optional
Optional
(1)
Qualification Pedigree
VIN
VOUT
IN
OUT
TPS736xx
GND
Stable With No Output Capacitor or Any Value
or Type of Capacitor
EN
NR
•
•
•
Input Voltage Range of 1.7 V to 5.5 V
Ultra-Low Dropout Voltage: 75 mV Typical
Excellent Load Transient Response—With or
Without Optional Output Capacitor
Optional
Typical Application Circuit for Fixed-Voltage Versions
•
•
New NMOS Topology Delivers Low Reverse
Leakage Current
Low Noise: 30 µVRMS Typical
(10 Hz to 100 kHz)
•
•
0.5% Initial Accuracy
1% Overall Accuracy Over Line, Load, and
Temperature
•
•
Less Than 1-µA Max IQ in Shutdown Mode
Thermal Shutdown and Specified Min/Max
Current Limit Protection
•
Available in Multiple Output Voltage Versions
–
Fixed Outputs of 1.2 V to 3.3 V
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
N/C - No internal connection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2009, Texas Instruments Incorporated
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C–APRIL 2006–REVISED FEBRUARY 2009.................................................................................................................................................. www.ti.com
DESCRIPTION
The TPS736xx family of low-dropout (LDO) linear voltage regulators uses a new topology—an NMOS pass
element in a voltage-follower configuration. This topology is stable using output capacitors with low ESR and
allows operation without a capacitor. It also provides high reverse blockage (low reverse current) and ground-pin
current that is nearly constant over all values of output current.
The TPS736xx uses an advanced BiCMOS process to yield high precision while delivering low dropout voltages
and low ground-pin current. Current consumption, when not enabled, is under 1 µA and ideal for portable
applications. The low output noise (30 µVRMS with 0.1-µF CNR) is ideal for powering VCOs. These devices are
protected by thermal shutdown and foldback current limit.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PRODUCT INFORMATION
(1)
PRODUCT
VOUT
xx is normal output voltage (for example, 25 = 2.5 V, 01 = Adjustable(2)).
yyy is package designator.
TPS736xxMyyyREP
z is package quantity.
(1) Additional output voltages from 1.25 V to 4.3 V in 100 mV increments are available on a quick-turn basis using innovative factory
EEPROM programming. Minimum order quantities apply; contact TI for details and availability.
(2) For fixed 1.2-V operation, tie FB to OUT.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TPS73601MDBVREP
TPS73615MDBVREP
TPS73618MDBVREP
TPS73625MDBVREP
TPS73630MDBVREP
TPS73632MDBVREP
TPS73633MDBVREP
TPS73601MDCQREP
TPS73601MDRBREP
TOP-SIDE MARKING
PJRM
T59
T60
SOT23 - DBV
T61
–55°C to 125°C
T62
T63
T64
SOT223 - DCQ
SON - DRB
PWZM
PMNM
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
TERMINAL FUNCTIONS
SOT23
(DBV)
SOT223
(DCQ)
3x3 SON
(DRB)
NAME
DESCRIPTION
PIN NO.
PIN NO.
PIN NO.
IN
GND
EN
1
2
3
1
3, 6
5
8
4, Pad
5
Unregulated input supply
Ground
Enable. Driving EN high turns on the regulator. Driving this pin low puts the regulator into
shutdown mode. See the Shutdown section under Applications Information for more details.
EN can be connected to IN if not used.
NR
FB
4
4
5
4
4
2
3
3
1
Fixed-voltage versions only. Connecting an external capacitor to this pin bypasses noise
generated by the internal bandgap, reducing output noise to low levels.
Feedback. Adjustable-voltage version only. This is the input to the control loop error
amplifier and is used to set the output voltage of the device.
OUT
Output of the regulator. There are no output capacitor requirements for stability.
2
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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP
TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C–APRIL 2006–REVISED FEBRUARY 2009
16
14
12
10
8
6
4
2
0
100
110
120
130
Continuous T − 5C
140
150
160
J
A. TJ = TJA × W + TA (Standard. JESD 51 conditions)
Figure 1. TPS736xxDBVzEP Estimated Device Life at Elevated Temperatures Electromigration Fail Mode
Copyright © 2006–2009, Texas Instruments Incorporated
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C–APRIL 2006–REVISED FEBRUARY 2009.................................................................................................................................................. www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
VIN range
–0.3 to 6
V
V
V
VEN range
–0.3 to 6
VOUT range
–0.3 to 5.5
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
Internally limited
Indefinite
See Dissipation Ratings Table
–55 to 150
–65 to 150
2
°C
°C
kV
V
Human-Body Model - HBM
ESD rating
Charged-Device Model - CDM
500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
POWER DISSIPATION RATINGS(1)
DERATING FACTOR
ABOVE TA = 25°C
T
A ≤ 25°C
TA = 70°C
TA = 85°C
BOARD
PACKAGE
RθJC
RθJA
POWER RATING POWER RATING POWER RATING
Low-K(2)
High-K(3)
Low-K(2)
High-K(3)
High-K(3)(4)
DBV
DBV
DCQ
DCQ
DRB
64°C/W
64°C/W
15°C/W
15°C/W
1.2°C/W
255°C/W
180°C/W
53°C/W
45°C/W
40°C/W
3.9 mW/°C
5.6 mW/°C
18.9 mW/°C
22.2 mW/°C
25.0 mW/°C
392 mW
556 mW
216 mW
306 mW
157 mW
222 mW
755 mW
889 mW
1000 mW
1887 mW
2222 mW
2500 mW
1038 mW
1222 mW
1375 mW
(1) See the Thermal Protection section for more information related to thermal design.
(2) The JEDEC Low-K (1s) board design used to derive this data was a 3 in × 3 in, two-layer board with 2 oz copper traces on top of the
board.
(3) The JEDEC High-K (2s2p) board design used to derive this data was a 3 in × 3 in, multilayer board with 1 oz internal power and ground
planes, and 2-oz copper traces on the top and bottom of the board.
(4) Based on preliminary thermal simulations.
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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP
TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C–APRIL 2006–REVISED FEBRUARY 2009
ELECTRICAL CHARACTERISTICS
over operating temperature range (TA = –55°C to 125°C), VIN = VOUT(nom) + 0.5 V(1), IOUT = 10 mA, VEN = 1.7 V, and
COUT = 0.1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
PARAMETER
Input voltage range(1) (2)
TEST CONDITIONS
MIN
1.7
TYP
MAX
5.5
UNIT
V
VIN
VFB
Internal reference (TPS73601)
TJ = 25°C
1.198
1.2
1.21
V
Output voltage range
(TPS73601)
5.5 –
VDO
VFB
–0.5%
–1%
V
VOUT
Nominal
TJ = 25°C
0.5%
Accuracy(1)
Over VIN, IOUT
and T
,
VOUT + 0.5 V ≤ VIN ≤ 5.5 V,
10 mA ≤ IOUT ≤ 400 mA
±0.5%
1%
ΔVOUT%/ΔVIN Line regulation(1)
VO(nom) + 0.5 V ≤ VIN ≤ 5.5 V
1 mA ≤ IOUT ≤ 400 mA
0.01
0.002
%/V
ΔVOUT%/ΔIOUT Load regulation
%/mA
10 mA ≤ IOUT ≤ 400 mA
0.0005
Dropout voltage(3)
VDO
IOUT = 400 mA
75
200
800
mV
(VIN = VOUT(nom) – 0.1 V)
ZO(DO)
ICL
Output impedance in dropout
Output current limit
1.7 V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0 V
0.25
650
Ω
400
mA
mA
µA
ISC
Short-circuit current
450
IREV
Reverse leakage current(4) (–IIN
)
VEN ≤ 0.5 V, 0 V ≤ VIN ≤ VOUT
0.1
15
550
1000
1
IOUT = 10 mA (IQ)
IOUT = 400 mA
400
IGND
Ground-pin current
µA
800
ISHDN
IFB
Shutdown current (IGND
)
VEN ≤ 0.5 V, VOUT ≤ VIN ≤ 5.5 V
0.02
µA
µA
FB pin current (TPS73601)
0.1
0.45
f = 100 Hz, IOUT = 400 mA
f = 10 kHz, IOUT = 400 mA
COUT = 10 µF, No CNR
58
Power-supply rejection ratio
(ripple rejection)
PSRR
dB
37
27 × VOUT
8.5 × VOUT
Output noise voltage
BW = 10 Hz to 100 kHz
VN
µVRMS
µs
COUT = 10 µF, CNR = 0.01 µF
VOUT = 3 V, RL = 30 Ω, COUT = 1 µF,
CNR = 0.01 µF
tSTR
Startup time
600
VEN(HI)
VEN(LO)
IEN(HI)
Enable high (enabled)
1.7
0
VIN
0.5
0.1
V
V
Enable low (shutdown)
Enable pin current (enabled)
VEN = 5.5 V
0.02
160
140
µA
Shutdown, temperature increasing
Reset, temperature decreasing
TSD
TA
Thermal shutdown temperature
Operating ambient temperature
°C
°C
-55
125
(1) Minimum VIN = VOUT + VDO or 1.7 V, whichever is greater.
(2) For VOUT(nom) < 1.6 V, when VIN ≤ 1.6 V, the output locks to VIN and may result in a damaging over-voltage level on the output. To avoid
this situation, disable the device before powering down the VIN
.
(3) VDO is not measured for the TPS73615 (VOUT(nom) = 1.5 V) since minimum VIN = 1.7 V.
(4) See the Applications section for more information.
Copyright © 2006–2009, Texas Instruments Incorporated
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C–APRIL 2006–REVISED FEBRUARY 2009.................................................................................................................................................. www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
IN
4-MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
27 kW
Bandgap
Error
Amp
Current
OUT
Limit
8 kW
GND
R
1
R
2
R + R = 80 kW
1
2
NR
Figure 2. Fixed-Voltage Version
IN
Standard 1% Resistor
Values for Common
Output Voltages
V
O
R
1
R
2
4-MHz
Charge Pump
1.2 V
1.5 V
1.8 V
2.5 V
2.8 V
3 V
Short
Open
23.2 kΩ
28 kΩ
95.3 kΩ
56.2 kΩ
36.5 kΩ
33.2 kΩ
30.9 kΩ
30.1 kΩ
EN
Thermal
Protection
39.2 kΩ
44.2 kΩ
46.4 kΩ
52.3 kΩ
Ref
Servo
27 kW
Bandgap
Error
Amp
3.3 V
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
OUT
FB
Current
Limit
R
R
19 kΩ for best
1
2
accuracy
GND
80 kW
8 kW
R
1
R
2
Figure 3. Adjustable-Voltage Version
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Product Folder Link(s): TPS73601-EP TPS73615-EP TPS73618-EP TPS73625-EP TPS73630-EP TPS73632-EP
TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C–APRIL 2006–REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
LOAD REGULATION
Referred to IOUT = 10 mA
LINE REGULATION
0.20
0.15
0.10
0.05
0
0.5
0.4
0.3
0.2
0.1
0
Referred to V = V
+ 0.5 V at I
= 10 mA
IN
OUT
OUT
−40°C
25°C
125°C
25°C
125°C
−
−
−
−
−
0.1
0.2
0.3
0.4
0.5
−
−
−
−
0.05
0.10
0.15
0.20
−40°C
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
50
100
150
200
250
300
350 400
−
VIN VOUT (V)
IOUT (mA)
Figure 4.
Figure 5.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
100
80
60
40
20
0
100
80
60
40
20
0
TPS73625DBV
TPS73625DBV
I
= 400 mA
125°C
OUT
25°C
−40°C
−
−
25
0
50
100
150
200
250
300
350
400
50
0
25
50
75
100
125
Temperature (°C)
IOUT (mA)
Figure 6.
OUTPUT VOLTAGE ACCURACY HISTOGRAM
Figure 7.
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
18
16
14
12
10
8
I
= 10 mA
OUT
I
= 10 mA
OUT
All Voltage Versions
25
20
15
10
5
6
4
2
0
0
Worst Case dV
/dT (ppm/°C)
VOUT Error (%)
OUT
Figure 8.
Figure 9.
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TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C–APRIL 2006–REVISED FEBRUARY 2009.................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
GROUND-PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
1000
900
800
700
600
500
400
300
200
100
0
1000
900
800
700
600
500
400
300
200
100
0
I
= 400 mA
OUT
V
IN
V
IN
V
IN
= 5.5 V
= 3 V
= 2 V
V
IN
V
IN
V
IN
= 5.5 V
= 4 V
= 2 V
0
100
200
300
400
−
−
25
50
0
25
50
75
100
125
Temperature (°C)
IOUT (mA)
Figure 10.
Figure 11.
CURRENT LIMIT vs VOUT
(FOLDBACK)
GROUND PIN CURRENT in SHUTDOWN
vs TEMPERATURE
1
800
700
600
500
400
300
200
100
0
V
= 0.5 V
= V + 0.5 V
ENABLE
V
IN
O
ICL
ISC
0.1
TPS73633
0.5
0.01
−
−
25
50
0
25
50
75
100
125
0
1.0
1.5
2.0
2.5
3.0
3.5
Temperature (°C)
VOUT (V)
Figure 12.
CURRENT LIMIT vs VIN
Figure 13.
CURRENT LIMIT vs TEMPERATURE
800
750
700
650
600
550
500
450
400
800
750
700
650
600
550
500
450
400
−
−
25
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
50
0
25
50
75
100
125
Temperature (°C)
VIN (V)
Figure 14.
Figure 15.
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C–APRIL 2006–REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
40
35
30
25
20
15
10
5
90
80
70
60
50
40
30
20
10
0
I
C
= 100 mA
= Any
I
C
= 1 mA
OUT
OUT
OUT
= 1 µF
OUT
I
= 1 mA
OUT
C
OUT
= 10 µF
I
= 100 mA
OUT
C
= 1 µF
I
C
= 1 mA
OUT
OUT
= Any
OUT
I
= 100 mA
OUT
Frequency = 100 kHz
C
OUT
= 10 µF
C
V
= 10 µF
= 2.5 V
OUT
OUT
I
= Any
OUT
C
OUT
= 0 µF
V
IN
= V
+ 1 V
OUT
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
−
VIN VOUT (V)
Frequency (Hz)
Figure 16.
Figure 17.
NOISE SPECTRAL DENSITY
NOISE SPECTRAL DENSITY
CNR = 0 µF
CNR = 0.01 µF
1
1
C
OUT
= 1 µF
C
OUT
= 1 µF
C
OUT
= 0 µF
0.1
0.1
C
OUT
= 10 µF
C
OUT
= 0 µF
C
OUT
= 10 µF
I
= 150 mA
100
I
= 150 mA
100
OUT
OUT
0.01
0.01
10
1k
10k
100k
10
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Figure 18.
Figure 19.
RMS NOISE VOLTAGE vs COUT
RMS NOISE VOLTAGE vs CNR
60
50
40
30
20
10
0
140
120
100
80
V
= 5 V
OUT
V
= 5 V
OUT
V
V
= 3.3 V
OUT
V
V
= 3.3 V
OUT
60
= 1.5 V
40
OUT
= 1.5 V
OUT
20
C
= 0 µF
C
= 0 µF
OUT
OUT
10 Hz < Frequency < 100 kHz
10 Hz < Frequency < 100 kHz
0
0.1
1
10
1p
10p
100p
1n
10n
µ
COUT ( F)
CNR (F)
Figure 20.
Figure 21.
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C–APRIL 2006–REVISED FEBRUARY 2009.................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
TPS73633
LOAD TRANSIENT RESPONSE
TPS73633
LINE TRANSIENT RESPONSE
V
IN
= 3.8 V
C
OUT
C
OUT
C
OUT
= 0 µF
= 1 µF
= 10 µF
I
= 400 mA
OUT
100 mV/tick
50 mV/tick
VOUT
VOUT
VOUT
IOUT
C
= 0 µF
OUT
50 mV/div
V
OUT
C
OUT
= 100 µF
50 mV/div
1 V/div
20 mV/tick
50 mA/tick
V
V
OUT
5.5 V
dV
IN
= 0.5 V/µs
400 mA
dt
4.5 V
10 mA
10 µs/div
IN
10 µs/div
Figure 22.
Figure 23.
TPS73633
TURNON RESPONSE
TPS73633
TURNOFF RESPONSE
R
C
= 1 kΩ
L
R
C
= 20 Ω
L
= 0 µF
VOUT
OUT
= 10 µF
OUT
R
C
= 20 Ω
L
R
= 20 Ω
= 1 µF
L
= 1 µF
1 V/div
1V/div
1V/div
OUT
C
OUT
R
C
= 1 kΩ
L
R
C
= 20 Ω
L
= 0 µF
OUT
= 10 µF
OUT
V
V
OUT
2 V
2 V
VEN
1 V/div
0 V
0 V
EN
100 µs/div
100 µs/div
Figure 24.
Figure 25.
TPS73633
POWER UP/POWER DOWN
IENABLE vs TEMPERATURE
6
5
4
3
2
1
0
1
2
10
1
VIN
VOUT
0.1
−
−
0.01
50 ms/div
−
−
25
50
0
25
50
75
100
125
Temperature (°C)
Figure 26.
Figure 27.
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C–APRIL 2006–REVISED FEBRUARY 2009
TYPICAL CHARACTERISTICS (continued)
For all voltage versions, TJ = 25°C, VIN = VOUT(nom) + 0.5 V, IOUT = 10 mA, VEN = 1.7 V, and COUT = 0.1 µF
(unless otherwise noted)
TPS73601
RMS NOISE VOLTAGE vs CADJ
TPS73601
IFB vs TEMPERATURE
60
55
50
45
40
35
30
25
20
160
140
120
100
80
60
V
C
R
= 2.5 V
= 0 µF
= 39.2 kΩ
40
OUT
OUT
20
1
10 Hz < Frequency < 100 kHz
0
10p
100p
1n
10n
−
−
25
50
0
25
50
75
100
125
Temperature (°C)
CFB (F)
Figure 28.
Figure 29.
TPS73601
LOAD TRANSIENT, ADJUSTABLE VERSION
TPS73601
LINE TRANSIENT, ADJUSTABLE VERSION
C
R
= 10 nF
= 39.2 kΩ
V
= 2.5 V
FB
1
OUT
CFB = 10 nF
C
= 0 µF
OUT
OUT
C
OUT
= 0 µF
V
OUT
100 mV/div
100 mV/div
V
200 mV/div
200 mV/div
OUT
C
= 10 µF
V
OUT
C
OUT
= 10 µF
V
OUT
4.5 V
400 mA
3.5 V
V
IN
10 mA
I
OUT
25 µs/div
5 µs/div
Figure 31.
Figure 30.
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TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
SGLS326C–APRIL 2006–REVISED FEBRUARY 2009.................................................................................................................................................. www.ti.com
APPLICATION INFORMATION
supply near the regulator. This counteracts reactive
The TPS736xx belongs to a family of new-generation
input sources and improves transient response, noise
LDO regulators that use an NMOS pass transistor to
rejection, and ripple rejection.
A
higher-value
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features, combined with low noise
and an enable input, make the TPS736xx ideal for
portable applications. This regulator family offers a
wide selection of fixed-output voltage versions and an
adjustable-output version. All versions have thermal
and overcurrent protection, including foldback current
limit.
capacitor may be necessary if large, fast rise-time
load transients are anticipated, or the device is
located several inches from the power source.
The TPS736xx does not require an output capacitor
for stability and has maximum phase margin with no
capacitor. It is designed to be stable for all available
types and values of capacitors. In applications where
VIN − VOUT < 0.5 V and multiple low ESR capacitors
are in parallel, ringing may occur when the product of
COUT and total ESR drops below 50 Ω. Total ESR
includes all parasitic resistance, including capacitor
ESR and board, socket, and solder-joint resistance.
In most applications, the sum of capacitor ESR and
trace resistance meets this requirement.
Figure 32 shows the basic circuit connections for the
fixed-voltage models. Figure 33 shows the
connections for the adjustable-output version
(TPS73601). R1 and R2 can be calculated for any
output voltage using the formula in Figure 33. Sample
resistor values for common output voltages are
shown in Figure 3. For the best accuracy, make the
parallel combination of R1 and R2 approximately 19
kΩ.
Output Noise
A precision band-gap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS736xx and
it generates approximately 32 µVRMS (10 Hz to
100 kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Optional input capacitor.
May improve source
impedance, noise, or PSRR.
Optional output capacitor.
May improve load transient,
noise, or PSRR.
VIN
VOUT
IN
OUT
TPS736xx
GND
EN
NR
VOUT
VREF
(R1 ) R2)
Optional bypass
capacitor to reduce
output noise
VN + 32 mVRMS
+ 32 mVRMS
R2
(1)
Since the value of VREF is 1.2 V, this relationship
reduces to:
Figure 32. Typical Application Circuit for
Fixed-Voltage Versions
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 27
VOUT(V)
(2)
Optional input capacitor.
May improve source
Optional output capacitor.
May improve load transient,
noise, or PSRR.
for the case of no CNR
.
impedance, noise, or PSRR.
VIN
VOUT
An internal 27-kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10 nF, the total noise in the 10-Hz to 100-kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
IN
OUT
FB
TPS736xx
R1
R2
CFB
EN
GND
Optional capacitor
reduces output noise
and improves
(R1 + R2)
×
1.204
VOUT
=
R1
mVRMS
V
ǒ Ǔ
VN(mVRMS) + 8.5
VOUT(V)
transient response.
(3)
Figure 33. Typical Application Circuit for
Adjustable-Voltage Versions
for CNR = 10 nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in Figure 21.
Input and Output Capacitor Requirements
Although an input capacitor is not required for
stability, it is good analog design practice to connect
a 0.1-µF to 1-µF low ESR capacitor across the input
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TPS73633-EP
TPS73601-EP, TPS73615-EP, TPS73618-EP
TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP
www.ti.com .................................................................................................................................................. SGLS326C–APRIL 2006–REVISED FEBRUARY 2009
The TPS73601 adjustable version does not have the
noise-reduction pin available. However, connecting a
feedback capacitor, CFB, from the output to the FB pin
reduces output noise and improves load transient
performance.
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the
dc
dropout.
Values
of
VIN – VOUT above this line ensure normal transient
response.
The TPS736xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250 µV of switching noise
at ~4 MHz; however, charge-pump noise contribution
is negligible at the output of the regulator for most
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under
worst-case conditions [full-scale instantaneous load
change with (VIN – VOUT) close to dc dropout levels],
values of IOUT and COUT
.
the TPS736xx can take
microseconds to return to the specified regulation
accuracy.
a couple of hundred
Board Layout Recommendation to Improve
PSRR and Noise Performance
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the GND pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the GND pin of the device.
Transient Response
The low open-loop output impedance provided by the
NMOS pass element in
configuration allows operation without an output
capacitor for many applications. As with any
regulator, the addition of a capacitor (nominal value
1 µF) from the output pin to ground reduces
undershoot magnitude but increases duration. In the
adjustable version, the addition of a capacitor, CFB
from the output to the adjust pin also improves the
transient response.
a
voltage-follower
Internal Current Limit
The TPS736xx internal current limit helps protect the
regulator during fault conditions. Foldback helps to
protect the regulator from damage during output
short-circuit conditions by reducing current limit when
VOUT drops below 0.5 V. See Figure 12 for a graph of
,
The TPS736xx does not have active pulldown when
the output is overvoltage. This allows applications
that connect higher voltage sources, such as
alternate power supplies, to the output. This also
results in an output overshoot of several percent if
load current quickly drops to zero when a capacitor is
connected to the output. The duration of overshoot
can be reduced by adding a load resistor. The
overshoot decays at a rate determined by output
capacitor COUT and the internal/external load
resistance. The rate of decay is given by:
IOUT vs VOUT
.
Shutdown
The enable (EN) pin is active high and is compatible
with standard TTL-CMOS levels. VEN below 0.5 V
(max) turns the regulator off and drops the ground-pin
current to approximately 10 nA. When shutdown
capability is not required, EN can be connected to
VIN. When a pullup resistor is used, and operation
down to 1.8 V is required, use pullup resistor values
below 50 kΩ.
Fixed-voltage version:
VOUT
dVńdt +
COUT 80 kW ø RLOAD
(4)
Dropout Voltage
Adjustable-voltage version:
The TPS736xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS-ON of the NMOS
pass element.
VOUT
dVńdt +
(
)
COUT 80 kW ø R1 ) R2 ø RLOAD
(5)
For large step changes in load current, the TPS736xx
requires a larger voltage drop from VIN to VOUT to
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SGLS326C–APRIL 2006–REVISED FEBRUARY 2009.................................................................................................................................................. www.ti.com
Reverse Current
35°C above the maximum expected ambient
condition of the application. This produces
worst-case junction temperature of 125°C at the
highest expected ambient temperature and
worst-case load.
a
The NMOS pass element of the TPS736xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
EN must be driven low before the input voltage is
removed. If this is not done, the pass element may be
left on due to stored charge on the gate.
The internal protection circuitry of the TPS736xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS736xx into thermal
shutdown degrades reliability.
After EN is driven low, no bias voltage is needed on
any pin for reverse current blocking. Note that
reverse current is specified as the current flowing out
of the IN pin due to voltage applied on the OUT pin.
There is additional current flowing into the OUT pin
due to the 80-kΩ internal resistor divider to ground
(see Figure 2 and Figure 3).
Power Dissipation
The ability to remove heat from the die is different for
each
package
type,
presenting
different
considerations in the PCB layout. The PCB area
around the device that is free of other components
moves the heat from the device to the ambient air.
Performance data for JEDEC low- and high-K boards
are shown in the Power Dissipation Ratings table.
Using heavier copper increases the effectiveness in
removing heat from the device. The addition of plated
through-holes to heat-dissipating layers also
improves the heatsink effectiveness.
For the TPS73601, reverse current may flow when
VFB is more than 1 V above VIN.
Thermal Protection
Thermal protection disables the output when the
junction temperature rises to approximately 160°C,
allowing the device to cool. When the junction
temperature cools to approximately 140°C, the output
circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This limits the dissipation of the regulator,
protecting it from damage due to overheating.
Power dissipation depends on input voltage and load
conditions. Power dissipation is equal to the product
of the output current times the voltage drop across
the output pass element (VIN to VOUT):
PD + (VIN * VOUT) IOUT
(6)
Power dissipation can be minimized by using the
lowest-possible input voltage necessary to ensure the
required output voltage.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to 125°C maximum. To
estimate the margin of safety in a complete design
Package Mounting
Solder-pad footprint recommendations for the
TPS736xx are presented in application bulletin Solder
Pad Recommendations for Surface-Mount Devices
(AB-132), available from the TI web site at
www.ti.com.
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
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PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TPS73601MDBVREP
TPS73601MDCQREP
TPS73601MDCQREPG4
TPS73601MDRBREP
TPS73615MDBVREP
TPS73618MDBVREP
TPS73625MDBVREP
TPS73630MDBVREP
TPS73632MDBVREP
TPS73633MDBVREP
TPS73633MDBVREPG4
V62/06626-01XE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-223
SOT-223
SON
DBV
DCQ
DCQ
DRB
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DCQ
DRB
DBV
DBV
DBV
5
6
6
8
5
5
5
5
5
5
5
5
6
8
5
5
5
3000
2500
2500
3000
3000
3000
3000
3000
3000
3000
3000
3000
2500
3000
3000
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-223
SON
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
V62/06626-01YE
Green (RoHS
& no Sb/Br)
V62/06626-01ZE
Green (RoHS
& no Sb/Br)
V62/06626-02XE
SOT-23
SOT-23
SOT-23
Green (RoHS
& no Sb/Br)
V62/06626-03XE
Green (RoHS
& no Sb/Br)
V62/06626-04XE
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
V62/06626-05XE
V62/06626-06XE
V62/06626-07XE
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
5
3000
3000
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73601-EP, TPS73615-EP, TPS73618-EP, TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP :
Catalog: TPS73601, TPS73615, TPS73618, TPS73625, TPS73630, TPS73632, TPS73633
•
Automotive: TPS73601-Q1
•
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
19-Nov-2011
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Nov-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73601MDBVREP
TPS73601MDRBREP
TPS73615MDBVREP
TPS73618MDBVREP
TPS73625MDBVREP
TPS73630MDBVREP
TPS73632MDBVREP
TPS73633MDBVREP
SOT-23
SON
DBV
DRB
DBV
DBV
DBV
DBV
DBV
DBV
5
8
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
179.0
330.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
12.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.3
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.3
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.0
1.4
1.4
1.4
1.4
1.4
1.4
4.0
8.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
12.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q2
Q3
Q3
Q3
Q3
Q3
Q3
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Nov-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS73601MDBVREP
TPS73601MDRBREP
TPS73615MDBVREP
TPS73618MDBVREP
TPS73625MDBVREP
TPS73630MDBVREP
TPS73632MDBVREP
TPS73633MDBVREP
SOT-23
SON
DBV
DRB
DBV
DBV
DBV
DBV
DBV
DBV
5
8
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
203.0
370.0
203.0
203.0
203.0
203.0
203.0
203.0
203.0
355.0
203.0
203.0
203.0
203.0
203.0
203.0
35.0
55.0
35.0
35.0
35.0
35.0
35.0
35.0
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
Pack Materials-Page 2
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