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TPS73625QDBVRQ1 [TI]

Cap-Free, NMOS, 400mA Low-Dropout Regulator with Reverse Current Protection;
TPS73625QDBVRQ1
型号： TPS73625QDBVRQ1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

Cap-Free, NMOS, 400mA Low-Dropout Regulator with Reverse Current Protection
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TPS736xx  
www.ti.com  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
Cap-Free, NMOS, 400mA Low-Dropout Regulator  
with Reverse Current Protection  
1
FEATURES  
DESCRIPTION  
2
•
Stable with No Output Capacitor or Any Value  
or Type of Capacitor  
The TPS736xx family of low-dropout (LDO) linear  
voltage regulators uses a new topology: an NMOS  
pass element in a voltage-follower configuration. This  
topology is stable using output capacitors with low  
ESR, and even allows operation without a capacitor.  
It also provides high reverse blockage (low reverse  
current) and ground pin current that is nearly constant  
over all values of output current.  
•
•
•
Input Voltage Range of 1.7V to 5.5V  
Ultra-Low Dropout Voltage: 75mV typ  
Excellent Load Transient Response—with or  
without Optional Output Capacitor  
•
New NMOS Topology Delivers Low Reverse  
Leakage Current  
•
•
•
Low Noise: 30mVRMS typ (10Hz to 100kHz)  
The TPS736xx uses an advanced BiCMOS process  
to yield high precision while delivering very low  
dropout voltages and low ground pin current. Current  
consumption, when not enabled, is under 1mA and  
ideal for portable applications. The extremely low  
output noise (30mVRMS with 0.1mF CNR) is ideal for  
powering VCOs. These devices are protected by  
thermal shutdown and foldback current limit.  
0.5% Initial Accuracy  
1% Overall Accuracy Over Line, Load, and  
Temperature  
•
•
Less Than 1mA max IQ in Shutdown Mode  
Thermal Shutdown and Specified Min/Max  
Current Limit Protection  
space  
•
Available in Multiple Output Voltage Versions  
–
–
–
Fixed Outputs of 1.20V to 5.0V  
Adjustable Output from 1.20V to 5.5V  
Custom Outputs Available  
DRB PACKAGE  
3mmx 3mm SON  
(TOP VIEW)  
DBV PACKAGE  
SOT23  
(TOP VIEW)  
OUT  
N/C  
1
2
3
4
8
7
6
5
IN  
1
5
IN  
GND  
EN  
OUT  
N/C  
N/C  
EN  
APPLICATIONS  
NR/FB  
GND  
2
•
•
•
•
Portable/Battery-Powered Equipment  
Post-Regulation for Switching Supplies  
Noise-Sensitive Circuitry such as VCOs  
Point of Load Regulation for DSPs, FPGAs,  
ASICs, and Microprocessors  
NR/FB  
3
4
DCQ PACKAGE  
SOT223  
(TOP VIEW)  
Optional  
Optional  
TAB IS GND  
6
3
VIN  
VOUT  
IN  
OUT  
TPS736xx  
GND  
1
2
4
5
EN  
NR  
ON  
IN  
GND  
EN  
OFF  
OUT NR/FB  
Optional  
Typical Application Circuit for Fixed-Voltage Versions  
space  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
All trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2003–2010, Texas Instruments Incorporated  
TPS736xx  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ORDERING INFORMATION(1)  
(2)  
PRODUCT  
VOUT  
TPS736xx yy yz  
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).  
YYY is package designator.  
Z is package quantity.  
(1) For the most current specification and package information, refer to the Package Option Addendum located at the end of this datasheet  
or see the TI website at www.ti.com.  
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available on a quick-turn basis using innovative factory  
EEPROM programming. Minimum order quantities apply; contact factory for details and availability.  
(3) For fixed 1.20V operation, tie FB to OUT.  
ABSOLUTE MAXIMUM RATINGS  
over operating free-air temperature range unless otherwise noted(1)  
PARAMETER  
TPS736xx  
–0.3 to 6.0  
–0.3 to 6.0  
–0.3 to 5.5  
–0.3 to 6.0  
Internally limited  
Indefinite  
UNIT  
VIN range  
V
V
V
V
VEN range  
VOUT range  
VNR, VFB range  
Peak output current  
Output short-circuit duration  
Continuous total power dissipation  
Junction temperature range, TJ  
Storage temperature range  
ESD rating, HBM  
See Thermal Information Table  
–55 to +150  
°C  
°C  
kV  
V
–65 to +150  
2
ESD rating, CDM  
500  
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics  
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.  
2
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Copyright © 2003–2010, Texas Instruments Incorporated  
TPS736xx  
www.ti.com  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
THERMAL INFORMATION  
TPS736xx(3)  
THERMAL METRIC(1)(2)  
DRB  
8 PINS  
47.8  
83  
DCQ  
6 PINS  
70.4  
70  
DBV  
5 PINS  
180  
UNITS  
qJA  
Junction-to-ambient thermal resistance(4)  
Junction-to-case (top) thermal resistance(5)  
Junction-to-board thermal resistance(6)  
Junction-to-top characterization parameter(7)  
Junction-to-board characterization parameter(8)  
Junction-to-case (bottom) thermal resistance(9)  
qJCtop  
qJB  
64  
N/A  
N/A  
35  
°C/W  
yJT  
2.1  
6.8  
N/A  
yJB  
17.8  
12.1  
30.1  
6.3  
N/A  
qJCbot  
N/A  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.  
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.  
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as  
specified in the JESD51 series. The following assumptions are used in the simulations:  
(a) i. DRB: The exposed pad is connected to the PCB ground layer through  
ii. DCQ: The exposed pad is connected to the PCB ground layer through  
. iii. DBV: There is no exposed pad with the DBV package.  
a
a
2x2 thermal via array.  
3x2 thermal via array.  
.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper  
coverage.  
.
ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.  
. iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper  
coverage.  
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To  
understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.  
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as  
specified in JESD51-7, in an environment described in JESD51-2a.  
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific  
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB  
temperature, as described in JESD51-8.  
(7) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).  
(8) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).  
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific  
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
Copyright © 2003–2010, Texas Instruments Incorporated  
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TPS736xx  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
www.ti.com  
ELECTRICAL CHARACTERISTICS  
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5V(1), IOUT = 10mA, VEN = 1.7V, and  
COUT = 0.1mF, unless otherwise noted. Typical values are at TJ = +25°C.  
PARAMETER  
Input voltage range(1) (2)  
TEST CONDITIONS  
MIN  
1.7  
TYP  
MAX  
5.5  
UNIT  
V
VIN  
VFB  
Internal reference (TPS73601)  
TJ = +25°C  
1.198  
1.20  
1.210  
V
Output voltage range  
(TPS73601)(3)  
VFB  
–0.5  
–1.0  
5.5 – VDO  
+0.5  
V
VOUT  
Nominal  
TJ = +25°C  
Accuracy(1)  
%
(4)  
over VIN, IOUT  
and T  
,
VOUT + 0.5V ≤ VIN ≤ 5.5V;  
10mA ≤ IOUT ≤ 400mA  
±0.5  
+1.0  
ΔVOUT%/ΔVIN Line regulation(1)  
VO(nom) + 0.5V ≤ VIN ≤ 5.5V  
1mA ≤ IOUT ≤ 400mA  
0.01  
0.002  
0.0005  
%/V  
ΔVOUT%/ΔIOUT Load regulation  
%/mA  
10mA ≤ IOUT ≤ 400mA  
Dropout voltage(5)  
VDO  
IOUT = 400mA  
75  
200  
mV  
(VIN = VOUT(nom) – 0.1V)  
ZO(DO)  
ICL  
Output impedance in dropout  
Output current limit  
1.7V ≤ VIN ≤ VOUT + VDO  
VOUT = 0.9 × VOUT(nom)  
3.6V ≤ VIN ≤ 4.2V, 0°C ≤ TJ ≤ +70°C  
VOUT = 0V  
0.25  
650  
Ω
400  
500  
800  
800  
mA  
mA  
mA  
mA  
ISC  
Short-circuit current  
Reverse leakage current(6) (–IIN  
450  
0.1  
IREV  
)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT  
10  
IOUT = 10mA (IQ)  
IOUT = 400mA  
400  
800  
550  
IGND  
GND pin current  
mA  
1000  
V
EN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5,  
ISHDN  
IFB  
Shutdown current (IGND  
)
0.02  
1
mA  
mA  
–40°C ≤ TJ ≤ +100°C  
FB pin current (TPS73601)  
0.1  
58  
0.3  
f = 100Hz, IOUT = 400mA  
f = 10KHz, IOUT = 400mA  
COUT = 10mF, No CNR  
Power-supply rejection ratio  
(ripple rejection)  
PSRR  
dB  
37  
27 × VOUT  
8.5 × VOUT  
Output noise voltage  
BW = 10Hz – 100KHz  
VN  
mVRMS  
ms  
COUT = 10mF, CNR = 0.01mF  
VOUT = 3V, RL = 30Ω COUT = 1mF,  
CNR = 0.01mF  
tSTR  
Startup time  
600  
VEN(HI)  
VEN(LO)  
IEN(HI)  
EN pin high (enabled)  
EN pin low (shutdown)  
EN pin current (enabled)  
1.7  
0
VIN  
0.5  
0.1  
V
V
VEN = 5.5V  
0.02  
+160  
+140  
mA  
Shutdown, temperature increasing  
Reset, temperature decreasing  
TSD  
TJ  
Thermal shutdown temperature  
Operating junction temperature  
°C  
°C  
–40  
+125  
(1) Minimum VIN = VOUT + VDO or 1.7V, whichever is greater.  
(2) For VOUT(nom) < 1.6V, when VIN ≤ 1.6V, the output will lock to VIN and may result in a damaging over-voltage level on the output. To  
avoid this situation, disable the device before powering down the VIN  
.
(3) TPS73601 is tested at VOUT = 2.5V.  
(4) Tolerance of external resistors not included in this specification.  
(5) VDO is not measured for fixed output versions with VOUT(nom) < 1.8V.  
(6) Fixed-voltage versions only; refer to Applications section for more information.  
4
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Copyright © 2003–2010, Texas Instruments Incorporated  
TPS736xx  
www.ti.com  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
FUNCTIONAL BLOCK DIAGRAMS  
IN  
4MHz  
Charge Pump  
EN  
Thermal  
Protection  
Ref  
Servo  
Ω
27k  
Bandgap  
Error  
Amp  
Current  
Limit  
OUT  
Ω
8k  
GND  
R1  
R2  
Ω
R1 + R2 = 80k  
NR  
Figure 1. Fixed Voltage Version  
IN  
Table 1. Standard 1%  
Resistor Values for  
Common Output Voltages  
V
O
R
1
R
2
4MHz  
1.2V  
1.5V  
1.8V  
2.5V  
2.8V  
3.0V  
3.3V  
Short  
Open  
Charge Pump  
23.2kΩ  
28.0kΩ  
39.2kΩ  
44.2kΩ  
46.4kΩ  
52.3kΩ  
95.3kΩ  
56.2kΩ  
36.5kΩ  
33.2kΩ  
30.9kΩ  
30.1kΩ  
EN  
Thermal  
Protection  
Ref  
Servo  
Ω
27k  
Bandgap  
Error  
Amp  
NOTE: V  
= (R + R )/R × 1.204;  
1 2 2  
OUT  
OUT  
FB  
Current  
Limit  
R
R
19kΩ for best  
1
2
accuracy.  
GND  
Ω
80k  
Ω
8k  
R1  
R2  
Figure 2. Adjustable Voltage Version  
Copyright © 2003–2010, Texas Instruments Incorporated  
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TPS736xx  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
www.ti.com  
PIN CONFIGURATIONS  
DRB PACKAGE  
3mm x 3mm SON  
(TOP VIEW)  
DCQ PACKAGE  
SOT223  
(TOP VIEW)  
DBV PACKAGE  
SOT23  
(TOP VIEW)  
OUT  
N/C  
1
2
3
4
8
7
6
5
IN  
TAB IS GND  
N/C  
N/C  
EN  
6
3
5
4
IN  
GND  
EN  
1
2
3
OUT  
NR/FB  
GND  
NR/FB  
1
2
4
5
IN  
GND  
EN  
OUT  
NR/FB  
PIN DESCRIPTIONS  
SOT23  
(DBV)  
SOT223  
(DCQ)  
3x3 SON  
(DRB)  
NAME  
IN  
PIN NO.  
PIN NO.  
PIN NO.  
DESCRIPTION  
1
2
1
8
Input supply  
Ground  
GND  
3, 6  
4, Pad  
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the  
regulator into shutdown mode. Refer to the Shutdown section under Applications  
Information for more details. EN can be connected to IN if not used.  
EN  
NR  
3
4
5
4
5
3
Fixed voltage versions only—connecting an external capacitor to this pin bypasses  
noise generated by the internal bandgap, reducing output noise to very low levels.  
Adjustable voltage version only—this is the input to the control loop error amplifier,  
and is used to set the output voltage of the device.  
FB  
4
5
4
2
3
1
OUT  
Output of the Regulator. There are no output capacitor requirements for stability.  
6
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Copyright © 2003–2010, Texas Instruments Incorporated  
TPS736xx  
www.ti.com  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
TYPICAL CHARACTERISTICS  
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise  
noted.  
LOAD REGULATION  
LINE REGULATION  
0.20  
0.15  
0.10  
0.05  
0
0.5  
0.4  
0.3  
0.2  
0.1  
0
Referred to IOUT = 10mA  
Referred to VIN = VOUT + 0.5V at IOUT = 10mA  
−
_
40 C  
_
+25  
C
_
+25  
C
_
+125 C  
_
+125  
C
−
−
−
−
−
0.1  
0.2  
0.3  
0.4  
0.5  
−
−
−
−
0.05  
0.10  
0.15  
0.20  
−
_
40  
C
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
0
50  
100  
150  
200  
250  
300  
350 400  
−
VIN VOUT (V)  
IOUT (mA)  
Figure 3.  
Figure 4.  
DROPOUT VOLTAGE vs OUTPUT CURRENT  
DROPOUT VOLTAGE vs TEMPERATURE  
100  
80  
60  
40  
20  
0
100  
80  
60  
40  
20  
0
TPS73625DBV  
IOUT = 400mA  
TPS73625DBV  
_
+125  
C
_
+25  
C
−
_
40  
C
−
−
25  
0
50  
100  
150  
200  
250  
300  
350  
400  
50  
0
25  
50  
75  
100  
125  
_
IOUT (mA)  
Temperature ( C)  
Figure 5.  
Figure 6.  
OUTPUT VOLTAGE ACCURACY HISTOGRAM  
OUTPUT VOLTAGE DRIFT HISTOGRAM  
30  
18  
16  
14  
12  
10  
8
IOUT = 10mA  
All Voltage Versions  
IOUT = 10mA  
25  
20  
15  
10  
5
6
4
2
0
0
VOUT Error (%)  
_
Worst Case dVOUT/dT (ppm/ C)  
Figure 7.  
Figure 8.  
Copyright © 2003–2010, Texas Instruments Incorporated  
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TPS736xx  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
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TYPICAL CHARACTERISTICS (continued)  
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise  
noted.  
GROUND PIN CURRENT vs OUTPUT CURRENT  
GROUND PIN CURRENT vs TEMPERATURE  
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
1000  
900  
800  
700  
600  
500  
400  
300  
200  
100  
0
IOUT = 400mA  
VIN = 5.5V  
VIN = 4V  
VIN = 2V  
VIN = 5.5V  
VIN = 3V  
VIN = 2V  
0
100  
200  
300  
400  
−
−
25  
50  
0
25  
50  
75  
100  
125  
IOUT (mA)  
_
Temperature ( C)  
Figure 9.  
Figure 10.  
GROUND PIN CURRENT in SHUTDOWN  
vs TEMPERATURE  
CURRENT LIMIT vs VOUT  
(FOLDBACK)  
1
800  
700  
600  
500  
400  
300  
200  
100  
0
TPS73633  
ICL  
VENABLE = 0.5V  
VIN = VO + 0.5V  
ISC  
0.1  
0.01  
-0.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
−
−
25  
50  
0
25  
50  
75  
100  
125  
Output Voltage (V)  
_
Temperature ( C)  
Figure 11.  
Figure 12.  
CURRENT LIMIT vs VIN  
CURRENT LIMIT vs TEMPERATURE  
800  
750  
700  
650  
600  
550  
500  
450  
400  
800  
750  
700  
650  
600  
550  
500  
450  
400  
−
−
25  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
50  
0
25  
50  
75  
100  
125  
_
VIN (V)  
Temperature ( C)  
Figure 13.  
Figure 14.  
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TPS736xx  
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SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
TYPICAL CHARACTERISTICS (continued)  
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise  
noted.  
PSRR (RIPPLE REJECTION) vs FREQUENCY  
PSRR (RIPPLE REJECTION) vs VIN – VOUT  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
40  
35  
30  
25  
20  
15  
10  
5
IOUT = 100mA  
COUT = Any  
IOUT = 1mA  
µ
COUT = 1  
F
IOUT = 1mA  
COUT = 10 F  
µ
IO = 100mA  
µ
CO = 1 F  
IOUT = 1mA  
COUT = Any  
Frequency = 10kHz  
IOUT = 100mA  
COUT = 10  
COUT = 10mF  
µ
F
VOUT = 2.5V  
IOUT = Any  
VIN = VOUT + 1V  
µ
IOUT = 100mA  
COUT = 0  
F
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0  
10  
100  
1k  
10k  
100k  
1M  
10M  
V
IN - VOUT (V)  
Frequency (Hz)  
Figure 15.  
Figure 16.  
NOISE SPECTRAL DENSITY  
NOISE SPECTRAL DENSITY  
CNR = 0mF  
CNR = 0.01mF  
1
1
µ
COUT = 1  
F
µ
COUT = 1  
F
µ
COUT = 0  
F
0.1  
0.1  
µ
COUT = 10 F  
µ
COUT = 0  
F
µ
COUT = 10  
F
IOUT = 150mA  
IOUT = 150mA  
10 100  
0.01  
0.01  
10  
100  
1k  
10k  
100k  
1k  
10k  
100k  
Frequency (Hz)  
Frequency (Hz)  
Figure 17.  
Figure 18.  
RMS NOISE VOLTAGE vs COUT  
RMS NOISE VOLTAGE vs CNR  
60  
50  
40  
30  
20  
10  
0
140  
120  
100  
80  
VOUT = 5.0V  
VOUT = 5.0V  
VOUT = 3.3V  
VOUT = 1.5V  
VOUT = 3.3V  
VOUT = 1.5V  
60  
40  
20  
µ
CNR = 0.01 F  
µ
COUT = 0 F  
10Hz < Frequency < 100kHz  
10Hz < Frequency < 100kHz  
0
0.1  
1
10  
1p  
10p  
100p  
1n  
10n  
µ
COUT ( F)  
CNR (F)  
Figure 19.  
Figure 20.  
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TPS736xx  
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TYPICAL CHARACTERISTICS (continued)  
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise  
noted.  
TPS73633  
TPS73633  
LOAD TRANSIENT RESPONSE  
LINE TRANSIENT RESPONSE  
µ
µ
µ
VIN = 3.8V  
COUT = 0  
F
F
F
IOUT = 400mA  
100mV/tick  
50mV/tick  
20mV/tick  
50mA/tick  
VOUT  
VOUT  
VOUT  
IOUT  
µ
COUT = 0  
F
50mV/div  
VOUT  
COUT = 1  
µ
COUT = 100  
F
COUT = 10  
50mV/div  
1V/div  
VOUT  
dVIN  
dt  
5.5V  
µ
= 0.5V/  
s
400mA  
4.5V  
VIN  
10mA  
µ
10 s/div  
µ
10 s/div  
Figure 21.  
Figure 22.  
TPS73633  
TPS73633  
TURN-ON RESPONSE  
TURN-OFF RESPONSE  
Ω
RL = 1k  
RL = 20Ω  
COUT = 10µF  
VOUT  
COUT = 0µF  
Ω
RL = 20  
Ω
RL = 20  
1V/div  
1V/div  
1V/div  
1V/div  
µ
COUT = 1  
F
µ
COUT = 1  
F
Ω
RL = 1k  
Ω
RL = 20  
COUT = 0µF  
µ
COUT = 10  
F
VOUT  
2V  
2V  
VEN  
0V  
0V  
VEN  
µ
100 s/div  
100µs/div  
Figure 23.  
Figure 24.  
TPS73633  
POWER UP / POWER DOWN  
IENABLE vs TEMPERATURE  
10  
1
6
5
4
3
2
1
0
VIN  
VOUT  
0.1  
−
−
1
2
0.01  
−
−
25  
50ms/div  
50  
0
25  
50  
75  
100  
125  
_
Temperature ( C)  
Figure 25.  
Figure 26.  
10  
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SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
TYPICAL CHARACTERISTICS (continued)  
For all voltage versions, at TJ = +25°C, VIN = VOUT(nom) + 0.5V, IOUT = 10mA, VEN = 1.7V, and COUT = 0.1mF, unless otherwise  
noted.  
TPS73601  
TPS73601  
RMS NOISE VOLTAGE vs CFB  
IFB vs TEMPERATURE  
60  
55  
50  
45  
40  
35  
30  
25  
20  
160  
140  
120  
100  
80  
60  
VOUT = 2.5V  
40  
µ
COUT = 0 F  
Ω
R1 = 39.2k  
20  
10Hz < Frequency < 100kHz  
0
10p  
100p  
1n  
10n  
−
−
25  
50  
0
25  
50  
75  
100  
125  
CFB (F)  
_
Temperature ( C)  
Figure 27.  
Figure 28.  
TPS73601  
TPS73601  
LOAD TRANSIENT, ADJUSTABLE VERSION  
LINE TRANSIENT, ADJUSTABLE VERSION  
CFB = 10nF  
VOUT = 2.5V  
CFB = 10nF  
Ω
R1 = 39.2k  
µ
COUT = 0  
F
µ
COUT = 0 F  
VOUT  
VOUT  
100mV/div  
100mV/div  
200mV/div  
200mV/div  
µ
COUT = 10 F  
VOUT  
µ
COUT = 10  
F
VOUT  
4.5V  
400mA  
3.5V  
VIN  
10mA  
IOUT  
µ
µ
s/div  
5
25 s/div  
Figure 29.  
Figure 30.  
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11  
TPS736xx  
SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
www.ti.com  
APPLICATION INFORMATION  
For best accuracy, make the parallel combination of  
R1 and R2 approximately equal to 19kΩ. This 19kΩ,  
in addition to the internal 8kΩ resistor, presents the  
same impedance to the error amp as the 27kΩ  
bandgap reference output. This impedance helps  
compensate for leakages into the error amp  
terminals.  
The TPS736xx belongs to a family of new generation  
LDO regulators that use an NMOS pass transistor to  
achieve ultra-low-dropout performance, reverse  
current blockage, and freedom from output capacitor  
constraints. These features, combined with low noise  
and an enable input, make the TPS736xx ideal for  
portable applications. This regulator family offers a  
wide selection of fixed output voltage versions and an  
adjustable output version. All versions have thermal  
and over-current protection, including foldback  
current limit.  
INPUT AND OUTPUT CAPACITOR  
REQUIREMENTS  
Although an input capacitor is not required for  
stability, it is good analog design practice to connect  
a 0.1mF to 1mF low ESR capacitor across the input  
supply near the regulator. This counteracts reactive  
input sources and improves transient response, noise  
Figure 31 shows the basic circuit connections for the  
fixed voltage models. Figure 32 gives the connections  
for the adjustable output version (TPS73601).  
rejection, and ripple rejection.  
A
higher-value  
Optional input capacitor.  
May improve source  
Optional output capacitor.  
May improve load transient,  
noise, or PSRR.  
capacitor may be necessary if large, fast rise-time  
load transients are anticipated or the device is  
located several inches from the power source.  
impedance, noise, or PSRR.  
VIN  
VOUT  
IN  
OUT  
TPS736xx  
GND  
The TPS736xx does not require an output capacitor  
for stability and has maximum phase margin with no  
capacitor. It is designed to be stable for all available  
types and values of capacitors. In applications where  
multiple low ESR capacitors are in parallel, ringing  
may occur when the product of COUT and total ESR  
drops below 50nΩF. Total ESR includes all parasitic  
resistances, including capacitor ESR and board,  
socket, and solder joint resistance. In most  
applications, the sum of capacitor ESR and trace  
resistance will meet this requirement.  
EN  
NR  
ON  
OFF  
Optional bypass  
capacitor to reduce  
output noise.  
Figure 31. Typical Application Circuit for  
Fixed-Voltage Versions  
OUTPUT NOISE  
Optional input capacitor.  
May improve source  
Optional output capacitor.  
May improve load transient,  
noise, or PSRR.  
A precision band-gap reference is used to generate  
the internal reference voltage, VREF. This reference is  
the dominant noise source within the TPS736xx and  
it generates approximately 32mVRMS (10Hz to  
100kHz) at the reference output (NR). The regulator  
control loop gains up the reference noise with the  
same gain as the reference voltage, so that the noise  
voltage of the regulator is approximately given by:  
impedance, noise, or PSRR.  
VIN  
VOUT  
IN  
OUT  
TPS73601  
R1  
CFB  
EN  
GND  
FB  
ON  
R2  
OFF  
Optional capacitor  
reduces output noise  
and improves  
(R1 + R2)  
R2  
VOUT  
=
x 1.204  
transient response.  
VOUT  
VREF  
(R1 ) R2)  
VN + 32mVRMS  
 
+ 32mVRMS  
 
R2  
(1)  
Figure 32. Typical Application Circuit for  
Adjustable-Voltage Version  
Since the value of VREF is 1.2V, this relationship  
reduces to:  
R1 and R2 can be calculated for any output voltage  
using the formula shown in Figure 32. Sample  
resistor values for common output voltages are  
shown in Figure 2.  
mVRMS  
V
ǒ Ǔ  
VN(mVRMS) + 27  
  VOUT(V)  
(2)  
for the case of no CNR  
.
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SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
An internal 27kΩ resistor in series with the noise  
reduction pin (NR) forms a low-pass filter for the  
voltage reference when an external noise reduction  
capacitor, CNR, is connected from NR to ground. For  
CNR = 10nF, the total noise in the 10Hz to 100kHz  
bandwidth is reduced by a factor of ~3.2, giving the  
approximate relationship:  
ENABLE PIN AND SHUTDOWN  
The enable pin (EN) is active high and is compatible  
with standard TTL-CMOS levels. A VEN below 0.5V  
(max) turns the regulator off and drops the GND pin  
current to approximately 10nA. When EN is used to  
shutdown the regulator, all charge is removed from  
the pass transistor gate, and the output ramps back  
up to a regulated VOUT (see Figure 23).  
mVRMS  
V
ǒ Ǔ  
VN(mVRMS) + 8.5  
  VOUT(V)  
(3)  
When shutdown capability is not required, EN can be  
connected to VIN. However, the pass gate may not be  
discharged using this configuration, and the pass  
transistor may be left on (enhanced) for a significant  
time after VIN has been removed. This scenario can  
result in reverse current flow (if the IN pin is low  
impedance) and faster ramp times upon power-up. In  
addition, for VIN ramp times slower than a few  
milliseconds, the output may overshoot upon  
power-up.  
for CNR = 10nF.  
This noise reduction effect is shown as RMS Noise  
Voltage vs CNR in the Typical Characteristics section.  
The TPS73601 adjustable version does not have the  
NR pin available. However, connecting a feedback  
capacitor, CFB, from the output to the feedback pin  
(FB) reduces output noise and improves load  
transient performance.  
Note that current limit foldback can prevent device  
start-up under some conditions. See the Internal  
Current Limit section for more information.  
The TPS736xx uses an internal charge pump to  
develop an internal supply voltage sufficient to drive  
the gate of the NMOS pass element above VOUT. The  
charge pump generates ~250mV of switching noise at  
~4MHz; however, charge-pump noise contribution is  
negligible at the output of the regulator for most  
DROPOUT VOLTAGE  
The TPS736xx uses an NMOS pass transistor to  
achieve extremely low dropout. When (VIN – VOUT) is  
less than the dropout voltage (VDO), the NMOS pass  
device is in its linear region of operation and the  
input-to-output resistance is the RDS-ON of the NMOS  
pass element.  
values of IOUT and COUT  
.
BOARD LAYOUT RECOMMENDATION TO  
IMPROVE PSRR AND NOISE PERFORMANCE  
To improve ac performance such as PSRR, output  
noise, and transient response, it is recommended that  
the board be designed with separate ground planes  
for VIN and VOUT, with each ground plane connected  
only at the GND pin of the device. In addition, the  
ground connection for the bypass capacitor should  
connect directly to the GND pin of the device.  
For large step changes in load current, the TPS736xx  
requires a larger voltage drop from VIN to VOUT to  
avoid degraded transient response. The boundary of  
this transient dropout region is approximately twice  
the dc dropout. Values of VIN – VOUT above this line  
ensure normal transient response.  
Operating in the transient dropout region can cause  
an increase in recovery time. The time required to  
recover from a load transient is a function of the  
magnitude of the change in load current rate, the rate  
of change in load current, and the available  
headroom (VIN to VOUT voltage drop). Under  
worst-case conditions [full-scale instantaneous load  
change with (VIN – VOUT) close to dc dropout levels],  
INTERNAL CURRENT LIMIT  
The TPS736xx internal current limit helps protect the  
regulator during fault conditions. Foldback current  
limit helps to protect the regulator from damage  
during output short-circuit conditions by reducing  
current limit when VOUT drops below 0.5V. See  
Figure 12 in the Typical Characteristics section.  
the TPS736xx can take  
a couple of hundred  
Note from Figure 12 that approximately –0.2V of VOUT  
results in a current limit of 0mA. Therefore, if OUT is  
forced below –0.2V before EN goes high, the device  
may not start up. In applications that work with both a  
positive and negative voltage supply, the TPS736xx  
should be enabled first.  
microseconds to return to the specified regulation  
accuracy.  
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TPS736xx  
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TRANSIENT RESPONSE  
After the EN pin is driven low, no bias voltage is  
needed on any pin for reverse current blocking. Note  
that reverse current is specified as the current flowing  
out of the IN pin due to voltage applied on the OUT  
pin. There will be additional current flowing into the  
OUT pin due to the 80kΩ internal resistor divider to  
ground (see Figure 1 and Figure 2).  
The low open-loop output impedance provided by the  
NMOS pass element in  
a
voltage follower  
configuration allows operation without an output  
capacitor for many applications. As with any  
regulator, the addition of a capacitor (nominal value  
1mF) from the OUT pin to ground will reduce  
undershoot magnitude but increase its duration. In  
the adjustable version, the addition of a capacitor,  
CFB, from the OUT pin to the FB pin will also improve  
the transient response.  
For the TPS73601, reverse current may flow when  
VFB is more than 1.0V above VIN.  
THERMAL PROTECTION  
The TPS736xx does not have active pull-down when  
the output is over-voltage. This allows applications  
that connect higher voltage sources, such as  
alternate power supplies, to the output. This also  
results in an output overshoot of several percent if  
load current quickly drops to zero when a capacitor is  
connected to the output. The duration of overshoot  
can be reduced by adding a load resistor. The  
overshoot decays at a rate determined by output  
capacitor COUT and the internal/external load  
resistance. The rate of decay is given by:  
Thermal protection disables the output when the  
junction temperature rises to approximately +160°C,  
allowing the device to cool. When the junction  
temperature cools to approximately +140°C, the  
output circuitry is again enabled. Depending on power  
dissipation, thermal resistance, and ambient  
temperature, the thermal protection circuit may cycle  
on and off. This limits the dissipation of the regulator,  
protecting it from damage due to overheating.  
Any tendency to activate the thermal protection circuit  
indicates excessive power dissipation or an  
inadequate heat sink. For reliable operation, junction  
temperature should be limited to +125°C maximum.  
To estimate the margin of safety in a complete design  
(including heat sink), increase the ambient  
temperature until the thermal protection is triggered;  
use worst-case loads and signal conditions. For good  
reliability, thermal protection should trigger at least  
+35°C above the maximum expected ambient  
(Fixed Voltage Version)  
VOUT  
dVńdt +  
COUT   80kW ø RLOAD  
(4)  
(Adjustable Voltage Version)  
VOUT  
condition of your application. This produces  
worst-case junction temperature of +125°C at the  
highest expected ambient temperature and  
worst-case load.  
a
dVńdt +  
(
)
COUT   80kW ø R1 ) R2 ø RLOAD  
(5)  
REVERSE CURRENT  
The internal protection circuitry of the TPS736xx has  
been designed to protect against overload conditions.  
It was not intended to replace proper heat sinking.  
Continuously running the TPS736xx into thermal  
shutdown degrades device reliability.  
The NMOS pass element of the TPS736xx provides  
inherent protection against current flow from the  
output of the regulator to the input when the gate of  
the pass device is pulled low. To ensure that all  
charge is removed from the gate of the pass element,  
the EN pin must be driven low before the input  
voltage is removed. If this is not done, the pass  
element may be left on due to stored charge on the  
gate.  
14  
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TPS736xx  
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SBVS038T –SEPTEMBER 2003–REVISED AUGUST 2010  
POWER DISSIPATION  
space  
PD + (VIN * VOUT)   IOUT  
(6)  
The ability to remove heat from the die is different for  
each  
package  
type,  
presenting  
different  
Power dissipation can be minimized by using the  
lowest possible input voltage necessary to assure the  
required output voltage.  
considerations in the PCB layout. The PCB area  
around the device that is free of other components  
moves the heat from the device to the ambient air.  
Performance data for JEDEC low- and high-K boards  
are shown in the Thermal Information table. Using  
heavier copper will increase the effectiveness in  
removing heat from the device. The addition of plated  
through-holes to heat-dissipating layers will also  
improve the heat-sink effectiveness.  
PACKAGE MOUNTING  
Solder pad footprint recommendations for the  
TPS736xx are presented in Application Bulletin  
Solder Pad Recommendations for Surface-Mount  
Devices (SBFA015), available from the Texas  
Instruments web site at www.ti.com.  
Power dissipation depends on input voltage and load  
conditions. Power dissipation (PD) is equal to the  
product of the output current times the voltage drop  
across the output pass element (VIN to VOUT):  
space  
REVISION HISTORY  
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.  
Changes from Revision S (August, 2009) to Revision T  
Page  
•
Replaced Dissipation Ratings Table with Thermal Information Table .................................................................................. 3  
Changes from Revision R (May, 2008) to Revision S  
Page  
•
•
•
Changed Figure 12 ............................................................................................................................................................... 8  
Added paragraph about recommended start-up sequence to Internal Current Limit section ............................................. 13  
Added paragraph about current foldback and device start-up to Enable Pin and Shutdown section ................................ 13  
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15  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Aug-2013  
PACKAGING INFORMATION  
Orderable Device  
TPS73601DBVR  
TPS73601DBVRG4  
TPS73601DBVT  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
ACTIVE  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-223  
SOT-223  
SOT-223  
SOT-223  
SON  
DBV  
5
5
5
5
6
6
6
6
8
8
8
8
8
8
8
8
5
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
PJFQ  
PJFQ  
PJFQ  
PJFQ  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DBV  
DBV  
DBV  
DCQ  
DCQ  
DCQ  
DCQ  
DRB  
DRB  
DRB  
DRB  
DRB  
DRB  
DRB  
DRB  
DBV  
3000  
250  
250  
78  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
TPS73601DBVTG4  
TPS73601DCQ  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
PS73601  
PS73601  
PS73601  
PS73601  
PJFQ  
PJFQ  
PJFQ  
PJFQ  
T49  
TPS73601DCQG4  
TPS73601DCQR  
TPS73601DCQRG4  
TPS73601DRBR  
TPS73601DRBRG4  
TPS73601DRBT  
78  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU SN  
2500  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
SON  
Green (RoHS  
& no Sb/Br)  
SON  
Green (RoHS  
& no Sb/Br)  
TPS73601DRBTG4  
TPS736125DRBR  
TPS736125DRBRG4  
TPS736125DRBT  
TPS736125DRBTG4  
TPS73615DBVR  
SON  
250  
Green (RoHS  
& no Sb/Br)  
SON  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
SON  
Green (RoHS  
& no Sb/Br)  
T49  
SON  
Green (RoHS  
& no Sb/Br)  
T49  
SON  
250  
Green (RoHS  
& no Sb/Br)  
T49  
SOT-23  
3000  
Green (RoHS  
& no Sb/Br)  
T44  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Aug-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
TPS73615DBVRG4  
TPS73615DBVT  
TPS73615DBVTG4  
TPS73615DCQ  
ACTIVE  
SOT-23  
SOT-23  
SOT-23  
SOT-223  
DBV  
5
5
5
6
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
T44  
T44  
T44  
ACTIVE  
ACTIVE  
ACTIVE  
DBV  
DBV  
DCQ  
250  
250  
78  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
PS73615  
TPS73615DCQG4  
TPS73615DCQR  
ACTIVE  
ACTIVE  
SOT-223  
SOT-223  
DCQ  
DCQ  
6
6
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
2500  
2500  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Level-2-260C-1 YEAR  
PS73615  
PS73615  
T44  
TPS73615DCQRG4  
TPS73615DRBR  
TPS73615DRBRG4  
TPS73615DRBT  
TPS73615DRBTG4  
TPS73616DBVR  
TPS73616DBVT  
TPS73618DBVR  
TPS73618DBVRG4  
TPS73618DBVT  
TPS73618DBVTG4  
TPS73618DCQ  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SOT-223  
SON  
DCQ  
DRB  
DRB  
DRB  
DRB  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
DCQ  
6
8
8
8
8
5
5
5
5
5
5
6
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 125  
-40 to 125  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Green (RoHS  
& no Sb/Br)  
SON  
Green (RoHS  
& no Sb/Br)  
T44  
SON  
Green (RoHS  
& no Sb/Br)  
T44  
SON  
250  
Green (RoHS  
& no Sb/Br)  
T44  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-223  
3000  
250  
Green (RoHS  
& no Sb/Br)  
OCQ  
OCQ  
T43  
Green (RoHS  
& no Sb/Br)  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
T43  
Green (RoHS  
& no Sb/Br)  
T43  
250  
Green (RoHS  
& no Sb/Br)  
T43  
78  
Green (RoHS  
& no Sb/Br)  
PS73618  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Aug-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
TPS73618DCQG4  
TPS73618DCQR  
ACTIVE  
SOT-223  
SOT-223  
DCQ  
6
6
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DCQ  
DCQ  
DRB  
DRB  
DRB  
DRB  
DBV  
DBV  
DBV  
DBV  
DCQ  
2500  
2500  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Level-2-260C-1 YEAR  
PS73618  
TPS73618DCQRG4  
TPS73619DRBR  
TPS73619DRBRG4  
TPS73619DRBT  
TPS73619DRBTG4  
TPS73625DBVR  
TPS73625DBVRG4  
TPS73625DBVT  
TPS73625DBVTG4  
TPS73625DCQ  
SOT-223  
SON  
6
8
8
8
8
5
5
5
5
6
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
-40 to 85  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 125  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
PS73618  
BYY  
Green (RoHS  
& no Sb/Br)  
SON  
Green (RoHS  
& no Sb/Br)  
BYY  
SON  
Green (RoHS  
& no Sb/Br)  
BYY  
SON  
250  
Green (RoHS  
& no Sb/Br)  
BYY  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-223  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
T42  
Green (RoHS  
& no Sb/Br)  
T42  
Green (RoHS  
& no Sb/Br)  
T42  
250  
Green (RoHS  
& no Sb/Br)  
T42  
78  
Green (RoHS  
& no Sb/Br)  
PS73625  
TPS73625DCQG4  
TPS73625DCQR  
ACTIVE  
ACTIVE  
SOT-223  
SOT-223  
DCQ  
DCQ  
6
6
TBD  
Call TI  
CU SN  
Call TI  
-40 to 85  
-40 to 85  
2500  
Green (RoHS  
& no Sb/Br)  
Level-2-260C-1 YEAR  
PS73625  
TPS73625DCQRG4  
TPS73630DBVR  
ACTIVE  
ACTIVE  
SOT-223  
SOT-23  
DCQ  
DBV  
6
5
TBD  
Call TI  
Call TI  
-40 to 85  
-40 to 85  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-1-260C-UNLIM  
T45  
T45  
T45  
TPS73630DBVRG4  
TPS73630DBVT  
ACTIVE  
ACTIVE  
SOT-23  
SOT-23  
DBV  
DBV  
5
5
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
-40 to 85  
-40 to 85  
Green (RoHS  
& no Sb/Br)  
Addendum-Page 3  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Aug-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
TPS73630DBVTG4  
TPS73630DCQ  
ACTIVE  
SOT-23  
SOT-223  
SOT-223  
SOT-223  
SOT-223  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-223  
SOT-223  
SOT-223  
SOT-223  
SON  
DBV  
5
6
6
6
6
5
5
5
5
5
5
5
5
6
6
6
6
8
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
T45  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DCQ  
DCQ  
DCQ  
DCQ  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
DBV  
DCQ  
DCQ  
DCQ  
DCQ  
DRB  
78  
Green (RoHS  
& no Sb/Br)  
PS73630  
PS73630  
PS73630  
PS73630  
T53  
TPS73630DCQG4  
TPS73630DCQR  
TPS73630DCQRG4  
TPS73632DBVR  
TPS73632DBVRG4  
TPS73632DBVT  
TPS73632DBVTG4  
TPS73633DBVR  
TPS73633DBVRG4  
TPS73633DBVT  
TPS73633DBVTG4  
TPS73633DCQ  
78  
Green (RoHS  
& no Sb/Br)  
2500  
2500  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
T53  
Green (RoHS  
& no Sb/Br)  
T53  
250  
Green (RoHS  
& no Sb/Br)  
T53  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
T46  
Green (RoHS  
& no Sb/Br)  
T46  
Green (RoHS  
& no Sb/Br)  
T46  
250  
Green (RoHS  
& no Sb/Br)  
T46  
78  
Green (RoHS  
& no Sb/Br)  
PS73633  
PS73633  
PS73633  
PS73633  
T46  
TPS73633DCQG4  
TPS73633DCQR  
TPS73633DCQRG4  
TPS73633DRBR  
78  
Green (RoHS  
& no Sb/Br)  
2500  
2500  
3000  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Addendum-Page 4  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Aug-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
TPS73633DRBRG4  
TPS73633DRBT  
ACTIVE  
SON  
SON  
DRB  
8
8
8
5
5
5
5
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
T46  
T46  
T46  
T54  
T54  
T54  
T54  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DRB  
DRB  
DBV  
DBV  
DBV  
DBV  
250  
250  
Green (RoHS  
& no Sb/Br)  
TPS73633DRBTG4  
TPS73643DBVR  
TPS73643DBVRG4  
TPS73643DBVT  
SON  
Green (RoHS  
& no Sb/Br)  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
3000  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
TPS73643DBVTG4  
250  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Addendum-Page 5  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Aug-2013  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF TPS73601, TPS73615, TPS73618, TPS73625, TPS73630, TPS73632, TPS73633 :  
Automotive: TPS73601-Q1, TPS73618-Q1  
•
Enhanced Product: TPS73601-EP, TPS73615-EP, TPS73618-EP, TPS73625-EP, TPS73630-EP, TPS73632-EP, TPS73633-EP  
•
NOTE: Qualified Version Definitions:  
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications  
•
Addendum-Page 6  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
30-Dec-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS73601DBVR  
TPS73601DBVT  
TPS73601DCQRG4  
TPS73601DRBR  
TPS73601DRBR  
TPS73601DRBT  
TPS73601DRBT  
TPS736125DRBR  
TPS736125DRBT  
TPS73615DBVR  
TPS73615DBVT  
TPS73615DCQRG4  
TPS73615DRBR  
TPS73615DRBT  
TPS73616DBVR  
TPS73616DBVT  
TPS73618DBVR  
TPS73618DBVT  
SOT-23  
SOT-23  
DBV  
DBV  
5
5
6
8
8
8
8
8
8
5
5
6
8
8
5
5
5
5
3000  
250  
178.0  
178.0  
330.0  
330.0  
330.0  
180.0  
180.0  
330.0  
180.0  
178.0  
178.0  
330.0  
330.0  
180.0  
179.0  
179.0  
178.0  
178.0  
9.0  
9.0  
3.23  
3.3  
3.17  
3.2  
1.37  
1.4  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
4.0  
4.0  
8.0  
8.0  
8.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
Q3  
Q3  
Q3  
Q2  
Q2  
Q2  
Q2  
Q2  
Q2  
Q3  
Q3  
Q3  
Q2  
Q2  
Q3  
Q3  
Q3  
Q3  
SOT-223 DCQ  
0
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
12.4  
9.0  
7.1  
7.45  
3.3  
1.88  
1.1  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
12.0  
8.0  
SON  
SON  
DRB  
DRB  
DRB  
DRB  
DRB  
DRB  
DBV  
DBV  
3000  
3000  
250  
3.3  
3.3  
3.3  
1.0  
SON  
3.3  
3.3  
1.1  
SON  
250  
3.3  
3.3  
1.0  
SON  
3000  
250  
3.3  
3.3  
1.1  
SON  
3.3  
3.3  
1.1  
SOT-23  
SOT-23  
3000  
250  
3.3  
3.2  
1.4  
9.0  
3.23  
7.05  
3.3  
3.17  
7.45  
3.3  
1.37  
1.88  
1.1  
8.0  
SOT-223 DCQ  
2500  
3000  
250  
12.4  
12.4  
12.4  
8.4  
12.0  
12.0  
12.0  
8.0  
SON  
DRB  
DRB  
DBV  
DBV  
DBV  
DBV  
SON  
3.3  
3.3  
1.1  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
3000  
250  
3.2  
3.2  
1.4  
8.4  
3.2  
3.2  
1.4  
8.0  
3000  
250  
9.0  
3.23  
3.23  
3.17  
3.17  
1.37  
1.37  
8.0  
9.0  
8.0  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
30-Dec-2013  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS73618DCQRG4  
TPS73619DRBR  
TPS73619DRBT  
TPS73625DBVR  
TPS73625DBVT  
TPS73630DBVR  
TPS73630DBVT  
TPS73630DCQR  
TPS73632DBVR  
TPS73632DBVT  
TPS73633DBVR  
TPS73633DBVT  
TPS73633DCQR  
TPS73633DRBR  
TPS73633DRBT  
TPS73643DBVR  
TPS73643DBVT  
SOT-223 DCQ  
6
8
8
5
5
5
5
6
5
5
5
5
6
8
8
5
5
2500  
3000  
250  
330.0  
330.0  
180.0  
178.0  
178.0  
178.0  
178.0  
330.0  
178.0  
178.0  
178.0  
178.0  
330.0  
330.0  
180.0  
179.0  
179.0  
12.4  
12.4  
12.4  
9.0  
7.05  
3.3  
7.45  
3.3  
1.88  
1.0  
8.0  
8.0  
8.0  
4.0  
4.0  
4.0  
4.0  
8.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
4.0  
4.0  
12.0  
12.0  
12.0  
8.0  
Q3  
Q2  
Q2  
Q3  
Q3  
Q3  
Q3  
Q3  
Q3  
Q3  
Q3  
Q3  
Q3  
Q2  
Q2  
Q3  
Q3  
SON  
DRB  
DRB  
DBV  
DBV  
DBV  
DBV  
SON  
3.3  
3.3  
1.0  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
3000  
250  
3.23  
3.23  
3.23  
3.23  
6.8  
3.17  
3.17  
3.17  
3.17  
7.3  
1.37  
1.37  
1.37  
1.37  
1.88  
1.37  
1.4  
9.0  
8.0  
3000  
250  
9.0  
8.0  
9.0  
8.0  
SOT-223 DCQ  
2500  
3000  
250  
12.4  
9.0  
12.0  
8.0  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
DBV  
DBV  
DBV  
DBV  
3.23  
3.3  
3.17  
3.2  
9.0  
8.0  
3000  
250  
9.0  
3.23  
3.23  
6.8  
3.17  
3.17  
7.3  
1.37  
1.37  
1.88  
1.1  
8.0  
9.0  
8.0  
SOT-223 DCQ  
2500  
3000  
250  
12.4  
12.4  
12.4  
8.4  
12.0  
12.0  
12.0  
8.0  
SON  
SON  
DRB  
DRB  
DBV  
DBV  
3.3  
3.3  
3.3  
3.3  
1.1  
SOT-23  
SOT-23  
3000  
250  
3.2  
3.2  
1.4  
8.4  
3.2  
3.2  
1.4  
8.0  
*All dimensions are nominal  
Pack Materials-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
30-Dec-2013  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS73601DBVR  
TPS73601DBVT  
TPS73601DCQRG4  
TPS73601DRBR  
TPS73601DRBR  
TPS73601DRBT  
TPS73601DRBT  
TPS736125DRBR  
TPS736125DRBT  
TPS73615DBVR  
TPS73615DBVT  
TPS73615DCQRG4  
TPS73615DRBR  
TPS73615DRBT  
TPS73616DBVR  
TPS73616DBVT  
TPS73618DBVR  
TPS73618DBVT  
TPS73618DCQRG4  
TPS73619DRBR  
TPS73619DRBT  
TPS73625DBVR  
TPS73625DBVT  
TPS73630DBVR  
TPS73630DBVT  
TPS73630DCQR  
TPS73632DBVR  
TPS73632DBVT  
TPS73633DBVR  
TPS73633DBVT  
TPS73633DCQR  
TPS73633DRBR  
TPS73633DRBT  
TPS73643DBVR  
TPS73643DBVT  
SOT-23  
SOT-23  
SOT-223  
SON  
DBV  
DBV  
DCQ  
DRB  
DRB  
DRB  
DRB  
DRB  
DRB  
DBV  
DBV  
DCQ  
DRB  
DRB  
DBV  
DBV  
DBV  
DBV  
DCQ  
DRB  
DRB  
DBV  
DBV  
DBV  
DBV  
DCQ  
DBV  
DBV  
DBV  
DBV  
DCQ  
DRB  
DRB  
DBV  
DBV  
5
5
6
8
8
8
8
8
8
5
5
6
8
8
5
5
5
5
6
8
8
5
5
5
5
6
5
5
5
5
6
8
8
5
5
3000  
250  
180.0  
180.0  
358.0  
367.0  
370.0  
210.0  
220.0  
367.0  
210.0  
180.0  
180.0  
358.0  
367.0  
210.0  
203.0  
203.0  
180.0  
180.0  
358.0  
370.0  
220.0  
180.0  
180.0  
180.0  
180.0  
358.0  
180.0  
180.0  
180.0  
180.0  
358.0  
367.0  
210.0  
203.0  
203.0  
180.0  
180.0  
335.0  
367.0  
355.0  
185.0  
205.0  
367.0  
185.0  
180.0  
180.0  
335.0  
367.0  
185.0  
203.0  
203.0  
180.0  
180.0  
335.0  
355.0  
205.0  
180.0  
180.0  
180.0  
180.0  
335.0  
180.0  
180.0  
180.0  
180.0  
335.0  
367.0  
185.0  
203.0  
203.0  
18.0  
18.0  
35.0  
35.0  
55.0  
35.0  
50.0  
35.0  
35.0  
18.0  
18.0  
35.0  
35.0  
35.0  
35.0  
35.0  
18.0  
18.0  
35.0  
55.0  
50.0  
18.0  
18.0  
18.0  
18.0  
35.0  
18.0  
18.0  
18.0  
18.0  
35.0  
35.0  
35.0  
35.0  
35.0  
0
3000  
3000  
250  
SON  
SON  
SON  
250  
SON  
3000  
250  
SON  
SOT-23  
SOT-23  
SOT-223  
SON  
3000  
250  
2500  
3000  
250  
SON  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-223  
SON  
3000  
250  
3000  
250  
2500  
3000  
250  
SON  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-223  
SOT-23  
SOT-23  
SOT-23  
SOT-23  
SOT-223  
SON  
3000  
250  
3000  
250  
2500  
3000  
250  
3000  
250  
2500  
3000  
250  
SON  
SOT-23  
SOT-23  
3000  
250  
Pack Materials-Page 3  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
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published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
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Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
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TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of  
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Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
Medical  
Logic  
Security  
www.ti.com/security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense  
Video and Imaging  
www.ti.com/space-avionics-defense  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/omap  
OMAP Applications Processors  
Wireless Connectivity  
TI E2E Community  
e2e.ti.com  
www.ti.com/wirelessconnectivity  
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Copyright © 2013, Texas Instruments Incorporated  

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