TPS73718DRBT [TI]
1A Low-Dropout Regulator with Reverse Current Protection; 1A低压降稳压器具有反向电流保护型号: | TPS73718DRBT |
厂家: | TEXAS INSTRUMENTS |
描述: | 1A Low-Dropout Regulator with Reverse Current Protection |
文件: | 总31页 (文件大小:1298K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TPS737xx
www.ti.com
SBVS067O –JANUARY 2006–REVISED JUNE 2012
1A Low-Dropout Regulator
with Reverse Current Protection
1
FEATURES
DESCRIPTION
The TPS737xx family of linear low-dropout (LDO)
voltage regulators uses an NMOS pass element in a
voltage-follower configuration. This topology is
relatively insensitive to output capacitor value and
ESR, allowing a wide variety of load configurations.
Load transient response is excellent, even with a
small 1.0μF ceramic output capacitor. The NMOS
topology also allows very low dropout.
2
•
Stable with 1.0μF or Larger Ceramic Output
Capacitor
•
•
•
Input Voltage Range: 2.2V to 5.5V
Ultra-Low Dropout Voltage: 130mV typ at 1A
Excellent Load Transient Response—Even
With Only 1.0μF Output Capacitor
•
NMOS Topology Delivers Low Reverse
Leakage Current
The TPS737xx family uses an advanced BiCMOS
process to yield high precision while delivering very
low dropout voltages and low ground pin current.
Current consumption, when not enabled, is under
20nA and ideal for portable applications. These
devices are protected by thermal shutdown and
foldback current limit.
•
•
1.0% Initial Accuracy
3% Overall Accuracy Over Line, Load, and
Temperature
•
•
Less Than 20nA typical IQ in Shutdown Mode
Thermal Shutdown and Current Limit for Fault
Protection
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
•
Available in Multiple Output Voltage Versions
–
–
Adjustable Output: 1.20V to 5.5V
OUT
N/C
1
2
3
4
8
7
6
5
IN
Custom Outputs Available Using Factory
Package-Level Programming
N/C
N/C
EN
NR/FB
GND
APPLICATIONS
•
Point of Load Regulation for DSPs, FPGAs,
ASICs, and Microprocessors
DCQ PACKAGE
SOT223
•
•
Post-Regulation for Switching Supplies
Portable/Battery-Powered Equipment
(TOP VIEW)
DRV PACKAGE(1)
2mm x 2mm SON
(TOP VIEW)
6
3
TAB IS GND
Optional
OUT
NR/FB
GND
1
2
3
6
5
4
IN
VIN
VOUT
1.0mF
IN
OUT
FB
N/C
EN
1
2
4
5
TPS737xx
EN
GND
IN
ON
GND
EN
OFF
OUT NR/FB
(1) Power dissipation may limit operating
range. Check Thermal Information table.
Typical Application Circuit
space
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
TPS737xx
SBVS067O –JANUARY 2006–REVISED JUNE 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS737xx yy yz
XX is nominal output voltage (for example, 25 = 2.5V, 01 = Adjustable(3)).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Most output voltages of 1.25V and 1.3V to 5.0V in 100mV increments are available on a quick-turn basis using innovative factory
package-level programming. Minimum order quantities apply; contact factory for details and availability.
(3) For fixed 1.20V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range unless otherwise noted.
PARAMETER
TPS737xx
–0.3 to +6.0
–0.3 to +6.0
–0.3 to +5.5
–0.3 to +6.0
Internally limited
Indefinite
UNIT
VIN range
V
V
V
V
VEN range
VOUT range
VNR, VFB range
Peak output current
Output short-circuit duration
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range
ESD rating, HBM
See Thermal Information table
–55 to +150
°C
°C
kV
V
–65 to +150
2
ESD rating, CDM
500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics
is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
2
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TPS737xx
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SBVS067O –JANUARY 2006–REVISED JUNE 2012
THERMAL INFORMATION
TPS737xx(2)
THERMAL METRIC(1)
DRB
8 PINS
49.5
58.9
25.1
1.7
DCQ
6 PINS
53.1
35.2
7.8
DRV(3)
6 PINS
67.2
87.6
36.8
1.8
UNITS
θJA
Junction-to-ambient thermal resistance(4)
Junction-to-case (top) thermal resistance(5)
Junction-to-board thermal resistance(6)
Junction-to-top characterization parameter(7)
Junction-to-board characterization parameter(8)
Junction-to-case (bottom) thermal resistance(9)
θJCtop
θJB
°C/W
ψJT
2.9
ψJB
25.2
8.6
7.7
37.2
7.7
θJCbot
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through
ii. DCQ: The exposed pad is connected to the PCB ground layer through
a
2x2 thermal via array.
.
a 3x2 thermal via array.
. iii. DRV: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array. Due to size limitation of thermal
pad, 0.8-mm pitch array is used which is off the JEDEC standard.
(b) The top copper layer has a detailed copper trace pattern. The bottom copper layer is assumed to have a 20% thermal conductivity of
copper, representing a 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(3) Power dissipation may limit operating range.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 1.0V(1), IOUT = 10mA, VEN = 2.2V, and
COUT = 2.2μF, unless otherwise noted. Typical values are at TJ = +25°C.
TPS737xx
PARAMETER
Input voltage range(1)(2)
TEST CONDITIONS
MIN
TYP
MAX
5.5
UNIT
VIN
2.2
V
Internal reference
(DCQ package)
TJ = +25°C
1.198
1.192
1.2
1.2
1.210
1.216
VFB
V
V
Internal reference
(DRB and DRV packages)
TJ = +25°C
Output voltage range
(TPS73701)(3)
VFB
5.5 – VDO
+1.0
Nominal
TJ = +25°C
–1.0
5.36V < VIN < 5.5V, VOUT = 5.08V,
10mA < IOUT < 800mA,
–40C < TJ < +85°C, TPS73701DCQ
VOUT
Accuracy(1) ,
–2.0
–3.0
+2.0
+3.0
%
(4)
over VIN, IOUT
and T
,
VOUT + 0.5V ≤ VIN ≤ 5.5V;
10mA ≤ IOUT ≤ 1A
±0.5
ΔVOUT%/ΔVIN
ΔVOUT%/ΔIOUT
Line regulation(1)
VOUT(nom) + 0.5V ≤ VIN ≤ 5.5V
1mA ≤ IOUT ≤ 1A
0.01
0.002
%/V
Load regulation
%/mA
10mA ≤ IOUT ≤ 1A
0.0005
Dropout voltage(5)
(VIN = VOUT(nom) – 0.1V)
VDO
IOUT = 1A
130
500
2.2
mV
ZO(DO)
ICL
Output impedance in dropout
Output current limit
2.2V ≤ VIN ≤ VOUT + VDO
VOUT = 0.9 × VOUT(nom)
VOUT = 0V
0.25
1.6
450
0.1
400
1300
20
Ω
A
1.05
ISC
Short-circuit current
Reverse leakage current(6) (–IIN
mA
μA
IREV
)
VEN ≤ 0.5V, 0V ≤ VIN ≤ VOUT
IOUT = 10mA (IQ)
IOUT = 1A
IGND
GND pin current
μA
ISHDN
IFB
Shutdown current (IGND
)
VEN ≤ 0.5V, VOUT ≤ VIN ≤ 5.5
nA
FB pin current (TPS73701)
0.1
58
0.6
μA
f = 100Hz, IOUT = 1A
f = 10kHz, IOUT = 1A
Power-supply rejection ratio
(ripple rejection)
PSRR
VN
dB
37
Output noise voltage
BW = 10Hz to 100kHz
COUT = 10μF
27 × VOUT
600
μVRMS
tSTR
Startup time
VOUT = 3V, RL = 30Ω, COUT = 1μF
μs
V
VEN(HI)
VEN(LO)
IEN(HI)
EN pin high (enabled)
EN pin low (shutdown)
EN pin current (enabled)
1.7
0
VIN
0.5
V
VEN = 5.5V
20
+160
+140
nA
Shutdown, temperature increasing
Reset, temperature decreasing
TSD
TJ
Thermal shutdown temperature
Operating junction temperature
°C
°C
–40
+125
(1) Minimum VIN = VOUT + VDO or 2.2V, whichever is greater.
(2) For VOUT(nom) < 1.6V, when VIN ≤ 1.6V, the output will lock to VIN and may result in an over-voltage condition on the output. To avoid this
situation, disable the device before powering down VIN
.
(3) TPS73701 is tested at VOUT = 1.2V.
(4) Tolerance of external resistors not included in this specification.
(5) VDO is not measured for fixed output versions with VOUT(nom) < 2.3V since minimum VIN = 2.2V.
(6) Fixed-voltage versions only; refer to the Applications section for more information.
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SBVS067O –JANUARY 2006–REVISED JUNE 2012
FUNCTIONAL BLOCK DIAGRAMS
IN
4MHz
Charge Pump
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
Current
Limit
OUT
Ω
8k
GND
R1
Ω
R1 + R2 = 80k
R2
NR
Figure 1. Fixed Voltage Version
IN
Table 1. Standard 1%
Resistor Values for
Common Output Voltages
V
O
R
1
R
2
4MHz
1.2V
1.5V
1.8V
2.5V
2.8V
3.0V
3.3V
Short
Open
Charge Pump
23.2kΩ
28.0kΩ
39.2kΩ
44.2kΩ
46.4kΩ
52.3kΩ
95.3kΩ
56.2kΩ
36.5kΩ
33.2kΩ
30.9kΩ
30.1kΩ
EN
Thermal
Protection
Ref
Servo
Ω
27k
Bandgap
Error
Amp
NOTE: V
= (R + R )/R × 1.204;
1 2 2
OUT
OUT
FB
Current
Limit
R
R
19kΩ for best
1
2
accuracy.
GND
Ω
80k
Ω
8k
R1
R2
Figure 2. Adjustable Voltage Version
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PIN CONFIGURATIONS
DCQ PACKAGE
SOT223-6
(TOP VIEW)
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
6
3
TAB IS GND
OUT
N/C
1
2
3
4
8
7
6
5
IN
N/C
N/C
EN
NR/FB
GND
1
2
4
5
IN
GND
EN
OUT NR/FB
DRV PACKAGE(1)
2mm x 2mm SON
(TOP VIEW)
OUT
NR/FB
GND
1
2
3
6
5
4
IN
N/C
EN
(1) Power dissipation may limit operating range. Check Thermal Information table.
Table 1. Pin Descriptions
SOT223
(DCQ)
3×3 SON
(DRB)
2×2 SON
(DRV)
PIN
NAME
PIN NO.
PIN NO.
PIN NO.
DESCRIPTION
IN
1
8
6
Unregulated input supply
Ground
GND
3, 6
4, Pad
3, Pad
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts
the regulator into shutdown mode. Refer to the Shutdown section under
Applications Information for more details. EN must not be left floating and can
be connected to IN if not used.
EN
5
5
4
Fixed voltage versions only—connecting an external capacitor to this pin
bypasses noise generated by the internal bandgap, reducing output noise to
very low levels.
NR
FB
4
4
3
3
2
2
Adjustable voltage version only—this is the input to the control loop error
amplifier, and is used to set the output voltage of the device.
OUT
NC
2
1
1
5
Regulator output. A 1.0μF or larger capacitor of any type is required for stability.
—
2, 6, 7
Not connected
6
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TYPICAL CHARACTERISTICS
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2μF, unless otherwise
noted.
LOAD REGULATION
LINE REGULATION
0.5
0.4
0.20
0.15
0.10
0.05
0
Referred to IOUT = 10mA
Referred to VIN = VOUT + 1.0V at IOUT = 10mA
-40°C
+25°C
+125°C
0.3
0.2
+25°C
+125°C
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.05
-0.10
-0.15
-0.20
-40°C
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
0
0.5
1.0
1.5
2.0
2.5
3.0 3.5
4.0
4.5
V
IN - VOUT (V)
Figure 3.
Figure 4.
DROPOUT VOLTAGE vs OUTPUT CURRENT
DROPOUT VOLTAGE vs TEMPERATURE
200
180
160
140
120
100
80
200
180
160
140
120
100
80
VOUT = 2.5V
+125°C
+25°C
60
60
-40°C
40
40
20
20
0
0
0
100 200 300 400 500 600 700 800 900 1000
IOUT (mA)
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
Figure 5.
Figure 6.
OUTPUT VOLTAGE HISTOGRAM
OUTPUT VOLTAGE DRIFT HISTOGRAM
30
25
20
15
10
5
18
16
14
12
10
8
IOUT = 10mA
IOUT = 10mA
6
4
2
0
0
VOUT Error (%)
Worst Case dVOUT/dT (ppm/°C)
Figure 7.
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2μF, unless otherwise
noted.
GROUND PIN CURRENT vs OUTPUT CURRENT
GROUND PIN CURRENT vs TEMPERATURE
3000
2500
2000
1500
1000
500
2500
2000
1500
1000
500
IOUT = 1A
VIN = 5.0V
VIN = 5.0V
VIN = 3.3V
VIN = 3.3V
VIN = 2.2V
VIN = 2.2V
0
0
-50
-25
0
25
50
75
100
125
0
200
400
600
800
1000
Temperature (°C)
IOUT (mA)
Figure 9.
Figure 10.
GROUND PIN CURRENT IN SHUTDOWN
vs TEMPERATURE
CURRENT LIMIT vs VOUT (FOLDBACK)
1
2.00
1.80
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20
0
VENABLE = 0.5V
VIN = VOUT + 0.5V
ICL
0.1
ISC
VOUT = 3.3V
0.01
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
-50
-25
0
25
50
75
100
125
Output Voltage (V)
Temperature (°C)
Figure 11.
Figure 12.
CURRENT LIMIT vs VIN
CURRENT LIMIT vs TEMPERATURE
2.0
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
VOUT = 1.2V
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
-25
0
25
50
75
100
125
VIN (V)
Temperature (°C)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2μF, unless otherwise
noted.
PSRR (RIPPLE REJECTION) vs FREQUENCY
PSRR (RIPPLE REJECTION) vs VIN – VOUT
90
80
70
60
50
40
30
20
10
0
40
35
30
25
20
15
10
5
IOUT = 100mA
COUT = Any
IOUT = 1mA
COUT = 1mF
IOUT = 1mA
COUT = 10mF
IO = 100mA
CO = 1mF
IOUT = 1mA
COUT = Any
Frequency = 10kHz
COUT = 10mF
IOUT = 100mA
COUT = 10mF
VOUT = 2.5V
IOUT = 100mA
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10
100
1k
10k
100k
1M
10M
VIN - VOUT (V)
Frequency (Hz)
Figure 15.
Figure 16.
TPS73701
NOISE SPECTRAL DENSITY
RMS NOISE VOLTAGE vs CFB
1
60
55
50
45
40
35
30
25
20
COUT = 1mF
0.1
COUT = 10mF
VOUT = 2.5V
COUT = 0mF
R1 = 39.2kW
IOUT = 150mA
10Hz < Frequency < 100kHz
0.01
10
100
1k
10k
100k
10p
100p
1n
10n
CFB (F)
Frequency (Hz)
Figure 17.
Figure 18.
RMS NOISE VOLTAGE vs CNR
RMS NOISE VOLTAGE vs COUT
60
50
40
30
20
10
0
140
120
100
80
VOUT = 5.0V
VOUT = 5.0V
VOUT = 3.3V
VOUT = 3.3V
VOUT = 1.5V
60
40
VOUT = 1.5V
20
CNR = 0.01mF
COUT = 0mF
10Hz < Frequency < 100kHz
10Hz < Frequency < 100kHz
0
0.1
1
10
1p
10p
100p
1n
10n
COUT (mF)
CNR (F)
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2μF, unless otherwise
noted.
TPS73733
TPS73733
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
CNR = 10nF
CNR = 10nF
COUT = 10mF
VOUT
200mV/div
COUT = 10mF
100mV/div
VOUT
1A
5.3V
10mA
4.3V
IOUT
VIN
10ms/div
10ms/div
Figure 21.
Figure 22.
TPS73701
TPS73701
TURN-ON RESPONSE
TURN-OFF RESPONSE
RL = 20W
COUT = 10mF
VOUT
RL = 20W
RL = 20W
COUT = 1mF
1V/div
1V/div
COUT = 1mF
RL = 20W
COUT = 10mF
VOUT
2V
2V
VEN
1V/div
1V/div
0V
0V
VEN
100ms/div
100ms/div
Figure 23.
Figure 24.
TPS73701, VOUT = 3.3V
POWER-UP/POWER-DOWN
IENABLE vs TEMPERATURE
6
5
10
1
VIN
4
VOUT
3
2
1
0.1
0.01
0
-1
-2
50ms/div
-50
-25
0
25
50
75
100
125
Temperature (°C)
Figure 25.
Figure 26.
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TYPICAL CHARACTERISTICS (continued)
For all voltage versions at TJ = +25°C, VIN = VOUT(nom) + 1.0V, IOUT = 10mA, VEN = 2.2V, and COUT = 2.2μF, unless otherwise
noted.
TPS73701
TPS73701
RMS NOISE VOLTAGE vs CFB
IFB vs TEMPERATURE
160
140
120
100
80
60
55
50
45
40
35
30
25
20
60
VOUT = 2.5V
40
COUT = 0mF
R1 = 39.2kW
20
10Hz < Frequency < 100kHz
0
-50
-25
0
25
50
75
100
125
10p
100p
1n
10n
Temperature (°C)
CFB (F)
Figure 27.
Figure 28.
TPS73701
TPS73701
LOAD TRANSIENT, ADJUSTABLE VERSION
LINE TRANSIENT, ADJUSTABLE VERSION
VOUT = 2.5V
CFB = 10nF
CFB = 10nF
R1 = 39.2kW
COUT = 10mF
COUT = 10mF
VOUT
VOUT
100mV/div
100mV/div
4.5V
250mA
3.5V
IOUT
VIN
10mA
10ms/div
5ms/div
Figure 29.
Figure 30.
Copyright © 2006–2012, Texas Instruments Incorporated
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11
TPS737xx
SBVS067O –JANUARY 2006–REVISED JUNE 2012
www.ti.com
APPLICATION INFORMATION
The TPS737xx belongs to a family of new generation
LDO regulators that use an NMOS pass transistor to
achieve ultra-low-dropout performance, reverse
current blockage, and freedom from output capacitor
constraints. These features combined with an enable
input make the TPS737xx ideal for portable
applications. This regulator family offers a wide
selection of fixed output voltage versions and an
adjustable output version. All versions have thermal
and over-current protection, including foldback
current limit.
For best accuracy, make the parallel combination of
R1 and R2 approximately equal to 19kΩ. This 19kΩ,
in addition to the internal 8kΩ resistor, presents the
same impedance to the error amp as the 27kΩ
bandgap reference output. This impedance helps
compensate for leakages into the error amp
terminals.
INPUT AND OUTPUT CAPACITOR
REQUIREMENTS
Although an input capacitor is not required for stability
if input impedance is very low, it is good analog
design practice to connect a 0.1μF to 1μF low
equivalent series resistance (ESR) capacitor across
the input supply near the regulator. This capacitor
counteracts reactive input sources and improves
transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary
if large, fast rise-time load transients are anticipated
or the device is located several inches from the
power source.
Figure 31 shows the basic circuit connections for the
fixed voltage models. Figure 32 gives the connections
for the adjustable output version (TPS73701).
VIN
VOUT
IN
OUT
TPS737xx
EN
GND
ON
OFF
The TPS737xx requires a 1.0µF output capacitor for
stability. It is designed to be stable for all available
types and values of capacitors. In applications where
multiple low ESR capacitors are in parallel, ringing
may occur when the product of COUT and total ESR
drops below 50nΩF. Total ESR includes all parasitic
resistances, including capacitor ESR and board,
socket, and solder joint resistance. In most
applications, the sum of capacitor ESR and trace
resistance will meet this requirement.
Figure 31. Typical Application Circuit for Fixed-
Voltage Versions
Optional input capacitor.
May improve source
Output capacitor
impedance, noise, or PSRR.
must be ³ 1.0mF.
VIN
VOUT
IN
OUT
TPS73701
R1
R2
CFB
EN
GND
FB
OUTPUT NOISE
ON
OFF
A precision bandgap reference is used to generate
the internal reference voltage, VREF. This reference is
the dominant noise source within the TPS737xx and
it generates approximately 32μVRMS (10Hz to
100kHz) at the reference output (NR). The regulator
control loop gains up the reference noise with the
same gain as the reference voltage, so that the noise
voltage of the regulator is approximately given by:
Optional capacitor
reduces output noise
and improves
(R1 + R2)
R2
VOUT
=
x 1.204
transient response.
Figure 32. Typical Application Circuit for
Adjustable-Voltage Version
(
)
VOUT
VREF
R1 ) R2
VN + 32mVRMS
+ 32mVRMS
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 32. Sample
resistor values for common output voltages are
shown in Figure 2.
R2
(1)
Since the value of VREF is 1.2V, this relationship
reduces to:
mVRMS
V
ǒ
Ǔ
+ 27ǒ Ǔ
( )
V
VN mVRMS
VOUT
(2)
for the case of no CNR
.
12
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TPS737xx
www.ti.com
SBVS067O –JANUARY 2006–REVISED JUNE 2012
An internal 27kΩ resistor in series with the noise
reduction pin (NR) forms a low-pass filter for the
voltage reference when an external noise reduction
capacitor, CNR, is connected from NR to ground. For
CNR = 10nF, the total noise in the 10Hz to 100kHz
bandwidth is reduced by a factor of ~3.2, giving the
approximate relationship:
ENABLE PIN AND SHUTDOWN
The enable pin (EN) is active high and is compatible
with standard TTL-CMOS levels. A VEN below 0.5V
(max) turns the regulator off and drops the GND pin
current to approximately 10nA. When EN is used to
shutdown the regulator, all charge is removed from
the pass transistor gate, and the output ramps back
up to a regulated VOUT (see Figure 23).
mVRMS
VN(mVRMS) = 8.5
x VOUT(V)
V
(3)
When shutdown capability is not required, EN can be
connected to VIN. However, the pass gate may not be
discharged using this configuration, and the pass
transistor may be left on (enhanced) for a significant
time after VIN has been removed. This scenario can
result in reverse current flow (if the IN pin is low
impedance) and faster ramp times upon power-up. In
addition, for VIN ramp times slower than a few
milliseconds, the output may overshoot upon power-
up.
for CNR = 10nF.
This noise reduction effect is shown as RMS Noise
Voltage vs CNR in the Typical Characteristics section.
The TPS73701 adjustable version does not have the
NR pin available. However, connecting a feedback
capacitor, CFB, from the output to the feedback pin
(FB) reduces output noise and improve load transient
performance. This capacitor should be limited to
0.1µF.
Note that current limit foldback can prevent device
start-up under some conditions. See the Internal
Current Limit section for more information.
The TPS737xx uses an internal charge pump to
develop an internal supply voltage sufficient to drive
the gate of the NMOS pass element above VOUT. The
charge pump generates ~250μV of switching noise at
~4MHz; however, charge-pump noise contribution is
negligible at the output of the regulator for most
DROPOUT VOLTAGE
The TPS737xx uses an NMOS pass transistor to
achieve extremely low dropout. When (VIN – VOUT) is
less than the dropout voltage (VDO), the NMOS pass
device is in its linear region of operation and the
input-to-output resistance is the RDS, ON of the NMOS
pass element.
values of IOUT and COUT
.
BOARD LAYOUT RECOMMENDATION TO
IMPROVE PSRR AND NOISE PERFORMANCE
For large step changes in load current, the TPS737xx
requires a larger voltage drop from VIN to VOUT to
avoid degraded transient response. The boundary of
this transient dropout region is approximately twice
the dc dropout. Values of VIN – VOUT above this line
ensure normal transient response.
To improve ac performance such as PSRR, output
noise, and transient response, it is recommended that
the printed circuit board (PCB) be designed with
separate ground planes for VIN and VOUT, with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the
bypass capacitor should connect directly to the GND
pin of the device.
Operating in the transient dropout region can cause
an increase in recovery time. The time required to
recover from a load transient is a function of the
magnitude of the change in load current rate, the rate
of change in load current, and the available
headroom (VIN to VOUT voltage drop). Under worst-
case conditions [full-scale instantaneous load change
with (VIN – VOUT) close to dc dropout levels], the
INTERNAL CURRENT LIMIT
The TPS737xx internal current limit helps protect the
regulator during fault conditions. Foldback current
limit helps to protect the regulator from damage
during output short-circuit conditions by reducing
current limit when VOUT drops below 0.5V. See
Figure 12 in the Typical Characteristics section.
TPS737xx can take
a
couple of hundred
microseconds to return to the specified regulation
accuracy.
Note from Figure 12 that approximately –0.2V of VOUT
results in a current limit of 0mA. Therefore, if OUT is
forced below –0.2V before EN goes high, the device
may not start up. In applications that work with both a
positive and negative voltage supply, the TPS737xx
should be enabled first.
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TPS737xx
SBVS067O –JANUARY 2006–REVISED JUNE 2012
www.ti.com
TRANSIENT RESPONSE
After the EN pin is driven low, no bias voltage is
needed on any pin for reverse current blocking. Note
that reverse current is specified as the current flowing
out of the IN pin because of voltage applied on the
OUT pin. There will be additional current flowing into
the OUT pin as a result of the 80kΩ internal resistor
divider to ground (see Figure 1 and Figure 2).
The low open-loop output impedance provided by the
NMOS pass element in
a
voltage follower
configuration allows operation without a 1.0µF output
capacitor. As with any regulator, the addition of
additional capacitance from the OUT pin to ground
reduces undershoot magnitude but increases its
duration. In the adjustable version, the addition of a
capacitor, CFB, from the OUT pin to the FB pin will
also improve the transient response.
For the TPS73701, reverse current may flow when
VFB is more than 1.0V above VIN.
THERMAL PROTECTION
The TPS737xx does not have active pull-down when
the output is over-voltage. This architecture allows
applications that connect higher voltage sources,
such as alternate power supplies, to the output. This
architecture also results in an output overshoot of
several percent if the load current quickly drops to
zero when a capacitor is connected to the output. The
duration of overshoot can be reduced by adding a
load resistor. The overshoot decays at a rate
determined by output capacitor COUT and the
internal/external load resistance. The rate of decay is
given by:
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature, the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage due to
overheating.
Any tendency to activate the thermal protection circuit
indicates excessive power dissipation or an
inadequate heatsink. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(Fixed voltage version)
VOUT
dV
dT
+
COUT 80kW ø RLOAD
(4)
(5)
(including
heatsink),
increase
the
ambient
temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+35°C above the maximum expected ambient
condition of your application. This produces a worst-
case junction temperature of +125°C at the highest
expected ambient temperature and worst-case load.
(Adjustable voltage version)
VOUT
dV
+
dT
(
)
COUT 80kW ø R1 ) R2 ø RLOAD
REVERSE CURRENT
The NMOS pass element of the TPS737xx provides
inherent protection against current flow from the
output of the regulator to the input when the gate of
the pass device is pulled low. To ensure that all
charge is removed from the gate of the pass element,
the EN pin must be driven low before the input
voltage is removed. If this is not done, the pass
element may be left on because of stored charge on
the gate.
The internal protection circuitry of the TPS737xx has
been designed to protect against overload conditions.
It was not intended to replace proper heatsinking.
Continuously running the TPS737xx into thermal
shutdown degrades device reliability.
14
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Copyright © 2006–2012, Texas Instruments Incorporated
TPS737xx
www.ti.com
SBVS067O –JANUARY 2006–REVISED JUNE 2012
POWER DISSIPATION
Knowing the maximum RθJA, the minimum amount of
PCB copper area needed for appropriate heatsinking
can be estimated using Figure 33.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation.
160
DCQ
DRV
DRB
140
Power dissipation of the device depends on input
voltage and load conditions and can be calculated
using Equation 6:
120
100
80
60
40
20
0
ǒ
Ǔ
PD + VIN * VOUT IOUT
(6)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
On both SON (DRB) and SON (DRV) packages, the
primary conduction path for heat is through the
exposed pad to the printed circuit board (PCB). The
pad can be connected to ground or be left floating;
however, it should be attached to an appropriate
amount of copper PCB area to ensure the device
does not overheat. On the SOT-223 (DCQ) package,
the primary conduction path for heat is through the
tab to the PCB. That tab should be connected to
ground. The maximum junction-to-ambient thermal
resistance depends on the maximum ambient
temperature, maximum device junction temperature,
and power dissipation of the device and can be
calculated using Equation 7:
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Note: θJA value at board size of 9in2 (that is, 3in ×
3in) is a JEDEC standard.
Figure 33. θJA vs Board Size
Figure 33 shows the variation of θJA as a function of
ground plane copper area in the board. It is intended
only as a guideline to demonstrate the effects of heat
spreading in the ground plane and should not be
used to estimate actual thermal performance in real
application environments.
O
(
)
)125 C * TA
NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
R
+
qJA
PD
(7)
Copyright © 2006–2012, Texas Instruments Incorporated
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TPS737xx
SBVS067O –JANUARY 2006–REVISED JUNE 2012
www.ti.com
ESTIMATING JUNCTION TEMPERATURE
35
30
25
20
15
10
5
Using the thermal metrics ΨJT and ΨJB, as shown in
the Thermal Information table, the junction
temperature can be estimated with corresponding
formulas (given in Equation 8). For backwards
compatibility, an older θJC,Top parameter is listed as
well.
DRV
DCQ
DRB
YJB
DRV
DCQ
DRB
YJT
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(8)
Where PD is the power dissipation shown by
Equation 6, TT is the temperature at the center-top of
the IC package, and TB is the PCB temperature
measured 1mm away from the IC package on the
PCB surface (as Figure 35 shows).
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 34. ΨJT and ΨJB vs Board Size
NOTE: Both TT and TB can be measured on actual
application boards using a thermo-gun (an infrared
thermometer).
For a more detailed discussion of why TI does not
recommend using θJC(top) to determine thermal
characteristics, refer to application report SBVA025,
Using New Thermal Metrics, available for download
at www.ti.com. For further information, refer to
application report SPRA953, IC Package Thermal
Metrics, also available on the TI website.
For more information about measuring TT and TB, see
the application note SBVA025, Using New Thermal
Metrics, available for download at www.ti.com.
By looking at Figure 34, the new thermal metrics (ΨJT
and ΨJB) have very little dependency on board size.
That is, using ΨJT or ΨJB with Equation 8 is a good
way to estimate TJ by simply measuring TT or TB,
regardless of the application board size.
TB
X
1mm
TT on top
of IC
TT on top
of IC
TB on PCB
surface
TB on PCB
surface
TT
X
1mm
1mm
See note (1)
(a) Example DRB (SON) Package Measurement
(b) Example DRV (SON) Package Measurement
(c) Example DCQ (SOT-223) Package Measurement
(1) Power dissipation may limit operating range. Check Thermal Information table.
Figure 35. Measuring Points for TT and TB
16
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TPS737xx
www.ti.com
SBVS067O –JANUARY 2006–REVISED JUNE 2012
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (June 2011) to Revision O
Page
•
•
•
Changed Thermal Information table data and footnote 2b ................................................................................................... 3
Changed VFB Internal reference parameter in Electrical Characteristics table ..................................................................... 4
Changed title of Figure 8 ...................................................................................................................................................... 7
Changes from Revision M (October, 2010) to Revision N
Page
•
•
Added footnote (3) to Thermal Information table .................................................................................................................. 3
Added footnote to Figure 35 ............................................................................................................................................... 16
Copyright © 2006–2012, Texas Instruments Incorporated
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17
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS73701DCQ
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOT-223
SOT-223
SOT-223
SOT-223
SON
DCQ
6
6
6
6
8
8
8
8
6
6
6
6
6
6
8
8
6
78
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS73701
TPS73701DCQG4
TPS73701DCQR
TPS73701DCQRG4
TPS73701DRBR
TPS73701DRBRG4
TPS73701DRBT
TPS73701DRBTG4
TPS73701DRVR
TPS73701DRVT
TPS73718DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DCQ
DCQ
DCQ
DRB
DRB
DRB
DRB
DRV
DRV
DCQ
DCQ
DCQ
DCQ
DRB
DRB
DCQ
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU SN
TPS73701
TPS73701
TPS73701
BZN
2500
2500
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
BZN
SON
Green (RoHS
& no Sb/Br)
BZN
SON
250
Green (RoHS
& no Sb/Br)
BZN
SON
3000
250
Green (RoHS
& no Sb/Br)
QTN
SON
Green (RoHS
& no Sb/Br)
QTN
SOT-223
SOT-223
SOT-223
SOT-223
SON
78
Green (RoHS
& no Sb/Br)
TPS73718
TPS73718
TPS73718
TPS73718
RAL
TPS73718DCQG4
TPS73718DCQR
TPS73718DCQRG4
TPS73718DRBR
TPS73718DRBT
TPS73725DCQ
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU SN
2500
2500
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
RAL
SOT-223
78
Green (RoHS
& no Sb/Br)
TPS73725
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TPS73725DCQG4
TPS73725DCQR
ACTIVE
SOT-223
SOT-223
DCQ
6
6
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DCQ
DCQ
DRB
DRB
DCQ
DCQ
DCQ
DCQ
DRV
DRV
DCQ
DCQ
2500
2500
3000
250
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
TPS73725
TPS73725DCQRG4
TPS73730DRBR
TPS73730DRBT
TPS73733DCQ
SOT-223
SON
6
8
8
6
6
6
6
6
6
6
6
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS73725
CVT
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
CVT
SOT-223
SOT-223
SOT-223
SOT-223
SON
78
Green (RoHS
& no Sb/Br)
TPS73733
TPS73733
TPS73733
TPS73733
SIJ
TPS73733DCQG4
TPS73733DCQR
TPS73733DCQRG4
TPS73733DRVR
TPS73733DRVT
TPS73734DCQ
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU SN
2500
2500
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
SIJ
SOT-223
SOT-223
78
Green (RoHS
& no Sb/Br)
OCH
TPS73734DCQR
2500
Green (RoHS
& no Sb/Br)
OCH
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS73733 :
Automotive: TPS73733-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS73701DCQRG4
TPS73701DRBR
TPS73701DRBR
TPS73701DRBT
TPS73701DRBT
TPS73701DRVR
TPS73701DRVT
TPS73718DCQRG4
TPS73718DRBR
TPS73718DRBT
TPS73725DCQRG4
TPS73730DRBR
TPS73730DRBT
TPS73733DCQRG4
TPS73733DRVR
TPS73733DRVT
TPS73734DCQR
SOT-223 DCQ
6
8
8
8
8
6
6
6
8
8
6
8
8
6
6
6
6
2500
3000
3000
250
330.0
330.0
330.0
180.0
180.0
179.0
179.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
179.0
179.0
330.0
12.4
12.4
12.4
12.4
12.4
8.4
7.05
3.3
3.3
3.3
3.3
2.2
2.2
7.05
3.3
3.3
7.05
3.3
3.3
7.05
2.2
2.2
6.8
7.45
3.3
3.3
3.3
3.3
2.2
2.2
7.45
3.3
3.3
7.45
3.3
3.3
7.45
2.2
2.2
7.3
1.88
1.1
8.0
8.0
8.0
8.0
8.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
4.0
4.0
8.0
12.0
12.0
12.0
12.0
12.0
8.0
Q3
Q2
Q2
Q2
Q2
Q2
Q2
Q3
Q2
Q2
Q3
Q2
Q2
Q3
Q2
Q2
Q3
SON
SON
SON
SON
SON
SON
DRB
DRB
DRB
DRB
DRV
DRV
1.1
1.1
250
1.1
3000
250
1.2
8.4
1.2
8.0
SOT-223 DCQ
2500
3000
250
12.4
12.4
12.4
12.4
12.4
12.4
12.4
8.4
1.88
1.1
12.0
12.0
12.0
12.0
12.0
12.0
12.0
8.0
SON
SON
DRB
DRB
1.1
SOT-223 DCQ
2500
3000
250
1.88
1.1
SON
SON
DRB
DRB
1.1
SOT-223 DCQ
2500
3000
250
1.88
1.2
SON
SON
DRV
DRV
8.4
1.2
8.0
SOT-223 DCQ
2500
12.4
1.88
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS73701DCQRG4
TPS73701DRBR
TPS73701DRBR
TPS73701DRBT
TPS73701DRBT
TPS73701DRVR
TPS73701DRVT
TPS73718DCQRG4
TPS73718DRBR
TPS73718DRBT
TPS73725DCQRG4
TPS73730DRBR
TPS73730DRBT
TPS73733DCQRG4
TPS73733DRVR
TPS73733DRVT
TPS73734DCQR
SOT-223
SON
DCQ
DRB
DRB
DRB
DRB
DRV
DRV
DCQ
DRB
DRB
DCQ
DRB
DRB
DCQ
DRV
DRV
DCQ
6
8
8
8
8
6
6
6
8
8
6
8
8
6
6
6
6
2500
3000
3000
250
358.0
367.0
552.0
210.0
552.0
195.0
195.0
358.0
367.0
210.0
358.0
367.0
210.0
358.0
195.0
195.0
358.0
335.0
367.0
367.0
185.0
185.0
200.0
200.0
335.0
367.0
185.0
335.0
367.0
185.0
335.0
200.0
200.0
335.0
35.0
35.0
36.0
35.0
36.0
45.0
45.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
45.0
45.0
35.0
SON
SON
SON
250
SON
3000
250
SON
SOT-223
SON
2500
3000
250
SON
SOT-223
SON
2500
3000
250
SON
SOT-223
SON
2500
3000
250
SON
SOT-223
2500
Pack Materials-Page 2
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