TPS74801AQWDRCRQ1 [TI]

具有电源正常指示和使能功能的汽车类 1.5A、0.8V 低噪声可调节 LDO 稳压器 | DRC | 10 | -40 to 150;


型号：	TPS74801AQWDRCRQ1
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常指示和使能功能的汽车类 1.5A、0.8V 低噪声可调节 LDO 稳压器 \| DRC \| 10 \| -40 to 150 稳压器
文件：	总35页 (文件大小：1952K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS748A-Q1

ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023

TPS748A-Q1 具有可编程软启动功能的汽车类1.5A 低压降线性稳压器

1 特性

3 说明

• 符合面向汽车应用的AEC-Q100 标准：

TPS748A-Q1 低压降 (LDO) 线性稳压器可面向多种应

用提供易于使用的稳健型电源管理解决方案。用户可编

程软启动通过减少启动时的电容涌入电流，最大限度地

减少了输入电源上的应力。软启动具有单调性，旨在为

各类处理器和专用集成电路 (ASIC) 供电。借助使能输

入和电源正常输出，可通过外部稳压器轻松实现上电排

序。凭借全方位的灵活性，该器件可为现场可编程门阵

列(FPGA)、数字信号处理器 (DSP) 和其他具有特殊启

动要求的应用配置可满足其时序要求的解决方案。

– 温度等级1：–40°C ≤T_A≤+125°C

– HBM ESD 分类等级2

– CDM ESD 分类等级C4A

• 扩展结温(T_J) 范围：

– –40°C 至+150°C

• 输入电压范围：

– IN: V_IN+ V_DO至6.0V

– BIAS：V_OUT+ V_DO(BIAS)至6.0V

• V_OUT范围：0.8V 至3.6V

• 低压降：1.5A、V_BIAS= 5V 下的典型值为60mV

• 电源正常(PG) 输出可实现电源监视或为其他电源

提供时序信号

• 线路、负载和温度范围内的精度为2%

• 可编程软启动可提供线性电压启动

• V_BIAS支持低V_IN运行，具有良好的瞬态响应

• 与≥2.2μF 的任何输出电容器一起工作时可保持

稳定

该器件还具有高精度的参考电压电路和误差放大器，可

在整个负载、线路、温度和过程范围内提供2% 精度。

该器件在使用大于或等于 2.2μF 的任何类型的电容器

时都能保持稳定运行，并具有 T_J= –40°C 至 +150°C

的额定结温范围。TPS748A-Q1 采用小型 3mm ×

3mm VSON-10 封装，可实现高度紧凑的解决方案总

尺寸。

封装信息

封装⁽¹⁾

封装尺寸⁽²⁾

器件型号

• 采用小型3mm × 3mm × 1mm VSON-10 封装

TPS748A-Q1

DRC（VSON，10） 3.00mm × 3.00mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。

• 远程信息处理控制单元

• 信息娱乐系统与仪表组

• 成像雷达

V_IN

OUT

V_OUT

C_OUT

C_IN

R₁

V_BIAS

C_BIAS

BIAS

TPS748A-Q1

R₂

V_OUT

C_SS

R_PG

GND

典型应用电路（可调节）

输出电压噪声密度与频率间的关系

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS425

TPS748A-Q1

ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023

www.ti.com.cn

Table of Contents

7.4 Device Functional Modes..........................................16

8 Application and Implementation..................................17

8.1 Application Information............................................. 17

8.2 Typical Application.................................................... 21

8.3 Power Supply Recommendations.............................22

8.4 Layout....................................................................... 22

9 Device and Documentation Support............................25

9.1 接收文档更新通知..................................................... 25

9.2 支持资源....................................................................25

9.3 Trademarks...............................................................25

9.4 静电放电警告............................................................ 25

9.5 术语表....................................................................... 25

10 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics: I_OUT= 50 mA.........................7

7 Detailed Description......................................................12

7.1 Overview...................................................................12

7.2 Functional Block Diagram.........................................12

7.3 Feature Description...................................................12

Information.................................................................... 25

10.1 Tape and Reel Information......................................26

10.2 Mechanical Data..................................................... 28

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision * (December 2022) to Revision A (May 2023)

Page

• 将文档状态从预告信息更改为量产数据 ............................................................................................................ 1

English Data Sheet: SBVS425

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5 Pin Configuration and Functions

OUT

Thermal

Pad

BIAS

GND

图5-1. DRC Package, 10-Pin VSON With Thermal Pad (Top View)

表5-1. Pin Functions

TYPE

DESCRIPTION

NAME

BIAS

VSON

Bias input voltage for the error amplifier, reference, and internal control circuits. Use a 1-µF or

larger input capacitor for optimal performance. If IN is connected to BIAS, a 4.7-µF or larger

capacitor must be used.

Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into

shutdown mode. This pin must not be left unconnected.

Feedback pin. This pin is the feedback connection to the center tap of an external resistor divider

network that sets the output voltage. This pin must not be left floating.

GND

Ground

—

1, 2

Input to the device. Use a 1-µF or larger input capacitor for optimal performance.

No connection. This pin can be left floating or connected to GND to allow better thermal contact

to the top-side plane.

N/A

—

Regulated output voltage. A small capacitor (total typical capacitance ≥2.2 μF, ceramic) is

needed from this pin to ground to assure stability.

OUT

9, 10

Power-good pin. An open-drain, active-high output that indicates the status of V_OUT. When V_OUT

exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When V_OUTis

below this threshold the pin is driven to a low-impedance state. Connect a pullup resistor (10 kΩ

to 1 MΩ) from this pin to a supply of up to 6.0 V. The supply can be higher than the input voltage.

Alternatively, the PG pin can be left unconnected if output monitoring is not necessary.

Soft-start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left

unconnected, the regulator output soft-start ramp time is typically 200 μs.

—

Must be soldered to the ground plane for increased thermal performance. Internally connected to

ground.

Thermal pad

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ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023

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6 Specifications

6.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

6.5

UNIT

IN, BIAS

6.5

Voltage

6.5

V_BIAS

–0.3

OUT

V_IN+ 0.3

1.5

–0.3

OUT

Current

Internally limited

Indefinite

Output short-circuit duration

Continuous total power dissipation, P_DISS

See Thermal Information

Junction, T_J

Temperature

150

–40

–55

°C

Storage, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per AEC Q100-002⁽¹⁾

V_(ESD)

Electrostatic discharge

Charged device model (CDM), per AEC specification Q100-011

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

VOUT + 0.3

V_IN

MAX

6.0

UNIT

V_OUT+ V_DO

V_IN

Input supply voltage

Enable supply voltage

BIAS supply voltage

(V_IN

)

V_EN

V_BIAS

6.0

V_OUT+ V_DO

(VBIAS)⁽¹⁾

V_OUT+

6.0

1.6⁽¹⁾

V_OUT

I_OUT

C_OUT

C_IN

Output voltage

0.8

3.3

1.5

Output current

Output capacitor ⁽³⁾

Input capacitor ^{(1) (2)}

Bias capacitor

µF

C_BIAS

C_SS

T_J

0.1

Soft-start capacitor

Operating junction temperature

100

150

–40

℃

(1) V_BIAShas a minimum voltage of 2.7 V or V_OUT+ V_DO(V_BIAS), whichever is higher.

(2) If V_INand V_BIASare connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.

(3) A maximum capacitor derating of 25% is considered for minimum capacitance

English Data Sheet: SBVS425

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6.4 Thermal Information

TPS748A-Q1

THERMAL METRIC⁽¹⁾

DRC (VSON)

10 PINS

47.2

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

°C/W

R_θJC(top)

R_θJB

63.7

Junction-to-board thermal resistance

19.5

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

4.2

ψ_JT

19.4

ψ_JB

R_θJC(bot)

3.3

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application

report.

6.5 Electrical Characteristics

At V_EN= 1.1 V, V_IN= V_OUT+ 0.3 V, C_BIAS= 0.1 μF, C_IN= C_OUT= 10 μF, C_SS= 1 nF, I_OUT= 50 mA, V_BIAS= 5.0 V ⁽⁴⁾, and T_J

= –40°C to 150°C, (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_OUT

V_IN

Input voltage range

6.0

V_DO

V_BIAS

BIAS pin voltage range

2.7

0.796

1.0

6.0

0.804

1.75

V_REF

Internal reference (Adj.) T_A= +25°C

Rising bias supply UVLO

0.8

V_BIAS(UVLO)

1.25

V_BIAS(UVLO),

Bias supply UVLO

hysteresis

HYST

Output voltage range

Accuracy ^{(1) (5)}

V_IN= 5 V, I_OUT= 1.5 A

V_REF

3.6

ΔV_{OUT (ΔVIN)}

±0.5

0.03

0.09

1.25

2.97 V ≤V_BIAS≤5.5 V, 50 mA ≤I_OUT≤1.5 A

V_OUT(nom)+ 0.3 ≤V_IN≤5.5 V

50 mA ≤I_OUT≤1.5 A

–1.25

Line regulation

%/V

%/A

ΔV_{OUT (ΔIOUT)}

V_OUT

Load regulation

I_OUT= 1.5 A, V_BIAS–V_OUT(nom)≥3.25 V⁽³⁾

I_OUT= 1.5 A, V_IN= V_BIAS

V_DO(IN)

V_DO(BIAS)

I_CL

V_INdropout voltage⁽²⁾

V_BIASdropout voltage⁽²⁾

Output current limit

BIAS pin current

150

1.35

3.1

1.14

V_OUT= 80% × V_OUT(nom)

2.3

I_BIAS

I_OUT= 50 mA

0.67

0.9

1.1

Shutdown supply current

I_SHDN

I_FB

µA

V_EN≤0.4 V, V_IN= 1.1 V, V_OUT= 0.8 V

(I_GND

)

Feedback pin current

±0.12

0.22

µA

–0.22

1 kHz, I_OUT= 1.5 A, V_IN= 1.1 V, V_OUT= 0.8 V

300 kHz, I_OUT= 1.5 A, V_IN= 1.1 V, V_OUT= 0.8 V

1 kHz, I_OUT= 1.5 A, V_IN= 1.1 V, V_OUT= 0.8 V

300 kHz, I_OUT= 1.5 A, V_IN= 1.1 V, V_OUT= 0.8 V

Power-supply rejection

(V_INto V_OUT

)

PSRR

Power-supply rejection

(V_BIASto V_OUT

)

μVrms x

Vout

V_n

Output noise voltage

Minimum startup time

BW = 100 Hz to 100 kHz, I_OUT= 1.5 A, C_SS= 1 nF

R_LOADfor I_OUT= 1.0 A, C_SS= open

V_SS= 0.4 V

170

7.5

1.2

t_STR

I_SS

µs

Soft-start charging

current

µA

t_SS

Soft-start time

Css = 10 nF

V_EN(hi)

V_EN(lo)

V_EN(hys)

Enable input high level

Enable input low level

Enable pin hysteresis

1.1

5.5

0.4

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English Data Sheet: SBVS425

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6.5 Electrical Characteristics (continued)

At V_EN= 1.1 V, V_IN= V_OUT+ 0.3 V, C_BIAS= 0.1 μF, C_IN= C_OUT= 10 μF, C_SS= 1 nF, I_OUT= 50 mA, V_BIAS= 5.0 V ⁽⁴⁾, and T_J

= –40°C to 150°C, (unless otherwise noted); typical values are at T_J= 25°C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V_EN(dg)

I_EN

Enable pin deglitch time

Enable pin current

PG trip threshold

µs

V_EN= 5 V

0.1

0.3

µA

V_IT

V_OUTdecreasing

94 %V_OUT

%V_OUT

V_HYS

V_PG(lo)

I_PG(lkg)

PG trip hysteresis

PG output low voltage

PG leakage current

2.5

I_PG= 1 mA (sinking), V_OUT< V_IT

V_PG= 5.25 V, V_OUT> V_IT

0.125

0.01

0.1

µA

Operating junction

temperature

T_J

125

–40

℃

Shutdown, temperature increasing

Reset, temperature decreasing

165

140

Thermal shutdown

temperature

T_SD

(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.

(2) Dropout is defined as the voltage from V_INto V_OUTwhen V_OUTis 3% below nominal.

(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 12.

(4) V_BIAS= V_{DO_MAX(BIAS)}+ V_OUTfor V_OUT≥3.4 V

(5) The device is not tested under conditions where V_IN> V_OUT+ 1.65 V and I_OUT= 1.5 A, because the power dissipation is higher than

the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the

power dissipation limit of the package under test.

English Data Sheet: SBVS425

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6.6 Typical Characteristics: I_OUT= 50 mA

at T_J= 25°C, V_IN= V_OUT(nom)+ 0.3 V, V_BIAS= 5 V, I_OUT= 50 mA, V_EN= V_IN, C_IN= 1 μF, C_BIAS= 4.7 μF, and C_OUT= 10 μF

(unless otherwise noted)

V_OUT= 0.8 V, I_OUT= 1.5 A, C_BIAS= 0.1 μF, C_OUT= 10 μF,

V_IN= 1.1 V, V_OUT= 0.8 V, I_OUT= 1.5 A, C_BIAS= 0.1 μF,

C_OUT= 10 μF, V_EN= V_BIAS= 6 V

C_SS= 10 nF, V_EN= V_BIAS= 6 V

图6-1. IN PSRR vs Frequency and V_IN

图6-2. IN PSRR vs Frequency and C_SS

V_IN= 1.1 V, V_OUT= 0.8 V, C_BIAS= 0.1 μF, C_OUT= 10 μF,

V_IN= 2.1 V, V_OUT= 1.8 V, C_BIAS= 0.1 μF, C_OUT= 10 μF,

C_SS= 10 nF, V_EN= V_BIAS= 6 V

图6-3. IN PSRR vs Frequency and I_OUTfor V_OUT= 0.8 V

图6-4. PSRR vs Frequency and I_OUTfor V_OUT= 1.8 V

V_IN= 3.6 V, V_OUT= 3.3 V, C_BIAS= 0.1 μF, C_OUT= 10 μF,

V_IN= 1.1 V, V_OUT= 0.8 V, I_OUT= 1.5 A, C_BIAS= 0.1 μF,

C_SS= 10 nF, V_EN= V_BIAS= 6 V

图6-5. IN PSRR vs Frequency and I_OUTfor V_OUT= 3.3 V

图6-6. IN PSRR vs Frequency and C_OUT

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6.6 Typical Characteristics: I_OUT= 50 mA (continued)

at T_J= 25°C, V_IN= V_OUT(nom)+ 0.3 V, V_BIAS= 5 V, I_OUT= 50 mA, V_EN= V_IN, C_IN= 1 μF, C_BIAS= 4.7 μF, and C_OUT= 10 μF

(unless otherwise noted)

V_EN= V_IN= 1.1 V, V_OUT= 0.8 V, I_OUT= 1.5 A, C_IN= 10 μF,

V_IN= 1.1 V, V_OUT= 0.8 V, I_OUT= 1.5 A, C_IN= 10 μF,

C_OUT= 10 μF, C_SS= 10 nF, V_BIAS= 6 V

C_OUT= 10 μF, C_SS= 10 nF, V_EN= 6 V

图6-8. BIAS PSRR vs Frequency and I_OUT

图6-7. BIAS PSRR vs Frequency and V_BIAS

V_EN= V_BIAS, V_IN= 1.1 V, V_OUT= 0.8 V, I_OUT= 1.5 A,

V_EN= V_BIAS, V_IN= 1.1 V, V_OUT= 0.8 V, C_IN= 10 μF,

C_OUT= 10 μF, C_SS= 10 nF, C_BIAS= 0.1 μF

C_IN= 10 μF, C_OUT= 10 μF, C_SS= 10 nF, C_BIAS= 0.1 μF

图6-9. Output Voltage Noise Density vs Frequency and V_BIAS

图6-10. Output Voltage Noise Density vs Frequency and I_OUT

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6.6 Typical Characteristics: I_OUT= 50 mA (continued)

at T_J= 25°C, V_IN= V_OUT(nom)+ 0.3 V, V_BIAS= 5 V, I_OUT= 50 mA, V_EN= V_IN, C_IN= 1 μF, C_BIAS= 4.7 μF, and C_OUT= 10 μF

(unless otherwise noted)

V_BIAS= 5 V, V_OUT= 0.8 V

V_IN= 1.1 V, V_OUT= 0.8 V

图6-11. IN-to-OUT Dropout Voltage vs I_OUTand Temperature (T_J) 图6-12. BIAS-to-OUT Dropout Voltage vs I_OUTand Temperature

(T_J)

V_IN= 1.1 V, V_BIAS= 5 V, V_OUT= 0.8 V

图6-14. Load Regulation vs ≥50-mA Output Current

图6-13. Load Regulation vs 0-mA to 50-mA Output Current

V_OUT= 0.8 V, V_BIAS= 5 V, I_OUT= 50 mA

V_BIAS= 5 V, V_OUT= 0.8 V, I_OUT= 50 mA

图6-15. Line Regulation vs Input Voltage

图6-16. Output Voltage vs Bias Voltage

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6.6 Typical Characteristics: I_OUT= 50 mA (continued)

at T_J= 25°C, V_IN= V_OUT(nom)+ 0.3 V, V_BIAS= 5 V, I_OUT= 50 mA, V_EN= V_IN, C_IN= 1 μF, C_BIAS= 4.7 μF, and C_OUT= 10 μF

(unless otherwise noted)

V_OUT= 0.8 V, V_BIAS= 5.0 V

V_OUT= 0.8 V, V_BIAS= 5.0 V, I_OUT= 50 mA

图6-18. IN Pin Quiescent Current vs Output Current

图6-17. IN Pin Quiescent Current vs Input Voltage

V_OUT= 0.8 V, V_BIAS= 5.0 V, I_OUT= 1.5 A

V_IN= 1.1 V, V_OUT= 0.8 V, V_BIAS= 5.0 V

图6-19. BIAS Pin Quiescent Current vs Input Voltage

图6-20. BIAS Pin Quiescent Current vs Output Current

V_BIAS= 5 V, V_EN= 0 V

V_IN= 1.1 V, V_EN= 0 V

图6-21. Shutdown Current (GND Pin) vs Input Voltage

图6-22. Shutdown Current (GND Pin) vs Bias Voltage

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6.6 Typical Characteristics: I_OUT= 50 mA (continued)

at T_J= 25°C, V_IN= V_OUT(nom)+ 0.3 V, V_BIAS= 5 V, I_OUT= 50 mA, V_EN= V_IN, C_IN= 1 μF, C_BIAS= 4.7 μF, and C_OUT= 10 μF

(unless otherwise noted)

图6-23. Current Limit vs Output Voltage

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7 Detailed Description

7.1 Overview

The TPS748A-Q1 is a low-input, low-output (LILO), low-quiescent-current linear regulator optimized to support

excellent transient performance. This regulator uses a low-current bias rail to power all internal control circuitry,

allowing the n-type field effect transistor (NMOS) pass transistor to regulate very-low input and output voltages.

Using an NMOS pass transistor offers several critical advantages for many applications. Unlike a p-channel

metal-oxide-semiconductor field effect transistor (PMOS) topology device, the output capacitor has little effect on

loop stability. This architecture allows the TPS748A-Q1 to be stable with any ceramic capacitor 10 μF or

greater. Transient response is also superior to PMOS topologies, particularly for low V_INapplications.

The TPS748A-Q1 features a programmable, voltage-controlled, soft-start circuit that provides a smooth,

monotonic start-up and limits start-up inrush currents that can be caused by large capacitive loads. An enable

(EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low

V_INand V_OUTcapability allows for inexpensive, easy-to-design, and efficient linear regulation between the

multiple supply voltages often required by processor-intensive systems.

7.2 Functional Block Diagram

OUT

V_OUT

500 ꢀ

BIAS

UVLO

Thermal &

Current

Limit

7.5 µA

R₁

C_SS

Soft-Start

Discharge

0.8-V

Reference

120 ꢀ

Hysteresis

and Deglitch

R₂

V_OUT

Delay^(B)

10 kꢀ

0.9 x

V_REF

GND

7.3 Feature Description

7.3.1 Enable and Shutdown

The enable (EN) pin is active high and compatible with standard digital-signaling levels. Setting V_ENbelow 0.4 V

turns the regulator off, and setting V_ENabove 1.1 V turns the regulator on. Unlike many regulators, the enable

circuitry has hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration

allows the device to be enabled by connecting the output of another supply to the EN pin. The enable circuitry

typically has 70 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in

the V_ENsignal.

The enable threshold is typically 0.75 V and varies with temperature and process variations. Temperature

variation is approximately –1.2 mV/°C; process variation accounts for most of the remaining variation to the 0.4-

V and 1.1-V limits. If precise turn-on timing is required, a fast rise-time signal must be used.

If not used, EN can be connected to BIAS. Place the connection as close as possible to the bias capacitor.

English Data Sheet: SBVS425

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7.3.2 Active Discharge

The TPS748A-Q1 has an internal active pulldown circuits on the OUT pin.

Each active discharge function uses an internal metal-oxide-semiconductor field-effect transistor (MOSFET) that

connects a resistor (R_PULLDOWN) to ground when the low-dropout resistor (LDO) is disabled in order to actively

discharge the output voltage. The active discharge circuit is activated when the device is disabled by driving EN

to logic low, when the voltage at IN or BIAS is below the UVLO threshold, or when the regulator is in thermal

shutdown.

The discharge time after disabling the device depends on the output capacitance (C_OUT) and the load resistance

(R_L) in parallel with the pulldown resistor.

The first active pulldown circuit connects the output to GND through a 600-Ω resistor when the device is

disabled.

The second circuit connects FB to GND through a 120-Ω resistor when the device is disabled. This resistor

discharges the FB pin. 方程式 1 calculates the output capacitor discharge time constant when OUT is shorted to

FB, or when the output voltage is set to 0.65 V.

τ_OUT= (600 || 120 × R_L/ (600 || 120 + R_L) × C_OUT

(1)

If the LDO is set to an output voltage greater than 0.65 V, a resistor divider network is in place and minimizes the

FB pin pulldown. 方程式2 and 方程式3 calculate the time constants set by these discharge resistors.

R_DISCHARGE= (120 || R₂) + R₁

(2)

(3)

τ_OUT= R_DISCHARGE× R_L/ (R_DISCHARGE+ R_L) × C_OUT

Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input

supply has collapsed because reverse current can flow from the output to the input and can cause damage to

the device. Limit reverse current to no more than 5% of the device-rated current.

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7.3.3 Power-Good Output (PG)

The PG signal provides an easy solution to meet demanding sequencing requirements because PG signals

when the output nears the nominal value. PG can be used to signal other devices in a system when the output

voltage is near, at, or above the set output voltage (V_OUT(nom)). 图7-1 shows a simplified schematic.

The PG signal is an open-drain digital output that requires a pullup resistor to a voltage source and is active

high. The PG circuit sets the PG pin into a high-impedance state to indicate that the power is good.

Using a large feed-forward capacitor (C_FF) delays the output voltage and, because the PG circuit monitors the

FB pin, the PG signal can indicate a false positive.

V_PG

V_BG

V_IN

V_FB

GND

UVLO_BIAS

GND

图7-1. Simplified PG Circuit

7.3.4 Internal Current Limit

The device has an internal current-limit circuit that protects the regulator during transient high-load current faults

or shorting events. The current limit is a hybrid brick-wall foldback scheme. The current limit transitions from a

brick-wall scheme to a foldback scheme at the foldback voltage (V_FOLDBACK). In a high-load current fault with the

output voltage above V_FOLDBACK, the brick-wall scheme limits the output current to the current limit (I_CL). When

the voltage drops below V_FOLDBACK, a foldback current limit activates that scales back the current when the

output voltage approaches GND. When the output is shorted, the device supplies a typical current called the

short-circuit current limit (I_SC). I_CLand I_SCare listed in the Electrical Characteristics table.

For this device, V_FOLDBACKis approximately 60% × V_OUT(nom)

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The output voltage is not regulated when the device is in current limit. When a current-limit event occurs, the

device begins to heat up because of the increase in power dissipation. When the device is in a brick-wall current

limit, the pass transistor dissipates power [(V_IN–V_OUT) × I_CL]. When the device output is shorted and the output

is below V_FOLDBACK, the pass transistor dissipates power [(V_IN– V_OUT) × I_SC]. If thermal shutdown is triggered,

the device turns off. When the device sufficiently cools down, the internal thermal shutdown circuit turns the

device back on. If the output current fault condition continues, the device cycles between current limit and

thermal shutdown. For more information on current limits, see the Know Your Limits application note. 图 7-2

shows a diagram of the foldback current limit.

V_OUT

Brickwall

V_OUT(NOM)

V_FOLDBACK

Foldback

0 V

I_OUT

I_RATED

0 mA

I_SC

I_CL

图7-2. Foldback Current Limit

7.3.5 Thermal Shutdown Protection (T_SD

)

The internal thermal shutdown protection circuit disables the output when the thermal junction temperature (T_J)

of the pass transistor rises to the thermal shutdown temperature threshold, T_{SD(shutdown) (typical)}. The thermal

shutdown circuit hysteresis makes sure that the LDO resets (turns on) when the temperature falls to

T_{SD(reset) (typical)}

The thermal time constant of the semiconductor die is fairly short; thus, the device can cycle on and off when

thermal shutdown is reached until the power dissipation is reduced. Power dissipation during start up can be

high from large V_IN– V_OUTvoltage drops across the device or from high inrush currents charging large output

capacitors. Under some conditions, the thermal shutdown protection disables the device before start up

completes.

For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating

Conditions table. Operation above this maximum temperature causes the device to exceed operational

specifications. Although the internal protection circuitry is designed to protect against thermal overload

conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the regulator into

thermal shutdown, or above the maximum recommended junction temperature, reduces long-term reliability.

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7.4 Device Functional Modes

表 7-1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table

for parameter values.

表7-1. Device Functional Mode Comparison

PARAMETER

OPERATING MODE

V_IN

V_BIAS

V_EN

I_OUT

T_J

V_IN≥V_{OUT (nom)}

V_DO(IN)and V_IN≥

T_J< T_SDfor

shutdown

_BIAS≥V_OUT+

V_DO(BIAS)

Normal mode

Dropout mode

I_OUT< I_CL

V_EN≥V_HI(EN)

V_IN(min)

V_IN(min)< V_IN< V_OUT

_(nom)+ V_DO(IN)

T_J< T_SDfor

shutdown

V_BIAS< V_OUT+ V_DO(BIAS)

V_EN> V_HI(EN)

I_OUT< I_CL

Disabled mode

(any true condition

disables the device)

T_J≥T_SDfor

shutdown

V_IN< V_UVLO(IN)

V_BIAS< V_BIAS(UVLO)

V_EN< V_LO(EN)

—

7.4.1 Normal Operation

The device regulates to the nominal output voltage when the following conditions are met:

• The input voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO(IN)

)

• The bias voltage is greater than the nominal output voltage plus the dropout voltage (V_OUT(nom)+ V_DO(BIAS)

• The output current is less than the current limit (I_OUT< I_CL)

)

• The device junction temperature is less than the thermal shutdown temperature ( T_J< T_SD(shutdown)

)

• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased

to less than the enable falling threshold

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other

conditions are met for normal operation, the device operates in dropout mode. Similarly, if the bias voltage is

lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for

normal operation, the device operates in dropout mode as well. In this mode, the output voltage tracks the input

voltage. During this mode, the transient performance of the device becomes significantly degraded because the

pass transistor is in the ohmic or triode region, and functions as a switch. Line or load transients in dropout can

result in large output voltage deviations.

When the device is in a steady dropout state, defined as when the device is in dropout (V_IN< V_OUT+ V_DO(IN)or

V_BIAS< V_OUT+ V_DO(BIAS)directly after being in normal regulation state, but not during start up), the pass

transistor is driven into the ohmic or triode region. When the input voltage returns to a value greater than or

equal to the nominal output voltage plus the dropout voltage (V_OUT(NOM)+ V_DO(IN)), the output voltage can

overshoot for a short time when the device pulls the pass transistor back into the linear region.

7.4.3 Disabled

The output of the device can be shutdown by forcing the voltage of the enable pin to less than V_IL(EN)(see the

Electrical Characteristics table). When disabled, the pass transistor is turned off, internal circuits are shutdown,

and the output voltage is actively discharged to ground by an internal discharge circuit from the output to ground.

The device is disabled under the following conditions:

• The input or bias voltages are below the respective minimum specifications

• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising

threshold

• The device junction temperature is greater than the thermal shutdown temperature

English Data Sheet: SBVS425

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8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPS748A-Q1 is a low-input, low-output (LILO), low-dropout regulator (LDO) that features soft-start

capability. This regulator uses a low-current bias input to power all internal control circuitry, allowing the NMOS

pass transistor to regulate very low input and output voltages.

Using an NMOS pass transistor offers several critical advantages for many applications. Unlike a PMOS

topology device, the output capacitor has little effect on loop stability. This architecture allows stability with

ceramic capacitors of 10 μF or greater. Transient response is also superior to PMOS topologies, particularly for

low V_INapplications.

A programmable voltage-controlled, soft-start circuit provides a smooth, monotonic start-up and limits start-up

inrush currents that can be caused by large capacitive loads. An enable (EN) pin with hysteresis and deglitch

allows slow-ramping signals to be used for sequencing the device. The low V_INand V_OUTcapability allows for

inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required

by processor-intensive systems.

8.1.1 Input, Output, and Bias Capacitor Requirements

The device is designed to be stable for ceramic capacitor of values ≥ 10 μF. The device is also stable with

multiple capacitors in parallel, which can be of any type or value.

The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To

counteract any inductance in the input, the minimum recommended capacitor for V_INis 1 μF and the minimum

recommended capacitor for V_BIASis 0.1 µF. If V_INand V_BIASare connected to the same supply, the

recommended minimum capacitor for V_BIASis 4.7 μF. Use good quality, low equivalent series resistance (ESR)

and equivalent series inductance (ESL) capacitors on the input; ceramic X5R and X7R capacitors are preferred.

Place these capacitors as close the pins as possible for optimum performance.

Low ESR and ESL capacitors improve high-frequency PSRR.

8.1.2 Dropout Voltage

The TPS748A-Q1 offers very low dropout performance, making the device designed for high-current, low V_IN

and low V_OUTapplications. The low dropout allows the device to be used in place of a dc/dc converter and still

achieve good efficiency. 方程式4 provides a quick estimate of the efficiency.

_OUT´ I_OUT

V_OUT

V_IN

at I_OUT>> I_Q

Efficiency »

V_IN´ (I_IN+ I_Q)

(4)

This efficiency provides designers with the power architecture for applications to achieve the smallest, simplest,

and lowest cost solutions.

For this architecture, there are two different specifications for dropout voltage. The first specification (see 图

6-11 ) is referred to as V_INdropout and is used when an external bias voltage is applied to achieve low dropout.

This specification assumes that V_BIASis at least 2.8 V above V_OUT, which is the case for V_BIASwhen powered by

a 5.0-V rail with 5% tolerance and with V_OUT= 1.5 V. If V_BIASis higher than V_OUT+ 2.8 V, the V_INdropout is less

than specified.

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备注

2.8 V is a test condition of this device and can be adjusted by referring to the Electrical Characteristics

table.

The second specification (illustrated in 图6-12 ) is referred to as V_BIASdropout and applies to applications where

IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias

voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because

V_BIASprovides the gate drive to the pass transistor; therefore, V_BIASmust be 1.9 V above V_OUT. Because of this

usage, having IN and BIAS tied together become a highly inefficient solution that can consume large amounts of

power. Pay attention not to exceed the power rating of the device package.

8.1.3 Output Noise

The TPS748A-Q1 provides low output noise when a soft-start capacitor is used. When the device reaches the

end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 10-nF,

soft-start capacitor, the output noise is reduced by half and is typically 7.1 μV_RMSfor a 0.8-V output (10 Hz to

100 kHz). Increasing C_SShas no effect on noise. Because most of the output noise is generated by the internal

reference, the noise is a function of the set output voltage. 方程式 5 gives the RMS noise with a 10-nF, soft-start

capacitor:

ꢀV

≈

∆

’

◊

RMS

V ( ꢀV_RMS) = 7.1∂

∂V_OUT(V)

(5)

The low output noise makes this LDO a good choice for powering transceivers, phase-locked loops (PLLs), or

other noise-sensitive circuitry.

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8.1.4 Estimating Junction Temperature

By using the thermal metrics Ψ_JTand Ψ_JB, as shown in the Thermal Information table, the junction temperature

can be estimated with corresponding formulas (given in 方程式 6). For backwards compatibility, an older θ_JC(top)

parameter is listed as well.

Y_JT: T_J= T_T+ Y_JT· P_D

Y_JB: T_J= T_B+ Y_JB· P_D

(6)

where:

• P_Dis the power dissipation

• T_Tis the temperature at the center-top of the package

• T_Bis the PCB temperature measured 1 mm away from the package on the PCB surface

备注

Both T_Tand T_Bcan be measured on actual application boards using a thermo-gun (an infrared

thermometer).

For more information about measuring T_Tand T_B, see the Using New Thermal Metrics application note,

available for download at www.ti.com.

For a more detailed discussion of why TI does not recommend using θ_JC(top)to determine thermal

characteristics, see the Using New Thermal Metrics application note, available for download at www.ti.com. For

further information, see the Semiconductor and IC Package Thermal Metrics application note, also available on

the TI website.

8.1.5 Soft Start, Sequencing, and Inrush Current

Soft-start refers to the ramp-up characteristic of the output voltage during LDO turn-on after EN and UVLO

achieve threshold voltage. The soft start current is fixed for fixed output voltage versions.

Although the device does not have any sequencing requirement, following the sequencing order of BIAS, IN, and

EN makes sure that the soft start starts from zero.

图 8-1 shows an example of the device behavior when the EN pin is enabled prior to having either power supply

up. Under this condition, the output jumps from 0 V to approximately 0.3 V almost instantly when the IN voltage

is sufficient to power the circuit.

图8-1. Sequencing and Soft-Start Behavior for V_OUT= 1 V

Inrush current is defined as the current into the LDO at the IN pin during start-up. Inrush current then consists

primarily of the sum of load current and the current used to charge the output capacitor. This current is difficult to

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measure because the input capacitor must be removed, which is not recommended. However, 方程式 7 can

estimate this soft-start current:

_OUT´ dV_OUT(t)

V_OUT(t)

R_LOAD

I_OUT(t)

(7)

where:

• V_OUT(t) is the instantaneous output voltage of the turn-on ramp

• dV_OUT(t) / dt is the slope of the V_OUTramp

• R_LOADis the resistive load impedance

8.1.6 Power-Good Operation

For proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ.

The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the

upper limit of 100 kΩresults from the maximum leakage current at the power-good node. If the pullup resistor is

outside of this range, then the power-good signal can possibly not read a valid digital logic level.

The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO

events and at light loads, power-good does not assert because the output voltage is sustained by the output

capacitance.

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8.2 Typical Application

This section discusses the implementation of the TPS748A-Q1 to regulate a 1-A load requiring good PSRR at

high frequency with low noise. 图8-2 provides a schematic for this typical application circuit.

V_IN

OUT

V_OUT

C_OUT

C_IN

R₁

V_BIAS

C_BIAS

BIAS

TPS748A-Q1

R₂

V_OUT

C_SS

R_PG

GND

图8-2. Typical ADJ Voltage Application

8.2.1 Design Requirements

For this design example, use the parameters listed in 表8-1 as the input parameters.

表8-1. Design Parameters

PARAMETER

Input voltage

DESIGN REQUIREMENT

2.1 V, ±3%, provided by the dc/dc converter switching at 500 kHz

Bias voltage

5.0 V

1.8 V, ±1%

Output voltage

Output current

1.0 A (maximum), 10 mA (minimum)

< 10 µV_RMS

RMS noise, 10 Hz to 100 kHz

PSRR at 500 kHz

Start-up time

> 40 dB

< 25 ms

8.2.2 Detailed Design Procedure

At 1.0 A and 1.8 V_OUT, the dropout of the TPS748A-Q1 has a 105-mV maximum dropout over temperature; thus,

a 300-mV headroom is sufficient for operation over both input and output voltage accuracy. At full load and high

temperature on some devices, the TPS748A can enter dropout if both the input and output supply are beyond

the edges of the respective accuracy specification.

To satisfy the required start-up time and still maintain low noise performance, a 10-nF C_SSis selected. 方程式 8

calculates this value.

t_SS= (V_SS× C_SS) / I_SS

(8)

At the 1.0-A maximum load, the internal power dissipation is 0.3 W and corresponds to a 13.3°C junction

temperature rise for the DRC package on a standard JEDEC board. With an 55°C maximum ambient

temperature, the junction temperature is at 68.3°C.

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8.2.3 Application Curve

图8-3. PSRR vs Frequency for

V_OUT= 1.8 V

8.3 Power Supply Recommendations

The TPS748A-Q1 is designed to operate from an input voltage up to 6.0 V, provided the bias rail is at least 1.3 V

higher than the input supply and dropout requirements are met. The bias rail and the input supply must both

provide adequate headroom and current for the device to operate normally. Connect a low output impedance

power supply directly to the IN pin. This supply must have at least 1 μF of capacitance near the IN pin for

optimal performance. A supply with similar requirements must also be connected directly to the BIAS rail with a

separate 0.1 μF or larger capacitor. If the IN pin is tied to the BIAS pin, a minimum 4.7-μF capacitor is required

for performance. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or ferrite bead

before the input capacitor.

8.4 Layout

8.4.1 Layout Guidelines

An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on

the input of the device during load transients, the capacitance on IN and BIAS must be connected as close as

possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the

input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the

top side of R₁in 图 8-2 must be connected as close as possible to the load. If BIAS is connected to IN, connect

BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on

BIAS during transient conditions and can improve the turn-on response.

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal

pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device can

be calculated using 方程式9 and depends on input voltage and load conditions.

P_D= (V_IN- V_OUT) ´ I_OUT

(9)

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input

voltage necessary to achieve the required output voltage regulation.

On the VSON (DRC) package, the primary conduction path for heat is through the exposed pad to the printed

circuit board (PCB). The pad can be connected to ground or left floating; however, the thermal pad must be

attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum

junction-to-ambient thermal resistance can be calculated using 方程式 10 and depends on the maximum

ambient temperature, maximum device junction temperature, and power dissipation of the device.

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(+125°C - T_A)

R_qJA

P_D

(10)

The minimum amount of PCB copper area needed for appropriate heat sinking (which can be estimated using 图

8-4) is determined by knowing the maximum R_θJA

140

120

100

DRC

RGW

Board Copper Area (in²)

The R_θJAvalue at board size of 9 in²(that is, 3 in × 3 in) is a JEDEC standard.

图8-4. R_θJAvs Board Size

图 8-4 shows the variation of R_θJAas a function of ground plane copper area in the board. This figure is

intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and is not intended

to be used to estimate actual thermal performance in real application environments.

备注

When the device is mounted on an application PCB, use Ψ_JTand Ψ_JB, as explained in the Estimating

Junction Temperature section.

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8.4.2 Layout Example

TOP View

GND Plane

C_IN

C_OUT

IINN

OUT

R₂

SNS

R_PG

R₁

BIAS

Thermal vias

GND Plane

CBIAS

C_SS

GND

BIAS

Represents a via

图8-5. Example Layout

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9 Device and Documentation Support

9.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

9.2 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

9.3 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

9.4 静电放电警告

静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理

和安装程序，可能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参

数更改都可能会导致器件与其发布的规格不相符。

9.5 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: TPS748A-Q1

English Data Sheet: SBVS425

TPS748A-Q1

ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023

www.ti.com.cn

10.1 Tape and Reel Information

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

Reel

Diameter

(mm)

Reel

Width W1

(mm)

Package

Type

Package

Drawing

(mm)

Pin1

Quadrant

Device

Pins

SPQ

TPS74801AQWDRCRQ

VSON

DRC

3000

330.0

12.4

3.3

1.1

8.0

12.0

English Data Sheet: SBVS425

Submit Document Feedback

Product Folder Links: TPS748A-Q1

TPS748A-Q1

ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023

www.ti.com.cn

TAPE AND REEL BOX DIMENSIONS

Width (mm)

Device

TPS74801AQWDRCRQ1

Package Type

Package Drawing Pins

DRC 10

SPQ

Length (mm) Width (mm)

367.0 367.0

Height (mm)

VSON

3000

35.0

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Product Folder Links: TPS748A-Q1

English Data Sheet: SBVS425

TPS748A-Q1

ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023

www.ti.com.cn

10.2 Mechanical Data

PACKAGE OUTLINE

DRC0010W

VSON - 1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE - NO LEAD

3.1

2.9

PIN 1 INDEX AREA

3.1

2.9

0.07 MIN

(0.13)

30.0

SECTION A-A

TYPICAL

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

1.65 0.1

2X (0.5)

4X (0.25)

(0.2) TYP

EXPOSED

THERMAL PAD

(0.16) TYP

SYMM

2.4 0.1

8X 0.5

0.3

0.2

10X

SYMM

PIN 1 ID

(OPTIONAL)

0.1

C A B

0.05

0.5

0.3

10X

4228236/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com

English Data Sheet: SBVS425

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Product Folder Links: TPS748A-Q1

TPS748A-Q1

ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023

www.ti.com.cn

EXAMPLE BOARD LAYOUT

DRC0010W

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

(1.65)

(0.5)

10X (0.6)

10X (0.25)

(2.4)

SYMM

(3.4)

(0.95)

8X (0.5)

(R0.05) TYP

( 0.2) VIA

TYP

(0.25)

(0.575)

SYMM

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

EXPOSED METAL

SOLDER MASK

OPENING

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4228236/A 12/2021

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

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Product Folder Links: TPS748A-Q1

English Data Sheet: SBVS425

TPS748A-Q1

ZHCSP78A –DECEMBER 2022 –REVISED MAY 2023

www.ti.com.cn

EXAMPLE STENCIL DESIGN

DRC0010W

VSON - 1 mm max height

PLASTIC SMALL OUTLINE - NO LEAD

2X (1.5)

(0.5)

SYMM

EXPOSED METAL

TYP

10X (0.6)

(1.53)

10X (0.25)

(1.06)

SYMM

(0.63)

8X (0.5)

(R0.05) TYP

4X (0.34)

4X (0.25)

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 11:

80% PRINTED SOLDER COVERAGE BY AREA

SCALE:25X

4228236/A 12/2021

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

English Data Sheet: SBVS425

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Product Folder Links: TPS748A-Q1

PACKAGE OPTION ADDENDUM

www.ti.com

28-May-2023

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

PTPS74801AQWDRCRQ1

TPS74801AQWDRCRQ1

ACTIVE

VSON

DRC

3000

TBD

Call TI

-40 to 150

Samples

3000 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

74801A

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

28-May-2023

OTHER QUALIFIED VERSIONS OF TPS748A-Q1 :

Catalog : TPS748A

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS74801AQWDRCRQ1 VSON

DRC

3000

330.0

12.4

3.3

1.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSON DRC 10

SPQ

Length (mm) Width (mm) Height (mm)

360.0 360.0 36.0

TPS74801AQWDRCRQ1

3000

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

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TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS74801AQWDRCRQ1 [TI]

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