TPS76201_17 [TI]
LOW OUTPUT ADJUSTABLE ULTRALOW-POWER 100-mA LDO LINEAR REGULATOR;
| 型号： | TPS76201_17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW OUTPUT ADJUSTABLE ULTRALOW-POWER 100-mA LDO LINEAR REGULATOR 输出元件 |
| 文件： | 总16页 (文件大小：580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢇ
ꢈ ꢉ ꢊ ꢉ ꢋꢀ ꢁꢋꢀ ꢌꢍꢎ ꢋ ꢂꢀꢌ ꢏꢈ ꢐ
ꢋꢈꢀ ꢑꢌꢈ ꢉ ꢊꢒꢁꢉ ꢊ ꢐꢑ ꢇ ꢆ ꢆ ꢒꢓꢌ ꢈ ꢍꢉ ꢈ ꢔꢕꢐ ꢌꢑ ꢑꢐ ꢖ ꢋꢈ ꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
DBV PACKAGE
(TOP VIEW)
D
D
D
D
D
D
100-mA Low-Dropout Regulator
Adjustable Output Voltage (0.7 V to 5.5 V)
Only 23 µA Quiescent Current at 100 mA
1 µA Quiescent Current in Standby Mode
Over Current Limitation
1
2
3
5
OUT
FB
IN
GND
4
EN
−40°C to 125°C Operating Junction
Temperature Range
D
5-Pin SOT-23 (DBV) Package
GROUND CURRENT
vs
JUNCTION TEMPERATURE
description
27
25
23
21
19
17
15
V = 2.7 V
I
O
I
O
= 100 mA
V
= 0.7 V
The TPS76201 low-dropout (LDO) voltage
regulator features an adjustable output voltage as
low as 0.7 V. It is an ideal regulator for sub 1.2-V
DSP core voltage supplies and is equally suited
for similar applications with other low-voltage
processors and controllers. SOT-23 packaging
and the high-efficiency that results from the
regulator’s ultralow power operation make the
TPS76201 especially useful in handheld and
portable battery applications. This regulator
features low dropout voltages and ultralow
quiescent current compared to conventional LDO
I
O
= 10 µA
−40 −25 −10
5
20 35 50 65 80 95 110 125
T
− Junction Temperature − °C
J
regulators. Offered in a 5-terminal small outline integrated-circuit SOT-23 package, the TPS76201 is ideal for
micropower operations and where board space is at a premium.
A combination of new circuit design and process innovation has enabled the usual PNP pass transistor to be
replaced by a PMOS pass element. Since the PMOS pass element is a voltage-driven device, the quiescent
current is ultralow (30 µA maximum) and is stable over the entire range of output load current (10 µA to 100 mA).
Intended for use in portable systems such as laptops and cellular phones, the ultralow-power operation results
in a significant increase in the system battery operating life.
The TPS76201 also features a logic-enabled sleep mode to shut down the regulator, reducing quiescent current
to 1 µA typical at T = 25°C. The TPS76201 is offered in an adjustable version (programmable over the range
J
of 0.7 V to 5.5 V).
†
AVAILABLE OPTIONS
T
J
VOLTAGE
PACKAGE
PART NUMBER
SYMBOL
Variable
0.7 V to 5.5 V
SOT-23
(DBV)
‡
§
−40°C to 125°C
TPS76201DBVT
TPS76201DBVR
PFUI
†
‡
§
Contact the factory for availability of fixed output options.
The DBVT indicates tape and reel of 250 parts.
The DBVR indicates tape and reel of 3000 parts.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
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Copyright 2001−2007, Texas Instruments Incorporated
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1
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ
ꢈ ꢉꢊ ꢉꢋ ꢀ ꢁꢋ ꢀ ꢌꢍ ꢎ ꢋꢂꢀꢌꢏ ꢈꢐ
ꢋ ꢈꢀ ꢑ ꢌꢈ ꢉꢊꢒꢁ ꢉꢊꢐ ꢑ ꢇ ꢆ ꢆꢒ ꢓꢌ ꢈꢍ ꢉ ꢈꢔ ꢕ ꢐ ꢌꢑ ꢑꢐꢖ ꢋꢈ ꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
Ĕ
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Input voltage range ꢀ ꢁ ꢂꢂ ꢃ ꢄꢅꢂ ꢆ ꢇ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 13.5 V
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
I
Voltage on OUT, FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
DERATING FACTOR
T
A
≤ 25°C
T
A
= 70°C
T = 85°C
A
BOARD
PACKAGE
R
R
θJC
θJA
ABOVE T = 25°C
POWER RATING POWER RATING POWER RATING
A
‡
Low K
DBV
DBV
65.8°C/W
65.8°C/W
259°C/W
180°C/W
3.9 mW/°C
5.6 mW/°C
386 mW
555 mW
212 mW
305 mW
154 mW
222 mW
§
High K
‡
§
The JEDEC Low K (1s) board design used to derive this data was a 3 inch x 3 inch, two layer board with 2 ounce copper traces on top of the board.
The JEDEC High K (2s2p) board design used to derive this data was a 3 inch x 3 inch, multilayer board with 1 ounce internal power and ground
planes and 2 ounce copper traces on top and bottom of the board.
recommended operating conditions
MIN NOM
MAX
10
UNIT
V
Input voltage, V (see Note 2)
2.7
0.7
I
Output voltage range, V
5.5
V
O
Continuous output current, I (see Note 3)
0.01
−40
100
125
mA
°C
O
Operating junction temperature, T
J
NOTES: 2. To calculate the minimum input voltage for your maximum output current, use the following formula:
= V + V (max load)
V
Imin
Omax DO
3. Continuous output current and operating junction temperature are limited by internal protection circuitry, but it is not recommended
that the device operate under conditions beyond those specified in this table for extended periods of time.
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2
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢇ
ꢈ ꢉ ꢊ ꢉ ꢋꢀ ꢁꢋꢀ ꢌꢍꢎ ꢋꢂ ꢀꢌ ꢏꢈ ꢐ
ꢋꢈꢀ ꢑꢌꢈ ꢉ ꢊꢒꢁꢉ ꢊ ꢐꢑ ꢇ ꢆ ꢆ ꢒꢓꢌ ꢈ ꢍꢉ ꢈ ꢔꢕꢐ ꢌꢑ ꢑꢐꢖ ꢋ ꢈꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
electrical characteristics over recommended operating free-air temperature range,
V = V
+ 1 V, I = 100 mA, EN = 0 V, C = 4.7 µF (unless otherwise noted)
I
O(typ)
O
o
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.7 V ≤ V ≤ 5.5 V, T = 25°C
V
O
O
J
Output voltage (10 µA to 100 mA load) (see Note 4)
V
0.7 V ≤ V ≤ 5.5 V,
T = −40°C to 125°C
J
0.97V
1.03V
O
O
O
EN = 0V,
10 µA < I < 100 mA
T = 25°C
J
23
O
Quiescent current (GND current)
(see Notes 4 and 5)
µA
EN = 0 V,
T = −40°C to 125°C,
J
30
10 µA < I < 100 mA
O
EN = 0 V,
T = 25°C
J
Load regulation
12
mV
10 µA < I < 100 mA
O
2.7 V < V ≤ 10 V,
See Note 4
T = 25°C,
J
I
0.04
Output voltage line regulation (∆V /V ) (see Note 5)
%/V
O
O
2.7 V < V ≤ 10 V,
T = −40°C to 125°C, See Note 4
J
I
0.1
BW = 300 Hz to 50 kHz,
C = 10 µF,
o
J
Output noise voltage
Output current limit
60
µV
RMS
V
O
= 0.7 V,
T = 25°C
V
O
= 0 V,
See Note 4
350
1
750
mA
µA
µA
µA
V
EN = V ,
2.7 < V < 10 V
I
I
Standby current
T = −40°C to 125°C
J
2
1
FB input current
FB = 0.666 V
−1
High level enable input voltage
Low level enable input voltage
2.7 V < V < 10 V
1.7
I
2.7 V < V < 10 V
I
0.8
V
f = 1 kHz,
T = 25°C,
J
C = 10 µF,
o
See Note 4
Power supply ripple rejection
Input current (EN)
60
0
dB
EN = 0 V
−1
−1
1
1
µA
µA
EN = V
I
NOTES: 4. Minimum IN operating voltage is 2.7 V or V
+ 1 V, whichever is greater. Maximum IN voltage 10 V, minimum output current
O(typ)
10 µA, maximum output current 100 mA.
5. If V ≤ 1.8 V then V
= 2.7 V, V
= 10 V:
O
Imin
Imax
OǒVImax * 2.7 VǓ
V
ǒ
Ǔ
Line Reg. (mV) + %ńV
1000
100
If V ≥ 2.5 V then V
Imin
= V + 1 V, V = 10 V:
Imax
O
O
* ǒVO
100
Ǔ
OǒVImax
) 1 V Ǔ
V
ǒ
Ǔ
Line Reg. (mV) + %ńV
1000
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3
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ
ꢈ ꢉꢊ ꢉꢋ ꢀ ꢁꢋ ꢀ ꢌꢍ ꢎ ꢋꢂꢀꢌꢏ ꢈꢐ
ꢋ ꢈꢀ ꢑ ꢌꢈ ꢉꢊꢒꢁ ꢉꢊꢐ ꢑ ꢇ ꢆ ꢆꢒ ꢓꢌ ꢈꢍ ꢉ ꢈꢔ ꢕ ꢐ ꢌꢑ ꢑꢐꢖ ꢋꢈ ꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
functional block diagram
TPS76201
OUT
FB
IN
EN
Current Limit
/ Thermal
Protection
V
REF
GND
Terminal Functions
TERMINAL
NAME NO.
GND
I/O
DESCRIPTION
2
3
4
1
5
Ground
EN
FB
I
I
Enable input
Feedback voltage
IN
I
Input supply voltage
OUT
O
Regulated output voltage
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
1, 2
V
O
Output voltage
vs Junction temperature
3
Ground current
vs Junction temperature
vs Frequency
4
Output spectral noise density
Output impedance
5
z
vs Frequency
6
7
o
vs Input voltage
V
DO
Dropout voltage
vs Junction temperature
vs Frequency
8
Power supply ripple rejection
Output voltage and enable voltage
Line transient response
9
vs Time (start-up)
10
11, 13
12, 14
15, 16
Load transient response
Equivalent series resistance (ESR)
vs Output current
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4
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢇ
ꢈ ꢉ ꢊ ꢉ ꢋꢀ ꢁꢋꢀ ꢌꢍꢎ ꢋꢂ ꢀꢌ ꢏꢈ ꢐ
ꢋꢈꢀ ꢑꢌꢈ ꢉ ꢊꢒꢁꢉ ꢊ ꢐꢑ ꢇ ꢆ ꢆ ꢒꢓꢌ ꢈ ꢍꢉ ꢈ ꢔꢕꢐ ꢌꢑ ꢑꢐꢖ ꢋ ꢈꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT CURRENT
JUNCTION TEMPERATURE
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
0.720
0.6680
0.6675
0.6670
0.6665
0.6660
V = 3.5 V
I
O
V = 2.7 V
I
V = 2.7 V
I
O
= 1 mA
I
V
= 2.5 V
= 4.7 µF
= 25° C
V
= 0.7 V
= 4.7 µF
= 25° C
V
= V
ref
0.715
0.710
0.705
0.700
0.695
0.690
0.685
O
O
C
o
C
C
= 4.7 µF
o
J
o
T
J
T
I
O
= 100 mA
0.6655
0.6650
0.6645
0
20
40
60
80
100
0
20
40
60
80
100
−40 −25−10
5
20 35 50 65 80 95 110 125
I
O
− Output Current − mA
I
O
− Output Current − mA
T
− Junction Temperature − °C
J
Figure 2
Figure 1
Figure 3
GROUND CURRENT
vs
OUTPUT SPECTRAL NOISE DENSITY
vs
OUTPUT IMPEDANCE
vs
JUNCTION TEMPERATURE
FREQUENCY
FREQUENCY
3.5
3
500
27
25
23
21
19
17
15
V = 2.7 V
I
O
V = 2.7 V
V = 2.7 V
V
I
I
O
450
I
O
= 100 mA
V
= 0.7 V
V
C
R
= 0.7 V
= 4.7 µF
≈ 0.3
O
o
ESR
= 0.7 V,
= 1 mA,
= 4.7 µF
400
350
2.5
2
I
O
C
o
1.5
1
300
250
I
O
= 10 µA
I
O
= 1 mA
0.5
0
200
150
I
= 100 mA
100 k
O
−0.5
100
50
0
−1
−1.5
10
100
1k
10 k
1 M
100
1 k
10 k
100 k
−40 −25 −10
5
20 35 50 65 80 95 110 125
f − Frequency − Hz
f − Frequency − Hz
T
− Junction Temperature − °C
J
Figure 6
Figure 5
Figure 4
POWER SUPPLY RIPPLE REJECTION
vs
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
DROPOUT VOLTAGE
vs
JUNCTION TEMPERATURE
FREQUENCY
90
180
160
140
120
100
80
1000
100
10
V = 2.7 V
I
I
O
= 100 mA
80
70
60
50
40
30
20
10
V = 3.2 V
I
V
C
= 0.7 V
= 4.7 µF
O
o
C
= 4.7 µF
O
I
O
= 100 mA
T
= 125°C
J
I
O
= 1 mA
T
= 25°C
J
I
O
= 10 mA
60
I
O
= 100 mA
T
= −40°C
J
40
20
0
−10
1
2
4
6
8
10
10
100
1 k
10 k 100 k 1 M
10 M
−40 −25 −10
5 20 35 50 65 80 95 110 125
− Junction Temperature − °C
V − Input Voltage − V
I
f − Frequency − Hz
T
J
Figure 7
Figure 9
Figure 8
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5
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ
ꢈ ꢉꢊ ꢉꢋ ꢀ ꢁꢋ ꢀ ꢌꢍ ꢎ ꢋꢂꢀꢌꢏ ꢈꢐ
ꢋ ꢈꢀ ꢑ ꢌꢈ ꢉꢊꢒꢁ ꢉꢊꢐ ꢑ ꢇ ꢆ ꢆꢒ ꢓꢌ ꢈꢍ ꢉ ꢈꢔ ꢕ ꢐ ꢌꢑ ꢑꢐꢖ ꢋꢈ ꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE AND ENABLE
VOLTAGE
vs
TIME (START-UP)
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
V = 2.7 V
I
100
0
V
C
= 0.7 V
= 4.7 µF
= 100 mA
3.7
O
o
5
0
I
T
o
= 25°C
J
2.7
10
1
0.5
0
0
-100
-200
0
−10
V = 2.7 V
I
O
I
V
C
= 10 mA
O
V
= 0.7 V
= 0.7 V
O
C
= 10 µF
o
= 4.7 µF
o
0
20 40 60 80 100 120 140 160 180 200
0
50 100 150 200 250 300 350 400 450 500
0
50 100 150 200 250 300 350 400 450 500
t − Time (Start-Up) − µs
t − Time − µs
t − Time − µs
Figure 10
Figure 11
Figure 12
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
100
0
4.5
3.5
20
100
0
0
−100
−20
V
= 2.5 V
O
V
= 2.5 V
= 100 mA
= 4.7 µF
O
V = 3.5 V
C
I
I
O
= 10 µF
o
C
o
0
60 80 100
t − Time − µs
140 160 180 200
120
20 40
0
50 100 150 200 250 300 350400 450 500
t − Time − µs
Figure 13
Figure 14
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
OUTPUT CURRENT
100
100
C
= 4.7 µF
C
= 10 µF
o
o
10
10
Region of Instability
Region of Instability
1
1
Region of Instability
Region of Instability
0.1
0.1
0
0.02
0.04
0.06
0.08
0.10
0
0.02
0.04
0.06
0.08
0.10
I
O
− Output Current − A
I
O
− Output Current − A
Figure 16
Figure 15
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6
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢇ
ꢈ ꢉ ꢊ ꢉ ꢋꢀ ꢁꢋꢀ ꢌꢍꢎ ꢋꢂ ꢀꢌ ꢏꢈ ꢐ
ꢋꢈꢀ ꢑꢌꢈ ꢉ ꢊꢒꢁꢉ ꢊ ꢐꢑ ꢇ ꢆ ꢆ ꢒꢓꢌ ꢈ ꢍꢉ ꢈ ꢔꢕꢐ ꢌꢑ ꢑꢐꢖ ꢋ ꢈꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
APPLICATION INFORMATION
The TPS76201 low-dropout (LDO) regulator has been optimized for use in battery-operated equipment
including, but not limited to, the sub 1.2-V DSP core voltage supplies. It features low quiescent current (23 µA
nominally) and enable inputs to reduce supply currents to 1 µA when the regulators are turned off.
A typical application circuit is shown in Figure 17.
TPS76201
1
V
I
IN
5
V
OUT
FB
O
C1
1 µF
3
EN
4
+
4.7 µF
GND
2
ESR = 0.5 Ω
Figure 17. Typical Application Circuit
external capacitor requirements
Although not required, a 0.047-µF or larger ceramic input bypass capacitor, connected between IN and GND
and located close to the TPS76201, is recommended to improve transient response and noise rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
Like all low dropout regulators, the TPS76201 requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance is 4.7 µF. The ESR (equivalent
series resistance) of the capacitor should be between 0.3 Ω and 1.5 Ω. to ensure stability. Capacitor values
larger than 4.7 µF are acceptable, and allow the use of smaller ESR values. Capacitances less than 4.7 µF are
not recommended because they require careful selection of ESR to ensure stability. Solid tantalum electrolytic,
aluminum electrolytic, and multilayer ceramic capacitors are all suitable, provided they meet the requirements
described above. Most of the commercially available 4.7 µF surface-mount solid tantalum capacitors, including
devices from Sprague, Kemet, and Nichico, meet the ESR requirements stated above. Multilayer ceramic
capacitors may have very small equivalent series resistances and may thus require the addition of a low value
series resistor to ensure stability.
CAPACITOR SELECTION
†
‡
PART NO.
MFR.
KEMET
SPRAGUE
SPRAGUE
AVX
VALUE
4.7 µF
10 µF
10 µF
4.7 µF
MAX ESR
1.5 Ω
SIZE (H × L × W)
1.9 × 3.5 × 2.8
1.3 × 7.0 × 2.7
2.5 × 7.6 × 2.5
2.6 × 6.0 × 3.2
T494B475K016AS
195D106x0016x2T
695D106x003562T
TPSC475K035R0600
1.5 Ω
1.3 Ω
0.6 Ω
†
‡
ESR is maximum resistance in Ohms at 100 kHz and T = 25°C. Contact manufacturer for minimum ESR values.
Size is in mm.
A
www.ti.com
7
ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ ꢇ
ꢈ ꢉꢊ ꢉꢋ ꢀ ꢁꢋ ꢀ ꢌꢍ ꢎ ꢋꢂꢀꢌꢏ ꢈꢐ
ꢋ ꢈꢀ ꢑ ꢌꢈ ꢉꢊꢒꢁ ꢉꢊꢐ ꢑ ꢇ ꢆ ꢆꢒ ꢓꢌ ꢈꢍ ꢉ ꢈꢔ ꢕ ꢐ ꢌꢑ ꢑꢐꢖ ꢋꢈ ꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
APPLICATION INFORMATION
output voltage programming
The output voltage of the TPS76201 adjustable regulator is programmed using an external resistor divider as
shown in Figure 18. The output voltage is calculated using:
R1
R2
ǒ1 )
Ǔ
(1)
V
+ V
O
ref
Where:
V
= 0.6663 V typ (the internal reference voltage)
ref
Resistors R1 and R2 should be chosen for approximately 10-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 66.5 kΩ to set the divider current at 10 µA and then calculate R1 using:
V
O
R1 +
ǒ
* 1
Ǔ
R2
(2)
V
ref
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS76201
DIVIDER RESISTANCE
OUTPUT
VOLTAGE
(V)
1
‡
V
(kΩ)
I
IN
1 µF
R1
R2
5
0.7
0.9
1.2
1.5
1.8
2.5
3.3
3.6
4
3.36
23.2
53.6
83.5
113
66.5
66.5
66.5
66.5
66.5
66.5
66.5
66.5
66.5
66.5
V
OUT
FB
O
≥1.7 V
3
R1
R2
EN
4
≤0.9 V
4.7 µF
GND
2
ESR = 0.5 Ω
182
246
294
332
432
5
‡
1% values shown.
Figure 18. TPS76201 Adjustable LDO Regulator Programming
www.ti.com
8
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢇ
ꢈ ꢉ ꢊ ꢉ ꢋꢀ ꢁꢋꢀ ꢌꢍꢎ ꢋꢂ ꢀꢌ ꢏꢈ ꢐ
ꢋꢈꢀ ꢑꢌꢈ ꢉ ꢊꢒꢁꢉ ꢊ ꢐꢑ ꢇ ꢆ ꢆ ꢒꢓꢌ ꢈ ꢍꢉ ꢈ ꢔꢕꢐ ꢌꢑ ꢑꢐꢖ ꢋ ꢈꢌꢀꢉ ꢑ
SLVS323B − FEBRUARY 2001 − REVISED JANUARY 2007
APPLICATION INFORMATION
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P
, and the actual dissipation, P , which must be less than
D(max)
D
or equal to P
.
D(max)
The maximum-power-dissipation limit is determined using the following equation:
T max * T
J
A
P
+
D(max)
R
qJA
Where:
T max is the maximum allowable junction temperature.
J
R
is the thermal resistance junction-to-ambient for the package, see the dissipation rating table.
θJA
T is the ambient temperature.
A
The regulator dissipation is calculated using:
+ ǒVI * V
Ǔ
P
I
D
O
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
regulator protection
The TPS76201 PMOS-pass transistor has a built-in back diode that conducts reverse current when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might
be appropriate.
The TPS76201 features internal current limiting and thermal protection. During normal operation, the
TPS76201 limits output current to approximately 350 mA. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package. If the
temperature of the device exceeds approximately 165°C, thermal-protection circuitry shuts it down. Once the
device has cooled down to below approximately 140°C, regulator operation resumes.
www.ti.com
9
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TPS76201DBVR
TPS76201DBVRG4
TPS76201DBVT
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
DBV
5
5
5
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
PFUI
ACTIVE
ACTIVE
ACTIVE
DBV
DBV
DBV
3000
250
Green (RoHS
& no Sb/Br)
PFUI
PFUI
PFUI
Green (RoHS
& no Sb/Br)
TPS76201DBVTG4
250
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF TPS76201 :
Automotive: TPS76201-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS76201DBVR
TPS76201DBVT
SOT-23
SOT-23
DBV
DBV
5
5
3000
250
178.0
178.0
9.0
9.0
3.23
3.23
3.17
3.17
1.37
1.37
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS76201DBVR
TPS76201DBVT
SOT-23
SOT-23
DBV
DBV
5
5
3000
250
180.0
180.0
180.0
180.0
18.0
18.0
Pack Materials-Page 2
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