TPS76501DR [TI]
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS;
| 型号： | TPS76501DR |
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TEXAS INSTRUMENTS |
| 描述： | ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS 光电二极管 输出元件 调节器 |
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TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
D PACKAGE
(TOP VIEW)
150-mA Low-Dropout Voltage Regulator
Available in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V,
3.0-V, 3.3-V, 5.0-V Fixed Output and
Adjustable Versions
NC/FB
PG
OUT
OUT
IN
1
2
3
4
8
7
6
5
Dropout Voltage to 85 mV (Typ) at 150 mA
(TPS76550)
GND
EN
IN
Ultra-Low 35-µA Typical Quiescent Current
3% Tolerance Over Specified Conditions for
Fixed-Output Versions
Open Drain Power Good
8-Pin SOIC Package
Thermal Shutdown Protection
description
This device is designed to have an ultra-low quiescent current and be stable with a 4.7-µF capacitor. This
combination provides high performance at a reasonable cost.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 85 mV
at an output current of 150 mA for the TPS76550) and is directly proportional to the output current. Additionally,
since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent
of output loading (typically 35 µA over the full range of output current, 0 mA to 150 mA). These two key
specifications yield a significant improvement in operating life for battery-powered systems. This LDO family
also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the
quiescent current to less than 1 µA (typ).
TPS76533
DROPOUT VOLTAGE
vs
TPS76533
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
LOAD CURRENT
0
10
35.0
34.9
34.8
34.7
34.6
34.5
34.4
34.3
34.2
34.1
34.0
V
T
= 3.3 V
= 25°C
O
A
V = 3.2 V
I
I
O
= 150 mA
–1
10
10
10
I
O
= 50 mA
I
O
= 10 mA
–2
–3
–50 –25
0
25
50
75
100 125 150
0
25
50
I – Load Current – mA
L
75
100
125
150
T
– Free-Air Temperature – °C
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
description (continued)
Power good (PG) is an active high output, which can be used to implement a power-on reset or a low-battery
indicator.
The TPS765xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3.0-V, 3.3-V and 5.0-V fixed-voltage versions and
in an adjustable version (programmable over the range of 1.25 V to 5.5 V). Output voltage tolerance is specified
as a maximum of 3% over line, load, and temperature ranges. The TPS765xx family is available in 8 pin SOIC
package.
AVAILABLE OPTIONS
OUTPUT VOLTAGE
PACKAGED DEVICES
(V)
T
J
SOIC
(D)
TYP
5.0
3.3
3.0
2.8
2.7
2.5
1.8
1.5
TPS76550D
TPS76533D
TPS76530D
TPS76528D
TPS76527D
TPS76525D
TPS76518D
TPS76515D
–40°C to 125°C
Adjustable
1.25 V to 5.5 V
TPS76501D
The TPS76501 is programmable using an external resistor divider (see application
information). The D package is available taped and reeled. Add an R suffix to the
device type (e.g., TPS76501DR).
TPS765xx
5
6
2
1
7
8
V
IN
IN
PG
PG
I
NC/FB
OUT
OUT
V
O
4
0.1 µF
EN
†
C
O
+
4.7 µF
GND
3
300 mΩ
†
See application information section for capacitor selection details.
Figure 1. Typical Application Configuration for Fixed Output Options
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
functional block diagram—adjustable version
IN
EN
PG
_
+
OUT
+
_
R1
V
ref
= 1.224 V
FB/NC
R2
GND
External to the device
functional block diagram—fixed-voltage version
IN
EN
PG
_
+
OUT
+
_
R1
V
ref
= 1.224 V
R2
GND
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
Terminal Functions – SOIC Package
TERMINAL
I/O
DESCRIPTION
NAME
NO.
4
EN
I
I
Enable input
FB/NC
GND
IN
1
Feedback input voltage for adjustable device (no connect for fixed options)
3
Regulator ground
Input voltage
5
I
IN
6
I
Input voltage
OUT
OUT
PG
7
O
O
O
Regulated output voltage
Regulated output voltage
PG output
8
2
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Input voltage range , V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 13.5 V
I
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 16.5 V
Maximum PG voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating tables
Output voltage, V (OUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
O
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE 1 – FREE-AIR TEMPERATURES
AIR FLOW
(CFM)
T
< 25°C
DERATING FACTOR
T
= 70°C
T = 85°C
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING POWER RATING
A
0
568 mW
5.68 mW/°C
9.04 mW/°C
312 mW
497 mW
227 mW
361 mW
D
250
904 mW
recommended operating conditions
MIN
MAX
UNIT
V
2.7
1.2
0
10
5.5
Input voltage, V
I
Output voltage range, V
V
O
Output current, I (Note 1)
150
125
mA
°C
O
Operating virtual junction temperature, T (Note 1)
–40
J
To calculate the minimum input voltage for your maximum output current, use the following equation: V
I(min)
= V
+ V
.
DO(max load)
O(max)
NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
electrical characteristics over recommended operating free-air temperature range,
V = V
+ 1 V, I = 10 µA, EN = 0 V, C = 4.7 µF (unless otherwise noted)
i
O(typ)
O
O
PARAMETER
TEST CONDITIONS
5.5 V ≥ V ≥ 1.25 V, T = 25°C
MIN
TYP
MAX
UNIT
V
O
O
J
TPS76501
TPS76515
TPS76518
TPS76525
TPS76527
TPS76528
TPS76530
TPS76533
TPS76550
5.5 V ≥ V ≥ 1.25 V, T = –40°C to 125°C
0.97V
1.03V
O
J
O
O
T = 25°C,
J
2.7 V < V < 10 V
IN
1.5
1.8
2.5
2.7
2.8
3.0
3.3
5.0
35
T = –40°C to 125°C, 2.7 V < V < 10 V
J IN
1.455
1.545
T = 25°C,
J
2.8 V < V < 10 V
IN
T = –40°C to 125°C, 2.8 V < V < 10 V
J IN
1.746
2.425
2.619
2.716
2.910
3.201
4.850
1.854
2.575
2.781
2.884
3.090
3.399
5.150
50
T = 25°C,
J
3.5 V < V < 10 V
IN
T = –40°C to 125°C, 3.5 V < V < 10 V
J IN
Output voltage
(10 µA to 150 mA load)
(see Note 2)
T = 25°C,
J
3.7 V < V < 10 V
IN
V
T = –40°C to 125°C, 3.7 V < V < 10 V
J IN
T = 25°C,
J
3.8 V < V < 10 V
IN
T = –40°C to 125°C, 3.8 V < V < 10 V
J IN
T = 25°C,
J
4.0 V < V < 10 V
IN
T = –40°C to 125°C, 4.0 V < V < 10 V
J IN
T = 25°C,
J
4.3 V < V < 10 V
IN
T = –40°C to 125°C, 4.3 V < V < 10 V
J IN
T = 25°C,
J
6.0 V < V < 10 V
IN
T = –40°C to 125°C, 6.0 V < V < 10 V
J IN
10 µA < I < 150 mA, T = 25°C
Quiescent current (GND current)
EN = 0V, (see Note 2)
O
J
µA
I
O
= 150 mA,
T = –40°C to 125°C
J
Output voltage line regulation (∆V /V
(see Notes 2 and 3)
O
O
)
V
+ 1 V < V ≤ 10 V, T = 25°C
0.01
0.3%
200
%/V
O
I
J
Load regulation
I
O
= 10 µA to 150 mA
BW = 300 Hz to 50 kHz,
C
Output noise voltage
Output current Limit
µVrms
= 4.7 µF,
T = 25°C
J
O
V
O
= 0 V
0.8
1.2
A
Thermal shutdown junction temperature
150
°C
EN = V
EN = V
T = 25°C,
J
I,
I,
1
µA
µA
2.7 V < V < 10 V
I
Standby current
T = –40°C to 125°C
J
10
2.7 V < V < 10 V
I
FB input current
TPS76501
FB = 1.5 V
2
nA
V
High level enable input voltage
Low level enable input voltage
2.0
92
0.8
V
f = 1 kHz,
C
= 4.7 µF,
O
Power supply ripple rejection (see Note 2)
63
dB
V
I
I
= 10 µA,
T = 25°C
J
O
Minimum input voltage for valid PG
Trip threshold voltage
= 300µA
1.1
O(PG)
V
O
decreasing
98
%V
%V
V
O
PG
Hysteresis voltage
Output low voltage
Leakage current
Measured at V
0.5
O
O
V = 2.7 V,
I
I
= 1mA
O(PG)
0.15
0.4
1
V
= 5 V
µA
(PG)
EN = 0 V
EN = V
–1
–1
0
1
Input current (EN)
µA
1
I
NOTE: 2. Minimum IN operating voltage is 2.7 V or V
+ 1 V, whichever is greater. Maximum IN voltage 10 V.
O(typ)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
electrical characteristics over recommended operating free-air temperature range,
V = V
+ 1 V, I = 10 µA, EN = 0 V, C = 4.7 µF (unless otherwise noted) (continued)
i
O(typ)
O
O
PARAMETER
TEST CONDITIONS
T = 25°C
MIN
TYP
MAX
330
280
240
150
UNIT
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
= 150 mA,
= 150 mA,
= 150 mA,
= 150 mA,
= 150 mA,
= 150 mA,
= 150 mA,
= 150 mA,
190
J
TPS76528
TPS76530
TPS76533
TPS76550
T = –40°C to 125°C
J
T = 25°C
J
160
140
85
T = –40°C to 125°C
J
Dropout voltage
(See Note 4)
mV
T = 25°C
J
T = –40°C to 125°C
J
T = 25°C
J
T = –40°C to 125°C
J
NOTES: 3. If V ≤ 1.8 V then V
imin
= 2.7 V, V = 10 V:
imax
O
V
V
V
2.7 V
1000
O
O
imax
100
Line Reg. (mV)
% V
If V ≥ 2.5 V then V
imin
= V + 1 V, V
imax
= 10 V:
% V
O
O
V
V
1 V
imax
O
Line Reg. (mV)
1000
100
4. IN voltage equals V (Typ) – 100 mV; TPS76501 output voltage set to 3.3 V nominal with external resistor divider. TPS76515,
O
TPS76518, TPS76525, and TPS76527 dropout voltage limited by input voltage range limitations (i.e., TPS76530 input voltage
needs to drop to 2.9 V for purpose of this test).
Table of Graphs
FIGURE
vs Load current
2, 3
4, 5
Output voltage
Ground current
vs Free-air temperature
vs Load current
6, 7
vs Free-air temperature
vs Frequency
8, 9
Power supply ripple rejection
Output spectral noise density
Output impedance
10
vs Frequency
11
vs Frequency
12
Dropout voltage
vs Free-air temperature
13, 14
15, 17
16, 18
19
Line transient response
Load transient response
Output voltage
vs Time
Dropout voltage
vs Input voltage
20
Equivalent series resistance (ESR)
Equivalent series resistance (ESR)
vs Output current
vs Added ceramic capacitance
21 – 24
25, 26
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
TYPICAL CHARACTERISTICS
TPS76533
OUTPUT VOLTAGE
vs
TPS76515
OUTPUT VOLTAGE
vs
LOAD CURRENT
LOAD CURRENT
3.304
3.302
3.300
3.298
3.296
3.294
3.292
1.494
1.493
1.492
1.491
1.490
1.489
1.488
1.487
V = 4.3 V
V = 2.7 V
I
A
I
T
A
= 25°C
T = 25°C
0
25
50
75
100
125
150
0
25
50
75
100
125
150
I
L
– Load Current – mA
I
L
– Load Current – mA
Figure 2
Figure 3
TPS76533
TPS76515
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
3.310
1.505
1.500
1.495
1.490
V = 4.3 V
I
V = 2.7 V
I
I
O
= 10 µA
I
O
= 10 µA
3.305
3.300
I
O
= 150 mA
3.295
3.290
I
O
= 150 mA
3.285
3.280
1.485
1.480
1.475
3.275
3.270
3.265
–50 –25
0
25
50
75 100 125 150
–50 –25
0
25
50
75
100 125
150
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 4
Figure 5
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
TYPICAL CHARACTERISTICS
TPS76533
GROUND CURRENT
vs
TPS76515
GROUND CURRENT
vs
LOAD CURRENT
LOAD CURRENT
35.0
34.9
34.8
34.7
34.6
34.5
34.4
34.3
34.2
34.1
34.0
34.0
33.9
33.8
33.7
33.6
33.5
33.4
33.3
33.2
33.1
33.0
V
T
= 3.3 V
= 25°C
O
A
V
T
A
= 1.5 V
= 25°C
O
0
25
50
75
100
125
150
0
25
50
75
100
125
150
I
L
– Load Current – mA
I
L
– Load Current – mA
Figure 6
Figure 7
TPS76533
TPS76515
GROUND CURRENT
vs
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
55
55
50
45
40
35
30
25
20
15
50
45
40
35
30
25
20
15
10
V
= 3.3 V
= 150 mA
V
= 1.5 V
O
O
I
O
I
O
= 150 mA
0
–50
0
50
100
150
–50
50
100
150
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 8
Figure 9
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
TYPICAL CHARACTERISTICS
TPS76533
TPS76533
POWER SUPPLY RIPPLE REJECTION
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
1
0
70
60
50
40
30
20
10
10
V = 4.3 V
I
I
= 150 mA
O
C
= 10 µF
= 150 mA
= 25°C
O
I
O
T
A
I
= 1 mA
O
10
–1
10
10
V = 4.3 V
I
O
A
C
T
= 10 µF
= 25°C
–2
10
10
100
1k
10k
100k
1M
10M
100
1k
10k
100k
f – Frequency – Hz
f – Frequency – Hz
Figure 10
Figure 11
TPS76533
OUTPUT IMPEDANCE
vs
FREQUENCY
1
0
10
V = 4.3 V
I
C
T
= 10 µF
= 25°C
O
A
10
I
O
= 1 mA
–1
10
10
I
O
= 150 mA
–2
10
100
1k
10k
100k
1M
f – Frequency – Hz
Figure 12
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS76515, TPS76518, TPS76525, TPS76527
TPS76528, TPS76530, TPS76533, TPS76550, TPS76501
ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
TYPICAL CHARACTERISTICS
TPS76550
DROPOUT VOLTAGE
vs
TPS76533
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0
10
0
10
V = 4.9 V
I
V = 3.2 V
I
C
= 4.7 µF
O
I
O
= 150 mA
I
= 150 mA
–1
10
–2
10
–3
10
O
–1
10
I
O
= 50 mA
I
O
= 50 mA
I
O
= 10 mA
–2
10
I
O
= 10 mA
–3
10
–50 –25
0
25
50
75
100 125 150
–50 –25
0
25
50
75
100 125 150
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 13
Figure 14
TPS76515
TPS76515
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
400
C
T
= 4.7 µF
= 25°C
L
A
C
T
A
= 4.7 µF
= 25°C
L
100
50
0
200
0
–200
–400
–50
150
3.7
2.7
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
t – Time – µs
Figure 15
Figure 16
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ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
SLVS236 – AUGUST 1999
TYPICAL CHARACTERISTICS
TPS76533
TPS76533
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
400
C
T
= 4.7 µF
= 25°C
L
A
C
T
A
= 4.7 µF
= 25°C
L
100
50
200
0
0
–50
–200
150
0
–100
5.3
4.3
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
t – Time – µs
Figure 17
Figure 18
TPS76533
OUTPUT VOLTAGE
vs
TPS76501
DROPOUT VOLTAGE
vs
TIME (AT STARTUP)
INPUT VOLTAGE
4
0.30
0.25
0.20
0.15
0.10
0.05
0.00
I
O
= 150 mA
3
2
1
T
A
= 125°C
0
T
A
= 25°C
4.3
0
T
A
= –40°C
2.5
3.0
3.5
4.0
4.5
5.0
0
100 200 300 400 500 600 700 800 900 1000
t – Time – µs
V – Input Voltage – V
I
Figure 19
Figure 20
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ULTRA-LOW QUIESCIENT CURRENT 150-mA LOW-DROPOUT VOLTAGE REGULATORS
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TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
†
†
OUTPUT CURRENT
OUTPUT CURRENT
2
2
10
10
Maximum ESR
Maximum ESR
Region of Instability
Region of Instability
1
1
10
10
Region of Stability
Region of Stability
V = 4.3 V
I
0
0
10
10
C
= 4.7 µF
= 3.3 V
= 25°C
O
O
A
V
T
V = 4.3 V
I
C
= 4.7 µF
= 3.3 V
O
O
Minimum ESR
V
T
–1
10
–1
10
= 125°C
A
Minimum ESR
Region of Instability
Region of Instability
75 100 125 150
–2
–2
10
10
0
25
50
75
100
125
150
0
25
50
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 21
Figure 22
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
†
†
EQUIVALENT SERIES RESISTANCE
vs
OUTPUT CURRENT
OUTPUT CURRENT
2
100
10
2
10
Maximum ESR
Maximum ESR
Region of Instability
Region of Instability
1
10
1
10
Region of Stability
0
0
10
10
V = 4.3 V
V = 4.3 V
Region of Stability
Minimum ESR
I
O
O
A
I
C
V
T
= 10 µF
= 3.3 V
= 125°C
C
V
= 10 µF
= 3.3 V
= 25°C
O
O
A
T
–1
–1
10
10
Minimum ESR
Region of Instability
Region of Instability
––22
10
–2
10
0
25
50
75
100
125
150
0
25
50
75
100
125
150
I
O
– Output Current – mA
I
O
– Output Current – mA
Figure 23
Figure 24
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C
.
O
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SLVS236 – AUGUST 1999
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE
vs
†
†
ADDED CERAMIC CAPACITANCE
ADDED CERAMIC CAPACITANCE
1
1
10
10
V = 4.3 V
V = 4.3 V
I
I
C
= 4.7 µF
= 3.3 V
= 25°C
V
O
= 3.3 V
= 10 µF
= 25°C
O
O
A
V
T
C
T
O
A
I
O
= 150 mA
I
O
= 150 mA
0
10
0
10
–1
–1
10
10
Minimum ESR
Region of Instability
Minimum ESR
Region of Instability
0.4 0.6
–2
10
–2
10
0
0.2
0.4
0.6
0.8
1.0
0
0.2
0.8
1.0
Added Ceramic Capacitance – µF
Added Ceramic Capacitance – µF
Figure 25
Figure 26
To Load
IN
V
I
OUT
+
C
O
R
EN
L
GND
ESR
Figure 27. Test Circuit for Typical Regions of Stability (Figures 20 through 23) (Fixed Output Options)
†
Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to C
.
O
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APPLICATION INFORMATION
The TPS765xx family includes eight fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3.0 V,
3.3 V, and 5.0 V), and an adjustable regulator, the TPS76501 (adjustable from 1.25 V to 5.5 V).
device operation
The TPS765xx features very low quiescent current, which remains virtually constant even with varying loads.
Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the
load current through the regulator (I = I /β). The TPS765xx uses a PMOS transistor to pass current; because
B
C
the gate of the PMOS is voltage driven, operating current is low and invariable over the full load range.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in I to maintain the load. During power up, this translates
B
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS765xx quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS765xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to 1 µA (typ). If the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage is reestablished in typically 160 µs.
minimum load requirements
The TPS765xx family is stable even at zero load; no minimum load is required for operation.
FB - pin connection (adjustable version only)
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option . The output
voltage is sensed through a resistor divider network to close the loop as it is shown in Figure 29. Normally, this
connection should be as short as possible; however, the connection can be made near a critical circuit to
improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and
noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup
is essential.
external capacitor requirements
An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 µF or larger) improves
load transient response and noise rejection if the TPS765xx is located more than a few inches from the power
supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
Like all low dropout regulators, the TPS765xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance value is 4.7 µF and the ESR
(equivalent series resistance) must be between 300-mΩ and 20-Ω. Capacitor values 4.7 µF or larger are
acceptable, provided the ESR is less than 20Ω. Solidtantalumelectrolytic, aluminumelectrolytic, andmultilayer
ceramic capacitors are all suitable, provided they meet the requirements described previously.
14
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APPLICATION INFORMATION
external capacitor requirements (continued)
TPS765xx
5
6
2
1
7
8
V
IN
IN
PG
PG
I
NC/FB
250 kΩ
OUT
OUT
V
O
4
0.1 µF
EN
C
O
+
4.7 µF
GND
3
300 mΩ
Figure 28. Typical Application Circuit (Fixed Versions)
programming the TPS76501 adjustable LDO regulator
The output voltage of the TPS76501 adjustable regulator is programmed using an external resistor divider as
shown in Figure 29. The output voltage is calculated using:
R1
R2
(1)
V
V
1
O
ref
Where
V
= 1.224 V typ (the internal reference voltage)
ref
Resistors R1 and R2 should be chosen for approximately 7-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 169 kΩ to set the divider current at 7 µA and then calculate R1 using:
V
O
R1
1
R2
(2)
V
ref
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS76501
OUTPUT
VOLTAGE
R1
R2
UNIT
V
I
IN
PG
OUT
PG
0.1 µF
≤ 0.8 V
2.5 V
3.3 V
3.6 V
4.0 V
5.0 V
174
287
324
383
523
169
169
169
169
169
kΩ
kΩ
kΩ
kΩ
kΩ
250 kΩ
≥ 2.0 V
EN
V
O
R1
R2
C
O
FB / NC
GND
300 mΩ
Figure 29. TPS76501 Adjustable LDO Regulator Programming
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APPLICATION INFORMATION
power-good indicator
The TPS765xx features a power-good (PG) output that can be used to monitor the status of the regulator. The
internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal
regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup
resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or used as a
low-battery indicator.
regulator protection
The TPS765xx PMOS-pass transistor has a built-in back diode that conducts reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS765xx also features internal current limiting and thermal protection. During normal operation, the
TPS765xxlimitsoutputcurrenttoapproximately0.8A. Whencurrentlimitingengages, theoutputvoltagescales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below
130°C(typ), regulator operation resumes.
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, P
, and the actual dissipation, P , which must be less than
D(max)
D
or equal to P
.
D(max)
The maximum-power-dissipation limit is determined using the following equation:
T max
J
T
A
P
D(max)
R
JA
Where
T max is the maximum allowable junction temperature
J
R
SOIC.
is the thermal resistance junction-to-ambient for the package, i.e., 176°C/W for the 8-terminal
θJA
T is the ambient temperature.
A
The regulator dissipation is calculated using:
P
V
V
I
D
I
O
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
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MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad.
E. Falls within JEDEC MS-012
17
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