TPS77625_15 [TI]
TPS775xx with RESET Output, TPS776xx with PG Output FAST-TRANSIENT-RESPONSE 500mA LOW-DROPOUT VOLTAGE REGULATORS;
| 型号： | TPS77625_15 |
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TEXAS INSTRUMENTS |
| 描述： | TPS775xx with RESET Output, TPS776xx with PG Output FAST-TRANSIENT-RESPONSE 500mA LOW-DROPOUT VOLTAGE REGULATORS |
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TPS775xx, TPS776xx
www.ti.com .............................................................................................................................................. SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009
TPS775xx with RESET Output, TPS776xx with PG Output
FAST-TRANSIENT-RESPONSE 500mA LOW-DROPOUT VOLTAGE REGULATORS
1
FEATURES
DESCRIPTION
23
•
Open Drain Power-On Reset with 200ms Delay
(TPS775xx)
The TPS775xx and TPS776xx devices are designed
to have a fast transient response and be stable with a
10µF low ESR capacitor. This combination provides
high performance at a reasonable cost.
•
•
•
Open Drain Power Good (TPS776xx)
500mA Low-Dropout Voltage Regulator
Because the PMOS device behaves as a low-value
resistor, the dropout voltage is very low (typically
169mV at an output current of 500mA for the
TPS77x33) and is directly proportional to the output
current. Additionally, since the PMOS pass element is
a voltage-driven device, the quiescent current is very
low and independent of output loading (typically 85µA
over the full range of output current, 0mA to 500mA).
These two key specifications yield a significant
improvement in operating life for battery-powered
systems. This LDO family also features a sleep
mode; applying a TTL high signal to EN (enable)
shuts down the regulator, reducing the quiescent
current to 1µA at TJ = +25°C.
Available in Fixed Output and Adjustable
Versions
•
Dropout Voltage to 169mV (Typ) at 500mA
(TPS77x33)
•
•
•
Ultralow 85µA Typical Quiescent Current
Fast Transient Response
2% Tolerance Over Specified Conditions for
Fixed-Output Versions
•
•
8-Pin SOIC and 20-Pin TSSOP PowerPAD™
(PWP) Packages
Thermal Shutdown Protection
The RESET output of the TPS775xx initiates a reset
in microcomputer and microprocessor systems in the
event of an undervoltage condition. An internal
comparator in the TPS775xx monitors the output
voltage of the regulator to detect an undervoltage
condition on the regulated output voltage.
APPLICATIONS
•
FPGA Power
•
DSP Core and I/O Voltages
Typical Application Circuit
(Fixed Voltage Options)
Power good (PG) of the TPS776xx is an active high
output, which can be used to implement a power-on
reset or a low-battery indicator.
6
7
16
RESET/
PG
VIN
IN
IN
RESET/PG
14
13
The TPS775xx and TPS776xx are offered in 1.5V,
1.6V (TPS77516 only), 1.8V, 2.5V, 2.8V (TPS77628
only), and 3.3V fixed-voltage versions and in an
adjustable version (programmable over the range of
1.5V to 5.5V for the TPS77501 and 1.2V to 5.5V for
the TPS77601). Output voltage tolerance is specified
as a maximum of 2% over line, load, and temperature
ranges. The TPS775xx and TPS776xx families are
available in 8-pin SOIC and 20-pin TSSOP packages.
VOUT
OUT
OUT
0.1mF
5
EN
(1)
COUT
+
10mF
GND
3
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2009, Texas Instruments Incorporated
TPS775xx, TPS776xx
SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009.............................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS775xxyyyz, TPS776xxyyyz
XX is nominal output voltage (for example, 28 = 2.8V, 285 = 2.85V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Custom fixed output voltages are available; minimum order quantities may apply. Contact factory for details and availability.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature range (unless otherwise noted)(1)
PARAMETER
TPS775xx, TPS776xx
UNIT
(2)
Input voltage range, VIN
Voltage range at EN
–0.3 to +13.5
–0.3 to +16.5
16.5
V
V
V
V
Maximum RESET voltage (TPS775xx)
Maximum PG voltage (TPS776xx)
Peak output current
16.5
Internally limited
7
Voltage range at OUT, FB
V
Continuous total power dissipation
Operating junction temperature range, TJ
Storage junction temperature range , TSTG
ESD rating, HBM
See Dissipation Ratings Table
–40 to +125
–65 to +150
2
°C
°C
kV
(1) Stresses above these ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those specified is not implied.
(2) All voltages are with respect to network terminal ground.
DISSIPATION RATINGS
AIRFLOW
(CFM)
DERATING FACTOR
ABOVE TA = +25°C
BOARD
PACKAGE
TA < +25°C (mW)
TA = +70°C (mW)
TA = +85°C (mW)
0
250
0
568
904
5.68mW/°C
9.04mW/°C
23.5mW/°C
34.6mW/°C
23.8mW/°C
57.9mW/°C
312
497
227
362
—
D
2350
3460
2380
5790
1300
1900
1300
3200
940
Low-K(1)
High-K(2)
PWP
PWP
300
0
1400
952
300
2300
(1) This parameter is measured with the recommended copper heat sink pattern on a 1-layer, 5in × 5in printed circuit board (PCB), 1-ounce
copper, 2in × 2in coverage (4in2).
(2) This parameter is measured with the recommended copper heat sink pattern on a 8-layer, 1.5in × 2in PCB, 1-ounce copper with layers
1, 2, 4, 5, 7, and 8 at 5% coverage (0.9in2) and layers 3 and 6 at 100% coverage (6in2). For more information, refer to TI technical brief
SLMA002.
2
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TPS775xx, TPS776xx
www.ti.com .............................................................................................................................................. SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(TYP) + 1V; IOUT = 1mA, VEN = 0V, COUT
=
10µF, unless otherwise noted. Typical values are at TJ = +25°C.
PARAMETER
TEST CONDITIONS
MIN
2.7
1.5
1.2
TYP
MAX
10
UNIT
VIN
Input voltage range
V
V
V
TPS77501
TPS77601
5.5
5.5
VOUT
Output voltage range
Accuracy
VOUT + 1V ≤ VIN ≤ 10V(1)
10µA < IOUT < 500mA
VOUT
–2.0
+2.0
%
IOUT = 10mA
85
IGND
Ground pin current
µA
IOUT = 500mA
125
ΔVOUT%/ ΔVIN
ΔVOUT%/ ΔIOUT
Output voltage line regulation
Load regulation
VOUT + 1V ≤ VIN ≤ 10V(1)
0.01
3
%/V
mV
Output noise voltage
BW = 200Hz to 100kHz
VN
TPS77x18
IC = 500mA, COUT = 10µF
53
µVRMS
TPS77628
TPS77533
TPS77633
IOUT = 500mA
IOUT = 500mA
IOUT = 500mA
VOUT = 0V
285
169
169
1.6
410
287
287
1.9
mV
mV
mV
A
VDO
Dropout voltage(2)
ICL
TSD
TJ
Output current limit
1.2
Shutdown temperature
150
°C
Operating junction temperature range
–40
+125
10
°C
EN = VIN, at TJ = +25°C,
2.7V < VIN < 10V
1
2
ISTBY
Standby current
µA
EN = VIN, 2.7V < VIN < 10V
FB = 1.5V
IFB
FB input current
TPS77x01
nA
V
VEN(HI)
VEN(LO)
PSRR
High-level enable input voltage
Low-level enable input voltage
Power-supply ripple rejection
Minimum input voltage for valid RESET
Trip threshold voltage
1.7
92
0.9
98
V
f = 100Hz, COUT = 10µF
IOUT(RESET) = 300µA
VOUT decreasing
60
dB
V
1.1
%VOUT
%VOUT
V
Hysteresis voltage
Measured at VOUT
0.5
RESET
(TPS775xx)
Output low voltage
VIN = 2.7V, IOUT(RESET) = 1mA
V(RESET) = 5V
0.15
0.4
1
Leakage current
µA
RESET time-out delay
Minimum input voltage for valid PG
Trip threshold voltage
200
1.1
ms
IOUT(PG) = 300µA
VOUT decreasing
Measured at VOUT
VIN = 2.7V, IOUT(PG) = 1mA
V(PG) = 5V
V
92
98
%VOUT
%VOUT
V
PG
(TPS776xx)
Hysteresis voltage
0.5
Output low voltage
0.15
0.4
1
Leakage current
µA
EN = 0V
–1
–1
0
1
Input current (EN)
µA
EN = VIN
1
(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater.
(2) VDO is not measured for fixed output versions with VOUT(NOM) < 2.8 V because mimimum VIN = 2.7V.
Copyright © 1999–2009, Texas Instruments Incorporated
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SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009.............................................................................................................................................. www.ti.com
FUNCTIONAL BLOCK DIAGRAMS
Adjustable Voltage Versions
IN
EN
PG or RESET
_
+
OUT
+
200ms Delay
(for RESET Option)
R1
_
Vref = 1.183V
FB/NC
R2
GND
External to the device
Fixed Voltage Versions
IN
EN
PG or RESET
_
+
OUT
+
_
200ms Delay
(for RESET Option)
R1
Vref = 1.183V
R2
GND
4
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Copyright © 1999–2009, Texas Instruments Incorporated
TPS775xx, TPS776xx
www.ti.com .............................................................................................................................................. SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009
PIN CONFIGURATIONS
TSSOP-20
PWP
SOIC-8
D
(TOP VIEW)
(TOP VIEW)
GND/HSINK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND/HSINK
GND/HSINK
NC
GND
1
RESET/PG
8
7
6
5
GND/HSINK
EN
IN
2
3
FB/NC
OUT
GND
NC
NC
IN
4
OUT
EN
RESET/PG
FB/NC
IN
IN
OUT
NC
OUT
GND/HSINK
GND/HSINK
GND/HSINK
GND/HSINK
Table 1. PIN DESCRIPTIONS
TPS775xx, TPS776xx
TSSOP-20
(PWP)
PIN NO.
SOIC-8 (D)
PIN NO.
NAME
DESCRIPTION
EN
2
5
Negative polarity enable (EN) input
Adjustable voltage version only; feedback voltage for setting output voltage of the device.
Not internally connected on adjustable versions.
FB
7
15
1, 2, 3, 9, 10,
GND
1
11, 12, 19, Ground
20
IN
OUT
3, 4
5, 6
8
6, 7
13, 14
16
Input voltage
Regulated output voltage
RESET
PG
TPS775xx devices only; open-drain RESET output.
TPS776xx devices only; open-drain power-good (PG) output.
8
16
NC
—
—
4, 8, 17, 18 No internal connection
Should be soldered to ground plane and used for heat sinking.
PAD/TAB
—
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TPS775xx, TPS776xx
SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009.............................................................................................................................................. www.ti.com
TPS775xx RESET Timing Diagram
VIN
(1)
(1)
Vres
Vres
t
(2)
(2)
VOUT
VIT+
VIT+
Threshold
Voltage
Less than 5% of the
output voltage
(2)
VIT-
(2)
VIT-
t
RESET
Output
200ms Delay
200ms Delay
Output
Undefined
Output
Undefined
t
(1) Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
(2) VIT: Trip voltage is typically 5% lower than the output voltage (95% VOUT). VIT– to VIT+ is the hysteresis voltage.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE NO.
vs Output Current
vs Free-Air Temperature
vs Time
Figure 3, Figure 4, Figure 5
VOUT
Output Voltage
Figure 6, Figure 7, Figure 8
Figure 20
IGND
Ground Current
vs Free-Air Temperature
vs Frequency
Figure 9
PSRR
Power-Supply Ripple Rejection
Output Spectral Noise Density
Output Impedance
Figure 10
vs Frequency
Figure 11
ZOUT
VDO
vs Frequency
Figure 12
vs Input Voltage
vs Free-Air Temperature
vs Output Voltage
Figure 13
Dropout Voltage
Figure 14
VIN
LINE
LOAD
ESR
Input Voltage (Min)
Line Transient Response
Load Transient Response
Equivalent Series Resistance
Figure 15
Figure 16, Figure 18
Figure 17, Figure 19
Figure 22, Figure 23
vs Output Current
6
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Copyright © 1999–2009, Texas Instruments Incorporated
TPS775xx, TPS776xx
www.ti.com .............................................................................................................................................. SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009
TYPICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C.
TPS77x33
OUTPUT VOLTAGE
vs OUTPUT CURRENT
TPS77x15
OUTPUT VOLTAGE
vs OUTPUT CURRENT
3.2835
3.2830
3.2825
3.2820
3.2815
3.2810
1.4985
1.4980
1.4975
1.4970
1.4965
1.4960
VIN = 4.3V
VIN = 2.7V
TA = +25°C
TA = +25°C
3.2805
3.2800
1.4955
1.4950
0.0
0.1
0.2
0.3
0.4
0.5
0.0
0.1
0.2
0.3
0.4
0.5
IOUT - Output Current - A
IOUT - Output Current - A
Figure 3.
Figure 4.
TPS77x25
OUTPUT VOLTAGE
vs OUTPUT CURRENT
TPS77x33
OUTPUT VOLTAGE
vs FREE-AIR TEMPERATURE
2.4960
2.4955
2.4950
2.4945
3.32
3.31
3.30
3.29
3.28
3.27
VIN = 3.5V
VIN = 4.3V
TA = +25°C
IOUT = 500mA
2.4940
2.4935
2.4930
IOUT = 1mA
3.26
3.25
2.4925
2.4920
0.0
0.1
0.2
0.3
0.4
0.5
-60 -40 -20
0
20
40
60 80 100 120 140
IOUT - Output Current - A
TA - Free-Air Temperature - °C
Figure 5.
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C.
TPS77x15
TPS77x25
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs FREE-AIR TEMPERATURE
vs FREE-AIR TEMPERATURE
1.515
1.510
2.515
VIN = 3.5V
VIN = 2.7V
2.510
2.505
2.500
2.495
1.505
1.500
1.495
1.490
1.485
IOUT = 500mA
IOUT = 500mA
IOUT = 1mA
IOUT = 1mA
2.490
2.485
2.480
-60 -40 -20
0
20
40
60 80 100 120 140
-60 -40 -20
0
20
40
60 80 100 120 140
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 7.
Figure 8.
TPS77xxx
TPS77x33
POWER-SUPPLY RIPPLE REJECTION
vs FREQUENCY
GROUND CURRENT
vs FREE-AIR TEMPERATURE
90
100
95
VIN = 4.3V
VIN = 2.7V
80
70
COUT = 10mF
TA = +25°C
60
50
40
90
IOUT = 1mA
30
20
85
80
75
IOUT = 500mA
10
0
-10
103
101
102
104
105
106
-60 -40 -20
0
20
40
60 80 100 120 140
TA - Free-Air Temperature - °C
f - Frequency - Hz
Figure 9.
Figure 10.
8
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TPS775xx, TPS776xx
www.ti.com .............................................................................................................................................. SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009
TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C.
TPS77x33
OUTPUT SPECTRAL NOISE DENSITY
vs FREQUENCY
TPS77x33
OUTPUT IMPEDANCE
vs FREQUENCY
100
10-5
10-6
10-7
10-8
VIN = 4.3V
VIN = 4.3V
COUT = 10mF
COUT = 10mF
TA = +25°C
TA = +25°C
IOUT = 7mA
IOUT = 1mA
10-1
IOUT = 500mA
IOUT = 500mA
10-2
101
102
103
104
105
103
102
104
105
106
f - Frequency - Hz
f - Frequency - Hz
Figure 11.
Figure 12.
TPS77x01
DROPOUT VOLTAGE
vs INPUT VOLTAGE
TPS77x33
DROPOUT VOLTAGE
vs FREE-AIR TEMPERATURE
103
350
300
250
200
150
100
IOUT = 500mA
COUT = 10mF
102
IOUT = 500mA
TA = +125°C
101
TA = +25°C
IOUT = 10mA
100
TA = -40°C
10-1
50
0
IOUT = 0mA
10-2
-60 -40 -20
2.5
3.0
3.5
4.0
4.5
5.0
0
20
40
60 80 100 120 140
VIN - Input Voltage - V
T
A - Free-Air Temperature - °C
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C.
INPUT VOLTAGE (MIN)
vs OUTPUT VOLTAGE
TPS77x15
LINE TRANSIENT RESPONSE
4
IOUT = 0.5A
3.7
2.7
TA = +25°C
TA = +125°C
3
TA = -40°C
10
0
2.7
COUT = 10 F
TA = +25°C
-10
2
1.50 1.75
2.0
2.25 2.50 2.75
VOUT - Output Voltage - V
Figure 15.
3.0
3.25
3.5
0
20
40
60
80 100 120 140 160 180 200
t - Time -
s
Figure 16.
TPS77x15
LOAD TRANSIENT RESPONSE
TPS77x33
LINE TRANSIENT RESPONSE
COUT = 2x47 F
COUT = 10 F
TA = +25°C
ESR = 1/2x100m
VOUT = 1.5V
50
VIN = 2.7V
0
5.3
4.3
-50
10
0
500
0
-10
0
20
40
60
80 100 120 140 160 180 200
0
20
40
60
80 100 120 140 160 180 200
t - Time -
s
t - Time - s
Figure 17.
Figure 18.
10
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C.
TPS77x33
LOAD TRANSIENT RESPONSE
TPS77x33OUTPUT VOLTAGE
vs TIME (AT STARTUP)
4
COUT = 2x47 F
COUT = 10 F
ESR = 1/2x100m
VOUT = 3.3V
IOUT = 500mA
TA = +25°C
50
0
3
2
VIN = 4.3V
-50
1
0
500
0
0
20
40
60
80 100 120 140 160 180 200
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
t - Time -
s
t - Time - ms
Figure 19.
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
Over operating temperature range (TJ= –40°C to +125°C) unless otherwise noted. Typical values are at TJ = +25°C.
Test Circuit for Typical Regions of Stability (Figure 22 and Figure 23) (Fixed Output Options)
To Load
VIN
IN
OUT
+
RL
COUT
ESR
EN
R
GND
Figure 21.
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE(1)
vs OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE(1)
vs OUTPUT CURRENT
10
10
Region of Instability
Region of Instability
1
1
VOUT = 3.3V
COUT = 22 F
VIN = 4.3V
VOUT = 3.3V
COUT = 22 F
VIN = 4.3V
Region of Stability
Region of Stability
TJ = +125°C
TA = +25°C
0.1
0.1
Region of Instability
Region of Instability
0.01
0.01
0
100
200
300
400
500
0
100
200
300
400
500
IOUT - Output Current - mA
IOUT - Output Current - mA
(1) Equivalent series resistance (ESR) refers to
the total series resistance, including the ESR
of the capacitor, any series resistance added
(1) Equivalent series resistance (ESR) refers to
the total series resistance, including the ESR
of the capacitor, any series resistance added
externally, and PWB trace resistance to COUT
.
externally, and PWB trace resistance to COUT.
Figure 22.
Figure 23.
12
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APPLICATION INFORMATION
The TPS775xx and TPS776xx feature very low quiescent current, which remains virtually constant even with
varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is directly
proportional to the load current through the regulator (IB = IC/β). The TPS775xx and TPS776xx use a PMOS
transistor to pass current; because the gate of the PMOS is voltage driven, operating current is low and
invariable over the full load range.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this IB increase
translates to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered
systems, it means rapid battery discharge when the voltage decays below the minimum required for regulation.
The TPS775xx and TPS776xx quiescent currents remain low even when the regulator drops out, eliminating both
problems.
The TPS775xx and TPS776xx families also feature a shutdown mode that places the output in the
high-impedance state (essentially equal to the feedback-divider resistance) and reduces quiescent current to
2µA. If the shutdown feature is not used, EN should be tied to ground.
Minimum Load Requirements
The TPS775xx and TPS776xx families are stable at zero load; no minimum load is required for operation.
FB—Pin Connection (Adjustable Version Only)
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option. The output
voltage is sensed through a resistor divider network to close the loop as it is shown in Figure 25. Normally, this
connection should be as short as possible; however, the connection can be made near a critical circuit to
improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and
noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup is
essential.
External Capacitor Requirements
An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047µF or larger) improves
load transient response and noise rejection if the TPS775xx or TPS776xx are located more than a few inches
from the power supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of
milliamps) load transients with fast rise times are anticipated.
Like all low dropout regulators, the TPS775xx and TPS776xx require an output capacitor connected between
OUT and GND to stabilize the internal control loop. The minimum recommended capacitance value is 10µF and
the ESR (equivalent series resistance) must be between 50mΩ and 1.5Ω. Capacitor values 10µF or larger are
acceptable, provided the ESR is less than 1.5Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer
ceramic capacitors are all suitable, provided they meet the requirements described previously.
6
7
16
RESET/
PG
VIN
IN
IN
RESET/PG
250kW
VOUT
14
13
OUT
OUT
C1
0.1mF
5
EN
COUT
10mF
+
GND
3
Figure 24. Typical Application Circuit (Fixed Versions)
Copyright © 1999–2009, Texas Instruments Incorporated
Submit Documentation Feedback
13
TPS775xx, TPS776xx
SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009.............................................................................................................................................. www.ti.com
Programming the TPS77x01 Adjustable LDO Regulator
The output voltage of the TPS77x01 adjustable regulator is programmed using an external resistor divider as
shown in Figure 25. The output voltage is calculated using Equation 1:
R1
VOUT = Vref x (1 +
)
R2
(1)
Where:
•
Vref = 1.1834V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 10µA divider current. Lower value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose R2 = 110kΩ
to set the divider current at approximately 10µA and then calculate R1 using Equation 2:
VOUT
R1 = (
- 1) x R2
Vref
(2)
TPS77x01
OUTPUT VOLTAGE
PROGRAMMING GUIDE
RESET/
PG
OUTPUT
VIN
RESET or PG Output
IN
VOLTAGE
R1
R2
UNIT
0.1mF
250kW
2.5V
121
196
226
332
110
110
110
110
kW
kW
kW
kW
3.3V
VOUT
OUT
> 1.7V
3.6V
R1
R2
EN
4.75V
< 0.9V
FB/NC
COUT
GND
Figure 25. TPS77x01 Adjustable LDO Regulator Programming
Reset Indicator
The TPS775xx features a RESET output that can be used to monitor the status of the regulator. The internal
comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal
regulated value, the RESET output transistor turns on, taking the signal low. The open-drain output requires a
pullup resistor. If not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as a
low-battery indicator. RESET does not assert itself when the regulated output voltage falls outside the specified
2% tolerance, but instead reports an output voltage low relative to its nominal regulated value (refer to Timing
Diagram for start-up sequence).
Power-Good Indicator
The TPS776xx features a power-good (PG) output that can be used to monitor the status of the regulator. The
internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal
regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pullup
resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or used as a
low-battery indicator.
14
Submit Documentation Feedback
Copyright © 1999–2009, Texas Instruments Incorporated
TPS775xx, TPS776xx
www.ti.com .............................................................................................................................................. SLVS232J–SEPTEMBER 1999–REVISED MARCH 2009
Regulator Protection
The TPS775xx and TPS776xx PMOS-pass transistors have a built-in back diode that conducts reverse currents
when the input voltage drops below the output voltage (for example, during power down). Current is conducted
from the output to the input and is not internally limited. When extended reverse voltage is anticipated, external
limiting may be appropriate.
The TPS775xx and TPS776xx also feature internal current limiting and thermal protection. During normal
operation, the TPS775xx and TPS776xx limit output current to approximately 1.7A. When current limiting
engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is
designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the
package. If the temperature of the device exceeds +150°C(typ), thermal-protection circuitry shuts it down. Once
the device has cooled below +130°C(typ), regulator operation resumes.
Power Dissipation and Junction Temperature
Specified regulator operation is assured to a junction temperature of +125°C; the maximum junction temperature
should be restricted to +125°C under normal operating conditions. This restriction limits the power dissipation the
regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than or
equal to PD(max)
.
The maximum-power-dissipation limit is determined using the following equation:
T
J(max) - TA
PD(max)
=
RqJA
where:
•
•
TJ(max) is the maximum allowable junction temperature
θJA is the thermal resistance junction-to-ambient for the package, and is calculated as
R
1
derating factor
from the dissipation rating tables
TA is the ambient temperature
•
The regulator dissipation is calculated using:
PD = (VIN - VOUT) x IOUT
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
Copyright © 1999–2009, Texas Instruments Incorporated
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
PACKAGING INFORMATION
Orderable Device
TPS77501D
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
77501
77501
77501
77501
TPS77501DG4
TPS77501DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
2500
2500
70
Green (RoHS
& no Sb/Br)
SOIC
8
Green (RoHS
& no Sb/Br)
TPS77501DRG4
TPS77501PWP
TPS77501PWPG4
TPS77501PWPR
TPS77501PWPRG4
TPS77515D
SOIC
D
8
Green (RoHS
& no Sb/Br)
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
PWP
PWP
PWP
D
20
20
20
20
8
Green (RoHS
& no Sb/Br)
PT77501
PT77501
PT77501
PT77501
77515
70
Green (RoHS
& no Sb/Br)
2000
2000
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS77515DG4
TPS77515DR
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
77515
SOIC
D
8
2500
2500
70
Green (RoHS
& no Sb/Br)
77515
TPS77515DRG4
TPS77515PWP
TPS77515PWPR
TPS77516D
SOIC
D
8
Green (RoHS
& no Sb/Br)
77515
HTSSOP
HTSSOP
SOIC
PWP
PWP
D
20
20
8
Green (RoHS
& no Sb/Br)
PT77515
PT77515
77516
2000
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS77516DG4
TPS77516DR
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
-40 to 85
77516
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
-40 to 85
77516
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TPS77516PWP
TPS77516PWPG4
TPS77516PWPR
TPS77516PWPRG4
TPS77518D
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
20
20
20
20
8
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
PT77516
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
PWP
D
70
2000
2000
75
Green (RoHS
& no Sb/Br)
-40 to 85
PT77516
PT77516
PT77516
77518
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS77518DG4
TPS77518DR
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
77518
SOIC
D
8
2500
70
Green (RoHS
& no Sb/Br)
77518
TPS77518PWP
TPS77518PWPG4
TPS77518PWPR
TPS77518PWPRG4
TPS77525D
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
PWP
PWP
PWP
D
20
20
20
20
8
Green (RoHS
& no Sb/Br)
PT77518
PT77518
PT77518
PT77518
77525
70
Green (RoHS
& no Sb/Br)
2000
2000
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS77525DG4
TPS77525DR
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
77525
SOIC
D
8
2500
70
Green (RoHS
& no Sb/Br)
77525
TPS77525PWP
TPS77525PWPG4
TPS77533D
HTSSOP
HTSSOP
SOIC
PWP
PWP
D
20
20
8
Green (RoHS
& no Sb/Br)
PT77525
PT77525
77533
70
Green (RoHS
& no Sb/Br)
75
Green (RoHS
& no Sb/Br)
TPS77533DG4
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
77533
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TPS77533DR
TPS77533DRG4
TPS77533PWP
TPS77533PWPG4
TPS77533PWPR
TPS77533PWPRG4
TPS77601D
ACTIVE
SOIC
SOIC
D
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
77533
77533
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
PWP
PWP
PWP
PWP
D
2500
70
Green (RoHS
& no Sb/Br)
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
20
20
20
20
8
Green (RoHS
& no Sb/Br)
PT77533
PT77533
PT77533
PT77533
77601
70
Green (RoHS
& no Sb/Br)
2000
2000
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS77601DG4
TPS77601DR
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
77601
SOIC
D
8
2500
2500
70
Green (RoHS
& no Sb/Br)
77601
TPS77601DRG4
TPS77601PWP
TPS77601PWPG4
TPS77601PWPR
TPS77601PWPRG4
TPS77615D
SOIC
D
8
Green (RoHS
& no Sb/Br)
77601
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
PWP
PWP
PWP
D
20
20
20
20
8
Green (RoHS
& no Sb/Br)
PT77601
PT77601
PT77601
PT77601
77615
70
Green (RoHS
& no Sb/Br)
2000
2000
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS77615DG4
TPS77615DR
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
77615
SOIC
D
8
2500
2500
Green (RoHS
& no Sb/Br)
77615
TPS77615DRG4
SOIC
D
8
Green (RoHS
& no Sb/Br)
77615
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TPS77615PWP
TPS77618D
ACTIVE
HTSSOP
SOIC
PWP
20
8
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
PT77615
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
75
Green (RoHS
& no Sb/Br)
77618
TPS77618DG4
TPS77618DR
SOIC
8
Green (RoHS
& no Sb/Br)
77618
SOIC
D
8
2500
2500
70
Green (RoHS
& no Sb/Br)
77618
TPS77618DRG4
TPS77618PWP
TPS77618PWPG4
TPS77618PWPR
TPS77618PWPRG4
TPS77625D
SOIC
D
8
Green (RoHS
& no Sb/Br)
77618
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
PWP
PWP
PWP
D
20
20
20
20
8
Green (RoHS
& no Sb/Br)
PT77618
PT77618
PT77618
PT77618
77625
70
Green (RoHS
& no Sb/Br)
2000
2000
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TPS77625DG4
TPS77625DR
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
77625
SOIC
D
8
2500
2500
70
Green (RoHS
& no Sb/Br)
77625
TPS77625DRG4
TPS77625PWP
TPS77625PWPG4
TPS77625PWPR
TPS77625PWPRG4
TPS77628D
SOIC
D
8
Green (RoHS
& no Sb/Br)
77625
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
PWP
PWP
PWP
D
20
20
20
20
8
Green (RoHS
& no Sb/Br)
PT77625
PT77625
PT77625
PT77625
77628
70
Green (RoHS
& no Sb/Br)
2000
2000
75
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
TPS77628PWP
TPS77633D
ACTIVE
HTSSOP
SOIC
PWP
20
8
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
PT77628
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
75
Green (RoHS
& no Sb/Br)
77633
TPS77633DG4
TPS77633DR
SOIC
8
Green (RoHS
& no Sb/Br)
77633
SOIC
D
8
2500
2500
70
Green (RoHS
& no Sb/Br)
77633
TPS77633DRG4
TPS77633PWP
TPS77633PWPG4
TPS77633PWPR
TPS77633PWPRG4
SOIC
D
8
Green (RoHS
& no Sb/Br)
77633
HTSSOP
HTSSOP
HTSSOP
HTSSOP
PWP
PWP
PWP
PWP
20
20
20
20
Green (RoHS
& no Sb/Br)
PT77633
PT77633
PT77633
PT77633
70
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2014
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS77501, TPS77515, TPS77518, TPS77525, TPS77533, TPS77601, TPS77615, TPS77618, TPS77625, TPS77633 :
Automotive: TPS77501-Q1, TPS77515-Q1, TPS77518-Q1, TPS77525-Q1, TPS77533-Q1, TPS77601-Q1, TPS77615-Q1, TPS77618-Q1, TPS77625-Q1, TPS77633-Q1
•
Enhanced Product: TPS77501-EP, TPS77515-EP, TPS77518-EP, TPS77525-EP, TPS77533-EP, TPS77601-EP, TPS77615-EP, TPS77618-EP, TPS77625-EP, TPS77633-EP
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS77501DR
TPS77501PWPR
TPS77515DR
SOIC
HTSSOP PWP
SOIC
HTSSOP PWP
SOIC
HTSSOP PWP
SOIC
HTSSOP PWP
D
8
20
8
2500
2000
2500
2000
2500
2000
2500
2000
2500
2500
2000
2500
2000
2500
2500
2000
2500
2000
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
12.4
16.4
12.4
16.4
12.4
12.4
16.4
12.4
16.4
6.4
6.95
6.4
5.2
7.1
5.2
7.1
5.2
7.1
5.2
7.1
5.2
5.2
7.1
5.2
7.1
5.2
5.2
7.1
5.2
7.1
2.1
1.6
2.1
1.6
2.1
1.6
2.1
1.6
2.1
2.1
1.6
2.1
1.6
2.1
2.1
1.6
2.1
1.6
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
12.0
16.0
12.0
16.0
12.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
D
TPS77515PWPR
TPS77516DR
20
8
6.95
6.4
D
TPS77516PWPR
TPS77518DR
20
8
6.95
6.4
D
TPS77518PWPR
TPS77525DR
20
8
6.95
6.4
SOIC
SOIC
D
D
TPS77533DR
8
6.4
TPS77533PWPR
TPS77601DR
HTSSOP PWP
SOIC
HTSSOP PWP
20
8
6.95
6.4
D
TPS77601PWPR
TPS77615DR
20
8
6.95
6.4
SOIC
SOIC
D
D
TPS77618DR
8
6.4
TPS77618PWPR
TPS77625DR
HTSSOP PWP
SOIC
HTSSOP PWP
20
8
6.95
6.4
D
TPS77625PWPR
20
6.95
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS77633DR
SOIC
D
8
2500
2000
330.0
330.0
12.4
16.4
6.4
5.2
7.1
2.1
1.6
8.0
8.0
12.0
16.0
Q1
Q1
TPS77633PWPR
HTSSOP PWP
20
6.95
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS77501DR
TPS77501PWPR
TPS77515DR
SOIC
HTSSOP
SOIC
D
PWP
D
8
20
8
2500
2000
2500
2000
2500
2000
2500
2000
2500
2500
2000
2500
2000
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
38.0
35.0
35.0
38.0
35.0
38.0
35.0
35.0
TPS77515PWPR
TPS77516DR
HTSSOP
SOIC
PWP
D
20
8
TPS77516PWPR
TPS77518DR
HTSSOP
SOIC
PWP
D
20
8
TPS77518PWPR
TPS77525DR
HTSSOP
SOIC
PWP
D
20
8
TPS77533DR
SOIC
D
8
TPS77533PWPR
TPS77601DR
HTSSOP
SOIC
PWP
D
20
8
TPS77601PWPR
TPS77615DR
HTSSOP
SOIC
PWP
D
20
8
TPS77618DR
SOIC
D
8
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS77618PWPR
TPS77625DR
HTSSOP
SOIC
PWP
D
20
8
2000
2500
2000
2500
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
38.0
35.0
38.0
TPS77625PWPR
TPS77633DR
HTSSOP
SOIC
PWP
D
20
8
TPS77633PWPR
HTSSOP
PWP
20
Pack Materials-Page 3
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