TPS78342DDCR [TI]
TPS783xx 500-nA IQ, 150-mA, Ultralow Quiescent Current Low-Dropout Linear Regulator;
| 型号： | TPS78342DDCR |
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| 描述： | TPS783xx 500-nA IQ, 150-mA, Ultralow Quiescent Current Low-Dropout Linear Regulator 光电二极管 输出元件 调节器 |
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TPS783
SBVS133A –FEBRUARY 2010–REVISED NOVEMBER 2014
TPS783xx 500-nA IQ, 150-mA, Ultralow Quiescent Current
Low-Dropout Linear Regulator
1 Features
3 Description
The TPS783 family of low-dropout regulators (LDOs)
offers the benefits of ultralow power and miniaturized
packaging.
1
•
•
•
•
•
•
•
•
•
•
Input Voltage Range: 2.2 V to 5.5 V
Low Quiescent Current (IQ): 500 nA
150-mA, Low-Dropout Regulator
This LDO family is designed specifically for battery-
powered applications where ultralow quiescent
current is a critical parameter. The TPS783, with
ultralow IQ (500 nA), is ideal for microprocessors,
microcontrollers,
applications.
Low-Dropout at 25°C, 130 mV at 150 mA
Low-Dropout at 85°C, 175 mV at 150 mA
3% Accuracy Over Load, Line, and Temperature
Stable with a 1.0-μF Ceramic Capacitor
Thermal Shutdown and Overcurrent Protection
CMOS Logic Level-Compatible Enable Pin
DDC (SOT-5) Package
and
other
battery-powered
The absence of pulldown circuitry at the output of the
LDO provides the flexibility to use the regulator output
capacitor as a temporary backup power supply (for
example, during battery replacement).
2 Applications
The ultralow power and miniaturized packaging allow
designers to customize power consumption for
specific applications. Consult with your local factory
representative for exact voltage options and ordering
information; minimum order quantities may apply.
•
•
•
•
TI MSP430 Attach Applications
Wireless Handsets and Smartphones
MP3 Players
Battery-Operated Handheld Products
The TPS783 family is compatible with the TI MSP430
and other similar products. The enable pin (EN) is
compatible with standard CMOS logic. This device
allows for minimal board space because of
miniaturized packaging and a potentially small output
capacitor. The TPS783 family also features thermal
shutdown and current limit to protect the device
during fault conditions. All packages have a specified
operating temperature range of TJ = –40°C to 105°C.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TPS783xx
SOT (5)
2.90 mm × 1.60 mm
(1) For all available packages, see the package option addendum
at the end of the datasheet.
Simplified Schematic
TPS783xxDDC
SOT-5
(Top View)
VIN
VOUT
IN
OUT
2.2 mF
1 mF
TPS783xx
1
2
3
5
4
IN
GND
EN
OUT
GND
On
EN
Off
GND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS783
SBVS133A –FEBRUARY 2010–REVISED NOVEMBER 2014
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application .................................................. 11
8.3 System Examples ................................................... 13
8.4 Do's and Don’ts....................................................... 15
Power-Supply Recommendations...................... 15
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 Handling Ratings....................................................... 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 6
Detailed Description .............................................. 9
7.1 Overview ................................................................... 9
7.2 Functional Block Diagram ......................................... 9
7.3 Feature Description................................................... 9
8
9
10 Layout................................................................... 15
10.1 Layout Guidelines ................................................. 15
10.2 Layout Example .................................................... 16
11 Device and Documentation Support ................. 17
11.1 Device Support .................................................... 17
11.2 Trademarks........................................................... 17
11.3 Electrostatic Discharge Caution............................ 17
11.4 Glossary................................................................ 17
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 17
4 Revision History
Changes from Original (February 2010) to Revision A
Page
•
Changed document format to latest data sheet standards; added Handling Ratings, Thermal Information,
Recommended Operating Conditions, Power Supply Recommendations, and Device and Documentation Support
sections; moved existing sections .......................................................................................................................................... 1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Deleted factory programming feature bullet .......................................................................................................................... 1
Added input voltage range feature bullet ............................................................................................................................... 1
Deleted programmable mode application bullet ..................................................................................................................... 1
Added simplified schematic to front page............................................................................................................................... 1
Changed Pin Functions table ................................................................................................................................................ 3
Changed operating junction temperature maximum value in Absolute Maximum Ratings table ........................................... 4
Deleted Dissipation Ratings table; see Thermal Information table......................................................................................... 4
Changed symbol and parameter names for clarity in Electrical Characteristics table ........................................................... 5
Added footnote (2) to Electrical Characteristics table ............................................................................................................ 5
Changed Figure 7 y-axis title and measurement range ......................................................................................................... 7
Changed Figure 9 VEN labels to match Electrical Characteristics table ................................................................................. 7
Changed Figure 10 y-axis title to match Electrical Characteristics table ............................................................................... 7
Deleted Figure 14 IOUT condition ............................................................................................................................................ 7
Deleted Figure 15 IOUT condition ............................................................................................................................................ 7
Changed Functional Block Diagram....................................................................................................................................... 9
Changed Figure 18 .............................................................................................................................................................. 10
Added reference for Table 1 in Device Functional Modes ................................................................................................... 10
Changed Figure 19............................................................................................................................................................... 11
Changed Table 2 format....................................................................................................................................................... 14
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SBVS133A –FEBRUARY 2010–REVISED NOVEMBER 2014
5 Pin Configuration and Functions
DDC Package
SOT-5
(Top View)
1
2
3
5
4
IN
GND
EN
OUT
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
EN
NO.
3
Enable pin. Drive this pin over 1.2 V to turn on the regulator. Drive this pin below 0.4 V to put
the regulator into shutdown mode, reducing operating current to 18 nA, typical.
I
GND
2, 4
—
Ground pin. Tie all ground pins to ground for proper operation.
Input pin. For stable operation, place a small, 0.1-μF capacitor from this pin to ground; typical
input capacitor = 1.0 μF. Tie back both input and output capacitor grounds to the IC ground,
with no significant impedance between them.
IN
1
5
I
Regulated output voltage pin. Connect a small (1-μF or greater) ceramic capacitor from this
pin to ground for stable operation. See the Input and Output Capacitor Requirements in the
Application and Implementation section for more details.
OUT
O
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6 Specifications
6.1 Absolute Maximum Ratings
At TJ = –40°C to 105°C (unless otherwise noted). All voltages are with respect to GND.(1)
MIN
MAX
6.0
UNIT
VIN
–0.3
–0.3
–0.3
V
V
V
A
Voltage
EN pin
VIN + 0.3
VIN + 0.3
VOUT
IOUT
Internally limited
Current
Output short-circuit duration
Operating junction, TJ
Indefinite
160
Temperature
–40
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN
–55
MAX
150
UNIT
Tstg
Storage temperature range
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
–2000
–500
2000
500
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
2.2
1.8
0
NOM
MAX
5.5
UNIT
VIN
Input voltage
V
V
VOUT
VEN
IOUT
TJ
Output voltage
Enable voltage
Output current
Junction temperature
4.2
VIN
V
0
150
105
mA
°C
–40
6.4 Thermal Information
TPS783xx
THERMAL METRIC(1)
DDC (SOT)
5 PINS
193.0
40.0
UNIT
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
34.3
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.9
ψJB
34.1
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
At TJ = –40°C to 105°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1.0 μF,
and fixed VOUT test conditions (unless otherwise noted). Typical values at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.2
TYP
MAX
5.5
UNIT
VIN
Input voltage range
V
Nominal
TJ = 25°C
–2%
2%
VOUT
DC output accuracy
Over VIN, IOUT
temperature
,
VOUT + 0.5 V ≤ VIN ≤ 5.5 V,
100 μA ≤ IOUT ≤ 150 mA
–3.0%
±2.0%
3.0%
ΔVO(ΔVI)
ΔVO(ΔIO)
VDO
Line regulation
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V
100 μA ≤ IOUT ≤ 150 mA
VIN = 95% VOUT(nom), IOUT = 150 mA
VOUT = 0.90 × VOUT(nom)
IOUT = 0 mA
±1.0%
±1.0%
130
230
420
8
Load regulation
Dropout voltage(1)
Output current limit
250
400
800
mV
mA
nA
μA
nA
nA
ILIM
150
IGND
GND pin current
EN pin current
IOUT = 150 mA
IEN
VIN = VEN = 5.5 V
0.07
18
40
ISHDN(GND)
Shutdown current at GND pin
V
EN ≤ 0.4 V, VIN(min) ≤ VIN < 5.5 V(2)
150
Shutdown current at OUT pin
(leakage)(3)
VIN = open, VEN = 0.4 V,
VOUT = VOUT(nom)
ISHDN(OUT)
137
500
nA
VEN(HI)
VEN(LO)
Enable high-level voltage
Enable low-level voltage
VIN = 5.5 V
VIN = 5.5 V
1.2
0
VIN
0.4
V
V
f = 10 Hz
40
20
15
dB
dB
dB
VIN = 4.3 V,
VOUT = 3.0 V,
IOUT = 150 mA
PSRR
Power-supply rejection ratio
f = 100 Hz
f = 1 kHz
BW = 100 Hz to 100 kHz, VIN = 2.2 V,
VOUT = 1.2 V, IOUT = 1 mA
Vn
Output noise voltage
Startup time(4)
86
μVRMS
μs
COUT = 1.0 μF, VOUT = 10% VOUT(nom) to
VOUT = 90% VOUT(nom)
tSTR
500
Shutdown, temperature increasing
Reset, temperature decreasing
160
140
°C
°C
°C
Tsd
TJ
Thermal shutdown temperature
Operating junction temperature
–40
125
(1) VDO is not measured for devices with VOUT(nom) ≤ 2.3 V because minimum VIN = 2.2 V.
(2) VIN(min) = (VOUT(nom) + 0.5 V) or 2.2 V, whichever is greater.
(3) See Shutdown in the Application and Implementation section for more details.
(4) Time from VEN = 1.2 V to VOUT = 90% (VOUT(nom)).
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6.6 Typical Characteristics
At TJ = –40°C to 105°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1 μF, and
CIN = 1 μF (unless otherwise noted).
1.0
0.8
3
2
-40°C
0.6
0.4
1
+85°C
+25°C
-40°C
0.2
+25°C
0
0
+105°C
-0.2
-0.4
-0.6
-0.8
-1.0
+105°C
+85°C
-1
-2
-3
3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
VIN (V)
IOUT = 5 mA, VOUT(nom) = 3.0 V
IOUT = 150 mA, VOUT(nom) = 3.0 V
Figure 1. TPS78330 Line Regulation
Figure 2. TPS78330 Line Regulation
3
2
200
150
100
50
+85°C
+105°C
1
-40°C
+25°C
+85°C
0
+105°C
-1
-2
-3
+25°C
-40°C
0
0
25
50
75
100
125
150
0
25
50
75
100
125
150
IOUT (mA)
IOUT (mA)
VIN = 3.5 V, VOUT(nom) = 3.0 V
VOUT(nom) = 3.0 V, VIN = 0.95 × VOUT(nom)
Figure 3. TPS78330 Load Regulation
Figure 4. TPS78330 Dropout Voltage vs Output Current
900
800
700
250
200
150
100
50
+85°C
600
100mA
500
400
300
150mA
50mA
-40°C
200
+25°C
10mA
100
0
0
3.8
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4 5.5
-40 -25 -10
5
20 35 50 65 80 95 110 125
VIN (V)
TJ (°C)
IOUT = 0 mA, VOUT(nom) = 3.0 V
VOUT(nom) = 3.0 V, VIN = 0.95 × VOUT(nom)
Figure 6. TPS78330 Ground Pin Current vs Input Voltage
Figure 5. TPS78330 Dropout Voltage vs
Junction Temperature
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Typical Characteristics (continued)
At TJ = –40°C to 105°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1 μF, and
CIN = 1 μF (unless otherwise noted).
250
240
230
220
210
200
3.0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-40°C
+105°C
+25°C
+85°C
+85°C
+105°C
+25°C
-40°C
3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5
VIN (V)
VOUT = 95% VOUT(nom), VOUT(nom) = 3.0 V
IOUT = 100 μA, VOUT(nom) = 3.0 V
Figure 7. TPS78330 Current Limit vs Input Voltage
Figure 8. TPS78330 Enable Pin Current vs Input Voltage
250
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
200
150
VEN(HI)
+105°C
100
+85°C
+25°C
VEN(LO)
50
-40°C
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TJ (°C)
VOUT (V)
IOUT = 1 mA, VOUT(nom) = 3.0 V
VOUT = VOUT(nom) = 3.0 V, VEN = 0.4 V
Figure 9. TPS78330 Enable Pin Hysteresis vs
Junction Temperature
Figure 10. TPS78330 Output Current Leakage at Shutdown
100
10
3
2
10mA
100mA
1
0
1
150mA
150mA
5mA
0.1
-1
-2
-3
50mA
1mA
1mA = 130mVRMS
0.01
0.001
50mA = 134mVRMS
150mA = 138.0mVRMS
-40 -25 -10
5
20 35 50 65 80 95 110 125
10
100
1k
10k
100k
TJ (°C)
Frequency (Hz)
CIN = 1 μF, COUT = 2.2 μF, VIN = 3.5 V, VOUT(nom) = 3.0 V
VIN = 3.5 V, VOUT(nom) = 3.0 V
Figure 11. TPS78330 Output Spectral Noise Density
Figure 12. TPS78330 %ΔVO vs Junction Temperature
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Typical Characteristics (continued)
At TJ = –40°C to 105°C, VIN = VOUT(nom) + 0.5 V or 2.2 V, whichever is greater; IOUT = 100 μA, VEN = VIN, COUT = 1 μF, and
CIN = 1 μF (unless otherwise noted).
80
VIN = 0.0V to 5.0V
VOUT = 3.0V
VIN
70
60
50
40
30
20
10
0
1mA
COUT = 10mF
Enable
50mA
VOUT
Load Current
0V
150mA
Time (20ms/div)
10
100
1k
10k
100k
1M
Frequency (Hz)
VIN = 3.5 V, VOUT(nom) = 3.0 V, COUT = 2.2 μF
Figure 14. TPS78330 Input Voltage Ramp vs Output Voltage
Figure 13. TPS78330 Ripple Rejection vs Frequency
VIN
Enable
VIN = 5.5V
VOUT = 3.0V
IOUT = 150mA
VIN
COUT = 10mF
VOUT
VENABLE
VIN = 5.5V
VOUT
Load Current
VOUT = 3.0V
COUT = 10mF
0V
Time (20ms/div)
Time (500ms/div)
Figure 15. TPS78330 Output Voltage vs Enable (Slow Ramp)
Figure 16. TPS78330 Input Voltage vs Delay to Output
Enable
VIN
VOUT
VIN = 5.5V
VOUT = 3.0V
IOUT = 0mA to 10mA
Load
COUT = 10mF
Current
0A
Time (5ms/div)
Figure 17. TPS78330 Load Transient Response
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7 Detailed Description
7.1 Overview
The TPS783 family of low-dropout regulators (LDOs) designed specifically for battery-powered applications
where ultralow quiescent current is a critical parameter. The absence of pulldown circuitry at the output of the
LDO provides the flexibility to use the regulator output capacitor as a temporary backup power supply for a short
period of time (for example, during battery replacement). The TPS783 family is compatible with the TI MSP430
and other similar products. The enable pin (EN) is compatible with standard CMOS logic. This LDO family is
stable with any output capacitor greater than 1.0 µF.
7.2 Functional Block Diagram
IN
OUT
Current
Limit
Thermal
Shutdown
EPROM
Mux
EN
Bandgap
Logic
GND
7.3 Feature Description
7.3.1 Internal Current Limit
The TPS783 is internally current-limited to protect the regulator during fault conditions. During current limit, the
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, do
not operate the device in a current-limit state for extended periods of time.
The PMOS pass element in the TPS783 family has a built-in body diode that conducts current when the voltage
at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is
anticipated, external limiting up to the maximum rated current for the device may be required.
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Feature Description (continued)
7.3.2 Shutdown
The enable pin (EN) is active high and is compatible with standard and low-voltage CMOS levels. When
shutdown capability is not required, connect EN to the IN pin, as shown in Figure 18.
VIN
VOUT
IN
OUT
1mF
1mF
TPS783xx
EN
GND
Figure 18. Circuit Showing EN Tied High When Shutdown Capability is Not Required
7.4 Device Functional Modes
Table 1 provides a quick comparison between the normal, dropout, and disabled modes of operation.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
EN
IOUT
IOUT < ILIM
IOUT < ILIM
—
TJ
Normal
Dropout
Disabled
VIN > VOUT(nom) + VDO
VIN < VOUT(nom) + VDO
—
VEN > VEN(HI)
VEN > VEN(HI)
VEN < VEN(LO)
TJ < 160°C
TJ < 160°C
TJ > 160°C
7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO).
The enable voltage has previously exceeded the enable rising threshold voltage (VEN > VEN(HI)) and not yet
decreased below the enable falling threshold.
•
•
The output current is less than the current limit (IOUT < ILIM).
The device junction temperature is less than the thermal shutdown temperature (TJ < 160°C).
7.4.2 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line
or load transients in dropout can result in large output-voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
•
The enable voltage is less than the enable falling threshold voltage (VEN < VEN(LO)) or has not yet exceeded
the enable rising threshold.
•
The device junction temperature is greater than the thermal shutdown temperature (TJ > 160°C).
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The TPS783 family of LDOs is factory-programmable to have a fixed output. Note that during startup or steady-
state conditions, do not allow the EN pin voltage to exceed VIN + 0.3 V.
8.2 Typical Application
VIN
VOUT
IN
OUT
2.2 mF
1 mF
TPS783xx
On
EN
Off
GND
Figure 19. Providing a Low-Power Standby Rail
8.2.1 Design Requirements
8.2.1.1 Input and Output Capacitor Requirements
A 0.1-μF input capacitor is necessary for stable operation. Good analog design practice is to connect a 0.1-μF to
1.0-μF, low equivalent series resistance (ESR) capacitor across the input supply near the regulator. This
capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple
rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if
the device is not located near the power source.
The TPS783 family is designed to be stable with standard ceramic capacitors with values of 1.0 μF or larger at
the output. X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over
temperature. Maximum ESR must be less than 1.0 Ω. With tolerance and dc bias effects, the minimum
capacitance for stable operation is 1 μF.
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Typical Application (continued)
8.2.1.2 Dropout Voltage
The TPS783 family uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the
dropout voltage (VDO), the PMOS pass device is the linear region of operation and the input-to-output resistance
is the RDS(ON) of the PMOS pass element. VDO approximately scales with output current because the PMOS
device behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are
degraded as (VIN – VOUT) approaches dropout. This effect is shown in the Typical Characteristics section. Refer
to application report SLVA207, Understanding LDO Dropout, available for download from www.ti.com.
8.2.1.3 Transient Response
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude
but increases duration of the transient response. For more information, see Figure 17.
8.2.1.4 Minimum Load
The TPS783 family is stable with no output load. Traditional PMOS LDO regulators suffer from lower loop gain at
very light output loads. The TPS783 employs an innovative, low-current circuit under very light or no-load
conditions, resulting in improved output voltage regulation performance down to zero output current. See
Figure 17 for the load transient response.
8.2.2 Detailed Design Procedure
Select the desired device based on the output voltage.
Provide an input supply with adequate headroom to account for dropout and output current to account for the
GND pin current, and power the load. Select input and output capacitors based on application needs.
8.2.3 Application Curves
100
10
80
70
60
50
40
30
20
10
0
1mA
1
50mA
150mA
0.1
50mA
1mA = 130mVRMS
0.01
0.001
150mA
50mA = 134mVRMS
150mA = 138.0mVRMS
1mA
10k
10
100
1k
10k
100k
1M
10
100
1k
100k
Frequency (Hz)
Frequency (Hz)
CIN = 1 μF, COUT = 2.2 μF, VIN = 3.5 V, VOUT(nom) = 3.0 V
VIN = 3.5 V, VOUT(nom) = 3.0 V, COUT = 2.2 μF
Figure 20. TPS78330 Output Spectral Noise Density
Figure 21. TPS78330 Ripple Rejection vs Frequency
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8.3 System Examples
The TPS783 family is designed to be compatible with low-power microprocessors and microcontrollers such as
the TI MSP430. In particular, the ultralow quiescent current allows for the TPS783 family to be used in battery-
powered applications.
When the system is active, a voltage supervisor enables the regulator and puts the MSP430 into active mode
when there is a battery installed and its voltage is above a certain threshold, as shown in Figure 22. The dashed
red line indicates the ground current.
I
mC
IN
OUT
Battery
MSP430
TPS783xx
10% Duty Cycle
EN = High
EN
SVS
GND
500nA
Battery OK
Figure 22. MSP430 Application in Active Mode
When the battery is depleted, the voltage supervisor signals to replace the system battery. After the battery is
removed, the voltage supervisor disables the regulator and signals the MSP430 to go into low-power mode. At
this moment, the output capacitor functions as a power supply for the MSP430 during the absence of the battery
while it is being replaced, as Figure 23 illustrates. The dashed red line indicates the ground current.
ILP
IN
OUT
No Battery
COUT
MSP430
TPS783xx
10% Duty Cycle
EN = Low
EN
SVS
GND
150nA = ILKG
Battery Low
Low-Power Mode
Figure 23. MSP430 Application While Battery is Replaced
Equation 1 shows how to find the required value of the output capacitor (COUT) to provide an appropriate voltage
level to the MSP430 for a given amount of time. This time varies from a few seconds to a few minutes,
depending on several factors.
tMAX
V
OUT(Nom) - VMIN
COUT
=
ILKG + ILP
where
•
•
•
•
•
tMAX = maximum time to replace depleted battery
VOUT(nom) = nominal regulator output equal to initial voltage of capacitor when regulator is disabled
VMIN = minimum voltage required by MSP430
I(LKG) = leakage current into regulator output
I(LP) = current demand from MSP430 in low-power mode
(1)
13
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System Examples (continued)
8.3.1 Extending Battery Life in Keep-Alive Circuitry Applications for MSP430 and Other Low-Power
Microcontrollers
One of the primary advantages of a low quiescent current LDO is the extremely low energy requirement.
Counter-intuitively, this requirement enables a longer battery life compared to using only the battery as an
unregulated voltage supply for low-power microcontrollers, such as the MSP430. Figure 24 illustrates the
characteristic performance of an unregulated, 3.0-V battery supply versus a regulated TPS783 supply for a
typical MSP430 application. Table 2 summarizes this comparison.
90
Battery, VCC = 3.0V
80
TPS783, VCC = 2.2V
70
60
50
40
30
20
10
0
5 10
20
30
40
50
60
70
80
90 100
Duty Cycle (Time in Active Mode) (%)
Calculated with an MSP430F model, operating at 6 MHz.
Figure 24. Battery Life Comparison vs Duty Cycle for MSP430 Application
Table 2. Battery Life Comparison vs Active Mode Time for MSP430 Application
TPS783xx
(NO. OF DAYS)
BATTERY ONLY
(NO. OF DAYS)
1-μA LDO
(NO. OF DAYS)
ACTIVE DUTY CYCLE
Active mode, 1 sec/hour (0.028% duty cycle)
Active mode, 10 sec/hour (0.28% duty cycle)
Active mode, 100 sec/hour (2.8% duty cycle)
Active mode, 1000 sec/hour (28% duty cycle)
Active mode, on all the time (100% duty cycle)
5742
1320
151
6286
998
106
10.7
3.0
4373
1085
148
15.4
4.2
15.4
4.2
CONDITIONS
Efficiency with VBAT = 3.0 V and VCC = 2.2 V (VOUT/VIN
)
73%
0.5 μA
2.19 mA
0.5 μA
100%
0
73%
1 μA
LDO quiescent current (IQ)
MSP430 active current
3.09 mA
0.6 μA
2.19 mA
0.5 μA
MSP430 low-power current
8.3.2 Supercapacitor-Based Backup Power
The very-low leakage current at the LDO output provides a system with the flexibility to use the device output
capacitor, or supercapacitor, as a temporary backup power supply. The leakage current going into the regulator
output from the output capacitor when the LDO is disabled is typically 170 nA; see Figure 10.
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8.4 Do's and Don’ts
Do place at least one 1-µF ceramic capacitor as close as possible to the OUT pin of the regulator.
Do not place the output capacitor more than 10 mm away from the regulator.
Do connect a 0.1-μF to 1.0-μF low equivalent series resistance (ESR) capacitor across the IN pin and GND of
the regulator.
Do not exceed the absolute maximum ratings.
9 Power-Supply Recommendations
For best performance, connect a low-output impedance power supply directly to the IN pin of the TPS783.
Inductive impedances between the input supply and the IN pin create significant voltage excursions at the IN pin
during startup or load transient events. If inductive impedances are unavoidable, use an input capacitor.
10 Layout
10.1 Layout Guidelines
10.1.1 Board Layout Recommendations to Improve PSRR and Noise Performance
To improve ac performance (such as PSRR, output noise, and transient response), design the printed circuit
board (PCB) with separate ground planes for VIN and VOUT, with each ground plane connected only at the GND
pin of the device. In addition, the output capacitor must be as close as possible to the ground pin of the device to
provide a common reference for regulation purposes. High ESR capacitors may degrade PSRR.
10.1.2 Package Mounting
Solder pad footprint recommendations for the TPS783 series are available from the Texas Instruments website
at www.ti.com through the TPS783 family product folders.
10.1.3 Thermal Information
10.1.3.1 Thermal Protection
Thermal protection disables the device output when the junction temperature rises to approximately 160°C,
allowing the device to cool. After the junction temperature cools to approximately 140°C, the output circuitry is
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection
circuit may cycle on and off again. This cycling limits the dissipation of the regulator, protecting it from damage
as a result of overheating.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate
heatsink. For reliable operation, limit junction temperature to 105°C maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until the thermal protection is
triggered; use worst-case loads and signal conditions.
The internal protection circuitry of the TPS783 family is designed to protect against overload conditions.
However, this circuitry is not intended to replace proper heatsinking. Continuously running the TPS783 series
into thermal shutdown degrades device reliability.
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Layout Guidelines (continued)
10.1.3.2 Power Dissipation
The ability to remove heat from the die is different for each package type, presenting different considerations in
the PCB layout. The PCB area around the device that is free of other components moves the heat from the
device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves the heatsink effectiveness. Power
dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the
output current times the voltage drop across the output pass element (VIN to VOUT), as shown in Equation 2:
PD = (VIN - VOUT) ´ IOUT
(2)
10.2 Layout Example
VIN
VOUT
CIN
COUT
GND PLANE
Represents via used for
application-specific connections
Figure 25. TPS783xx Layout Example
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Evaluation Modules
An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS783.
The TPS782xxEVM evaluation modules (and related user guide) can be requested at the Texas Instruments
website through the product folders or purchased directly from the TI eStore.
11.1.1.2 Spice Models
Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of
analog circuits and systems. A SPICE model for the TPS783 is available through the product folders under
Simulation Models.
11.1.2 Device Nomenclature
Table 3. Device Nomenclature(1)
PRODUCT
VOUT
TPS783xxyyyz
XX is the nominal output voltage
YYY is the package designator.
Z is the tape and reel quantity (R = 3000, T = 250).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2014
PACKAGING INFORMATION
Orderable Device
TPS78318DDCR
TPS78318DDCT
TPS78319DDCR
TPS78319DDCT
TPS78326DDCR
TPS78326DDCT
TPS78330DDCR
TPS78330DDCT
TPS78342DDCR
TPS78342DDCT
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
-40 to 105
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
ACTIVE
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
DDC
5
5
5
5
5
5
5
5
5
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
SIO
SIO
SIP
SIP
SIB
SIB
DAZ
DAZ
SIQ
SIQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
250
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2014
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS78318DDCR
TPS78318DDCT
TPS78319DDCR
TPS78319DDCT
TPS78326DDCR
TPS78326DDCT
TPS78330DDCR
TPS78330DDCT
TPS78342DDCR
TPS78342DDCT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
5
5
5
5
5
5
5
5
5
5
3000
250
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
179.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Oct-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS78318DDCR
TPS78318DDCT
TPS78319DDCR
TPS78319DDCT
TPS78326DDCR
TPS78326DDCT
TPS78330DDCR
TPS78330DDCT
TPS78342DDCR
TPS78342DDCT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
SOT
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
5
5
5
5
5
5
5
5
5
5
3000
250
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
195.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
200.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
45.0
3000
250
3000
250
3000
250
3000
250
Pack Materials-Page 2
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TPS784-Q1 300-mA, High-PSRR Low-Dropout Voltage Regulator With High Accuracy and Enable
TI
TPS784-Q1_V07
TPS784-Q1 Automotive, 300-mA, High-PSRR Low-Dropout Voltage Regulator With High Accuracy and Enable
TI
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