TPS78425QWDRBRQ1 [TI]
TPS784-Q1 Automotive, 300-mA, High-PSRR Low-Dropout Voltage Regulator With High Accuracy and Enable;
| 型号： | TPS78425QWDRBRQ1 |
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TEXAS INSTRUMENTS |
| 描述： | TPS784-Q1 Automotive, 300-mA, High-PSRR Low-Dropout Voltage Regulator With High Accuracy and Enable |
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TPS784-Q1
SBVS387C – FEBRUARY 2020 – REVISED JANUARY 2022
TPS784-Q1 Automotive, 300-mA, High-PSRR Low-Dropout Voltage Regulator With
High Accuracy and Enable
1 Features
3 Description
•
AEC-Q100 qualified for automotive applications:
– Temperature grade 1: –40°C to +125°C, TA
Device junction temperature: –40°C to +150°C, TJ
Input voltage range: 1.65 V to 6.0 V
Available output voltages:
– Adjustable option: 1.2 V to 5.5 V
– Fixed options: 0.65 V to 5.0 V
Output accuracy: 0.5% typical, 1.7% maximum
50-dB PSRR out to 100 kHz
The TPS784-Q1 ultra low-dropout regulator (LDO)
is a small, low quiescent current LDO that can
source 300 mA with excellent line and load transient
performance.
•
•
•
The low output noise and great PSRR performance
make the device suitable to power sensitive analog
loads. The TPS784-Q1 is a flexible device for post
regulation because this device supports an input
voltage range from 1.65 V to 6.0 V and offers an
adjustable output range of 1.2 V to 5.5 V. The device
also features fixed output voltages from 0.65 V to
5.0 V for powering common voltage rails.
•
•
•
•
Low IQ: 25 µA (typical)
Ultra-low dropout:
– 115 mV (max) at 300 mA (3.3 VOUT
)
•
Internal 500-µs soft-start time to reduce inrush
current
Active output discharge
Functional Safety-Capable
– Documentation available to aid functional safety
system design
The TPS784-Q1 offers foldback current limit to reduce
power dissipation during over current condition. The
EN input helps with power sequencing requirements
of the system. The internal soft-start provides a
controlled start up, reducing the inrush current and
allowing for lower input capacitance to be used.
•
•
•
Packages:
The TPS784-Q1 provides an active pulldown circuit to
quickly discharge output loads when disabled.
– 3-mm × 3-mm wettable flank VSON (8)
– 5-pin SOT-23
Device Information(1)
2 Applications
PART NUMBER
PACKAGE
BODY SIZE (NOM)
3.00 mm × 3.00 mm
2.90 mm × 1.60 mm
•
•
•
•
Automotive head units
Hybrid instrument clusters
Telematics control units
DC/DC converters
Wettable flank
VSON (8)
TPS784-Q1
SOT-23 (5)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
200
0.25
TJ
180
0.2
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
160
0.15
0.1
140
120
100
80
0.05
0
-0.05
60
-0.1
TJ
40
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-0.15
-0.2
20
0
-0.25
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Output Current (A)
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Output Current (A)
Dropout vs IOUT for 5.0 V
Output Accuracy vs IOUT for 5.0 V
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS784-Q1
SBVS387C – FEBRUARY 2020 – REVISED JANUARY 2022
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................6
6.4 Thermal Information ...................................................6
6.5 Electrical Characteristics ............................................7
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................23
7.1 Overview...................................................................23
7.2 Functional Block Diagrams....................................... 23
7.3 Feature Description...................................................24
7.4 Device Functional Modes..........................................27
8 Application and Implementation..................................28
8.1 Application Information............................................. 28
8.2 Typical Application.................................................... 35
9 Power Supply Recommendations................................36
10 Layout...........................................................................37
10.1 Layout Guidelines................................................... 37
10.2 Layout Examples.................................................... 38
11 Device and Documentation Support..........................39
11.1 Device Support........................................................39
11.2 Documentation Support.......................................... 39
11.3 Receiving Notification of Documentation Updates..39
11.4 Support Resources................................................. 39
11.5 Trademarks............................................................. 39
11.6 Electrostatic Discharge Caution..............................39
11.7 Glossary..................................................................39
12 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from May 16, 2021 to January 11, 2022 (from Revision B (April 2021) to Revision C
(January 2022))
Page
•
•
•
Changed VSON package from preview to production data ...............................................................................1
Added B version DRB package (VSON) to the Pin Configuration and Functions section..................................3
Changed Device Nomenclature table...............................................................................................................39
Changes from Revision A (November 2020) to Revision B (April 2021)
Page
Reworded the VIN conditions to have more clarity on what 1.65 V or whichever is greater applies to..............7
Added line item for 1.2 V ≤ VOUT < 1.5 V dropout voltage in the DRB package. ...............................................7
•
•
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5 Pin Configuration and Functions
IN
GND
EN
1
2
3
5
OUT
IN
GND
EN
1
2
3
5
OUT
4
NC
4
FB
Not to scale
Not to scale
Figure 5-1. DBV Package (Fixed), 5-Pin SOT-23,
Top View
Figure 5-2. DBV Package (Adjustable), 5-Pin
SOT-23, Top View
1
2
8
7
OUT
NC
IN
1
2
8
7
OUT
FB
IN
EN
EN
Thermal
Pad
Thermal
Pad
3
4
6
5
NC
NC
NC
3
4
6
5
NC
NC
NC
GND
GND
Figure 5-3. DRB Package (Fixed), 8-Pin VSON,
Top View
Figure 5-4. DRB Package (Adjustable), 8-Pin VSON,
Top View
OUT
NC
1
2
3
4
8
7
6
5
IN
OUT
FB
1
2
3
4
8
7
6
5
IN
NC
EN
GND
NC
EN
GND
Thermal
Pad
Thermal
Pad
NC
NC
NC
NC
Not to scale
Figure 5-5. DRB Package (Fixed) B Version, 8-Pin
VSON, Top View
Not to scale
Figure 5-6. DRB Package (Adjustable) B Version,
8-Pin VSON, Top View
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Table 5-1. Pin Functions
PIN
DRB
(Fixed)
DRB
I/O
DESCRIPTION
DBV
DBV
DRB
DRB
NAME
(Adjustable)
(Adjustable) (Fixed) (Adjustable) (Fixed)
B
B Version
Version
Enable pin. Driving this pin to logic high enables the device; driving
Input this pin to logic low disables the device. Do not float this pin. If not
used, connect EN to IN.
EN
3
3
7
7
6
6
Feedback pin. Input to the control-loop error amplifier. This pin
is used to set the output voltage of the device with the use of
external resistors. Do not float this pin. For adjustable-voltage
version devices only.
FB
4
2
—
2
2
5
—
5
2
5
—
5
Input
GND
—
Ground pin. This pin must be connected to ground on the board.
Input pin. For best transient response and to minimize input
impedance, use the recommended value or larger ceramic
IN
1
—
5
1
4
5
8
3, 4, 6
1
8
8
3, 4, 7
1
8
Input capacitor from IN to ground; see the Recommended Operating
Conditions table. Place the input capacitor as close to the input of
the device as possible.
2, 3, 4,
6
2, 3, 4,
7
No connect pin. This pin is not internally connected. Connect to
ground for best thermal performance or leave floating.
NC
OUT
—
A 0.47-µF or greater effective capacitance is required from OUT
to ground for stability. For best transient response, use a 1-µF or
Output larger ceramic capacitor from OUT to ground. Place the output
capacitor as close to output of the device as possible; see the
Recommended Operating Conditions table.
1
1
The thermal pad is electrically connected to the GND pin. Connect
the thermal pad to a large-area GND plane for improved thermal
performance.
Thermal
Pad
N/A
N/A
Pad
Pad
Pad
Pad
—
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX
UNIT
Supply, VIN
6.5
V
V
V
V
Enable, VEN
6.5
VIN + 0.3(2)
2
Voltage
Output, VOUT
Feedback, VFB
Current
Output, IOUT
Internally limited
Operating junction, TJ
Storage, Tstg
–40
–65
150
150
°C
°C
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The absolute maximum rating is VIN + 0.3 V or 6.5 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
1.65
1.2
0.65
0.1
1(1)
0
NOM
MAX
6.0
UNIT
VIN
Input voltage
V
Adjustable output
Fixed output
5.5
VOUT
Output voltage
V
5.0
CIN
Input capacitor
1
µF
µF
nF
mA
Ω
COUT
CFF
Output capacitor
200
100
300
1
Feed-forward capacitor(2)
Output current
10
IOUT
COUT,ESR
VEN
0
Output capacitor ESR
Enable voltage
0.001
0
6
V
FEN
Enable toggle frequency
Junction temperature
10
kHz
°C
TJ
–40
150
(1) The minimum effective capacitance is 0.47 µF.
(2) Feed-forward capacitor is optional and not required for stability.
6.4 Thermal Information
TPS784-Q1
THERMAL METRIC(1)
DRB (VSON)
8 PINS
61.8(2)
74.1
DBV (SOT-23)
5 PINS
170.8(3)
93.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
34.3
10.2
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
6.2
17.5
ψJB
34.1
40
RθJC(bot)
18.1
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The 1s0p RθJA value (based on JEDEC 51-3) is 226.5 ℃/W for the DRB package.
(3) The 1s0p RθJA value (based on JEDEC 51-3) is 277.3 ℃/W for the DBV package.
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6.5 Electrical Characteristics
at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(nom) + 0.5 V or 1.65 V (whichever is greater), IOUT
1 mA, VEN = VIN, and CIN = COUT = 1 µF, unless otherwise noted. All typical values at TJ = 25°C.
=
PARAMETER
TEST CONDITIONS
MIN
1.65
1.2
TYP
MAX UNIT
VIN
Input voltage
6.0
5.5
5.0
0.5
1
V
Adjustable output
Fixed output
VOUT
Output voltage
V
0.65
–0.5
–1
1 mA ≤ IOUT ≤ 300 mA,
VOUT(nom) + 0.5 V or 1.65 V
(whichever is greater) ≤ VIN
6.0 V
TJ = 25°C
VOUT
Output accuracy(1)
–40°C ≤ TJ ≤ 85°C
–40°C ≤ TJ ≤ 150°C
%
≤
–1.7
1.7
VOUT(nom) + 0.5 V or 1.65 V (whichever is greater) ≤ VIN
6.0 V
≤
VOUT
Line regulation
Load regulation
0.3
mV
mV
µs
–40°C ≤ TJ ≤ 85°C
0.1 mA ≤ IOUT ≤ 300 mA
–5
–5
5
VOUT
–40°C ≤ TJ ≤ 150°C
10
Load transient response
settling time(2) (3)
COUT = 10 µF
10
IOUT = 90 mA to
210 mA
–2%
ΔVOUT
Load transient response
IOUT = 210 mA to
tR = tF = 1 µs, COUT = 10 µF
90 mA
10% %VOUT
overshoot, undershoot (3) (5)
IOUT = 0 mA to
300 mA
–10%
15
IOUT = 0 mA
TJ = 25°C
25
33
30
33
VOUT(nom) + 0.5 V or 1.65 V
(whichever is greater) ≤ VIN
6.0 V
–40°C ≤ TJ ≤ 85°C
–40°C ≤ TJ ≤ 150°C
TJ = 25°C
≤
≤
≤
40
µA
43
IGND
Ground current
IOUT = 500 µA
VOUT(nom) + 0.5 V or 1.65 V
(whichever is greater) ≤ VIN
6.0 V
–40°C ≤ TJ ≤ 85°C
–40°C ≤ TJ ≤ 150°C
TJ = 25°C
45
48
VEN ≤ 0.3 V
0.01
0.05
VOUT(nom) + 0.5 V or 1.65 V
(whichever is greater) ≤ VIN
6.0 V
ISHDN
Shutdown current
–40°C ≤ TJ ≤ 85°C
–40°C ≤ TJ ≤ 150°C
0.25
3
µA
VFB
IFB
Feedback voltage
Adjustable output only
Adjustable output only
VIN = VOUT(nom) + 1 V,
1.182
–0.05
1.2
1.218
0.05
V
Feedback pin current
0.01
µA
ICL
ISC
Output current limit
320
420
mA
mA
(4)
VOUT = 0.9 x VOUT(nom)
Short-circuit current limit
VOUT = 0 V
162.5
0.65 V ≤ VOUT < 0.8 V
0.8 V ≤ VOUT < 1.2 V
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 1.8 V
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT ≤ 5.0 V
900
775
300
175
140
115
IOUT = 300 mA,
VOUT = 0.95 x VOUT(nom)
VDO
Dropout voltage
mV
1.2 V ≤ VOUT < 1.5 V,
DRB Package only
320
f = 1 kHz
60
45
IOUT = 300 mA , VIN
VOUT + 1 V
=
PSRR
Power-supply rejection ratio
f = 100 kHz
f = 1 MHz
dB
30
Vn
Output noise voltage
UVLO threshold
BW = 10 Hz to 100 kHz, VOUT = 1.2 V
30
µVRMS
V
VIN rising
1.32
1.17
1.42
1.29
130
500
1.6
VUVLO
VIN falling
1.42
VUVLO(HYST)
tSTR
UVLO hysteresis
VIN hysteresis
mV
µs
Start-up time
From EN low-to-high transition to VOUT = VOUT(nom) x 95%
280
780
VEN(HI)
EN pin logic high voltage
EN pin logic low voltage
0.85
V
VEN(LOW)
0.425
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6.5 Electrical Characteristics (continued)
at operating temperature range (TJ = –40°C to +150°C), VIN = VOUT(nom) + 0.5 V or 1.65 V (whichever is greater), IOUT
1 mA, VEN = VIN, and CIN = COUT = 1 µF, unless otherwise noted. All typical values at TJ = 25°C.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
IEN
Enable pin current
Pulldown resistance
VIN = VEN = 6.0 V
VIN = 3.3 V
10
nA
Ω
RPULLDOWN
120
Thermal shutdown
temperature
TSD(shutdown)
TSD(reset)
Shutdown, temperature increasing
Reset, temperature decreasing
170
155
°C
Thermal shutdown reset
temperature
(1) Resistor tolerance is not included in overall accuracy in the adjustable version.
(2) The settling time is measured from when IOUT is stepped from 90 mA to 210 mA to when the output voltage recovers to VOUT
VOUT(nom) - 5 mV.
=
(3) This specification is verified by design.
(4) The output is being forced to 90% of the nominal VOUT value.
(5) This specification is in relation to the change from the nominal output voltage (VOUT(nom)).
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6.6 Typical Characteristics
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
TJ
-0.05
-0.1
-0.15
-0.2
-0.25
-0.05
-0.1
-0.15
-0.2
-0.25
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
T
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Output Current (A)
1.5
2
2.5
3
3.5 4
Input Voltage (V)
4.5
5
5.5
6
VOUT = 0.65 V
VOUT = 0.65 V
Figure 6-1. Output Accuracy vs IOUT
Figure 6-2. Output Accuracy vs VIN
0.25
0.2
0.25
0.2
TJ
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
0.15
0.1
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.05
-0.1
-0.15
-0.2
-0.25
TJ
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Output Current (A)
3.8 4.05 4.3 4.55 4.8 5.05 5.3 5.55 5.8
Input Voltage (V)
6
VOUT = 1.2 V
VOUT = 3.3 V
Figure 6-3. Output Accuracy vs IOUT
Figure 6-4. Output Accuracy vs VIN
0.25
0.2
0.25
0.2
0.15
0.1
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.05
-0.1
-0.15
-0.2
-0.25
TJ
TJ
-55èC
-40èC
0èC
85èC
125èC
150èC
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
25èC
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Output Current (A)
5.5 5.55 5.6 5.65 5.7 5.75 5.8 5.85 5.9 5.95
Input Voltage (V)
6
VOUT = 5.0 V
VOUT = 5.0 V
Figure 6-5. Output Accuracy vs IOUT
Figure 6-6. Output Accuracy vs VIN
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
0.2
0.15
0.1
0.2
0.15
0.1
-55 èC
-40 èC
0 èC
25 èC
85 èC
125 èC
150 èC
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature èC
1.5
2
2.5
3
3.5 4
Input Voltage (V)
4.5
5
5.5
6
VOUT = 1.2 V, IOUT = 50 mA
Figure 6-8. Accuracy vs Temperature
VOUT = 1.2 V, IOUT = 50 mA
Figure 6-7. 50-mA Line Regulation
0.2
0.15
0.1
0.2
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.05
-0.1
-0.15
-0.2
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature èC
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature èC
VOUT = 1.2 V, IOUT = 100 mA
VOUT = 1.2 V, IOUT = 300 mA
Figure 6-9. Accuracy vs Temperature
Figure 6-10. Accuracy vs Temperature
200
200
TJ
TJ
180
160
140
120
100
80
175
150
125
100
75
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
50
60
25
40
0
20
-25
0
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Output Current (A)
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Output Current (A)
VOUT = 1.8 V
VOUT = 3.3 V
Figure 6-11. Dropout Voltage vs IOUT
Figure 6-12. Dropout Voltage vs IOUT
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
200
180
160
140
120
100
80
700
600
500
400
300
200
100
0
TJ
TJ
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-55èC
-40èC
0èC
85èC
125èC
150èC
25èC
60
40
20
0
0
0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Output Current (A)
0.0001
0.001
0.005 0.02 0.05 0.1 0.2 0.4
Output Current (A)
VOUT = 5.0 V
Figure 6-13. Dropout Voltage vs IOUT
Figure 6-14. IGND vs IOUT
100
0
38
36
34
32
30
28
TJ
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
-100
-200
-300
-400
-500
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
IOUT = 500 µA
Figure 6-15. IGND vs VIN
IOUT = 500 µA
Figure 6-16. 500-µA Ground Current vs Temperature
352
3.5
TJ
-55èC
-40èC
0èC
85èC
150èC
3
2.5
2
351
350
349
348
347
346
345
344
25èC
125èC
1.5
1
0.5
0
-0.5
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
VEN = 0.3 V
IOUT = 50 mA
Figure 6-18. ISHDN vs VIN
Figure 6-17. 50-mA Ground Current vs Temperature
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
300
250
200
150
100
50
0.8
0.75
0.7
TJ
VEN(HI)
VEN(LO)
-55èC
-40èC
0èC
25èC
150èC
85èC
125èC
0.65
0.6
0.55
0.5
0
0.45
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
-75
-50
-25
0
25
50
75
100 125 150
Temperature (èC)
VEN = 0.3 V
VIN = 2 V
Figure 6-19. Pulldown Resistor (RPulldown) vs VIN
Figure 6-20. VEN(HI) and VEN(LOW) Thresholds vs Temperature
0.85
1.6
VEN(HI)
VEN(LO)
TJ
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
1.4
1.2
1
0.8
0.75
0.7
0.8
0.6
0.4
0.2
0
0.65
0.6
0.55
-75
-50
-25
0
25
50
75
100 125 150
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
Temperature (èC)
VIN = 6 V
VOUT = 1.2 V
Figure 6-21. VEN(HI) and VEN(LOW) Thresholds vs Temperature
Figure 6-22. Foldback Current Limit vs IOUT and Temperature
7
20
17.5
15
5
TJ
4.5
4
-55èC
-40èC
0èC
25èC
85èC
125èC
150èC
6
5
4
3
2
1
0
12.5
10
3.5
3
VOUT
VIN
7.5
5
2.5
2
2.5
0
1.5
1
-2.5
-5
0.5
0
0
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Output Current (A)
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
VOUT = 5.0 V
VOUT = 3.3 V, IOUT = 1 mA, slew rate = 1 V/µs
Figure 6-23. Foldback Current Limit vs IOUT and Temperature
Figure 6-24. Line Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
15
12.5
10
5
24
18
12
6
3
VOUT
VIN
4.5
4
2.4
1.8
1.2
0.6
0
7.5
5
3.5
3
VOUT
VIN
2.5
0
2.5
2
-2.5
-5
1.5
1
0
-7.5
-10
0.5
0
-6
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
0
100
200
Time (ms)
300
400
500
VOUT = 3.3 V, IOUT = 300 mA, slew rate = 1 V/µs
VOUT = 1.2 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = 25℃
Figure 6-25. Line Transient
Figure 6-26. Line Transient
24
18
12
6
3
24
3
VOUT
VIN
VOUT
VIN
2.4
1.8
1.2
0.6
0
18
12
6
2.4
1.8
1.2
0.6
0
0
0
-6
-6
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 1.2 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = -40℃
VOUT = 1.2 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = 150℃
Figure 6-27. Line Transient
Figure 6-28. Line Transient
24
3
24
3
VOUT
VIN
VOUT
VIN
18
12
6
2.4
1.8
1.2
0.6
0
18
12
6
2.4
1.8
1.2
0.6
0
0
0
-6
-6
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 1.2 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = 25℃
VOUT = 1.2 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = -40℃
Figure 6-29. Line Transient
Figure 6-30. Line Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
24
18
12
6
3
20
15
10
5
3.2
2.4
1.6
0.8
0
VOUT
VIN
VOUT
VIN
2.4
1.8
1.2
0.6
0
0
0
-5
-0.8
-1.6
-6
-10
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 1.2 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = 150℃
VOUT = 1.2 V, IOUT = 300 mA, slew rate = 1 V/µs, TJ = 25℃
Figure 6-31. Line Transient
Figure 6-32. Line Transient
20
15
10
5
3.2
2.4
1.6
0.8
0
20
3.2
2.4
1.6
0.8
0
VOUT
VIN
VOUT
VIN
15
10
5
0
0
-5
-0.8
-1.6
-5
-0.8
-1.6
-10
-10
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 1.2 V, IOUT = 300 mA, slew rate = 1 V/µs, TJ = -40℃
VOUT = 1.2 V, IOUT = 300 mA, slew rate = 1 V/µs, TJ = 150℃
Figure 6-33. Line Transient
Figure 6-34. Line Transient
35
30
25
20
15
10
5
5.4
4.8
4.2
3.6
3
35
30
25
20
15
10
5
5.4
4.8
4.2
3.6
3
VOUT
VIN
VOUT
VIN
2.4
1.8
1.2
0.6
0
2.4
1.8
1.2
0.6
0
0
0
-5
-5
-10
-10
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 3.3 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = 25℃
VOUT = 3.3 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = -40℃
Figure 6-35. Line Transient
Figure 6-36. Line Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
35
30
25
20
15
10
5
5.4
4.8
4.2
3.6
3
35
30
25
20
15
10
5
5.4
4.8
4.2
3.6
3
VOUT
VIN
VOUT
VIN
2.4
1.8
1.2
0.6
0
2.4
1.8
1.2
0.6
0
0
0
-5
-5
-10
-10
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 3.3 V, IOUT = 50 mA, slew rate = 1 V/µs, TJ = 150℃
VOUT = 3.3 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = 25℃
Figure 6-37. Line Transient
Figure 6-38. Line Transient
35
5.4
4.8
4.2
3.6
3
35
5.4
4.8
4.2
3.6
3
VOUT
VIN
VOUT
VIN
30
25
20
15
10
5
30
25
20
15
10
5
2.4
1.8
1.2
0.6
0
2.4
1.8
1.2
0.6
0
0
0
-5
-5
-10
-10
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 3.3 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = -40℃
VOUT = 3.3 V, IOUT = 100 mA, slew rate = 1 V/µs, TJ = 150℃
Figure 6-39. Line Transient
Figure 6-40. Line Transient
40
2400
2100
1800
1500
1200
900
40
20
2400
2100
1800
1500
1200
900
VOUT
IOUT
VOUT
IOUT
20
0
0
-20
-40
-60
-80
-100
-120
-20
-40
-60
-80
-100
-120
600
600
300
300
0
0
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
0
2.5
5
7.5
10
Time (ms)
12.5
15
17.5
20
VIN = 5.5 V, VOUT = 5.0 V, IOUT slew rate = 1 A/µs
VIN = 5.5 V, VOUT = 5.0 V, IOUT slew rate = 1 A/µs
Figure 6-41. IOUT Transient From 1 mA to 300 mA
Figure 6-42. IOUT Transient From 1 mA to 300 mA
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
60
50
40
30
20
10
0
2400
2100
1800
1500
1200
900
40
20
2400
2100
1800
1500
1200
900
VOUT
IOUT
VOUT
IOUT
0
-20
-40
-60
-80
-100
-120
600
600
-10
-20
300
300
0
0
0
2.5
5
7.5
10
Time (ms)
12.5
15
17.5
20
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
VIN = 5.5 V, VOUT = 5.0 V, IOUT slew rate = 1 A/µs
Figure 6-43. IOUT Transient From 300 mA to 1 mA
VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 1 A/µs
Figure 6-44. IOUT Transient From 1 mA to 300 mA
40
20
2400
60
50
40
30
20
10
0
2400
VOUT
IOUT
VOUT
IOUT
2100
1800
1500
1200
900
600
300
0
2100
1800
1500
1200
900
600
300
0
0
-20
-40
-60
-80
-100
-120
-10
-20
0
2.5
5
7.5
10
Time (ms)
12.5
15
17.5
20
0
2.5
5
7.5
10
Time (ms)
12.5
15
17.5
20
VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 1 A/µs
Figure 6-45. IOUT Transient From 1-mA to 300-mA Rising Edge
VIN = 3.8 V, VOUT = 3.3 V, IOUT slew rate = 0.5 A/µs
Figure 6-46. IOUT Transient From 1-mA to 300-mA Falling Edge
20
600
500
400
300
200
100
0
20
600
500
400
300
200
100
0
VOUT
IOUT
VOUT
IOUT
10
10
0
0
-10
-20
-30
-40
-10
-20
-30
-40
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 1.2 V, IOUT = 0 mA to 100 mA , IOUT slew rate = 1 A/µs,
VOUT = 1.2 V, IOUT = 0 mA to 100 mA , IOUT slew rate = 1 A/µs,
TJ = 25℃
TJ = -40℃
Figure 6-47. Load Transient
Figure 6-48. Load Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
20
600
500
400
300
200
100
0
40
3000
2400
1800
1200
600
VOUT
IOUT
VOUT
IOUT
10
20
0
0
-10
-20
-30
-40
-20
-40
-60
0
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 1.2 V, IOUT = 0 mA to 100 mA , IOUT slew rate = 1 A/µs,
VOUT = 1.2 V, IOUT = 0 mA to 300 mA , IOUT slew rate = 1 A/µs,
TJ = 150℃
TJ = 25℃
Figure 6-49. Load Transient
Figure 6-50. Load Transient
40
20
3000
2400
1800
1200
600
60
20
2400
1800
1200
600
0
VOUT
IOUT
VOUT
IOUT
0
-20
-20
-40
-60
-60
0
-100
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 1.2 V, IOUT = 0 mA to 300 mA , IOUT slew rate = 1 A/µs,
VOUT = 1.2 V, IOUT = 0 mA to 300 mA , IOUT slew rate = 1 A/µs,
TJ = -40℃
TJ = 150℃
Figure 6-51. Load Transient
Figure 6-52. Load Transient
10
5
600
500
400
300
200
100
0
10
5
600
500
400
300
200
100
0
VOUT
IOUT
VOUT
IOUT
0
0
-5
-5
-10
-15
-20
-10
-15
-20
0
40
80
120
Time (ms)
160
200
0
40
80
120
Time (ms)
160
200
VOUT = 1.2 V, IOUT = 90 mA to 200 mA,
VOUT = 1.2 V, IOUT = 90 mA to 200 mA,
IOUT slew rate = 1 A/µs, TJ = 25℃
IOUT slew rate = 1 A/µs, TJ = -40℃
Figure 6-53. Load Transient
Figure 6-54. Load Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
10
600
500
400
300
200
100
0
30
20
800
700
600
500
400
300
200
100
0
VOUT
IOUT
VOUT
IOUT
5
10
0
0
-5
-10
-20
-30
-40
-50
-10
-15
-20
0
40
80
120
Time (ms)
160
200
0
100
200
Time (ms)
300
400
500
VOUT = 1.2 V, IOUT = 90 mA to 200 mA,
VOUT = 3.3 V, IOUT = 0 mA to 100 mA,
IOUT slew rate = 1 A/µs, TJ = 150℃
IOUT slew rate = 1 A/µs, TJ = 25℃
Figure 6-55. Load Transient
Figure 6-56. Load Transient
30
20
800
700
600
500
400
300
200
100
0
30
20
1000
900
800
700
600
500
400
300
200
100
0
VOUT
IOUT
VOUT
IOUT
10
10
0
0
-10
-20
-30
-40
-50
-60
-70
-10
-20
-30
-40
-50
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 3.3 V, IOUT = 0 mA to 100 mA, IOUT slew rate = 1 A/µs,
VOUT = 3.3 V, IOUT = 0 mA to 100 mA, IOUT slew rate = 1 A/µs,
TJ = -40℃
TJ = 150℃
Figure 6-57. Load Transient
Figure 6-58. Load Transient
50
30
1400
1200
1000
800
600
400
200
0
50
30
1400
1200
1000
800
600
400
200
0
VOUT
IOUT
VOUT
IOUT
10
10
-10
-30
-50
-70
-90
-10
-30
-50
-70
-90
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 3.3 V, IOUT = 0 mA to 300 mA, IOUT slew rate = 1 A/µs,
VOUT = 3.3 V, IOUT = 0 mA to 300 mA, IOUT slew rate = 1 A/µs,
TJ = 25℃
TJ = -40℃
Figure 6-59. Load Transient
Figure 6-60. Load Transient
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
50
30
1600
1400
1200
1000
800
600
400
200
0
15
10
5
800
700
600
500
400
300
200
100
0
VOUT
IOUT
VOUT
IOUT
10
-10
-30
-50
-70
-90
-110
0
-5
-10
-15
-20
-25
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 3.3 V, IOUT = 0 mA to 300 mA, IOUT slew rate = 1 A/µs,
VOUT = 3.3 V, IOUT = 90 mA to 200 mA,
TJ = 150℃
IOUT slew rate = 1 A/µs, TJ = 25℃
Figure 6-61. Load Transient
Figure 6-62. Load Transient
15
10
5
800
700
600
500
400
300
200
100
0
15
10
5
800
700
600
500
400
300
200
100
0
VOUT
IOUT
VOUT
IOUT
0
0
-5
-5
-10
-15
-20
-25
-10
-15
-20
-25
0
100
200
300
400
500
0
100
200
300
400
500
Time (ms)
Time (ms)
VOUT = 3.3 V, IOUT = 90 mA to 200 mA,
VOUT = 3.3 V, IOUT = 90 mA to 200 mA,
IOUT slew rate = 1 A/µs, TJ = -40℃
IOUT slew rate = 1 A/µs, TJ = 150℃
Figure 6-63. Load Transient
Figure 6-64. Load Transient
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
IOUT
1 mA
10 mA
50 mA
100 mA
200 mA
300 mA
IOUT
50 mA
100 mA
1 mA
10 mA
200 mA
300 mA
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VIN = 1.65 V, CIN = 0 µF, VOUT = 0.65 V
Figure 6-65. PSRR vs Frequency and IOUT
VIN = 2.2 V, CIN = 0 µF, VOUT = 1.2 V
Figure 6-66. PSRR vs Frequency and IOUT
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
90
80
70
60
50
40
30
20
10
0
90
80
70
60
50
40
30
20
10
0
COUT
4.7 mF
1.0 mF
10 mF
IOUT
50 mA
100 mA
1 mA
10 mA
200 mA
300 mA
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VIN = 4.3 V, CIN = 0 µF, VOUT = 3.3 V
VIN = 4.3 V, CIN = 0 µF, VOUT = 3.3 V, IOUT = 300 mA
Figure 6-67. PSRR vs Frequency and IOUT
Figure 6-68. PSRR vs Frequency and COUT
110
100
90
80
70
60
50
40
30
20
10
0
90
VDO (mV)
400 mV
500 mV
80
70
60
50
40
30
20
10
0
200 mV
300 mV
600 mV
700 mV
1 V
IOUT
50 mA
100 mA
1 mA
10 mA
200 mA
300 mA
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
CIN = 0 µF, VOUT = 3.3 V, IOUT = 300 mA
VIN = 6 V, CIN = 0 µF, VOUT = 5.0 V
Figure 6-69. PSRR vs Frequency and VDO
Figure 6-70. PSRR vs Frequency and IOUT
90
80
70
60
50
40
30
20
10
0
5
COUT
4.7 µF
(VOUT), (mVRMS
)
3
2
1.0 µF
10 µF
(1.2 V), (29.6)
(0.65V), (40.6)
(3.3 V), (75.8)
(5.0 V), (110.4)
1
0.5
0.3
0.2
0.1
0.05
0.03
0.02
0.01
0.005
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VIN = 6 V, CIN = 0 µF, VOUT = 5.0 V, IOUT = 300 mA
VIN = VOUT(nom) + 1 V, IOUT = 300 mA,
VRMS BW = 10 Hz to 100 kHz
Figure 6-71. PSRR vs Frequency and COUT
Figure 6-72. Output Noise vs Frequency and VOUT
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
5
10
5
(CFF (nF)), (mVRMS
)
(CFF (nF)), (mVRMS)
(Open), (110.4)
(1), (91.1)
3
2
(Open), (75.8)
(1), (62.3)
2
1
1
(4.7), (54.7)
(10), (49.7)
(100), (37.6)
(4.7), (79.2)
(10), (70.7)
(100), (42.1)
0.5
0.5
0.3
0.2
0.2
0.1
0.1
0.05
0.05
0.03
0.02
0.02
0.01
0.01
0.005
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
VIN = 4.3 V, VOUT = 3.3 V, IOUT = 300 mA,
VRMS BW = 10 Hz to 100 kHz
VIN = 6 V, VOUT = 5.0 V, IOUT = 300 mA,
VRMS BW = 10 Hz to 100 kHz
Figure 6-73. Output Noise vs Frequency and CFF
Figure 6-74. Output Noise vs Frequency and CFF
8
7
40
8
7
40
20
20
6
0
6
0
5
-20
-40
-60
-80
-100
-120
-140
5
-20
-40
-60
-80
-100
-120
-140
4
4
VIN
VEN
VOUT
IIN
VIN
VEN
VOUT
IIN
3
3
2
2
1
1
0
0
-1
-1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
VIN = 5.5 V, CIN = 0 µF, COUT = 1 µF, VOUT = 5.0 V,
IOUT = 0 mA
VIN = VEN = 5.5 V, CIN = 0 µF, COUT = 1 µF, VOUT = 5.0 V,
IOUT = 0 mA
Figure 6-75. Start-Up Inrush Current With
COUT = 1 µF
Figure 6-76. Start-Up Inrush Current With
COUT = 1 µF
8
7
6
5
4
3
2
1
0
160
80
7
6
280
Input Voltage
Enable Voltage
Output Voltage
Output Current
240
200
160
120
80
0
5
-80
-160
4
3
-240
-320
-400
-480
-560
VIN
VEN
VOUT
IIN
2
1
40
0
0
-1
-1
-40
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ms)
VIN = 5.5 V, CIN = 0 µF, COUT = 4.7 µF, VOUT = 5.0 V,
IOUT = 0 mA
VIN = 5 V, CIN = 1 µF, COUT = 10 µF, VOUT = 1.2 V,
IOUT = 500 mA
Figure 6-77. Start-Up Inrush Current With
COUT = 4.7 µF
Figure 6-78. Start Up at –40°C
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6.6 Typical Characteristics (continued)
at operating temperature TJ = 25°C, IOUT = 1 mA, VEN = 1.0 V, CIN = 1.0 µF, COUT = 1.0 μF, and VIN = VOUT(NOM) + 0.5 V or
1.65 V (whichever is greater), unless otherwise noted; typical values are at TJ = 25°C
7
6
280
240
200
160
120
80
7
6
280
240
200
160
120
80
Input Voltage
Enable Voltage
Output Voltage
Output Current
Input Voltage
Enable Voltage
Output Voltage
Output Current
5
5
4
4
3
3
2
2
1
40
1
40
0
0
0
0
-1
-40
-1
-40
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ms)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (ms)
VIN = 5 V, CIN = 1 µF, COUT = 10 µF, VOUT = 1.2 V,
IOUT = 500 mA
VIN = 5 V, CIN = 1 µF, COUT = 10 µF, VOUT = 1.2 V,
IOUT = 500 mA
Figure 6-79. Start Up at 25°C
Figure 6-80. Start Up at 150°C
5
2
1
OFF
0.5
0.2
0.1
0.05
Stable region
0.02
0.01
ON
0.005
0.002
0.001
0.0005
0.5
1
2
3 4 567 10
20 30 50 70100 200
500
-50 -25
0
25
50
75 100 125 150 175 200
COUT (mF)
Temperature (èC)
VIN = 5 V, CIN = 1 µF, COUT = 10 µF, VOUT = 1.2 V,
IOUT = 500 mA
COUT denotes nominal capacitor size
(not effective capacitance)
Figure 6-81. Thermal Shutdown Activation
Figure 6-82. ESR vs COUT
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7 Detailed Description
7.1 Overview
The TPS784-Q1 is an ultra low-dropout, high PSRR, high-accuracy linear voltage regulator that is optimized for
excellent transient performance. These characteristics make the device ideal for most automotive applications.
This regulator offers foldback current limit, output enable, active discharge, undervoltage lockout (UVLO), and
thermal protection.
7.2 Functional Block Diagrams
Current
Limit
IN
OUT
1.2-V
Bandgap
120 Ω
UVLO
FB
Internal
Controller
Thermal
Shutdown
GND
EN
Figure 7-1. Adjustable Version Block Diagram
Current
Limit
IN
OUT
1.2-V
Bandgap
2.18 Mꢀ
120 Ω
UVLO
2.42 Mꢀ
550 kꢀ
Internal
Controller
Thermal
Shutdown
GND
EN
Figure 7-2. Fixed Version Block Diagram
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7.3 Feature Description
7.3.1 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with
the output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL).
When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the
output voltage approaches GND. When the output is shorted, the device supplies a typical current called the
short-circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 0.4 × VOUT(NOM)
.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered,
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 7-3 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0 V
IOUT
IRATED
0 mA
ISC
ICL
Figure 7-3. Foldback Current Limit
7.3.2 Output Enable
The enable pin (EN) is active high. Enable the device by forcing the voltage of the enable pin to exceed the
minimum EN pin high-level input voltage (see the Electrical Characteristics table). Turn off the device by forcing
the voltage of the enable pin to drop below the maximum EN pin low-level input voltage (see the Electrical
Characteristics table). If shutdown capability is not required, connect EN to IN.
This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.
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7.3.3 Active Discharge
The device has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when the device is
disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin.
Do not rely on the active discharge circuit to discharge the output voltage after the input supply has collapsed
because reverse current can possibly flow from the output to the input. This reverse current flow can cause
damage to the device, especially when a large output capacitor is used. Limit reverse current to no more than
5% of the device rated current for a short period of time.
7.3.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum
operational voltage range, and ensures that the device shuts down when the input supply collapses. Figure
7-4 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the
following parts:
•
•
•
Region A: The device does not start until the input reaches the UVLO rising threshold.
Region B: Normal operation, regulating device.
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device remains enabled.
•
•
Region D: Normal operation, regulating device.
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
•
•
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 7-4. Typical UVLO Operation
7.3.5 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a
switch. The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed
output voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than
the nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. The following equation calculates the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
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7.3.6 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can
be high from large VIN – VOUT voltage drops across the device or from high inrush currents charging large
output capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 7-1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
The output current is less than the current limit (IOUT < ICL)
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
)
•
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased
to less than the enable falling threshold
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during start up), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum
EN pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is
turned off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
The device requires an input capacitor of 1.0 µF or larger as specified in the Recommended Operating
Conditions table for stability. A higher value capacitor may be necessary if large, fast rise-time load or line
transients are anticipated or if the device is located several inches from the input power source.
The device also requires an output capacitor of 1.0 µF or larger as specified in the Recommended Operating
Conditions table for stability. Dynamic performance of the device is improved by using a higher capacitor than
the minimum output capacitor.
8.1.3 Adjustable Device Feedback Resistors
The device requires external feedback divider resistors to set the output voltage. Figure 8-1 shows how the
output voltage of an adjustable device can be configured from 1.2 V to 5.5 V by using a resistor divider network.
Feed-Forward capacitor CFF is not required for stability (Optional)
VIN
OUT
VOUT
COUT
IN
CFF
CIN
R1
R2
FB
TPS784-Q1
GND
EN
GND
VEN
GND
Figure 8-1. Adjustable Operation
Equation 2 calculates the values of the R1 and R2 resistors to set the output voltage:
VOUT = VFB × (1 + R1 / R2) + IFB × R1
(2)
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To disregard the effect of the FB pin current error term in Equation 2 and to achieve best accuracy, choose
R2 to be equal to or smaller than 550 kΩ so that the current flowing through R1 and R2 is at least 100 times
larger than the IFB current listed in the Electrical Characteristics table. Lowering the value of R2 increases the
immunity against noise injection. Increasing the value of R2 reduces the quiescent current for achieving higher
efficiency at low load currents. Equation 3 calculates the setting that provides the maximum feedback divider
series resistance.
(R1 + R2) ≤ VOUT / (IFB × 100)
(3)
8.1.4 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in Figure
8-2 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.
tAt
tCt
tDt
tEt
tGt
tHt
B
F
Figure 8-2. Load Transient Waveform
During transitions from a light load to a heavy load, the:
•
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C)
•
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
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8.1.5 Exiting Dropout
Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up.
As with other LDOs, the output can overshoot on recovery from these conditions. A ramping input supply causes
an LDO to overshoot on start-up, as shown in Figure 8-3, when the slew rate and voltage levels are in the
correct range. Use an enable signal to avoid this condition.
Input Voltage
Response time for
LDO to get back into
regulation.
Load current discharges
output voltage.
VIN = VOUT(nom) + VDO
Output Voltage
Dropout
VOUT = VIN - VDO
Output Voltage in
normal regulation.
Time
Figure 8-3. Start-Up Into Dropout
Line transients out of dropout can also cause overshoot on the output of the regulator. These overshoots are
caused by the error amplifier having to drive the gate capacitance of the pass element and bring the gate back to
the correct voltage for proper regulation. Figure 8-4 illustrates what is happening internally with the gate voltage
and how overshoot can be caused during operation. When the LDO is placed in dropout, the gate voltage (VGS
)
is pulled all the way down to ground to give the pass device the lowest on-resistance as possible. However, if
a line transient occurs when the device is in dropout, the loop is not in regulation and can cause the output to
overshoot until the loop responds and the output current pulls the output voltage back down into regulation. If
these transients are not acceptable, then continue to add input capacitance in the system until the transient is
slow enough to reduce the overshoot.
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Transient response
time of the LDO
Input Voltage
Load current
discharges
output
voltage
Dropout
VOUT = VIN - VDO
Output Voltage
VDO
Output Voltage in
normal regulation
Time
VGS voltage
(pass device
fully off)
Input Voltage
VGS voltage for
normal operation
VGS voltage for
normal operation
Gate Voltage
VGS voltage in
dropout (pass device
fully on)
Time
Figure 8-4. Line Transients From Dropout
8.1.6 Dropout Voltage
The device uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation.
8.1.7 Reverse Current
As with most LDOs, excessive reverse current can damage this device.
Reverse current flows through the body diode on the pass element instead of the normal conducting channel.
At high magnitudes, this current flow degrades the long-term reliability of the device as a result of one of the
following conditions:
•
•
•
Degradation caused by electromigration
Excessive heat dissipation
Potential for a latch-up condition
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Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute
maximum rating of VOUT > VIN + 0.3 V:
•
•
•
If the device has a large COUT and the input supply collapses with little or no load current
The output is biased when the input supply is not established
The output is biased above the input supply
If reverse current flow is expected in the application, external protection must be used to protect the device.
Figure 8-5 shows one approach of protecting the device.
Schottky Diode
Internal Body Diode
IN
OUT
Device
COUT
CIN
GND
Figure 8-5. Example Circuit for Reverse Current Protection Using a Schottky Diode
8.1.8 Feed-Forward Capacitor (CFF)
For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin
to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability.
Recommended CFF values are listed in the Recommended Operating Conditions table. A higher capacitance
CFF can be used; however, the startup time increases. For a detailed description of CFF tradeoffs, see the Pros
and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.
8.1.9 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 4 to approximate PD:
PD = (VIN – VOUT) × IOUT
(4)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS784-Q1 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 5, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 6 rearranges Equation 5 for output current.
TJ = TA + (RθJA × PD)
(5)
(6)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location
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of the planes. The RθJA recorded in the Recommended Operating Conditions table is determined by the
JEDEC standard, PCB, and copper-spreading area, and is only used as a relative measure of package thermal
performance. For a well-designed thermal layout, RθJA is actually the sum of the VSON package junction-to-case
(bottom) thermal resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.9.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 7 and are given in the Recommended Operating Conditions table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
(7)
where:
•
•
•
PD is the power dissipated as explained in Equation 4
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
8.1.9.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 8-6 and can be
separated into the following parts:
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Voltage section for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
– The shape of the slope is given by Equation 6. The slope is nonlinear because the maximum rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN
VOUT increases the output current must decrease.
–
•
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
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Figure 8-6 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
RθJA as given in the Recommended Operating Conditions table.
Output current limited
by dropout
Rated output
current
Output current limited by thermals
Limited by
minimum VIN
Limited by
maximum VIN
VIN œ VOUT (V)
Figure 8-6. Region Description of Continuous Operation Regime
8.1.9.3 Power Dissipation versus Ambient Temperature
Figure 8-7 is based off of a JESD51-7 four-layer high-K board. The allowable power dissipation was estimated
using the following equation. As disscussed in the An empirical analysis of the impact of board layout on
LDO thermal performance application report, thermal dissipation can be improved in the JEDEC high-K layout
by adding top layer copper and increasing the number of thermal vias. If a good thermal layout is used, the
allowable thermal dissipation can be improved by up to 50%.
6 + 4à,# T 2& Q 150 °%
#
(8)
1.6
DRB Package
DBV Package
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-40
-20
0
20
40
60
80
100 120 140
Ambient Temerature (èC)
Figure 8-7. Allowable Power Dissipation
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8.2 Typical Application
VIN
VOUT
IN
OUT
IN
OUT
CIN
COUT
COUT
DC/DC
Converter
TPS784-Q1
GND
GND
EN
GND
GND
VEN
GND
GND
Figure 8-8. Operation From a DC/DC Converter
8.2.1 Design Requirements
Table 8-1 summarizes the design requirement for this application.
Table 8-1. Design Parameters
PARAMETER
DESIGN REQUIREMENT
Input voltage
Output voltage
3.8 V
3.3 V, ±1.5%
100 mA
10 µF
Output load
Output capacitor
Maximum ambient temperature
85°C
8.2.2 Detailed Design Procedure
For this design example, the 3.3-V, fixed-version device is selected. The device is powered of a DC/DC
converter connected to a battery. A 500-mV headroom between VIN and VOUT is used to keep the device within
the dropout voltage specification and to ensure the device stays in regulation under all load and temperature
conditions for this design.
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8.2.3 Application Curves
A 10-µF capacitor is used to reduce overshoot and undershoot of output voltage during load transients with
ramps rates greater than 0.5 A/µs. Figure 8-9 and Figure 8-10 show captures of load transient behavior for this
application.
50
40
1000
900
800
700
600
500
400
300
200
100
0
50
40
1000
900
800
700
600
500
400
300
200
100
0
VOUT
IOUT
VOUT
IOUT
30
30
20
20
10
10
0
0
-10
-20
-30
-40
-50
-10
-20
-30
-40
-50
0
50 100 150 200 250 300 350 400 450 500
Time (ms)
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
VIN = 3.8 V, VOUT = 3.3 V, COUT = 10 µF,
IOUT slew rate = 1 A/µs
VIN = 3.8 V, VOUT = 3.3 V, COUT = 10 µF,
IOUT slew rate = 1 A/µs
Figure 8-9. IOUT Transient From 0 mA to 100 mA
Figure 8-10. IOUT Transient From 1 mA to 100 mA
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.65 V to 6.0 V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 0.5 V. TI requires using a 1-µF or greater
input capacitor to reduce the impedance of the input supply, especially during transients.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections in order to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Only place tented thermal vias directly beneath the thermal pad of the DRB package. An untented via can
wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a
compromised solder joint on the thermal pad.
10.1.1 Additional Layout Considerations
The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that may couple
undesirable signals from nearby components (especially from logic and digital devices, such as microcontrollers
and microprocessors); these capacitively-coupled signals may produce undesirable output voltage transients. In
these cases, TI recommends using a fixed-voltage version of the device, or isolating the FB node by placing a
copper ground plane on the layer directly underneath the LDO circuitry and FB pin to minimize any undesirable
signal coupling.
110
100
90
80
70
60
50
40
30
20
110
100
90
80
70
60
50
40
30
20
1oz PCB
2oz PCB
1oz PCB
2oz PCB
0
20
40
60
80
100
0
20
40
60
80
100
PCB Copper Area (cm2)
PCB Copper Area (cm2)
4-layer PCB
2-layer PCB
Figure 10-1. Junction-to-Ambient Thermal
Resistance (RθJA) vs PCB Copper Area
Figure 10-2. Junction-to-Ambient Thermal
Resistance (RθJA) vs PCB Copper Area
40
40
1oz PCB
2oz PCB
1oz PCB
2oz PCB
35
30
25
20
15
35
30
25
20
15
0
20
40
60
80
100
0
10
20
30
40
50
60
70
80
90 100
PCB Cuppoer Area (cm2)
PCB Copper Area (cm2)
4-layer PCB
2-layer PCB
Figure 10-3. Junction-to-Board Characterization
Parameter (ψJB) vs PCB Copper Area
Figure 10-4. Junction-to-Board Characterization
Parameter (ψJB) vs PCB Copper Area
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10.2 Layout Examples
COUT
COUT
CIN
CIN
R1 OUT
FB
1
2
3
4
8
7
6
5
IN
OUT
NC
1
2
3
4
8
7
6
5
IN
CFF
EN
NC
EN
NC
R2
NC
NC
NC
GND
NC
GND
GND PLANE
GND PLANE
Represents a thermal via
Represents a thermal via
Figure 10-6. Layout Example for the DRB Package
Fixed Version
Figure 10-5. Layout Example for the DRB Package
Adjustable Version
CIN
CIN
COUT
OUT
COUT
OUT
5
1
2
5
4
5
5
5
1
2
5
4
5
5
IN
GND
EN
IN
GND
EN
R1
R2
CFF
FB
5
5
5
5
NC
3
3
GND PLANE
GND PLANE
Figure 10-7. Layout Example for the DBV Package Figure 10-8. Layout Example for the DBV Package
Adjustable Version
Fixed Version
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 11-1. Device Nomenclature
PRODUCT(1) (2)
VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 285 = 2.85 V).
Z indicates the pinout of the device. If no letter is present, the EN pin is pin 7, if the B version is used,
EN is now pin 6.
TPS784xx(x)ZQ(W)yyyRQ1
yyy is the package designator.
W is used to denote a wettable flank package.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 0.65 V to 5.5 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, Universal Low-Dropout (LDO) Linear Voltage Regulator MultiPkgLDOEVM-823 Evaluation
Module user's guide
Texas Instruments, Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator
application report
Texas Instruments, An empirical analysis of the impact of board layout on LDO thermal performance
application report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS78401BQWDRBRQ1
TPS78401QDBVRQ1
TPS78401QWDRBRQ1
TPS784075QWDRBRQ1
TPS78408QDBVRQ1
TPS784105QWDRBRQ1
TPS78410QWDRBRQ1
TPS78411QWDRBRQ1
TPS78412BQWDRBRQ1
TPS78412QDBVRQ1
TPS78412QWDRBRQ1
TPS78415QDBVRQ1
TPS78415QWDRBRQ1
TPS78417QDBVRQ1
TPS78418BQWDRBRQ1
TPS78418QDBVRQ1
TPS78418QWDRBRQ1
TPS78425BQWDRBRQ1
TPS78425QDBVRQ1
TPS78425QWDRBRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SOT-23
SON
DRB
DBV
DRB
DRB
DBV
DRB
DRB
DRB
DRB
DBV
DRB
DBV
DRB
DBV
DRB
DBV
DRB
DRB
DBV
DRB
8
5
8
8
5
8
8
8
8
5
8
5
8
5
8
5
8
8
5
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
8401BQ
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
23JF
8401WQ
84075W
2BGF
SON
SOT-23
SON
84105W
8410WQ
8411WQ
8412BQ
23KF
SON
SON
SON
SOT-23
SON
8412WQ
23LF
SOT-23
SON
8415WQ
2BHF
SOT-23
SON
8418BQ
23MF
SOT-23
SON
8418WQ
8425BQ
23NF
SON
SOT-23
SON
8425WQ
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jan-2022
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS78428QDBVRQ1
TPS78429QDBVRQ1
TPS78430QDBVRQ1
TPS78430QWDRBRQ1
TPS78433BQWDRBRQ1
TPS78433QDBVRQ1
TPS78433QWDRBRQ1
TPS78450QDBVRQ1
TPS78450QWDRBRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SON
DBV
DBV
DBV
DRB
DRB
DBV
DRB
DBV
DRB
5
5
5
8
8
5
8
5
8
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
-40 to 150
23OF
23PF
23QF
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
8430WQ
8433BQ
23RF
SON
SOT-23
SON
8433WQ
2BIF
SOT-23
SON
8450WQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jan-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS784-Q1 :
Catalog : TPS784
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS78401QDBVRQ1
TPS78408QDBVRQ1
TPS78412QDBVRQ1
TPS78415QDBVRQ1
TPS78417QDBVRQ1
TPS78418QDBVRQ1
TPS78425QDBVRQ1
TPS78428QDBVRQ1
TPS78429QDBVRQ1
TPS78430QDBVRQ1
TPS78433QDBVRQ1
TPS78450QDBVRQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
3.2
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS78401QDBVRQ1
TPS78408QDBVRQ1
TPS78412QDBVRQ1
TPS78415QDBVRQ1
TPS78417QDBVRQ1
TPS78418QDBVRQ1
TPS78425QDBVRQ1
TPS78428QDBVRQ1
TPS78429QDBVRQ1
TPS78430QDBVRQ1
TPS78433QDBVRQ1
TPS78450QDBVRQ1
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
DBV
5
5
5
5
5
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
1 MAX
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
(0.2) TYP
6X 0.65
(0.19)
4
5
SYMM
9
2.5
2.3
1.95
1
8
0.36
0.26
8X
PIN 1 ID
(OPTIONAL)
0.1
0.05
C A B
C
SYMM
0.5
0.3
8X
4225036/A 06/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
(1.65)
8X (0.6)
8X (0.31)
SYMM
1
8
6X (0.65)
SYMM
9
(1.95) (2.4)
(0.95)
(R0.05) TYP
4
5
(Ø 0.2) VIA
TYP
(0.575)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
NON- SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225036/A 06/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
VSON - 1 mm max height
DRB0008J
PLASTIC QUAD FLAT PACK- NO LEAD
(2.8)
2X
(1.51)
8X (0.6)
8X (0.31)
SYMM
1
8
2X
(1.06)
6X (0.65)
SYMM
(1.95)
(0.63)
9
(R0.05) TYP
4
5
METAL
TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
81% PRINTED COVERAGE BY AREA
SCALE: 20X
4225036/A 06/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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