TPS78601 [TI]
ULTRALOW-NOISE, HIGH PSRR, FAST RF 1.5 A LOW-DROPOUT LINEAR REGULATORS; 超低噪声，高PSRR ，快速射频1.5低压差线性稳压器
| 型号： | TPS78601 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | ULTRALOW-NOISE, HIGH PSRR, FAST RF 1.5 A LOW-DROPOUT LINEAR REGULATORS |
| 文件： | 总17页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
ULTRALOW-NOISE, HIGH PSRR, FAST RF 1.5 A LOW-DROPOUT LINEAR
REGULATORS
FEATURES
DESCRIPTION
•
1.5 A Low-Dropout Regulator With Enable
The TPS786xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power supply rejection ratio (PSRR), ultralow noise,
fast start-up, and excellent line and load transient
responses in small outline, SOT223-6 and 5-pin
DDPAK packages. Each device in the family is
stable, with a small 1-µF ceramic capacitor on the
output. The family uses an advanced, proprietary
BiCMOS fabrication process to yield extremely low
dropout voltages (e.g., 390 mV at 1.5 A). Each device
achieves fast start-up times (approximately 50 µs with
a 0.001 µF bypass capacitor) while consuming very
low quiescent current (265 µA typical). Moreover,
when the device is placed in standby mode, the
supply current is reduced to less than 1 µA. The
TPS78630 exhibits approximately 48 µVRMS of output
voltage at 3.0 V output noise with a 0.1 µF bypass
capacitor. Applications with analog components that
are noise sensitive, such as portable RF electronics,
benefit from the high PSRR, low noise features, and
the fast response time.
•
Available in 1.8-V, 2.5-V, 2.8-V, 3-V, 3.3-V, and
Adjustable (1.2-V to 5.5-V)
•
•
•
•
•
•
High PSRR (49 dB at 10 kHz)
Ultralow Noise (48 µVRMS, TPS79630)
Fast Start-Up Time (50 µs)
Stable With a 1-µF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (390 mV at Full
Load, TPS78630)
•
6-Pin SOT223-6 and 5-Pin DDPAK Package
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth™, Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
TPS78630
TPS78630
DCQ PACKAGE
SOT223-6
(TOP VIEW)
RIPPLE REJECTION
vs
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
FREQUENCY
1
2
3
4
EN
IN
GND
OUT
NR
80
70
60
50
40
30
20
10
0
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
V
= 4 V
IN
V
= 5.5 V
= 2.2 µF
6
GND
IN
C
C
= 10 µF
C
C
OUT
= 0.01 µF
OUT
= 0.1 µF
I
= 1 mA
= 1.5 A
OUT
NR
NR
5
I
OUT
KTT (DDPAK) PACKAGE
(TOP VIEW)
I
= 1 mA
OUT
EN
1
2
IN
GND
OUT
NR
3
4
I
= 1.5 A
OUT
5
1
10
100
1k 10k 100k 1M 10M
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Bluetooth is a trademark of Bluetooth SIG, Inc.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2004, Texas Instruments Incorporated
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
AVAILABLE OPTIONS(1)
TRANSPORT MEDIA,
PRODUCT
VOLTAGE
PACKAGE
TJ
SYMBOL
PART NUMBER
QUANTITY
TPS78601DCQ
TPS78601DCQR
TPS78601KTT
TPS78618DCQ
TPS78618DCQR
TPS78618KTT
TPS78625DCQ
TPS78625DCQR
TPS78625KTT
TPS78628DCQ
TPS78628DCQR
TPS78628KTT
TPS78630DCQ
TPS78630DCQR
TPS78630KTT
TPS78633DCQ
TPS78633DCQR
TPS78633KTT
Tube, 78
SOT223-6
DDPAK
PS78601
TPS78601
PS78618
TPS78618
PS78625
TPS78625
PS78628
TPS78628
PS78630
TPS78630
PS78633
TPS78633
TPS78601
1.2 to 5.5 V
Tape and Reel, 2500
Reel, 500
Tube, 78
SOT223-6
DDPAK
TPS78618
TPS78625
TPS78628
TPS78630
TPS78633
1.8 V
2.5 V
2.8 V
3.0 V
3.3 V
Tape and Reel, 2500
Reel, 500
Tube 78
SOT223-6
DDPAK
Tape and Reel, 2500
Reel, 500
-40°C to 125°C
Tube 78
SOT223-6
DDPAK
Tape and Reel, 2500
Reel, 500
Tube 78
SOT223-6
DDPAK
Tape and Reel, 2500
Reel, 500
Tube 78
SOT223-6
DDPAK
Tape and Reel, 2500
Reel, 500
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
ABSOLUTE MAXIMUM RATINGS
over operating temperature (unless otherwise noted)(1)
VALUE
VIN range
-0.3 V to 6 V
-0.3 V to VIN + 0.3 V
6 V
VEN range
VOUT range
Peak output current
ESD rating, HBM
Internally limited
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range, Tstg
See Dissipation Ratings table
-40°C to 150°C
-65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
PACKAGE DISSIPATION RATINGS
PACKAGE
DDPAK
BOARD
High-K(1)
Low-K(2)
RΘJC
RΘJA
2 °C/W
15 °C/W
23 °C/W
53 °C/W
SOT223
(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-in x 3-in (7,5-cm x 7,5-cm), multilayer board with 1 ounce
internal power and ground planes and 2 ounce copper traces on top and bottom of the board.
(2) The JEDEC low-K (1s) board design used to derive this data was a 3-in x 3-in (7,5-cm x 7,5cm), two-layered board with 2 ounce copper
traces on top of the board.
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ = -40°C to 125°C), VEN = VIN, VIN = VOUT(nom) + 1 V, IOUT = 1mA,
COUT = 10µF, CNR = 0.01 µF, unless otherwise noted. Typical values are at 25°C.
PARAMETER
TEST CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNIT
V
(1)
Input voltage, VIN
Continuous output current IOUT
0
1.5
A
TPS78601
VFB
5.5 - VDO
1.836
2.55
V
TPS78618 0 µA < IOUT < 1.5 A
TPS78625 0 µA < IOUT < 1.5 A
TPS78628 0 µA < IOUT < 1.5 A
TPS78630 0 µA < IOUT < 1.5 A
2.8 V < VIN < 5.5 V
3.5 V < VIN < 5.5 V
3.8 V < VIN < 5.5 V
4 V < VIN < 5.5 V
4.3 V < VIN < 5.5 V
1.764
2.45
2.744
2.94
3.234
1.8
2.5
2.8
3
V
V
Output voltage
2.856
3.06
V
V
TPS78633 0 µA < IOUT < 1.5 A
3.3
5
3.366
12
V
(1)
Output voltage line regulation (∆VOUT%/VIN
)
VOUT + 1 V < VIN ≤ 5.5 V
%/V
mV
Load regulation (∆VOUT%/VOUT
)
0 µA < IOUT < 1.5 A
TJ = 25°C
7
TPS78628 IOUT = 1.5 A
TPS78630 IOUT = 1.5 A
TPS78633 IOUT = 1.5 A
VOUT = 0 V
410
390
340
580
550
510
4.2
385
1
Dropout voltage(2)
VIN = VOUT(nom) - 0.1 V
mV
Output current limit
Ground pin current
Shutdown current(3)
FB pin current
2.4
A
0 µA < IOUT < 1.5 A
260
µA
µA
µA
VEN = 0 V, 2.7 V < VIN < 5.5 V
FB = 1.8 V
0.07
1
f = 100 Hz, IOUT = 10 mA
f = 100 Hz, IOUT = 1.5 A
f = 10 kHz, IOUT = 1.5 A
f = 100 kHz, IOUT = 1.5 A
59
52
49
32
66
51
49
48
50
75
110
Power supply ripple rejection
TPS78630
dB
µVRMS
µs
CNR = 0.001 µF
CNR = 0.0047 µF
CNR = 0.01 µF
CNR = 0.1 µF
BW = 100 Hz to 100 kHz,
IOUT = 1.5 A
Output noise voltage (TPS78630)
Time, start-up (TPS78630)
CNR = 0.001 µF
CNR = 0.0047 µF
CNR = 0.01 µF
RL = 2 Ω, COUT = 1 µF
High-level enable input voltage
Low-level enable input voltage
EN pin current
2.7 V < VIN < 5.5 V
2.7 V < VIN < 5.5 V
VEN = 0
1.7
0
VIN
0.7
1
V
V
-1
µA
V
UVLO threshold
VCC rising
2.25
2.65
UVLO hysteresis
100
mV
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.
(2) Dropout is not measured for TPS78618 or TPS78625 since minimum VIN = 2.7 V.
(3) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
3
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
IN
OUT
Current
Sense
UVLO
SHUTDOWN
ILIM
R
1
_
GND
EN
+
FB
UVLO
R
2
Thermal
Shutdown
Quickstart
External to
the Device
Bandgap
Reference
1.225 V
250 kΩ
V
REF
V
IN
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
IN
OUT
UVLO
Current
Sense
GND
EN
SHUTDOWN
ILIM
R
1
_
+
UVLO
Thermal
Shutdown
R
2
Quickstart
R = 40k
2
Bandgap
Reference
1.225 V
250 kΩ
V
REF
V
IN
NR
Terminal Functions
TERMINAL
ADJ
DESCRIPTION
NAME
FIXED
NR
NA
5
An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a
low-pass filter to further reduce regulator noise.
EN
1
5
1
The EN terminal is an input which enables or shuts down the device. When EN goes to a logic high, the device
will be enabled. When the device goes to a logic low, the device is in shutdown mode.
FB
N/A This terminal is the feedback input voltage for the adjustable device.
GND
IN
3, Tab 3, Tab Regulator ground
2
4
2
4
Unregulated input to the device.
Output of the regulator.
OUT
4
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
TPS78630
OUTPUT VOLTAGE
vs
TPS78628
OUTPUT VOLTAGE
vs
TPS78628
GROUND CURRENT
vs
OUTPUT CURRENT
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.798
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
350
340
330
320
310
300
290
V
C
= 4 V
= 10 µF
OUT
= 25°C
V
C
= 3.8 V
V
= 3.8 V
IN
IN
IN
= 10 µF
C
OUT
= 10 µF
OUT
2.794
T
J
I
= 1 mA
OUT
2.790
I
= 1.5 A
OUT
2.786
I
= 1.5 A
OUT
I
= 1 mA
OUT
2.782
2.778
0.0
0.3
0.6
0.9
(A)
1.2
1.5
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
I
T
J
T
J
OUT
Figure 1.
Figure 2.
Figure 3.
TPS78630
TPS78630
TPS78630
OUTPUT SPECTRAL NOISE DEN-
OUTPUT SPECTRAL NOISE DEN-
OUTPUT SPECTRAL NOISE DEN-
SITY
vs
FREQUENCY
SITY
vs
FREQUENCY
SITY
vs
FREQUENCY
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
V
C
C
= 5.5 V
V
C
C
= 5.5 V
V
= 5.5 V
IN
= 10 µF
OUT
= 1.5 A
IN
IN
= 2.2 µF
= 10 µF
C
I
OUT
= 0.1 µF
OUT
= 0.1 µF
NR
NR
OUT
I
= 1.5 A
OUT
C
NR
= 0.1 µF
C
NR
= 0.0047 µF
I
= 1 mA
C
NR
= 0.01 µF
OUT
C
= 0.001 µF
NR
I
= 1 mA
OUT
I
= 1.5 A
OUT
100
1k
10k
100k
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Figure 4.
Figure 5.
Figure 6.
5
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS78630
ROOT MEAN SQUARED OUTPUT
TPS78628
DROPOUT VOLTAGE
vs
TPS78630
NOISE
vs
BYPASS CAPACITANCE
RIPPLE REJECTION
vs
JUNCTION TEMPERATURE
FREQUENCY
80
70
60
50
40
30
20
10
0
600
500
400
300
200
100
0
80
70
60
50
40
30
20
10
0
V
C
C
= 4 V
V
C
= 2.7 V
= 10 µF
OUT
= 1.5 A
IN
IN
= 10 µF
OUT
= 0.01 µF
I
= 1 mA
I
OUT
NR
OUT
I
= 1.5 A
OUT
I
C
= 1.5 A
= 10 µF
OUT
OUT
BW = 100 Hz to 100 kHz
0.001 µF
0.0047 µF
0.01 µF
(µF)
0.1 µF
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
1
10
100
1k 10k 100k 1M 10M
C
NR
f (Hz)
T
J
Figure 7.
Figure 8.
Figure 9.
TPS78630
RIPPLE REJECTION
vs
TPS78630
TPS78630
RIPPLE REJECTION
vs
RIPPLE REJECTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
80
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
V
= 4 V
V
C
C
= 4 V
V
C
C
= 4 V
IN
= 2.2 µF
OUT
= 0.01 µF
NR
IN
IN
70
60
50
40
30
20
10
0
C
C
= 2.2 µF
= 10 µF
OUT
= 0.1 µF
OUT
= 0.1 µF
I
= 1 mA
I
= 1 mA
I
= 1 mA
= 1.5 A
OUT
OUT
OUT
NR
NR
I
OUT
I
= 1.5 A
OUT
I
= 1.5 A
OUT
0
1
1
10
100
1k 10k 100k 1M 10M
10
100
1k 10k 100k 1M 10M
1
10
100
1k 10k 100k 1M 10M
f (Hz)
f (Hz)
f (Hz)
Figure 10.
Figure 11.
Figure 12.
TPS78618
LINE TRANSIENT RESPONSE
TPS78630
LINE TRANSIENT RESPONSE
TPS78628
LOAD TRANSIENT RESPONSE
5
4
3
2
2
1
0
6
5
4
3
V
C
C
= 3.8 V
I
C
C
= 1.5 A
IN
di
dt
dv
dt
OUT
1.5 A
ms
1 V
ms
dv
dt
1 V
ms
−1
I
C
C
= 1.5 A
= 10 µF
OUT
= 0.01 µF
OUT
+
+
+
= 10 µF
= 10 µF
OUT
= 0.01 µF
OUT
= 0.01 µF
NR
NR
60
30
150
75
80
40
NR
0
0
0
−30
−60
−75
−150
−40
−80
0
20 40 60 80 100 120 140 160 180 200
0
100 200 300 400 500 600 700 800 900 1000
0
20 40 60 80 100 120 140 160 180 200
t (µs)
t (µs)
t (µs)
Figure 13.
Figure 14.
Figure 15.
6
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS78630
DROPOUT VOLTAGE
vs
TPS78601
DROPOUT VOLTAGE
vs
TPS78625
POWER UP/POWER DOWN
OUTPUT CURRENT
INPUT VOLTAGE
600
500
400
300
200
100
0
4.0
3.5
3.0
2.5
500
450
400
V
R
C
= 2.5 V
= 1.6 Ω
= 0.01 µF
OUT
L
NR
T
= 125°C
= 25°C
J
T
= 125°C
J
350
300
250
200
150
100
50
T
J
T
J
= 25°C
2.0
1.5
1.0
0.5
0
T
= −40°C
J
V
IN
T
J
= −40°C
I
C
C
= 1.5 A
= 10 µF
OUT
= 0.01 µF
OUT
V
OUT
3
NR
0
0
200 400 600 800 1000 1200 1400
(mA)
0
1
2
4
5
6
7
8
9
10
2.5
3.0
3.5
4.0
(V)
4.5
5.0
I
V
200 µs/Div
OUT
IN
Figure 16.
Figure 17.
Figure 18.
TPS78630
TPS78630
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
MINIMUM REQUIRED INPUT VOLT-
EQUIVALENT SERIES RESISTANCE
EQUIVALENT SERIES RESISTANCE
AGE
vs
(ESR)
vs
(ESR)
vs
OUTPUT VOLTAGE
OUTPUT CURRENT
OUTPUT CURRENT
100
10
5.0
4.5
4.0
3.5
3.0
2.5
2.0
100
10
C
OUT
= 1 µF
C
OUT
= 2.2 µF
I
= 1.5 A
OUT
Region of
Instability
Region of
Instability
T
J
= 125°C
1
0.1
1
0.1
Region of Stability
Region of Stability
T
J
= −40°C
T
J
= 25°C
0.01
0.01
1
30
125
500
(mA)
1000
1500
1.5
2.0
2.5
3.0
(V)
3.5
4.0
1
30
125
500
(mA)
1000
1500
I
I
OUT
OUT
V
OUT
Figure 19.
Figure 20.
Figure 21.
7
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS (continued)
TPS78630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs
OUTPUT CURRENT
START-UP
100
3
2.75
2.50
2.25
2
V
C
= 4 V,
IN
C
OUT
= 10 µF
C
=
NR
= 10 µF,
OUT
0.0047 µF
I
= 1.5 A
IN
Region of
Instability
10
Enable
C
=
NR
0.001 µF
1.75
1.50
1.25
1
1
0.1
C
=
NR
0.01 µF
Region of Stability
0.75
0.50
0.25
0
0.01
0
100
200
300
400
500
600
1
30
125
500
(mA)
1000
1500
t (ns)
I
OUT
Figure 22.
Figure 23.
8
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
APPLICATION INFORMATION
flow out of the NR pin must be at a minimum,
because any leakage current creates an IR drop
across the internal resistor, thus creating an output
error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor
should be no more than 0.1-µf to ensure that it is fully
charged during the quickstart time provided by the
internal switch shown in the functional block diagram.
The TPS786xx family of low-dropout (LDO) regulators
has been optimized for use in noise-sensitive equip-
ment. The device features extremely low dropout
voltages, high PSRR, ultralow output noise, low
quiescent current (265 µA typically), and enable input
to reduce supply currents to less than 1 µA when the
regulator is turned off.
A typical application circuit is shown in Figure 24.
For example, the TPS78630 exhibits only 48 µVRMS
of output voltage noise using a 0.1-µF ceramic
bypass capacitor and a 10-µF ceramic output capaci-
tor. Note that the output starts up slower as the
bypass capacitance increases due to the RC time
constant at the bypass pin that is created by the
internal 250-kΩ resistor and external capacitor.
VIN
VOUT
IN
OUT
TPS786xx
GND
µ
1 µF
2.2 F
EN
NR
µ
0.01 F
Figure 24. Typical Application Circuit
Board Layout Recommendation to Improve
PSRR and Noise Performance
External Capacitor Requirements
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the ground pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
A 2.2-µF or larger ceramic input bypass capacitor,
connected between IN and GND and located close to
the TPS786xx, is required for stability and improves
transient response, noise rejection, and ripple rejec-
tion. A higher-value input capacitor may be necessary
if large, fast-rise-time load transients are anticipated
and the device is located several inches from the
power source.
Regulator Mounting
Like most low dropout regulators, the TPS786xx
requires an output capacitor connected between OUT
and GND to stabilize the internal control loop. The
minimum recommended capacitance is 1 µF. Any 1
µF or larger ceramic capacitor is suitable.
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat dissipation.
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS786xx has an NR
pin which is connected to the voltage reference
through a 250-kΩ internal resistor. The 250-kΩ
internal resistor, in conjunction with an external by-
pass capacitor connected to the NR pin, creates a
low pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
order for the regulator to operate properly, the current
Solder pad footprint recommendations for the devices
are presented in an application bulletin Solder Pad
Recommendations for Surface-Mount Devices, litera-
ture number AB-132, available from the TI web site
(www.ti.com).
9
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
–7
(3 x 10 ) x (R1 ) R2)
Programming the TPS78601 Adjustable LDO
Regulator
C1 +
(R1 x R2)
(3)
The output voltage of the TPS78601 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 25. The output voltage is
calculated using Equation 1:
The suggested value of this capacitor for several
resistor ratios is shown in the table below. If this
capacitor is not used (such as in a unity-gain con-
figuration), then the minimum recommended output
capacitor is 2.2 µF instead of 1 µF.
R1
R2
ǒ1 ) Ǔ
V
+ V
O
ref
(1)
Regulator Protection
where:
The TPS786xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (e.g.,
during power down). Current is conducted from the
output to the input and is not internally limited. If
extended reverse voltage operation is anticipated,
external limiting might be appropriate.
•
VREF = 1.2246 V typ (the internal reference
voltage)
Resistors R1 and R2 should be chosen for approxi-
mately 40-µA divider current. Lower value resistors
can be used for improved noise performance, but the
device wastes more power. Higher values should be
avoided, as leakage current at FB increases the
output voltage error. The recommended design pro-
cedure is to choose R2 = 30.1 kΩ to set the divider
current at 40 µA, C1 = 15 pF for stability, and then
calculate R1 using Equation 2:
The TPS786xx features internal current limiting and
thermal protection. During normal operation, the
TPS786xx limits output current to approximately 2.8
A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition
ends. While current limiting is designed to prevent
gross device failure, care should be taken not to
exceed the power dissipation ratings of the package.
If the temperature of the device exceeds approxi-
mately 165°C, thermal-protection circuitry shuts it
down. Once the device has cooled down to below
approximately 140°C, regulator operation resumes.
V
O
R1 +
* 1 R2
ǒ Ǔ
V
ref
(2)
In order to improve the stability of the adjustable
version, it is suggested that a small compensation
capacitor be placed between OUT and FB. The
approximate value of this capacitor can be calculated
using Equation 3:
OUTPUT VOLTAGE
VIN
VOUT
PROGRAMMING GUIDE
IN
OUT
TPS78601
2.2 µF
R1
R2
C1
OUTPUT
EN
NR
1 µF
VOLTAGE
1.8 V
R1
R2
C1
GND
F
FB
14.0 kΩ 30.1 kΩ 33 pF
57.9 kΩ 30.1 kΩ 15 pF
µ
0.01
3.6V
Figure 25. TPS78601 Adjustable LDO Regulator Programming
10
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
THERMAL INFORMATION
temperature due to the regulator's power dissipation.
The temperature rise is computed by multiplying the
maximum expected power dissipation by the sum of
the thermal resistances between the junction and the
case (RΘJC), the case to heatsink (RΘCS), and the
heatsink to ambient (RΘSA). Thermal resistances are
measures of how effectively an object dissipates
heat. Typically, the larger the device, the more
surface area available for power dissipation and the
lower the object's thermal resistance.
The amount of heat that an LDO linear regulator
generates is directly proportional to the amount of
power it dissipates during operation. All integrated
circuits have a maximum allowable junction tempera-
ture (TJMAX) above which normal operation is not
assured.
A
system designer must design the
operating environment so that the operating junction
temperature (TJ) does not exceed the maximum
junction temperature (TJMAX). The two main environ-
mental variables that a designer can use to improve
thermal performance are air flow and external
heatsinks. The purpose of this information is to aid
the designer in determining the proper operating
environment for a linear regulator that is operating at
a specific power level.
Figure 26 illustrates these thermal resistances for (a)
a SOT223 package mounted in a JEDEC low-K
board, and (b) a DDPAK package mounted on a
JEDEC high-K board.
Equation 5 summarizes the computation:
In general, the maximum expected power (PD(max)
consumed by a linear regulator is computed as
shown in Equation 4:
)
) P max x ǒR
θSAǓ
T
+ T
) R
) R
D
J
A
θJC
θCS
(5)
max + ǒVI(avg)
Ǔ
P
* V
I
) V
x I
The RΘJC is specific to each regulator as determined
by its package, lead frame, and die size provided in
the regulator's data sheet. The RΘSA is a function of
the type and size of heatsink. For example, black
body radiator type heatsinks can have RΘCS values
ranging from 5°C/W for very large heatsinks to
50°C/W for very small heatsinks. The RΘCS is a
function of how the package is attached to the
heatsink. For example, if a thermal compound is used
to attach a heatsink to a SOT223 package, RΘCS of
1°C/W is reasonable.
D
O(avg)
O(avg)
I(avg) (Q)
(4)
where:
•
•
•
•
VI(avg) is the average input voltage.
VO(avg) is the average output voltage.
IO(avg) is the average output current.
I(Q) is the quiescent current.
For most TI LDO regulators, the quiescent current is
insignificant compared to the average output current;
therefore, the term VI(avg) x I(Q) can be neglected. The
operating junction temperature is computed by adding
the ambient temperature (TA) and the increase in
T
J
A
A
CIRCUIT BOARD COPPER AREA
R
θ
JC
B
C
T
C
B
B
R
θ
θ
CS
A
C
R
SA
C
DDPAK Package
SOT223 Package
(a)
(b)
T
A
Figure 26. Thermal Resistances
11
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
Even if no external black body radiator type heatsink
is attached to the package, the board on which the
regulator is mounted provides some heatsinking
through the pin solder connections. Some packages,
like the DDPAK and SOT223 packages, use a copper
plane underneath the package or the circuit board's
ground plane for additional heatsinking to improve
their thermal performance. Computer-aided thermal
modeling can be used to compute very accurate
approximations of an integrated circuit's thermal per-
formance in different operating environments (e.g.,
different types of circuit boards, different types and
sizes of heatsinks, and different air flows, etc.). Using
these models, the three thermal resistances can be
combined into one thermal resistance between junc-
tion and ambient (RΘJA). This RΘJA is valid only for the
specific operating environment used in the computer
model.
R
max + (125 * 55)°Cń2.5 W + 28°CńW
θJA
(9)
From Figure 27, DDPAK Thermal Resistance vs
Copper Heatsink Area, the ground plane needs to be
1 cm2 for the part to dissipate 2.5 W. The operating
environment used in the computer model to construct
Figure 27 consisted of a standard JEDEC High-K
board (2S2P) with a 1 oz. internal copper plane and
ground plane. The package is soldered to a 2 oz.
copper pad. The pad is tied through thermal vias to
the 1 oz. ground plane. Figure 28 shows the side
view of the operating environment used in the com-
puter model.
40
No Air Flow
35
Equation 5 simplifies into Equation 6:
150 LFM
30
T
+ T ) P max x R
D
J
A
θJA
(6)
Rearranging Equation 6 gives Equation 7:
T –T
250 LFM
25
J
A
R
+
θJA
P max
D
(7)
Using Equation 6 and the computer model generated
curves shown in Figure 27 and Figure 30, a designer
can quickly compute the required heatsink thermal
resistance/board area for a given ambient tempera-
ture, power dissipation, and operating environment.
20
15
0.1
1
10
100
2
Copper Heatsink Area − cm
DDPAK Power Dissipation
The DDPAK package provides an effective means of
managing power dissipation in surface mount appli-
cations. The DDPAK package dimensions are pro-
vided in the Mechanical Data section at the end of
the data sheet. The addition of a copper plane
directly underneath the DDPAK package enhances
the thermal performance of the package.
Figure 27. DDPAK Thermal Resistance vs Copper
Heatsink Area
2 oz. Copper Solder Pad
with 25 Thermal Vias
1 oz. Copper
Power Plane
To illustrate, the TPS78625 in a DDPAK package
was chosen. For this example, the average input
voltage is 5 V, the output voltage is 2.5 V, the
average output current is 1 A, the ambient tempera-
ture 55°C, the air flow is 150 LFM, and the operating
environment is the same as documented below.
Neglecting the quiescent current, the maximum aver-
age power is shown in Equation 8:
1 oz. Copper
Ground Plane
Thermal Vias, 0.3 mm
Diameter, 1,5 mm Pitch
Figure 28. DDPAK Thermal Resistance
(
)
P max
5
2.5 V x 1 A
2.5 W
D
(8)
Substituting TJmax for TJ into Equation 6 gives
Equation 9:
12
TPS78601, TPS78618
TPS78625, TPS78628
TPS78630, TPS78633
www.ti.com
SLVS389D–SEPTEMBER 2002–REVISED OCTOBER 2004
From the data in Figure 29 and rearranging
Equation 6, the maximum power dissipation for a
different ground plane area and a specific ambient
temperature can be computed.
dissipate 800 mW. The operating environment used
to construct Figure 30 consisted of a board with 1 oz.
copper planes. The package is soldered to a 1 oz.
copper pad on the top of the board. The pad is tied
through thermal vias to the 1 oz. ground plane.
5
180
T
A
= 55°C
No Air Flow
160
250 LFM
4
3
140
120
100
150 LFM
80
60
40
No Air Flow
2
20
0
1
0.1
1
10
100
2
0.1
1
10
Copper Heatsink Area − cm
2
PCB Copper Area − in
Figure 29. Maximum Power Dissipation vs Copper
Heatsink Area
Figure 30. SOT223 Thermal Resistance vs PCB
Area
SOT223 Power Dissipation
From the data in Figure 30 and rearranging
Equation 6, the maximum power dissipation for a
different ground plane area and a specific ambient
temperature can be computed (see Figure 31).
The SOT223 package provides an effective means of
managing power dissipation in surface mount appli-
cations. The SOT223 package dimensions are pro-
vided in the Mechanical Data section at the end of
the data sheet. The addition of a copper plane
directly underneath the SOT223 package enhances
the thermal performance of the package.
6
T
A
= 25°C
5
4
To illustrate, the TPS78625 in a SOT223 package
was chosen. For this example, the average input
voltage is 3.3 V, the output voltage is 2.5 V, the
average output current is 1 A, the ambient tempera-
ture 55°C, no air flow is present, and the operating
environment is the same as documented below.
Neglecting the quiescent current, the maximum aver-
age power is calculated as shown in Equation 10:
2
4 in PCB Area
3
2
2
0.5 in PCB Area
(
)
P max
3.3
2.5 V x 1 A
800 mW
D
(10)
1
0
Substituting TJmax for TJ into Equation 6 gives
Equation 11:
R
max + (125 * 55)°Cń800 mW + 87.5°CńW
θJA
0
25
50
75
100
125
150
(11)
T
A
− Ambient Temperature − °C
From Figure 30, RΘJA vs PCB Copper Area, the
ground plane needs to be 0.55 in2 for the part to
Figure 31. SOT223 Power Dissipation
13
PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2004
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
TPS78601DCQ
TPS78601DCQR
TPS78601KTT
TPS78601KTTR
TPS78601KTTT
TPS78618DCQ
TPS78618DCQR
TPS78618KTT
TPS78618KTTR
TPS78618KTTT
TPS78625DCQ
TPS78625DCQR
TPS78625KTT
TPS78625KTTR
TPS78625KTTT
TPS78628DCQ
TPS78628DCQR
TPS78628KTT
TPS78628KTTR
TPS78628KTTT
TPS78630DCQ
TPS78630DCQR
TPS78630KTT
TPS78630KTTR
TPS78630KTTT
TPS78633DCQ
TPS78633DCQR
TPS78633KTT
TPS78633KTTR
TPS78633KTTT
ACTIVE
ACTIVE
SOP
SOP
PFM
PFM
PFM
SOP
SOP
PFM
PFM
PFM
SOP
SOP
PFM
PFM
PFM
SOP
SOP
PFM
PFM
PFM
SOP
SOP
PFM
PFM
PFM
SOP
SOP
PFM
PFM
PFM
DCQ
DCQ
KTT
KTT
KTT
DCQ
DCQ
KTT
KTT
KTT
DCQ
DCQ
KTT
KTT
KTT
DCQ
DCQ
KTT
KTT
KTT
DCQ
DCQ
KTT
KTT
KTT
DCQ
DCQ
KTT
KTT
KTT
6
6
5
5
5
6
6
5
5
5
6
6
5
5
5
6
6
5
5
5
6
6
5
5
5
6
6
5
5
5
49
2500
OBSOLETE
ACTIVE
500
50
ACTIVE
ACTIVE
78
ACTIVE
2500
OBSOLETE
ACTIVE
500
50
ACTIVE
ACTIVE
78
ACTIVE
2500
OBSOLETE
ACTIVE
500
50
ACTIVE
ACTIVE
78
ACTIVE
2500
OBSOLETE
ACTIVE
500
50
ACTIVE
ACTIVE
78
ACTIVE
2500
OBSOLETE
ACTIVE
500
50
ACTIVE
ACTIVE
78
ACTIVE
2500
OBSOLETE
ACTIVE
500
50
ACTIVE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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