TPS79601DRBTG4 [TI]
Ultralow-Noise, High PSRR, Fast, RF, 1A Low-Dropout Linear Regulators; 超低噪声，高PSRR ，快速， RF ， 1A低压降线性稳压器
| 型号： | TPS79601DRBTG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Ultralow-Noise, High PSRR, Fast, RF, 1A Low-Dropout Linear Regulators |
| 文件： | 总30页 (文件大小：1249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS796
www.ti.com
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
Ultralow-Noise, High PSRR, Fast, RF, 1A
Low-Dropout Linear Regulators
1
FEATURES
DESCRIPTION
The TPS796xx family of low-dropout (LDO) low-
234
•
1A Low-Dropout Regulator With Enable
power linear voltage regulators features high power
supply rejection ratio (PSRR), ultralow-noise, fast
start-up, and excellent line and load transient
responses in small outline, 3 × 3 SON, SOT223-6,
and DDPAK-5 packages. Each device in the family is
stable with a small 1μF ceramic capacitor on the
output. The family uses an advanced, proprietary
BiCMOS fabrication process to yield extremely low
dropout voltages (for example, 250mV at 1A). Each
device achieves fast start-up times (approximately
•
Available in Fixed and Adjustable (1.2V to
5.5V) Versions
•
•
•
•
•
•
High PSRR (53dB at 10kHz)
Ultralow-Noise (40μVRMS, TPS79630)
Fast Start-Up Time (50μs)
Stable With a 1μF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (250mV at Full
Load, TPS79630)
50μs with
a 0.001μF bypass capacitor) while
consuming very low quiescent current (265 μA
typical). Moreover, when the device is placed in
standby mode, the supply current is reduced to less
than 1μA. The TPS79630 exhibits approximately
40μVRMS of output voltage noise at 3.0V output, with
a 0.1μF bypass capacitor. Applications with analog
components that are noise sensitive, such as portable
RF electronics, benefit from the high PSRR, low
noise features, and the fast response time.
•
3 × 3 SON PowerPAD™, SOT223-6, and
DDPAK-5 Packages
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth™, Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TPS79630
RIPPLE REJECTION
vs
TPS79630
OUTPUT SPECTRAL NOISE DENSITY
vs
DCQ PACKAGE
SOT223-6
(TOP VIEW)
IN
IN
1
2
3
4
8
7
6
5
EN
FREQUENCY
FREQUENCY
NC
80
70
60
50
40
30
20
10
0
0.7
OUT
OUT
GND
NR/FB
V
= 4 V
V
= 5.5 V
IN
IN
1
2
3
4
0.6
0.5
0.4
0.3
0.2
0.1
0.0
EN
IN
C
OUT
= 10 mF
C
= 2.2 mF
OUT
= 0.1 mF
NR
I
= 1 mA
C
NR
= 0.01 mF
C
OUT
6
GND
OUT
GND
I
= 1 A
OUT
5
NR/FB
KTT (DDPAK) PACKAGE
(TOP VIEW)
I
= 1 mA
OUT
EN
1
2
IN
GND
I
= 1.5 A
OUT
3
4
OUT
1
10 100
1k 10k 100k 1M 10M
100
1k
10k
100k
NR/FB
Frequency (Hz)
Frequency (Hz)
5
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
PowerPAD is a trademark of Texas Instruments Inc.
Bluetooth is a trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2013, Texas Instruments Incorporated
TPS796
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS796xx yyy z
XX is nominal output voltage (for example, 28 = 2.8V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Output voltages from 1.3V to 4.9V in 100mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating temperature range (unless otherwise noted).
UNIT
VIN range
–0.3V to 6V
VEN range
–0.3V to VIN + 0.3V
6V
VOUT range
Peak output current
ESD rating, HBM
Internally limited
2kV
ESD rating, CDM
500V
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range, Tstg
See Thermal Information Table
–40°C to +150°C
–65°C to +150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
TPS796
www.ti.com
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
THERMAL INFORMATION
TPS796xx(3)
THERMAL METRIC(1)(2)
DRB
8 PINS
47.8
83
DCQ
6 PINS
70.4
70
KTT
5 PINS
25
UNITS
θJA
Junction-to-ambient thermal resistance(4)
Junction-to-case (top) thermal resistance(5)
Junction-to-board thermal resistance(6)
Junction-to-top characterization parameter(7)
Junction-to-board characterization parameter(8)
Junction-to-case (bottom) thermal resistance(9)
θJCtop
θJB
35
N/A
N/A
N/A
1.5
°C/W
ψJT
2.1
6.8
ψJB
17.8
12.1
30.1
6.3
8.52
0.4
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through
ii. DCQ: The exposed pad is connected to the PCB ground layer through
a
a
2x2 thermal via array.
3x2 thermal via array.
.
. iii. KTT: The exposed pad is connected to the PCB ground layer through a 5x4 thermal via array.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
.
ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
. iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
3
TPS796
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ = –40°C to +125°C), VEN = VIN,, VIN = VOUT(nom) + 1 V(1), IOUT = 1mA,
COUT = 10μF, and CNR = 0.01μF, unless otherwise noted. Typical values are at +25°C.
PARAMETER
VIN Input voltage(1)
TEST CONDITIONS
MIN
TYP
MAX UNIT
2.7
5.5
1.250
1
V
V
A
VFB Internal reference (TPS79601)
IOUT Continuous output current
1.200 1.225
0
Output
TPS79601
voltage range
1.225
5.5 – VDD
V
V
TPS79601(2)
0μA ≤ IOUT ≤ 1A, VOUT + 1V ≤ VIN ≤ 5.5V(1)
0μA ≤ IOUT ≤ 1A, VOUT + 1V ≤ VIN ≤ 5.5V(1)
0.98VOUT VOUT 1.02VOUT
Output
voltage
Fixed
VOUT < 5V
–2.0
–3.0
+2.0
+3.0
0.12
%
Accuracy
Fixed
VOUT = 5V
0μA ≤ IOUT ≤ 1A, VOUT + 1V ≤ VIN ≤ 5.5V(1)
VOUT + 1V ≤ VIN ≤ 5.5V
%
Output voltage line regulation
0.05
%/V
mV
(1)
(ΔVOUT%/VIN
Load regulation (ΔVOUT%/ΔIOUT
TPS79628
)
)
0μA ≤ IOUT ≤ 1A
5
270
52
IOUT = 1A
365
90
TPS79628DRB IOUT = 250mA
Dropout voltage(3)
(VIN = VOUT (nom) – 0.1V)
TPS79630
TPS79633
TPS79650
IOUT = 1A
250
220
200
345
325
300
4.2
385
1
mV
IOUT = 1A
IOUT = 1A
Output current limit
Ground pin current
Shutdown current(4)
FB pin current
VOUT = 0V
2.4
A
0μA ≤ IOUT ≤ 1A
VEN = 0V, 2.7V ≤ VIN ≤ 5.5V
VFB = 1.225V
265
μA
μA
μA
0.07
1
f = 100Hz, IOUT = 10mA
f = 100Hz, IOUT = 1A
f = 10kHz, IOUT = 1A
f = 100kHz, IOUT = 1A
59
54
53
42
54
46
41
40
50
75
110
Power-supply ripple
rejection
TPS79630
dB
CNR = 0.001μF
CNR = 0.0047μF
CNR = 0.01μF
CNR = 0.1μF
BW = 100Hz to 100kHz,
IOUT = 1A
Output noise voltage (TPS79630)
Time, start-up (TPS79630)
μVRMS
CNR = 0.001μF
CNR = 0.0047μF
CNR = 0.01μF
RL = 3Ω, COUT = 1μF
μs
EN pin current
VEN = 0V
VCC rising
–1
1
μA
V
UVLO threshold
2.25
2.65
UVLO hysteresis
100
mV
V
High-level enable input voltage
Low-level enable input voltage
2.7V ≤ VIN ≤ 5.5V
2.7V ≤ VIN ≤ 5.5V
1.7
0
VIN
0.7
V
(1) Minimum VIN = VOUT + VDO or 2.7V, whichever is greater. TPS79650 is tested at VIN = 5.5V.
(2) Tolerance of external resistors not included in this specification.
(3) VDO is not measured for TPS79618 and TPS79625 because minimum VIN = 2.7V.
(4) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
4
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
TPS796
www.ti.com
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
IN
OUT
Current
Sense
UVLO
SHUTDOWN
ILIM
R
1
_
GND
EN
+
FB
UVLO
R
2
Thermal
Shutdown
Quickstart
External to
the Device
Bandgap
Reference
1.225 V
250 kΩ
V
REF
V
IN
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
IN
OUT
UVLO
Current
Sense
GND
EN
SHUTDOWN
ILIM
R
1
_
+
UVLO
Thermal
Shutdown
R
2
Quickstart
R = 40k
2
Bandgap
Reference
1.225 V
250 kΩ
V
REF
V
IN
NR
Table 1. Terminal Functions
TERMINAL
SOT223
(DCQ)
DDPAK
(KTT)
SON
(DRB)
NAME
DESCRIPTION
Connecting an external capacitor to this pin bypasses noise generated by the internal
bandgap. This improves power-supply rejection and reduces output noise.
NR
5
5
FB
EN
5
1
5
8
This terminal is the feedback input voltage for the adjustable device.
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator
into shutdown mode. EN can be connected to IN if not used.
GND
IN
3, Tab
6, PowerPAD Regulator ground
2
4
1, 2
3, 4
Unregulated input to the device.
Output of the regulator.
OUT
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
TPS796
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS
TPS79630
OUTPUT VOLTAGE
vs
TPS79628
OUTPUT VOLTAGE
vs
TPS79628
GROUND CURRENT
vs
OUTPUT CURRENT
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.795
350
340
330
320
310
300
290
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
V
C
= 4 V
= 10 µF
= 25°C
V
= 3.8 V
= 10 µF
V
C
= 3.8 V
IN
IN
IN
C
OUT
= 10 µF
OUT
OUT
T
J
I
= 1 mA
OUT
2.790
2.785
I
= 1 A
I
= 1 A
OUT
OUT
2.780
I
= 1 mA
OUT
2.775
0.0
0.2
0.4
0.6
(A)
0.8
1.0
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
I
T
J
T
J
OUT
Figure 1.
Figure 2.
Figure 3.
TPS79630
TPS79630
TPS79630
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
0.7
vs
FREQUENCY
0.6
vs
FREQUENCY
2.5
2.0
1.5
1.0
0.5
0.0
V
= 5.5 V
V
= 5.5 V
V
C
= 5.5 V
IN
IN
IN
C
C
= 2.2 µF
C
C
= 10 µF
= 0.1 µF
= 10 µF
0.6
0.5
0.4
0.3
0.2
0.1
0.0
OUT
OUT
OUT
0.5
0.4
0.3
0.2
0.1
0.0
= 0.1 µF
I = 1 A
OUT
NR
NR
C
NR
= 0.01 µF
C
NR
= 0.1 µF
I
= 1 mA
OUT
C
NR
= 0.0047 µF
I
= 1 mA
OUT
C
NR
= 0.001 µF
I
= 1 A
OUT
I
= 1.5 A
1k
OUT
100
10k
100k
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Figure 4.
Figure 5.
Figure 6.
TPS79630
TPS79628
TPS79630
ROOT MEAN SQUARED OUTPUT
NOISE
vs
BYPASS CAPACITANCE
DROPOUT VOLTAGE
vs
RIPPLE REJECTION
vs
JUNCTION TEMPERATURE
FREQUENCY
350
300
250
200
150
100
50
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
VIN = 2.7 V
V
C
C
= 4 V
IN
µ
COUT = 10
F
= 10 µF
OUT
I
= 1 mA
= 0.01 µF
OUT
IOUT = 1 A
NR
I
= 1 A
OUT
I
C
= 250 mA
OUT
= 10 µF
OUT
IOUT = 250 mA
BW = 100 Hz to 100 kHz
0
−40−25−10
5
20 35 50 65 80 95 110 125
0.001 µF
0.0047 µF
0.01 µF
(µF)
0.1 µF
1
10
100
1k 10k 100k 1M 10M
_
(
TJ
C)
C
NR
Frequency (Hz)
Figure 7.
Figure 8.
Figure 9.
6
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
TPS796
www.ti.com
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
TYPICAL CHARACTERISTICS (continued)
TPS79630
RIPPLE REJECTION
vs
TPS79630
RIPPLE REJECTION
vs
FREQUENCY
FREQUENCY
START-UP TIME
3
2.75
2.50
2.25
2
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
V
C
= 4 V,
= 10 µF,
IN
V
C
C
= 4 V
V
C
C
= 4 V
IN
= 2.2 µF
OUT
= 0.01 µF
NR
IN
C
=
NR
OUT
= 10 µF
OUT
0.0047 µF
I = 1.0 A
OUT
I
= 1 mA
I
= 1 mA
OUT
= 0.1 µF
OUT
NR
Enable
C
=
NR
0.001 µF
I
= 1 A
I
= 1 A
OUT
OUT
1.75
1.50
1.25
1
C
NR
=
0.01 µF
0.75
0.50
0.25
0
0
1
0
100
200
300
400
500
600
10
100
1k 10k 100k 1M 10M
1
10
100
1k 10k 100k 1M 10M
t (ms)
Frequency (Hz)
Frequency (Hz)
Figure 10.
TPS79618
Figure 11.
Figure 12.
TPS79630
LINE TRANSIENT RESPONSE
TPS79628
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
5
4
6
5
4
3
2
1
3
0
I
C
C
= 1 A
V
C
C
= 3.8 V
IN
= 10 µF
OUT
OUT
dv
dt
dv
dt
di
dt
1 V
ms
1 V
ms
1 A
ms
2
−1
I
C
C
= 1 A
OUT
+
+
+
= 10 µF
= 0.01 µF
OUT
= 10 µF
= 0.01 µF
OUT
= 0.01 µF
NR
NR
40
20
40
20
150
75
NR
0
0
0
−20
−40
−20
−40
−75
−150
0
0
20 40 60 80 100 120 140 160 180 200
0
20 40 60 80 100 120 140 160 180 200
100 200 300 400 500 600 700 800 900 1000
t (µs)
t (µs)
t (µs)
Figure 13.
Figure 14.
Figure 15.
TPS79630
DROPOUT VOLTAGE
vs
TPS79601
DROPOUT VOLTAGE
vs
TPS79625
POWER UP/POWER DOWN
OUTPUT CURRENT
INPUT VOLTAGE
300
250
200
150
100
50
4.0
350
300
250
200
150
100
50
V
R
C
= 2.5 V
= 10 Ω
= 0.01 µF
OUT
3.5
3.0
2.5
L
NR
T
J
= 125°C
T
= 125°C
J
T
= 25°C
J
T
J
= 25°C
2.0
1.5
1.0
0.5
0
T
= −40°C
J
V
IN
T
J
= −40°C
I
C
C
= 1 A
= 10 µF
= 0.01 µF
OUT
V
OUT
OUT
NR
0
0
0
1
2
3
4
5
6
7
8
9
10
0
100 200 300 400 500 600 700 800 9001000
(mA)
2.5
3.0
3.5
4.0
4.5
5.0
I
V
(V)
IN
200 µs/Div
OUT
Figure 16.
Figure 17.
Figure 18.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
TPS796
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TPS79630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
TPS79630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
TPS79630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
vs
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
OUTPUT CURRENT
100
100
100
10
C
OUT
= 1 µF
C
OUT
= 2.2 µF
C
OUT
= 10.0 µF
Region of
Instability
Region of
Instability
Region of
Instability
10
10
1
0.1
1
0.1
1
0.1
Region of Stability
Region of Stability
Region of Stability
0.01
0.01
0.01
1
10 30 60 125 250 500 750 1000
(mA)
1
10 30 60 125 250 500 750 1000
(mA)
1
10 30 60 125 250 500 750 1000
(mA)
I
I
OUT
I
OUT
OUT
Figure 19.
Figure 20.
Figure 21.
8
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
TPS796
www.ti.com
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
APPLICATION INFORMATION
The TPS796xx family of low-dropout (LDO) regulators
has been optimized for use in noise-sensitive
equipment. The device features extremely low
dropout voltages, high PSRR, ultralow output noise,
low quiescent current (265μA typically), and enable
input to reduce supply currents to less than 1μA
when the regulator is turned off.
For example, the TPS79630 exhibits 40μVRMS of
output voltage noise using a 0.1μF ceramic bypass
capacitor and a 10μF ceramic output capacitor. Note
that the output starts up slower as the bypass
capacitance increases due to the RC time constant at
the bypass pin that is created by the internal 250kΩ
resistor and external capacitor.
A typical application circuit is shown in Figure 22.
Board Layout Recommendation to Improve
PSRR and Noise Performance
VIN
VOUT
IN
OUT
TPS796xx
GND
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the ground pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
2.2µF
1 µF
EN
NR
µ
0.01 F
Figure 22. Typical Application Circuit
External Capacitor Requirements
Regulator Mounting
Although not required, it is good analog design
practice to place a 0.1μF to 2.2μF capacitor near the
input of the regulator to counteract reactive input
sources. A 2.2μF or larger ceramic input bypass
capacitor, connected between IN and GND and
located close to the TPS796xx, is required for stability
and improves transient response, noise rejection, and
ripple rejection. A higher-value input capacitor may be
necessary if large, fast-rise-time load transients are
anticipated and the device is located several inches
from the power source.
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat dissipation.
Solder pad footprint recommendations for the devices
are presented in an application bulletin Solder Pad
Recommendations for Surface-Mount Devices,
literature number AB-132, available for download
from the TI web site (www.ti.com).
Like most low dropout regulators, the TPS796xx
requires an output capacitor connected between OUT
and GND to stabilize the internal control loop. The
minimum recommended capacitor is 1μF. Any 1μF or
larger ceramic capacitor is suitable.
Programming the TPS79601 Adjustable LDO
Regulator
The output voltage of the TPS79601 adjustable
regulator is programmed using an external resistor
divider (see Figure 23). The output voltage is
calculated using Equation 1:
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS796xx has an NR
pin which is connected to the voltage reference
through a 250kΩ internal resistor. The 250kΩ internal
resistor, in conjunction with an external bypass
capacitor connected to the NR pin, creates a low-
pass filter to reduce the voltage reference noise and,
therefore, the noise at the regulator output. In order
for the regulator to operate properly, the current flow
out of the NR pin must be at a minimum, because
any leakage current creates an IR drop across the
internal resistor, thus creating an output error.
Therefore, the bypass capacitor must have minimal
leakage current. The bypass capacitor should be no
more than 0.1μF in order to ensure that it is fully
charged during the quickstart time provided by the
internal switch shown in the functional block diagram.
R1
R2
ǒ1) Ǔ
VOUT + VREF
(1)
where:
•
VREF
voltage)
= 1.2246V typ (the internal reference
Resistors R1 and R2 should be chosen for
approximately 40μA divider current. Lower value
resistors can be used for improved noise
performance, but the device wastes more power.
Higher values should be avoided, as leakage current
at FB increases the output voltage error.
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
9
TPS796
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
www.ti.com
The recommended design procedure is to choose
R2 = 30.1kΩ to set the divider current at 40μA, C1 =
15pF for stability, and then calculate R1 using
Equation 2:
Regulator Protection
The TPS796xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (for
example, during power-down). Current is conducted
from the output to the input and is not internally
limited. If extended reverse voltage operation is
anticipated, external limiting might be appropriate.
VOUT
R1 + ǒ Ǔ
*1 R2
VREF
(2)
In order to improve the stability of the adjustable
version, it is suggested that a small compensation
capacitor be placed between OUT and FB. The
approximate value of this capacitor can be calculated
as Equation 3:
The TPS796xx features internal current limiting and
thermal protection. During normal operation, the
TPS796xx limits output current to approximately 2.8A.
When current limiting engages, the output voltage
scales back linearly until the overcurrent condition
ends. While current limiting is designed to prevent
gross device failure, care should be taken not to
exceed the power dissipation ratings of the package.
If the temperature of the device exceeds
approximately +165°C, thermal-protection circuitry
shuts it down. Once the device has cooled down to
below approximately +140°C, regulator operation
resumes.
–7
(3 x 10 ) x (R1 ) R2)
C1 +
(R1 x R2)
(3)
The suggested value of this capacitor for several
resistor ratios is shown in the table in Figure 23. If
this capacitor is not used (such as in a unity-gain
configuration) then the minimum recommended
output capacitor is 2.2μF instead of 1μF.
OUTPUT VOLTAGE
VOUT
VIN
PROGRAMMING GUIDE
IN
OUT
FB
TPS79601
R1
R2
C1
OUTPUT
2.2 µF
EN
1 µF
R1
R2
C1
VOLTAGE
GND
1.8 V
3.6V
14.0 kΩ 30.1 kΩ
33 pF
57.9 kΩ 30.1 kΩ 15 pF
Figure 23. TPS79601 Adjustable LDO Regulator Programming
10
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
TPS796
www.ti.com
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
THERMAL INFORMATION
Knowing the maximum RθJA, the minimum amount of
PCB copper area needed for appropriate heatsinking
can be estimated using Figure 24.
POWER DISSIPATION
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation.
160
DCQ
DRB
KTT
140
Power dissipation of the device depends on input
voltage and load conditions and can be calculated
using Equation 4:
120
100
80
60
40
20
0
ǒ
Ǔ
PD + VIN * VOUT IOUT
(4)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
On the SON (DRB) package, the primary conduction
path for heat is through the exposed pad to the
printed circuit board (PCB). The pad can be
connected to ground or be left floating; however, it
should be attached to an appropriate amount of
copper PCB area to ensure the device does not
overheat. On both SOT-223 (DCQ) and DDPAK
(KTT) packages, the primary conduction path for heat
is through the tab to the PCB. That tab should be
connected to ground. The maximum junction-to-
ambient thermal resistance depends on the maximum
ambient temperature, maximum device junction
temperature, and power dissipation of the device and
can be calculated using Equation 5:
4
5
7
0
1
2
3
6
8
9
10
Board Copper Area (in2)
Note: θJA value at board size of 9in2 (that is, 3in ×
3in) is a JEDEC standard.
Figure 24. θJA vs Board Size
Figure 24 shows the variation of θJA as a function of
ground plane copper area in the board. It is intended
only as a guideline to demonstrate the effects of heat
spreading in the ground plane and should not be
used to estimate actual thermal performance in real
application environments.
O
(
)
)125 C * TA
NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
R
+
qJA
PD
(5)
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
11
TPS796
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
www.ti.com
ESTIMATING JUNCTION TEMPERATURE
35
30
25
20
15
10
5
Using the thermal metrics ΨJT and ΨJB, as shown in
the Thermal Information table, the junction
temperature can be estimated with corresponding
formulas (given in Equation 6). For backwards
compatibility, an older θJC,Top parameter is listed as
well.
DCQ
DRB
KTT
YJB
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(6)
DCQ YJT
DRB YJT
KTT YJT
Where PD is the power dissipation shown by
Equation 5, TT is the temperature at the center-top of
the IC package, and TB is the PCB temperature
measured 1mm away from the IC package on the
PCB surface (as Figure 26 shows).
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 25. ΨJT and ΨJB vs Board Size
NOTE: Both TT and TB can be measured on actual
application boards using a thermo-gun (an infrared
thermometer).
For a more detailed discussion of why TI does not
recommend using θJC(top) to determine thermal
characteristics, refer to application report SBVA025,
Using New Thermal Metrics, available for download
at www.ti.com. For further information, refer to
application report SPRA953, IC Package Thermal
Metrics, also available on the TI website.
For more information about measuring TT and TB, see
the application note SBVA025, Using New Thermal
Metrics, available for download at www.ti.com.
By looking at Figure 25, the new thermal metrics (ΨJT
and ΨJB) have very little dependency on board size.
That is, using ΨJT or ΨJB with Equation 6 is a good
way to estimate TJ by simply measuring TT or TB,
regardless of the application board size.
TT on top of IC(1)
TB
X
1mm
TT on top
of IC
TB on PCB
surface
TB on PCB
surface(2)
TT
1mm
X
1mm
(c) Example KTT (DDPAK) Package Measurement
(a) Example DRB (SON) Package Measurement
(b) Example DCQ (SOT-223) Package Measurement
(1) TT is measured at the center of both the X- and Y-dimensional axes.
(2) TB is measured below the package lead on the PCB surface.
Figure 26. Measuring Points for TT and TB
12
Submit Documentation Feedback
Copyright © 2002–2013, Texas Instruments Incorporated
TPS796
www.ti.com
SLVS351O –SEPTEMBER 2002–REVISED NOVEMBER 2013
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (January 2011) to Revision O
Page
•
•
Changed Power-Supply Ripple Rejection 3rd test condition from "f = 10Hz" to "f = 10kHz" (typo) ..................................... 4
Changed Power-Supply Ripple Rejection 4th test condition from "f = 100Hz" to "f = 100kHz" (typo) ................................. 4
Changes from Revision M (October 2010) to Revision N
Page
•
Corrected typo in front-page figure ....................................................................................................................................... 1
Changes from Revision L (August 2010) to Revision M
Page
•
Corrected typo in Figure 26 ................................................................................................................................................ 12
Copyright © 2002–2013, Texas Instruments Incorporated
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2013
PACKAGING INFORMATION
Orderable Device
TPS79601DCQ
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SOT-223
SOT-223
SOT-223
SOT-223
SON
DCQ
6
6
6
6
8
8
8
8
5
5
5
5
5
8
8
8
8
78
Green (RoHS
& no Sb/Br)
CU SN
CU NIPDAU
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
PS79601
TPS79601DCQG4
TPS79601DCQR
TPS79601DCQRG4
TPS79601DRBR
TPS79601DRBRG4
TPS79601DRBT
TPS79601DRBTG4
TPS79601KTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DCQ
DCQ
DCQ
DRB
DRB
DRB
DRB
KTT
KTT
KTT
KTT
KTT
DRB
DRB
DRB
DRB
78
Green (RoHS
& no Sb/Br)
PS79601
PS79601
PS79601
CES
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
3000
3000
250
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
CES
SON
Green (RoHS
& no Sb/Br)
CES
SON
250
Green (RoHS
& no Sb/Br)
CES
OBSOLETE DDPAK/
TO-263
TBD
TPS79601KTTR
TPS79601KTTRG3
TPS79601KTTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500
500
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS
79601
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
79601
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
79601
TPS79601KTTTG3
TPS79613DRBR
TPS79613DRBRG4
TPS79613DRBT
TPS79613DRBTG4
DDPAK/
TO-263
50
Green (RoHS
& no Sb/Br)
CU SN
TPS
79601
SON
SON
SON
SON
3000
3000
250
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CCT
CCT
CCT
CCT
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS79618DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
PS79618
TPS79618DCQG4
TPS79618DCQR
ACTIVE
ACTIVE
SOT-223
SOT-223
DCQ
DCQ
6
6
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
2500
2500
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
PS79618
PS79618
TPS79618DCQRG4
TPS79618KTT
ACTIVE
SOT-223
DCQ
KTT
KTT
KTT
KTT
KTT
DCQ
6
5
5
5
5
5
6
Green (RoHS
& no Sb/Br)
CU NIPDAU
Call TI
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
OBSOLETE DDPAK/
TO-263
TBD
TPS79618KTTR
TPS79618KTTRG3
TPS79618KTTT
TPS79618KTTTG3
TPS79625DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500
500
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS
79618
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
79618
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
-40 to 125
-40 to 125
-40 to 125
TPS
79618
DDPAK/
TO-263
50
Green (RoHS
& no Sb/Br)
CU SN
TPS
79618
SOT-223
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
PS79625
TPS79625DCQG4
TPS79625DCQR
ACTIVE
ACTIVE
SOT-223
SOT-223
DCQ
DCQ
6
6
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
2500
2500
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
PS79625
PS79625
TPS79625DCQRG4
TPS79625KTT
ACTIVE
SOT-223
DCQ
KTT
KTT
KTT
KTT
KTT
6
5
5
5
5
5
Green (RoHS
& no Sb/Br)
CU NIPDAU
Call TI
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
OBSOLETE DDPAK/
TO-263
TBD
TPS79625KTTR
TPS79625KTTRG3
TPS79625KTTT
TPS79625KTTTG3
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500
500
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS
79625
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
79625
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
-40 to 125
-40 to 125
TPS
79625
DDPAK/
TO-263
50
Green (RoHS
& no Sb/Br)
CU SN
TPS
79625
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS79628DCQ
TPS79628DCQG4
TPS79628DCQR
TPS79628DCQRG4
TPS79628DRBR
TPS79628DRBRG4
TPS79628DRBT
TPS79628DRBTG4
TPS79628KTT
ACTIVE
SOT-223
SOT-223
SOT-223
SOT-223
SON
DCQ
6
6
6
6
8
8
8
8
5
5
5
6
6
6
6
5
5
5
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
PS79628
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DCQ
DCQ
DCQ
DRB
DRB
DRB
DRB
KTT
78
Green (RoHS
& no Sb/Br)
PS79628
PS79628
PS79628
AMI
2500
2500
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
-40 to 85
AMI
SON
Green (RoHS
& no Sb/Br)
-40 to 85
AMI
SON
250
Green (RoHS
& no Sb/Br)
-40 to 85
AMI
OBSOLETE DDPAK/
TO-263
TBD
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS79628KTTT
TPS79628KTTTG3
TPS79630DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTT
50
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
TPS
79628
DDPAK/
TO-263
KTT
Green (RoHS
& no Sb/Br)
CU SN
TPS
79628
SOT-223
SOT-223
SOT-223
SOT-223
DCQ
DCQ
DCQ
DCQ
KTT
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
PS79630
PS79630
PS79630
PS79630
TPS79630DCQG4
TPS79630DCQR
TPS79630DCQRG4
TPS79630KTT
78
Green (RoHS
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
TPS79630KTTR
TPS79630KTTRG3
ACTIVE
DDPAK/
TO-263
KTT
500
500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS
79630
ACTIVE
DDPAK/
TO-263
KTT
Green (RoHS
& no Sb/Br)
CU SN
TPS
79630
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS79630KTTT
TPS79630KTTTG3
TPS79633DCQ
ACTIVE
DDPAK/
TO-263
KTT
5
5
6
6
6
6
5
5
5
5
5
6
6
6
6
8
8
8
50
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
TPS
79630
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTT
DCQ
DCQ
DCQ
DCQ
KTT
50
78
Green (RoHS
& no Sb/Br)
TPS
79630
SOT-223
SOT-223
SOT-223
SOT-223
Green (RoHS
& no Sb/Br)
CU SN
PS79633
PS79633
PS79633
PS79633
TPS79633DCQG4
TPS79633DCQR
TPS79633DCQRG4
TPS79633KTT
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU SN
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Call TI
OBSOLETE DDPAK/
TO-263
TBD
TPS79633KTTR
TPS79633KTTRG3
TPS79633KTTT
TPS79633KTTTG3
TPS79650DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTT
500
500
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS
79633
DDPAK/
TO-263
KTT
Green (RoHS
& no Sb/Br)
CU SN
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS
79633
DDPAK/
TO-263
KTT
Green (RoHS
& no Sb/Br)
CU SN
TPS
79633
DDPAK/
TO-263
KTT
50
Green (RoHS
& no Sb/Br)
CU SN
TPS
79633
SOT-223
SOT-223
SOT-223
SOT-223
SON
DCQ
DCQ
DCQ
DCQ
DRB
DRB
DRB
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
PS79650
PS79650
PS79650
PS79650
BYZ
TPS79650DCQG4
TPS79650DCQR
TPS79650DCQRG4
TPS79650DRBR
TPS79650DRBRG4
TPS79650DRBT
78
Green (RoHS
& no Sb/Br)
2500
2500
3000
3000
250
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
BYZ
SON
Green (RoHS
& no Sb/Br)
BYZ
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2013
Orderable Device
TPS79650DRBTG4
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SON
DRB
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BYZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS79633 :
Automotive: TPS79633-Q1
•
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
16-Oct-2013
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS79601DCQRG4
TPS79601DRBR
TPS79601DRBT
TPS79601KTTR
SOT-223 DCQ
6
8
8
5
0
330.0
330.0
180.0
330.0
12.4
12.4
12.4
24.4
7.05
3.3
7.45
3.3
1.88
1.1
1.1
4.9
8.0
8.0
12.0
12.0
12.0
24.0
Q3
Q2
Q2
Q2
SON
SON
DRB
DRB
KTT
3000
250
500
3.3
3.3
8.0
DDPAK/
TO-263
10.6
15.6
16.0
TPS79601KTTT
DDPAK/
TO-263
KTT
5
50
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
TPS79613DRBR
TPS79613DRBT
TPS79618DCQRG4
TPS79618KTTR
SON
SON
DRB
DRB
8
8
6
5
3000
250
330.0
180.0
330.0
330.0
12.4
12.4
12.4
24.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
12.0
24.0
Q2
Q2
Q3
Q2
SOT-223 DCQ
2500
500
7.05
10.6
7.45
15.6
1.88
4.9
8.0
DDPAK/
TO-263
KTT
16.0
TPS79618KTTT
DDPAK/
TO-263
KTT
5
50
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
TPS79625DCQRG4
TPS79625KTTR
SOT-223 DCQ
6
5
2500
500
330.0
330.0
12.4
24.4
7.05
10.6
7.45
15.6
1.88
4.9
8.0
12.0
24.0
Q3
Q2
DDPAK/
TO-263
KTT
16.0
TPS79625KTTT
TPS79628DCQR
DDPAK/
TO-263
KTT
5
6
50
330.0
330.0
24.4
12.4
10.6
6.8
15.6
7.3
4.9
16.0
8.0
24.0
12.0
Q2
Q3
SOT-223 DCQ
2500
1.88
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS79628DRBR
TPS79628DRBT
TPS79628KTTT
SON
SON
DRB
DRB
KTT
8
8
5
3000
250
50
330.0
180.0
330.0
12.4
12.4
24.4
3.3
3.3
3.3
3.3
1.1
1.1
4.9
8.0
8.0
12.0
12.0
24.0
Q2
Q2
Q2
DDPAK/
TO-263
10.6
15.6
16.0
TPS79630DCQR
TPS79630KTTR
SOT-223 DCQ
6
5
2500
500
330.0
330.0
12.4
24.4
6.8
7.3
1.88
4.9
8.0
12.0
24.0
Q3
Q2
DDPAK/
TO-263
KTT
10.6
15.6
16.0
TPS79630KTTT
DDPAK/
TO-263
KTT
5
50
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
TPS79633DCQRG4
TPS79633KTTR
SOT-223 DCQ
6
5
2500
500
330.0
330.0
12.4
24.4
7.05
10.6
7.45
15.6
1.88
4.9
8.0
12.0
24.0
Q3
Q2
DDPAK/
TO-263
KTT
16.0
TPS79633KTTT
DDPAK/
TO-263
KTT
5
50
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
TPS79650DCQR
TPS79650DRBR
TPS79650DRBT
SOT-223 DCQ
6
8
8
2500
3000
250
330.0
330.0
180.0
12.4
12.4
12.4
6.8
3.3
3.3
7.3
3.3
3.3
1.88
1.1
8.0
8.0
8.0
12.0
12.0
12.0
Q3
Q2
Q2
SON
SON
DRB
DRB
1.1
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOT-223 DCQ
SPQ
Length (mm) Width (mm) Height (mm)
358.0 335.0 35.0
TPS79601DCQRG4
6
0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Oct-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS79601DRBR
TPS79601DRBT
TPS79601KTTR
TPS79601KTTT
TPS79613DRBR
TPS79613DRBT
TPS79618DCQRG4
TPS79618KTTR
TPS79618KTTT
TPS79625DCQRG4
TPS79625KTTR
TPS79625KTTT
TPS79628DCQR
TPS79628DRBR
TPS79628DRBT
TPS79628KTTT
TPS79630DCQR
TPS79630KTTR
TPS79630KTTT
TPS79633DCQRG4
TPS79633KTTR
TPS79633KTTT
TPS79650DCQR
TPS79650DRBR
TPS79650DRBT
SON
SON
DRB
DRB
KTT
KTT
DRB
DRB
DCQ
KTT
KTT
DCQ
KTT
KTT
DCQ
DRB
DRB
KTT
DCQ
KTT
KTT
DCQ
KTT
KTT
DCQ
DRB
DRB
8
8
5
5
8
8
6
5
5
6
5
5
6
8
8
5
6
5
5
6
5
5
6
8
8
3000
250
500
50
367.0
210.0
367.0
367.0
367.0
210.0
358.0
367.0
367.0
358.0
367.0
367.0
358.0
367.0
210.0
367.0
358.0
367.0
367.0
358.0
367.0
367.0
358.0
367.0
210.0
367.0
185.0
367.0
367.0
367.0
185.0
335.0
367.0
367.0
335.0
367.0
367.0
335.0
367.0
185.0
367.0
335.0
367.0
367.0
335.0
367.0
367.0
335.0
367.0
185.0
35.0
35.0
45.0
45.0
35.0
35.0
35.0
45.0
45.0
35.0
45.0
45.0
35.0
35.0
35.0
45.0
35.0
45.0
45.0
35.0
45.0
45.0
35.0
35.0
35.0
DDPAK/TO-263
DDPAK/TO-263
SON
3000
250
2500
500
50
SON
SOT-223
DDPAK/TO-263
DDPAK/TO-263
SOT-223
2500
500
50
DDPAK/TO-263
DDPAK/TO-263
SOT-223
2500
3000
250
50
SON
SON
DDPAK/TO-263
SOT-223
2500
500
50
DDPAK/TO-263
DDPAK/TO-263
SOT-223
2500
500
50
DDPAK/TO-263
DDPAK/TO-263
SOT-223
2500
3000
250
SON
SON
Pack Materials-Page 3
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
Medical
Logic
Security
www.ti.com/security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense
Video and Imaging
www.ti.com/space-avionics-defense
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/omap
OMAP Applications Processors
Wireless Connectivity
TI E2E Community
e2e.ti.com
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明