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TPS79927QDDCRQ1 [TI]

200 mA, LOW QUIESCENT CURRENT, ULTRA-LOW NOISE HIGH PSRR, LOW DROPOUT, LINEAR REGULATORS; 200毫安，低静态电流，超低噪声，高PSRR ，低压差，线性稳压器
TPS79927QDDCRQ1
型号： TPS79927QDDCRQ1
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

200 mA, LOW QUIESCENT CURRENT, ULTRA-LOW NOISE HIGH PSRR, LOW DROPOUT, LINEAR REGULATORS
200毫安，低静态电流，超低噪声，高PSRR ，低压差，线性稳压器

稳压器
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TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
www.ti.com  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
200 mA, LOW QUIESCENT CURRENT, ULTRA-LOW NOISE,  
HIGH PSRR, LOW DROPOUT, LINEAR REGULATORS  
Check for Samples: TPS79901-Q1, TPS79912-Q1, TPS79915-Q1, TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
1
FEATURES  
23  
•
Qualified for Automotive Applications  
DESCRIPTION  
•
200-mA Low-Dropout (LDO) Regulator  
With Enable (EN)  
The TPS799xx family of low-dropout (LDO)  
low-power linear regulators offers excellent ac  
performance with very low ground current. High  
power-supply rejection ratio (PSRR), low noise, fast  
start-up, and excellent line and load transient  
response are provided while consuming a very low  
40-μA (typical) ground current. The TPS799xx is  
stable with ceramic capacitors and uses an advanced  
BiCMOS fabrication process to yield a dropout  
voltage of 100 mV (typ) at 200-mA output. The  
TPS799xx uses a precision voltage reference and  
feedback loop to achieve overall accuracy of 2% over  
all load, line, process, and temperature variations. It  
is fully specified from TJ = –40°C to 125°C and is  
offered in low profile ThinSOT-23 and 2-mm × 2-mm  
SON packages, ideal for wireless handsets and  
WLAN cards.  
•
•
Low IQ: 40 μA  
Multiple Output Voltage Versions Available:  
–
Fixed Outputs of 1.2 V to 4.5 V Using  
Innovative Factory EEPROM Programming  
–
Adjustable Outputs from 1.2 V to 6.5 V  
•
•
•
•
High PSRR: 66 dB at 1 kHz  
Ultralow Noise: 29.5 μVRMS  
Fast Start-Up Time: 45 μs  
Stable With a Low ESR, 2-μF (Typ) Output  
Capacitance  
•
•
•
•
Excellent Load/Line Transient Response  
2% Overall Accuracy (Load/Line/Temperature)  
Very Low Dropout: 100 mV  
DDC (TSOT-23-5) PACKAGE  
(TOP VIEW)  
DRV (SON-6) PACKAGE  
(TOP VIEW)  
Thin SOT-23 and 2-mm × 2-mm SON-6  
Packages  
OUT  
FB  
1
2
3
6
5
4
IN  
5
4
1
2
3
IN  
GND  
EN  
OUT  
NR  
APPLICATIONS  
GND  
N/C  
EN  
•
•
•
•
Cellular Phones  
GND  
Wireless LANs, Bluetooth®  
N/C – No internal connection  
VCOs, RF  
Handheld Organizers, PDAs  
ORDERING INFORMATION(1)  
TJ  
VOUT  
PACKAGE(2)  
ORDERABLE PART NUMBER  
TPS79912QDRVRQ1  
TPS79915QDDCRQ1  
TPS79915QDRVRQ1  
TSP79918QDDCRQ1  
TPS79925QDDCRQ1  
TPS79927QDDCRQ1  
TPS79927QDRVRQ1  
TSP79933QDDCRQ1  
TSP79901QDRVRQ1  
TOP-SIDE MARKING  
1.2 V  
SON-6 – DRV  
Reel of 3000  
Reel of 3000  
Reel of 3000  
Reel of 3000  
Reel of 3000  
Reel of 3000  
Reel of 3000  
Reel of 3000  
Reel of 3000  
DAV  
OFC  
RAQ  
CEW  
OFM  
OFD  
OFK  
PSEQ  
CFA  
TSOT-23-5 – DDC  
SON-6 – DRV  
1.5 V  
1.8 V  
2.5 V  
TSOT-23-5 – DDC  
TSOT-23-5 – DDC  
TSOT-23-5 – DDC  
SON-6 – DRV  
–40°C to 125°C  
2.7 V  
3.3 V  
TSOT-23-5 – DDC  
Adjustable(3) SON-6 – DRV  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
(3) For fixed 1.2-V operation, tie FB to OUT.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
Bluetooth is a registered trademark of Bluetooth SIG, Inc.  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2012, Texas Instruments Incorporated  
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating temperature range (unless otherwise noted)  
VIN range  
–0.3 V to 7 V  
–0.3 V to VIN + 0.3 V  
–0.3 V to VIN + 0.3 V  
Internally limited  
VEN range  
VOUT range  
Peak output current  
Continuous total power dissipation  
Junction temperature range, TJ  
Storage junction temperature range , Tstg  
ESD rating, HBM  
See the Thermal Information table  
–55°C to 150°C  
–55°C to 150°C  
2000 V  
ESD rating, CDM  
1000 V  
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may  
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond  
those specified is not implied.  
THERMAL INFORMATION  
TPS799xxQ1  
THERMAL METRIC(1)(2)  
UNITS  
DRV (6 PINS)  
74.2  
DDC (5 PINS)  
178.1  
70.7  
θJA  
Junction-to-ambient thermal resistance  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
θJCtop  
θJB  
58.8  
145.9  
0.2  
73.4  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
2.5  
ψJB  
54.4  
74.1  
θJCbot  
7.2  
n/a  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.  
2
Submit Documentation Feedback  
Copyright © 2008–2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
 
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
www.ti.com  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
ELECTRICAL CHARACTERISTICS  
over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA,  
VEN = VIN, COUT = 2.2 μF, CNR = 0.01 μF (unless otherwise noted) For TPS79901, VOUT = 3.0 V. Typical values are at  
TJ = 25°C.  
PARAMETER  
Input voltage range(1)  
TEST CONDITIONS  
MIN  
2.7  
TYP  
MAX  
6.5  
UNIT  
V
VIN  
VFB  
Internal reference (TPS79901)  
1.169  
1.193  
1.217  
V
Output voltage range  
(TPS79901)  
VOUT  
VOUT  
VFB  
6.5 – VDO  
V
Output accuracy  
Output accuracy(1)  
Line regulation(1)  
Nominal, TJ = 25°C  
–1.0  
+1.0  
%
Over VIN, IOUT, temperature,  
VOUT + 0.3 V ≤ VIN ≤ 6.5 V,  
500 μA ≤ IOUT ≤ 200 mA  
VOUT  
–2.0  
±1.0  
+2.0  
%
ΔVOUT%/ ΔVIN  
VOUT(NOM) + 0.3 V ≤ VIN ≤ 6.5 V  
500 μA ≤ IOUT ≤ 200 mA  
0.02  
0.002  
100  
90  
%/V  
ΔVOUT%/ ΔIOUT Load regulation  
%/mA  
Dropout voltage(2)  
VDO  
VOUT < 3.3 V  
175  
160  
600  
60  
IOUT = 200 mA  
mV  
(VIN = VOUT(NOM) – 0.1 V)  
VOUT ≥ 3.3 V  
ICL  
Output current limit  
VOUT = 0.9 × VOUT(NOM)  
500 μA ≤ IOUT ≤ 200 mA  
200  
400  
40  
mA  
μA  
μA  
IGND  
ISHDN  
Ground pin current  
Shutdown current (IGND  
)
VEN ≤ 0.4 V, 2.7 V ≤ VIN ≤ 6.5 V  
0.15  
1.0  
Feedback pin current  
(TPS79901)  
IFB  
–0.5  
0.5  
μA  
f = 100 Hz  
70  
VIN = 3.85 V,  
f = 1 kHz  
66  
51  
VOUT = 2.85 V,  
CNR = 0.01 μF,  
IOUT = 100 mA  
PSRR  
Power-supply rejection ratio  
dB  
f = 10 kHz  
f = 100 kHz  
38  
Output noise voltage  
BW = 10 Hz to 100 kHz, VOUT  
2.8 V  
CNR = 0.01 μF  
10.5 VOUT  
VN  
=
μVRMS  
CNR = none  
94 VOUT  
CNR = 0.001 μF  
CNR = 0.047 μF  
CNR = 0.01 μF  
CNR = none  
45  
45  
50  
50  
VOUT = 2.85 V,  
RL = 14 Ω,  
COUT = 2.2 μF  
TSTR  
Startup time  
μs  
VEN(HI)  
VEN(LO)  
IEN(HI)  
Enable high (enabled)  
Enable low (shutdown)  
Enable pin current, enabled  
1.2  
0
VIN  
0.4  
1.0  
V
V
VEN = VIN = 6.5 V  
0.03  
165  
145  
μA  
°C  
°C  
°C  
V
Shutdown, temperature increasing  
Reset, temperature decreasing  
TSD  
Thermal shutdown temperature  
TJ  
Operating junction temperature  
Undervoltage lock-out  
Hysteresis  
–40  
125  
VUVLO  
VUVLO,hys  
VIN rising  
VIN falling  
1.90  
2.20  
70  
2.65  
mV  
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater.  
(2) VDO is not measured for devices with VOUT(NOM) < 2.8 V because minimum VIN = 2.7 V.  
Copyright © 2008–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
www.ti.com  
DEVICE INFORMATION  
FUNCTIONAL BLOCK DIAGRAMS  
IN  
OUT  
IN  
OUT  
Ω
400  
Ω
400  
µ
2
A
Ω
3.3M  
Current  
Limit  
Current  
Limit  
Overshoot  
Detect  
Overshoot  
Detect  
Thermal  
Shutdown  
Thermal  
Shutdown  
EN  
EN  
UVLO  
UVLO  
Quickstart  
1.193V  
Bandgap  
1.193V  
Bandgap  
NR  
FB  
500k  
500k  
GND  
GND  
Figure 1. Fixed-Voltage Version  
Figure 2. Adjustable-Voltage Version  
PIN CONFIGURATIONS  
DDC (TSOT-23-5) PACKAGE  
(TOP VIEW)  
DRV (SON-6) PACKAGE  
(TOP VIEW)  
OUT  
FB  
1
2
3
6
5
4
IN  
5
4
1
2
3
IN  
GND  
EN  
OUT  
NR  
GND  
N/C  
EN  
GND  
N/C – No internal connection  
Table 1. PIN DESCRIPTIONS  
PIN  
NO.  
DESCRIPTION  
NAME  
DDC  
DRV  
6
IN  
1
2
Input supply  
Ground. The pad must be tied to GND.  
GND  
3, Pad  
Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into  
shutdown mode. EN can be connected to IN if not used.  
EN  
NR  
FB  
3
4
4
4
2
2
Fixed-voltage versions only; connecting an external capacitor to this pin bypasses noise generated by  
the internal bandgap. This capacitor allows output noise to be reduced to very low levels.  
Adjustable version only; this pin is the input to the control loop error amplifier, and is used to set the  
output voltage of the device.  
Output of the regulator. A small capacitor (total typical capacitance ≥ 2 μF ceramic) is needed from  
this pin to ground to ensure stability.  
OUT  
N/C  
5
1
5
—
Not internally connected. This pin must either be left open or tied to GND.  
4
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Copyright © 2008–2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
 
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
www.ti.com  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
TYPICAL CHARACTERISTICS  
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA, VEN = VIN  
COUT = 2.2 μF, CNR = 0.01 μF (unless otherwise noted). For TPS79901, VOUT = 3 V. Typical values are at TJ = 25°C.  
LOAD REGULATION LINE REGULATION  
,
28.50  
21.38  
14.25  
7.13  
0
1.0  
0.8  
0.6  
0.4  
0.2  
0
IOUT = 100mA  
T
= −40°C  
J
T
= +25°C  
J
T
= +25°C  
J
T
= −40°C  
J
−
−
−
−
−
0.2  
0.4  
0.6  
0.8  
1.0  
−
7.13  
T
= +125°C  
J
T
= +85°C  
−
14.25  
21.38  
28.50  
J
T
= +125°C  
T
= +85°C  
J
J
−
−
2.5  
3.5  
4.5  
5.5  
6.5  
7.5  
0
50  
100  
150  
200  
VIN (V)  
IOUT (mA)  
Figure 3.  
Figure 4.  
OUTPUT VOLTAGE vs  
JUNCTION TEMPERATURE  
TPS79901 DROPOUT vs  
INPUT VOLTAGE  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
2.0  
1.5  
1.0  
0.5  
0
IOUT = 200mA  
IOUT = 1mA  
IOUT = 100mA  
−
−
−
−
0.5  
1.0  
1.5  
2.0  
IOUT = 200mA  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5 6.0  
6.5  
7.0  
−
−
−
40 25 15  
5
20 35 50 65 80 95 110 125  
(°C)  
VIN (V)  
T
J
Figure 5.  
Figure 6.  
GROUND PIN CURRENT vs  
INPUT VOLTAGE  
GROUND PIN CURRENT (DISABLED) vs  
JUNCTION TEMPERATURE  
60  
50  
40  
30  
20  
10  
0
600  
500  
400  
300  
200  
100  
0
VEN = 0.4V  
IOUT = 200mA  
IOUT = 500mA  
VIN = 6.5V  
VIN = 3.2V  
VOUT = 2.85V  
6.0 6.5 7.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
−
−
−
40 25 15  
5
20 35 50 65 80 95 110 125  
T
(°C)  
VIN (V)  
J
Figure 7.  
Figure 8.  
Copyright © 2008–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
www.ti.com  
TYPICAL CHARACTERISTICS (continued)  
Over operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(TYP) + 0.3 V or 2.7 V, whichever is greater; IOUT = 1 mA,  
VEN = VIN, COUT = 2.2 μF, CNR = 0.01 μF (unless otherwise noted). For TPS79901, VOUT = 3 V. Typical values are at  
TJ = 25°C.  
POWER-SUPPLY RIPPLE REJECTION vs  
IN – VOUT, IOUT = 1 mA  
POWER-SUPPLY RIPPLE REJECTION vs  
IN – VOUT, IOUT = 100 mA  
V
V
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0.1kHz  
1MHz  
1kHz  
0.1kHz  
1kHz  
10kHz  
100kHz  
10kHz  
100kHz  
1MHz  
µ
µ
µ
F
µ
CNR = 0.01  
F
CNR = 0.01  
COUT = 2.2 F  
COUT = 2.2 F  
0.0  
0.5 1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0 3.5 4.0  
−
−
VIN VOUT (V)  
VIN VOUT (V)  
Figure 9.  
Figure 10.  
POWER-SUPPLY RIPPLE REJECTION vs  
IN – VOUT, IOUT = 200 mA  
V
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
0.1kHz  
1kHz  
10kHz  
100kHz  
1MHz  
2.5  
µ
µ
CNR = 0.01  
COUT = 2.2 F  
F
0.0  
0.5  
1.0  
1.5  
2.0  
3.0 3.5 4.0  
−
VIN VOUT (V)  
Figure 11.  
6
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Copyright © 2008–2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
 
 
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
www.ti.com  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
APPLICATION INFORMATION  
The TPS799xx family of LDO regulators combines the high performance required of many RF and precision  
analog applications with ultra-low current consumption. High PSRR is provided by a high gain, high bandwidth  
error loop with good supply rejection at very low headroom (VIN – VOUT). Fixed voltage versions provide a noise  
reduction pin to bypass noise generated by the bandgap reference and to improve PSRR while a quick-start  
circuit fast-charges this capacitor at startup. The combination of high performance and low ground current also  
make the TPS799xx an excellent choice for portable applications. All versions have thermal and over-current  
protection and are fully specified from –40°C to 125°C.  
Figure 12 shows the basic circuit connections for fixed-voltage model. Figure 13 gives the connections for the  
adjustable output version (TPS79901). R1 and R2 can be calculated for any output voltage using the formula in  
Figure 13. Sample resistor values for common output voltages are shown in Figure 13.  
Input and Output Capacitor Requirements  
Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to  
1-μF low ESR capacitor across the input supply near the regulator. This counteracts reactive input sources and  
improve transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if  
large, fast rise-time load transients are anticipated or the device is located several inches from the power source.  
If source impedance is not sufficiently low, a 0.1-μF input capacitor may be necessary to ensure stability.  
The TPS799xx is designed to be stable with standard ceramic capacitors of values 2.2 μF or larger. X5R and  
X7R type capacitors are best as they have minimal variation in value and ESR over temperature. Maximum ESR  
should be <1.0 Ω.  
Feedback Capacitor Requirements (TPS79901 only)  
The feedback capacitor, CFB, shown in Figure 13 is required for stability. For a parallel combination of R1 and R2  
equal to 250 kΩ, any value from 3 pF to 1 nF can be used. Fixed voltage versions have an internal 30-pF  
feedback capacitor which is quick-charged at start-up. The adjustable version does not have this quick-charge  
circuit, so values below 5 pF should be used to ensure fast startup; values above 47 pF can be used to  
implement an output voltage soft-start. Larger value capacitors also improve noise slightly. The TPS79901 is  
stable in unity-gain configuration (OUT tied to FB) without CFB  
.
Output Noise  
In most LDOs, the bandgap is the dominant noise source. If a noise reduction capacitor (CNR) is used with the  
TPS799xx, the bandgap does not contribute significantly to noise. Instead, noise is dominated by the output  
resistor divider and the error amplifier input. To minimize noise in a given application, use a 0.01-μF noise  
reduction capacitor; for the adjustable version, smaller value resistors in the output resistor divider reduce noise.  
A parallel combination that gives 2 μA of divider current has the same noise performance as a fixed-voltage  
version. To further optimize noise, equivalent series resistance of the output capacitor can be set to  
approximately 0.2 Ω. This configuration maximizes phase margin in the control loop, reducing total output noise  
by up to 10%.  
Optional input capacitor.  
Optional input capacitor.  
(R1 + R2)  
VOUT  
=
´ 1.193  
May improve source  
May improve source  
R2  
impedance, noise, or PSRR.  
impedance, noise, or PSRR.  
VIN  
VOUT  
VIN  
VOUT  
IN  
OUT  
TPS799xx  
IN  
OUT  
FB  
TPS79901  
R1  
R2  
CFB  
µ
2.2  
F
2.2mF  
Ceramic  
EN  
GND  
NR  
EN  
GND  
Ceramic  
VEN  
VEN  
Optional bypass capacitor  
to reduce output noise  
and increase PSRR.  
Figure 12. Typical Application Circuit for  
Fixed Voltage Version  
Figure 13. Typical Application Circuit for  
Adjustable Voltage Version  
Noise can be referred to the feedback point (FB pin) such that with CNR = 0.01 μF, total noise is approximately  
given by Equation 1:  
Copyright © 2008–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
 
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
www.ti.com  
10.5mVRMS  
VN =  
x VOUT  
V
(1)  
The TPS79901 adjustable version does not have the noise-reduction pin available, so ultra-low noise operation is  
not possible. Noise can be minimized according to the previous recommendations.  
Board Layout Recommendations to Improve PSRR and Noise Performance  
To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the  
board be designed with separate ground planes for VIN and VOUT, with each ground plane connected only at the  
GND pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the  
GND pin of the device.  
Internal Current Limit  
The TPS799xx internal current limit helps protect the regulator during fault conditions. During current limit, the  
output sources a fixed amount of current that is largely independent of output voltage. For reliable operation, the  
device should not be operated in current limit for extended periods of time.  
The PMOS pass element in the TPS799xx has a built-in body diode that conducts current when the voltage at  
OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is  
anticipated, external limiting may be appropriate.  
Shutdown  
The enable pin (EN) is active high and is compatible with standard and low voltage TTL-CMOS levels. When  
shutdown capability is not required, EN can be connected to IN.  
Dropout Voltage  
The TPS799xx uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout  
voltage (VDO), the PMOS pass device is in its linear region of operation and the input-to-output resistance is the  
RDS, ON of the PMOS pass element. Because the PMOS device behaves like a resistor in dropout, VDO scales  
approximately with output current.  
As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.  
This effect is shown in Figure 9 through Figure 11 in the Typical Characteristics section.  
Startup  
Fixed voltage versions of the TPS799xx use a quick-start circuit to fast-charge the noise reduction capacitor,  
CNR, if present (see Functional Block Diagrams, Figure 1). This allows the combination of very low output noise  
and fast start-up times. The NR pin is high impedance so a low leakage CNR capacitor must be used; most  
ceramic capacitors are appropriate in this configuration.  
Note that for fastest startup, VIN should be applied first, then the enable pin (EN) driven high. If EN is tied to IN,  
startup is somewhat slower. The quick-start switch is closed for approximately 135 μs. To ensure that CNR is fully  
charged during the quick-start time, a 0.01 μF or smaller capacitor should be used.  
Transient Response  
As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but  
increase duration of the transient response. In the adjustable version, adding CFB between OUT and FB  
improves stability and transient response. The transient response of the TPS799xx is enhanced by an active  
pulldown that engages when the output overshoots by approximately 5% or more when the device is enabled.  
When enabled, the pulldown device behaves like a 350-Ω resistor to ground.  
Undervoltage Lockout (UVLO)  
The TPS799xx utilizes a UVLO circuit to keep the output shut off until internal circuitry is operating properly. The  
UVLO circuit has a deglitch feature so that it typically ignores undershoot transients on the input if they are less  
than 50-μs duration.  
8
Submit Documentation Feedback  
Copyright © 2008–2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
www.ti.com  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
Minimum Load  
The TPS799xx is stable and well behaved with no output load. To meet the specified accuracy, a minimum load  
of 500 μA is required. Below 500 μA at junction temperatures near 125°C, the output can drift up enough to  
cause the output pulldown to turn on. The output pulldown limits voltage drift to 5% typically, but ground current  
could increase by approximately 50 μA. In typical applications, the junction cannot reach high temperatures at  
light loads since there is no appreciable dissipated power. The specified ground current would then be valid at no  
load in most applications.  
THERMAL INFORMATION  
Thermal Protection  
Thermal protection disables the output when the junction temperature rises to approximately 165°C, allowing the  
device to cool. When the junction temperature cools to approximately 145°C, the output circuitry is again  
enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection  
circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage due to  
overheating.  
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate  
heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the  
margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal  
protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should  
trigger at least 35°C above the maximum expected ambient condition of your particular application. This  
configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature  
and worst-case load.  
The internal protection circuitry of the TPS799xx has been designed to protect against overload conditions. It  
was not intended to replace proper heatsinking. Continuously running the TPS799xx into thermal shutdown  
degrades device reliability.  
Power Dissipation  
The ability to remove heat from the die is different for each package type, presenting different considerations in  
the PCB layout. The PCB area around the device that is free of other components moves the head from the  
device to the ambient air. Performance data for JEDEC low- and high-K boards are given in the Thermal  
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The  
addition of plated through holes to heat-dissipating layers also improves the heatsink effectiveness.  
Power dissipation depends on input voltage and load conditions. Power dissipation is equal to the product of the  
output current times the voltage drop across the output pass element, as shown in Equation 2:  
ǒ
Ǔ
PD + VIN*VOUT   IOUT  
(2)  
Package Mounting  
Solder pad footprint recommendations for the TPS799xx are available from the Texas Instruments' web site at  
www.ti.com.  
Copyright © 2008–2012, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
 
TPS79901-Q1, TPS79912-Q1, TPS79915-Q1  
TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1  
SBVS097E –MARCH 2008–REVISED JANUARY 2012  
www.ti.com  
REVISION HISTORY  
Changes from Revision D (June 2011) to Revision E  
Page  
•
Changed CDM ESD rating from 500 V to 1000 V ................................................................................................................ 2  
10  
Submit Documentation Feedback  
Copyright © 2008–2012, Texas Instruments Incorporated  
Product Folder Link(s): TPS79901-Q1 TPS79912-Q1 TPS79915-Q1 TPS79918-Q1 TPS79925-Q1 TPS79927-Q1  
TPS79933-Q1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2012  
PACKAGING INFORMATION  
Status (1)  
Eco Plan (2)  
MSL Peak Temp (3)  
Samples  
Orderable Device  
Package Type Package  
Drawing  
Pins  
Package Qty  
Lead/  
Ball Finish  
(Requires Login)  
TPS79901QDRVRQ1  
TPS79912QDRVRQ1  
TPS79915QDDCRQ1  
TPS79915QDRVRQ1  
TPS79918QDDCRQ1  
TPS79925QDDCRQ1  
TPS79927QDDCRQ1  
TPS79927QDRVRQ1  
TPS79933QDDCRQ1  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SON  
SON  
SOT  
SON  
SOT  
SOT  
SOT  
SON  
SOT  
DRV  
DRV  
DDC  
DRV  
DDC  
DDC  
DDC  
DRV  
DDC  
6
6
5
6
5
5
5
6
5
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-1-260C-UNLIM  
CU NIPDAU Level-2-260C-1 YEAR  
CU NIPDAU Level-1-260C-UNLIM  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
24-Jan-2012  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF TPS79901-Q1, TPS79912-Q1, TPS79915-Q1, TPS79918-Q1, TPS79925-Q1, TPS79927-Q1, TPS79933-Q1 :  
Catalog: TPS79901, TPS79912, TPS79915, TPS79918, TPS79925, TPS79927, TPS79933  
•
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
•
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jan-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
TPS79912QDRVRQ1  
TPS79915QDDCRQ1  
TPS79915QDRVRQ1  
TPS79925QDDCRQ1  
TPS79927QDDCRQ1  
TPS79927QDRVRQ1  
TPS79933QDDCRQ1  
SON  
SOT  
SON  
SOT  
SOT  
SON  
SOT  
DRV  
DDC  
DRV  
DDC  
DDC  
DRV  
DDC  
6
5
6
5
5
6
5
3000  
3000  
3000  
3000  
3000  
3000  
3000  
179.0  
179.0  
179.0  
179.0  
179.0  
179.0  
179.0  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
8.4  
2.2  
3.2  
2.2  
3.2  
3.2  
2.2  
3.2  
2.2  
3.2  
2.2  
3.2  
3.2  
2.2  
3.2  
1.2  
1.4  
1.2  
1.4  
1.4  
1.2  
1.4  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
4.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
8.0  
Q2  
Q3  
Q2  
Q3  
Q3  
Q2  
Q3  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
23-Jan-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
TPS79912QDRVRQ1  
TPS79915QDDCRQ1  
TPS79915QDRVRQ1  
TPS79925QDDCRQ1  
TPS79927QDDCRQ1  
TPS79927QDRVRQ1  
TPS79933QDDCRQ1  
SON  
SOT  
SON  
SOT  
SOT  
SON  
SOT  
DRV  
DDC  
DRV  
DDC  
DDC  
DRV  
DDC  
6
5
6
5
5
6
5
3000  
3000  
3000  
3000  
3000  
3000  
3000  
195.0  
203.0  
195.0  
203.0  
203.0  
195.0  
203.0  
200.0  
203.0  
200.0  
203.0  
203.0  
200.0  
203.0  
45.0  
35.0  
45.0  
35.0  
35.0  
45.0  
35.0  
Pack Materials-Page 2  
IMPORTANT NOTICE  
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