TPS7A0228PDQNR [TI]
具有使能功能的 200mA、毫微功耗 IQ (25nA)、低压降 (LDO) 稳压器 | DQN | 4 | -40 to 125;
| 型号： | TPS7A0228PDQNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 200mA、毫微功耗 IQ (25nA)、低压降 (LDO) 稳压器 | DQN | 4 | -40 to 125 稳压器 |
| 文件： | 总43页 (文件大小：3228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7A02
SBVS277B –JULY 2019–REVISED MARCH 2020
TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast
Transient Response
1 Features
3 Description
The TPS7A02 is an ultra-small, ultra-low quiescent
current low-dropout linear regulator (LDO) that can
source 200 mA with excellent transient performance.
1
•
Ultra-low IQ: 25 nA (typ), even in dropout
Shutdown IQ: 3 nA (typ)
•
•
Excellent transient response (1 mA to 50 mA)
The TPS7A02, with an ultra-low IQ of 25 nA, is
designed specifically for applications where very-low
quiescent current is a critical parameter. This device
maintains low IQ consumption even in dropout mode
to further increase the battery life. When in shutdown
or disabled mode, the device consumes ultra-low,
3-nA IQ that helps increase the shelf life of the
battery. The TPS7A02 has an output range of 0.8 V
to 5.0 V available in 50-mV steps to support the lower
core voltages of modern microcontrollers (MCUs).
–
–
< 10-µs settling time
100-mV undershoot
•
Packages:
–
–
–
1.0-mm × 1.0-mm X2SON
SOT23-5
0.64-mm x 0.64-mm DSBGA (preview)
•
•
•
•
•
Input voltage range: 1.5 V to 6.0 V
Output voltage range: 0.8 V to 5.0 V (fixed)
Output accuracy: 1.5% over temperature
Smart enable pulldown
The TPS7A02 features a smart enable circuit with an
internally controlled pulldown resistor that keeps the
LDO disabled even when the EN pin is left floating
and helps minimize the external components used to
pulldown the EN pin. This circuit also helps minimize
the current drawn through the external pulldown
circuit when the device is enabled.
Very low dropout:
–
270 mV (max) at 200 mA (VOUT = 3.3 V)
•
Stable with a 1-µF or larger capacitor
The TPS7A02 is fully specified for TJ = –40°C to
+125°C operation.
2 Applications
•
•
•
•
•
•
•
Wearables electronics
Device Information(1)
Thermostats, smoke and heat detectors
Gas, heat, and water meters
PART NUMBER
PACKAGE
BODY SIZE (NOM)
1.00 mm × 1.00 mm
0.64 mm × 0.64 mm
2.90 mm × 1.60 mm
X2SON (4)
Blood glucose monitors and pulse oximeters
Residential circuit breakers and fault indicators
Building security and video surveillance devices
EPOS card readers
TPS7A02
DSBGA (4)(2)
SOT-23 (5)
(1) For all available packages, see the package option addendum
at the end of the data sheet.
(2) Preview package.
Load Transient Response
(VIN = VOUT + 1 V, COUT = 1 µF,
IOUT = 1 mA to 50 mA in 1 µs)
Ground Current Efficiency vs Output Current
102
100
98
400
350
300
250
200
150
100
50
250
200
150
100
50
96
94
0
-50
92
-100
-150
-200
-250
-300
-350
90
0
-50
88
TJ
-100
-150
-200
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
100
86
84
VOUT
IOUT
0.001
0.01
0.1 1
Output Current (mA)
10
-200 -100
0
100 200 300 400 500 600 700 800
Time (µs)
Curr
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A02
SBVS277B –JULY 2019–REVISED MARCH 2020
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 22
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 26
Power Supply Recommendations...................... 27
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 ESD Ratings.............................................................. 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 19
8
9
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Examples................................................... 28
11 Device and Documentation Support ................. 29
11.1 Device Support .................................................... 29
11.2 Receiving Notification of Documentation Updates 29
11.3 Community Resources.......................................... 29
11.4 Trademarks........................................................... 29
11.5 Electrostatic Discharge Caution............................ 29
11.6 Glossary................................................................ 29
7
12 Mechanical, Packaging, and Orderable
Information ........................................................... 29
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (December 2019) to Revision B
Page
•
Changed DBV (SOT23-5) package from preview to production data .................................................................................... 1
Changes from Original (July 2019) to Revision A
Page
•
Changed device status from advance information to production data ................................................................................... 1
2
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Copyright © 2019–2020, Texas Instruments Incorporated
TPS7A02
www.ti.com
SBVS277B –JULY 2019–REVISED MARCH 2020
5 Pin Configuration and Functions
DQN Package
1-mm × 1-mm, 4-pin X2SON
Top View
DBV Package
5-Pin SOT-23
Top View
OUT
1
4
IN
IN
GND
EN
1
2
3
5
OUT
Thermal Pad
4
NC
GND
2
3
EN
Not to scale
Not to scale
Pin Functions: DQN, DBV
PIN
NAME
EN
DQN
DBV
I/O(1)
Input
—
DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low
or floating this pin disables the device. This pin features an internal pulldown resistor,
which is disconnected when EN is driven high externally and the device has started up.
3
2
3
2
GND
IN
Ground pin. This pin must be connected to ground on the board.
Input pin. For best transient response and to minimize input impedance, use the
recommended value or larger ceramic capacitor from IN to ground; see the
Recommended Operating Conditions table. Place the input capacitor as close to the
input of the device as possible.
4
—
1
1
4
5
Input
—
NC
No connect pin. This pin is not internally connected. Connect to ground or leave floating.
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to
ground for stability. For best transient response, use a 1-µF or larger ceramic capacitor
from OUT to ground. Place the output capacitor as close to output of the device as
possible; see the Recommended Operating Conditions table.
OUT
Output
Connect the thermal pad to a large-area ground plane. The thermal pad is internally
connect to ground.
Thermal pad
––
—
(1) NC = No internal connection.
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SBVS277B –JULY 2019–REVISED MARCH 2020
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YCH Package (Preview)
4-Pin DSBGA, 0.35-mm Pitch
Top View
YCH Package (Preview)
4-Pin DSBGA, 0.35-mm Pitch
Bottom View
1
2
1
2
A
IN
OUT
B
EN
GND
B
EN
GND
A
IN
OUT
Not to scale
Not to scale
Pin Functions: YCH
PIN
NAME
EN
YCH
B1
I/O
Input
—
DESCRIPTION
Enable pin. Driving this pin to logic high enables the device; driving this pin to logic low or floating
this pin disables the device. This pin features an internal pulldown resistor, which is disconnected
when EN is driven high externally and the device has started up.
GND
IN
B2
Ground pin. This pin must be connected to ground and the thermal pad.
Input pin. For best transient response and to minimize input impedance, use the recommended
value or larger ceramic capacitor from IN to ground; see the Recommended Operating
Conditions table. Place the input capacitor as close to input of the device as possible.
A1
Input
Regulated output pin. A 0.5-µF or greater effective capacitance is required from OUT to ground
for stability. For best transient response, use a 1-µF or larger ceramic capacitor from OUT to
ground. Place the output capacitor as close to output of the device as possible; see the
Recommended Operating Conditions table.
OUT
A2
Output
4
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TPS7A02
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SBVS277B –JULY 2019–REVISED MARCH 2020
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
VIN
6.5
6.5
Voltage
VEN
V
VOUT
VIN + 0.3 or 5.5(2)
Current
Maximum output
Operating junction, TJ
Storage, Tstg
Internally limited
A
–40
–65
150
150
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Maximum is VIN + 0.3 V or 5.5 V, whichever is smaller.
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted)
MIN
1.5
0
NOM
MAX
6.0
UNIT
VIN
Input voltage
V
V
VEN
VOUT
IOUT
CIN
Enable voltage
Output voltage
Output current
Input capacitor
Output capacitor(1)
6.0
0.8
0
5.0
V
200
mA
µF
µF
kHz
°C
1
1
(2)
COUT
FEN
TJ
1
22
10
EN toggle frequency
Operating junction temperature
–40
125
(1) Effective output capacitance of 0.5 µF minimum required for stability.
(2) 22 µF is the maximum derated capacitance that can be used for stability.
6.4 Thermal Information
TPS7A02
DBV (SOT-23-5)
5 PINS
181.9
THERMAL METRIC(1)
DQN (X2SON)
4 PINS
179.1
YCH (DSBGA)
UNIT
4 PINS
TBD
TBD
TBD
TBD
TBD
TBD
RθJA
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
137.6
53.0
116.3
88.1
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case(bottom) thermal resistance
6.1
27.1
ψJB
116.3
52.7
RθJC(bot)
112.3
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBVS277B –JULY 2019–REVISED MARCH 2020
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6.5 Electrical Characteristics
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
=
PARAMETER
TEST CONDITIONS
TJ = 25°C, VOUT ≥ 1.5 V, 1 µA(1) ≤ IOUT ≤ 1 mA
TJ = 25°C; VOUT < 1.5 V
MIN
–1
TYP
MAX UNIT
1
15
%
mV
%
Nominal accuracy
–15
–1.5
–20
VOUT ≥ 1.5 V
1.5
20
Accuracy over
temperature
TJ = –40°C to +125°C
VOUT < 1.5 V
mV
VOUT(nom) + 0.5 V ≤ VIN ≤ 6.0 V(2)
ΔVOUT(ΔVIN
)
Line regulation
TJ = –40°C to +125°C
TJ = –40°C to +85°C
TJ = –40°C to +125°C
5
38
50
mV
20
25
1 mA ≤ IOUT ≤ 200 mA,
VIN = VOUT(nom) + 0.5 V(2)
ΔVOUT(ΔIOUT
)
Load regulation(3)
mV
TJ = 25°C
46
60
IGND
Ground current
IOUT = 0 mA
nA
%
TJ = –40°C to +85°C
5 µA ≤ IOUT < 1 mA
1
0.25
0.15
Ground current vs
load current
IGND/IOUT
1 mA ≤ IOUT < 100 mA
TJ = 25°C
IOUT ≥ 100 mA
Ground current in
dropout(1)
IGND(DO)
ISHDN
IOUT = 0 mA, VIN = 95% x VOUT(NOM)
TJ = 25°C
25
3
nA
nA
Shutdown current
VEN = 0 V, 1.5 V ≤ VIN ≤ 5.0 V, TJ = 25°C
10
VOUT < 2.5V,
240
240
450
750
mA
VIN = VOUT(nom)
VDO(max) + 1.0 V
+
ICL
Output current limit VOUT = 90% × VOUT(nom)
VOUT ≥ 2.5V,
450
65
750
mA
mA
VIN = VOUT(nom)
VDO(max) + 0.5 V
+
Short-circuit current
VOUT = 0 V
limit
ISC
0.8 V ≤ VOUT < 1.0 V
1.0 V ≤ VOUT < 1.2 V
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 1.8 V
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
3.3 V ≤ VOUT ≤ 5.0 V
0.8 V ≤ VOUT < 1.0 V
1.0 V ≤ VOUT < 1.2 V
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 1.8 V
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
3.3 V ≤ VOUT ≤ 5.0 V
1050
790
650
490
400
310
270
1100
850
700
560
450
360
310
TJ = –40°C to +85°C
VDO
Dropout voltage(4)
mV
TJ = –40°C to +125°C
Power-supply
PSRR
VN
f = 1 kHz, IOUT = 30 mA
rejection ratio
55
dB
Output voltage
noise
BW = 10 Hz to 100 kHz, VOUT = 0.8 V, IOUT = 30 mA
130
µVRMS
VIN rising
VIN falling
1.23
1.0
1.3
1.47
1.41
VUVLO
UVLO threshold
V
1.12
(1) Specified by design
(2) VIN = 2.0 V for VOUT ≤ 1.5 V.
(3) Load Regulation is normalized to the output voltage at IOUT = 1 mA.
(4) Dropout is measured by ramping VIN down until VOUT = VOUT(nom) x 95%, with IOUT = 200 mA.
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SBVS277B –JULY 2019–REVISED MARCH 2020
Electrical Characteristics (continued)
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
=
PARAMETER
VUVLO(HYST) UVLO hysteresis
TEST CONDITIONS
MIN
TYP
MAX UNIT
VIN hysteresis
180
mV
EN pin logic high
voltage
VEN(HI)
VEN(LOW)
IEN
REN(PULLDOWN)
RPULLDOWN
1.1
V
EN pin logic low
voltage
0.3
V
EN pin leakage
current
VEN = VIN = 6.0 V
VEN = 0.3 V
10
nA
Smart enable
pulldown resistor
500
60
KΩ
Pulldown resistor
VIN = 3.3 V, device disabled
Ω
Thermal shutdown
temperature
TSD(shutdown)
Shutdown, temperature increasing
170
°C
Thermal shutdown
reset temperature
TSD(reset)
Reset, temperature decreasing
145
6.6 Switching Characteristics
Specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN
COUT = 1 µF (unless otherwise noted). Typical values are at TJ = 25°C.
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
0.8V ≤ VOUT ≤ 1.5 V
500
800
tSTR
Start-up time
From EN assertion to VOUT = 90% × VOUT(nom) 1.5V < VOUT ≤ 3.0 V
3.0V < VOUT ≤ 5.0 V
750
1200
1600
µs
1200
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6.7 Typical Characteristics
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
60
50
40
30
20
10
0
700
650
600
550
500
450
400
350
300
250
200
150
100
50
TJ
0°C
25°C
TJ
125°C
140°C
-55°C
-40°C
85°C
0
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
IOUT = 0 mA, VEN = VIN
IOUT = 0 mA, VEN = VIN
Figure 1. IQ vs VIN and Temperature
Figure 2. IQ vs VIN and Temperature
500
450
400
350
300
250
200
150
100
50
500000
100000
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
10000
1000
100
0
10
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
0.001
0.01
0.1 1
Output Current (mA)
10
100200
VOUT = 1.8 V, VIN = VEN = 2.3 V
VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 4. IQ vs IOUT and Temperature Up to 200 mA
Figure 3. IQ vs IOUT and Temperature up to 200 mA
25
20
15
10
5
5000
4000
3000
2000
1000
0
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
0
0
0.2
0.4 0.6
Output Current (mA)
0.8
1
1
3
5
Output Current (mA)
7
9
10
VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 5. IQ vs IOUT and Temperature Up to 1 mA
VOUT = 1.8 V, VIN = VEN = 2.3 V
Figure 6. IQ vs IOUT and Temperature for 1 mA to 10 mA
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
60
50
40
30
20
10
0
300
250
200
150
100
50
TJ
0°C
25°C
TJ
125°C
140°C
-55°C
-40°C
85°C
0
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
VOUT = 5.0 V, VEN = VIN
VOUT = 5.0 V, VEN = VIN
Figure 7. IQ in Dropout vs VIN and Temperature
Figure 8. IQ in Dropout vs VIN and Temperature
4000
3000
2000
1000
0
6
5
4
3
2
1
0
TJ
TJ
-55°C
-40°C
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
0°C
25°C
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
6
IOUT = 0 mA, VEN = 1.1 V
VEN = 0 V
Figure 9. IQ vs VIN and Temperature
Figure 10. ISHDN vs VIN and Temperature
400
350
300
250
200
150
100
50
400
250
200
150
100
50
TJ
85°C
125°C
350
300
250
200
150
100
50
140°C
0
-50
-100
-150
-200
-250
-300
-350
0
-50
-100
-150
-200
VOUT
IOUT
0
1.5
2
2.5
3
3.5 4
Input Voltage (V)
4.5
5
5.5
6
-200 -100
0
100 200 300 400 500 600 700 800
Time (µs)
VEN = 0 V
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 11. ISHDN vs VIN and Temperature
Figure 12. IOUT Transient From 1 mA to 50 mA
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
400
350
300
250
200
150
100
50
250
200
150
100
50
400
350
300
250
200
150
100
50
250
200
150
100
50
0
0
-50
-50
-100
-150
-200
-250
-300
-350
-100
-150
-200
-250
-300
-350
0
0
-50
-50
-100
-150
-200
-100
-150
-200
VOUT
IOUT
VOUT
IOUT
-200 -100
0
100 200 300 400 500 600 700 800
Time (µs)
-200 -100
0
100 200 300 400 500 600 700 800
Time (µs)
Load
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 13. IOUT Transient From 1 mA to 100 mA
Figure 14. IOUT Transient From 1 mA to 200 mA
200
100
75
280
240
200
160
120
80
100
175
150
125
100
75
75
50
50
25
25
0
0
-25
-50
-75
-100
-125
-150
-175
-200
-25
-50
-75
-100
-125
-150
-175
-200
50
40
25
0
0
-40
-80
-120
-160
-200
-25
-50
-75
VOUT
IOUT
VOUT
IOUT
-100
80
90 100 110 120 130 140 150 160 170 180
Time (ms)
Load
-60 -40 -20
0
20
40
Time (µs)
60
80 100 120 140
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Load
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 16. IOUT Transient From 50 mA to 0 mA
Figure 15. IOUT Transient From 0 mA to 50 mA
420
200
150
100
50
200
200
150
100
50
360
300
240
180
120
60
175
150
125
100
75
0
0
-50
-50
-100
-150
-200
-250
-300
-350
-400
50
-100
-150
-200
-250
-300
-350
-400
0
25
-60
0
-120
-180
-240
-300
-25
-50
-75
-100
IOUT
VOUT
VOUT
IOUT
-80 -60 -40 -20
0
20
Time (µs)
40
60
80 100 120
-10
0
10
20
30
40
Time (ms)
50
60
70
80
90
Load
Load
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 17. IOUT Transient From 0 mA to 100 mA
Figure 18. IOUT Transient From 100 mA to 0 mA
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
420
360
300
240
180
120
60
300
250
200
150
100
50
400
350
300
250
200
150
100
50
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
0
0
-50
-60
-100
-150
-200
-250
-300
0
-120
-180
-240
-300
-50
VOUT
IOUT
-100
-150
-200
VOUT
IOUT
-30 -20 -10
0
10
20
Time (µs)
30
40
50
60
70
Load
-10
0
10
20
30 40
Time (ms)
50
60
70
80
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, tr = tf = 1 µs
Figure 19. IOUT Transient From 0 mA to 200 mA
Figure 20. IOUT Transient From 200 mA to 0 mA
400
10
150
6
350
300
250
200
150
100
50
7.5
5
125
100
75
4.5
3
2.5
0
1.5
0
-2.5
-5
50
-7.5
-10
-12.5
25
-1.5
-3
0
-50
0
-100
-150
-200
-15
-25
-50
-4.5
-6
VOUT
VIN
VOUT
VIN
-17.5
-20
-40
0
40
80 120 160 200 240 280 320 360
Time (µs)
-200 -100
0
100 200 300 400 500 600 700
Time (µs)
Line
Line
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, slew rate = 1 V/µs
VOUT = 1.8 V, IOUT = 1 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 21. VIN Transient From 2.8 V to 4.8 V
Figure 22. VIN Transient From 2.8 V to 6.0 V
5
4.5
4
5
150
125
100
75
10
7.5
5
4.5
4
3.5
3
3.5
3
2.5
0
2.5
2
2.5
2
50
25
-2.5
-5
1.5
1
1.5
1
0
VOUT
VIN
-25
-50
-7.5
-10
VOUT
VIN
0.5
0
0.5
0
-40
0
40
80 120 160 200 240 280 320 360
Time (µs)
-40 -20
0
20
40
60
Time (µs)
80 100 120 140 160
Drop
Line
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, slew rate = 1 V/µs
VOUT = 1.8 V, IOUT = 100 mA, COUT = 1 µF, slew rate = 1 V/µs
Figure 23. VIN Transient From 2.8 V to 6.0 V
Figure 24. VIN Transient From 1.5 V to 4.5 V
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
10
0.3
TJ
TJ
8
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
6
0.1
4
2
0
-0.1
-0.3
-0.5
-2
-4
-6
-8
-10
2
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
6
2
2.5
3
3.5
4
Input Voltage (V)
4.5
5
5.5
6
VOUT = 1.8 V, IOUT = 1 mA
VOUT = 1.8 V, IOUT = 1 mA
Figure 25. Line Regulation vs VIN and Temperature
Figure 26. Output Accuracy vs VIN and Temperature
0.3
0.1
20
15
10
5
VOUT %
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
-0.1
-0.3
-0.5
0
-5
-10
-15
-60 -40 -20
0
20 40 60 80 100 120 140150
Temperature (èC)
5
5.2
5.4 5.6
Input Voltage (V)
5.8
6
VOUT = 1.8 V, IOUT = 1 mA
VOUT = 5.0 V, IOUT = 1 mA
Figure 27. Output Accuracy vs Temperature
Figure 28. Line Regulation vs VIN and Temperature
0.5
0.3
0.5
0.3
TJ
VOUT %
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
0.1
0.1
-0.1
-0.3
-0.5
-0.1
-0.3
5
5.2
5.4 5.6
Input Voltage (V)
5.8
6
-60 -40 -20
0
20 40 60 80 100 120 140150
Temperature (èC)
VOUT = 5.0 V, IOUT = 1 mA
Figure 29. Output Accuracy vs VIN and Temperature
VOUT = 5.0 V, IOUT = 1 mA
Figure 30. Output Accuracy vs Temperature
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
10
550
500
450
400
350
300
250
200
150
100
50
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
5
0
-5
-10
-15
-20
0
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
VOUT = 1.8 V
VOUT = 1.8 V
Figure 32. Dropout vs IOUT and Temperature
Figure 31. Load Regulation vs VIN and Temperature
300
280
260
240
220
200
180
160
140
120
100
80
600
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
400
200
0
60
40
20
0
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
VOUT = 5.0 V
IOUT = 200 mA
Figure 33. Dropout vs IOUT and Temperature
Figure 34. Dropout vs VIN and Temperature
300
250
200
150
100
50
1.2
TJ
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
1
0.8
0.6
0.4
0.2
0
0
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
IOUT = 50 mA
Figure 35. Dropout vs VIN and Temperature
VOUT = 0.8 V
Figure 36. Foldback Current Limit vs IOUT and Temperature
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
2.5
0.9
0.85
0.8
TJ
0°C
25°C
VEN(LOW)
VEN(HIGH)
-55°C
-40°C
85°C
125°C
2
1.5
1
0.75
0.7
0.5
0
0.65
0.6
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
-60 -40 -20
0
20 40 60 80 100 120 140150
Temperature (èC)
VOUT = 1.8 V
VOUT = 0.8 V
Figure 37. Foldback Current Limit vs IOUT and Temperature
Figure 38. EN High and Low Threshold vs Temperature
1.5
1.1
VEN(LOW)
VEN(HIGH)
VUVLO(HIGH)
VUVLO(LOW)
1.05
1.45
1.4
1
0.95
0.9
1.35
1.3
0.85
0.8
1.25
1.2
0.75
0.7
1.15
1.1
-60 -40 -20
0
20 40 60 80 100 120 140150
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140150
Temperature (èC)
VOUT = 5.0 V
VOUT = 5.0 V, IOUT = 1 mA
Figure 39. EN High and Low Threshold vs Temperature
Figure 40. UVLO Rising and Falling Threshold vs
Temperature
70
65
60
55
50
45
40
580
570
560
550
540
530
520
510
500
490
480
VOUT
1.8V
VOUT
1.8V
0.8V
5.0V
0.8V
5.0V
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
-60 -40 -20
0
20 40 60 80 100 120 140 160
Temperature (èC)
Figure 41. Pulldown Resistor vs Temperature and VOUT
Figure 42. Smart Enable Pulldown Resistor vs Temperature
and VOUT
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
IOUT
10 mA
20 mA
VIN
3.8 V
4.8 V
0 mA
1 mA
100 mA
200 mA
2.3 V
2.8 V
6.0 V
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D001
VIN = 2.8 V, VOUT = 1.8 V, COUT = 1 µF
VOUT = 1.8 V, IOUT = 20 mA, COUT = 1 µF
Figure 43. PSRR vs Frequency and IOUT
Figure 44. PSRR vs Frequency and VIN
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
VIN
3.8 V
4.8 V
VIN
2.8 V
3.8 V
2.3 V
2.8 V
6.0 V
4.8 V
6.0 V
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D001
D001
VOUT = 1.8 V, IOUT = 100 mA, COUT = 1 µF
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 45. PSRR vs Frequency and VIN
Figure 46. PSRR vs Frequency and VIN
100
50
50
VOUT
1.8 V, RMS Noise = 269.5 mVRMS
5.0 V, RMS Noise = 710 mVRMS
IOUT
100 mA, RMS Noise = 117.5 mVRMS
1 mA, RMS Noise = 269.5 mVRMS
30
20
20
10
5
10
5
3
2
2
1
1
0.5
0.5
0.3
0.2
0.2
0.1
0.1
0.05
0.05
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VIN = VOUT+ 1.0 V, IOUT = 1 mA, COUT = 1 µF
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF
Figure 47. Output Noise vs Frequency and VOUT
Figure 48. Output Noise vs Frequency and IOUT
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
50
5
VOUT
VEN = VIN
COUT
1 mF, RMS Noise = 269.5 mVRMS
22 mF, RMS Noise = 301.1 mVRMS
30
20
4
10
3
5
2
3
2
1
1
0
0.5
0.3
0.2
-1
-2
0.1
-450 -300 -150
0
150 300 450 600 750 900 1050
Time (ms)
0.05
Star
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
VOUT = 1.8 V, VIN = 2.8 V, IOUT = 1 mA
Figure 50. Startup With VEN = VIN
Figure 49. Output Noise vs Frequency and COUT
5
4
3
2
1
0
6
5
VOUT
VEN
VIN
VOUT
VEN
VIN
4
3
2
1
-1
-2
0
-1
-450 -300 -150
0
150 300 450 600 750 900 1050
Time (ms)
-600 -400 -200
0
200 400 600 800 1000 1200 1400
Time (ms)
Star
Star
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
Figure 51. Startup With VEN Before VIN
Figure 52. Startup With VEN After VIN
5.5
5
10
9
VOUT
VEN
VIN
VOUT
VEN
VIN
4.5
4
8
7
3.5
3
6
5
2.5
2
4
3
1.5
1
2
1
0.5
0
0
-0.5
-1
-450 -300 -150
0
150 300 450 600 750 900 1050
Time (ms)
-800 -400
0
400 800 1200 1600 2000 2400 2800 3200
Time (ms)
Star
Star
VOUT = 1.8 V, IOUT = 0 mA, COUT = 1 µF
VOUT = 5.0 V, IOUT = 200 mA, COUT = 1 µF
Figure 53. Startup With VEN After VIN
Figure 54. Startup With VEN After VIN
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Typical Characteristics (continued)
at operating temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
9
50
40
30
20
10
0
9
400
300
200
100
0
VIN
VIN
8
8
VEN
VOUT
IIN
VEN
VOUT
IIN
7
7
6
6
5
5
4
4
-100
-200
-300
-400
-500
-600
3
-10
-20
-30
-40
-50
3
2
2
1
1
0
0
-1
-1
-400 -200
0
200
400
Time (ms)
600
800 1000 1200
-400 -200
0
200
400
Time (ms)
600
800 1000 1200
Star
VOUT = 1.8 V, IOUT = 0 mA
Figure 55. Startup Inrush Current With COUT= 1 µF
VOUT = 1.8 V, IOUT = 0 mA
Figure 56. Startup Inrush Current With COUT= 22 µF
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7 Detailed Description
7.1 Overview
The TPS7A02 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance.
These characteristics make the device ideal for most battery-powered applications.
This low-dropout linear regulator (LDO) offers active discharge, foldback current limit, shutdown, and thermal
protection capability.
7.2 Functional Block Diagram
Current
Limit
IN
OUT
1.2-V
Bandgap
+
Active Discharge
P-Version Only
œ
œ
Error
Amp
+
UVLO
Internal
Controller
Thermal
Shutdown
EN
Smart
Enable
Resistor
GND
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7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A02 includes several innovative circuits to ensure excellent transient response. Dynamic biasing
increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the
output response time to transients.
Adaptive biasing increases the IQ as the DC load current increases, extending the bandwidth of the loop. The
response time across the output voltage range is constant because a buffered reference topology is used, which
keeps the control loop in unity gain at any output voltage.
These features give the device a wide loop bandwidth during transients that ensures excellent transient response
while maintaining low IQ in steady-state conditions.
7.3.2 Active Discharge (P-Version Only)
The device has an internal pulldown MOSFET that connects a RPULLDOWN resistor to ground when the device is
disabled to actively discharge the output voltage. The active discharge circuit is activated by the enable pin or by
the undervoltage lockout (UVLO).
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can possibly flow from the output to the input. This reverse current
flow can cause damage to the device. Limit reverse current to no more than 5% of the device rated current for a
short period of time.
7.3.3 Low IQ in Dropout
In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for
low IQ LDOs. The TPS7A02 helps to reduce the battery discharge by detecting when the device is operating in
dropout conditions and maintaining a low IQ.
7.3.4 Smart Enable
The enable pin for the device is an active-high pin. The output voltage is enabled when the voltage of the enable
pin is greater than the high-level input voltage of the EN pin and disabled with the enable pin voltage is less than
the low-level input voltage of the EN pin. If independent control of the output voltage is not needed, connect the
enable pin to the input of the device.
This device has a smart enable circuit to reduce quiescent current. When the voltage on the enable pin is driven
above VEN(HI), as listed in the Electrical Characteristics table, the device is enabled and the smart enable internal
pulldown resistor (REN(PULLDOWN)) is disconnected. When the enable pin is floating, the REN(PULLDOWN) is
connected and pulls the enable pin low to disable the device. The REN(PULLDOWN) value is listed in the Electrical
Characteristics table.
This device has an internal pulldown circuit that activates when the device is disabled to actively discharge the
output voltage.
7.3.5 Dropout Voltage
Dropout voltage (VDO) is defined as the input voltage minus the output voltage (VIN – VOUT) at the rated output
current (IRATED), where the pass transistor is fully on. IRATED is the maximum IOUT listed in the Recommended
Operating Conditions table. The pass transistor is in the ohmic or triode region of operation, and acts as a switch.
The dropout voltage indirectly specifies a minimum input voltage greater than the nominal programmed output
voltage at which the output voltage is expected to stay in regulation. If the input voltage falls to less than the
nominal output regulation, then the output voltage falls as well.
For a CMOS regulator, the dropout voltage is determined by the drain-source on-state resistance (RDS(ON)) of the
pass transistor. Therefore, if the linear regulator operates at less than the rated current, the dropout voltage for
that current scales accordingly. Use Equation 1 to calculate the RDS(ON) of the device.
VDO
RDS(ON)
=
IRATED
(1)
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Feature Description (continued)
7.3.6 Foldback Current Limit
The device has an internal current limit circuit that protects the regulator during transient high-load current faults
or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a
brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the
output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the
voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output
voltage approaches GND. When the output is shorted, the device supplies a typical current called the short-
circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.
For this device, VFOLDBACK = 0.5 V.
The output voltage is not regulated when the device is in current limit. When a current limit event occurs, the
device begins to heat up because of the increase in power dissipation. When the device is in brickwall current
limit, the pass transistor dissipates power [(VIN – VOUT) × ICL]. When the device output is shorted and the output
is below VFOLDBACK, the pass transistor dissipates power [(VIN – VOUT) × ISC]. If thermal shutdown is triggered, the
device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If
the output current fault condition continues, the device cycles between current limit and thermal shutdown. For
more information on current limits, see the Know Your Limits application report.
Figure 57 shows a diagram of the foldback current limit.
VOUT
Brickwall
VOUT(NOM)
VFOLDBACK
Foldback
0 V
IOUT
IRATED
0 mA
ISC
ICL
Figure 57. Foldback Current Limit
7.3.7 Undervoltage Lockout (UVLO)
The device has an independent undervoltage lockout (UVLO) circuit that monitors the input voltage, allowing a
controlled and consistent turn on and off of the output voltage. To prevent the device from turning off if the input
drops during turn on, the UVLO has hysteresis as specified in the Electrical Characteristics table.
7.3.8 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the junction temperature
(TJ) of the pass transistor rises to TSD(shutdown) (typical). Thermal shutdown hysteresis assures that the device
resets (turns on) when the temperature falls to TSD(reset) (typical).
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Feature Description (continued)
The thermal time-constant of the semiconductor die is fairly short, thus the device may cycle on and off when
thermal shutdown is reached until power dissipation is reduced. Power dissipation during startup can be high
from large VIN – VOUT voltage drops across the device or from high inrush currents charging large output
capacitors. Under some conditions, the thermal shutdown protection disables the device before startup
completes.
For reliable operation, limit the junction temperature to the maximum listed in the Recommended Operating
Conditions table. Operation above this maximum temperature causes the device to exceed its operational
specifications. Although the internal protection circuitry of the device is designed to protect against thermal
overall conditions, this circuitry is not intended to replace proper heat sinking. Continuously running the device
into thermal shutdown or above the maximum recommended junction temperature reduces long-term reliability.
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7.4 Device Functional Modes
7.4.1 Device Functional Mode Comparison
The Device Functional Mode Comparison table shows the conditions that lead to the different modes of
operation. See the Electrical Characteristics table for parameter values.
Table 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal operation
Dropout operation
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < TSD(shutdown)
TJ < TSD(shutdown)
Disabled
(any true condition
disables the device)
VIN < VUVLO
VEN < VEN(LOW)
Not applicable
TJ > TSD(shutdown)
7.4.2 Normal Operation
The device regulates to the nominal output voltage when the following conditions are met:
•
•
•
•
The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO
The output current is less than the current limit (IOUT < ICL
The device junction temperature is less than the thermal shutdown temperature (TJ < TSD
The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to
less than the enable falling threshold
)
)
)
7.4.3 Dropout Operation
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this mode, the output voltage
tracks the input voltage. During this mode, the transient performance of the device becomes significantly
degraded because the pass transistor is in the ohmic or triode region, and acts as a switch. Line or load
transients in dropout can result in large output-voltage deviations.
When the device is in a steady dropout state (defined as when the device is in dropout, VIN < VOUT(NOM) + VDO
,
directly after being in a normal regulation state, but not during startup), the pass transistor is driven into the
ohmic or triode region. When the input voltage returns to a value greater than or equal to the nominal output
voltage plus the dropout voltage (VOUT(NOM) + VDO), the output voltage can overshoot for a short period of time
while the device pulls the pass transistor back into the linear region.
7.4.4 Disabled
The output of the device can be shutdown by forcing the voltage of the enable pin to less than the maximum EN
pin low-level input voltage (see the Electrical Characteristics table). When disabled, the pass transistor is turned
off, internal circuits are shutdown, and the output voltage is actively discharged to ground by an internal
discharge circuit from the output to ground.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
C0G-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, expect the effective capacitance to decrease by as much as 50%. The input
and output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located
several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. There are two key transitions during a load transient response: the
transition from a light to a heavy load and the transition from a heavy to a light load. The regions shown in
Figure 58 are broken down as follows. Regions A, E, and H are where the output voltage is in steady-state.
tAt
tCt
tDt
tEt
tGt
tHt
B
F
Figure 58. Load Transient Waveform
During transitions from a light load to a heavy load, the:
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
•
Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C)
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Application Information (continued)
During transitions from a heavy load to a light load, the:
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
•
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger DC load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
8.1.4 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational
voltage range, and ensures that the device shuts down when the input supply collapses. Figure 59 shows the
UVLO circuit response to various input voltage events. The diagram can be separated into the following parts:
•
•
•
Region A: The device does not start until the input reaches the UVLO rising threshold.
Region B: Normal operation, regulating device.
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation but the device remains enabled.
•
•
Region D: Normal operation, regulating device.
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls because of the load and active discharge circuit. The device is reenabled when the UVLO rising
threshold is reached by the input voltage and a normal start-up follows.
•
•
Region F: Normal operation followed by the input falling to the UVLO falling threshold.
Region G: The device is disabled when the input voltage falls below the UVLO falling threshold to 0 V. The
output falls because of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
Figure 59. Typical UVLO Operation
8.1.5 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
As a first-order approximation, power dissipation in the regulator depends on the input-to-output voltage
difference and load conditions. Use Equation 2 to approximate PD:
PD = (VIN – VOUT) × IOUT
(2)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A02 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device is through the thermal pad on the package. As such, the thermal
pad must be soldered to a copper pad area under the device. This pad area contains an array of plated vias that
conduct heat to any inner plane areas or to a bottom-side copper plane.
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Application Information (continued)
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to Equation 3, power dissipation and junction temperature are most often related by the junction-to-
ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the ambient
air (TA). Equation 4 rearranges Equation 3 for output current.
TJ = TA + (RθJA × PD)
(3)
(4)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the X2SON package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
8.1.5.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with Equation 5 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
where:
•
•
•
PD is the power dissipated as explained in Equation 2
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(5)
8.1.5.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is given in Figure 60 and can be
separated into the following parts:
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level. See the Dropout Operation section for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
–
The shape of the slope is given by Equation 4. The slope is nonlinear because the maximum rated
junction temperature of the LDO is controlled by the power dissipation across the LDO; thus when VIN
VOUT increases the output current must decrease.
–
•
The rated input voltage range governs both the minimum and maximum of VIN – VOUT
.
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Application Information (continued)
Figure 60 shows the recommended area of operation for this device on a JEDEC-standard high-K board with a
θJA as given in the Thermal Information table.
R
Output current limited by
dropout
Rated output
current
Output current limited by thermals
Limited by
minimum VIN
Limited by
maximum VIN
VIN œ VOUT (V)
Figure 60. Region Description of Continuous Operation Regime
8.2 Typical Application
IN
OUT
GND
CIN
COUT
Device
VBAT
Load
EN
Figure 61. Operation From a Battery Input Supply
Table 2. Design Parameters
8.2.1 Design Requirements
PARAMETER
DESIGN REQUIREMENT
1.8 V to 3.0 V (two 1.5-V batteries)
1.0 V, ±1%
Input voltage
Output voltage
Input current
200 mA, maximum
10-mA DC
Output load
Maximum ambient temperature
70°C
8.2.2 Detailed Design Procedure
For this design example, the 1.0-V, fixed-version TPS7A0210 is selected. A dual AA Alkaline battery was used,
thus a 1.0-µF input capacitor is recommended to minimize transient currents drawn from the battery. A 1.0-µF
output capacitor is also recommended for excellent load transient response. The dropout voltage (VDO) is kept
within the TPS7A02 dropout voltage specification for the 1.0-V output voltage option to keep the device in
regulation under all load and temperature conditions for this design. Use the recommend 1-µF input and output
capacitor because the input source has a high equivalent series resistor (ESR) of 600 mΩ (typ). The very small
ground current consumed by the regulator maintains a high current efficiency as compared to the load current
consumed by the system, as shown in Figure 62 which allows for long battery life. Equation 6 can be used to
calculate the current efficiency (Iη) of this system.
Iη(%) = IOUT / (IOUT + IQ) × 100
(6)
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8.2.3 Application Curve
102
100
98
96
94
92
90
88
86
84
TJ
-55°C
-40°C
0°C
25°C
85°C
125°C
140°C
100
0.001
0.01
0.1 1
Output Current (mA)
10
Curr
Figure 62. Current Efficiency vs IOUT and Temperature
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.5 V to 6.0 V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 0.5 V. TI highly recommends using a 1-µF
or greater input capacitor to reduce the impedance of the input supply, especially during transients.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute the heat.
Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Examples
VOUT
VIN
1
4
COUT
CIN
3
2
GND PLANE
Represents via used for
application specific connections
Figure 63. Layout Example for the DQN Package
VOUT
VIN
5
1
CIN
COUT
2
3
4
GND PLANE
Represents via used for
application specific connections
Figure 64. Layout Example for the DBV Package
IN
OUT
A2
A1
COUT
CIN
Via
B1
B2
EN
GND
Figure 65. Layout Example for the YCH Package
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 3. Device Nomenclature(1)(2)
PRODUCT
VOUT
XX(X) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TPS7A02 family actively discharge
the output when the device is disabled.
TPS7A02xx(x)Pyyyz
YYY is the package designator.
Z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPS7A0218PYCHR
PTPS7A0233PYCHR
ACTIVE
DSBGA
DSBGA
YCH
4
4
12000
12000
Non-RoHS &
Non-Green
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
ACTIVE
YCH
Non-RoHS &
Non-Green
Call TI
TPS7A0210PDQNR
TPS7A0212PDBVR
TPS7A0215PDBVR
TPS7A0215PDQNR
TPS7A02175PYCHR
TPS7A02185PDQNR
TPS7A0218PDBVR
TPS7A0218PDQNR
TPS7A0218PYCHR
TPS7A0220PDBVR
TPS7A0220PDQNR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2SON
SOT-23
SOT-23
X2SON
DSBGA
X2SON
SOT-23
X2SON
DSBGA
SOT-23
X2SON
DQN
DBV
DBV
DQN
YCH
DQN
DBV
DQN
YCH
DBV
DQN
4
5
5
4
4
4
5
4
4
5
4
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
GH
21GF
21KF
F3
3000 RoHS & Green
3000 RoHS & Green
NIPDAU | SN
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
12000 RoHS & Green SNAGCU Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
S
HO
21LF
F4
12000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
B
NIPDAU | SN
22MT
F5
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
TPS7A0222DQNR
TPS7A0222PDBVR
PREVIEW
ACTIVE
X2SON
SOT-23
DQN
DBV
4
5
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
IN
NIPDAU | SN
21HF
TPS7A0222PDQNR
TPS7A0223PDBVR
TPS7A0223PDQNR
TPS7A0225PDBVR
TPS7A0225PDQNR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2SON
SOT-23
X2SON
SOT-23
X2SON
DQN
DBV
DQN
DBV
DQN
4
5
4
5
4
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
GI
21IF
F6
21DF
F7
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A0228DBVR
TPS7A0228DQNR
TPS7A0228PDBVR
PREVIEW
PREVIEW
ACTIVE
SOT-23
X2SON
SOT-23
DBV
DQN
DBV
5
4
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
29PT
IE
NIPDAU
NIPDAU | SN
21EF
TPS7A0228PDQNR
TPS7A0230PDBVR
TPS7A0230PDQNR
TPS7A0230PYCHR
TPS7A0231PDQNR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
X2SON
SOT-23
X2SON
DSBGA
X2SON
DQN
DBV
DQN
YCH
DQN
4
5
4
4
4
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
12000 RoHS & Green SNAGCU Level-1-260C-UNLIM
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F8
21MF
F9
F
GJ
TPS7A0233DBVR
TPS7A0233DQNR
TPS7A0233PDBVR
PREVIEW
PREVIEW
ACTIVE
SOT-23
X2SON
SOT-23
DBV
DQN
DBV
5
4
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
29QT
IF
NIPDAU
NIPDAU | SN
21FF
TPS7A0233PDQNR
ACTIVE
X2SON
DQN
4
3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM
-40 to 125
FA
G
TPS7A0233PYCHR
TPS7A0236PDBVR
PREVIEW
ACTIVE
DSBGA
SOT-23
YCH
DBV
4
5
12000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
NIPDAU | SN
(21FF, 21JF)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jun-2021
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A0210PDQNR
TPS7A0210PDQNR
TPS7A0212PDBVR
TPS7A0215PDBVR
TPS7A0215PDQNR
TPS7A0215PDQNR
TPS7A02175PYCHR
TPS7A02185PDQNR
TPS7A02185PDQNR
TPS7A0218PDBVR
TPS7A0218PDQNR
TPS7A0218PDQNR
TPS7A0218PYCHR
TPS7A0220PDBVR
TPS7A0220PDQNR
TPS7A0220PDQNR
TPS7A0222PDBVR
TPS7A0222PDQNR
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
DSBGA
X2SON
X2SON
SOT-23
X2SON
X2SON
DSBGA
SOT-23
X2SON
X2SON
SOT-23
X2SON
DQN
DQN
DBV
DBV
DQN
DQN
YCH
DQN
DQN
DBV
DQN
DQN
YCH
DBV
DQN
DQN
DBV
DQN
4
4
5
5
4
4
4
4
4
5
4
4
4
5
4
4
5
4
3000
3000
3000
3000
3000
3000
12000
3000
3000
3000
3000
3000
12000
3000
3000
3000
3000
3000
178.0
180.0
178.0
178.0
178.0
180.0
180.0
180.0
178.0
178.0
178.0
180.0
180.0
178.0
178.0
180.0
178.0
178.0
8.4
9.5
9.0
9.0
8.4
9.5
8.4
9.5
8.4
9.0
8.4
9.5
8.4
9.0
8.4
9.5
9.0
8.4
1.13
1.16
3.3
1.13
1.16
3.2
0.53
0.5
4.0
4.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q3
Q3
Q2
Q2
Q1
Q2
Q2
Q3
Q2
Q2
Q1
Q3
Q2
Q2
Q3
Q2
1.4
3.3
3.2
1.4
1.13
1.16
0.72
1.16
1.13
3.3
1.13
1.16
0.72
1.16
1.13
3.2
0.53
0.5
0.42
0.5
0.53
1.4
1.13
1.16
0.72
3.3
1.13
1.16
0.72
3.2
0.53
0.5
0.42
1.4
1.13
1.16
3.3
1.13
1.16
3.2
0.53
0.5
1.4
1.13
1.13
0.53
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A0222PDQNR
TPS7A0223PDBVR
TPS7A0223PDQNR
TPS7A0223PDQNR
TPS7A0225PDBVR
TPS7A0225PDQNR
TPS7A0225PDQNR
TPS7A0228PDBVR
TPS7A0228PDQNR
TPS7A0228PDQNR
TPS7A0230PDBVR
TPS7A0230PDQNR
TPS7A0230PDQNR
TPS7A0230PYCHR
TPS7A0231PDQNR
TPS7A0231PDQNR
TPS7A0233PDBVR
TPS7A0233PDQNR
TPS7A0233PDQNR
TPS7A0236PDBVR
X2SON
SOT-23
X2SON
X2SON
SOT-23
X2SON
X2SON
SOT-23
X2SON
X2SON
SOT-23
X2SON
X2SON
DSBGA
X2SON
X2SON
SOT-23
X2SON
X2SON
SOT-23
DQN
DBV
DQN
DQN
DBV
DQN
DQN
DBV
DQN
DQN
DBV
DQN
DQN
YCH
DQN
DQN
DBV
DQN
DQN
DBV
4
5
4
4
5
4
4
5
4
4
5
4
4
4
4
4
5
4
4
5
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
12000
3000
3000
3000
3000
3000
3000
180.0
178.0
178.0
180.0
178.0
180.0
178.0
178.0
178.0
180.0
178.0
178.0
180.0
180.0
178.0
180.0
178.0
180.0
178.0
178.0
9.5
9.0
8.4
9.5
9.0
9.5
8.4
9.0
8.4
9.5
9.0
8.4
9.5
8.4
8.4
9.5
9.0
9.5
8.4
9.0
1.16
3.3
1.16
3.2
0.5
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q3
Q2
Q2
Q3
Q2
Q2
Q3
Q2
Q2
Q3
Q2
Q2
Q1
Q2
Q2
Q3
Q2
Q2
Q3
1.13
1.16
3.3
1.13
1.16
3.2
0.53
0.5
1.4
1.16
1.13
3.3
1.16
1.13
3.2
0.5
0.53
1.4
1.13
1.16
3.3
1.13
1.16
3.2
0.53
0.5
1.4
1.13
1.16
0.72
1.13
1.16
3.3
1.13
1.16
0.72
1.13
1.16
3.2
0.53
0.5
0.42
0.53
0.5
1.4
1.16
1.13
3.3
1.16
1.13
3.2
0.5
0.53
1.4
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Jun-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A0210PDQNR
TPS7A0210PDQNR
TPS7A0212PDBVR
TPS7A0215PDBVR
TPS7A0215PDQNR
TPS7A0215PDQNR
TPS7A02175PYCHR
TPS7A02185PDQNR
TPS7A02185PDQNR
TPS7A0218PDBVR
TPS7A0218PDQNR
TPS7A0218PDQNR
TPS7A0218PYCHR
TPS7A0220PDBVR
TPS7A0220PDQNR
TPS7A0220PDQNR
TPS7A0222PDBVR
TPS7A0222PDQNR
TPS7A0222PDQNR
TPS7A0223PDBVR
TPS7A0223PDQNR
TPS7A0223PDQNR
TPS7A0225PDBVR
TPS7A0225PDQNR
TPS7A0225PDQNR
TPS7A0228PDBVR
TPS7A0228PDQNR
TPS7A0228PDQNR
TPS7A0230PDBVR
TPS7A0230PDQNR
TPS7A0230PDQNR
TPS7A0230PYCHR
TPS7A0231PDQNR
TPS7A0231PDQNR
TPS7A0233PDBVR
TPS7A0233PDQNR
TPS7A0233PDQNR
TPS7A0236PDBVR
X2SON
X2SON
SOT-23
SOT-23
X2SON
X2SON
DSBGA
X2SON
X2SON
SOT-23
X2SON
X2SON
DSBGA
SOT-23
X2SON
X2SON
SOT-23
X2SON
X2SON
SOT-23
X2SON
X2SON
SOT-23
X2SON
X2SON
SOT-23
X2SON
X2SON
SOT-23
X2SON
X2SON
DSBGA
X2SON
X2SON
SOT-23
X2SON
X2SON
SOT-23
DQN
DQN
DBV
DBV
DQN
DQN
YCH
DQN
DQN
DBV
DQN
DQN
YCH
DBV
DQN
DQN
DBV
DQN
DQN
DBV
DQN
DQN
DBV
DQN
DQN
DBV
DQN
DQN
DBV
DQN
DQN
YCH
DQN
DQN
DBV
DQN
DQN
DBV
4
4
5
5
4
4
4
4
4
5
4
4
4
5
4
4
5
4
4
5
4
4
5
4
4
5
4
4
5
4
4
4
4
4
5
4
4
5
3000
3000
3000
3000
3000
3000
12000
3000
3000
3000
3000
3000
12000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
3000
12000
3000
3000
3000
3000
3000
3000
205.0
184.0
180.0
180.0
205.0
184.0
182.0
184.0
205.0
180.0
205.0
184.0
182.0
180.0
205.0
184.0
180.0
205.0
184.0
180.0
205.0
184.0
180.0
184.0
205.0
180.0
205.0
184.0
180.0
205.0
184.0
182.0
205.0
184.0
180.0
184.0
205.0
180.0
200.0
184.0
180.0
180.0
200.0
184.0
182.0
184.0
200.0
180.0
200.0
184.0
182.0
180.0
200.0
184.0
180.0
200.0
184.0
180.0
200.0
184.0
180.0
184.0
200.0
180.0
200.0
184.0
180.0
200.0
184.0
182.0
200.0
184.0
180.0
184.0
200.0
180.0
33.0
19.0
18.0
18.0
33.0
19.0
20.0
19.0
33.0
18.0
33.0
19.0
20.0
18.0
33.0
19.0
18.0
33.0
19.0
18.0
33.0
19.0
18.0
19.0
33.0
18.0
33.0
19.0
18.0
33.0
19.0
20.0
33.0
19.0
18.0
19.0
33.0
18.0
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
2X 0.95
1.9
3.05
2.75
1.9
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
+0.12
-0.1
0.05
0.00
0.48
(0.05) TYP
NOTE 6
2
1
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
4
0.28
PIN 1 ID
(OPTIONAL)
NOTE 4
4X
0.15
(0.11)
0.3
0.2
0.1
C A B
0.05
C
0.30
0.15
3X
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
4X (0.36)
(0.03)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party
intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,
costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either
on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s
applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
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TPS7A0233PDBVR
具有使能功能的 200mA、毫微功耗 IQ (25nA)、低压降 (LDO) 稳压器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS7A0233PDQNR
具有使能功能的 200mA、毫微功耗 IQ (25nA)、低压降 (LDO) 稳压器 | DQN | 4 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS7A0233PYCHR
TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient ResponseWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS7A0236PDBVR
具有使能功能的 200mA、毫微功耗 IQ (25nA)、低压降 (LDO) 稳压器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TPS7A02_V06
TPS7A02 Nanopower IQ, 25-nA, 200-mA, Low-Dropout Voltage Regulator With Fast Transient ResponseWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
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