TPS7A0510PYKAR [TI]
具有使能功能的 200mA、超低 IQ、高精度、低压降稳压器 | YKA | 4 | -40 to 125;
| 型号： | TPS7A0510PYKAR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有使能功能的 200mA、超低 IQ、高精度、低压降稳压器 | YKA | 4 | -40 to 125 稳压器 |
| 文件： | 总55页 (文件大小：4431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TPS7A05
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
采用小型封装的 TPS7A05 1µA 超低 IQ 200mA
低压降稳压器
1 特性
3 说明
1
•
超低 IQ：1µA（典型值）、3µA（最大值）
GND：在 200mA 下为 6µA（典型值）
TPS7A05 是一款超小型低静态电流低压降稳压器
(LDO)，可提供 200mA 的电流以及出色的瞬态性能。
该器件的输出范围为 0.8V 至 3.3V，典型精度为 1%。
–
I
•
•
绝佳的瞬态响应
封装：
TPS7A05 具有超低 IQ (1µA)，消耗的静态电流极低，
从而能够在电池供电应用中延长电池 寿命提供了出色
的功能性与安全性。该器件可由可再充电的锂离子电
池、锂原电池化学物质（如 Li-SOCl2、Li-MnO2）以
及两到三节碱性电池供电。
–
–
–
–
1.0mm × 1.0mm X2SON (4)
0.65mm × 0.65mm DSBGA (4)
SOT-23 (5)
SOT-23 (3)
•
•
•
输入电压范围：1.4V 至 5.5V
输出精度：1% 典型值，3% 最大值
可提供固定输出电压：
TPS7A05 采用有源下拉电路，用于在器件处于禁用状
态时对输出进行快速放电。
–
0.8V 至 3.3V
非常低的压降：
200mA 时为 235mV（最大值）(3.3VOUT
TPS7A05 的完整额定工作温度范围为 TJ = -40°C 至
+125°C，采用标准的 X2SON (DQN)、SOT-23（DBV
和 DBZ）以及 DSBGA (YKA) 封装。
•
–
)
•
•
•
有源输出放电
折返电流限制
器件信息(1)
器件型号
封装
X2SON (4)
封装尺寸（标称值）
1.00mm x 1.00mm
0.65mm × 0.65mm
2.90mm × 1.60mm
2.90mm x 1.60mm
与 0.47µF 或更大的电容器一起工作时保持稳定
DSBGA (4)
SOT-23 (5)
SOT-23 (3)
2 应用
TPS7A05
•
•
•
•
•
•
•
可穿戴电子产品
超极本、平板电脑、电子阅读器
始终通电型电源
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。
机顶盒
游戏控制器、遥控器、玩具、无人机
无线手持终端和智能手机
便携式和电池供电类设备
典型应用电路
接地电流与输出电流间的关系
7
IN
OUT
6
5
4
3
2
1
0
TPS7A05
COUT
CIN
EN
GND
ON
OFF
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
D043
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBVS254
TPS7A05
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 21
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 27
Power Supply Recommendations...................... 27
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 4
Specifications......................................................... 6
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics........................................... 7
6.6 Switching Characteristics.......................................... 9
6.7 Typical Characteristics............................................ 10
Detailed Description ............................................ 18
7.1 Overview ................................................................. 18
7.2 Functional Block Diagram ....................................... 18
7.3 Feature Description................................................. 19
8
9
10 Layout................................................................... 28
10.1 Layout Guidelines ................................................. 28
10.2 Layout Example .................................................... 28
11 器件和文档支持 ..................................................... 29
11.1 器件支持................................................................ 29
11.2 文档支持................................................................ 29
11.3 接收文档更新通知 ................................................. 29
11.4 社区资源................................................................ 29
11.5 商标....................................................................... 29
11.6 静电放电警告......................................................... 29
11.7 Glossary................................................................ 29
12 机械、封装和可订购信息....................................... 30
7
4 修订历史记录
Changes from Revision C (April 2019) to Revision D
Page
•
•
•
•
已更改 将 DBZ 封装从 APL 更改为生产数据 .......................................................................................................................... 1
Added DBZ package to Load Regulation parameter in Electrical Characteristics table ....................................................... 7
Added DBZ package to Dropout voltage parameter in Electrical Characteristics table ......................................................... 8
已添加 condition statement to IQ vs VIN and Temperature figure ........................................................................................ 10
Changes from Revision B (August 2018) to Revision C
Page
•
已添加 向文档添加了 DBZ 封装（作为 APL 发行版）............................................................................................................ 1
Changes from Revision A (May 2018) to Revision B
Page
•
•
•
•
•
•
•
•
•
•
•
•
•
已更改 在文档标题中将 1mm × 1mm 更改成了小型............................................................................................................... 1
已更改 将 YKA (DSBGA) 封装状态更改成了“生产数据” ......................................................................................................... 1
Added Accuracy for 1.825 V in Electrical Characteristics table ............................................................................................. 7
Changed Output current limit in Electrical Characteristics table ............................................................................................ 7
Added Output current limit for +85°C in Electrical Characteristics table................................................................................ 7
Changed Short-circuit current limit in Electrical Characteristics table.................................................................................... 7
Added Dropout voltage for 1.825 V in Electrical Characteristics table................................................................................... 8
已更改 y-axis scaling and added conditions for IOUT Transient 0 mA to 100 mA figure ....................................................... 10
已更改 y-axis scaling and added conditions for IOUT Transient 0 mA to 200 mA figure ...................................................... 11
已添加 IOUT Transient 0 mA to 50 mA figure to IOUT Transient 3 µA to 3 mA figure............................................................. 11
已添加 slew rate condition to VIN Transient figures (IOUT = 100 mA and IOUT = 200 mA)..................................................... 12
已添加 VIN Transient figures (IOUT = 150 mA and IOUT = 20 mA).......................................................................................... 13
已添加 VIN condition to PSRR vs Frequency and IOUT figure (VOUT = 1.8 V)........................................................................ 16
2
版权 © 2018–2019, Texas Instruments Incorporated
TPS7A05
www.ti.com.cn
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
Changes from Original (February 2018) to Revision A
Page
•
已发布至生产 .......................................................................................................................................................................... 1
Copyright © 2018–2019, Texas Instruments Incorporated
3
TPS7A05
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
www.ti.com.cn
5 Pin Configuration and Functions
DQN Package
1-mm × 1-mm, 4-Pin X2SON
Top View
OUT
1
4
IN
Pad
GND
2
3
EN
Not to scale
DBV Package
5-Pin SOT-23
Top View
DBZ Package
3-Pin SOT-23
Top View
IN
GND
EN
1
2
3
5
OUT
GND
OUT
1
3
IN
4
NC
2
Not to scale
Not to scale
YKA Package
YKA Package
4-Pin DSBGA, 0.35-mm Pitch
Top View
4-Pin DSBGA, 0.35-mm Pitch
Bottom View
1
2
1
2
A
IN
OUT
B
EN
GND
B
EN
GND
A
IN
OUT
Not to scale
Not to scale
4
Copyright © 2018–2019, Texas Instruments Incorporated
TPS7A05
www.ti.com.cn
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
Pin Functions
PIN
DBV
NAME
DQN
DBZ
YKA
I/O
DESCRIPTION
Input pin. For best transient response and to minimize input
impedance, use the recommended value or larger ceramic
Input capacitor from IN to ground as listed in the Recommended
Operating Conditions table. Place the input capacitor as close to
input of the device as possible.
IN
4
1
3
A1
Enable pin. Driving this pin to logic high enables the device;
driving this pin to logic low disables the device. If enable
functionality is not required, this pin must be connected to IN.
EN
3
2
3
2
—
1
B1
B2
Input
VEN must not exceed VIN
.
GND
—
Ground pin. This pin must be connected to ground on the board.
Regulated output pin. A capacitor is required from OUT to
ground for stability. For best transient response, use the nominal
recommended value or larger ceramic capacitor from OUT to
ground. Follow the recommended capacitor value as listed in the
Recommended Operating Conditions table. Place the output
capacitor as close to output of the device as possible.
OUT
1
5
2
A2
Output
No connect pin. This pin is not internally connected. Connect to
ground or leave floating.
NC
—
4
—
—
—
—
—
—
Connect the thermal pad to a large-area ground plane. This pad
is not an electrical connection to the device ground.
Thermal pad
Pad
—
Copyright © 2018–2019, Texas Instruments Incorporated
5
TPS7A05
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
MAX
UNIT
IN
6.0
VIN + 0.3
VIN + 0.3 or 3.6(3)
Voltage(2)
EN
V
OUT
Current
Maximum output current
Operating junction temperature, TJ
Storage temperature, Tstg
Internally limited
A
–40
–65
125
150
Temperature
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages with respect to GND.
(3) VIN + 0.3 V or 3.6 V (whichever is smaller)
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
1.4
0
NOM
MAX
5.5
UNIT
VIN
Input supply voltage
Enable supply voltage
Nominal output voltage range
Output current(1)
V
V
VEN
VOUT
IOUT
CIN
VIN
0.8
0
3.3
V
200
mA
µF
µF
°C
Input capacitor
1
1
COUT
TJ
Output capacitor
0.47
–40
22
Operating junction temperature
125
(1) Output current of 10 µA minimum required to meet output voltage accuracy specification.
6.4 Thermal Information
TPS7A05
DBZ
(SOT-23)
DBV
(SOT-23)
DQN
YKA
THERMAL METRIC(1)
UNIT
(X2SON)
4 PINS
144.1
137.9
83.5
(DSBGA)
4 PINS
198.0
2.1
3 PINS
267.3
103.5
98.0
9.2
5 PINS
185.6
104.3
54.5
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
66.9
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
31.0
5.3
0.9
YJB
97.4
n/a
54.5
83.8
76.0
RθJC(bot)
n/a
71.8
n/a
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6
Copyright © 2018–2019, Texas Instruments Incorporated
TPS7A05
www.ti.com.cn
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
6.5 Electrical Characteristics
specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF,
and COUT = 1 µF (unless otherwise noted); typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
OUT ≥ 1.0 V, TJ = 25°C
VOUT < 1.0 V, TJ = 25°C
MIN
–1%
–10
TYP
MAX
1%
10
UNIT
V
Nominal accuracy(1)
mV
V
OUT ≥ 1.0 V, TJ = –40°C to +85°C
OUT ≥ 1.0 V
–2%
–3%
–20
2%
3%
20
V
VOUT < 1.0 V, TJ = –40°C to +85°C
VOUT < 1.0 V
Accuracy over
temperature(1)
mV
–30
30
VOUT = 1.825 V, TJ = +10℃ to +45℃,
IOUT = 100 µA
–0.9%
0.9%
16.5
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V(2)
,
5
TJ = –40°C to +85°C
ΔVOUT(ΔVIN)
Line regulation
mV
mV
VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V(2)
18
43
100 μA ≤ IOUT ≤ 200 mA,
VIN = VOUT(nom) + VDO(max) + 0.1 V,
TJ = –40°C to +85°C
DBV, DQN, YKA
DBZ
20
27
50
ΔVOUT(ΔIOUT) Load regulation(3)
DBV, DQN, YKA
DBZ
55
62
100 μA ≤ IOUT ≤ 200 mA,
VIN = VOUT(nom) + VDO(max) + 0.1 V
TJ = 25°C, IOUT = 1 µA
IOUT = 1 µA, TJ = –40°C to +85°C
IOUT = 1 µA
0.6
1
1.3
2
IGND
Ground current
µA
3
ISHDN
ICL
Shutdown current
Output current limit
VEN = 0.4 V, 1.4 V ≤ VIN ≤ 5.5 V, TJ = 25°C
100
450
300
700
nA
VOUT = 90% × VOUT(nom), VIN = VOUT(nom) + VDO(max) + 0.5 V
210
250
mA
VOUT = 90% × VOUT(nom)
,
ICL
Output current limit
VIN = VOUT(nom) + VDO(max) + 0.5 V,
TJ = 0°C to +85°C
450
65
700
150
mA
mA
Short-circuit current
limit
ISC
VOUT = 0 V
(1)
IOUT ≥ 10 µA required to meet accuracy specifications.
(2) VIN = 1.4 V for VOUT ≤ 0.9 V.
(3) Load Regulation is normalized to the output voltage at IOUT = 1 mA.
Copyright © 2018–2019, Texas Instruments Incorporated
7
TPS7A05
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
www.ti.com.cn
Electrical Characteristics (continued)
specified at TJ = –40°C to +125°C, VIN = VOUT(nom) + 0.5 V or 1.4 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN = 1 µF,
and COUT = 1 µF (unless otherwise noted); typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
0.8 V ≤ VOUT < 1.0 V
MIN
TYP
MAX
915
758
609
469
341
275
212
1004
837
679
525
382
308
235
351
285
222
392
318
245
UNIT
1.0 V ≤ VOUT < 1.2 V
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 1.8 V
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
VOUT = 3.3 V
IOUT = 200 mA,
TJ = –40°C to +85°C
0.8 V ≤ VOUT < 1.0 V
1.0 V ≤ VOUT < 1.2 V
1.2 V ≤ VOUT < 1.5 V
1.5 V ≤ VOUT < 1.8 V
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
VOUT = 3.3 V
IOUT = 200 mA
VDO
Dropout voltage(4)
mV
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
VOUT = 3.3 V
IOUT = 200 mA,
TJ = –40°C to +85°C,
DBZ Package
1.8 V ≤ VOUT < 2.5 V
2.5 V ≤ VOUT < 3.3 V
VOUT = 3.3 V
IOUT = 200 mA,
DBZ Package
IOUT = 100 µA,
TJ = +10℃ to +45℃
VOUT = 1.825 V
20
f = 1 kHz, IOUT = 30 mA
f = 500 kHz, IOUT = 30 mA
f = 1 MHz, IOUT = 30 mA
40
30
40
Power-supply
rejection ratio
PSRR
VN
dB
BW = 10 Hz to 100 kHz, VOUT = 1.2 V,
IOUT = 30 mA
Output voltage noise
180
µVRMS
VUVLO
UVLO threshold
UVLO hysteresis
UVLO threshold
VIN rising
VIN falling
VIN falling
1.21
1.3
40
1.37
1.33
V
mV
V
VUVLO(HYST)
VUVLO
1.17
0.9
EN pin logic high
voltage
VEN(HI)
VEN(LO)
V
V
EN pin logic low
voltage
0.4
IEN
EN pin current
VEN = VIN = 5.5 V
10
120
160
140
nA
RPULLDOWN
Pulldown resistor
VIN = 3.3 V, P version only
Shutdown, temperature increasing
Reset, temperature decreasing
Ω
Thermal shutdown
temperature
Tsd
°C
(4) Dropout is measured by ramping VIN down until VOUT = VOUT(nom) – 5%.
8
Copyright © 2018–2019, Texas Instruments Incorporated
TPS7A05
www.ti.com.cn
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
6.6 Switching Characteristics
specified at TJ = –40 to +125°C, VIN = VOUT(nom) + VDO(max) + 0.5 V, IOUT = 10 mA, CIN = 1 µF, and COUT = 1 µF (unless
otherwise noted); typical values are at TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
From EN assertion to VOUT = 95% × VOUT(nom) , VOUT
1.8 V
=
tSTR
Start-up time(1)
1.5
2.8
ms
(1) See the Special Considerations When Ramping Down IN and Enable section for details on minimum ramp down rates to ensure
specified start-up time.
版权 © 2018–2019, Texas Instruments Incorporated
9
TPS7A05
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
www.ti.com.cn
6.7 Typical Characteristics
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN
1 µF, and COUT = 1 µF (unless otherwise noted)
=
2.25
2
550
500
450
400
350
300
250
200
150
100
50
TJ
25°C
85°C
TJ
0°C
-40°C
0°C
125°C
-40°C
25°C
85°C
1.75
1.5
1.25
1
0.75
0.5
1
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
5.5
1.5
2
2.5
3
Input Voltage (V)
3.5
4
4.5
5
5.5
D001
D002
VOUT = 3.3 V, includes IQ in dropout
VEN < 0.4 V
图 1. IQ vs VIN and Temperature
图 2. ISHDN vs VIN and Temperature
3500
3000
2500
2000
1500
1000
4
3
2
1
0
TJ
125°C
1.5
2
2.5
3
Input Voltage (V)
3.5
4
4.5
5
5.5
0
1
2
3
4
Output Current (mA)
5
6
7
8
9
10
D044
D042
VEN < 0.4 V
图 3. ISHDN vs VIN and Temperature
图 4. IGND vs IOUT up to 10 mA
7
6
5
4
3
2
1
0
300
550
500
450
400
350
300
250
200
150
100
50
VOUT
IOUT
200
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
0
-50
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
D043
D036
Output current slew rate = 3.3 mA/µs
图 5. IGND vs IOUT up to 200 mA
图 6. IOUT Transient 0 mA to 100 mA
10
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TPS7A05
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ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN
=
1 µF, and COUT = 1 µF (unless otherwise noted)
300
550
500
450
400
350
300
250
200
150
100
50
300
200
550
VOUT
IOUT
VOUT
IOUT
200
500
450
400
350
300
250
200
150
100
50
100
100
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
0
0
-50
-50
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D008
D045
Output current slew rate = 6.6 mA/µs
Output current slew rate = 50 mA/µs
图 7. IOUT Transient 0 mA to 200 mA
图 8. IOUT Transient 0 mA to 50 mA
300
200
550
600
400
550
500
450
400
350
300
250
200
150
100
50
VOUT
IOUT
VOUT
IOUT
500
450
400
350
300
250
200
150
100
50
100
200
0
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-200
-400
-600
-800
-1000
-1200
-1400
-1600
-1800
0
0
-50
-50
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D046
D047
Output current slew rate = 100 mA/µs
Output current slew rate = 150 mA/µs
图 9. IOUT Transient 0 mA to 100 mA
图 10. IOUT Transient 0 mA to 150 mA
600
400
550
500
450
400
350
300
250
200
150
100
50
300
200
550
500
450
400
350
300
250
200
150
100
50
VOUT
IOUT
VOUT
IOUT
200
100
0
0
-200
-400
-600
-800
-1000
-1200
-1400
-1600
-1800
-100
-200
-300
-400
-500
-600
-700
-800
-900
0
0
-50
-50
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
D048
D049
Output current slew rate = 200 mA/µs
Output current slew rate = 50 mA/µs
图 11. IOUT Transient 0 mA to 200 mA
图 12. IOUT Transient 1 mA to 50 mA
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11
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Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN
1 µF, and COUT = 1 µF (unless otherwise noted)
=
300
550
500
450
400
350
300
250
200
150
100
50
600
550
VOUT
IOUT
VOUT
IOUT
200
400
500
450
400
350
300
250
200
150
100
50
100
200
0
0
-100
-200
-300
-400
-500
-600
-700
-800
-900
-200
-400
-600
-800
-1000
-1200
-1400
-1600
-1800
0
0
-50
-50
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
DE0x5ce0
D051
Output current slew rate = 100 mA/µs
Output current slew rate = 150 mA/µs
图 13. IOUT Transient 1 mA to 100 mA
图 14. IOUT Transient 1 mA to 150 mA
600
400
550
500
450
400
350
300
250
200
150
100
50
30
20
70
60
50
40
30
20
10
0
VOUT
IOUT
VOUT
IOUT
200
0
10
-200
-400
-600
-800
-1000
-1200
-1400
-1600
-1800
0
-10
-20
-30
-40
-50
0
-50
-10
0
50 100 150 200 250 300 350 400 450 500
Time (µs)
0
20
40
60
80 100 120 140 160 180 200
Time (ms)
D052
D053
Output current slew rate = 200 mA/µs
CIN = COUT = 10 µF, output current slew rate = 3 mA/µs
图 15. IOUT Transient 1 mA to 200 mA
图 16. IOUT Transient 3 µA to 3 mA
300
200
100
0
2100
1800
1500
1200
900
600
300
0
300
2100
VOUT
VIN
VOUT
VIN
200
100
0
1800
1500
1200
900
600
300
0
-100
-200
-300
-400
-500
-100
-200
-300
-400
-500
-300
-300
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
D012
D011
IOUT = 100 mA, input voltage slew rate = 0.6 V/µs
IOUT = 200 mA, input voltage slew rate = 0.6 V/µs
图 17. VIN Transient
图 18. VIN Transient
12
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TPS7A05
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ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN
=
1 µF, and COUT = 1 µF (unless otherwise noted)
300
3500
3000
2500
2000
1500
1000
500
150
100
50
3500
3000
2500
2000
1500
1000
500
VOUT
VIN
VOUT
VIN
200
100
0
0
-100
-200
-300
-400
-500
-50
-100
-150
-200
-250
0
0
-500
-500
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
D054
D055
IOUT = 150 mA, input voltage slew rate = 0.1 V/µs
IOUT = 20 mA, input voltage slew rate = 0.01 V/µs
图 19. VIN Transient
图 20. VIN Transient
600
500
400
300
200
100
0
600
500
400
300
200
100
0
TJ
25°C
85°C
TJ
25°C
85°C
-40°C
0°C
125°C
-40°C
0°C
125°C
0
25
50
75
Load Current (mA)
100
125
150
175
200
0
25
50
75
Load Current (mA)
100
125
150
175
200
D013
D014
VOUT = 1.8 V
VOUT = 3.3 V
图 21. Dropout vs IOUT and Temperature
图 22. Dropout vs IOUT and Temperature
600
500
400
300
200
100
0
10
9
TJ
-40°C
0°C
25°C
85°C
125°C
TJ
25°C
85°C
-40°C
0°C
125°C
8
7
6
5
4
3
2
1
0
-1
1.6
1.8
2
2.2
Input Voltage (V)
2.4
2.6
2.8
3
3.2
1
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
5.5
D027
D009
VOUT = 0.8 V
图 23. Dropout vs VIN and Temperature
图 24. Line Regulation VIN and Temperature
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TPS7A05
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www.ti.com.cn
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN
1 µF, and COUT = 1 µF (unless otherwise noted)
=
1.2
14
12
10
8
TJ
25°C
85°C
TJ
25°C
85°C
-40°C
0°C
125°C
-40°C
0°C
125°C
1
0.8
0.6
0.4
0.2
0
6
4
2
0
-0.2
-2
1
1.5
2
2.5
3 3.5
Input Voltage (V)
4
4.5
5
5.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
D006
D004
VOUT = 0.8 V
VOUT = 1.8 V
图 25. Output Accuracy VIN and Temperature
图 26. Line Regulation VIN and Temperature
1
0.8
0.6
0.4
0.2
0
6
TJ
25°C
85°C
-40°C
0°C
125°C
0
-6
-12
-18
-24
-30
TJ
-40°C
0°C
25°C
85°C
125°C
-0.2
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
5.5
0
20
40
60
80 100 120 140 160 180 200
Output Current (mA)
D005
VOUT = 1.8 V
VOUT = 1.8 V
图 28. Load Regulation vs IOUT and Temperature
图 27. Output Accuracy VIN and Temperature
2.5
2
3
2.8
2.6
2.4
2.2
2
TJ
-40°C
0°C
25°C
85°C
1.8
1.6
1.4
1.2
1
1.5
1
0.8
0.6
0.4
0.2
0
VEN
VIN
VOUT
0.5
0
-0.2
0
50 100 150 200 250 300 350 400 450 500
Output Current (mA)
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
D003
D029
VOUT = 1.8 V
图 29. Foldback Current Limit vs IOUT and Temperature
VOUT = 0.8 V, IOUT = 1 mA
图 30. Startup With VEN = VIN
14
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TPS7A05
www.ti.com.cn
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN
=
1 µF, and COUT = 1 µF (unless otherwise noted)
3
2.8
2.6
2.4
2.2
2
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
VEN
VIN
VOUT
VEN
VIN
VOUT
-0.2
-0.2
0
0
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
D030
D031
VOUT = 0.8 V, IOUT = 30 mA
图 31. Startup With VEN = VIN
VOUT = 1.8 V, IOUT = 30 mA
图 32. Startup With VEN = VIN
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
VEN
VIN
VOUT
VEN
VIN
VOUT
-0.2
-0.2
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
D032
D033
VOUT = 0.8 V, IOUT = 1 mA
图 33. Startup With Separate VIN and VEN
VOUT = 0.8 V, IOUT = 30 mA
图 34. Startup With Separate VIN and VEN
3
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
60
55
50
45
40
35
30
25
20
15
10
5
VIN
1.4 V
1.5 V
1.6 V
1.8 V
VEN
VIN
VOUT
-0.2
0.5
1
1.5
2
2.5
Time (ms)
3
3.5
4
4.5
5
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
D034
D022
VOUT = 1.8 V, IOUT = 30 mA
图 35. Startup With Separate VIN and VEN
VOUT = 0.8 V, IOUT = 200 mA, COUT = 1 µF, CIN = 0 µF
图 36. PSRR vs Frequency and VIN
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Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN
1 µF, and COUT = 1 µF (unless otherwise noted)
=
55
50
45
40
35
30
25
20
15
10
5
60
50
40
30
20
10
0
VIN
2.2 V
2.3 V
2.4 V
2.5 V
VIN
3.6 V
3.8 V
4.0 V
2.8 V
3.3 V
3.6 V
4.2 V
4.6 V
0
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D016
D020
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF, CIN = 0 µF
VOUT = 3.3 V, IOUT = 200 mA, COUT = 1 µF, CIN = 0 µF
图 37. PSRR vs Frequency and VIN
图 38. PSRR vs Frequency and VIN
70
65
60
55
50
45
40
35
30
70
65
60
55
50
45
40
35
30
25
20
15
10
5
IOUT
0 mA
25
10 mA
50 mA
100 mA
150 mA
200 mA
IOUT
0 mA
10 mA
50 mA
100 mA
20
15
10
5
0
0
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D021
D015
VOUT = 0.8 V, VIN = 1.4 V, COUT = 1 µF, CIN = 0 µF
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF, CIN = 0 µF
图 39. PSRR vs Frequency and IOUT
图 40. PSRR vs Frequency and IOUT
70
65
60
55
50
45
40
35
30
25
20
15
10
5
20
10
5
2
1
0.5
IOUT
0 mA
0.2
0.1
10 mA
50 mA
100 mA
150 mA
200 mA
0.05
VIN
2.2 V
2.8 V
3.3 V
5.5 V
0.02
0.01
0
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D019
D025
VOUT = 3.3 V, VIN = 3.8 V, COUT = 1 µF, CIN = 0 µF
VOUT = 1.8 V, IOUT = 200 mA, COUT = 1 µF
图 41. PSRR vs Frequency and IOUT
图 42. Output Noise vs Frequency and VIN
16
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TPS7A05
www.ti.com.cn
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
Typical Characteristics (接下页)
at operating temperature TJ = 25°C, VIN = VOUT(NOM) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, CIN
=
1 µF, and COUT = 1 µF (unless otherwise noted)
20
IOUT
10
5
10
50 mA
100 mA
150 mA
200 mA
5
2
1
2
1
0.5
0.5
0.2
0.1
0.2
0.1
0.05
0.05
COUT
1.0 µF
10 µF
0.02
0.01
0.02
0.01
0.005
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
D024
D026
VOUT = 1.8 V, VIN = 2.8 V, COUT = 1 µF
VOUT = 1.8 V, VIN = 2.8 V, IOUT = 200 mA
图 43. Output Noise vs Frequency and IOUT
图 44. Output Noise vs Frequency and COUT
20
10
5
1.3
1.28
1.26
1.24
1.22
VUVLO, Rising
VUVLO, Falling
2
1
0.5
0.2
0.1
0.05
VOUT
0.8 V
1.8 V
3.3 V
0.02
0.01
0.005
10
100
1k
10k 100k
Frequency (Hz)
1M
10M
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D028
D035
VIN = VOUT + 1 V, IOUT = 200 mA, COUT = 1 µF
图 45. Output Noise vs Frequency and VOUT
图 46. UVLO VIN Rising and Falling Thresholds vs
Temperature
0.68
0.66
0.64
0.62
0.6
VEN(HI)
VEN(LO)
0.58
0.56
0.54
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D037
图 47. Enable High and Low Thresholds vs
Temperature
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www.ti.com.cn
7 Detailed Description
7.1 Overview
The TPS7A05 is a ultra-low IQ linear voltage regulator that is optimized for excellent transient performance.
These characteristics make the TPS7A05 ideal for most battery-powered applications.
This low-dropout regulator (LDO) offers foldback current limit, shutdown, thermal protection, and optional active
discharge.
7.2 Functional Block Diagram
Current
Limit
IN
OUT
1.2-V
Bandgap
+
Active Discharge
P-Version Only
œ
œ
Error
Amp
+
UVLO
Internal
Controller
Thermal
Shutdown
EN
GND
18
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TPS7A05
www.ti.com.cn
ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
7.3 Feature Description
7.3.1 Excellent Transient Response
The device includes several innovative circuits to ensure excellent transient response. Dynamic biasing
increases the IQ for a short duration during transients to extend the closed-loop bandwidth and improve the
device response time during transients.
Adaptive biasing increases the IQ as the dc load current increases, extending the bandwidth of the control loop.
The device response time across the output voltage range is constant because of the use of a buffered reference
topology, which keeps the control loop in unity gain at any output voltage.
These features give the device a wide loop bandwidth during transients that ensure excellent transient response
while maintaining the device low IQ in steady-state conditions; see the Application and Implementation section for
more details.
7.3.2 Active Discharge
Devices with this option have an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the
device is disabled to actively discharge the output voltage. The active discharge circuit is activated when the
device is disabled, in undervoltage lockout (UVLO), or in thermal shutdown.
The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in
parallel with the 120-Ω pulldown resistor. 公式 1 calculates the time constant:
120 · RL
t =
· COUT
120 + RL
(1)
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply has collapsed because reverse current can flow from the output to the input. This reverse current flow can
cause damage to the device. Limit reverse current to no more than 5% of the device-rated current.
7.3.3 Low IQ in Dropout
In most LDOs the IQ significantly increases when the device is placed into dropout, which is especially true for
low IQ LDOs with adaptive biasing. The TPS7A05 detects when operating in dropout and disables the adaptive
biasing, minimizing the IQ increase.
7.3.4 Undervoltage Lockout (UVLO)
The undervoltage lockout (UVLO) circuit monitors the input voltage (VIN) to prevent the device from turning on
before VIN rises above the lockout voltage. The UVLO circuit also disables the output of the device when VIN falls
below the lockout voltage. If the device includes the optional active discharge, the output is connected to ground
with a 120-Ω pulldown resistor when VIN is below the lockout voltage; see the Application and Implementation
section for more details.
7.3.5 Enable
The enable pin for the device is active high. The output of the device is turned on when the enable pin voltage is
greater than the EN pin logic high voltage, and the output of the device is turned off when the enable pin voltage
is less than the EN pin logic low voltage. A voltage less than the EN pin logic low voltage on the enable pin
disables all internal circuits.
At the next turn-on, any voltage on the EN pin below the logic low voltage ensures a normal start-up waveform
with start-up ramp rate control, provided there is enough time to discharge the output capacitance. If shutdown
capability is not required, connect EN to IN. VEN must not exceed VIN.
7.3.6 Internal Foldback Current Limit
The internal foldback current-limit circuit is used to protect the LDO against high-load current faults or shorting
events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power
dissipation during short-circuit events while still allowing for the device to operate at its rated output current; see
图 29.
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www.ti.com.cn
Feature Description (接下页)
A foldback example for this device is that when VOUT is 90% of VOUT(nom) the current limit is ICL(typical); however,
if VOUT is forced to 0 V the current limit is ISC (typical).
In many LDOs the foldback current limit can prevent start-up into a constant-current load or a negatively-biased
output. The foldback mechanism for this device goes into a brick-wall current limit when VOUT > 500 mV (typ),
thus limiting current to ICL(typical) and, when VOUT is approximately 0 V, current is limited to ISC (typical) to
ensure normal start-up into a variety of loads.
The foldback current limit is disengaged when IOUT < 1 mA (typical) to reduce IQ. As such, the current-limit loop
takes longer to respond to a current-limit event when IOUT < 1 mA (typ).
Thermal shutdown can activate during a current-limit event because of the high power dissipation typically found
in these conditions. To ensure proper operation of the current limit, minimize the inductances to the input and
load. Continuous operation in current limit is not recommended.
7.3.7 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when thermal junction
temperature (TJ) of the main pass-FET rises to Tsd(Shutdown) (typical). Thermal shutdown hysteresis assures that
the LDO resets again (turns on) when the temperature falls to Tsd(Reset) (typical).
The thermal time-constant of the semiconductor die is fairly short, and thus the device may cycle on and off
when thermal shutdown is reached until power dissipation is reduced.
For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the
device to exceed its operational specifications. Although the internal protection circuitry of the device is designed
to protect against thermal overload conditions, this circuitry is not intended to replace proper heat sinking.
Continuously running the device into thermal shutdown or above a junction temperature of 125°C reduces long-
term reliability.
A fast start-up when TJ > Tsd(Reset) (typical, outside of the specified operating range) causes the device thermal
shutdown to assert at Tsd(Reset) and prevents the device from turning on until the junction temperature is reduced
below Tsd(Shutdown)
.
20
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ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
7.4 Device Functional Modes
The device has several modes of operation,:
•
•
•
Normal operation: The device regulates to the nominal output voltage
Dropout operation: The pass element operates as a resistor and the output voltage is set as VIN – VDO
Shutdown: The output of the device is disabled and the discharge circuit is activated
表 1 shows the conditions that lead to the different modes of operation. See the Electrical Characteristics table
for parameter values.
表 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VEN
IOUT
TJ
Normal mode
Dropout mode
VIN > VOUT(nom) + VDO and VIN > VIN(min)
VIN(min) < VIN < VOUT(nom) + VDO
VEN > VEN(HI)
VEN > VEN(HI)
IOUT < IOUT(max)
IOUT < IOUT(max)
TJ < Tsd(Shutdown)
TJ < Tsd(Shutdown)
Disabled mode
(any true condition
disables the device)
VIN < VUVLO
VEN < VEN(LO)
—
TJ > Tsd(Shutdown)
7.4.1 Normal Mode
The device regulates the output to the nominal output voltage when all normal mode conditions in 表 1 are met.
7.4.2 Dropout Mode
The device is not in regulation, and the output voltage tracks the input voltage minus the voltage drop across the
pass transistor of the device. In this mode, the PSRR, noise, and transient performance of the device are
significantly degraded.
7.4.3 Disable Mode
In this mode, the pass element is turned off, the internal circuits are shut down, and the output voltage is actively
discharged to ground by an internal resistor.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input
and output. Multilayer ceramic capacitors have become the industry standard for these types of applications and
are recommended, but must be used with good judgment. Ceramic capacitors that employ X7R-, X5R-, and
COG-rated dielectric materials provide relatively good capacitive stability across temperature, whereas the use of
Y5V-rated capacitors is discouraged because of large variations in capacitance.
Regardless of the ceramic capacitor type selected, the effective capacitance varies with operating voltage and
temperature. As a rule of thumb, assume effective capacitance to decrease by as much as 50%. The input and
output capacitors recommended in the Recommended Operating Conditions table account for an effective
capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
Although an input capacitor is not required for stability, good analog design practice is to connect a capacitor
from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple,
and PSRR. An input capacitor is recommended if the source impedance is more than 0.5 Ω. A higher value
capacitor may be necessary if large, fast rise-time load or line transients are anticipated or if the device is located
several inches from the input power source.
Dynamic performance of the device is improved with the use of an output capacitor. Use an output capacitor
within the range specified in the Recommended Operating Conditions table for stability.
8.1.3 Special Considerations When Ramping Down VIN and Enable
Care must be taken when ramping down voltage on the IN and EN pins to power-down the device when the
operating free-air temperature is less than 15°C. The minimum ramp-down time for the IN pin is 10 ms. The
minimum ramp-down time for the EN pin is 100 µs. Ramping at faster rates can cause the regulator to exhibit
undesired startup behavior on the next power-on.
If VIN is ramped down faster than 10 ms, the next startup may exhibit a partial startup, shutoff, followed by a
normal soft-start startup. 图 48 shows this response.
4
VEN
VIN
3.5
VOUT
3
2.5
2
1.5
1
0.5
0
-0.5
-1
0
1
2
3
4
5
Time (ms)
6
7
8
9
10
D040
图 48. Partial Startup, Shutdown, Normal Startup With VEN = VIN
22
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Application Information (接下页)
If the EN pin is ramped down faster than 100 µs, the next startup may exhibit a delay time of up to 130 ms
before the output ramps up with a normal soft-start startup. 图 49 shows this delay.
4
3.5
3
2.5
2
1.5
1
0.5
VOUT
VIN
0
-0.5
-1
0
100 200 300 400 500 600 700 800 900 1000
Time (ms)
D041
图 49. Long Delay to Startup With VEN = VIN
Fast ramp downs of VIN and the EN pin charge internal high-impedance nodes in the device, which take
extended time to discharge below 15°C. To avoid these startup behaviors, follow the recommended minimum
ramp down times for VIN and the EN pin.
8.1.4 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current, whereby
output voltage regulation is maintained. See 图 6 for typical load transient response. There are two key
transitions during a load transient response: the transition from a light to a heavy load and the transition from a
heavy to a light load. The regions in 图 50 are broken down as described in this section. Regions A, E, and H are
where the output voltage is in steady-state.
During transitions from a light load to a heavy load, the:
•
Initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
•
Recovery from the dip results from the LDO increasing its sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load, the:
•
Initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge to
increase (region F)
•
Recovery from the rise results from the LDO decreasing its sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered and a higher
current discharge path is provided for the output capacitor.
tAt
tCt
tDt
tEt
tGt
tHt
B
F
图 50. Load Transient Waveform
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Application Information (接下页)
8.1.5 Dropout Voltage
The device uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass transistor is in the linear region of operation, and the input-to-output resistance of
the device is the drain-to-source resistance of the PMOS pass transistor. VDO scales with the output current and
changes with temperature because the PMOS pass transistor functions like a resistor in dropout mode. For a
graph of dropout voltage, see 图 22. As with any linear regulator, PSRR and the transient response degrade as
(VIN – VOUT) approaches dropout operation. See 图 23 for dropout performance.
8.1.5.1 Behavior When Transitioning From Dropout Into Regulation
Some applications may have transients that place the device into dropout, especially as this device can be
powered from a battery with high ESR. A typical application with these conditions is using a stack of two 1.55-V
coin-cell batteries with an ESR of 30 Ω to create a 2.5-V rail and experiencing a load transient from 1 µA to 25
mA. This load transient causes the input supply to drop 750 mV, placing the device into dropout.
The load transient saturates the output stage of the error amplifier when the pass element is driven fully on,
making the pass element function like a resistor from VIN to VOUT. The error amplifier response time to this load
transient is limited because the error amplifier must first recover from saturation and then place the pass element
back into active mode. During this time VOUT overshoots because the pass element is functioning as a resistor
from VIN to VOUT. This device uses a loop pulldown circuit to help mitigate the overshoot.
If operating under these conditions, applying a higher dc load or increasing the output capacitance reduces the
overshoot because these solutions provide a path to dissipate the excess charge.
8.1.5.2 Behavior of Output Resulting From Line Transient When in Dropout
The output deviation resulting from a line transient can be significantly higher when the device is operating in
dropout. As explained in the Dropout Voltage section, the response time of the error amplifier is limited when in
dropout, so the output deviation is larger and can exceed twice the regulated output voltage. Care must be taken
in applications where line transients are expected when the device is operating in dropout.
8.1.6 Undervoltage Lockout (UVLO) Operation
The UVLO circuit ensures that the device stays disabled before its input supply reaches the minimum operational
voltage range, and ensures that the device shuts down when the input supply collapses. See 图 46 for rising and
falling thresholds. 图 51 depicts the UVLO circuit response to various input voltage events. The diagram can be
separated into the following parts:
•
•
•
Region A: The device does not start until the input reaches the UVLO rising threshold
Region B: Normal operation, regulating device
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hystersis). The
output may fall out of regulation but the device is still enabled.
•
•
Region D: Normal operation, regulating device
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases and the
output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO
rising threshold is reached by the input voltage and a normal start-up follows.
•
•
Region F: Normal operation followed by the input falling to the UVLO falling threshold
Region G: The device is disabled as the input voltage falls below the UVLO falling threshold to 0 V. The
output falls as a result of the load and active discharge circuit.
24
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Application Information (接下页)
UVLO Rising Threshold
UVLO Hysteresis
VIN
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
图 51. Typical UVLO Operation
8.1.7 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
公式 2 calculates the maximum allowable power dissipation for the device in a given package:
PD-MAX = ((TJ – TA) / RθJA
)
(2)
公式 3 represents the actual power being dissipated in the device:
PD = (VIN - VOUT) × IOUT
(3)
An important note is that power dissipation can be minimized, and thus greater efficiency achieved, by proper
selection of the system voltage rails. Proper selection allows the minimum input-to-output voltage differential to
be obtained. The low dropout of the TPS7A05 allows for maximum efficiency across a wide range of output
voltages.
The main heat conduction path for the device depends on the ambient temperature and the thermal resistance
across the various interfaces between the die junction and ambient air.
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to 公式 4, maximum power dissipation and junction temperature are most often related by the junction-
to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the
ambient air (TA). The equation is rearranged in 公式 5 for output current.
TJ = TA + (RθJA × PD)
(4)
(5)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance. For a well-
designed thermal layout, RθJA is actually the sum of the DQN package junction-to-case (bottom) thermal
resistance (RθJC(bot)) plus the thermal resistance contribution by the PCB copper.
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Application Information (接下页)
8.1.7.1 Estimating Junction Temperature
The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures
of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with 公式 6 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
where:
•
•
•
PD is the power dissipated as explained in 公式 3
TT is the temperature at the center-top of the device package, and
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(6)
8.1.7.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is shown in 图 52 and can be
separated into the following regions:
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level; see the Dropout Voltage section for more details.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
–
公式 5 provides the shape of the slope. The slope is nonlinear because the maximum rated junction
temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT
increases the output current must decrease.
•
The rated input voltage range governs both the minimum and maximum of VIN – VOUT
.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Minimum VIN
Limited by
Maximum VIN
VIN œ VOUT (V)
图 52. Region Description for Continuous Operation
26
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8.2 Typical Application
IN
OUT
CIN
COUT
TPS7A05
VBAT
Load
GND
EN
图 53. Operation From the Battery Input Supply
8.2.1 Design Requirements
表 2 summarizes the design requirements for 图 53.
表 2. Design Parameters
PARAMETER
Input voltage
Output voltage
Output load
DESIGN REQUIREMENT
3.0 V to 2.0 V (CR2032 battery)
1.0 V, ±2% (TJ from –40 to +85ºC)
10 mA
8.2.2 Design Considerations
For this design example, the 1.0-V, fixed-version TPS7A0510 device is selected. A single CR2032 coin-cell
battery was used, thus a 1.0-µF input capacitor is recommended to minimize transient currents drawn from the
battery. A 1.0-µF output capacitor is also recommended for excellent load transient response. The dropout
voltage (VDO) is kept within the TPS7A05 dropout voltage specification for the 1.0-V output voltage option to keep
the device in regulation under all load and temperature conditions for this design. The very small ground current
consumed by the regulator shown in 图 54 allows for long battery life.
8.2.3 Application Curve
4
3
2
1
0
0
1
2
3
4
5
6
Output Current (mA)
7
8
9
10
D042
图 54. IGND vs IOUT at 25°C
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 1.4 V to 5.5 V. The input supply must
be well regulated and free of spurious noise. To ensure that the output voltage is well regulated and dynamic
performance is optimum, the input supply must be at least VOUT(nom) + 0.5 V. A 1 µF or greater input capacitor is
recommended to be used to reduce the impedance of the input supply, especially during transients.
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10 Layout
10.1 Layout Guidelines
•
•
•
•
Place input and output capacitors as close to the device as possible
Use copper planes for device connections to optimize thermal performance
Place thermal vias around the device to distribute heat
Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Example
IN
OUT
A2
A1
COUT
CIN
Via
B1
B2
EN
GND
图 55. Layout Example for the YKA Package
VOUT
VIN
5
1
CIN
COUT
2
3
4
EN
GND PLANE
Represents via used for
application specific connections
图 56. Layout Example for the DBV Package
VOUT
VIN
1
4
COUT
CIN
3
2
EN
GND PLANE
Represents via used for
application specific connections
图 57. Layout Example for the DQN Package
28
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ZHCSHN3D –FEBRUARY 2018–REVISED AUGUST 2019
11 器件和文档支持
11.1 器件支持
11.1.1 Spice 模型
您可以从产品文件夹中的工具与软件下获取 TPS7A05 的 SPICE 模型。
11.1.2 器件命名规则
表 3. 器件命名规则(1)(2)
产品
VOUT
xx(x) 为标称输出电压。对于分辨率为 100mV 的输出电压，订货编号中使用两位数字；否则，使用三位数
字（例如，28 = 2.8V；125 = 1.25V）。
TPS7A05xx(x)Pyyyz
P 是可选的；P 表示有源输出放电功能。
yyy 为封装标识符。
z 为封装数量。R 表示卷（3000 片），T 表示带（250 片）。
(1) 要获得最新的封装和订货信息，请参阅本文档末尾的封装选项附录，或者访问器件产品文件夹（www.ti.com.cn）。
(2) 可提供 1.0V 至 3.3V 范围内的输出电压（以 50mV 为单位增量）。更多详细信息及可用性，请联系制造商。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档：
《通用低压降 (LDO) 线性稳压器 MultiPkgLDOEVM-823 评估模块》
11.3 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
30
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A0508PDBVR
TPS7A0508PDBVT
TPS7A0508PDBZR
TPS7A0508PDBZT
TPS7A0508PDQNR
TPS7A0508PDQNT
TPS7A0508PYKAR
TPS7A0510PDBVR
TPS7A0510PDBVT
TPS7A0510PDQNR
TPS7A0510PDQNT
TPS7A0510PYKAR
TPS7A0511PDQNR
TPS7A0512PDBVR
TPS7A0512PDBVT
TPS7A0512PDBZR
TPS7A0512PDBZT
TPS7A0512PDQNR
TPS7A0512PDQNT
TPS7A0512PYKAR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
X2SON
DSBGA
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
DBV
DBV
DQN
DQN
YKA
DQN
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
5
5
3
3
4
4
4
5
5
4
4
4
4
5
5
3
3
4
4
4
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1C6F
1C6F
NIPDAU
SN
1QMW
1QMW
6G
SN
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
NIPDAU
NIPDAU
NIPDAU
SN
6G
12000 RoHS & Green
3000 RoHS & Green
3
1IKF
1IKF
C7
250
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
C7
12000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
L
HK
1ILF
1ILF
1QOW
1QOW
C8
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
12000 RoHS & Green
RoHS & Green
SN
NIPDAU
NIPDAU
SNAGCU
C8
M
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A0515PDBVR
TPS7A0515PDBVT
TPS7A0515PDQNR
TPS7A0515PDQNT
TPS7A0515PYKAR
TPS7A051825PYKAR
TPS7A0518PDBVR
TPS7A0518PDBVT
TPS7A0518PDBZR
TPS7A0518PDBZT
TPS7A0518PDQNR
TPS7A0518PDQNT
TPS7A0518PYKAR
TPS7A0520PDBZR
TPS7A0520PDBZT
TPS7A0520PDQNR
TPS7A0522PDBVR
TPS7A0522PDBVT
TPS7A0522PDBZR
TPS7A0522PDBZT
TPS7A0525PDBVR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
SOT-23
X2SON
X2SON
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
DBV
DBV
DQN
DQN
YKA
YKA
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
DBZ
DBZ
DQN
DBV
DBV
DBZ
DBZ
DBV
5
5
4
4
4
4
5
5
3
3
4
4
4
3
3
4
5
5
3
3
5
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1IMF
1IMF
C9
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SNAGCU
NIPDAU
NIPDAU
SN
C9
12000 RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
N
P
1INF
1INF
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
1QQW
1QQW
CA
SN
NIPDAU
NIPDAU
SNAGCU
SN
CA
12000 RoHS & Green
3000 RoHS & Green
P
1U8W
1U8W
G1
250
RoHS & Green
SN
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
NIPDAU
SN
1P3F
1P3F
1U9W
1U9W
1IOF
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
RoHS & Green
SN
NIPDAU
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A0525PDBVT
TPS7A0525PDQNR
TPS7A0525PDQNT
TPS7A0525PYKAR
TPS7A0527PDBZR
TPS7A0527PDBZT
TPS7A05285PDBVR
TPS7A05285PDBVT
TPS7A05285PDQNR
TPS7A05285PDQNT
TPS7A05285PYKAR
TPS7A0528PDBZR
TPS7A0528PDBZT
TPS7A0528PDQNR
TPS7A0528PDQNT
TPS7A0530PDBVR
TPS7A0530PDBVT
TPS7A0530PDBZR
TPS7A0530PDBZT
TPS7A0530PDQNR
TPS7A0530PDQNT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DBV
DQN
DQN
YKA
DBZ
DBZ
DBV
DBV
DQN
DQN
YKA
DBZ
DBZ
DQN
DQN
DBV
DBV
DBZ
DBZ
DQN
DQN
5
4
4
4
3
3
5
5
4
4
4
3
3
4
4
5
5
3
3
4
4
250
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1IOF
CB
CB
Q
3000 RoHS & Green
250 RoHS & Green
NIPDAU
NIPDAU
SNAGCU
SN
12000 RoHS & Green
3000 RoHS & Green
1UAW
1UAW
1IRF
1IRF
CC
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
RoHS & Green
SN
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SNAGCU
SN
CC
12000 RoHS & Green
3000 RoHS & Green
R
1QSW
1QSW
DH
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
RoHS & Green
SN
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SN
DH
1QWF
1QWF
1QUW
1QUW
DG
SN
NIPDAU
NIPDAU
250
RoHS & Green
DG
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A0530PYKAR
TPS7A0531PDBVR
TPS7A0531PDBVT
TPS7A0531PDQNR
TPS7A0533PDBVR
TPS7A0533PDBVT
TPS7A0533PDBZR
TPS7A0533PDBZT
TPS7A0533PDQNR
TPS7A0533PDQNT
TPS7A0533PYKAR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
SOT-23
SOT-23
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
YKA
DBV
DBV
DQN
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
4
5
5
4
5
5
3
3
4
4
4
12000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
W
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
SN
1P4F
1P4F
I6
250
RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
1IPF
1IPF
250
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
12000 RoHS & Green
RoHS & Green
1QVW
1QVW
CD
SN
NIPDAU
NIPDAU
SNAGCU
CD
S
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A0508PDBVR
TPS7A0508PDBVT
TPS7A0508PDBZR
TPS7A0508PDBZT
TPS7A0508PDQNR
TPS7A0508PDQNT
TPS7A0508PYKAR
TPS7A0510PDBVR
TPS7A0510PDBVT
TPS7A0510PDQNR
TPS7A0510PDQNT
TPS7A0510PYKAR
TPS7A0511PDQNR
TPS7A0512PDBVR
TPS7A0512PDBVT
TPS7A0512PDBZR
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
X2SON
DSBGA
X2SON
SOT-23
SOT-23
SOT-23
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
DBV
DBV
DQN
DQN
YKA
DQN
DBV
DBV
DBZ
5
5
3
3
4
4
4
5
5
4
4
4
4
5
5
3
3000
250
180.0
180.0
178.0
178.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
178.0
8.4
8.4
9.0
9.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
9.0
3.2
3.2
3.2
3.2
1.4
1.4
4.0
4.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q2
Q2
Q1
Q3
Q3
Q2
Q2
Q1
Q2
Q3
Q3
Q3
3000
250
3.15
3.15
1.16
1.16
0.76
3.2
2.77
2.77
1.16
1.16
0.76
3.2
1.22
1.22
0.5
3000
250
0.5
12000
3000
250
0.46
1.4
3.2
3.2
1.4
3000
250
1.16
1.16
0.76
1.16
3.2
1.16
1.16
0.76
1.16
3.2
0.5
0.5
12000
3000
3000
250
0.46
0.5
1.4
3.2
3.2
1.4
3000
3.15
2.77
1.22
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A0512PDBZT
TPS7A0512PDQNR
TPS7A0512PDQNT
TPS7A0512PYKAR
TPS7A0515PDBVR
TPS7A0515PDBVT
TPS7A0515PDQNR
TPS7A0515PDQNT
TPS7A0515PYKAR
TPS7A051825PYKAR
TPS7A0518PDBVR
TPS7A0518PDBVT
TPS7A0518PDBZR
TPS7A0518PDBZT
TPS7A0518PDQNR
TPS7A0518PDQNT
TPS7A0518PYKAR
TPS7A0520PDBZR
TPS7A0520PDBZT
TPS7A0520PDQNR
TPS7A0522PDBVR
TPS7A0522PDBVT
TPS7A0522PDBZR
TPS7A0522PDBZT
TPS7A0525PDBVR
TPS7A0525PDBVT
TPS7A0525PDQNR
TPS7A0525PDQNT
TPS7A0525PYKAR
TPS7A0527PDBZR
TPS7A0527PDBZT
TPS7A05285PDBVR
TPS7A05285PDBVT
TPS7A05285PDQNR
TPS7A05285PDQNT
TPS7A05285PYKAR
TPS7A0528PDBZR
TPS7A0528PDBZT
TPS7A0528PDQNR
TPS7A0528PDQNT
TPS7A0530PDBVR
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
X2SON
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
X2SON
SOT-23
DBZ
DQN
DQN
YKA
DBV
DBV
DQN
DQN
YKA
YKA
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
DBZ
DBZ
DQN
DBV
DBV
DBZ
DBZ
DBV
DBV
DQN
DQN
YKA
DBZ
DBZ
DBV
DBV
DQN
DQN
YKA
DBZ
DBZ
DQN
DQN
DBV
3
4
4
4
5
5
4
4
4
4
5
5
3
3
4
4
4
3
3
4
5
5
3
3
5
5
4
4
4
3
3
5
5
4
4
4
3
3
4
4
5
250
3000
250
178.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
9.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
3.15
1.16
1.16
0.76
3.2
2.77
1.16
1.16
0.76
3.2
1.22
0.5
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
2.0
2.0
4.0
4.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q2
Q2
Q1
Q3
Q3
Q2
Q2
Q1
Q1
Q3
Q3
Q3
Q3
Q2
Q2
Q1
Q3
Q3
Q2
Q3
Q3
Q3
Q3
Q3
Q3
Q2
Q2
Q1
Q3
Q3
Q3
Q3
Q2
Q2
Q1
Q3
Q3
Q2
Q2
Q3
0.5
12000
3000
250
0.46
1.4
3.2
3.2
1.4
3000
250
1.16
1.16
0.76
0.76
3.2
1.16
1.16
0.76
0.76
3.2
0.5
0.5
12000
12000
3000
250
0.46
0.46
1.4
3.2
3.2
1.4
3000
250
3.15
3.15
1.16
1.16
0.76
3.15
3.15
1.16
3.2
2.77
2.77
1.16
1.16
0.76
2.77
2.77
1.16
3.2
1.22
1.22
0.5
3000
250
0.5
12000
3000
250
0.46
1.22
1.22
0.5
3000
3000
250
1.4
3.2
3.2
1.4
3000
250
3.15
3.15
3.2
2.77
2.77
3.2
1.22
1.22
1.4
3000
250
3.2
3.2
1.4
3000
250
1.16
1.16
0.76
3.15
3.15
3.2
1.16
1.16
0.76
2.77
2.77
3.2
0.5
0.5
12000
3000
250
0.46
1.22
1.22
1.4
3000
250
3.2
3.2
1.4
3000
250
1.16
1.16
0.76
3.15
3.15
1.16
1.16
3.2
1.16
1.16
0.76
2.77
2.77
1.16
1.16
3.2
0.5
0.5
12000
3000
250
0.46
1.22
1.22
0.5
3000
250
0.5
3000
1.4
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A0530PDBVT
TPS7A0530PDBZR
TPS7A0530PDBZT
TPS7A0530PDQNR
TPS7A0530PDQNT
TPS7A0530PYKAR
TPS7A0531PDBVR
TPS7A0531PDBVT
TPS7A0531PDQNR
TPS7A0533PDBVR
TPS7A0533PDBVT
TPS7A0533PDBZR
TPS7A0533PDBZT
TPS7A0533PDQNR
TPS7A0533PDQNT
TPS7A0533PYKAR
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
DBV
DBZ
DBZ
DQN
DQN
YKA
DBV
DBV
DQN
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
5
3
3
4
4
4
5
5
4
5
5
3
3
4
4
4
250
3000
250
180.0
178.0
178.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
178.0
178.0
180.0
180.0
180.0
8.4
9.0
9.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
9.0
9.0
8.4
8.4
8.4
3.2
3.15
3.15
1.16
1.16
0.76
3.2
3.2
2.77
2.77
1.16
1.16
0.76
3.2
1.4
1.22
1.22
0.5
4.0
4.0
4.0
4.0
4.0
2.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
4.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q2
Q2
Q1
Q3
Q3
Q2
Q3
Q3
Q3
Q3
Q2
Q2
Q1
3000
250
0.5
12000
3000
250
0.46
1.4
3.2
3.2
1.4
3000
3000
250
1.16
3.2
1.16
3.2
0.5
1.4
3.2
3.2
1.4
3000
250
3.15
3.15
1.16
1.16
0.76
2.77
2.77
1.16
1.16
0.76
1.22
1.22
0.5
3000
250
0.5
12000
0.46
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A0508PDBVR
TPS7A0508PDBVT
TPS7A0508PDBZR
TPS7A0508PDBZT
TPS7A0508PDQNR
TPS7A0508PDQNT
TPS7A0508PYKAR
TPS7A0510PDBVR
TPS7A0510PDBVT
TPS7A0510PDQNR
TPS7A0510PDQNT
TPS7A0510PYKAR
TPS7A0511PDQNR
TPS7A0512PDBVR
TPS7A0512PDBVT
TPS7A0512PDBZR
TPS7A0512PDBZT
TPS7A0512PDQNR
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
X2SON
DSBGA
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
DBV
DBV
DQN
DQN
YKA
DQN
DBV
DBV
DBZ
DBZ
DQN
5
5
3
3
4
4
4
5
5
4
4
4
4
5
5
3
3
4
3000
250
210.0
210.0
180.0
180.0
210.0
210.0
182.0
210.0
210.0
210.0
210.0
182.0
210.0
210.0
210.0
180.0
180.0
210.0
185.0
185.0
180.0
180.0
185.0
185.0
182.0
185.0
185.0
185.0
185.0
182.0
185.0
185.0
185.0
180.0
180.0
185.0
35.0
35.0
18.0
18.0
35.0
35.0
20.0
35.0
35.0
35.0
35.0
20.0
35.0
35.0
35.0
18.0
18.0
35.0
3000
250
3000
250
12000
3000
250
3000
250
12000
3000
3000
250
3000
250
3000
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A0512PDQNT
TPS7A0512PYKAR
TPS7A0515PDBVR
TPS7A0515PDBVT
TPS7A0515PDQNR
TPS7A0515PDQNT
TPS7A0515PYKAR
TPS7A051825PYKAR
TPS7A0518PDBVR
TPS7A0518PDBVT
TPS7A0518PDBZR
TPS7A0518PDBZT
TPS7A0518PDQNR
TPS7A0518PDQNT
TPS7A0518PYKAR
TPS7A0520PDBZR
TPS7A0520PDBZT
TPS7A0520PDQNR
TPS7A0522PDBVR
TPS7A0522PDBVT
TPS7A0522PDBZR
TPS7A0522PDBZT
TPS7A0525PDBVR
TPS7A0525PDBVT
TPS7A0525PDQNR
TPS7A0525PDQNT
TPS7A0525PYKAR
TPS7A0527PDBZR
TPS7A0527PDBZT
TPS7A05285PDBVR
TPS7A05285PDBVT
TPS7A05285PDQNR
TPS7A05285PDQNT
TPS7A05285PYKAR
TPS7A0528PDBZR
TPS7A0528PDBZT
TPS7A0528PDQNR
TPS7A0528PDQNT
TPS7A0530PDBVR
TPS7A0530PDBVT
TPS7A0530PDBZR
TPS7A0530PDBZT
TPS7A0530PDQNR
X2SON
DSBGA
SOT-23
SOT-23
X2SON
X2SON
DSBGA
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
SOT-23
SOT-23
X2SON
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
DQN
YKA
DBV
DBV
DQN
DQN
YKA
YKA
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
DBZ
DBZ
DQN
DBV
DBV
DBZ
DBZ
DBV
DBV
DQN
DQN
YKA
DBZ
DBZ
DBV
DBV
DQN
DQN
YKA
DBZ
DBZ
DQN
DQN
DBV
DBV
DBZ
DBZ
DQN
4
4
5
5
4
4
4
4
5
5
3
3
4
4
4
3
3
4
5
5
3
3
5
5
4
4
4
3
3
5
5
4
4
4
3
3
4
4
5
5
3
3
4
250
12000
3000
250
210.0
182.0
210.0
210.0
210.0
210.0
182.0
182.0
210.0
210.0
180.0
180.0
210.0
210.0
182.0
180.0
180.0
210.0
210.0
210.0
180.0
180.0
210.0
210.0
210.0
210.0
182.0
180.0
180.0
210.0
210.0
210.0
210.0
182.0
180.0
180.0
210.0
210.0
210.0
210.0
180.0
180.0
210.0
185.0
182.0
185.0
185.0
185.0
185.0
182.0
182.0
185.0
185.0
180.0
180.0
185.0
185.0
182.0
180.0
180.0
185.0
185.0
185.0
180.0
180.0
185.0
185.0
185.0
185.0
182.0
180.0
180.0
185.0
185.0
185.0
185.0
182.0
180.0
180.0
185.0
185.0
185.0
185.0
180.0
180.0
185.0
35.0
20.0
35.0
35.0
35.0
35.0
20.0
20.0
35.0
35.0
18.0
18.0
35.0
35.0
20.0
18.0
18.0
35.0
35.0
35.0
18.0
18.0
35.0
35.0
35.0
35.0
20.0
18.0
18.0
35.0
35.0
35.0
35.0
20.0
18.0
18.0
35.0
35.0
35.0
35.0
18.0
18.0
35.0
3000
250
12000
12000
3000
250
3000
250
3000
250
12000
3000
250
3000
3000
250
3000
250
3000
250
3000
250
12000
3000
250
3000
250
3000
250
12000
3000
250
3000
250
3000
250
3000
250
3000
Pack Materials-Page 5
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jul-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A0530PDQNT
TPS7A0530PYKAR
TPS7A0531PDBVR
TPS7A0531PDBVT
TPS7A0531PDQNR
TPS7A0533PDBVR
TPS7A0533PDBVT
TPS7A0533PDBZR
TPS7A0533PDBZT
TPS7A0533PDQNR
TPS7A0533PDQNT
TPS7A0533PYKAR
X2SON
DSBGA
SOT-23
SOT-23
X2SON
SOT-23
SOT-23
SOT-23
SOT-23
X2SON
X2SON
DSBGA
DQN
YKA
DBV
DBV
DQN
DBV
DBV
DBZ
DBZ
DQN
DQN
YKA
4
4
5
5
4
5
5
3
3
4
4
4
250
12000
3000
250
210.0
182.0
210.0
210.0
210.0
210.0
210.0
180.0
180.0
210.0
210.0
182.0
185.0
182.0
185.0
185.0
185.0
185.0
185.0
180.0
180.0
185.0
185.0
182.0
35.0
20.0
35.0
35.0
35.0
35.0
35.0
18.0
18.0
35.0
35.0
20.0
3000
3000
250
3000
250
3000
250
12000
Pack Materials-Page 6
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.12 MAX
1.4
1.2
B
A
0.1 C
PIN 1
INDEX AREA
1
0.95
(0.125)
3.04
2.80
1.9
3
(0.15)
NOTE 4
2
0.5
0.3
3X
0.10
0.01
(0.95)
TYP
0.2
C A B
0.25
GAGE PLANE
0.20
0.08
TYP
0.6
0.2
TYP
SEATING PLANE
0 -8 TYP
4214838/D 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214838/D 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/D 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
YKA0004
DSBGA - 0.4 mm max height
SCALE 14.000
DIE SIZE BALL GRID ARRAY
A
D
B
E
BALL A1
CORNER
0.4 MAX
C
SEATING PLANE
0.05 C
0.18
0.13
BALL TYP
0.35 TYP
B
A
SYMM
0.35
TYP
D: Max = 0.694 mm, Min =0.634 mm
E: Max = 0.694 mm, Min =0.634 mm
1
2
0.25
0.15
C A B
4X
0.015
SYMM
4221909/B 08/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.2)
(0.35) TYP
2
1
A
B
SYMM
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:60X
(
0.2)
0.0325 MIN
0.0325 MAX
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
(
0.2)
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4221909/B 08/2018
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKA0004
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35) TYP
4X ( 0.21)
(R0.05) TYP
2
1
A
B
SYMM
(0.35)
TYP
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm - 0.1 mm THICK STENCIL
SCALE:60X
4221909/B 08/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
A
B
1
1.05
0.95
PIN 1
INDEX AREA
C
0.4 MAX
SEATING PLANE
0.08
NOTE 6
+0.12
-0.1
0.05
0.00
0.48
(0.05) TYP
NOTE 6
2
1
3
EXPOSED
THERMAL PAD
5
2X 0.65
(0.07) TYP
NOTE 5
4
0.28
PIN 1 ID
(OPTIONAL)
NOTE 4
4X
0.15
(0.11)
0.3
0.2
0.1
C A B
0.05
C
0.30
0.15
3X
4215302/E 12/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.
5. Shape of exposed side leads may differ.
6. Number and location of exposed tie bars may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.86)
SYMM
SEE DETAIL
4X
4X (0.36)
(0.03)
4
4X (0.21)
1
5
SYMM
(0.65)
4X (0.18)
2
3
(
0.48)
(0.22) TYP
EXPOSED METAL
CLEARANCE
LAND PATTERN EXAMPLE
SCALE: 40X
0.05 MIN
ALL AROUND
SOLDER MASK
OPENING
EXPOSED METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAIL
4215302/E 12/2016
NOTES: (continued)
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
8. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
X2SON - 0.4 mm max height
DQN0004A
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
SYMM
4X (0.4)
4X (0.03)
4
1
4X (0.21)
5
SYMM
(0.65)
SOLDER MASK
EDGE
4X (0.22)
2
3
(
0.45)
4X (0.235)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1mm THICK STENCIL
EXPOSED PAD
88% PRINTED SOLDER COVERAGE BY AREA
SCALE: 60X
4215302/E 12/2016
NOTES: (continued)
9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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