TPS7A1025PYKAR [TI]
具有使能功能的 300mA、低输入电压 (0.75V)、超低 IQ、低压降稳压器 | YKA | 5 | -40 to 125;型号: | TPS7A1025PYKAR |
厂家: | TEXAS INSTRUMENTS |
描述: | 具有使能功能的 300mA、低输入电压 (0.75V)、超低 IQ、低压降稳压器 | YKA | 5 | -40 to 125 稳压器 |
文件: | 总40页 (文件大小:2644K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
TPS7A10 300mA 低输入电压、低输出电压、超低压降稳压器
1 特性
3 说明
1
•
•
超低输入电压范围:0.75V 至 3.3V
可实现最低功率损耗的超低压降:
TPS7A10 是一款超小型低静态电流低压降稳压器
(LDO),它能够实现 300mA 的拉电流并具有出色的交
流性能(负载和线路瞬态响应)。该器件具有 0.75V
至 3.3V 的输入范围以及 0.5V 至 3.0V 的输出范围,并
在负载、线路和温度上具有 1.5% 的极高精度。此性能
非常适合于为更低的现代 MCU 内核电压和模拟传感器
供电。
–
在 300mA 下为 70mV(最大值)(VOUT
1.0V),YKA 封装
>
•
低静态电流:
–
–
VIN IQ= 1.6µA(典型值)
VBIAS IQ= 6µA(典型值)
•
•
•
负载、线路和温度上的精度为 1.5%
高 PSRR:频率 1kHz 时为 60dB
可提供固定输出电压:
主要电源路径通过 VIN,可连接至高于输出电压的值低
至 70mV 的电源。该器件使用一个用于为 LDO 的内部
电路供电的附加 VBIAS 电源轨,支持极低的输入电压。
VIN 和 VBIAS 分别消耗 1.6µA 和 6µA 的极低静态电
流。低 IQ 和超低压降 特性 有助于提高功耗敏感型应
用中解决方案的 效率。例如,VIN 可以是高效直流/直
流降压稳压器的输出,而 VBIAS 引脚可以连接至一个可
再充电电池。
–
0.5V 至 3.0V(阶跃 为 50mV)
BIAS 范围:1.7V 至 5.5V
•
•
V
封装:
–
–
0.74mm × 1.09mm WCSP-5
1.50mm × 1.50mm WSON-6
•
•
内置软启动功能,具有单调 VOUT 上升
TPS7A10 配备了一个有源下拉电路,用于在处于禁用
状态时对输出进行快速放电,并提供已知的启动状态。
有源输出放电
2 应用
TPS7A10 可采用超小型 5 引脚 DSBGA (YKA) 封装,
从而使其非常适合空间受限的 应用。该器件还可采用
6 引脚 WSON (DSE) 封装。
•
•
•
•
•
智能手表、健身追踪器
无线耳机和耳塞
摄像头模块
器件信息(1)
智能手机和平板电脑
便携式医疗设备
器件型号
封装
WSON (6)
封装尺寸(标称值)
1.50mm × 1.50mm
0.74mm ×
1.09mm(0.35mm
间距)
TPS7A10
DSBGA (5)
(1) 如需了解所有可用封装,请参阅产品说明书末尾的封装选项附
录。
压降与 IOUT 和温度间的关系(YKA 封装)
典型应用电路
VBATTERY
80
TJ
CBIAS
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
60
40
20
0
BIAS
VOUT
IN
OUT
Standalone
IN
OUT
CIN
COUT
TPS7A10
DC/DC Converter
or PMU
EN
GND
GND
VEN
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
D013
1
本文档旨在为方便起见,提供有关 TI 产品中文版本的信息,以确认产品的概要。 有关适用的官方英文版本的最新信息,请访问 www.ti.com,其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前,请务必参考最新版本的英文版本。
English Data Sheet: SBVS314
TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
www.ti.com.cn
目录
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
7.4 Device Functional Modes........................................ 17
8
9
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Application .................................................. 22
Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Examples................................................... 24
11 器件和文档支持 ..................................................... 25
11.1 器件支持 ............................................................... 25
11.2 文档支持................................................................ 25
11.3 接收文档更新通知 ................................................. 25
11.4 社区资源................................................................ 25
11.5 商标....................................................................... 25
11.6 静电放电警告......................................................... 25
11.7 术语表 ................................................................... 26
12 机械、封装和可订购信息....................................... 26
7
4 修订历史记录
注:之前版本的页码可能与当前版本有所不同。
Changes from Revision A (June 2018) to Revision B
Page
•
•
•
•
•
已添加 YKA 封装 添加至以下章节的可实现最低功率损耗的超低压降 项目的子项目: ......................................................... 1
已添加 在 部分中添加了最后一个句子说明 部分的关断相关文字 ........................................................................................... 1
已更改 将 WSON (DSE) 封装从“预告信息”更改为“生产数据(正在供货)” ........................................................................... 1
已添加 YKA 封装 添加至压降与 IOUT 和温度间的关系(YKA 封装) 一图的标题中 ............................................................... 1
已添加 YKA Package to captions of Output Accuracy Over Temperature, YKA Package and Output Accuracy Over
Temperature, YKA Package figures....................................................................................................................................... 7
•
已添加 Output Accuracy Over Temperature, DSE Package and Output Accuracy Over Temperature, DSE Package
figures..................................................................................................................................................................................... 7
•
•
已添加 YKA Package to caption of Dropout vs IIOUT and Temperature, YKA Package figure ............................................... 7
已添加 Dropout vs IIOUT and Temperature, DSE Package figure .......................................................................................... 8
Changes from Original (March 2018) to Revision A
Page
•
已更改 从“预告信息”更改为“生产数据(正在供货)” .............................................................................................................. 1
2
Copyright © 2018, Texas Instruments Incorporated
TPS7A10
www.ti.com.cn
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
5 Pin Configuration and Functions
DSE Package
6-Pin WSON
Top View
YKA Package
5-Pin DSBGA
Top View
OUT
1
2
3
6
5
IN
IN
GND
BIAS
A1
A3
OUT
GND
BIAS
B2
EN
4
C1
C3
EN
Not to scale
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
DSE
YKA
Input pin. For best transient response and to minimize input impedance, use the
recommended or larger value ceramic capacitor from IN to ground. as listed in the
Recommended Operation Conditions. Place the input capacitor as close as possible to input
of the device.
IN
6
A1
I
Regulated output pin. A capacitor is required from OUT to ground for stability. For best
transient response, use larger than the minimum recommended value ceramic capacitor.
Follow the recommended capacitor value as listed in the Recommended Operation
Conditions. Place the output capacitor as close as possible to output of the device.
OUT
GND
BIAS
1
5
4
A3
B2
C1
O
—
I
Ground pin. This pin must be connected to ground.
BIAS pin. This pin enables the use of low-input voltage, low-output voltage conditions, (LILO).
For best response, use the recommended or larger value ceramic capacitor from BIAS to
ground as listed in the Recommended Operation Conditions. Place the bias capacitor as
close as possible to input of the device.
Enable pin. Driving this pin to logic high enables the device. Driving this pin to logic low
disables the device. If enable functionality is not required, this pin must be connected to IN or
BIAS; however, connecting EN to IN is only acceptable if the VIN voltage is greater than 0.9 V.
EN
3
C3
I
Copyright © 2018, Texas Instruments Incorporated
3
TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted.(1)
MIN
–0.3
–0.3
–0.3
–0.3
MAX UNIT
Supply, VIN
3.6
Enable, VEN
Voltage
6.0
V
Bias, VBIAS
6.0
VIN + 0.3(2)
Output, VOUT
Current
Maximum output current
Internally limited
A
Operating junction temperature, TJ
Storage temperature, Tstg
–40
–65
150
150
°C
°C
Temperature
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum rating is 3.6 or (VIN + 0.3) , whichever is less.
6.2 ESD Ratings
VALUE
±1000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating junction temperature range (unless otherwise noted).
MIN
0.75
1.7
0.5
0
NOM
MAX
3.3
UNIT
V
VIN
Input voltage
VBIAS
VOUT
IOUT
CIN
Bias voltage
5.5
V
Output voltage
3.0
V
Peak output current
Input capacitor
300
mA
µF
µF
µF
℃
2.2
CBIAS
COUT
TJ
Bias capacitor
0.1
(1)
Output capacitor
Operating junction temperature
2.2
22
–40
125
(1) Maximum ESR must be lower than 250 mΩ
6.4 Thermal Information
TPS7A10
YKA (WSCP)
THERMAL METRIC(1)
DSE (WSON)
6 PINS
188.8
82.9
UNIT
5 PINS
169.4
1.1
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
101.0
6.6
55.4
1.7
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
100.4
N/A
55.6
N/A
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics .
4
Copyright © 2018, Texas Instruments Incorporated
TPS7A10
www.ti.com.cn
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
6.5 Electrical Characteristics
over TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = 1.0 V, CIN = 2.2 μF, COUT
2.2 μF, and CBIAS = 0.1 μF ( unless otherwise noted); all typical values are at TJ = 25°C .
=
PARAMETER
Nominal Accuracy
TEST CONDITIONS
MIN
TYP
MAX UNIT
TJ = 25°C
–0.5
0.5
–20°C ≤ TJ ≤ 85, DSE package
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V,
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 300 mA
–1.25
–1.25
1.25
–40°C ≤ TJ ≤ 85, YKA package
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V,
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 300 mA
%
Accuracy over
temperature
1.25
1.5
–40°C ≤ TJ ≤ 125, DSE and YKA
package
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V,
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V,
1 mA ≤ IOUT ≤ 300 mA
–1.5
ΔVOUT / ΔVIN
ΔVOUT / ΔVBIAS
ΔVOUT / ΔIOUT
VIN line regulation
VBIAS line regulation
Load regulation
VOUT(NOM) + 0.5 V ≤ VIN ≤ 3.3 V
VOUT(NOM) + 1.4 V ≤ VBIAS ≤ 5.5 V
0.1 mA ≤ IOUT ≤ 300 mA
TJ = 25°C, IOUT = 0 mA
–40°C < TJ < 85°C, IOUT = 0 mA
IOUT = 0 mA
0.001
0.03
0.2
%/V
%/V
%/A
3
6
8
11
14
60
2.1
2.3
2.6
9
IQ(BIAS)
Bias pin current
µA
µA
IOUT = 300 mA
TJ = 25°C, IOUT = 0 mA
–40°C < TJ < 85°C, IOUT = 0 mA
IOUT = 0 mA
1.6
IQ(IN)
Input pin current(1)
IOUT = 300 mA
–40°C < TJ < 85°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
400
1200
1
ISHDN(BIAS)
VBIAS shutdown current
VIN shutdown current
nA
µA
–40°C < TJ < 125°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
–40°C < TJ < 85°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
ISHDN(IN)
–40°C < TJ < 125°C,
VIN = 3.3 V, VBIAS = 5.5 V, VEN ≤ 0.4 V
3
VOUT = 0.9 × VOUT(NOM), YKA package
VOUT = 0.9 × VOUT(NOM), DSE package
VOUT = 0 V
325
350
450
450
150
600
625
mA
mA
mA
ICL
ISC
Output current limit
Short circuit current limit
VIN = VOUT(NOM) – 0.1 V, IOUT = 300 mA,
YKA package
40
55
70
90
VDO(IN)
VIN dropout voltage(2)
VBIAS dropout voltage(2)
mV
V
VIN = VOUT(NOM) – 0.1 V, IOUT = 300 mA,
DSE package
IOUT = 300 mA
IOUT = 150 mA
0.85
0.75
1.05
0.95
VDO(BIAS)
(1) This current flowing from VIN to GND.
(2) Dropout is not measured for VOUT < 1.0 V
Copyright © 2018, Texas Instruments Incorporated
5
TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
www.ti.com.cn
Electrical Characteristics (continued)
over TJ = –40°C to +125°C, VIN = VOUT(NOM) + 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = 1.0 V, CIN = 2.2 μF, COUT
2.2 μF, and CBIAS = 0.1 μF ( unless otherwise noted); all typical values are at TJ = 25°C .
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
f = 1 kHz,
VOUT = 1.1 V, IOUT = 50 mA
60
f = 100 kHz,
VOUT = 1.1 V, IOUT = 50 mA
36
32
VIN power-supply rejection
ratio
VIN PSRR
dB
f = 1 MHz,
VOUT = 1.1 V, IOUT = 50 mA
f = 1.5 MHz,
VOUT = 1.1 V, IOUT = 50 mA
35
f = 1 kHz,
VOUT = 1.1 V, IOUT = 300 mA
60
f = 100 kHz,
VOUT = 1.1 V, IOUT = 300 mA
VBIAS power-supply
rejection ratio
VBIAS PSRR
40
dB
f = 1 MHz,
VOUT = 1.1 V, IOUT = 300 mA
35
Bandwidth = 10 Hz to 100 kHz,
VOUT = 1.0 V, IOUT = 50 mA
Vn
Output voltage noise
93.9
µVRMS
V
VBIAS rising
VBIAS falling
VBIAS hysteresis
VIN rising
1.46
1.35
1.54
1.44
80
1.63
1.55
VUVLO(BIAS)
VUVLO_HYST(BIAS)
VUVLO(IN)
Bias supply UVLO
Bias supply hysteresis
Input supply UVLO
mV
mV
mV
mV
µs
V
645
565
675
600
75
710
640
VIN falling
VUVLO_HYST(IN)
tSTR
Input supply hysteresis
Start-up time(3)
VIN hysteresis
525
1200
0.4
VHI(EN)
EN pin logic high voltage
EN pin logic low voltage
EN pin current
0.9
VLO(EN)
IEN
V
EN = 5.5 V
10
120
160
145
nA
Ω
RPULLDOWN
Pulldown resistor
VBIAS = 3.3 V, P version only
Shutdown, temperature rising
Reset, temperature falling
Thermal shutdown
temperature
TSD
°C
(3) Startup time = time from EN assertion to 0.95 × VOUT(NOM).
6
版权 © 2018, Texas Instruments Incorporated
TPS7A10
www.ti.com.cn
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
6.6 Typical Characteristics
at TJ = –40 °C to +125 °C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = 2.2 µF, COUT
2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
0.25
0.2
0.25
0.2
TJ
TJ
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
0.15
0.1
0.15
0.1
0.05
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
-0.05
-0.1
-0.15
-0.2
-0.25
1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
Input Voltage (V)
3
3.2 3.4
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
VOUT = 1.0 V
VOUT = 1.0 V
图 1. Output Accuracy Over Temperature, YKA Package
0.5
图 2. Output Accuracy Over Temperature, YKA Package
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.1
-0.2
-0.3
-0.4
-0.5
TJ
25 èC
85 èC
TJ
25 èC
85 èC
-40 èC
0 èC
105 èC
125 èC
-40 èC
0 èC
105 èC
125 èC
1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
Input Voltage (V)
3
3.2 3.4
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
VOUT = 1.0 V
VOUT = 1.0 V
图 3. Output Accuracy Over Temperature, DSE Package
0.25
图 4. Output Accuracy Over Temperature, DSE Package
80
TJ
TJ
0.2
0.15
0.1
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
60
40
20
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.25
2
2.5
3
3.5
4
4.5
5
5.5
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
Bias Voltage (V)
D013
VOUT = 1.0 V
VOUT = 1.0 V
图 5. Output Accuracy Over Temperature and VBIAS
图 6. Dropout vs IIOUT and Temperature, YKA Package
版权 © 2018, Texas Instruments Incorporated
7
TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
www.ti.com.cn
Typical Characteristics (接下页)
at TJ = –40 °C to +125 °C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = 2.2 µF, COUT
2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
100
80
60
40
20
0
1100
1000
900
800
700
600
500
400
TJ
-40 èC
85 èC
105 èC
125 èC
0 èC
25 èC
TJ
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
0
30
60
90 120 150 180 210 240 270 300
Output Current (mA)
D013
VOUT = 1.0 V
图 8. Dropout vs VBIAS and Temperature
VOUT = 1.0 V
图 7. Dropout vs IIOUT and Temperature, DSE Package
200
100
0
700
200
700
600
500
400
300
200
100
0
VOUT
IOUT
VOUT
IOUT
600
500
400
300
200
100
0
100
0
-100
-200
-300
-400
-500
-600
-100
-200
-300
-400
-500
-600
-100
-100
0
100 200 300 400 500 600 700 800 900 1000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
Time (µs)
D028
VOUT = 1.1 V, IOUT = 0 mA to 150 mA
VOUT = 1.1 V, IOUT = 1 mA to 150 mA
图 9. IOUT Transient
图 10. IOUT Transient
200
100
0
700
200
100
0
700
VOUT
IOUT
VOUT
IOUT
600
500
400
300
200
100
0
600
500
400
300
200
100
0
-100
-200
-300
-400
-500
-600
-100
-200
-300
-400
-500
-600
-100
-100
0
100 200 300 400 500 600 700 800 900 1000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Time (µs)
Time (µs)
D028
VOUT = 1.1 V, IOUT = 0 mA to 300 mA
VOUT = 1.1 V, IOUT = 1 mA to 300 mA
图 11. IOUT Transient
图 12. IOUT Transient
8
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Typical Characteristics (接下页)
at TJ = –40 °C to +125 °C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = 2.2 µF, COUT
2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
6
5.5
5
100
6
5.5
5
100
50
50
0
0
4.5
4
-50
4.5
4
-50
-100
-150
-200
-250
-300
-350
-400
-100
-150
-200
-250
-300
-350
-400
VIN
VOUT
VIN
VOUT
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
VOUT = 1.1 V, IOUT = 300 mA
VOUT = 1.1 V, IOUT = 1 mA
图 13. VIN Transient
图 14. VIN Transient
1.2
1
12
10
8
TJ
0.8
0.6
0.4
0.2
0
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
6
4
TJ
2
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
0
100
150
200
250
300
350
400
450
500
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Output Current (mA)
Bias Voltage (V)
D012
D007
IOUT = 0 mA
图 15. Foldback Current Limit Over Temperature
图 16. IQ (VBIAS) Over Temperature
45
40
35
30
25
20
15
10
5
2.2
2
1.8
1.6
1.4
1.2
1
TJ
TJ
-40 °C
0 °C
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
85 °C
105 °C
125 °C
25 °C
0
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
3.25 3.5
Bias Voltage (V)
Input Voltage (V)
D007
D008
IOUT = 300 mA
图 17. IQ (VBIAS) Over Temperature
IOUT = 0 mA
图 18. IQ (VIN) Over Temperature
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Typical Characteristics (接下页)
at TJ = –40 °C to +125 °C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = 2.2 µF, COUT
2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
10
3.5
TJ
-40 °C
0 °C
25 °C
85 °C
105 °C
125 °C
3
8
2.5
2
6
1.5
1
4
0.5
0
2
TJ
25 °C
85 °C
-40 °C
0 °C
105 °C
0
-0.5
1
1.25 1.5 1.75
2
2.25 2.5 2.75
3
3.25 3.5
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
Input Voltage (V)
Input Voltage (V)
D009
D011
IOUT = 300 mA
VOUT = 1.0 V, VEN < 0.4 V
图 19. IQ (VIN) Over Temperature
图 20. ISHDN (VIN) Over Temperature
3
2.5
2
2.75
2.5
2.25
2
1.75
1.5
1.5
1
1.25
1
0.75
0.5
0.5
0
0.25
0
VIN
VOUT
VBIAS
VEN
VIN
VOUT
VBIAS
VEN
-0.5
-0.25
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
VOUT = 1.1 V
VOUT = 1.1 V
图 21. Startup With VEN = VIN
图 22. Startup With Separated VEN
2
1.5
1
2
1.5
1
VIN
VOUT
VEN
VBIAS
VIN
VOUT
VEN
VBIAS
0.5
0
0.5
0
-0.5
-0.5
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
0
100 200 300 400 500 600 700 800 900 1000
Time (µs)
VOUT = 0.5 V
VOUT = 0.5 V
图 23. Startup With VEN and VBIAS Powering Up
图 24. Startup With VBIAS Powering Up After VIN and VEN
Simultaneously
10
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Typical Characteristics (接下页)
at TJ = –40 °C to +125 °C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = 2.2 µF, COUT
2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
80
70
60
50
40
30
20
10
0
80
70
60
50
40
30
20
10
0
I OUT
1 mA
10 mA
50 mA
I OUT
1 mA
10 mA
50 mA
100 mA
200 mA
300 mA
100 mA
200 mA
300 mA
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
CIN = 0 µF, VOUT = 1.1 V, VBIAS = 2.5 V, CBIAS = 0.1 µF
CIN = 0 µF, VOUT = 0.5 V, VBIAS = 1.9 V, CBIAS = 0.1 µF
图 25. PSRR vs Frequency and IOUT
图 26. PSRR vs Frequency and IOUT
80
80
2.2 mF Cout
22 mF Cout
2.2mF Cout
22mF Cout
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
0
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
CIN = 0 µF, VOUT = 1.1 V, VBIAS = 2.5 V, CBIAS = 0.1 µF
CIN = 0 µF, VOUT = 0.5 V, VBIAS = 1.9 V, CBIAS = 0.1 µF
图 27. PSRR vs Frequency and COUT
图 28. PSRR vs Frequency and COUT
80
80
VDO
200mV
400mV
600mV
800mV
1.0V
70
60
50
40
30
20
10
0
70
60
50
40
30
20
10
VIN-VOUT
200mV
400mV
600mV
800mV
1.0V
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
CIN = 0 µF, VOUT = 1.1 V, IOUT = 300 mA, VBIAS = 2.5 V,
CBIAS = 0.1 µF
CIN = 0 µF, VOUT = 0.5 V, IOUT = 300 mA, VBIAS = 1.9 V,
CBIAS = 0.1 µF
图 29. PSRR vs Frequency and VDO
图 30. PSRR vs Frequency and VDO
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Typical Characteristics (接下页)
at TJ = –40 °C to +125 °C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = 2.2 µF, COUT
2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted); typical values are at TJ = 25°C
=
80
70
60
50
40
30
20
10
0
20
VOUT = 0.5 V, 42.3 µVRMS
VOUT = 1.0 V, 87.6 µVRMS
VOUT = 3.0 V, 201.1 µVRMS
10
1
0.1
VBIAS
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
0.01
0.005
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D023
VOUT = 1.1 V, IOUT = 300 mA, CBIAS = 0 µF
IOUT = 300 mA
图 31. VBIAS PSRR vs Frequency and VBIAS
图 32. Output Noise vs Frequency and VOUT
20
20
10
IOUT, (mVRMS
50 mA, (93.9)
100 mA, (90.8)
150 mA, (89.6)
)
COUT, (mVRMS
)
10
200 mA, (88.8)
250 mA, (87.8)
300 mA, (87.6)
2.2 µF, (87.6)
4.7 µF, (85.1)
10 µF, (89.4)
1
1
0.1
0.1
0.01
0.01
0.005
0.005
10
100
1k
10k
100k
1M
10M
10
100
1k
10k
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
D025
VOUT = 1.0 V, VBIAS = 2.5 V
图 33. Output Noise vs Frequency and IOUT
VEN(LO)
VOUT = 1.0 V, IOUT = 300 mA
图 34. Output Noise vs Frequency and COUT
0.605
0.595
0.585
0.575
0.565
0.555
0.545
0.535
0.525
0.515
0.69
0.68
0.67
0.66
0.65
0.64
0.63
0.62
0.61
0.6
VEN(HI)
VIN UVLO (Falling)
VIN UVLO (Rising)
0.59
0.58
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
Temperature (°C)
D014
D015
图 35. Enable High and Low Thresholds vs Temperature
图 36. VUVLO(IN) Rising and Falling Thresholds vs
Temperature
12
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Typical Characteristics (接下页)
at TJ = –40 °C to +125 °C, VIN = VOUT(NOM)+ 0.5 V, VBIAS = VOUT(NOM) + 1.4 V, IOUT = 1 mA, VEN = VIN, CIN = 2.2 µF, COUT
=
2.2 µF, and CBIAS = 0.1 µF (unless otherwise noted); typical values are at TJ = 25°C
1.65
1.6
1.55
1.5
1.45
1.4
1.35
VBIAS UVLO (Falling)
VBIAS UVLO (Rising)
1.3
-40
-20
0
20
40
60
80 100 120 140
Temperature (°C)
D016
图 37. VUVLO(BIAS) Rising and Falling Thresholds vs Temperature
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7 Detailed Description
7.1 Overview
The TPS7A10 is a low input, ultra-low dropout, and low quiescent current linear regulator that is optimized for
excellent transient performance. These characteristics make the device ideal for most battery-powered
applications. The implementation of the BIAS pin on the TPS7A10 vastly improves efficiency of low-voltage
output applications by allowing the use of a preregulated, low-voltage input supply that offers sub-band-gap
output voltages. The high power-supply rejection ratio (PSRR), low noise, low ground pin current, and ultra-small
packaging make this device suitable for ultra-portable applications. This device also offers high output voltage
accuracy of 1.5% over the recommended junction temperature range.
7.2 Functional Block Diagram
Current
Limit
IN
BIAS
EN
OUT
Thermal
Shutdown
+
Global
UVLO
Active Discharge
P-Version Only
œ
Bandgap
GND
Internal
Controller
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7.3 Feature Description
7.3.1 Excellent Transient Response
The TPS7A10 responds quickly to a transient on the input supply (line transient) or the output current (load
transient) that results from the device high input impedance and low output impedance across frequency. This
same capability also means that the device has a high power-supply rejection ratio (PSRR) and low internal
noise floor (en). The low-dropout regulator (LDO) approximates an ideal power supply in ac (small-signal) and dc
(large-signal) conditions.
The choice of external component values optimizes the small- and large-signal response; see the Input and
Output Capacitor Requirements section for proper selection.
7.3.2 Global Undervoltage Lockout (UVLO)
The TPS7A10 uses two undervoltage lockout (UVLO) circuits: one on the BIAS pin and one on the IN pin to
prevent the device from turning on before both VBIAS and VIN rise above their lockout voltages. The two UVLO
signals are connected internally through an AND gate, as shown in 图 38. This internal connection allows the
device to be turned off when either rail is below its lockout voltage.
UVLO(IN)
Global UVLO
UVLO(BIAS)
图 38. Global UVLO circuit
7.3.3 Active Discharge
The active discharge option (P version only) have internal pulldown MOSFET that connects a 120-Ω resistor to
ground when the device is disabled in order to actively discharge the output voltage. The active discharge circuit
is activated by driving the enable pin to logic low to disable the device, or when the device is in thermal
shutdown.
The discharge time after disabling the device depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. 公式 1 calculates the discharge time constant:
120 · RL
t =
· COUT
120 + RL
(1)
Do not rely on the active discharge circuit for discharging a large amount of output capacitance after the input
supply collapses because reverse current can possibly flow from the output to the input. This reverse current flow
can cause damage to the device. Limit reverse current to no more than 5% of the device-rated current.
7.3.4 Enable
The enable pin for this device is active high. The output of the device is turned on when the enable pin voltage is
greater than the EN pin logic high voltage, and the output of the device is turned off when the enable pin voltage
is less than the EN pin voltage logic low .
The EN pin can be tied to the IN pin, the BIAS pin, or can be driven separately to enable and disable the device;
however, connecting the EN pin to the IN pin is only acceptable if the VIN voltage is greater than 0.9 V.
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Feature Description (接下页)
7.3.5 Sequencing Requirement
The VIN, VBIAS, and VEN voltages can be sequenced in any order without causing damage to the device. The start
up is always monotonic regardless of the sequencing order or the ramp rates of IN, BIAS, and EN pins. For
optimum device performance, have VBIAS present before enabling the device in any sequence order between VIN
and VEN because the device internal circuitry is powered off the VBIAS, refer to Recommended Operating
Conditions for proper voltage ranges of VIN, VBIAS, and VEN
.
7.3.6 Internal Foldback Current Limit
The internal foldback current limit circuit is used to protect the LDO against high-load current faults or shorting
events. The foldback mechanism lowers the current limit as the output voltage decreases, and limits power
dissipation during short-circuit events while still allowing for the device to operate at the rated output current; see
图 15.
For example, when VOUT is 90% of VOUT(nom), the current limit is ICL (typical); however, if VOUT is forced to 0 V, the
current limit is ISC (typical).
In many LDOs, the foldback current limit can prevent start up into a constant-current load or a negatively-biased
output. A brick-wall current limit is when there is an abrupt current stop after the current limit is reached. The
foldback mechanism for this device goes into a brick-wall current limit when VOUT > 500 mV (typical), thus limiting
current to ICL (typical). When VOUT is approximately 0 V, current is limited to ISC (typical) in order to provide
normal start up into a variety of loads.
Thermal shutdown can activate during a current-limit event because of the high power dissipation typically found
in these conditions. To provide proper operation of the current limit, minimize the inductances to the input and
load. Continuous operation in current limit is not recommended.
7.3.7 Thermal Shutdown
The device contains a thermal shutdown protection circuit to disable the device when the thermal junction
temperature (TJ) of the main pass-FET rises to the thermal shutdown temperature (TSD ) for shutdown listed in
the Electrical Characteristics. Thermal shutdown hysteresis makes sure that the LDO resets again (turns on)
when the temperature falls to the TSD for reset.
The thermal time constant of the semiconductor die is fairly short, and thus the device may cycle on and off
when thermal shutdown is reached until the power dissipation is reduced.
For reliable operation, limit the junction temperature to a maximum of 125°C. Operation above 125°C causes the
device to exceed the operational specifications. Although the internal protection circuitry of the device is
designed to protect against thermal overload conditions, this circuitry is not intended to replace proper heat
sinking. Continuously running the device into thermal shutdown or above a junction temperature of 125°C
reduces long-term reliability.
A fast start up when TJ > the TSD for reset causes the device thermal shutdown to assert at TSD for reset, and
prevents the device from turning on until the junction temperature is reduced below TSD for reset.
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7.4 Device Functional Modes
The device has the following modes of operation:
•
•
•
Normal operation: The device regulates to the nominal output voltage.
Dropout operation: The pass element operates as a resistor and the output voltage is set as VIN – VDO
Disabled: The output of the device is disabled and the discharge circuit is activated.
.
表 1 shows the conditions that lead to the different modes of operation.
表 1. Device Functional Mode Comparison
PARAMETER
OPERATING MODE
VIN
VBIAS
VEN
IOUT
TJ
Normal mode
Dropout mode
VIN > VOUT(nom) + VDO and VIN > VIN(min) VBIAS > VOUT + 1.05 V
VEN > VHI(EN)
VEN > VHI(EN)
IOUT < ICL
IOUT < ICL
TJ < TSD for shutdown
TJ < TSD for shutdown
VIN(min) < VIN < VOUT(nom) + VDO
VIN < VUVLO(IN)
VBIAS < VOUT + 1.05 V
VBIAS < VBIAS(UVLO)
Disabled mode
(any true condition
disables the device)
VEN < VLO(EN)
—
TJ > TSD for shutdown
7.4.1 Normal Mode
The device regulates the output to the nominal output voltage when all normal mode conditions in 表 1 are met.
7.4.2 Dropout Mode
The device is not in regulation, and the output voltage tracks the input voltage minus the voltage drop across the
pass element of the device. In this mode, PSRR and the noise performance of the device are significantly
degraded.
7.4.3 Disable Mode
In this mode, the pass element is turned off, the internal circuits are shut down, and the output voltage is actively
discharged to ground by an internal resistor.
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8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
Successfully implementing an LDO in an application depends on the application requirements. This section
discusses key device features and the best implementation to achieve a reliable design.
8.1.1 Recommended Capacitor Types
The device is designed to be stable using low equivalent series resistance (ESR) ceramic capacitors at the input,
output, and BIAS pins. Multilayer ceramic capacitors are the industry standard for these types of applications, but
must be used with good judgment. Ceramic capacitors that use X7R-, X5R-, and COG-rated dielectric materials
provide relatively good capacitive stability across temperature. Avoid Y5V-rated capacitors because of large
variations in capacitance.
Regardless of the ceramic capacitor type selected, ceramic capacitance varies with operating voltage and
temperature. As a rule of thumb, assume that effective capacitance decreases by as much as 50%. The input,
output, and bias capacitors recommended in the Recommended Operating Conditions table account for an
effective capacitance of approximately 50% of the nominal value.
8.1.2 Input and Output Capacitor Requirements
A minimum 2.2-µF ceramic capacitor at the input is required for stability, A minimum 2.2-µF ceramic capacitor
with a maximum ESR value of less than 250 mΩ at the output is also required for stability. The input capacitor
counteracts reactive input sources and improves transient response, input ripple, and PSRR. A higher-value
input capacitor may be necessary if large, fast rise-time load or line transients are anticipated, or if the device is
located several inches from the input power source. Dynamic performance of the device is improved with the use
of an output capacitor larger than the minimum value specified in the Recommended Operating Conditions table.
Although a bias capacitor is not required, connect a 0.1-µF ceramic capacitor from BIAS to GND for best analog
design practice. This capacitor counteracts reactive bias sources if the source impedance is not sufficiently low.
Place the input, output, and bias capacitors as close as possible to the device to minimize traces parasitics.
18
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Application Information (接下页)
8.1.3 Load Transient Response
The load-step transient response is the output voltage response by the LDO to a step in load current while output
voltage regulation is maintained. See 图 9, 图 10, 图 11, and 图 12 for typical load transient response. There are
two key transitions during a load transient response: the transition from a light to a heavy load, and the transition
from a heavy to a light load. The regions in 图 39 are broken down as described in this section. Regions A, E,
and H are where the output voltage is in steady-state operation.
tAt
tCt
tDt
tEt
tGt
tHt
B
F
图 39. Load Transient Waveform
During transitions from a light load to a heavy load:
•
The initial voltage dip is a result of the depletion of the output capacitor charge and parasitic impedance to the
output capacitor (region B)
•
Recovery from the dip results from the LDO increasing the sourcing current, and leads to output voltage
regulation (region C)
During transitions from a heavy load to a light load:
•
The initial voltage rise results from the LDO sourcing a large current, and leads to the output capacitor charge
to increase (region F)
•
Recovery from the rise results from the LDO decreasing the sourcing current in combination with the load
discharging the output capacitor (region G)
A larger output capacitance reduces the peaks during a load transient, but slows down the response time of the
device. A larger dc load also reduces the peaks because the amplitude of the transition is lowered, and a higher
current discharge path is provided for the output capacitor.
8.1.4 Dropout Voltage
Generally, dropout voltage refers to the minimum voltage difference between the input and output voltage (VDO
=
VIN – VOUT ) that is required for regulation. When VIN – VOUT drops below the required VDO for the given load
current, the device functions as a resistive switch and does not regulate output voltage. Dropout voltage is
proportional to the output current because the device is operating as a resistive switch.
Dropout voltage is affected by the drive strength of the pass-element gate. This drive strength is nonlinear with
respect to VIN on this device.
8.1.5 Behavior During Transition From Dropout Into Regulation
Some applications may have transients that place this device into dropout, especially when this device can be
powered from a battery with relatively high ESR. The load transient saturates the output stage of the error
amplifier when the pass element is driven fully on, making the pass element function like a resistor from VIN to
VOUT. The error amplifier response time to this load transient is limited because the error amplifier must first
recover from saturation and then place the pass element back into active mode. During this time, VOUT
overshoots because the pass element is functioning as a resistor from VIN to VOUT
.
When VIN ramps up slowly for start-up, the slow ramp-up voltage may place the device in dropout. As with many
other LDOs, the output can overshoot on recovery from this condition. However, this condition is easily avoided
through the use of the enable signal.
If operating under these conditions, apply a higher dc load or increase the output capacitance to reduce the
overshoot. These solutions provide a path to dissipate the excess charge.
版权 © 2018, Texas Instruments Incorporated
19
TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
www.ti.com.cn
Application Information (接下页)
8.1.6 Undervoltage Lockout Circuit Operation
The VIN UVLO circuit makes sure that the device remains disabled before the input supply reaches the minimum
operational voltage range. The VIN UVLO circuit also makes sure that the device shuts down when the input
supply collapses. Similarly, the VBIAS UVLO circuit makes sure that the device stays disabled before the bias
supply reaches the minimum operational voltage range. The VBIAS UVLO circuit also makes sure that the device
shuts down when the bias supply collapses.
图 40 depicts the UVLO circuit response to various input or bias voltage events. This figure can be separated into
the following parts:
•
•
•
Region A: The device does not start until the input or bias voltage reaches the UVLO rising threshold.
Region B: Normal operation, regulating device
Region C: Brownout event above the UVLO falling threshold (UVLO rising threshold – UVLO hysteresis). The
output may fall out of regulation, but the device is still enabled.
•
•
Region D: Normal operation, regulating device
Region E: Brownout event below the UVLO falling threshold. The device is disabled in most cases, and the
output falls as a result of the load and active discharge circuit. The device is re-enabled when the UVLO
rising threshold is reached, and a normal start-up follows.
•
•
Region F: Normal operation followed by the input or bias falling to the UVLO falling threshold
Region G: The device is disabled as the input or bias voltages fall below the UVLO falling threshold to 0 V.
The output falls as a result of the load and active discharge circuit.
UVLO Rising Threshold
UVLO Hysteresis
VIN / VBIAS
C
VOUT
tAt
tBt
tDt
tEt
tFt
tGt
图 40. Typical VIN or VBIAS UVLO Circuit Operation
8.1.7 Power Dissipation (PD)
Circuit reliability demands that proper consideration be given to device power dissipation, location of the circuit
on the printed circuit board (PCB), and correct sizing of the thermal plane. The PCB area around the regulator
must be as free as possible of other heat-generating devices that cause added thermal stresses.
公式 2 calculates the maximum allowable power dissipation for the device in a given package:
PD-MAX = [(TJ – TA) / RθJA
]
(2)
公式 3 represents the actual power being dissipated in the device:
PD = (IGND+ IOUT) × (VIN – VOUT
)
(3)
Power dissipation can be minimized, and thus greater efficiency achieved, by proper selection of the system
voltage rails. Proper selection allows the minimum input-to-output voltage differential to be obtained. The low
dropout of the TPS7A10 allows for maximum efficiency across a wide range of output voltages.
The main heat conduction path for the device depends on the ambient temperature and the thermal resistance
across the various interfaces between the die junction and ambient air.
20
版权 © 2018, Texas Instruments Incorporated
TPS7A10
www.ti.com.cn
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
Application Information (接下页)
The maximum power dissipation determines the maximum allowable junction temperature (TJ) for the device.
According to 公式 4, maximum power dissipation and junction temperature are most often related by the junction-
to-ambient thermal resistance (RθJA) of the combined PCB and device package and the temperature of the
ambient air (TA). The equation is rearranged in 公式 5 for output current.
TJ = TA + (RθJA × PD)
(4)
(5)
IOUT = (TJ – TA) / [RθJA × (VIN – VOUT)]
Unfortunately, this thermal resistance (RθJA) is highly dependent on the heat-spreading capability built into the
particular PCB design, and therefore varies according to the total copper area, copper weight, and location of the
planes. The RθJA recorded in the Thermal Information table is determined by the JEDEC standard, PCB, and
copper-spreading area, and is only used as a relative measure of package thermal performance.
8.1.7.1 Estimating Junction Temperature
The JEDEC standard recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of
the LDO when in-circuit on a typical PCB board application. These metrics are not strictly speaking thermal
resistances, but rather offer practical and relative means of estimating junction temperatures. These psi metrics
are determined to be significantly independent of the copper-spreading area. The key thermal metrics (ΨJT and
ΨJB) are used in accordance with 公式 6 and are given in the Thermal Information table.
ΨJT : TJ = TT + ΨJT × PD and ΨJB : TJ = TB + ΨJB × PD
where:
•
•
•
PD is the power dissipated as explained in 公式 3
TT is the temperature at the center-top of the device package
TB is the PCB surface temperature measured 1 mm from the device package and centered on the package
edge
(6)
8.1.7.2 Recommended Area for Continuous Operation
The operational area of an LDO is limited by the dropout voltage, output current, junction temperature, and input
voltage. The recommended area for continuous operation for a linear regulator is shown in 图 41, and can be
separated into the following regions:
•
•
•
Dropout voltage limits the minimum differential voltage between the input and the output (VIN – VOUT) at a
given output current level.
The rated output currents limits the maximum recommended output current level. Exceeding this rating
causes the device to fall out of specification.
The rated junction temperature limits the maximum junction temperature of the device. Exceeding this rating
causes the device to fall out of specification and reduces long-term reliability.
–
公式 5 provides the shape of the slope. The slope is nonlinear because the maximum rated junction
temperature of the LDO is controlled by the power dissipation across the LDO, thus when VIN – VOUT
increases, the output current must decrease.
•
The rated input voltage range governs both the minimum and maximum of VIN – VOUT.
Output Current Limited
by Dropout
Rated Output
Current
Output Current Limited
by Thermals
Limited by
Limited by
Minimum VIN
Maximum VIN
VIN œ VOUT (V)
图 41. Region Description of Continuous Operation Regime
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21
TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
www.ti.com.cn
8.2 Typical Application
VBATTERY
CBIAS
BIAS
1.4 V
1.2 V
COUT
IN
VOUT
OUT
Standalone
DC/DC Converter
or PMU
CIN
TPS7A10
EN
GND
VEN
图 42. Supplying a Clean DC Voltage
8.2.1 Design Requirements
表 2 summarizes the design requirements for 图 42.
表 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
VIN
1.4 V
2.7 V
1.2 V
VBIAS
VOUT
IOUT
10-mA typical, 300-mA peak
65°C
Maximum ambient temperature
8.2.2 Detailed Design Procedure
For this design example, the 1.2-V, fixed-version TPS7A1012 device is selected. Use a 4.7-µF input capacitor to
minimize transient currents drawn from the DC/DC convertor. Use a 4.7-µF output capacitor for optimized load
transient response. The dropout voltage (VDO) is kept within the TPS7A10 dropout voltage specification for the
1.2-V output voltage option inorder to keep the device in regulation under all load and temperature conditions for
this design. The high-PSRR and low-noise measurements for this design example are given in the Thermal
Dissipation section.
8.2.2.1 Input Current
During normal operation, the input current to the LDO is approximately equal to the output current of the LDO.
During startup, the input current is higher as a result of the inrush current charging the output capacitor. Use 公式
7 to calculate the current through the input.
C
OUT ´ dVOUT(t)
VOUT(t)
RLOAD
IOUT(t)
=
+
dt
where:
•
•
•
VOUT(t) is the instantaneous output voltage of the turnon ramp
dVOUT(t) / dt is the slope of the VOUT ramp
RLOAD is the resistive load impedance
(7)
22
版权 © 2018, Texas Instruments Incorporated
TPS7A10
www.ti.com.cn
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
8.2.2.2 Thermal Dissipation
The junction temperature can be determined using the junction-to-ambient thermal resistance (RθJA) and the total
power dissipation (PD). Use 公式 8 to calculate the power dissipation. As 公式 9 shows, multiply PD by RθJA and
add the ambient temperature (TA) to calculate the junction temperature (TJ).
PD = (IGND+ IOUT) × (VIN – VOUT
)
(8)
(9)
TJ = RθJA × PD + TA
If the (TJ(MAX)) value does not exceed 125°C, use 公式 10 to calculate the maximum ambient temperature. 公式
11 calculates the maximum ambient temperature with a value of 99.59°C.
TA(MAX) = TJ(MAX) – RθJA × PD
(10)
(11)
TA(MAX) = 125°C – 169.4 × (1.4 V – 1.2 V) × (0.3 A) = 114.84°C
8.2.3 Application Curve
90
IOUT
10 mA
40 mA
80 mA
120 mA
80
70
60
50
40
30
20
10
0
160 mA
200 mA
250 mA
300 mA
-10
10
100
1k
10k
100k
1M
10M
Input Voltage (V)
D036
VIN = 1.4 V, VOUT = 1.2 V, VBIAS = 2.7 V,
CIN = 4.7 µF, COUT = 4.7 µF, CBIAS = 0.1 µF
图 43. PSRR vs Frequency and IOUT
版权 © 2018, Texas Instruments Incorporated
23
TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
www.ti.com.cn
9 Power Supply Recommendations
This device is designed to operate from an input supply voltage range of 0.75 V to 3.3 V, and a bias supply
voltage range of 1.7 V to 5.5 V. The input and bias supplies must be well regulated and free of spurious noise.
To make sure that the output voltage is well regulated and dynamic performance is optimum, the input supply
must be at least VOUT(nom) + 0.5 V and VBIAS = VOUT(nom) + 1.05 V.
10 Layout
10.1 Layout Guidelines
For correct printed circuit board (PCB) layout, follow these guidelines:
•
•
•
Place input, output, and bias capacitors as close to the device as possible.
Use copper planes for device connections to optimize thermal performance.
Place thermal vias around the device to distribute heat.
10.2 Layout Examples
OUT
COUT
IN
CIN
A1
C1
A3
C3
GND
B2
CBIAS
BIAS
EN
图 44. Recommended Layout for the YKA Package
OUT
COUT
NC
1
IN
6
CIN
2
3
5
4
GND
CBIAS
BIAS
EN
图 45. Recommended Layout for the DSE Package
24
版权 © 2018, Texas Instruments Incorporated
TPS7A10
www.ti.com.cn
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
11 器件和文档支持
11.1 器件支持
11.1.1 开发支持
11.1.1.1 评估模块
我们为您提供了评估模块 (EVM),可以借此来对使用 TPS7A10 时的电路性能进行初始评估。可通过德州仪器 (TI)
网站上的产品文件夹申请获取 TPS7A10EVM,也可以直接从 TI eStore 购买。
11.1.1.2 Spice 模型
可以通过 TPS7A10 产品文件夹的工具与软件选项卡获取该器件的 Spice 模型。
11.1.2 器件命名规则
表 3. 器件命名规则(1)(2)
产品
VOUT
xx(x) 为标称输出电压。对于分辨率为 50mV 的输出电压,订货编号中使用两位数字;否则,使用三位数
字(例如,28 = 2.8V;125 = 1.25 V)。
yyy 为封装标识符。
TPS7A10xx(x)yyyz
z 为封装数量。R 表示卷,T 表示带。
(1) 要获得最新的封装和订货信息,请参阅本文档末尾的封装选项附录,或者访问器件产品文件夹(www.ti.com.cn)。
(2) 可提供 0.5V 至 3.0V 的输出电压(以 50mV 为单位增量)。有关器件的详细信息和供货情况,请联系制造商。
11.2 文档支持
11.2.1 相关文档
请参阅如下相关文档:
•
•
•
德州仪器 (TI),《TPS7A10EVM-004 评估模块》用户指南
德州仪器 (TI),《使用新的热度量指标》应用报告
德州仪器 (TI),《AN-1112 DSBGA 晶圆级芯片级封装》应用报告
11.3 接收文档更新通知
要接收文档更新通知,请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册,即可每周接收产
品信息更改摘要。有关更改的详细信息,请查看任何已修订文档中包含的修订历史记录。
11.4 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范,
并且不一定反映 TI 的观点;请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中,您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持
TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。
11.5 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时,应将导线一起截短或将装置放置于导电泡棉中,以防止 MOS 门极遭受静电损
伤。
版权 © 2018, Texas Instruments Incorporated
25
TPS7A10
ZHCSHU2B –MARCH 2018–REVISED OCTOBER 2018
www.ti.com.cn
11.7 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更,恕不另行通知,且
不会对此文档进行修订。如需获取此数据表的浏览器版本,请查阅左侧的导航栏。
26
版权 © 2018, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A1006PDSER
TPS7A1006PDSET
TPS7A1006PYKAR
TPS7A1008PDSER
TPS7A1008PDSET
TPS7A1008PYKAR
TPS7A10105PDSER
TPS7A10105PDSET
TPS7A10105PYKAR
TPS7A1010PDSER
TPS7A1010PDSET
TPS7A1010PYKAR
TPS7A1011PDSER
TPS7A1011PDSET
TPS7A1011PYKAR
TPS7A1012PDSER
TPS7A1012PDSET
TPS7A1012PYKAR
TPS7A1015PDSER
TPS7A1015PDSET
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
EF
EF
T
NIPDAUAG
SNAGCU
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
SNAGCU
E2
E2
A
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
SNAGCU
DZ
DZ
C
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
SNAGCU
E1
E1
B
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
SNAGCU
DX
DX
D
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
SNAGCU
DW
DW
E
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
DV
DV
250
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPS7A1015PYKAR
TPS7A1018PDSER
TPS7A1018PDSET
TPS7A1018PYKAR
TPS7A1025PDSER
TPS7A1025PDSET
TPS7A1025PYKAR
TPS7A1028PDSER
TPS7A1028PDSET
TPS7A1028PYKAR
TPS7A1030PDSER
TPS7A1030PDSET
TPS7A1030PYKAR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
5
6
6
5
6
6
5
6
6
5
6
6
5
12000 RoHS & Green
3000 RoHS & Green
SNAGCU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
F
NIPDAUAG
NIPDAUAG
SNAGCU
DU
DU
G
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
SNAGCU
DT
DT
H
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
SNAGCU
DS
DS
I
250
RoHS & Green
12000 RoHS & Green
3000 RoHS & Green
NIPDAUAG
NIPDAUAG
SNAGCU
DR
DR
J
250
RoHS & Green
12000 RoHS & Green
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A1006PDSER
TPS7A1006PDSET
TPS7A1006PYKAR
TPS7A1008PDSER
TPS7A1008PDSET
TPS7A1008PYKAR
TPS7A10105PDSER
TPS7A10105PDSET
TPS7A10105PYKAR
TPS7A1010PDSER
TPS7A1010PDSET
TPS7A1010PYKAR
TPS7A1011PDSER
TPS7A1011PDSET
TPS7A1011PYKAR
TPS7A1012PDSER
TPS7A1012PDSET
TPS7A1012PYKAR
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.83
1.83
0.9
1.83
1.83
1.25
1.83
1.83
1.25
1.83
1.83
1.25
1.83
1.83
1.25
1.83
1.83
1.25
1.83
1.83
1.25
0.89
0.89
0.48
0.89
0.89
0.48
0.89
0.89
0.48
0.89
0.89
0.48
0.89
0.89
0.48
0.89
0.89
0.48
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
12000
3000
250
1.83
1.83
0.9
12000
3000
250
1.83
1.83
0.9
12000
3000
250
1.83
1.83
0.9
12000
3000
250
1.83
1.83
0.9
12000
3000
250
1.83
1.83
0.9
12000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS7A1015PDSER
TPS7A1015PDSET
TPS7A1015PYKAR
TPS7A1018PDSER
TPS7A1018PDSET
TPS7A1018PYKAR
TPS7A1025PDSER
TPS7A1025PDSET
TPS7A1025PYKAR
TPS7A1028PDSER
TPS7A1028PDSET
TPS7A1028PYKAR
TPS7A1030PDSER
TPS7A1030PDSET
TPS7A1030PYKAR
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
3000
250
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
8.4
1.83
1.83
0.9
1.83
1.83
1.25
1.83
1.83
1.25
1.83
1.83
1.25
1.83
1.83
1.25
1.83
1.83
1.25
0.89
0.89
0.48
0.89
0.89
0.48
0.89
0.89
0.48
0.89
0.89
0.48
0.89
0.89
0.48
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
4.0
4.0
2.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q2
Q2
Q1
12000
3000
250
1.83
1.83
0.9
12000
3000
250
1.83
1.83
0.9
12000
3000
250
1.83
1.83
0.9
12000
3000
250
1.83
1.83
0.9
12000
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A1006PDSER
TPS7A1006PDSET
WSON
WSON
DSE
DSE
6
6
3000
250
183.0
183.0
183.0
183.0
20.0
20.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jan-2019
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS7A1006PYKAR
TPS7A1008PDSER
TPS7A1008PDSET
TPS7A1008PYKAR
TPS7A10105PDSER
TPS7A10105PDSET
TPS7A10105PYKAR
TPS7A1010PDSER
TPS7A1010PDSET
TPS7A1010PYKAR
TPS7A1011PDSER
TPS7A1011PDSET
TPS7A1011PYKAR
TPS7A1012PDSER
TPS7A1012PDSET
TPS7A1012PYKAR
TPS7A1015PDSER
TPS7A1015PDSET
TPS7A1015PYKAR
TPS7A1018PDSER
TPS7A1018PDSET
TPS7A1018PYKAR
TPS7A1025PDSER
TPS7A1025PDSET
TPS7A1025PYKAR
TPS7A1028PDSER
TPS7A1028PDSET
TPS7A1028PYKAR
TPS7A1030PDSER
TPS7A1030PDSET
TPS7A1030PYKAR
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
WSON
WSON
DSBGA
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
DSE
DSE
YKA
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
6
6
5
12000
3000
250
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
183.0
183.0
182.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
20.0
12000
3000
250
12000
3000
250
12000
3000
250
12000
3000
250
12000
3000
250
12000
3000
250
12000
3000
250
12000
3000
250
12000
3000
250
12000
Pack Materials-Page 3
PACKAGE OUTLINE
YKA0005
DSBGA - 0.4 mm max height
SCALE 13.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
INDEX AREA
D
0.4 MAX
C
SEATING PLANE
0.05 C
0.18
0.13
BALL
TYP
0.35
C
B
A
0.7
SYMM
D: Max = 1.12 mm, Min = 1.06 mm
E: Max = 0.77 mm, Min = 0.71 mm
0.35
0.24
5X
1
2
3
0.19
0.015
C A B
SYMM
4223737/B 05/2017
NanoFree Is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. NanoFreeTM package configuration.
www.ti.com
EXAMPLE BOARD LAYOUT
YKA0005
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35)
2
5X ( 0.2)
1
3
A
B
(0.35)
SYMM
C
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:50X
(
0.2)
0.0325 MAX
0.0325 MIN
METAL
UNDER
METAL
SOLDER MASK
EXSPOSED
EXPOSED
METAL
SOLDER MASK
OPENING
(
0.2)
METAL
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4223737/B 05/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YKA0005
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.35)
2
5X ( 0.21)
(R0.05) TYP
1
3
A
B
(0.35)
SYMM
METAL
TYP
C
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm - 0.1 mm THICK STENCIL
SCALE:50X
4223737/B 05/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DSE0006A
WSON - 0.8 mm max height
SCALE 6.000
PLASTIC SMALL OUTLINE - NO LEAD
1.55
1.45
A
B
1.55
1.45
PIN 1 INDEX AREA
0.8 MAX
C
SEATING PLANE
0.08 C
(0.2) TYP
0.05
0.00
0.6
0.4
5X
3
4
2X 1
4X 0.5
6
1
0.3
6X
0.7
0.5
0.2
0.1
0.05
PIN 1 ID
C A B
C
4220552/A 04/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
(0.8)
5X (0.7)
1
6
6X (0.25)
SYMM
4X 0.5
4
3
(R0.05) TYP
(1.6)
LAND PATTERN EXAMPLE
SCALE:40X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
PADS 4-6
NON SOLDER MASK
DEFINED
PADS 1-3
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220552/A 04/2021
NOTES: (continued)
3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSE0006A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
PKG
5X (0.7)
(0.8)
6X (0.25)
1
6
SYMM
4X (0.5)
4
3
(R0.05) TYP
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:40X
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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