TPS7A1601ADGNR [TI]

具有电源正常指示和使能功能的 100mA 60V 5μA 静态电流低压降 (LDO) 稳压器 | DGN | 8 | -40 to 150;


型号：	TPS7A1601ADGNR
厂家：	TEXAS INSTRUMENTS
描述：	具有电源正常指示和使能功能的 100mA 60V 5μA 静态电流低压降 (LDO) 稳压器 \| DGN \| 8 \| -40 to 150 稳压器
文件：	总27页 (文件大小：2158K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TPS7A16A

ZHCSPP1 –MAY 2022

TPS7A16A 具有使能和电源正常指示功能的

60V、5µA I_Q、100mA 低压降稳压器

1 特性

3 说明

• 宽输入电压范围：3 V 至60 V

• 超低静态电流：5μA

• 关断时静态电流为：1μA

• 输出电流：100mA

• 低压降：20 mA 时为60 mV

• 精度：2%

TPS7A16A 超低功耗、低压降 (LDO) 稳压器具有超低

静态电流、高输入电压以及微型高热性能封装等诸多优

势。

TPS7A16A 设计用于连续或者断续（备用电源）电池

供电的应用，在此类应用中超低的静态电流对于延长系

统电池的寿命十分关键。

• 可提供：

TPS7A16A 提供了一个与标准互补金属氧化物半导体

(CMOS) 逻辑兼容的使能引脚 (EN)，以及一个具有用

户可编程延迟的集成开漏高电平有效电源正常输出

(PG)。这些引脚用于基于微控制器、由电池供电且需

要电源轨排序的应用。

– 固定输出电压：3.3V 和5V

– 可调版本：大概1.2V 至18.5V

• 具有可编程延迟的电源正常指示功能

• 电流限制和热关断保护

• 与陶瓷输出电容器一起工作时保持稳定：≥2.2µF

• 封装：高热性能HVSSOP-8 PowerPAD^™

此外，TPS7A16A 非常适合为多节电池解决方案（从

多节电池电动工具组到汽车应用）生成低电压电源。

TPS7A16A 器件不但能够提供一个稳压良好的电压

轨，还能够承受瞬态电压并在电压瞬态期间保持稳压状

态。这些特性意味着电涌保护电路更加简单且更为经济

高效。

2 应用

• 紧急呼叫(eCall)

• 电池管理系统(BMS)

• 车载充电器(OBC) 和无线充电器

• 直流/直流转换器

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

TPS7A16A

封装

HVSSOP PowerPAD

(8)

3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

V_IN

60 V

12 V

V_OUT

V_IN

OUT

VCC

mC2

C_IN

C_OUT

R_PG

TPS7A16A

V_EN

DELAY

IO1

GND

V_PG

C_DELAY

IO3

mC1

IO2

典型应用原理图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBVS428

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

Table of Contents

8 Application and Implementation.................................. 11

8.1 Application Information..............................................11

8.2 Typical Application.................................................... 11

9 Power Supply Recommendations................................14

10 Layout...........................................................................14

10.1 Layout Guidelines................................................... 14

10.2 Layout Examples.................................................... 15

11 Device and Documentation Support..........................17

11.1 Device Support........................................................17

11.2 接收文档更新通知................................................... 17

11.3 支持资源..................................................................17

11.4 Trademarks............................................................. 17

11.5 Electrostatic Discharge Caution..............................17

11.6 术语表..................................................................... 17

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 Typical Characteristics................................................6

7 Detailed Description........................................................9

7.1 Overview.....................................................................9

7.2 Functional Block Diagram...........................................9

7.3 Feature Description.....................................................9

7.4 Device Functional Modes..........................................10

Information.................................................................... 17

12.1 Mechanical Data..................................................... 18

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

DATE

REVISION

NOTES

May 2022

Initial release

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

5 Pin Configuration and Functions

OUT

FB/DNC

DELAY

Thermal pad

GND

Not to scale

图5-1. DGN Package, 8-Pin HVSSOP PowerPAD With Exposed Thermal Pad (Top View)

NC –No internal connection

表5-1. Pin Functions

NAME

I/O

DESCRIPTION

NO.

Delay pin. Connect a capacitor to GND to adjust the PG delay time; leave open if the reset function is not

needed.

DELAY

Enable pin. This pin turns the regulator on or off.

If V_EN≥V_{EN_HI}, the regulator is enabled.

If V_EN≤V_{EN_LO}, the regulator is disabled.

If not used, the EN pin can be connected to IN. Make sure that V_EN≤V_INat all times.

For the adjustable version, the feedback pin is the input to the control-loop error amplifier. This pin sets the

output voltage of the device when the regulator output voltage is set by external resistors.

For the fixed-voltage versions, do not connect to this pin. Do not route this pin to any electrical net, not even

to GND or IN.

FB/DNC

GND

Ground pin.

—

Regulator input supply pin. A capacitor > 0.1 µF must be tied from this pin to ground to assure stability.

Connect a 10-µF ceramic capacitor from IN to GND (as close to the device as possible) to reduce circuit

sensitivity to the printed-circuit-board (PCB) layout, especially when long input traces or high source

impedances are encountered.

This pin can be left open or tied to any voltage between GND and IN.

—

Regulator output pin. A capacitor > 2.2 µF must be tied from this pin to ground to assure stability. Connect a

10-µF ceramic capacitor from OUT to GND (as close to the device as possible) to maximize ac performance.

OUT

Power-good pin. Open-collector output; leave open or connect to GND if the power-good function is not

needed.

Thermal

pad

Solder to the PCB to enhance thermal performance. Although the thermal pad can be left floating, TI highly

recommends connecting the thermal pad to the GND plane.

Pad

—

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature range (unless otherwise noted)⁽¹⁾

MIN

–0.3

MAX

UNIT

IN pin to GND pin

OUT pin to GND pin

OUT pin to IN pin

FB pin to GND pin

–0.3

0.3

–62

–0.3

Voltage

FB pin to IN pin

0.3

–62

EN pin to IN pin

–62

EN pin to GND pin

–0.3

PG pin to GND pin

5.5

–0.3

DELAY pin to GND pin

Peak output

–0.3

Current

Internally limited

–40

Operating virtual junction, T_J, absolute maximum⁽²⁾

Storage, T_STG

150

Temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Permanent damage does not occur to the part operating within this range, though electrical performance is not specified outside the

operating ambient temperature range.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

Device HBM ESD classification level 2

±2000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC Corner pins (OUT, GND, IN, and EN)

specification JESD22-C101⁽²⁾

Device CDM ESD classification level C3B

±750

±500

Other pins

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_IN

Input voltage

V_OUT

Output voltage

1.2

18.5

V_IN

1.5

EN pin voltage

EN pin slew-rate, voltage ramp-up

Delay pin voltage

V/µs

DELAY

Power-good pin voltage

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

6.4 Thermal Information

DGN (HVSSOP)

THERMAL METRIC⁽¹⁾

UNIT

8 PINS

52.5

72.2

24.1

2.3

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case(top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case(bottom) thermal resistance

ψ_JT

24.0

10.1

ψ_JB

R_θJC(bot)

(1) For information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at T_A= –40°C to +125°C, V_IN= V_OUT(NOM)+ 500 mV or V_IN= 3 V (whichever is greater), V_EN= V_IN, I_OUT= 10 μA, C_IN

2.2 μF, C_OUT= 2.2 μF, and FB tied to OUT (unless otherwise noted)

PARAMETER

TEST CONDITIONS

T_A= 25°C, V_FB= V_REF, V_IN= 3 V, I_OUT= 10 μA

V_IN≥V_OUT(NOM)+ 0.5 V

MIN

TYP

MAX

UNIT

V_IN

Input voltage range

V_REF

V_UVLO

V_OUT

Internal reference

1.169

1.193

1.217

Undervoltage lockout threshold

Output voltage range

V_REF

18.5

V_OUT(NOM)+ 0.5 V ≤V_IN≤60 V⁽¹⁾

10 μA ≤I_OUT≤100 mA

Overall V_OUTaccuracy

–2%

Line regulation

Load regulation

±1

%V_OUT

ΔV_O(ΔVI)

ΔV_O(ΔIO)

3 V ≤V_IN≤60 V

10 μA ≤I_OUT≤100 mA

V_IN= 0.95xV_OUT(NOM), I_OUT= 20 mA

V_IN= 0.95 × V_OUT(NOM), I_OUT= 100 mA

V_OUT= 90% V_OUT(NOM), V_IN= V_OUT(NOM)+ 1 V⁽³⁾

V_OUT= 90% V_OUT(NOM), V_IN= 3 V⁽⁴⁾

3 V ≤V_IN≤60 V, I_OUT= 10 μA

I_OUT= 100 mA, V_OUT= 1.2 V

V_DO

Dropout voltage

Current limit

μA

265

225

500

400

101

I_LIM

I_GND

Ground current

I_SHDN

I _FB

Shutdown supply current

Feedback current⁽²⁾

V_EN= 0.4 V, V_IN= 12 V

0.59

5.0

μA

–1

1.2

I_EN

Enable current

0.01

3 V ≤V_IN≤12 V, V_IN= V_EN

V_{EN_HI}

V_{EN_LO}

Enable high-level voltage

Enable low-level voltage

0.3

OUT pin floating, V_FBincreasing, V_IN≥V_{IN_MIN}

OUT pin floating, V_FBdecreasing, V_IN≥V_{IN_MIN}

V_IT

PG trip threshold

%V_OUT

V_HYS

PG trip hysteresis

PG output low voltage

PG leakage current

DELAY pin current

2.3

%V_OUT

V_{PG, LO}

I_{PG, LKG}

I_DELAY

0.4

OUT pin floating, V_FB= 80% V_REF, I_PG= 100 μA

V_PG= V_OUT(NOM)

–1

μA

V_IN= 3 V, V_OUT(NOM)= V_REF, C_OUT= 10 μF,

f = 100 Hz

PSRR

T_SD

Power-supply rejection ratio

°C

Shutdown, temperature increasing

Reset, temperature decreasing

175

155

Thermal shutdown temperature

(1) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈(V_IN–V_OUT) × I_OUT

(24 V –V_REF) × 50 mA ≈1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as

the power dissipated is within the thermal limits of the package plus any external heat sinking.

(2) I_FB> 0 μA flows out of the device.

(3) For fixed output voltages only.

(4) For adjustable output only, where V_OUT= 1.2 V.

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

6.6 Typical Characteristics

at T_A= –40°C to 125°C, V_IN= V_OUT(NOM)+ 0.5 V or V_IN= 3 V (whichever is greater), V_EN= V_IN, I_OUT= 10 μA, C_IN= 1 µF,

C_OUT= 2.2 µF, and FB tied to OUT (unless otherwise noted)

V_EN= 0.4 V

− 40°C

+ 25°C

+ 85°C

+ 105°C

+ 125°C

I_OUT= 0mA

− 40°C

+ 25°C

+ 85°C

+ 105°C

+ 125°C

Input Voltage (V)

图6-2. Shutdown Current vs Input Voltage

图6-1. Quiescent Current vs Input Voltage

1000

100

− 40°C

+ 25°C

+ 85°C

+ 105°C

+ 125°C

− 40°C

+ 25°C

+ 85°C

+ 105°C

+ 125°C

900

800

700

600

500

400

300

200

100

90 100

100

Output Current (mA)

图6-4. Dropout Voltage vs Output Current

图6-3. Ground Current vs Output Current

1.294

1.244

1.194

1.144

1.094

7.5

− 40°C

+ 25°C

+ 85°C

+ 105°C

+ 125°C

− 40°C

+ 25°C

+ 85°C

+ 105°C

+ 125°C

2.5

−2.5

−5

−7.5

−10

Input Voltage (V)

图6-5. Feedback Voltage vs Input Voltage

图6-6. Line Regulation

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

6.6 Typical Characteristics (continued)

at T_A= –40°C to 125°C, V_IN= V_OUT(NOM)+ 0.5 V or V_IN= 3 V (whichever is greater), V_EN= V_IN, I_OUT= 10 μA, C_IN= 1 µF,

C_OUT= 2.2 µF, and FB tied to OUT (unless otherwise noted)

7.5

300

250

200

150

100

− 40°C

+ 25°C

+ 85°C

+ 105°C

+ 125°C

2.5

−2.5

−5

− 40°C

+ 25°C

+ 85°C

+ 105°C

+ 125°C

−7.5

−10

90 100

Output Current (mA)

Input Voltage (V)

图6-7. Load Regulation

图6-8. Current Limit vs Input Voltage

2.5

PG Rising

1.5

OFF−TO−ON

ON−TO−OFF

0.5

PG Falling

−40 −25 −10

20 35 50 65 80 95 110 125

Temperature (°C)

−40 −25 −10

20 35 50 65 80 95 110 125

Temperature (°C)

图6-9. Power-Good Threshold Voltage vs Temperature

图6-10. Enable Threshold Voltage vs Temperature

100

0.1

0.01

V_IN= 3V

V_OUT= ~1.2V

C_OUT= 10µF

V_IN= 3V

V_OUT= 1.2V

C_OUT= 2.2µF

0.001

100

10k

100k

100

10k

100k

10M

Frequency (Hz)

图6-11. Power-Supply Rejection Ratio vs Frequency

图6-12. Output Spectral Noise Density

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

6.6 Typical Characteristics (continued)

at T_A= –40°C to 125°C, V_IN= V_OUT(NOM)+ 0.5 V or V_IN= 3 V (whichever is greater), V_EN= V_IN, I_OUT= 10 μA, C_IN= 1 µF,

C_OUT= 2.2 µF, and FB tied to OUT (unless otherwise noted)

V_IN(2 V/div)

V_PG(2 V/div)

V_IN= 1 V ® 6.5 V

I_OUT= 1 mA

V_OUT(1 V/div)

C_OUT= 10 mF

C_FF= 0 nF

Time (5 ms/div)

图6-13. Power-Good Delay

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

7 Detailed Description

7.1 Overview

The TPS7A16A is an ultra-low-power, low-dropout (LDO) voltage regulator that offers the benefits of ultra-low

quiescent current, high input voltage, and miniaturized, high thermal-performance packaging. The TPS7A16A

also offers an enable pin (EN) and an integrated open-drain, active-high, power-good output (PG) with a user-

programmable delay.

7.2 Functional Block Diagram

OUT

UVLO

Pass

Device

Thermal

Shutdown

Current

Limit

Error

Amp

Enable

Power

Good

Control

DELAY

7.3 Feature Description

7.3.1 Enable (EN)

The enable pin is a high-voltage-tolerant pin. A high input on EN actives the device and turns on the regulator.

For self-bias applications, connect this input to the IN pin. Ensure that V_EN≤V_INat all times.

When the enable signal is comprised of pulse-width modulation (PWM) pulses, the slew rate of the rising and

falling edges must be less than 1.5 V/µs. Adding a 0.1-µF capacitor from the EN pin to GND is recommended.

7.3.2 Regulated Output (V_OUT

)

The OUT pin is the regulated output based on the required voltage. The output has current limitation. During

initial power up, the regulator has a soft-start incorporated to control the initial current through the pass element.

In the event that the regulator drops out of regulation, the output tracks the input minus a drop based on the load

current. When the input voltage drops below the undervoltage lockout (UVLO) threshold, the regulator shuts

down until the input voltage recovers above the minimum start-up level.

7.3.3 PG Delay Timer (DELAY)

The power-good delay time (t_DELAY) is defined as the time period from when V_OUTexceeds the PG trip threshold

voltage (V_IT) to when the PG output is high. This power-good delay time is set by an external capacitor (C_DELAY

)

connected from the DELAY pin to GND; this capacitor is charged from 0 V to approximately 1.8 V by the DELAY

pin current (I_DELAY) when V_OUTexceeds the PG trip threshold (V_IT).

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

7.4 Device Functional Modes

7.4.1 Power-Good

The power-good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an

external pullup resistor. When no C_DELAYis used, the PG output is high-impedance when V_OUTis greater than

the PG trip threshold (V_IT). If V_OUTdrops below V_IT, the open-drain output turns on and pulls the PG output low.

If output voltage monitoring is not needed, the PG pin can be left floating or connected to GND.

To ensure proper operation of the power-good feature, maintain V_IN≥3 V (V_{IN_MIN}).

7.4.1.1 Power-Good Delay and Delay Capacitor

The power-good delay time (t_DELAY) is defined as the time period from when V_OUTexceeds the PG trip threshold

voltage (V_IT) to when the PG output is high. This power-good delay time is set by an external capacitor (C_DELAY

)

connected from the DELAY pin to GND; this capacitor is charged from 0 V to approximately 1.8 V by the DELAY

pin current (I_DELAY) when V_OUTexceeds the PG trip threshold (V_IT).

When C_DELAYis used, the PG output is high-impedance when V_OUTexceeds V_IT, and V_DELAYexceeds V_REF

The power-good delay time can be calculated using: t_DELAY= (C_DELAY× V_REF) / I_DELAY. For example, when

C_DELAY= 10 nF, the PG delay time is approximately 12 ms; that is, (10 nF × 1.193 V) / 1 μA = 11.93 ms.

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

8 Application and Implementation

备注

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

8.1 Application Information

The TPS7A16A offers the benefit of ultra-low quiescent current, high input voltage, and miniaturized, high-

thermal-performance packaging.

The TPS7A16A is designed for continuous or sporadic (power backup) battery-operated applications where

ultra-low quiescent current is critical to extending system battery life.

8.2 Typical Application

8.2.1 TPS7A16A Circuit as an Adjustable Regulator

V_IN

V_OUT

OUT

C_OUT

C_IN

R₁

C_FF

V_OUT

TPS7A16A

Where: R₁= R₂

- 1

R_PG

V_EN

V_REF

R₂

V_PG

DELAY

GND

C_DELAY

图8-1. The TPS7A16A Circuit as an Adjustable Regulator Schematic

8.2.1.1 Design Requirements

表8-1 lists the design parameters for this application.

表8-1. Design Parameters

DESIGN PARAMETER

Input voltage range

Output voltage

EXAMPLE VALUE

5.5 V to 40 V

5 V

Output current rating

Output capacitor range

Delay capacitor range

100 mA

2.2 µF to 100 µF

100 pF to 100 nF

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

8.2.1.2 Detailed Design Procedure

8.2.1.2.1 Adjustable Voltage Operation

The TPS7A16A has an output voltage range from 1.194 V to 20 V. As shown in 图 8-2, the nominal output of the

device is set by two external resistors.

V_IN

C_IN

R_PG

0.1 mF

1 MW

V_OUT

5 V

OUT

C_OUT

R₁

2.2 mF

3.4 MW

DELAY

C_DELAY

0.1 mF

R₂

GND

1.07 MW

图8-2. Adjustable Operation

方程式1 can calculate R₁and R₂for any output voltage range:

V_OUT

R₁= R₂

- 1

V_REF

(1)

8.2.1.2.1.1 Resistor Selection

Use resistors in the order of MΩ to keep the overall quiescent current of the system as low as possible (by

making the current used by the resistor divider negligible compared to the quiescent current of the device).

If greater voltage accuracy is required, take into account the voltage offset contributions as a result of feedback

current and use 0.1% tolerance resistors.

表 8-2 shows the resistor combination to achieve an output for a few of the most common rails using

commercially available 0.1% tolerance resistors to maximize nominal voltage accuracy, while adhering to the

formula in 方程式1.

表8-2. Selected Resistor Combinations

V_OUT

1.194 V

1.8 V

2..5 V

3.3 V

5 V

R₁

R₂

V_OUT/ (R₁+ R₂) « I_Q

NOMINAL ACCURACY

±2%

0 Ω

0 μA

∞

514 nA

±(2% + 0.14%)

±(2% + 0.16%)

±(2% + 0.35%)

±(2% + 0.39%)

±(2% + 0.42%)

±(2% + 0.18%)

±(2% + 0.19%)

±(2% + 0.26%)

1.18 MΩ

1.5 MΩ

2 MΩ

2.32 MΩ

1.37 MΩ

1.13 MΩ

1.07 MΩ

1.58 MΩ

3.65 MΩ

1.15 MΩ

871 nA

1056 nA

1115 nA

755 nA

3.4 MΩ

7.87 MΩ

14.3 MΩ

42.2 MΩ

16.2 MΩ

10 V

12 V

15 V

327 nA

18 V

1038 nA

Close attention must be paid to board contamination when using high-value resistors; board contaminants can

significantly impact voltage accuracy. If board cleaning measures cannot be ensured, consider using a fixed-

voltage version of the TPS7A16A or using resistors in the order of hundreds or tens of kΩ.

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

8.2.1.2.2 Capacitor Recommendations

Use low equivalent-series-resistance (ESR) capacitors for the input, output, and feed-forward capacitors.

Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable

characteristics. Ceramic X7R capacitors offer improved overtemperature performance, but ceramic X5R

capacitors are the most cost-effective and are available in higher values.

However, high-ESR capacitors can degrade PSRR.

8.2.1.2.3 Input and Output Capacitor Requirements

The TPS7A16A ultra-low-power, high-voltage linear regulator achieves stability with a minimum input

capacitance of 0.1 µF and output capacitance of 2.2 µF; however, use a 10-µF ceramic capacitor to maximize ac

performance.

8.2.1.2.4 Feed-Forward Capacitor (Only for Adjustable Version)

Although a feed-forward capacitor (C_FF) from OUT to FB is not needed to achieve stability, using a 0.01-µF feed-

forward capacitor helps maximize ac performance.

8.2.1.2.5 Transient Response

As with any regulator, increasing the size of the output capacitor reduces over- and undershoot magnitude but

increases the duration of the transient response.

8.2.1.3 Application Curves

图8-3. Channel 1 is V_OUT, Channel 2 is PG,

Channel 4 is I_OUT, V_INis 12 V and Ready Before EN

图8-4. Channel1 is V_OUT, Channel 2 is PG, Channel

3 is EN, Channel 4 is I_OUT, and V_INis 12 V

Connected to EN

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

9 Power Supply Recommendations

The device is designed for operation from an input voltage supply with a range between 3 V and 60 V. This input

supply must be well regulated. The TPS7A16A ultra-low-power, high-voltage linear regulator achieves stability

with a minimum input capacitance of 0.1 µF and output capacitance of 2.2 µF; however, use a 10-µF ceramic

capacitor to maximize ac performance.

10 Layout

10.1 Layout Guidelines

To improve ac performance such as PSRR, output noise, and transient response, the board is recommended to

be designed with separate ground planes for IN and OUT, with each ground plane connected only at the GND

pin of the device. This grounding scheme is commonly referred to as star grounding. In addition, directly connect

the ground connection for the output capacitor to the GND pin of the device.

Equivalent series inductance (ESL) and ESR must be minimized in order to maximize performance and ensure

stability. Every capacitor must be placed as close as possible to the device and on the same side of the PCB as

the regulator itself.

Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use

of vias and long traces is strongly discouraged because they can impact system performance negatively and

even cause instability.

If possible, and to ensure the maximum performance denoted in this document, use the same layout pattern

used for the TPS7A16A evaluation board, available at www.ti.com.

Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing

currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade

the power-supply performance. To help eliminate these problems, bypass the IN pin to ground with a low-ESR

ceramic bypass capacitor with X5R or X7R dielectric.

Acceptable performance can be obtained with alternative PCB layouts; however, the layout and the schematic

have been shown to produce good results and are meant as a guideline.

图 10-1 illustrates the schematic for the suggested layout. 图 10-2 and 图 10-3 depict the top and bottom printed

circuit board (PCB) layers for the suggested layout, respectively.

10.1.1 Additional Layout Considerations

The high impedance of the FB pin makes the regulator sensitive to parasitic capacitances that can couple

undesirable signals from nearby components (especially from logic and digital devices, such as microcontrollers

and microprocessors). These capacitively-coupled signals can produce undesirable output voltage transients.

Thus, use a fixed-voltage version of the TPS7A16A, or isolate the FB node by flooding the local PCB area with

ground-plane copper to minimize any undesirable signal coupling.

10.1.2 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in

the PCB layout. The PCB area around the device that is free of other components moves the heat from the

device to the ambient air. Using heavier copper increases the effectiveness of removing heat from the device.

The addition of plated through-holes to heat dissipating layers also improves the heat sink effectiveness.

Power dissipation depends on input voltage and load conditions. As 方程式 2 shows, power dissipation (P_D) is

equal to the product of the output current times the voltage drop across the output pass transistor:

P_D= (V_IN- V_OUT) I_OUT

(2)

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

10.1.3 Thermal Considerations

Thermal protection disables the output when the junction temperature rises to approximately 170°C, allowing the

device to cool. When the junction temperature cools to approximately 150°C, the output circuitry is enabled.

Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit

may cycle on and off. This cycling limits the dissipation of the regulator, protecting the regulator from damage as

a result of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate

heat-spreading area. For reliable operation, limit junction temperature to a maximum of 125°C at the worst-case

ambient temperature for a given application. To estimate the margin of safety in a complete design (including the

copper heat-spreading area), increase the ambient temperature until the thermal protection is triggered; use

worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 45°C above the

maximum expected ambient condition of the particular application. This configuration produces a worst-case

junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TPS7A16A is designed to protect against overload conditions. This

circuitry is not intended to replace proper heat sinking. Continuously running the TPS7A16A into thermal

shutdown degrades device reliability.

10.2 Layout Examples

图10-1. Schematic for Suggested Layout

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

TPS7A16A

1300 mil

2200 mil

图10-2. Suggested Layout: Top Layer

1300 mil

2200 mil

图10-3. Suggested Layout: Bottom Layer

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

表11-1. Device Nomenclature1

PRODUCT

V_OUT, PACKAGE, QUANTITY

xx is the nominal output voltage. Two digits are used in the ordering number (for example, 33 = 3.3 V;

01 = adjustable).

yyy is the package designator.

TPS7A16xxAyyyz

z is the package quantity. R is for reel (2500 pieces for DGN).

1. For the most current package and ordering information see the Package Option Addendum at the end of this

document, or visit the device product folder at www.ti.com.

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

PowerPAD^™and TI E2E^™are trademarks of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

12.1 Mechanical Data

PACKAGE OUTLINE

PowerPAD^TMVSSOP - 1.1 mm max height

DGN0008A

SMALL OUTLINE PACKAGE

5.05

4.75

TYP

0.1 C

SEATING

PLANE

PIN 1 INDEX AREA

6X 0.65

3.1

2.9

1.95

NOTE 3

0.38

0.25

3.1

2.9

0.13

C A B

NOTE 4

0.23

0.13

SEE DETAIL A

EXPOSED THERMAL PAD

0.25

GAGE PLANE

2.0

1.7

1.1 MAX

0.15

0.05

0.7

0.4

0 -8

DETAIL A

TYPICAL

1.88

1.58

4218836/A 11/2019

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold ﬂash, protrusions, or gate burrs. Mold ﬂash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead ﬂash. Interlead ﬂash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187.

www.ti.com

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

EXAMPLE BOARD LAYOUT

PowerPAD^TMVSSOP - 1.1 mm max height

DGN0008A

SMALL OUTLINE PACKAGE

(2)

NOTE 9

METAL COVERED

BY SOLDER MASK

(1.88)

SOLDER MASK

DEFINED PAD

SYMM

8X (1.4)

(R0.05) TYP

8X (0.45)

(3)

NOTE 9

SYMM

(2)

(1.22)

6X (0.65)

(

0.2) TYP

VIA

SEE DETAILS

(0.55)

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

15.000

SOLDER MASK DETAILS

4218836/A 11/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be ﬁlled, plugged or tented.

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

Submit Document Feedback

Product Folder Links: TPS7A16A

TPS7A16A

ZHCSPP1 –MAY 2022

www.ti.com.cn

EXAMPLE STENCIL DESIGN

PowerPAD^TMVSSOP - 1.1 mm max height

DGN0008A

SMALL OUTLINE PACKAGE

(1.88)

BASED ON

0.125 THICK

STENCIL

SYMM

(R0.05) TYP

8X (1.4)

8X (0.45)

(2)

BASED ON

SYMM

0.125 THICK

STENCIL

6X (0.65)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

(4.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:

100% PRINTED SOLDER COVERAGE BY AREA

SCALE: 15X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.10 X 2.24

1.88 X 2.00 (SHOWN)

1.72 X 1.83

0.125

0.15

0.175

1.59 X 1.69

4218836/A 11/2019

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may oﬀer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have diﬀerent recommendations for stencil design.

www.ti.com

Submit Document Feedback

Product Folder Links: TPS7A16A

PACKAGE OPTION ADDENDUM

www.ti.com

10-Aug-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TPS7A1601ADGNR

ACTIVE

HVSSOP

DGN

2500 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 150

2RDT

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS7A16A :

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Aug-2022

Automotive : TPS7A16A-Q1

•

NOTE: Qualified Version Definitions:

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

•

Addendum-Page 2

GENERIC PACKAGE VIEW

DGN 8

3 x 3, 0.65 mm pitch

PowerPAD VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225482/A

www.ti.com

PACKAGE OUTLINE

DGN0008A

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

5.05

4.75

TYP

0.1 C

SEATING

PLANE

PIN 1 INDEX AREA

6X 0.65

3.1

2.9

1.95

NOTE 3

0.38

0.25

3.1

2.9

0.13

C A B

NOTE 4

0.23

0.13

SEE DETAIL A

EXPOSED THERMAL PAD

0.25

GAGE PLANE

2.0

1.7

1.1 MAX

0.15

0.05

0.7

0.4

0 -8

DETAIL A

TYPICAL

1.88

1.58

4218836/A 11/2019

PowerPAD is a trademark of Texas Instruments.

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187.

www.ti.com

EXAMPLE BOARD LAYOUT

DGN0008A

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

(2)

NOTE 9

METAL COVERED

BY SOLDER MASK

(1.88)

SOLDER MASK

DEFINED PAD

SYMM

8X (1.4)

(R0.05) TYP

8X (0.45)

(3)

NOTE 9

SYMM

(2)

(1.22)

6X (0.65)

(

0.2) TYP

VIA

SEE DETAILS

(0.55)

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4218836/A 11/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

DGN0008A

PowerPAD^TMVSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE

(1.88)

BASED ON

0.125 THICK

STENCIL

SYMM

(R0.05) TYP

8X (1.4)

8X (0.45)

(2)

BASED ON

SYMM

0.125 THICK

STENCIL

6X (0.65)

METAL COVERED

BY SOLDER MASK

SEE TABLE FOR

DIFFERENT OPENINGS

FOR OTHER STENCIL

THICKNESSES

(4.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:

100% PRINTED SOLDER COVERAGE BY AREA

SCALE: 15X

STENCIL

THICKNESS

SOLDER STENCIL

OPENING

0.1

2.10 X 2.24

1.88 X 2.00 (SHOWN)

1.72 X 1.83

0.125

0.15

0.175

1.59 X 1.69

4218836/A 11/2019

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

11. Board assembly site may have different recommendations for stencil design.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TPS7A1601ADGNR [TI]

相关型号：

TPS7A1601AQDGNRQ1

TPS7A1601DGN

TPS7A1601DGNR

TPS7A1601DGNT

TPS7A1601DRBR

TPS7A1601DRBT

TPS7A1601EVM-046

TPS7A1601QDGNRQ1

TPS7A1633-Q1

TPS7A1633AQDGNRQ1

TPS7A1633DGNR

TPS7A1633DGNT